drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/swap.h>
  35 #include <linux/pci.h>
  36
  37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  38
  39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  43                                              int write);
  44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  45                                                      uint64_t offset,
  46                                                      uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  50                                            unsigned alignment);
  51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
  53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
  54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file_priv);
  57
  58 static LIST_HEAD(shrink_list);
  59 static DEFINE_SPINLOCK(shrink_list_lock);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, start,
  73                     end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94 int
  95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  96                             struct drm_file *file_priv)
  97 {
  98         struct drm_i915_gem_get_aperture *args = data;
  99
 100         if (!(dev->driver->driver_features & DRIVER_GEM))
 101                 return -ENODEV;
 102
 103         args->aper_size = dev->gtt_total;
 104         args->aper_available_size = (args->aper_size -
 105                                      atomic_read(&dev->pin_memory));
 106
 107         return 0;
 108 }
 109
 110
 111 /**
 112  * Creates a new mm object and returns a handle to it.
 113  */
 114 int
 115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 116                       struct drm_file *file_priv)
 117 {
 118         struct drm_i915_gem_create *args = data;
 119         struct drm_gem_object *obj;
 120         int ret;
 121         u32 handle;
 122
 123         args->size = roundup(args->size, PAGE_SIZE);
 124
 125         /* Allocate the new object */
 126         obj = drm_gem_object_alloc(dev, args->size);
 127         if (obj == NULL)
 128                 return -ENOMEM;
 129
 130         ret = drm_gem_handle_create(file_priv, obj, &handle);
 131         mutex_lock(&dev->struct_mutex);
 132         drm_gem_object_handle_unreference(obj);
 133         mutex_unlock(&dev->struct_mutex);
 134
 135         if (ret)
 136                 return ret;
 137
 138         args->handle = handle;
 139
 140         return 0;
 141 }
 142
 143 static inline int
 144 fast_shmem_read(struct page **pages,
 145                 loff_t page_base, int page_offset,
 146                 char __user *data,
 147                 int length)
 148 {
 149         char __iomem *vaddr;
 150         int unwritten;
 151
 152         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 153         if (vaddr == NULL)
 154                 return -ENOMEM;
 155         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 156         kunmap_atomic(vaddr, KM_USER0);
 157
 158         if (unwritten)
 159                 return -EFAULT;
 160
 161         return 0;
 162 }
 163
 164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 165 {
 166         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 167         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 168
 169         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 170                 obj_priv->tiling_mode != I915_TILING_NONE;
 171 }
 172
 173 static inline int
 174 slow_shmem_copy(struct page *dst_page,
 175                 int dst_offset,
 176                 struct page *src_page,
 177                 int src_offset,
 178                 int length)
 179 {
 180         char *dst_vaddr, *src_vaddr;
 181
 182         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
 183         if (dst_vaddr == NULL)
 184                 return -ENOMEM;
 185
 186         src_vaddr = kmap_atomic(src_page, KM_USER1);
 187         if (src_vaddr == NULL) {
 188                 kunmap_atomic(dst_vaddr, KM_USER0);
 189                 return -ENOMEM;
 190         }
 191
 192         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 193
 194         kunmap_atomic(src_vaddr, KM_USER1);
 195         kunmap_atomic(dst_vaddr, KM_USER0);
 196
 197         return 0;
 198 }
 199
 200 static inline int
 201 slow_shmem_bit17_copy(struct page *gpu_page,
 202                       int gpu_offset,
 203                       struct page *cpu_page,
 204                       int cpu_offset,
 205                       int length,
 206                       int is_read)
 207 {
 208         char *gpu_vaddr, *cpu_vaddr;
 209
 210         /* Use the unswizzled path if this page isn't affected. */
 211         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 212                 if (is_read)
 213                         return slow_shmem_copy(cpu_page, cpu_offset,
 214                                                gpu_page, gpu_offset, length);
 215                 else
 216                         return slow_shmem_copy(gpu_page, gpu_offset,
 217                                                cpu_page, cpu_offset, length);
 218         }
 219
 220         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
 221         if (gpu_vaddr == NULL)
 222                 return -ENOMEM;
 223
 224         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
 225         if (cpu_vaddr == NULL) {
 226                 kunmap_atomic(gpu_vaddr, KM_USER0);
 227                 return -ENOMEM;
 228         }
 229
 230         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 231          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 232          */
 233         while (length > 0) {
 234                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 235                 int this_length = min(cacheline_end - gpu_offset, length);
 236                 int swizzled_gpu_offset = gpu_offset ^ 64;
 237
 238                 if (is_read) {
 239                         memcpy(cpu_vaddr + cpu_offset,
 240                                gpu_vaddr + swizzled_gpu_offset,
 241                                this_length);
 242                 } else {
 243                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 244                                cpu_vaddr + cpu_offset,
 245                                this_length);
 246                 }
 247                 cpu_offset += this_length;
 248                 gpu_offset += this_length;
 249                 length -= this_length;
 250         }
 251
 252         kunmap_atomic(cpu_vaddr, KM_USER1);
 253         kunmap_atomic(gpu_vaddr, KM_USER0);
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * This is the fast shmem pread path, which attempts to copy_from_user directly
 260  * from the backing pages of the object to the user's address space.  On a
 261  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 262  */
 263 static int
 264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 265                           struct drm_i915_gem_pread *args,
 266                           struct drm_file *file_priv)
 267 {
 268         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 269         ssize_t remain;
 270         loff_t offset, page_base;
 271         char __user *user_data;
 272         int page_offset, page_length;
 273         int ret;
 274
 275         user_data = (char __user *) (uintptr_t) args->data_ptr;
 276         remain = args->size;
 277
 278         mutex_lock(&dev->struct_mutex);
 279
 280         ret = i915_gem_object_get_pages(obj, 0);
 281         if (ret != 0)
 282                 goto fail_unlock;
 283
 284         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 285                                                         args->size);
 286         if (ret != 0)
 287                 goto fail_put_pages;
 288
 289         obj_priv = obj->driver_private;
 290         offset = args->offset;
 291
 292         while (remain > 0) {
 293                 /* Operation in this page
 294                  *
 295                  * page_base = page offset within aperture
 296                  * page_offset = offset within page
 297                  * page_length = bytes to copy for this page
 298                  */
 299                 page_base = (offset & ~(PAGE_SIZE-1));
 300                 page_offset = offset & (PAGE_SIZE-1);
 301                 page_length = remain;
 302                 if ((page_offset + remain) > PAGE_SIZE)
 303                         page_length = PAGE_SIZE - page_offset;
 304
 305                 ret = fast_shmem_read(obj_priv->pages,
 306                                       page_base, page_offset,
 307                                       user_data, page_length);
 308                 if (ret)
 309                         goto fail_put_pages;
 310
 311                 remain -= page_length;
 312                 user_data += page_length;
 313                 offset += page_length;
 314         }
 315
 316 fail_put_pages:
 317         i915_gem_object_put_pages(obj);
 318 fail_unlock:
 319         mutex_unlock(&dev->struct_mutex);
 320
 321         return ret;
 322 }
 323
 324 static int
 325 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 326 {
 327         int ret;
 328
 329         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 330
 331         /* If we've insufficient memory to map in the pages, attempt
 332          * to make some space by throwing out some old buffers.
 333          */
 334         if (ret == -ENOMEM) {
 335                 struct drm_device *dev = obj->dev;
 336
 337                 ret = i915_gem_evict_something(dev, obj->size);
 338                 if (ret)
 339                         return ret;
 340
 341                 ret = i915_gem_object_get_pages(obj, 0);
 342         }
 343
 344         return ret;
 345 }
 346
 347 /**
 348  * This is the fallback shmem pread path, which allocates temporary storage
 349  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 350  * can copy out of the object's backing pages while holding the struct mutex
 351  * and not take page faults.
 352  */
 353 static int
 354 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 355                           struct drm_i915_gem_pread *args,
 356                           struct drm_file *file_priv)
 357 {
 358         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 359         struct mm_struct *mm = current->mm;
 360         struct page **user_pages;
 361         ssize_t remain;
 362         loff_t offset, pinned_pages, i;
 363         loff_t first_data_page, last_data_page, num_pages;
 364         int shmem_page_index, shmem_page_offset;
 365         int data_page_index,  data_page_offset;
 366         int page_length;
 367         int ret;
 368         uint64_t data_ptr = args->data_ptr;
 369         int do_bit17_swizzling;
 370
 371         remain = args->size;
 372
 373         /* Pin the user pages containing the data.  We can't fault while
 374          * holding the struct mutex, yet we want to hold it while
 375          * dereferencing the user data.
 376          */
 377         first_data_page = data_ptr / PAGE_SIZE;
 378         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 379         num_pages = last_data_page - first_data_page + 1;
 380
 381         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 382         if (user_pages == NULL)
 383                 return -ENOMEM;
 384
 385         down_read(&mm->mmap_sem);
 386         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 387                                       num_pages, 1, 0, user_pages, NULL);
 388         up_read(&mm->mmap_sem);
 389         if (pinned_pages < num_pages) {
 390                 ret = -EFAULT;
 391                 goto fail_put_user_pages;
 392         }
 393
 394         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 395
 396         mutex_lock(&dev->struct_mutex);
 397
 398         ret = i915_gem_object_get_pages_or_evict(obj);
 399         if (ret)
 400                 goto fail_unlock;
 401
 402         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 403                                                         args->size);
 404         if (ret != 0)
 405                 goto fail_put_pages;
 406
 407         obj_priv = obj->driver_private;
 408         offset = args->offset;
 409
 410         while (remain > 0) {
 411                 /* Operation in this page
 412                  *
 413                  * shmem_page_index = page number within shmem file
 414                  * shmem_page_offset = offset within page in shmem file
 415                  * data_page_index = page number in get_user_pages return
 416                  * data_page_offset = offset with data_page_index page.
 417                  * page_length = bytes to copy for this page
 418                  */
 419                 shmem_page_index = offset / PAGE_SIZE;
 420                 shmem_page_offset = offset & ~PAGE_MASK;
 421                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 422                 data_page_offset = data_ptr & ~PAGE_MASK;
 423
 424                 page_length = remain;
 425                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 426                         page_length = PAGE_SIZE - shmem_page_offset;
 427                 if ((data_page_offset + page_length) > PAGE_SIZE)
 428                         page_length = PAGE_SIZE - data_page_offset;
 429
 430                 if (do_bit17_swizzling) {
 431                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 432                                                     shmem_page_offset,
 433                                                     user_pages[data_page_index],
 434                                                     data_page_offset,
 435                                                     page_length,
 436                                                     1);
 437                 } else {
 438                         ret = slow_shmem_copy(user_pages[data_page_index],
 439                                               data_page_offset,
 440                                               obj_priv->pages[shmem_page_index],
 441                                               shmem_page_offset,
 442                                               page_length);
 443                 }
 444                 if (ret)
 445                         goto fail_put_pages;
 446
 447                 remain -= page_length;
 448                 data_ptr += page_length;
 449                 offset += page_length;
 450         }
 451
 452 fail_put_pages:
 453         i915_gem_object_put_pages(obj);
 454 fail_unlock:
 455         mutex_unlock(&dev->struct_mutex);
 456 fail_put_user_pages:
 457         for (i = 0; i < pinned_pages; i++) {
 458                 SetPageDirty(user_pages[i]);
 459                 page_cache_release(user_pages[i]);
 460         }
 461         drm_free_large(user_pages);
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * Reads data from the object referenced by handle.
 468  *
 469  * On error, the contents of *data are undefined.
 470  */
 471 int
 472 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 473                      struct drm_file *file_priv)
 474 {
 475         struct drm_i915_gem_pread *args = data;
 476         struct drm_gem_object *obj;
 477         struct drm_i915_gem_object *obj_priv;
 478         int ret;
 479
 480         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 481         if (obj == NULL)
 482                 return -EBADF;
 483         obj_priv = obj->driver_private;
 484
 485         /* Bounds check source.
 486          *
 487          * XXX: This could use review for overflow issues...
 488          */
 489         if (args->offset > obj->size || args->size > obj->size ||
 490             args->offset + args->size > obj->size) {
 491                 drm_gem_object_unreference(obj);
 492                 return -EINVAL;
 493         }
 494
 495         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 496                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 497         } else {
 498                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 499                 if (ret != 0)
 500                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 501                                                         file_priv);
 502         }
 503
 504         drm_gem_object_unreference(obj);
 505
 506         return ret;
 507 }
 508
 509 /* This is the fast write path which cannot handle
 510  * page faults in the source data
 511  */
 512
 513 static inline int
 514 fast_user_write(struct io_mapping *mapping,
 515                 loff_t page_base, int page_offset,
 516                 char __user *user_data,
 517                 int length)
 518 {
 519         char *vaddr_atomic;
 520         unsigned long unwritten;
 521
 522         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 523         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 524                                                       user_data, length);
 525         io_mapping_unmap_atomic(vaddr_atomic);
 526         if (unwritten)
 527                 return -EFAULT;
 528         return 0;
 529 }
 530
 531 /* Here's the write path which can sleep for
 532  * page faults
 533  */
 534
 535 static inline int
 536 slow_kernel_write(struct io_mapping *mapping,
 537                   loff_t gtt_base, int gtt_offset,
 538                   struct page *user_page, int user_offset,
 539                   int length)
 540 {
 541         char *src_vaddr, *dst_vaddr;
 542         unsigned long unwritten;
 543
 544         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
 545         src_vaddr = kmap_atomic(user_page, KM_USER1);
 546         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
 547                                                       src_vaddr + user_offset,
 548                                                       length);
 549         kunmap_atomic(src_vaddr, KM_USER1);
 550         io_mapping_unmap_atomic(dst_vaddr);
 551         if (unwritten)
 552                 return -EFAULT;
 553         return 0;
 554 }
 555
 556 static inline int
 557 fast_shmem_write(struct page **pages,
 558                  loff_t page_base, int page_offset,
 559                  char __user *data,
 560                  int length)
 561 {
 562         char __iomem *vaddr;
 563         unsigned long unwritten;
 564
 565         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 566         if (vaddr == NULL)
 567                 return -ENOMEM;
 568         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 569         kunmap_atomic(vaddr, KM_USER0);
 570
 571         if (unwritten)
 572                 return -EFAULT;
 573         return 0;
 574 }
 575
 576 /**
 577  * This is the fast pwrite path, where we copy the data directly from the
 578  * user into the GTT, uncached.
 579  */
 580 static int
 581 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 582                          struct drm_i915_gem_pwrite *args,
 583                          struct drm_file *file_priv)
 584 {
 585         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 586         drm_i915_private_t *dev_priv = dev->dev_private;
 587         ssize_t remain;
 588         loff_t offset, page_base;
 589         char __user *user_data;
 590         int page_offset, page_length;
 591         int ret;
 592
 593         user_data = (char __user *) (uintptr_t) args->data_ptr;
 594         remain = args->size;
 595         if (!access_ok(VERIFY_READ, user_data, remain))
 596                 return -EFAULT;
 597
 598
 599         mutex_lock(&dev->struct_mutex);
 600         ret = i915_gem_object_pin(obj, 0);
 601         if (ret) {
 602                 mutex_unlock(&dev->struct_mutex);
 603                 return ret;
 604         }
 605         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 606         if (ret)
 607                 goto fail;
 608
 609         obj_priv = obj->driver_private;
 610         offset = obj_priv->gtt_offset + args->offset;
 611
 612         while (remain > 0) {
 613                 /* Operation in this page
 614                  *
 615                  * page_base = page offset within aperture
 616                  * page_offset = offset within page
 617                  * page_length = bytes to copy for this page
 618                  */
 619                 page_base = (offset & ~(PAGE_SIZE-1));
 620                 page_offset = offset & (PAGE_SIZE-1);
 621                 page_length = remain;
 622                 if ((page_offset + remain) > PAGE_SIZE)
 623                         page_length = PAGE_SIZE - page_offset;
 624
 625                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 626                                        page_offset, user_data, page_length);
 627
 628                 /* If we get a fault while copying data, then (presumably) our
 629                  * source page isn't available.  Return the error and we'll
 630                  * retry in the slow path.
 631                  */
 632                 if (ret)
 633                         goto fail;
 634
 635                 remain -= page_length;
 636                 user_data += page_length;
 637                 offset += page_length;
 638         }
 639
 640 fail:
 641         i915_gem_object_unpin(obj);
 642         mutex_unlock(&dev->struct_mutex);
 643
 644         return ret;
 645 }
 646
 647 /**
 648  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 649  * the memory and maps it using kmap_atomic for copying.
 650  *
 651  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 652  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 653  */
 654 static int
 655 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 656                          struct drm_i915_gem_pwrite *args,
 657                          struct drm_file *file_priv)
 658 {
 659         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 660         drm_i915_private_t *dev_priv = dev->dev_private;
 661         ssize_t remain;
 662         loff_t gtt_page_base, offset;
 663         loff_t first_data_page, last_data_page, num_pages;
 664         loff_t pinned_pages, i;
 665         struct page **user_pages;
 666         struct mm_struct *mm = current->mm;
 667         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 668         int ret;
 669         uint64_t data_ptr = args->data_ptr;
 670
 671         remain = args->size;
 672
 673         /* Pin the user pages containing the data.  We can't fault while
 674          * holding the struct mutex, and all of the pwrite implementations
 675          * want to hold it while dereferencing the user data.
 676          */
 677         first_data_page = data_ptr / PAGE_SIZE;
 678         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 679         num_pages = last_data_page - first_data_page + 1;
 680
 681         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 682         if (user_pages == NULL)
 683                 return -ENOMEM;
 684
 685         down_read(&mm->mmap_sem);
 686         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 687                                       num_pages, 0, 0, user_pages, NULL);
 688         up_read(&mm->mmap_sem);
 689         if (pinned_pages < num_pages) {
 690                 ret = -EFAULT;
 691                 goto out_unpin_pages;
 692         }
 693
 694         mutex_lock(&dev->struct_mutex);
 695         ret = i915_gem_object_pin(obj, 0);
 696         if (ret)
 697                 goto out_unlock;
 698
 699         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 700         if (ret)
 701                 goto out_unpin_object;
 702
 703         obj_priv = obj->driver_private;
 704         offset = obj_priv->gtt_offset + args->offset;
 705
 706         while (remain > 0) {
 707                 /* Operation in this page
 708                  *
 709                  * gtt_page_base = page offset within aperture
 710                  * gtt_page_offset = offset within page in aperture
 711                  * data_page_index = page number in get_user_pages return
 712                  * data_page_offset = offset with data_page_index page.
 713                  * page_length = bytes to copy for this page
 714                  */
 715                 gtt_page_base = offset & PAGE_MASK;
 716                 gtt_page_offset = offset & ~PAGE_MASK;
 717                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 718                 data_page_offset = data_ptr & ~PAGE_MASK;
 719
 720                 page_length = remain;
 721                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 722                         page_length = PAGE_SIZE - gtt_page_offset;
 723                 if ((data_page_offset + page_length) > PAGE_SIZE)
 724                         page_length = PAGE_SIZE - data_page_offset;
 725
 726                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
 727                                         gtt_page_base, gtt_page_offset,
 728                                         user_pages[data_page_index],
 729                                         data_page_offset,
 730                                         page_length);
 731
 732                 /* If we get a fault while copying data, then (presumably) our
 733                  * source page isn't available.  Return the error and we'll
 734                  * retry in the slow path.
 735                  */
 736                 if (ret)
 737                         goto out_unpin_object;
 738
 739                 remain -= page_length;
 740                 offset += page_length;
 741                 data_ptr += page_length;
 742         }
 743
 744 out_unpin_object:
 745         i915_gem_object_unpin(obj);
 746 out_unlock:
 747         mutex_unlock(&dev->struct_mutex);
 748 out_unpin_pages:
 749         for (i = 0; i < pinned_pages; i++)
 750                 page_cache_release(user_pages[i]);
 751         drm_free_large(user_pages);
 752
 753         return ret;
 754 }
 755
 756 /**
 757  * This is the fast shmem pwrite path, which attempts to directly
 758  * copy_from_user into the kmapped pages backing the object.
 759  */
 760 static int
 761 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 762                            struct drm_i915_gem_pwrite *args,
 763                            struct drm_file *file_priv)
 764 {
 765         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 766         ssize_t remain;
 767         loff_t offset, page_base;
 768         char __user *user_data;
 769         int page_offset, page_length;
 770         int ret;
 771
 772         user_data = (char __user *) (uintptr_t) args->data_ptr;
 773         remain = args->size;
 774
 775         mutex_lock(&dev->struct_mutex);
 776
 777         ret = i915_gem_object_get_pages(obj, 0);
 778         if (ret != 0)
 779                 goto fail_unlock;
 780
 781         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 782         if (ret != 0)
 783                 goto fail_put_pages;
 784
 785         obj_priv = obj->driver_private;
 786         offset = args->offset;
 787         obj_priv->dirty = 1;
 788
 789         while (remain > 0) {
 790                 /* Operation in this page
 791                  *
 792                  * page_base = page offset within aperture
 793                  * page_offset = offset within page
 794                  * page_length = bytes to copy for this page
 795                  */
 796                 page_base = (offset & ~(PAGE_SIZE-1));
 797                 page_offset = offset & (PAGE_SIZE-1);
 798                 page_length = remain;
 799                 if ((page_offset + remain) > PAGE_SIZE)
 800                         page_length = PAGE_SIZE - page_offset;
 801
 802                 ret = fast_shmem_write(obj_priv->pages,
 803                                        page_base, page_offset,
 804                                        user_data, page_length);
 805                 if (ret)
 806                         goto fail_put_pages;
 807
 808                 remain -= page_length;
 809                 user_data += page_length;
 810                 offset += page_length;
 811         }
 812
 813 fail_put_pages:
 814         i915_gem_object_put_pages(obj);
 815 fail_unlock:
 816         mutex_unlock(&dev->struct_mutex);
 817
 818         return ret;
 819 }
 820
 821 /**
 822  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 823  * the memory and maps it using kmap_atomic for copying.
 824  *
 825  * This avoids taking mmap_sem for faulting on the user's address while the
 826  * struct_mutex is held.
 827  */
 828 static int
 829 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 830                            struct drm_i915_gem_pwrite *args,
 831                            struct drm_file *file_priv)
 832 {
 833         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 834         struct mm_struct *mm = current->mm;
 835         struct page **user_pages;
 836         ssize_t remain;
 837         loff_t offset, pinned_pages, i;
 838         loff_t first_data_page, last_data_page, num_pages;
 839         int shmem_page_index, shmem_page_offset;
 840         int data_page_index,  data_page_offset;
 841         int page_length;
 842         int ret;
 843         uint64_t data_ptr = args->data_ptr;
 844         int do_bit17_swizzling;
 845
 846         remain = args->size;
 847
 848         /* Pin the user pages containing the data.  We can't fault while
 849          * holding the struct mutex, and all of the pwrite implementations
 850          * want to hold it while dereferencing the user data.
 851          */
 852         first_data_page = data_ptr / PAGE_SIZE;
 853         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 854         num_pages = last_data_page - first_data_page + 1;
 855
 856         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 857         if (user_pages == NULL)
 858                 return -ENOMEM;
 859
 860         down_read(&mm->mmap_sem);
 861         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 862                                       num_pages, 0, 0, user_pages, NULL);
 863         up_read(&mm->mmap_sem);
 864         if (pinned_pages < num_pages) {
 865                 ret = -EFAULT;
 866                 goto fail_put_user_pages;
 867         }
 868
 869         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 870
 871         mutex_lock(&dev->struct_mutex);
 872
 873         ret = i915_gem_object_get_pages_or_evict(obj);
 874         if (ret)
 875                 goto fail_unlock;
 876
 877         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 878         if (ret != 0)
 879                 goto fail_put_pages;
 880
 881         obj_priv = obj->driver_private;
 882         offset = args->offset;
 883         obj_priv->dirty = 1;
 884
 885         while (remain > 0) {
 886                 /* Operation in this page
 887                  *
 888                  * shmem_page_index = page number within shmem file
 889                  * shmem_page_offset = offset within page in shmem file
 890                  * data_page_index = page number in get_user_pages return
 891                  * data_page_offset = offset with data_page_index page.
 892                  * page_length = bytes to copy for this page
 893                  */
 894                 shmem_page_index = offset / PAGE_SIZE;
 895                 shmem_page_offset = offset & ~PAGE_MASK;
 896                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 897                 data_page_offset = data_ptr & ~PAGE_MASK;
 898
 899                 page_length = remain;
 900                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 901                         page_length = PAGE_SIZE - shmem_page_offset;
 902                 if ((data_page_offset + page_length) > PAGE_SIZE)
 903                         page_length = PAGE_SIZE - data_page_offset;
 904
 905                 if (do_bit17_swizzling) {
 906                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 907                                                     shmem_page_offset,
 908                                                     user_pages[data_page_index],
 909                                                     data_page_offset,
 910                                                     page_length,
 911                                                     0);
 912                 } else {
 913                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
 914                                               shmem_page_offset,
 915                                               user_pages[data_page_index],
 916                                               data_page_offset,
 917                                               page_length);
 918                 }
 919                 if (ret)
 920                         goto fail_put_pages;
 921
 922                 remain -= page_length;
 923                 data_ptr += page_length;
 924                 offset += page_length;
 925         }
 926
 927 fail_put_pages:
 928         i915_gem_object_put_pages(obj);
 929 fail_unlock:
 930         mutex_unlock(&dev->struct_mutex);
 931 fail_put_user_pages:
 932         for (i = 0; i < pinned_pages; i++)
 933                 page_cache_release(user_pages[i]);
 934         drm_free_large(user_pages);
 935
 936         return ret;
 937 }
 938
 939 /**
 940  * Writes data to the object referenced by handle.
 941  *
 942  * On error, the contents of the buffer that were to be modified are undefined.
 943  */
 944 int
 945 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 946                       struct drm_file *file_priv)
 947 {
 948         struct drm_i915_gem_pwrite *args = data;
 949         struct drm_gem_object *obj;
 950         struct drm_i915_gem_object *obj_priv;
 951         int ret = 0;
 952
 953         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 954         if (obj == NULL)
 955                 return -EBADF;
 956         obj_priv = obj->driver_private;
 957
 958         /* Bounds check destination.
 959          *
 960          * XXX: This could use review for overflow issues...
 961          */
 962         if (args->offset > obj->size || args->size > obj->size ||
 963             args->offset + args->size > obj->size) {
 964                 drm_gem_object_unreference(obj);
 965                 return -EINVAL;
 966         }
 967
 968         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 969          * it would end up going through the fenced access, and we'll get
 970          * different detiling behavior between reading and writing.
 971          * pread/pwrite currently are reading and writing from the CPU
 972          * perspective, requiring manual detiling by the client.
 973          */
 974         if (obj_priv->phys_obj)
 975                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 976         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 977                  dev->gtt_total != 0) {
 978                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 979                 if (ret == -EFAULT) {
 980                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 981                                                        file_priv);
 982                 }
 983         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 984                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 985         } else {
 986                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 987                 if (ret == -EFAULT) {
 988                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 989                                                          file_priv);
 990                 }
 991         }
 992
 993 #if WATCH_PWRITE
 994         if (ret)
 995                 DRM_INFO("pwrite failed %d\n", ret);
 996 #endif
 997
 998         drm_gem_object_unreference(obj);
 999
1000         return ret;
1001 }
1002
1003 /**
1004  * Called when user space prepares to use an object with the CPU, either
1005  * through the mmap ioctl's mapping or a GTT mapping.
1006  */
1007 int
1008 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009                           struct drm_file *file_priv)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         struct drm_i915_gem_set_domain *args = data;
1013         struct drm_gem_object *obj;
1014         struct drm_i915_gem_object *obj_priv;
1015         uint32_t read_domains = args->read_domains;
1016         uint32_t write_domain = args->write_domain;
1017         int ret;
1018
1019         if (!(dev->driver->driver_features & DRIVER_GEM))
1020                 return -ENODEV;
1021
1022         /* Only handle setting domains to types used by the CPU. */
1023         if (write_domain & I915_GEM_GPU_DOMAINS)
1024                 return -EINVAL;
1025
1026         if (read_domains & I915_GEM_GPU_DOMAINS)
1027                 return -EINVAL;
1028
1029         /* Having something in the write domain implies it's in the read
1030          * domain, and only that read domain.  Enforce that in the request.
1031          */
1032         if (write_domain != 0 && read_domains != write_domain)
1033                 return -EINVAL;
1034
1035         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036         if (obj == NULL)
1037                 return -EBADF;
1038         obj_priv = obj->driver_private;
1039
1040         mutex_lock(&dev->struct_mutex);
1041
1042         intel_mark_busy(dev, obj);
1043
1044 #if WATCH_BUF
1045         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046                  obj, obj->size, read_domains, write_domain);
1047 #endif
1048         if (read_domains & I915_GEM_DOMAIN_GTT) {
1049                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1050
1051                 /* Update the LRU on the fence for the CPU access that's
1052                  * about to occur.
1053                  */
1054                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055                         list_move_tail(&obj_priv->fence_list,
1056                                        &dev_priv->mm.fence_list);
1057                 }
1058
1059                 /* Silently promote "you're not bound, there was nothing to do"
1060                  * to success, since the client was just asking us to
1061                  * make sure everything was done.
1062                  */
1063                 if (ret == -EINVAL)
1064                         ret = 0;
1065         } else {
1066                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1067         }
1068
1069         drm_gem_object_unreference(obj);
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 /**
1075  * Called when user space has done writes to this buffer
1076  */
1077 int
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079                       struct drm_file *file_priv)
1080 {
1081         struct drm_i915_gem_sw_finish *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         int ret = 0;
1085
1086         if (!(dev->driver->driver_features & DRIVER_GEM))
1087                 return -ENODEV;
1088
1089         mutex_lock(&dev->struct_mutex);
1090         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091         if (obj == NULL) {
1092                 mutex_unlock(&dev->struct_mutex);
1093                 return -EBADF;
1094         }
1095
1096 #if WATCH_BUF
1097         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098                  __func__, args->handle, obj, obj->size);
1099 #endif
1100         obj_priv = obj->driver_private;
1101
1102         /* Pinned buffers may be scanout, so flush the cache */
1103         if (obj_priv->pin_count)
1104                 i915_gem_object_flush_cpu_write_domain(obj);
1105
1106         drm_gem_object_unreference(obj);
1107         mutex_unlock(&dev->struct_mutex);
1108         return ret;
1109 }
1110
1111 /**
1112  * Maps the contents of an object, returning the address it is mapped
1113  * into.
1114  *
1115  * While the mapping holds a reference on the contents of the object, it doesn't
1116  * imply a ref on the object itself.
1117  */
1118 int
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120                    struct drm_file *file_priv)
1121 {
1122         struct drm_i915_gem_mmap *args = data;
1123         struct drm_gem_object *obj;
1124         loff_t offset;
1125         unsigned long addr;
1126
1127         if (!(dev->driver->driver_features & DRIVER_GEM))
1128                 return -ENODEV;
1129
1130         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131         if (obj == NULL)
1132                 return -EBADF;
1133
1134         offset = args->offset;
1135
1136         down_write(&current->mm->mmap_sem);
1137         addr = do_mmap(obj->filp, 0, args->size,
1138                        PROT_READ | PROT_WRITE, MAP_SHARED,
1139                        args->offset);
1140         up_write(&current->mm->mmap_sem);
1141         mutex_lock(&dev->struct_mutex);
1142         drm_gem_object_unreference(obj);
1143         mutex_unlock(&dev->struct_mutex);
1144         if (IS_ERR((void *)addr))
1145                 return addr;
1146
1147         args->addr_ptr = (uint64_t) addr;
1148
1149         return 0;
1150 }
1151
1152 /**
1153  * i915_gem_fault - fault a page into the GTT
1154  * vma: VMA in question
1155  * vmf: fault info
1156  *
1157  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158  * from userspace.  The fault handler takes care of binding the object to
1159  * the GTT (if needed), allocating and programming a fence register (again,
1160  * only if needed based on whether the old reg is still valid or the object
1161  * is tiled) and inserting a new PTE into the faulting process.
1162  *
1163  * Note that the faulting process may involve evicting existing objects
1164  * from the GTT and/or fence registers to make room.  So performance may
1165  * suffer if the GTT working set is large or there are few fence registers
1166  * left.
1167  */
1168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169 {
1170         struct drm_gem_object *obj = vma->vm_private_data;
1171         struct drm_device *dev = obj->dev;
1172         struct drm_i915_private *dev_priv = dev->dev_private;
1173         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174         pgoff_t page_offset;
1175         unsigned long pfn;
1176         int ret = 0;
1177         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1178
1179         /* We don't use vmf->pgoff since that has the fake offset */
1180         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181                 PAGE_SHIFT;
1182
1183         /* Now bind it into the GTT if needed */
1184         mutex_lock(&dev->struct_mutex);
1185         if (!obj_priv->gtt_space) {
1186                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187                 if (ret)
1188                         goto unlock;
1189
1190                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1191
1192                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193                 if (ret)
1194                         goto unlock;
1195         }
1196
1197         /* Need a new fence register? */
1198         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1199                 ret = i915_gem_object_get_fence_reg(obj);
1200                 if (ret)
1201                         goto unlock;
1202         }
1203
1204         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205                 page_offset;
1206
1207         /* Finally, remap it using the new GTT offset */
1208         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1209 unlock:
1210         mutex_unlock(&dev->struct_mutex);
1211
1212         switch (ret) {
1213         case 0:
1214         case -ERESTARTSYS:
1215                 return VM_FAULT_NOPAGE;
1216         case -ENOMEM:
1217         case -EAGAIN:
1218                 return VM_FAULT_OOM;
1219         default:
1220                 return VM_FAULT_SIGBUS;
1221         }
1222 }
1223
1224 /**
1225  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226  * @obj: obj in question
1227  *
1228  * GEM memory mapping works by handing back to userspace a fake mmap offset
1229  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1230  * up the object based on the offset and sets up the various memory mapping
1231  * structures.
1232  *
1233  * This routine allocates and attaches a fake offset for @obj.
1234  */
1235 static int
1236 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1237 {
1238         struct drm_device *dev = obj->dev;
1239         struct drm_gem_mm *mm = dev->mm_private;
1240         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241         struct drm_map_list *list;
1242         struct drm_local_map *map;
1243         int ret = 0;
1244
1245         /* Set the object up for mmap'ing */
1246         list = &obj->map_list;
1247         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248         if (!list->map)
1249                 return -ENOMEM;
1250
1251         map = list->map;
1252         map->type = _DRM_GEM;
1253         map->size = obj->size;
1254         map->handle = obj;
1255
1256         /* Get a DRM GEM mmap offset allocated... */
1257         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258                                                     obj->size / PAGE_SIZE, 0, 0);
1259         if (!list->file_offset_node) {
1260                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261                 ret = -ENOMEM;
1262                 goto out_free_list;
1263         }
1264
1265         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266                                                   obj->size / PAGE_SIZE, 0);
1267         if (!list->file_offset_node) {
1268                 ret = -ENOMEM;
1269                 goto out_free_list;
1270         }
1271
1272         list->hash.key = list->file_offset_node->start;
1273         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274                 DRM_ERROR("failed to add to map hash\n");
1275                 ret = -ENOMEM;
1276                 goto out_free_mm;
1277         }
1278
1279         /* By now we should be all set, any drm_mmap request on the offset
1280          * below will get to our mmap & fault handler */
1281         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282
1283         return 0;
1284
1285 out_free_mm:
1286         drm_mm_put_block(list->file_offset_node);
1287 out_free_list:
1288         kfree(list->map);
1289
1290         return ret;
1291 }
1292
1293 /**
1294  * i915_gem_release_mmap - remove physical page mappings
1295  * @obj: obj in question
1296  *
1297  * Preserve the reservation of the mmapping with the DRM core code, but
1298  * relinquish ownership of the pages back to the system.
1299  *
1300  * It is vital that we remove the page mapping if we have mapped a tiled
1301  * object through the GTT and then lose the fence register due to
1302  * resource pressure. Similarly if the object has been moved out of the
1303  * aperture, than pages mapped into userspace must be revoked. Removing the
1304  * mapping will then trigger a page fault on the next user access, allowing
1305  * fixup by i915_gem_fault().
1306  */
1307 void
1308 i915_gem_release_mmap(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1312
1313         if (dev->dev_mapping)
1314                 unmap_mapping_range(dev->dev_mapping,
1315                                     obj_priv->mmap_offset, obj->size, 1);
1316 }
1317
1318 static void
1319 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1320 {
1321         struct drm_device *dev = obj->dev;
1322         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323         struct drm_gem_mm *mm = dev->mm_private;
1324         struct drm_map_list *list;
1325
1326         list = &obj->map_list;
1327         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1328
1329         if (list->file_offset_node) {
1330                 drm_mm_put_block(list->file_offset_node);
1331                 list->file_offset_node = NULL;
1332         }
1333
1334         if (list->map) {
1335                 kfree(list->map);
1336                 list->map = NULL;
1337         }
1338
1339         obj_priv->mmap_offset = 0;
1340 }
1341
1342 /**
1343  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344  * @obj: object to check
1345  *
1346  * Return the required GTT alignment for an object, taking into account
1347  * potential fence register mapping if needed.
1348  */
1349 static uint32_t
1350 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1351 {
1352         struct drm_device *dev = obj->dev;
1353         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354         int start, i;
1355
1356         /*
1357          * Minimum alignment is 4k (GTT page size), but might be greater
1358          * if a fence register is needed for the object.
1359          */
1360         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361                 return 4096;
1362
1363         /*
1364          * Previous chips need to be aligned to the size of the smallest
1365          * fence register that can contain the object.
1366          */
1367         if (IS_I9XX(dev))
1368                 start = 1024*1024;
1369         else
1370                 start = 512*1024;
1371
1372         for (i = start; i < obj->size; i <<= 1)
1373                 ;
1374
1375         return i;
1376 }
1377
1378 /**
1379  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380  * @dev: DRM device
1381  * @data: GTT mapping ioctl data
1382  * @file_priv: GEM object info
1383  *
1384  * Simply returns the fake offset to userspace so it can mmap it.
1385  * The mmap call will end up in drm_gem_mmap(), which will set things
1386  * up so we can get faults in the handler above.
1387  *
1388  * The fault handler will take care of binding the object into the GTT
1389  * (since it may have been evicted to make room for something), allocating
1390  * a fence register, and mapping the appropriate aperture address into
1391  * userspace.
1392  */
1393 int
1394 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395                         struct drm_file *file_priv)
1396 {
1397         struct drm_i915_gem_mmap_gtt *args = data;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         struct drm_gem_object *obj;
1400         struct drm_i915_gem_object *obj_priv;
1401         int ret;
1402
1403         if (!(dev->driver->driver_features & DRIVER_GEM))
1404                 return -ENODEV;
1405
1406         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407         if (obj == NULL)
1408                 return -EBADF;
1409
1410         mutex_lock(&dev->struct_mutex);
1411
1412         obj_priv = obj->driver_private;
1413
1414         if (obj_priv->madv != I915_MADV_WILLNEED) {
1415                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416                 drm_gem_object_unreference(obj);
1417                 mutex_unlock(&dev->struct_mutex);
1418                 return -EINVAL;
1419         }
1420
1421
1422         if (!obj_priv->mmap_offset) {
1423                 ret = i915_gem_create_mmap_offset(obj);
1424                 if (ret) {
1425                         drm_gem_object_unreference(obj);
1426                         mutex_unlock(&dev->struct_mutex);
1427                         return ret;
1428                 }
1429         }
1430
1431         args->offset = obj_priv->mmap_offset;
1432
1433         /*
1434          * Pull it into the GTT so that we have a page list (makes the
1435          * initial fault faster and any subsequent flushing possible).
1436          */
1437         if (!obj_priv->agp_mem) {
1438                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1439                 if (ret) {
1440                         drm_gem_object_unreference(obj);
1441                         mutex_unlock(&dev->struct_mutex);
1442                         return ret;
1443                 }
1444                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1445         }
1446
1447         drm_gem_object_unreference(obj);
1448         mutex_unlock(&dev->struct_mutex);
1449
1450         return 0;
1451 }
1452
1453 void
1454 i915_gem_object_put_pages(struct drm_gem_object *obj)
1455 {
1456         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457         int page_count = obj->size / PAGE_SIZE;
1458         int i;
1459
1460         BUG_ON(obj_priv->pages_refcount == 0);
1461         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1462
1463         if (--obj_priv->pages_refcount != 0)
1464                 return;
1465
1466         if (obj_priv->tiling_mode != I915_TILING_NONE)
1467                 i915_gem_object_save_bit_17_swizzle(obj);
1468
1469         if (obj_priv->madv == I915_MADV_DONTNEED)
1470                 obj_priv->dirty = 0;
1471
1472         for (i = 0; i < page_count; i++) {
1473                 if (obj_priv->dirty)
1474                         set_page_dirty(obj_priv->pages[i]);
1475
1476                 if (obj_priv->madv == I915_MADV_WILLNEED)
1477                         mark_page_accessed(obj_priv->pages[i]);
1478
1479                 page_cache_release(obj_priv->pages[i]);
1480         }
1481         obj_priv->dirty = 0;
1482
1483         drm_free_large(obj_priv->pages);
1484         obj_priv->pages = NULL;
1485 }
1486
1487 static void
1488 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1489 {
1490         struct drm_device *dev = obj->dev;
1491         drm_i915_private_t *dev_priv = dev->dev_private;
1492         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1493
1494         /* Add a reference if we're newly entering the active list. */
1495         if (!obj_priv->active) {
1496                 drm_gem_object_reference(obj);
1497                 obj_priv->active = 1;
1498         }
1499         /* Move from whatever list we were on to the tail of execution. */
1500         spin_lock(&dev_priv->mm.active_list_lock);
1501         list_move_tail(&obj_priv->list,
1502                        &dev_priv->mm.active_list);
1503         spin_unlock(&dev_priv->mm.active_list_lock);
1504         obj_priv->last_rendering_seqno = seqno;
1505 }
1506
1507 static void
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 {
1510         struct drm_device *dev = obj->dev;
1511         drm_i915_private_t *dev_priv = dev->dev_private;
1512         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1513
1514         BUG_ON(!obj_priv->active);
1515         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516         obj_priv->last_rendering_seqno = 0;
1517 }
1518
1519 /* Immediately discard the backing storage */
1520 static void
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 {
1523         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1524         struct inode *inode;
1525
1526         inode = obj->filp->f_path.dentry->d_inode;
1527         if (inode->i_op->truncate)
1528                 inode->i_op->truncate (inode);
1529
1530         obj_priv->madv = __I915_MADV_PURGED;
1531 }
1532
1533 static inline int
1534 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1535 {
1536         return obj_priv->madv == I915_MADV_DONTNEED;
1537 }
1538
1539 static void
1540 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1541 {
1542         struct drm_device *dev = obj->dev;
1543         drm_i915_private_t *dev_priv = dev->dev_private;
1544         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1545
1546         i915_verify_inactive(dev, __FILE__, __LINE__);
1547         if (obj_priv->pin_count != 0)
1548                 list_del_init(&obj_priv->list);
1549         else
1550                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1551
1552         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1553
1554         obj_priv->last_rendering_seqno = 0;
1555         if (obj_priv->active) {
1556                 obj_priv->active = 0;
1557                 drm_gem_object_unreference(obj);
1558         }
1559         i915_verify_inactive(dev, __FILE__, __LINE__);
1560 }
1561
1562 #define PIPE_CONTROL_FLUSH(addr)                                        \
1563         OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |          \
1564                  PIPE_CONTROL_DEPTH_STALL);                             \
1565         OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT);                       \
1566         OUT_RING(0);                                                    \
1567         OUT_RING(0);                                                    \
1568
1569 /**
1570  * Creates a new sequence number, emitting a write of it to the status page
1571  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1572  *
1573  * Must be called with struct_lock held.
1574  *
1575  * Returned sequence numbers are nonzero on success.
1576  */
1577 uint32_t
1578 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1579                  uint32_t flush_domains)
1580 {
1581         drm_i915_private_t *dev_priv = dev->dev_private;
1582         struct drm_i915_file_private *i915_file_priv = NULL;
1583         struct drm_i915_gem_request *request;
1584         uint32_t seqno;
1585         int was_empty;
1586         RING_LOCALS;
1587
1588         if (file_priv != NULL)
1589                 i915_file_priv = file_priv->driver_priv;
1590
1591         request = kzalloc(sizeof(*request), GFP_KERNEL);
1592         if (request == NULL)
1593                 return 0;
1594
1595         /* Grab the seqno we're going to make this request be, and bump the
1596          * next (skipping 0 so it can be the reserved no-seqno value).
1597          */
1598         seqno = dev_priv->mm.next_gem_seqno;
1599         dev_priv->mm.next_gem_seqno++;
1600         if (dev_priv->mm.next_gem_seqno == 0)
1601                 dev_priv->mm.next_gem_seqno++;
1602
1603         if (HAS_PIPE_CONTROL(dev)) {
1604                 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
1605
1606                 /*
1607                  * Workaround qword write incoherence by flushing the
1608                  * PIPE_NOTIFY buffers out to memory before requesting
1609                  * an interrupt.
1610                  */
1611                 BEGIN_LP_RING(32);
1612                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1613                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
1614                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1615                 OUT_RING(seqno);
1616                 OUT_RING(0);
1617                 PIPE_CONTROL_FLUSH(scratch_addr);
1618                 scratch_addr += 128; /* write to separate cachelines */
1619                 PIPE_CONTROL_FLUSH(scratch_addr);
1620                 scratch_addr += 128;
1621                 PIPE_CONTROL_FLUSH(scratch_addr);
1622                 scratch_addr += 128;
1623                 PIPE_CONTROL_FLUSH(scratch_addr);
1624                 scratch_addr += 128;
1625                 PIPE_CONTROL_FLUSH(scratch_addr);
1626                 scratch_addr += 128;
1627                 PIPE_CONTROL_FLUSH(scratch_addr);
1628                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1629                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
1630                          PIPE_CONTROL_NOTIFY);
1631                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1632                 OUT_RING(seqno);
1633                 OUT_RING(0);
1634                 ADVANCE_LP_RING();
1635         } else {
1636                 BEGIN_LP_RING(4);
1637                 OUT_RING(MI_STORE_DWORD_INDEX);
1638                 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1639                 OUT_RING(seqno);
1640
1641                 OUT_RING(MI_USER_INTERRUPT);
1642                 ADVANCE_LP_RING();
1643         }
1644
1645         DRM_DEBUG_DRIVER("%d\n", seqno);
1646
1647         request->seqno = seqno;
1648         request->emitted_jiffies = jiffies;
1649         was_empty = list_empty(&dev_priv->mm.request_list);
1650         list_add_tail(&request->list, &dev_priv->mm.request_list);
1651         if (i915_file_priv) {
1652                 list_add_tail(&request->client_list,
1653                               &i915_file_priv->mm.request_list);
1654         } else {
1655                 INIT_LIST_HEAD(&request->client_list);
1656         }
1657
1658         /* Associate any objects on the flushing list matching the write
1659          * domain we're flushing with our flush.
1660          */
1661         if (flush_domains != 0) {
1662                 struct drm_i915_gem_object *obj_priv, *next;
1663
1664                 list_for_each_entry_safe(obj_priv, next,
1665                                          &dev_priv->mm.gpu_write_list,
1666                                          gpu_write_list) {
1667                         struct drm_gem_object *obj = obj_priv->obj;
1668
1669                         if ((obj->write_domain & flush_domains) ==
1670                             obj->write_domain) {
1671                                 uint32_t old_write_domain = obj->write_domain;
1672
1673                                 obj->write_domain = 0;
1674                                 list_del_init(&obj_priv->gpu_write_list);
1675                                 i915_gem_object_move_to_active(obj, seqno);
1676
1677                                 trace_i915_gem_object_change_domain(obj,
1678                                                                     obj->read_domains,
1679                                                                     old_write_domain);
1680                         }
1681                 }
1682
1683         }
1684
1685         if (!dev_priv->mm.suspended) {
1686                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1687                 if (was_empty)
1688                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1689         }
1690         return seqno;
1691 }
1692
1693 /**
1694  * Command execution barrier
1695  *
1696  * Ensures that all commands in the ring are finished
1697  * before signalling the CPU
1698  */
1699 static uint32_t
1700 i915_retire_commands(struct drm_device *dev)
1701 {
1702         drm_i915_private_t *dev_priv = dev->dev_private;
1703         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1704         uint32_t flush_domains = 0;
1705         RING_LOCALS;
1706
1707         /* The sampler always gets flushed on i965 (sigh) */
1708         if (IS_I965G(dev))
1709                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1710         BEGIN_LP_RING(2);
1711         OUT_RING(cmd);
1712         OUT_RING(0); /* noop */
1713         ADVANCE_LP_RING();
1714         return flush_domains;
1715 }
1716
1717 /**
1718  * Moves buffers associated only with the given active seqno from the active
1719  * to inactive list, potentially freeing them.
1720  */
1721 static void
1722 i915_gem_retire_request(struct drm_device *dev,
1723                         struct drm_i915_gem_request *request)
1724 {
1725         drm_i915_private_t *dev_priv = dev->dev_private;
1726
1727         trace_i915_gem_request_retire(dev, request->seqno);
1728
1729         /* Move any buffers on the active list that are no longer referenced
1730          * by the ringbuffer to the flushing/inactive lists as appropriate.
1731          */
1732         spin_lock(&dev_priv->mm.active_list_lock);
1733         while (!list_empty(&dev_priv->mm.active_list)) {
1734                 struct drm_gem_object *obj;
1735                 struct drm_i915_gem_object *obj_priv;
1736
1737                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1738                                             struct drm_i915_gem_object,
1739                                             list);
1740                 obj = obj_priv->obj;
1741
1742                 /* If the seqno being retired doesn't match the oldest in the
1743                  * list, then the oldest in the list must still be newer than
1744                  * this seqno.
1745                  */
1746                 if (obj_priv->last_rendering_seqno != request->seqno)
1747                         goto out;
1748
1749 #if WATCH_LRU
1750                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1751                          __func__, request->seqno, obj);
1752 #endif
1753
1754                 if (obj->write_domain != 0)
1755                         i915_gem_object_move_to_flushing(obj);
1756                 else {
1757                         /* Take a reference on the object so it won't be
1758                          * freed while the spinlock is held.  The list
1759                          * protection for this spinlock is safe when breaking
1760                          * the lock like this since the next thing we do
1761                          * is just get the head of the list again.
1762                          */
1763                         drm_gem_object_reference(obj);
1764                         i915_gem_object_move_to_inactive(obj);
1765                         spin_unlock(&dev_priv->mm.active_list_lock);
1766                         drm_gem_object_unreference(obj);
1767                         spin_lock(&dev_priv->mm.active_list_lock);
1768                 }
1769         }
1770 out:
1771         spin_unlock(&dev_priv->mm.active_list_lock);
1772 }
1773
1774 /**
1775  * Returns true if seq1 is later than seq2.
1776  */
1777 bool
1778 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1779 {
1780         return (int32_t)(seq1 - seq2) >= 0;
1781 }
1782
1783 uint32_t
1784 i915_get_gem_seqno(struct drm_device *dev)
1785 {
1786         drm_i915_private_t *dev_priv = dev->dev_private;
1787
1788         if (HAS_PIPE_CONTROL(dev))
1789                 return ((volatile u32 *)(dev_priv->seqno_page))[0];
1790         else
1791                 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1792 }
1793
1794 /**
1795  * This function clears the request list as sequence numbers are passed.
1796  */
1797 void
1798 i915_gem_retire_requests(struct drm_device *dev)
1799 {
1800         drm_i915_private_t *dev_priv = dev->dev_private;
1801         uint32_t seqno;
1802
1803         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1804                 return;
1805
1806         seqno = i915_get_gem_seqno(dev);
1807
1808         while (!list_empty(&dev_priv->mm.request_list)) {
1809                 struct drm_i915_gem_request *request;
1810                 uint32_t retiring_seqno;
1811
1812                 request = list_first_entry(&dev_priv->mm.request_list,
1813                                            struct drm_i915_gem_request,
1814                                            list);
1815                 retiring_seqno = request->seqno;
1816
1817                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1818                     atomic_read(&dev_priv->mm.wedged)) {
1819                         i915_gem_retire_request(dev, request);
1820
1821                         list_del(&request->list);
1822                         list_del(&request->client_list);
1823                         kfree(request);
1824                 } else
1825                         break;
1826         }
1827
1828         if (unlikely (dev_priv->trace_irq_seqno &&
1829                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1830                 i915_user_irq_put(dev);
1831                 dev_priv->trace_irq_seqno = 0;
1832         }
1833 }
1834
1835 void
1836 i915_gem_retire_work_handler(struct work_struct *work)
1837 {
1838         drm_i915_private_t *dev_priv;
1839         struct drm_device *dev;
1840
1841         dev_priv = container_of(work, drm_i915_private_t,
1842                                 mm.retire_work.work);
1843         dev = dev_priv->dev;
1844
1845         mutex_lock(&dev->struct_mutex);
1846         i915_gem_retire_requests(dev);
1847         if (!dev_priv->mm.suspended &&
1848             !list_empty(&dev_priv->mm.request_list))
1849                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1850         mutex_unlock(&dev->struct_mutex);
1851 }
1852
1853 int
1854 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1855 {
1856         drm_i915_private_t *dev_priv = dev->dev_private;
1857         u32 ier;
1858         int ret = 0;
1859
1860         BUG_ON(seqno == 0);
1861
1862         if (atomic_read(&dev_priv->mm.wedged))
1863                 return -EIO;
1864
1865         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1866                 if (HAS_PCH_SPLIT(dev))
1867                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1868                 else
1869                         ier = I915_READ(IER);
1870                 if (!ier) {
1871                         DRM_ERROR("something (likely vbetool) disabled "
1872                                   "interrupts, re-enabling\n");
1873                         i915_driver_irq_preinstall(dev);
1874                         i915_driver_irq_postinstall(dev);
1875                 }
1876
1877                 trace_i915_gem_request_wait_begin(dev, seqno);
1878
1879                 dev_priv->mm.waiting_gem_seqno = seqno;
1880                 i915_user_irq_get(dev);
1881                 if (interruptible)
1882                         ret = wait_event_interruptible(dev_priv->irq_queue,
1883                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1884                                 atomic_read(&dev_priv->mm.wedged));
1885                 else
1886                         wait_event(dev_priv->irq_queue,
1887                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1888                                 atomic_read(&dev_priv->mm.wedged));
1889
1890                 i915_user_irq_put(dev);
1891                 dev_priv->mm.waiting_gem_seqno = 0;
1892
1893                 trace_i915_gem_request_wait_end(dev, seqno);
1894         }
1895         if (atomic_read(&dev_priv->mm.wedged))
1896                 ret = -EIO;
1897
1898         if (ret && ret != -ERESTARTSYS)
1899                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1900                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1901
1902         /* Directly dispatch request retiring.  While we have the work queue
1903          * to handle this, the waiter on a request often wants an associated
1904          * buffer to have made it to the inactive list, and we would need
1905          * a separate wait queue to handle that.
1906          */
1907         if (ret == 0)
1908                 i915_gem_retire_requests(dev);
1909
1910         return ret;
1911 }
1912
1913 /**
1914  * Waits for a sequence number to be signaled, and cleans up the
1915  * request and object lists appropriately for that event.
1916  */
1917 static int
1918 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1919 {
1920         return i915_do_wait_request(dev, seqno, 1);
1921 }
1922
1923 static void
1924 i915_gem_flush(struct drm_device *dev,
1925                uint32_t invalidate_domains,
1926                uint32_t flush_domains)
1927 {
1928         drm_i915_private_t *dev_priv = dev->dev_private;
1929         uint32_t cmd;
1930         RING_LOCALS;
1931
1932 #if WATCH_EXEC
1933         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1934                   invalidate_domains, flush_domains);
1935 #endif
1936         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1937                                      invalidate_domains, flush_domains);
1938
1939         if (flush_domains & I915_GEM_DOMAIN_CPU)
1940                 drm_agp_chipset_flush(dev);
1941
1942         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1943                 /*
1944                  * read/write caches:
1945                  *
1946                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1947                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1948                  * also flushed at 2d versus 3d pipeline switches.
1949                  *
1950                  * read-only caches:
1951                  *
1952                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1953                  * MI_READ_FLUSH is set, and is always flushed on 965.
1954                  *
1955                  * I915_GEM_DOMAIN_COMMAND may not exist?
1956                  *
1957                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1958                  * invalidated when MI_EXE_FLUSH is set.
1959                  *
1960                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1961                  * invalidated with every MI_FLUSH.
1962                  *
1963                  * TLBs:
1964                  *
1965                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1966                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1967                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1968                  * are flushed at any MI_FLUSH.
1969                  */
1970
1971                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1972                 if ((invalidate_domains|flush_domains) &
1973                     I915_GEM_DOMAIN_RENDER)
1974                         cmd &= ~MI_NO_WRITE_FLUSH;
1975                 if (!IS_I965G(dev)) {
1976                         /*
1977                          * On the 965, the sampler cache always gets flushed
1978                          * and this bit is reserved.
1979                          */
1980                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1981                                 cmd |= MI_READ_FLUSH;
1982                 }
1983                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1984                         cmd |= MI_EXE_FLUSH;
1985
1986 #if WATCH_EXEC
1987                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1988 #endif
1989                 BEGIN_LP_RING(2);
1990                 OUT_RING(cmd);
1991                 OUT_RING(MI_NOOP);
1992                 ADVANCE_LP_RING();
1993         }
1994 }
1995
1996 /**
1997  * Ensures that all rendering to the object has completed and the object is
1998  * safe to unbind from the GTT or access from the CPU.
1999  */
2000 static int
2001 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
2002 {
2003         struct drm_device *dev = obj->dev;
2004         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2005         int ret;
2006
2007         /* This function only exists to support waiting for existing rendering,
2008          * not for emitting required flushes.
2009          */
2010         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2011
2012         /* If there is rendering queued on the buffer being evicted, wait for
2013          * it.
2014          */
2015         if (obj_priv->active) {
2016 #if WATCH_BUF
2017                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2018                           __func__, obj, obj_priv->last_rendering_seqno);
2019 #endif
2020                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
2021                 if (ret != 0)
2022                         return ret;
2023         }
2024
2025         return 0;
2026 }
2027
2028 /**
2029  * Unbinds an object from the GTT aperture.
2030  */
2031 int
2032 i915_gem_object_unbind(struct drm_gem_object *obj)
2033 {
2034         struct drm_device *dev = obj->dev;
2035         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2036         int ret = 0;
2037
2038 #if WATCH_BUF
2039         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2040         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2041 #endif
2042         if (obj_priv->gtt_space == NULL)
2043                 return 0;
2044
2045         if (obj_priv->pin_count != 0) {
2046                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2047                 return -EINVAL;
2048         }
2049
2050         /* blow away mappings if mapped through GTT */
2051         i915_gem_release_mmap(obj);
2052
2053         /* Move the object to the CPU domain to ensure that
2054          * any possible CPU writes while it's not in the GTT
2055          * are flushed when we go to remap it. This will
2056          * also ensure that all pending GPU writes are finished
2057          * before we unbind.
2058          */
2059         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2060         if (ret) {
2061                 if (ret != -ERESTARTSYS)
2062                         DRM_ERROR("set_domain failed: %d\n", ret);
2063                 return ret;
2064         }
2065
2066         BUG_ON(obj_priv->active);
2067
2068         /* release the fence reg _after_ flushing */
2069         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2070                 i915_gem_clear_fence_reg(obj);
2071
2072         if (obj_priv->agp_mem != NULL) {
2073                 drm_unbind_agp(obj_priv->agp_mem);
2074                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2075                 obj_priv->agp_mem = NULL;
2076         }
2077
2078         i915_gem_object_put_pages(obj);
2079         BUG_ON(obj_priv->pages_refcount);
2080
2081         if (obj_priv->gtt_space) {
2082                 atomic_dec(&dev->gtt_count);
2083                 atomic_sub(obj->size, &dev->gtt_memory);
2084
2085                 drm_mm_put_block(obj_priv->gtt_space);
2086                 obj_priv->gtt_space = NULL;
2087         }
2088
2089         /* Remove ourselves from the LRU list if present. */
2090         if (!list_empty(&obj_priv->list))
2091                 list_del_init(&obj_priv->list);
2092
2093         if (i915_gem_object_is_purgeable(obj_priv))
2094                 i915_gem_object_truncate(obj);
2095
2096         trace_i915_gem_object_unbind(obj);
2097
2098         return 0;
2099 }
2100
2101 static struct drm_gem_object *
2102 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2103 {
2104         drm_i915_private_t *dev_priv = dev->dev_private;
2105         struct drm_i915_gem_object *obj_priv;
2106         struct drm_gem_object *best = NULL;
2107         struct drm_gem_object *first = NULL;
2108
2109         /* Try to find the smallest clean object */
2110         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2111                 struct drm_gem_object *obj = obj_priv->obj;
2112                 if (obj->size >= min_size) {
2113                         if ((!obj_priv->dirty ||
2114                              i915_gem_object_is_purgeable(obj_priv)) &&
2115                             (!best || obj->size < best->size)) {
2116                                 best = obj;
2117                                 if (best->size == min_size)
2118                                         return best;
2119                         }
2120                         if (!first)
2121                             first = obj;
2122                 }
2123         }
2124
2125         return best ? best : first;
2126 }
2127
2128 static int
2129 i915_gem_evict_everything(struct drm_device *dev)
2130 {
2131         drm_i915_private_t *dev_priv = dev->dev_private;
2132         int ret;
2133         uint32_t seqno;
2134         bool lists_empty;
2135
2136         spin_lock(&dev_priv->mm.active_list_lock);
2137         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2138                        list_empty(&dev_priv->mm.flushing_list) &&
2139                        list_empty(&dev_priv->mm.active_list));
2140         spin_unlock(&dev_priv->mm.active_list_lock);
2141
2142         if (lists_empty)
2143                 return -ENOSPC;
2144
2145         /* Flush everything (on to the inactive lists) and evict */
2146         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2147         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2148         if (seqno == 0)
2149                 return -ENOMEM;
2150
2151         ret = i915_wait_request(dev, seqno);
2152         if (ret)
2153                 return ret;
2154
2155         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2156
2157         ret = i915_gem_evict_from_inactive_list(dev);
2158         if (ret)
2159                 return ret;
2160
2161         spin_lock(&dev_priv->mm.active_list_lock);
2162         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2163                        list_empty(&dev_priv->mm.flushing_list) &&
2164                        list_empty(&dev_priv->mm.active_list));
2165         spin_unlock(&dev_priv->mm.active_list_lock);
2166         BUG_ON(!lists_empty);
2167
2168         return 0;
2169 }
2170
2171 static int
2172 i915_gem_evict_something(struct drm_device *dev, int min_size)
2173 {
2174         drm_i915_private_t *dev_priv = dev->dev_private;
2175         struct drm_gem_object *obj;
2176         int ret;
2177
2178         for (;;) {
2179                 i915_gem_retire_requests(dev);
2180
2181                 /* If there's an inactive buffer available now, grab it
2182                  * and be done.
2183                  */
2184                 obj = i915_gem_find_inactive_object(dev, min_size);
2185                 if (obj) {
2186                         struct drm_i915_gem_object *obj_priv;
2187
2188 #if WATCH_LRU
2189                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2190 #endif
2191                         obj_priv = obj->driver_private;
2192                         BUG_ON(obj_priv->pin_count != 0);
2193                         BUG_ON(obj_priv->active);
2194
2195                         /* Wait on the rendering and unbind the buffer. */
2196                         return i915_gem_object_unbind(obj);
2197                 }
2198
2199                 /* If we didn't get anything, but the ring is still processing
2200                  * things, wait for the next to finish and hopefully leave us
2201                  * a buffer to evict.
2202                  */
2203                 if (!list_empty(&dev_priv->mm.request_list)) {
2204                         struct drm_i915_gem_request *request;
2205
2206                         request = list_first_entry(&dev_priv->mm.request_list,
2207                                                    struct drm_i915_gem_request,
2208                                                    list);
2209
2210                         ret = i915_wait_request(dev, request->seqno);
2211                         if (ret)
2212                                 return ret;
2213
2214                         continue;
2215                 }
2216
2217                 /* If we didn't have anything on the request list but there
2218                  * are buffers awaiting a flush, emit one and try again.
2219                  * When we wait on it, those buffers waiting for that flush
2220                  * will get moved to inactive.
2221                  */
2222                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2223                         struct drm_i915_gem_object *obj_priv;
2224
2225                         /* Find an object that we can immediately reuse */
2226                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2227                                 obj = obj_priv->obj;
2228                                 if (obj->size >= min_size)
2229                                         break;
2230
2231                                 obj = NULL;
2232                         }
2233
2234                         if (obj != NULL) {
2235                                 uint32_t seqno;
2236
2237                                 i915_gem_flush(dev,
2238                                                obj->write_domain,
2239                                                obj->write_domain);
2240                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2241                                 if (seqno == 0)
2242                                         return -ENOMEM;
2243
2244                                 ret = i915_wait_request(dev, seqno);
2245                                 if (ret)
2246                                         return ret;
2247
2248                                 continue;
2249                         }
2250                 }
2251
2252                 /* If we didn't do any of the above, there's no single buffer
2253                  * large enough to swap out for the new one, so just evict
2254                  * everything and start again. (This should be rare.)
2255                  */
2256                 if (!list_empty (&dev_priv->mm.inactive_list))
2257                         return i915_gem_evict_from_inactive_list(dev);
2258                 else
2259                         return i915_gem_evict_everything(dev);
2260         }
2261 }
2262
2263 int
2264 i915_gem_object_get_pages(struct drm_gem_object *obj,
2265                           gfp_t gfpmask)
2266 {
2267         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2268         int page_count, i;
2269         struct address_space *mapping;
2270         struct inode *inode;
2271         struct page *page;
2272
2273         if (obj_priv->pages_refcount++ != 0)
2274                 return 0;
2275
2276         /* Get the list of pages out of our struct file.  They'll be pinned
2277          * at this point until we release them.
2278          */
2279         page_count = obj->size / PAGE_SIZE;
2280         BUG_ON(obj_priv->pages != NULL);
2281         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2282         if (obj_priv->pages == NULL) {
2283                 obj_priv->pages_refcount--;
2284                 return -ENOMEM;
2285         }
2286
2287         inode = obj->filp->f_path.dentry->d_inode;
2288         mapping = inode->i_mapping;
2289         for (i = 0; i < page_count; i++) {
2290                 page = read_cache_page_gfp(mapping, i,
2291                                            GFP_HIGHUSER |
2292                                            __GFP_COLD |
2293                                            gfpmask);
2294                 if (IS_ERR(page))
2295                         goto err_pages;
2296
2297                 obj_priv->pages[i] = page;
2298         }
2299
2300         if (obj_priv->tiling_mode != I915_TILING_NONE)
2301                 i915_gem_object_do_bit_17_swizzle(obj);
2302
2303         return 0;
2304
2305 err_pages:
2306         while (i--)
2307                 page_cache_release(obj_priv->pages[i]);
2308
2309         drm_free_large(obj_priv->pages);
2310         obj_priv->pages = NULL;
2311         obj_priv->pages_refcount--;
2312         return PTR_ERR(page);
2313 }
2314
2315 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2316 {
2317         struct drm_gem_object *obj = reg->obj;
2318         struct drm_device *dev = obj->dev;
2319         drm_i915_private_t *dev_priv = dev->dev_private;
2320         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2321         int regnum = obj_priv->fence_reg;
2322         uint64_t val;
2323
2324         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2325                     0xfffff000) << 32;
2326         val |= obj_priv->gtt_offset & 0xfffff000;
2327         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2328         if (obj_priv->tiling_mode == I915_TILING_Y)
2329                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2330         val |= I965_FENCE_REG_VALID;
2331
2332         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2333 }
2334
2335 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2336 {
2337         struct drm_gem_object *obj = reg->obj;
2338         struct drm_device *dev = obj->dev;
2339         drm_i915_private_t *dev_priv = dev->dev_private;
2340         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2341         int regnum = obj_priv->fence_reg;
2342         int tile_width;
2343         uint32_t fence_reg, val;
2344         uint32_t pitch_val;
2345
2346         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2347             (obj_priv->gtt_offset & (obj->size - 1))) {
2348                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2349                      __func__, obj_priv->gtt_offset, obj->size);
2350                 return;
2351         }
2352
2353         if (obj_priv->tiling_mode == I915_TILING_Y &&
2354             HAS_128_BYTE_Y_TILING(dev))
2355                 tile_width = 128;
2356         else
2357                 tile_width = 512;
2358
2359         /* Note: pitch better be a power of two tile widths */
2360         pitch_val = obj_priv->stride / tile_width;
2361         pitch_val = ffs(pitch_val) - 1;
2362
2363         if (obj_priv->tiling_mode == I915_TILING_Y &&
2364             HAS_128_BYTE_Y_TILING(dev))
2365                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2366         else
2367                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2368
2369         val = obj_priv->gtt_offset;
2370         if (obj_priv->tiling_mode == I915_TILING_Y)
2371                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2372         val |= I915_FENCE_SIZE_BITS(obj->size);
2373         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2374         val |= I830_FENCE_REG_VALID;
2375
2376         if (regnum < 8)
2377                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2378         else
2379                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2380         I915_WRITE(fence_reg, val);
2381 }
2382
2383 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2384 {
2385         struct drm_gem_object *obj = reg->obj;
2386         struct drm_device *dev = obj->dev;
2387         drm_i915_private_t *dev_priv = dev->dev_private;
2388         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2389         int regnum = obj_priv->fence_reg;
2390         uint32_t val;
2391         uint32_t pitch_val;
2392         uint32_t fence_size_bits;
2393
2394         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2395             (obj_priv->gtt_offset & (obj->size - 1))) {
2396                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2397                      __func__, obj_priv->gtt_offset);
2398                 return;
2399         }
2400
2401         pitch_val = obj_priv->stride / 128;
2402         pitch_val = ffs(pitch_val) - 1;
2403         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2404
2405         val = obj_priv->gtt_offset;
2406         if (obj_priv->tiling_mode == I915_TILING_Y)
2407                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2408         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2409         WARN_ON(fence_size_bits & ~0x00000f00);
2410         val |= fence_size_bits;
2411         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2412         val |= I830_FENCE_REG_VALID;
2413
2414         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2415 }
2416
2417 /**
2418  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2419  * @obj: object to map through a fence reg
2420  *
2421  * When mapping objects through the GTT, userspace wants to be able to write
2422  * to them without having to worry about swizzling if the object is tiled.
2423  *
2424  * This function walks the fence regs looking for a free one for @obj,
2425  * stealing one if it can't find any.
2426  *
2427  * It then sets up the reg based on the object's properties: address, pitch
2428  * and tiling format.
2429  */
2430 int
2431 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2432 {
2433         struct drm_device *dev = obj->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2436         struct drm_i915_fence_reg *reg = NULL;
2437         struct drm_i915_gem_object *old_obj_priv = NULL;
2438         int i, ret, avail;
2439
2440         /* Just update our place in the LRU if our fence is getting used. */
2441         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2442                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2443                 return 0;
2444         }
2445
2446         switch (obj_priv->tiling_mode) {
2447         case I915_TILING_NONE:
2448                 WARN(1, "allocating a fence for non-tiled object?\n");
2449                 break;
2450         case I915_TILING_X:
2451                 if (!obj_priv->stride)
2452                         return -EINVAL;
2453                 WARN((obj_priv->stride & (512 - 1)),
2454                      "object 0x%08x is X tiled but has non-512B pitch\n",
2455                      obj_priv->gtt_offset);
2456                 break;
2457         case I915_TILING_Y:
2458                 if (!obj_priv->stride)
2459                         return -EINVAL;
2460                 WARN((obj_priv->stride & (128 - 1)),
2461                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2462                      obj_priv->gtt_offset);
2463                 break;
2464         }
2465
2466         /* First try to find a free reg */
2467         avail = 0;
2468         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2469                 reg = &dev_priv->fence_regs[i];
2470                 if (!reg->obj)
2471                         break;
2472
2473                 old_obj_priv = reg->obj->driver_private;
2474                 if (!old_obj_priv->pin_count)
2475                     avail++;
2476         }
2477
2478         /* None available, try to steal one or wait for a user to finish */
2479         if (i == dev_priv->num_fence_regs) {
2480                 struct drm_gem_object *old_obj = NULL;
2481
2482                 if (avail == 0)
2483                         return -ENOSPC;
2484
2485                 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2486                                     fence_list) {
2487                         old_obj = old_obj_priv->obj;
2488
2489                         if (old_obj_priv->pin_count)
2490                                 continue;
2491
2492                         /* Take a reference, as otherwise the wait_rendering
2493                          * below may cause the object to get freed out from
2494                          * under us.
2495                          */
2496                         drm_gem_object_reference(old_obj);
2497
2498                         /* i915 uses fences for GPU access to tiled buffers */
2499                         if (IS_I965G(dev) || !old_obj_priv->active)
2500                                 break;
2501
2502                         /* This brings the object to the head of the LRU if it
2503                          * had been written to.  The only way this should
2504                          * result in us waiting longer than the expected
2505                          * optimal amount of time is if there was a
2506                          * fence-using buffer later that was read-only.
2507                          */
2508                         i915_gem_object_flush_gpu_write_domain(old_obj);
2509                         ret = i915_gem_object_wait_rendering(old_obj);
2510                         if (ret != 0) {
2511                                 drm_gem_object_unreference(old_obj);
2512                                 return ret;
2513                         }
2514
2515                         break;
2516                 }
2517
2518                 /*
2519                  * Zap this virtual mapping so we can set up a fence again
2520                  * for this object next time we need it.
2521                  */
2522                 i915_gem_release_mmap(old_obj);
2523
2524                 i = old_obj_priv->fence_reg;
2525                 reg = &dev_priv->fence_regs[i];
2526
2527                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2528                 list_del_init(&old_obj_priv->fence_list);
2529
2530                 drm_gem_object_unreference(old_obj);
2531         }
2532
2533         obj_priv->fence_reg = i;
2534         list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2535
2536         reg->obj = obj;
2537
2538         if (IS_I965G(dev))
2539                 i965_write_fence_reg(reg);
2540         else if (IS_I9XX(dev))
2541                 i915_write_fence_reg(reg);
2542         else
2543                 i830_write_fence_reg(reg);
2544
2545         trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2546
2547         return 0;
2548 }
2549
2550 /**
2551  * i915_gem_clear_fence_reg - clear out fence register info
2552  * @obj: object to clear
2553  *
2554  * Zeroes out the fence register itself and clears out the associated
2555  * data structures in dev_priv and obj_priv.
2556  */
2557 static void
2558 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2559 {
2560         struct drm_device *dev = obj->dev;
2561         drm_i915_private_t *dev_priv = dev->dev_private;
2562         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2563
2564         if (IS_I965G(dev))
2565                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2566         else {
2567                 uint32_t fence_reg;
2568
2569                 if (obj_priv->fence_reg < 8)
2570                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2571                 else
2572                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2573                                                        8) * 4;
2574
2575                 I915_WRITE(fence_reg, 0);
2576         }
2577
2578         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2579         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2580         list_del_init(&obj_priv->fence_list);
2581 }
2582
2583 /**
2584  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2585  * to the buffer to finish, and then resets the fence register.
2586  * @obj: tiled object holding a fence register.
2587  *
2588  * Zeroes out the fence register itself and clears out the associated
2589  * data structures in dev_priv and obj_priv.
2590  */
2591 int
2592 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2593 {
2594         struct drm_device *dev = obj->dev;
2595         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2596
2597         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2598                 return 0;
2599
2600         /* On the i915, GPU access to tiled buffers is via a fence,
2601          * therefore we must wait for any outstanding access to complete
2602          * before clearing the fence.
2603          */
2604         if (!IS_I965G(dev)) {
2605                 int ret;
2606
2607                 i915_gem_object_flush_gpu_write_domain(obj);
2608                 i915_gem_object_flush_gtt_write_domain(obj);
2609                 ret = i915_gem_object_wait_rendering(obj);
2610                 if (ret != 0)
2611                         return ret;
2612         }
2613
2614         i915_gem_clear_fence_reg (obj);
2615
2616         return 0;
2617 }
2618
2619 /**
2620  * Finds free space in the GTT aperture and binds the object there.
2621  */
2622 static int
2623 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2624 {
2625         struct drm_device *dev = obj->dev;
2626         drm_i915_private_t *dev_priv = dev->dev_private;
2627         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2628         struct drm_mm_node *free_space;
2629         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2630         int ret;
2631
2632         if (obj_priv->madv != I915_MADV_WILLNEED) {
2633                 DRM_ERROR("Attempting to bind a purgeable object\n");
2634                 return -EINVAL;
2635         }
2636
2637         if (alignment == 0)
2638                 alignment = i915_gem_get_gtt_alignment(obj);
2639         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2640                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2641                 return -EINVAL;
2642         }
2643
2644         /* If the object is bigger than the entire aperture, reject it early
2645          * before evicting everything in a vain attempt to find space.
2646          */
2647         if (obj->size > dev->gtt_total) {
2648                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2649                 return -E2BIG;
2650         }
2651
2652  search_free:
2653         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2654                                         obj->size, alignment, 0);
2655         if (free_space != NULL) {
2656                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2657                                                        alignment);
2658                 if (obj_priv->gtt_space != NULL) {
2659                         obj_priv->gtt_space->private = obj;
2660                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2661                 }
2662         }
2663         if (obj_priv->gtt_space == NULL) {
2664                 /* If the gtt is empty and we're still having trouble
2665                  * fitting our object in, we're out of memory.
2666                  */
2667 #if WATCH_LRU
2668                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2669 #endif
2670                 ret = i915_gem_evict_something(dev, obj->size);
2671                 if (ret)
2672                         return ret;
2673
2674                 goto search_free;
2675         }
2676
2677 #if WATCH_BUF
2678         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2679                  obj->size, obj_priv->gtt_offset);
2680 #endif
2681         ret = i915_gem_object_get_pages(obj, gfpmask);
2682         if (ret) {
2683                 drm_mm_put_block(obj_priv->gtt_space);
2684                 obj_priv->gtt_space = NULL;
2685
2686                 if (ret == -ENOMEM) {
2687                         /* first try to clear up some space from the GTT */
2688                         ret = i915_gem_evict_something(dev, obj->size);
2689                         if (ret) {
2690                                 /* now try to shrink everyone else */
2691                                 if (gfpmask) {
2692                                         gfpmask = 0;
2693                                         goto search_free;
2694                                 }
2695
2696                                 return ret;
2697                         }
2698
2699                         goto search_free;
2700                 }
2701
2702                 return ret;
2703         }
2704
2705         /* Create an AGP memory structure pointing at our pages, and bind it
2706          * into the GTT.
2707          */
2708         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2709                                                obj_priv->pages,
2710                                                obj->size >> PAGE_SHIFT,
2711                                                obj_priv->gtt_offset,
2712                                                obj_priv->agp_type);
2713         if (obj_priv->agp_mem == NULL) {
2714                 i915_gem_object_put_pages(obj);
2715                 drm_mm_put_block(obj_priv->gtt_space);
2716                 obj_priv->gtt_space = NULL;
2717
2718                 ret = i915_gem_evict_something(dev, obj->size);
2719                 if (ret)
2720                         return ret;
2721
2722                 goto search_free;
2723         }
2724         atomic_inc(&dev->gtt_count);
2725         atomic_add(obj->size, &dev->gtt_memory);
2726
2727         /* Assert that the object is not currently in any GPU domain. As it
2728          * wasn't in the GTT, there shouldn't be any way it could have been in
2729          * a GPU cache
2730          */
2731         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2732         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2733
2734         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2735
2736         return 0;
2737 }
2738
2739 void
2740 i915_gem_clflush_object(struct drm_gem_object *obj)
2741 {
2742         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2743
2744         /* If we don't have a page list set up, then we're not pinned
2745          * to GPU, and we can ignore the cache flush because it'll happen
2746          * again at bind time.
2747          */
2748         if (obj_priv->pages == NULL)
2749                 return;
2750
2751         trace_i915_gem_object_clflush(obj);
2752
2753         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2754 }
2755
2756 /** Flushes any GPU write domain for the object if it's dirty. */
2757 static void
2758 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2759 {
2760         struct drm_device *dev = obj->dev;
2761         uint32_t seqno;
2762         uint32_t old_write_domain;
2763
2764         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2765                 return;
2766
2767         /* Queue the GPU write cache flushing we need. */
2768         old_write_domain = obj->write_domain;
2769         i915_gem_flush(dev, 0, obj->write_domain);
2770         seqno = i915_add_request(dev, NULL, obj->write_domain);
2771         BUG_ON(obj->write_domain);
2772         i915_gem_object_move_to_active(obj, seqno);
2773
2774         trace_i915_gem_object_change_domain(obj,
2775                                             obj->read_domains,
2776                                             old_write_domain);
2777 }
2778
2779 /** Flushes the GTT write domain for the object if it's dirty. */
2780 static void
2781 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2782 {
2783         uint32_t old_write_domain;
2784
2785         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2786                 return;
2787
2788         /* No actual flushing is required for the GTT write domain.   Writes
2789          * to it immediately go to main memory as far as we know, so there's
2790          * no chipset flush.  It also doesn't land in render cache.
2791          */
2792         old_write_domain = obj->write_domain;
2793         obj->write_domain = 0;
2794
2795         trace_i915_gem_object_change_domain(obj,
2796                                             obj->read_domains,
2797                                             old_write_domain);
2798 }
2799
2800 /** Flushes the CPU write domain for the object if it's dirty. */
2801 static void
2802 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2803 {
2804         struct drm_device *dev = obj->dev;
2805         uint32_t old_write_domain;
2806
2807         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2808                 return;
2809
2810         i915_gem_clflush_object(obj);
2811         drm_agp_chipset_flush(dev);
2812         old_write_domain = obj->write_domain;
2813         obj->write_domain = 0;
2814
2815         trace_i915_gem_object_change_domain(obj,
2816                                             obj->read_domains,
2817                                             old_write_domain);
2818 }
2819
2820 void
2821 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2822 {
2823         switch (obj->write_domain) {
2824         case I915_GEM_DOMAIN_GTT:
2825                 i915_gem_object_flush_gtt_write_domain(obj);
2826                 break;
2827         case I915_GEM_DOMAIN_CPU:
2828                 i915_gem_object_flush_cpu_write_domain(obj);
2829                 break;
2830         default:
2831                 i915_gem_object_flush_gpu_write_domain(obj);
2832                 break;
2833         }
2834 }
2835
2836 /**
2837  * Moves a single object to the GTT read, and possibly write domain.
2838  *
2839  * This function returns when the move is complete, including waiting on
2840  * flushes to occur.
2841  */
2842 int
2843 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2844 {
2845         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2846         uint32_t old_write_domain, old_read_domains;
2847         int ret;
2848
2849         /* Not valid to be called on unbound objects. */
2850         if (obj_priv->gtt_space == NULL)
2851                 return -EINVAL;
2852
2853         i915_gem_object_flush_gpu_write_domain(obj);
2854         /* Wait on any GPU rendering and flushing to occur. */
2855         ret = i915_gem_object_wait_rendering(obj);
2856         if (ret != 0)
2857                 return ret;
2858
2859         old_write_domain = obj->write_domain;
2860         old_read_domains = obj->read_domains;
2861
2862         /* If we're writing through the GTT domain, then CPU and GPU caches
2863          * will need to be invalidated at next use.
2864          */
2865         if (write)
2866                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2867
2868         i915_gem_object_flush_cpu_write_domain(obj);
2869
2870         /* It should now be out of any other write domains, and we can update
2871          * the domain values for our changes.
2872          */
2873         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2874         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2875         if (write) {
2876                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2877                 obj_priv->dirty = 1;
2878         }
2879
2880         trace_i915_gem_object_change_domain(obj,
2881                                             old_read_domains,
2882                                             old_write_domain);
2883
2884         return 0;
2885 }
2886
2887 /*
2888  * Prepare buffer for display plane. Use uninterruptible for possible flush
2889  * wait, as in modesetting process we're not supposed to be interrupted.
2890  */
2891 int
2892 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2893 {
2894         struct drm_device *dev = obj->dev;
2895         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2896         uint32_t old_write_domain, old_read_domains;
2897         int ret;
2898
2899         /* Not valid to be called on unbound objects. */
2900         if (obj_priv->gtt_space == NULL)
2901                 return -EINVAL;
2902
2903         i915_gem_object_flush_gpu_write_domain(obj);
2904
2905         /* Wait on any GPU rendering and flushing to occur. */
2906         if (obj_priv->active) {
2907 #if WATCH_BUF
2908                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2909                           __func__, obj, obj_priv->last_rendering_seqno);
2910 #endif
2911                 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2912                 if (ret != 0)
2913                         return ret;
2914         }
2915
2916         old_write_domain = obj->write_domain;
2917         old_read_domains = obj->read_domains;
2918
2919         obj->read_domains &= I915_GEM_DOMAIN_GTT;
2920
2921         i915_gem_object_flush_cpu_write_domain(obj);
2922
2923         /* It should now be out of any other write domains, and we can update
2924          * the domain values for our changes.
2925          */
2926         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2927         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2928         obj->write_domain = I915_GEM_DOMAIN_GTT;
2929         obj_priv->dirty = 1;
2930
2931         trace_i915_gem_object_change_domain(obj,
2932                                             old_read_domains,
2933                                             old_write_domain);
2934
2935         return 0;
2936 }
2937
2938 /**
2939  * Moves a single object to the CPU read, and possibly write domain.
2940  *
2941  * This function returns when the move is complete, including waiting on
2942  * flushes to occur.
2943  */
2944 static int
2945 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2946 {
2947         uint32_t old_write_domain, old_read_domains;
2948         int ret;
2949
2950         i915_gem_object_flush_gpu_write_domain(obj);
2951         /* Wait on any GPU rendering and flushing to occur. */
2952         ret = i915_gem_object_wait_rendering(obj);
2953         if (ret != 0)
2954                 return ret;
2955
2956         i915_gem_object_flush_gtt_write_domain(obj);
2957
2958         /* If we have a partially-valid cache of the object in the CPU,
2959          * finish invalidating it and free the per-page flags.
2960          */
2961         i915_gem_object_set_to_full_cpu_read_domain(obj);
2962
2963         old_write_domain = obj->write_domain;
2964         old_read_domains = obj->read_domains;
2965
2966         /* Flush the CPU cache if it's still invalid. */
2967         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2968                 i915_gem_clflush_object(obj);
2969
2970                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2971         }
2972
2973         /* It should now be out of any other write domains, and we can update
2974          * the domain values for our changes.
2975          */
2976         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2977
2978         /* If we're writing through the CPU, then the GPU read domains will
2979          * need to be invalidated at next use.
2980          */
2981         if (write) {
2982                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2983                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2984         }
2985
2986         trace_i915_gem_object_change_domain(obj,
2987                                             old_read_domains,
2988                                             old_write_domain);
2989
2990         return 0;
2991 }
2992
2993 /*
2994  * Set the next domain for the specified object. This
2995  * may not actually perform the necessary flushing/invaliding though,
2996  * as that may want to be batched with other set_domain operations
2997  *
2998  * This is (we hope) the only really tricky part of gem. The goal
2999  * is fairly simple -- track which caches hold bits of the object
3000  * and make sure they remain coherent. A few concrete examples may
3001  * help to explain how it works. For shorthand, we use the notation
3002  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3003  * a pair of read and write domain masks.
3004  *
3005  * Case 1: the batch buffer
3006  *
3007  *      1. Allocated
3008  *      2. Written by CPU
3009  *      3. Mapped to GTT
3010  *      4. Read by GPU
3011  *      5. Unmapped from GTT
3012  *      6. Freed
3013  *
3014  *      Let's take these a step at a time
3015  *
3016  *      1. Allocated
3017  *              Pages allocated from the kernel may still have
3018  *              cache contents, so we set them to (CPU, CPU) always.
3019  *      2. Written by CPU (using pwrite)
3020  *              The pwrite function calls set_domain (CPU, CPU) and
3021  *              this function does nothing (as nothing changes)
3022  *      3. Mapped by GTT
3023  *              This function asserts that the object is not
3024  *              currently in any GPU-based read or write domains
3025  *      4. Read by GPU
3026  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3027  *              As write_domain is zero, this function adds in the
3028  *              current read domains (CPU+COMMAND, 0).
3029  *              flush_domains is set to CPU.
3030  *              invalidate_domains is set to COMMAND
3031  *              clflush is run to get data out of the CPU caches
3032  *              then i915_dev_set_domain calls i915_gem_flush to
3033  *              emit an MI_FLUSH and drm_agp_chipset_flush
3034  *      5. Unmapped from GTT
3035  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3036  *              flush_domains and invalidate_domains end up both zero
3037  *              so no flushing/invalidating happens
3038  *      6. Freed
3039  *              yay, done
3040  *
3041  * Case 2: The shared render buffer
3042  *
3043  *      1. Allocated
3044  *      2. Mapped to GTT
3045  *      3. Read/written by GPU
3046  *      4. set_domain to (CPU,CPU)
3047  *      5. Read/written by CPU
3048  *      6. Read/written by GPU
3049  *
3050  *      1. Allocated
3051  *              Same as last example, (CPU, CPU)
3052  *      2. Mapped to GTT
3053  *              Nothing changes (assertions find that it is not in the GPU)
3054  *      3. Read/written by GPU
3055  *              execbuffer calls set_domain (RENDER, RENDER)
3056  *              flush_domains gets CPU
3057  *              invalidate_domains gets GPU
3058  *              clflush (obj)
3059  *              MI_FLUSH and drm_agp_chipset_flush
3060  *      4. set_domain (CPU, CPU)
3061  *              flush_domains gets GPU
3062  *              invalidate_domains gets CPU
3063  *              wait_rendering (obj) to make sure all drawing is complete.
3064  *              This will include an MI_FLUSH to get the data from GPU
3065  *              to memory
3066  *              clflush (obj) to invalidate the CPU cache
3067  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3068  *      5. Read/written by CPU
3069  *              cache lines are loaded and dirtied
3070  *      6. Read written by GPU
3071  *              Same as last GPU access
3072  *
3073  * Case 3: The constant buffer
3074  *
3075  *      1. Allocated
3076  *      2. Written by CPU
3077  *      3. Read by GPU
3078  *      4. Updated (written) by CPU again
3079  *      5. Read by GPU
3080  *
3081  *      1. Allocated
3082  *              (CPU, CPU)
3083  *      2. Written by CPU
3084  *              (CPU, CPU)
3085  *      3. Read by GPU
3086  *              (CPU+RENDER, 0)
3087  *              flush_domains = CPU
3088  *              invalidate_domains = RENDER
3089  *              clflush (obj)
3090  *              MI_FLUSH
3091  *              drm_agp_chipset_flush
3092  *      4. Updated (written) by CPU again
3093  *              (CPU, CPU)
3094  *              flush_domains = 0 (no previous write domain)
3095  *              invalidate_domains = 0 (no new read domains)
3096  *      5. Read by GPU
3097  *              (CPU+RENDER, 0)
3098  *              flush_domains = CPU
3099  *              invalidate_domains = RENDER
3100  *              clflush (obj)
3101  *              MI_FLUSH
3102  *              drm_agp_chipset_flush
3103  */
3104 static void
3105 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3106 {
3107         struct drm_device               *dev = obj->dev;
3108         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
3109         uint32_t                        invalidate_domains = 0;
3110         uint32_t                        flush_domains = 0;
3111         uint32_t                        old_read_domains;
3112
3113         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3114         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3115
3116         intel_mark_busy(dev, obj);
3117
3118 #if WATCH_BUF
3119         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3120                  __func__, obj,
3121                  obj->read_domains, obj->pending_read_domains,
3122                  obj->write_domain, obj->pending_write_domain);
3123 #endif
3124         /*
3125          * If the object isn't moving to a new write domain,
3126          * let the object stay in multiple read domains
3127          */
3128         if (obj->pending_write_domain == 0)
3129                 obj->pending_read_domains |= obj->read_domains;
3130         else
3131                 obj_priv->dirty = 1;
3132
3133         /*
3134          * Flush the current write domain if
3135          * the new read domains don't match. Invalidate
3136          * any read domains which differ from the old
3137          * write domain
3138          */
3139         if (obj->write_domain &&
3140             obj->write_domain != obj->pending_read_domains) {
3141                 flush_domains |= obj->write_domain;
3142                 invalidate_domains |=
3143                         obj->pending_read_domains & ~obj->write_domain;
3144         }
3145         /*
3146          * Invalidate any read caches which may have
3147          * stale data. That is, any new read domains.
3148          */
3149         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3150         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3151 #if WATCH_BUF
3152                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3153                          __func__, flush_domains, invalidate_domains);
3154 #endif
3155                 i915_gem_clflush_object(obj);
3156         }
3157
3158         old_read_domains = obj->read_domains;
3159
3160         /* The actual obj->write_domain will be updated with
3161          * pending_write_domain after we emit the accumulated flush for all
3162          * of our domain changes in execbuffers (which clears objects'
3163          * write_domains).  So if we have a current write domain that we
3164          * aren't changing, set pending_write_domain to that.
3165          */
3166         if (flush_domains == 0 && obj->pending_write_domain == 0)
3167                 obj->pending_write_domain = obj->write_domain;
3168         obj->read_domains = obj->pending_read_domains;
3169
3170         dev->invalidate_domains |= invalidate_domains;
3171         dev->flush_domains |= flush_domains;
3172 #if WATCH_BUF
3173         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3174                  __func__,
3175                  obj->read_domains, obj->write_domain,
3176                  dev->invalidate_domains, dev->flush_domains);
3177 #endif
3178
3179         trace_i915_gem_object_change_domain(obj,
3180                                             old_read_domains,
3181                                             obj->write_domain);
3182 }
3183
3184 /**
3185  * Moves the object from a partially CPU read to a full one.
3186  *
3187  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3188  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3189  */
3190 static void
3191 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3192 {
3193         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3194
3195         if (!obj_priv->page_cpu_valid)
3196                 return;
3197
3198         /* If we're partially in the CPU read domain, finish moving it in.
3199          */
3200         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3201                 int i;
3202
3203                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3204                         if (obj_priv->page_cpu_valid[i])
3205                                 continue;
3206                         drm_clflush_pages(obj_priv->pages + i, 1);
3207                 }
3208         }
3209
3210         /* Free the page_cpu_valid mappings which are now stale, whether
3211          * or not we've got I915_GEM_DOMAIN_CPU.
3212          */
3213         kfree(obj_priv->page_cpu_valid);
3214         obj_priv->page_cpu_valid = NULL;
3215 }
3216
3217 /**
3218  * Set the CPU read domain on a range of the object.
3219  *
3220  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3221  * not entirely valid.  The page_cpu_valid member of the object flags which
3222  * pages have been flushed, and will be respected by
3223  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3224  * of the whole object.
3225  *
3226  * This function returns when the move is complete, including waiting on
3227  * flushes to occur.
3228  */
3229 static int
3230 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3231                                           uint64_t offset, uint64_t size)
3232 {
3233         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3234         uint32_t old_read_domains;
3235         int i, ret;
3236
3237         if (offset == 0 && size == obj->size)
3238                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3239
3240         i915_gem_object_flush_gpu_write_domain(obj);
3241         /* Wait on any GPU rendering and flushing to occur. */
3242         ret = i915_gem_object_wait_rendering(obj);
3243         if (ret != 0)
3244                 return ret;
3245         i915_gem_object_flush_gtt_write_domain(obj);
3246
3247         /* If we're already fully in the CPU read domain, we're done. */
3248         if (obj_priv->page_cpu_valid == NULL &&
3249             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3250                 return 0;
3251
3252         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3253          * newly adding I915_GEM_DOMAIN_CPU
3254          */
3255         if (obj_priv->page_cpu_valid == NULL) {
3256                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3257                                                    GFP_KERNEL);
3258                 if (obj_priv->page_cpu_valid == NULL)
3259                         return -ENOMEM;
3260         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3261                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3262
3263         /* Flush the cache on any pages that are still invalid from the CPU's
3264          * perspective.
3265          */
3266         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3267              i++) {
3268                 if (obj_priv->page_cpu_valid[i])
3269                         continue;
3270
3271                 drm_clflush_pages(obj_priv->pages + i, 1);
3272
3273                 obj_priv->page_cpu_valid[i] = 1;
3274         }
3275
3276         /* It should now be out of any other write domains, and we can update
3277          * the domain values for our changes.
3278          */
3279         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3280
3281         old_read_domains = obj->read_domains;
3282         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3283
3284         trace_i915_gem_object_change_domain(obj,
3285                                             old_read_domains,
3286                                             obj->write_domain);
3287
3288         return 0;
3289 }
3290
3291 /**
3292  * Pin an object to the GTT and evaluate the relocations landing in it.
3293  */
3294 static int
3295 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3296                                  struct drm_file *file_priv,
3297                                  struct drm_i915_gem_exec_object2 *entry,
3298                                  struct drm_i915_gem_relocation_entry *relocs)
3299 {
3300         struct drm_device *dev = obj->dev;
3301         drm_i915_private_t *dev_priv = dev->dev_private;
3302         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3303         int i, ret;
3304         void __iomem *reloc_page;
3305         bool need_fence;
3306
3307         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3308                      obj_priv->tiling_mode != I915_TILING_NONE;
3309
3310         /* Check fence reg constraints and rebind if necessary */
3311         if (need_fence && !i915_obj_fenceable(dev, obj))
3312                 i915_gem_object_unbind(obj);
3313
3314         /* Choose the GTT offset for our buffer and put it there. */
3315         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3316         if (ret)
3317                 return ret;
3318
3319         /*
3320          * Pre-965 chips need a fence register set up in order to
3321          * properly handle blits to/from tiled surfaces.
3322          */
3323         if (need_fence) {
3324                 ret = i915_gem_object_get_fence_reg(obj);
3325                 if (ret != 0) {
3326                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3327                                 DRM_ERROR("Failure to install fence: %d\n",
3328                                           ret);
3329                         i915_gem_object_unpin(obj);
3330                         return ret;
3331                 }
3332         }
3333
3334         entry->offset = obj_priv->gtt_offset;
3335
3336         /* Apply the relocations, using the GTT aperture to avoid cache
3337          * flushing requirements.
3338          */
3339         for (i = 0; i < entry->relocation_count; i++) {
3340                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3341                 struct drm_gem_object *target_obj;
3342                 struct drm_i915_gem_object *target_obj_priv;
3343                 uint32_t reloc_val, reloc_offset;
3344                 uint32_t __iomem *reloc_entry;
3345
3346                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3347                                                    reloc->target_handle);
3348                 if (target_obj == NULL) {
3349                         i915_gem_object_unpin(obj);
3350                         return -EBADF;
3351                 }
3352                 target_obj_priv = target_obj->driver_private;
3353
3354 #if WATCH_RELOC
3355                 DRM_INFO("%s: obj %p offset %08x target %d "
3356                          "read %08x write %08x gtt %08x "
3357                          "presumed %08x delta %08x\n",
3358                          __func__,
3359                          obj,
3360                          (int) reloc->offset,
3361                          (int) reloc->target_handle,
3362                          (int) reloc->read_domains,
3363                          (int) reloc->write_domain,
3364                          (int) target_obj_priv->gtt_offset,
3365                          (int) reloc->presumed_offset,
3366                          reloc->delta);
3367 #endif
3368
3369                 /* The target buffer should have appeared before us in the
3370                  * exec_object list, so it should have a GTT space bound by now.
3371                  */
3372                 if (target_obj_priv->gtt_space == NULL) {
3373                         DRM_ERROR("No GTT space found for object %d\n",
3374                                   reloc->target_handle);
3375                         drm_gem_object_unreference(target_obj);
3376                         i915_gem_object_unpin(obj);
3377                         return -EINVAL;
3378                 }
3379
3380                 /* Validate that the target is in a valid r/w GPU domain */
3381                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3382                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3383                         DRM_ERROR("reloc with read/write CPU domains: "
3384                                   "obj %p target %d offset %d "
3385                                   "read %08x write %08x",
3386                                   obj, reloc->target_handle,
3387                                   (int) reloc->offset,
3388                                   reloc->read_domains,
3389                                   reloc->write_domain);
3390                         drm_gem_object_unreference(target_obj);
3391                         i915_gem_object_unpin(obj);
3392                         return -EINVAL;
3393                 }
3394                 if (reloc->write_domain && target_obj->pending_write_domain &&
3395                     reloc->write_domain != target_obj->pending_write_domain) {
3396                         DRM_ERROR("Write domain conflict: "
3397                                   "obj %p target %d offset %d "
3398                                   "new %08x old %08x\n",
3399                                   obj, reloc->target_handle,
3400                                   (int) reloc->offset,
3401                                   reloc->write_domain,
3402                                   target_obj->pending_write_domain);
3403                         drm_gem_object_unreference(target_obj);
3404                         i915_gem_object_unpin(obj);
3405                         return -EINVAL;
3406                 }
3407
3408                 target_obj->pending_read_domains |= reloc->read_domains;
3409                 target_obj->pending_write_domain |= reloc->write_domain;
3410
3411                 /* If the relocation already has the right value in it, no
3412                  * more work needs to be done.
3413                  */
3414                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3415                         drm_gem_object_unreference(target_obj);
3416                         continue;
3417                 }
3418
3419                 /* Check that the relocation address is valid... */
3420                 if (reloc->offset > obj->size - 4) {
3421                         DRM_ERROR("Relocation beyond object bounds: "
3422                                   "obj %p target %d offset %d size %d.\n",
3423                                   obj, reloc->target_handle,
3424                                   (int) reloc->offset, (int) obj->size);
3425                         drm_gem_object_unreference(target_obj);
3426                         i915_gem_object_unpin(obj);
3427                         return -EINVAL;
3428                 }
3429                 if (reloc->offset & 3) {
3430                         DRM_ERROR("Relocation not 4-byte aligned: "
3431                                   "obj %p target %d offset %d.\n",
3432                                   obj, reloc->target_handle,
3433                                   (int) reloc->offset);
3434                         drm_gem_object_unreference(target_obj);
3435                         i915_gem_object_unpin(obj);
3436                         return -EINVAL;
3437                 }
3438
3439                 /* and points to somewhere within the target object. */
3440                 if (reloc->delta >= target_obj->size) {
3441                         DRM_ERROR("Relocation beyond target object bounds: "
3442                                   "obj %p target %d delta %d size %d.\n",
3443                                   obj, reloc->target_handle,
3444                                   (int) reloc->delta, (int) target_obj->size);
3445                         drm_gem_object_unreference(target_obj);
3446                         i915_gem_object_unpin(obj);
3447                         return -EINVAL;
3448                 }
3449
3450                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3451                 if (ret != 0) {
3452                         drm_gem_object_unreference(target_obj);
3453                         i915_gem_object_unpin(obj);
3454                         return -EINVAL;
3455                 }
3456
3457                 /* Map the page containing the relocation we're going to
3458                  * perform.
3459                  */
3460                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3461                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3462                                                       (reloc_offset &
3463                                                        ~(PAGE_SIZE - 1)));
3464                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3465                                                    (reloc_offset & (PAGE_SIZE - 1)));
3466                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3467
3468 #if WATCH_BUF
3469                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3470                           obj, (unsigned int) reloc->offset,
3471                           readl(reloc_entry), reloc_val);
3472 #endif
3473                 writel(reloc_val, reloc_entry);
3474                 io_mapping_unmap_atomic(reloc_page);
3475
3476                 /* The updated presumed offset for this entry will be
3477                  * copied back out to the user.
3478                  */
3479                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3480
3481                 drm_gem_object_unreference(target_obj);
3482         }
3483
3484 #if WATCH_BUF
3485         if (0)
3486                 i915_gem_dump_object(obj, 128, __func__, ~0);
3487 #endif
3488         return 0;
3489 }
3490
3491 /** Dispatch a batchbuffer to the ring
3492  */
3493 static int
3494 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3495                               struct drm_i915_gem_execbuffer2 *exec,
3496                               struct drm_clip_rect *cliprects,
3497                               uint64_t exec_offset)
3498 {
3499         drm_i915_private_t *dev_priv = dev->dev_private;
3500         int nbox = exec->num_cliprects;
3501         int i = 0, count;
3502         uint32_t exec_start, exec_len;
3503         RING_LOCALS;
3504
3505         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3506         exec_len = (uint32_t) exec->batch_len;
3507
3508         trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3509
3510         count = nbox ? nbox : 1;
3511
3512         for (i = 0; i < count; i++) {
3513                 if (i < nbox) {
3514                         int ret = i915_emit_box(dev, cliprects, i,
3515                                                 exec->DR1, exec->DR4);
3516                         if (ret)
3517                                 return ret;
3518                 }
3519
3520                 if (IS_I830(dev) || IS_845G(dev)) {
3521                         BEGIN_LP_RING(4);
3522                         OUT_RING(MI_BATCH_BUFFER);
3523                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3524                         OUT_RING(exec_start + exec_len - 4);
3525                         OUT_RING(0);
3526                         ADVANCE_LP_RING();
3527                 } else {
3528                         BEGIN_LP_RING(2);
3529                         if (IS_I965G(dev)) {
3530                                 OUT_RING(MI_BATCH_BUFFER_START |
3531                                          (2 << 6) |
3532                                          MI_BATCH_NON_SECURE_I965);
3533                                 OUT_RING(exec_start);
3534                         } else {
3535                                 OUT_RING(MI_BATCH_BUFFER_START |
3536                                          (2 << 6));
3537                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3538                         }
3539                         ADVANCE_LP_RING();
3540                 }
3541         }
3542
3543         /* XXX breadcrumb */
3544         return 0;
3545 }
3546
3547 /* Throttle our rendering by waiting until the ring has completed our requests
3548  * emitted over 20 msec ago.
3549  *
3550  * Note that if we were to use the current jiffies each time around the loop,
3551  * we wouldn't escape the function with any frames outstanding if the time to
3552  * render a frame was over 20ms.
3553  *
3554  * This should get us reasonable parallelism between CPU and GPU but also
3555  * relatively low latency when blocking on a particular request to finish.
3556  */
3557 static int
3558 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3559 {
3560         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3561         int ret = 0;
3562         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3563
3564         mutex_lock(&dev->struct_mutex);
3565         while (!list_empty(&i915_file_priv->mm.request_list)) {
3566                 struct drm_i915_gem_request *request;
3567
3568                 request = list_first_entry(&i915_file_priv->mm.request_list,
3569                                            struct drm_i915_gem_request,
3570                                            client_list);
3571
3572                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3573                         break;
3574
3575                 ret = i915_wait_request(dev, request->seqno);
3576                 if (ret != 0)
3577                         break;
3578         }
3579         mutex_unlock(&dev->struct_mutex);
3580
3581         return ret;
3582 }
3583
3584 static int
3585 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3586                               uint32_t buffer_count,
3587                               struct drm_i915_gem_relocation_entry **relocs)
3588 {
3589         uint32_t reloc_count = 0, reloc_index = 0, i;
3590         int ret;
3591
3592         *relocs = NULL;
3593         for (i = 0; i < buffer_count; i++) {
3594                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3595                         return -EINVAL;
3596                 reloc_count += exec_list[i].relocation_count;
3597         }
3598
3599         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3600         if (*relocs == NULL) {
3601                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3602                 return -ENOMEM;
3603         }
3604
3605         for (i = 0; i < buffer_count; i++) {
3606                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3607
3608                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3609
3610                 ret = copy_from_user(&(*relocs)[reloc_index],
3611                                      user_relocs,
3612                                      exec_list[i].relocation_count *
3613                                      sizeof(**relocs));
3614                 if (ret != 0) {
3615                         drm_free_large(*relocs);
3616                         *relocs = NULL;
3617                         return -EFAULT;
3618                 }
3619
3620                 reloc_index += exec_list[i].relocation_count;
3621         }
3622
3623         return 0;
3624 }
3625
3626 static int
3627 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3628                             uint32_t buffer_count,
3629                             struct drm_i915_gem_relocation_entry *relocs)
3630 {
3631         uint32_t reloc_count = 0, i;
3632         int ret = 0;
3633
3634         if (relocs == NULL)
3635             return 0;
3636
3637         for (i = 0; i < buffer_count; i++) {
3638                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3639                 int unwritten;
3640
3641                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3642
3643                 unwritten = copy_to_user(user_relocs,
3644                                          &relocs[reloc_count],
3645                                          exec_list[i].relocation_count *
3646                                          sizeof(*relocs));
3647
3648                 if (unwritten) {
3649                         ret = -EFAULT;
3650                         goto err;
3651                 }
3652
3653                 reloc_count += exec_list[i].relocation_count;
3654         }
3655
3656 err:
3657         drm_free_large(relocs);
3658
3659         return ret;
3660 }
3661
3662 static int
3663 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3664                            uint64_t exec_offset)
3665 {
3666         uint32_t exec_start, exec_len;
3667
3668         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3669         exec_len = (uint32_t) exec->batch_len;
3670
3671         if ((exec_start | exec_len) & 0x7)
3672                 return -EINVAL;
3673
3674         if (!exec_start)
3675                 return -EINVAL;
3676
3677         return 0;
3678 }
3679
3680 static int
3681 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3682                                struct drm_gem_object **object_list,
3683                                int count)
3684 {
3685         drm_i915_private_t *dev_priv = dev->dev_private;
3686         struct drm_i915_gem_object *obj_priv;
3687         DEFINE_WAIT(wait);
3688         int i, ret = 0;
3689
3690         for (;;) {
3691                 prepare_to_wait(&dev_priv->pending_flip_queue,
3692                                 &wait, TASK_INTERRUPTIBLE);
3693                 for (i = 0; i < count; i++) {
3694                         obj_priv = object_list[i]->driver_private;
3695                         if (atomic_read(&obj_priv->pending_flip) > 0)
3696                                 break;
3697                 }
3698                 if (i == count)
3699                         break;
3700
3701                 if (!signal_pending(current)) {
3702                         mutex_unlock(&dev->struct_mutex);
3703                         schedule();
3704                         mutex_lock(&dev->struct_mutex);
3705                         continue;
3706                 }
3707                 ret = -ERESTARTSYS;
3708                 break;
3709         }
3710         finish_wait(&dev_priv->pending_flip_queue, &wait);
3711
3712         return ret;
3713 }
3714
3715 int
3716 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3717                        struct drm_file *file_priv,
3718                        struct drm_i915_gem_execbuffer2 *args,
3719                        struct drm_i915_gem_exec_object2 *exec_list)
3720 {
3721         drm_i915_private_t *dev_priv = dev->dev_private;
3722         struct drm_gem_object **object_list = NULL;
3723         struct drm_gem_object *batch_obj;
3724         struct drm_i915_gem_object *obj_priv;
3725         struct drm_clip_rect *cliprects = NULL;
3726         struct drm_i915_gem_relocation_entry *relocs = NULL;
3727         int ret = 0, ret2, i, pinned = 0;
3728         uint64_t exec_offset;
3729         uint32_t seqno, flush_domains, reloc_index;
3730         int pin_tries, flips;
3731
3732 #if WATCH_EXEC
3733         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3734                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3735 #endif
3736
3737         if (args->buffer_count < 1) {
3738                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3739                 return -EINVAL;
3740         }
3741         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3742         if (object_list == NULL) {
3743                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3744                           args->buffer_count);
3745                 ret = -ENOMEM;
3746                 goto pre_mutex_err;
3747         }
3748
3749         if (args->num_cliprects != 0) {
3750                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3751                                     GFP_KERNEL);
3752                 if (cliprects == NULL) {
3753                         ret = -ENOMEM;
3754                         goto pre_mutex_err;
3755                 }
3756
3757                 ret = copy_from_user(cliprects,
3758                                      (struct drm_clip_rect __user *)
3759                                      (uintptr_t) args->cliprects_ptr,
3760                                      sizeof(*cliprects) * args->num_cliprects);
3761                 if (ret != 0) {
3762                         DRM_ERROR("copy %d cliprects failed: %d\n",
3763                                   args->num_cliprects, ret);
3764                         goto pre_mutex_err;
3765                 }
3766         }
3767
3768         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3769                                             &relocs);
3770         if (ret != 0)
3771                 goto pre_mutex_err;
3772
3773         mutex_lock(&dev->struct_mutex);
3774
3775         i915_verify_inactive(dev, __FILE__, __LINE__);
3776
3777         if (atomic_read(&dev_priv->mm.wedged)) {
3778                 mutex_unlock(&dev->struct_mutex);
3779                 ret = -EIO;
3780                 goto pre_mutex_err;
3781         }
3782
3783         if (dev_priv->mm.suspended) {
3784                 mutex_unlock(&dev->struct_mutex);
3785                 ret = -EBUSY;
3786                 goto pre_mutex_err;
3787         }
3788
3789         /* Look up object handles */
3790         flips = 0;
3791         for (i = 0; i < args->buffer_count; i++) {
3792                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3793                                                        exec_list[i].handle);
3794                 if (object_list[i] == NULL) {
3795                         DRM_ERROR("Invalid object handle %d at index %d\n",
3796                                    exec_list[i].handle, i);
3797                         /* prevent error path from reading uninitialized data */
3798                         args->buffer_count = i + 1;
3799                         ret = -EBADF;
3800                         goto err;
3801                 }
3802
3803                 obj_priv = object_list[i]->driver_private;
3804                 if (obj_priv->in_execbuffer) {
3805                         DRM_ERROR("Object %p appears more than once in object list\n",
3806                                    object_list[i]);
3807                         /* prevent error path from reading uninitialized data */
3808                         args->buffer_count = i + 1;
3809                         ret = -EBADF;
3810                         goto err;
3811                 }
3812                 obj_priv->in_execbuffer = true;
3813                 flips += atomic_read(&obj_priv->pending_flip);
3814         }
3815
3816         if (flips > 0) {
3817                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3818                                                      args->buffer_count);
3819                 if (ret)
3820                         goto err;
3821         }
3822
3823         /* Pin and relocate */
3824         for (pin_tries = 0; ; pin_tries++) {
3825                 ret = 0;
3826                 reloc_index = 0;
3827
3828                 for (i = 0; i < args->buffer_count; i++) {
3829                         object_list[i]->pending_read_domains = 0;
3830                         object_list[i]->pending_write_domain = 0;
3831                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3832                                                                file_priv,
3833                                                                &exec_list[i],
3834                                                                &relocs[reloc_index]);
3835                         if (ret)
3836                                 break;
3837                         pinned = i + 1;
3838                         reloc_index += exec_list[i].relocation_count;
3839                 }
3840                 /* success */
3841                 if (ret == 0)
3842                         break;
3843
3844                 /* error other than GTT full, or we've already tried again */
3845                 if (ret != -ENOSPC || pin_tries >= 1) {
3846                         if (ret != -ERESTARTSYS) {
3847                                 unsigned long long total_size = 0;
3848                                 for (i = 0; i < args->buffer_count; i++)
3849                                         total_size += object_list[i]->size;
3850                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3851                                           pinned+1, args->buffer_count,
3852                                           total_size, ret);
3853                                 DRM_ERROR("%d objects [%d pinned], "
3854                                           "%d object bytes [%d pinned], "
3855                                           "%d/%d gtt bytes\n",
3856                                           atomic_read(&dev->object_count),
3857                                           atomic_read(&dev->pin_count),
3858                                           atomic_read(&dev->object_memory),
3859                                           atomic_read(&dev->pin_memory),
3860                                           atomic_read(&dev->gtt_memory),
3861                                           dev->gtt_total);
3862                         }
3863                         goto err;
3864                 }
3865
3866                 /* unpin all of our buffers */
3867                 for (i = 0; i < pinned; i++)
3868                         i915_gem_object_unpin(object_list[i]);
3869                 pinned = 0;
3870
3871                 /* evict everyone we can from the aperture */
3872                 ret = i915_gem_evict_everything(dev);
3873                 if (ret && ret != -ENOSPC)
3874                         goto err;
3875         }
3876
3877         /* Set the pending read domains for the batch buffer to COMMAND */
3878         batch_obj = object_list[args->buffer_count-1];
3879         if (batch_obj->pending_write_domain) {
3880                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3881                 ret = -EINVAL;
3882                 goto err;
3883         }
3884         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3885
3886         /* Sanity check the batch buffer, prior to moving objects */
3887         exec_offset = exec_list[args->buffer_count - 1].offset;
3888         ret = i915_gem_check_execbuffer (args, exec_offset);
3889         if (ret != 0) {
3890                 DRM_ERROR("execbuf with invalid offset/length\n");
3891                 goto err;
3892         }
3893
3894         i915_verify_inactive(dev, __FILE__, __LINE__);
3895
3896         /* Zero the global flush/invalidate flags. These
3897          * will be modified as new domains are computed
3898          * for each object
3899          */
3900         dev->invalidate_domains = 0;
3901         dev->flush_domains = 0;
3902
3903         for (i = 0; i < args->buffer_count; i++) {
3904                 struct drm_gem_object *obj = object_list[i];
3905
3906                 /* Compute new gpu domains and update invalidate/flush */
3907                 i915_gem_object_set_to_gpu_domain(obj);
3908         }
3909
3910         i915_verify_inactive(dev, __FILE__, __LINE__);
3911
3912         if (dev->invalidate_domains | dev->flush_domains) {
3913 #if WATCH_EXEC
3914                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3915                           __func__,
3916                          dev->invalidate_domains,
3917                          dev->flush_domains);
3918 #endif
3919                 i915_gem_flush(dev,
3920                                dev->invalidate_domains,
3921                                dev->flush_domains);
3922                 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3923                         (void)i915_add_request(dev, file_priv,
3924                                                dev->flush_domains);
3925         }
3926
3927         for (i = 0; i < args->buffer_count; i++) {
3928                 struct drm_gem_object *obj = object_list[i];
3929                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3930                 uint32_t old_write_domain = obj->write_domain;
3931
3932                 obj->write_domain = obj->pending_write_domain;
3933                 if (obj->write_domain)
3934                         list_move_tail(&obj_priv->gpu_write_list,
3935                                        &dev_priv->mm.gpu_write_list);
3936                 else
3937                         list_del_init(&obj_priv->gpu_write_list);
3938
3939                 trace_i915_gem_object_change_domain(obj,
3940                                                     obj->read_domains,
3941                                                     old_write_domain);
3942         }
3943
3944         i915_verify_inactive(dev, __FILE__, __LINE__);
3945
3946 #if WATCH_COHERENCY
3947         for (i = 0; i < args->buffer_count; i++) {
3948                 i915_gem_object_check_coherency(object_list[i],
3949                                                 exec_list[i].handle);
3950         }
3951 #endif
3952
3953 #if WATCH_EXEC
3954         i915_gem_dump_object(batch_obj,
3955                               args->batch_len,
3956                               __func__,
3957                               ~0);
3958 #endif
3959
3960         /* Exec the batchbuffer */
3961         ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3962         if (ret) {
3963                 DRM_ERROR("dispatch failed %d\n", ret);
3964                 goto err;
3965         }
3966
3967         /*
3968          * Ensure that the commands in the batch buffer are
3969          * finished before the interrupt fires
3970          */
3971         flush_domains = i915_retire_commands(dev);
3972
3973         i915_verify_inactive(dev, __FILE__, __LINE__);
3974
3975         /*
3976          * Get a seqno representing the execution of the current buffer,
3977          * which we can wait on.  We would like to mitigate these interrupts,
3978          * likely by only creating seqnos occasionally (so that we have
3979          * *some* interrupts representing completion of buffers that we can
3980          * wait on when trying to clear up gtt space).
3981          */
3982         seqno = i915_add_request(dev, file_priv, flush_domains);
3983         BUG_ON(seqno == 0);
3984         for (i = 0; i < args->buffer_count; i++) {
3985                 struct drm_gem_object *obj = object_list[i];
3986
3987                 i915_gem_object_move_to_active(obj, seqno);
3988 #if WATCH_LRU
3989                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3990 #endif
3991         }
3992 #if WATCH_LRU
3993         i915_dump_lru(dev, __func__);
3994 #endif
3995
3996         i915_verify_inactive(dev, __FILE__, __LINE__);
3997
3998 err:
3999         for (i = 0; i < pinned; i++)
4000                 i915_gem_object_unpin(object_list[i]);
4001
4002         for (i = 0; i < args->buffer_count; i++) {
4003                 if (object_list[i]) {
4004                         obj_priv = object_list[i]->driver_private;
4005                         obj_priv->in_execbuffer = false;
4006                 }
4007                 drm_gem_object_unreference(object_list[i]);
4008         }
4009
4010         mutex_unlock(&dev->struct_mutex);
4011
4012 pre_mutex_err:
4013         /* Copy the updated relocations out regardless of current error
4014          * state.  Failure to update the relocs would mean that the next
4015          * time userland calls execbuf, it would do so with presumed offset
4016          * state that didn't match the actual object state.
4017          */
4018         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4019                                            relocs);
4020         if (ret2 != 0) {
4021                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4022
4023                 if (ret == 0)
4024                         ret = ret2;
4025         }
4026
4027         drm_free_large(object_list);
4028         kfree(cliprects);
4029
4030         return ret;
4031 }
4032
4033 /*
4034  * Legacy execbuffer just creates an exec2 list from the original exec object
4035  * list array and passes it to the real function.
4036  */
4037 int
4038 i915_gem_execbuffer(struct drm_device *dev, void *data,
4039                     struct drm_file *file_priv)
4040 {
4041         struct drm_i915_gem_execbuffer *args = data;
4042         struct drm_i915_gem_execbuffer2 exec2;
4043         struct drm_i915_gem_exec_object *exec_list = NULL;
4044         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4045         int ret, i;
4046
4047 #if WATCH_EXEC
4048         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4049                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4050 #endif
4051
4052         if (args->buffer_count < 1) {
4053                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4054                 return -EINVAL;
4055         }
4056
4057         /* Copy in the exec list from userland */
4058         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4059         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4060         if (exec_list == NULL || exec2_list == NULL) {
4061                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4062                           args->buffer_count);
4063                 drm_free_large(exec_list);
4064                 drm_free_large(exec2_list);
4065                 return -ENOMEM;
4066         }
4067         ret = copy_from_user(exec_list,
4068                              (struct drm_i915_relocation_entry __user *)
4069                              (uintptr_t) args->buffers_ptr,
4070                              sizeof(*exec_list) * args->buffer_count);
4071         if (ret != 0) {
4072                 DRM_ERROR("copy %d exec entries failed %d\n",
4073                           args->buffer_count, ret);
4074                 drm_free_large(exec_list);
4075                 drm_free_large(exec2_list);
4076                 return -EFAULT;
4077         }
4078
4079         for (i = 0; i < args->buffer_count; i++) {
4080                 exec2_list[i].handle = exec_list[i].handle;
4081                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4082                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4083                 exec2_list[i].alignment = exec_list[i].alignment;
4084                 exec2_list[i].offset = exec_list[i].offset;
4085                 if (!IS_I965G(dev))
4086                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4087                 else
4088                         exec2_list[i].flags = 0;
4089         }
4090
4091         exec2.buffers_ptr = args->buffers_ptr;
4092         exec2.buffer_count = args->buffer_count;
4093         exec2.batch_start_offset = args->batch_start_offset;
4094         exec2.batch_len = args->batch_len;
4095         exec2.DR1 = args->DR1;
4096         exec2.DR4 = args->DR4;
4097         exec2.num_cliprects = args->num_cliprects;
4098         exec2.cliprects_ptr = args->cliprects_ptr;
4099         exec2.flags = 0;
4100
4101         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4102         if (!ret) {
4103                 /* Copy the new buffer offsets back to the user's exec list. */
4104                 for (i = 0; i < args->buffer_count; i++)
4105                         exec_list[i].offset = exec2_list[i].offset;
4106                 /* ... and back out to userspace */
4107                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4108                                    (uintptr_t) args->buffers_ptr,
4109                                    exec_list,
4110                                    sizeof(*exec_list) * args->buffer_count);
4111                 if (ret) {
4112                         ret = -EFAULT;
4113                         DRM_ERROR("failed to copy %d exec entries "
4114                                   "back to user (%d)\n",
4115                                   args->buffer_count, ret);
4116                 }
4117         }
4118
4119         drm_free_large(exec_list);
4120         drm_free_large(exec2_list);
4121         return ret;
4122 }
4123
4124 int
4125 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4126                      struct drm_file *file_priv)
4127 {
4128         struct drm_i915_gem_execbuffer2 *args = data;
4129         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4130         int ret;
4131
4132 #if WATCH_EXEC
4133         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4134                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4135 #endif
4136
4137         if (args->buffer_count < 1) {
4138                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4139                 return -EINVAL;
4140         }
4141
4142         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4143         if (exec2_list == NULL) {
4144                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4145                           args->buffer_count);
4146                 return -ENOMEM;
4147         }
4148         ret = copy_from_user(exec2_list,
4149                              (struct drm_i915_relocation_entry __user *)
4150                              (uintptr_t) args->buffers_ptr,
4151                              sizeof(*exec2_list) * args->buffer_count);
4152         if (ret != 0) {
4153                 DRM_ERROR("copy %d exec entries failed %d\n",
4154                           args->buffer_count, ret);
4155                 drm_free_large(exec2_list);
4156                 return -EFAULT;
4157         }
4158
4159         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4160         if (!ret) {
4161                 /* Copy the new buffer offsets back to the user's exec list. */
4162                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4163                                    (uintptr_t) args->buffers_ptr,
4164                                    exec2_list,
4165                                    sizeof(*exec2_list) * args->buffer_count);
4166                 if (ret) {
4167                         ret = -EFAULT;
4168                         DRM_ERROR("failed to copy %d exec entries "
4169                                   "back to user (%d)\n",
4170                                   args->buffer_count, ret);
4171                 }
4172         }
4173
4174         drm_free_large(exec2_list);
4175         return ret;
4176 }
4177
4178 int
4179 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4180 {
4181         struct drm_device *dev = obj->dev;
4182         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4183         int ret;
4184
4185         i915_verify_inactive(dev, __FILE__, __LINE__);
4186
4187         if (obj_priv->gtt_space != NULL) {
4188                 if (alignment == 0)
4189                         alignment = i915_gem_get_gtt_alignment(obj);
4190                 if (obj_priv->gtt_offset & (alignment - 1)) {
4191                         ret = i915_gem_object_unbind(obj);
4192                         if (ret)
4193                                 return ret;
4194                 }
4195         }
4196
4197         if (obj_priv->gtt_space == NULL) {
4198                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4199                 if (ret)
4200                         return ret;
4201         }
4202
4203         obj_priv->pin_count++;
4204
4205         /* If the object is not active and not pending a flush,
4206          * remove it from the inactive list
4207          */
4208         if (obj_priv->pin_count == 1) {
4209                 atomic_inc(&dev->pin_count);
4210                 atomic_add(obj->size, &dev->pin_memory);
4211                 if (!obj_priv->active &&
4212                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4213                     !list_empty(&obj_priv->list))
4214                         list_del_init(&obj_priv->list);
4215         }
4216         i915_verify_inactive(dev, __FILE__, __LINE__);
4217
4218         return 0;
4219 }
4220
4221 void
4222 i915_gem_object_unpin(struct drm_gem_object *obj)
4223 {
4224         struct drm_device *dev = obj->dev;
4225         drm_i915_private_t *dev_priv = dev->dev_private;
4226         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4227
4228         i915_verify_inactive(dev, __FILE__, __LINE__);
4229         obj_priv->pin_count--;
4230         BUG_ON(obj_priv->pin_count < 0);
4231         BUG_ON(obj_priv->gtt_space == NULL);
4232
4233         /* If the object is no longer pinned, and is
4234          * neither active nor being flushed, then stick it on
4235          * the inactive list
4236          */
4237         if (obj_priv->pin_count == 0) {
4238                 if (!obj_priv->active &&
4239                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4240                         list_move_tail(&obj_priv->list,
4241                                        &dev_priv->mm.inactive_list);
4242                 atomic_dec(&dev->pin_count);
4243                 atomic_sub(obj->size, &dev->pin_memory);
4244         }
4245         i915_verify_inactive(dev, __FILE__, __LINE__);
4246 }
4247
4248 int
4249 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4250                    struct drm_file *file_priv)
4251 {
4252         struct drm_i915_gem_pin *args = data;
4253         struct drm_gem_object *obj;
4254         struct drm_i915_gem_object *obj_priv;
4255         int ret;
4256
4257         mutex_lock(&dev->struct_mutex);
4258
4259         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4260         if (obj == NULL) {
4261                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4262                           args->handle);
4263                 mutex_unlock(&dev->struct_mutex);
4264                 return -EBADF;
4265         }
4266         obj_priv = obj->driver_private;
4267
4268         if (obj_priv->madv != I915_MADV_WILLNEED) {
4269                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4270                 drm_gem_object_unreference(obj);
4271                 mutex_unlock(&dev->struct_mutex);
4272                 return -EINVAL;
4273         }
4274
4275         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4276                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4277                           args->handle);
4278                 drm_gem_object_unreference(obj);
4279                 mutex_unlock(&dev->struct_mutex);
4280                 return -EINVAL;
4281         }
4282
4283         obj_priv->user_pin_count++;
4284         obj_priv->pin_filp = file_priv;
4285         if (obj_priv->user_pin_count == 1) {
4286                 ret = i915_gem_object_pin(obj, args->alignment);
4287                 if (ret != 0) {
4288                         drm_gem_object_unreference(obj);
4289                         mutex_unlock(&dev->struct_mutex);
4290                         return ret;
4291                 }
4292         }
4293
4294         /* XXX - flush the CPU caches for pinned objects
4295          * as the X server doesn't manage domains yet
4296          */
4297         i915_gem_object_flush_cpu_write_domain(obj);
4298         args->offset = obj_priv->gtt_offset;
4299         drm_gem_object_unreference(obj);
4300         mutex_unlock(&dev->struct_mutex);
4301
4302         return 0;
4303 }
4304
4305 int
4306 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4307                      struct drm_file *file_priv)
4308 {
4309         struct drm_i915_gem_pin *args = data;
4310         struct drm_gem_object *obj;
4311         struct drm_i915_gem_object *obj_priv;
4312
4313         mutex_lock(&dev->struct_mutex);
4314
4315         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4316         if (obj == NULL) {
4317                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4318                           args->handle);
4319                 mutex_unlock(&dev->struct_mutex);
4320                 return -EBADF;
4321         }
4322
4323         obj_priv = obj->driver_private;
4324         if (obj_priv->pin_filp != file_priv) {
4325                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4326                           args->handle);
4327                 drm_gem_object_unreference(obj);
4328                 mutex_unlock(&dev->struct_mutex);
4329                 return -EINVAL;
4330         }
4331         obj_priv->user_pin_count--;
4332         if (obj_priv->user_pin_count == 0) {
4333                 obj_priv->pin_filp = NULL;
4334                 i915_gem_object_unpin(obj);
4335         }
4336
4337         drm_gem_object_unreference(obj);
4338         mutex_unlock(&dev->struct_mutex);
4339         return 0;
4340 }
4341
4342 int
4343 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4344                     struct drm_file *file_priv)
4345 {
4346         struct drm_i915_gem_busy *args = data;
4347         struct drm_gem_object *obj;
4348         struct drm_i915_gem_object *obj_priv;
4349
4350         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4351         if (obj == NULL) {
4352                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4353                           args->handle);
4354                 return -EBADF;
4355         }
4356
4357         mutex_lock(&dev->struct_mutex);
4358         /* Update the active list for the hardware's current position.
4359          * Otherwise this only updates on a delayed timer or when irqs are
4360          * actually unmasked, and our working set ends up being larger than
4361          * required.
4362          */
4363         i915_gem_retire_requests(dev);
4364
4365         obj_priv = obj->driver_private;
4366         /* Don't count being on the flushing list against the object being
4367          * done.  Otherwise, a buffer left on the flushing list but not getting
4368          * flushed (because nobody's flushing that domain) won't ever return
4369          * unbusy and get reused by libdrm's bo cache.  The other expected
4370          * consumer of this interface, OpenGL's occlusion queries, also specs
4371          * that the objects get unbusy "eventually" without any interference.
4372          */
4373         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4374
4375         drm_gem_object_unreference(obj);
4376         mutex_unlock(&dev->struct_mutex);
4377         return 0;
4378 }
4379
4380 int
4381 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4382                         struct drm_file *file_priv)
4383 {
4384     return i915_gem_ring_throttle(dev, file_priv);
4385 }
4386
4387 int
4388 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4389                        struct drm_file *file_priv)
4390 {
4391         struct drm_i915_gem_madvise *args = data;
4392         struct drm_gem_object *obj;
4393         struct drm_i915_gem_object *obj_priv;
4394
4395         switch (args->madv) {
4396         case I915_MADV_DONTNEED:
4397         case I915_MADV_WILLNEED:
4398             break;
4399         default:
4400             return -EINVAL;
4401         }
4402
4403         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4404         if (obj == NULL) {
4405                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4406                           args->handle);
4407                 return -EBADF;
4408         }
4409
4410         mutex_lock(&dev->struct_mutex);
4411         obj_priv = obj->driver_private;
4412
4413         if (obj_priv->pin_count) {
4414                 drm_gem_object_unreference(obj);
4415                 mutex_unlock(&dev->struct_mutex);
4416
4417                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4418                 return -EINVAL;
4419         }
4420
4421         if (obj_priv->madv != __I915_MADV_PURGED)
4422                 obj_priv->madv = args->madv;
4423
4424         /* if the object is no longer bound, discard its backing storage */
4425         if (i915_gem_object_is_purgeable(obj_priv) &&
4426             obj_priv->gtt_space == NULL)
4427                 i915_gem_object_truncate(obj);
4428
4429         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4430
4431         drm_gem_object_unreference(obj);
4432         mutex_unlock(&dev->struct_mutex);
4433
4434         return 0;
4435 }
4436
4437 int i915_gem_init_object(struct drm_gem_object *obj)
4438 {
4439         struct drm_i915_gem_object *obj_priv;
4440
4441         obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4442         if (obj_priv == NULL)
4443                 return -ENOMEM;
4444
4445         /*
4446          * We've just allocated pages from the kernel,
4447          * so they've just been written by the CPU with
4448          * zeros. They'll need to be clflushed before we
4449          * use them with the GPU.
4450          */
4451         obj->write_domain = I915_GEM_DOMAIN_CPU;
4452         obj->read_domains = I915_GEM_DOMAIN_CPU;
4453
4454         obj_priv->agp_type = AGP_USER_MEMORY;
4455
4456         obj->driver_private = obj_priv;
4457         obj_priv->obj = obj;
4458         obj_priv->fence_reg = I915_FENCE_REG_NONE;
4459         INIT_LIST_HEAD(&obj_priv->list);
4460         INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4461         INIT_LIST_HEAD(&obj_priv->fence_list);
4462         obj_priv->madv = I915_MADV_WILLNEED;
4463
4464         trace_i915_gem_object_create(obj);
4465
4466         return 0;
4467 }
4468
4469 void i915_gem_free_object(struct drm_gem_object *obj)
4470 {
4471         struct drm_device *dev = obj->dev;
4472         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4473
4474         trace_i915_gem_object_destroy(obj);
4475
4476         while (obj_priv->pin_count > 0)
4477                 i915_gem_object_unpin(obj);
4478
4479         if (obj_priv->phys_obj)
4480                 i915_gem_detach_phys_object(dev, obj);
4481
4482         i915_gem_object_unbind(obj);
4483
4484         if (obj_priv->mmap_offset)
4485                 i915_gem_free_mmap_offset(obj);
4486
4487         kfree(obj_priv->page_cpu_valid);
4488         kfree(obj_priv->bit_17);
4489         kfree(obj->driver_private);
4490 }
4491
4492 /** Unbinds all inactive objects. */
4493 static int
4494 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4495 {
4496         drm_i915_private_t *dev_priv = dev->dev_private;
4497
4498         while (!list_empty(&dev_priv->mm.inactive_list)) {
4499                 struct drm_gem_object *obj;
4500                 int ret;
4501
4502                 obj = list_first_entry(&dev_priv->mm.inactive_list,
4503                                        struct drm_i915_gem_object,
4504                                        list)->obj;
4505
4506                 ret = i915_gem_object_unbind(obj);
4507                 if (ret != 0) {
4508                         DRM_ERROR("Error unbinding object: %d\n", ret);
4509                         return ret;
4510                 }
4511         }
4512
4513         return 0;
4514 }
4515
4516 int
4517 i915_gem_idle(struct drm_device *dev)
4518 {
4519         drm_i915_private_t *dev_priv = dev->dev_private;
4520         uint32_t seqno, cur_seqno, last_seqno;
4521         int stuck, ret;
4522
4523         mutex_lock(&dev->struct_mutex);
4524
4525         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4526                 mutex_unlock(&dev->struct_mutex);
4527                 return 0;
4528         }
4529
4530         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4531          * We need to replace this with a semaphore, or something.
4532          */
4533         dev_priv->mm.suspended = 1;
4534         del_timer(&dev_priv->hangcheck_timer);
4535
4536         /* Cancel the retire work handler, wait for it to finish if running
4537          */
4538         mutex_unlock(&dev->struct_mutex);
4539         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4540         mutex_lock(&dev->struct_mutex);
4541
4542         i915_kernel_lost_context(dev);
4543
4544         /* Flush the GPU along with all non-CPU write domains
4545          */
4546         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4547         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4548
4549         if (seqno == 0) {
4550                 mutex_unlock(&dev->struct_mutex);
4551                 return -ENOMEM;
4552         }
4553
4554         dev_priv->mm.waiting_gem_seqno = seqno;
4555         last_seqno = 0;
4556         stuck = 0;
4557         for (;;) {
4558                 cur_seqno = i915_get_gem_seqno(dev);
4559                 if (i915_seqno_passed(cur_seqno, seqno))
4560                         break;
4561                 if (last_seqno == cur_seqno) {
4562                         if (stuck++ > 100) {
4563                                 DRM_ERROR("hardware wedged\n");
4564                                 atomic_set(&dev_priv->mm.wedged, 1);
4565                                 DRM_WAKEUP(&dev_priv->irq_queue);
4566                                 break;
4567                         }
4568                 }
4569                 msleep(10);
4570                 last_seqno = cur_seqno;
4571         }
4572         dev_priv->mm.waiting_gem_seqno = 0;
4573
4574         i915_gem_retire_requests(dev);
4575
4576         spin_lock(&dev_priv->mm.active_list_lock);
4577         if (!atomic_read(&dev_priv->mm.wedged)) {
4578                 /* Active and flushing should now be empty as we've
4579                  * waited for a sequence higher than any pending execbuffer
4580                  */
4581                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4582                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4583                 /* Request should now be empty as we've also waited
4584                  * for the last request in the list
4585                  */
4586                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4587         }
4588
4589         /* Empty the active and flushing lists to inactive.  If there's
4590          * anything left at this point, it means that we're wedged and
4591          * nothing good's going to happen by leaving them there.  So strip
4592          * the GPU domains and just stuff them onto inactive.
4593          */
4594         while (!list_empty(&dev_priv->mm.active_list)) {
4595                 struct drm_gem_object *obj;
4596                 uint32_t old_write_domain;
4597
4598                 obj = list_first_entry(&dev_priv->mm.active_list,
4599                                        struct drm_i915_gem_object,
4600                                        list)->obj;
4601                 old_write_domain = obj->write_domain;
4602                 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4603                 i915_gem_object_move_to_inactive(obj);
4604
4605                 trace_i915_gem_object_change_domain(obj,
4606                                                     obj->read_domains,
4607                                                     old_write_domain);
4608         }
4609         spin_unlock(&dev_priv->mm.active_list_lock);
4610
4611         while (!list_empty(&dev_priv->mm.flushing_list)) {
4612                 struct drm_gem_object *obj;
4613                 uint32_t old_write_domain;
4614
4615                 obj = list_first_entry(&dev_priv->mm.flushing_list,
4616                                        struct drm_i915_gem_object,
4617                                        list)->obj;
4618                 old_write_domain = obj->write_domain;
4619                 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4620                 i915_gem_object_move_to_inactive(obj);
4621
4622                 trace_i915_gem_object_change_domain(obj,
4623                                                     obj->read_domains,
4624                                                     old_write_domain);
4625         }
4626
4627
4628         /* Move all inactive buffers out of the GTT. */
4629         ret = i915_gem_evict_from_inactive_list(dev);
4630         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4631         if (ret) {
4632                 mutex_unlock(&dev->struct_mutex);
4633                 return ret;
4634         }
4635
4636         i915_gem_cleanup_ringbuffer(dev);
4637         mutex_unlock(&dev->struct_mutex);
4638
4639         return 0;
4640 }
4641
4642 /*
4643  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4644  * over cache flushing.
4645  */
4646 static int
4647 i915_gem_init_pipe_control(struct drm_device *dev)
4648 {
4649         drm_i915_private_t *dev_priv = dev->dev_private;
4650         struct drm_gem_object *obj;
4651         struct drm_i915_gem_object *obj_priv;
4652         int ret;
4653
4654         obj = drm_gem_object_alloc(dev, 4096);
4655         if (obj == NULL) {
4656                 DRM_ERROR("Failed to allocate seqno page\n");
4657                 ret = -ENOMEM;
4658                 goto err;
4659         }
4660         obj_priv = obj->driver_private;
4661         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4662
4663         ret = i915_gem_object_pin(obj, 4096);
4664         if (ret)
4665                 goto err_unref;
4666
4667         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4668         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4669         if (dev_priv->seqno_page == NULL)
4670                 goto err_unpin;
4671
4672         dev_priv->seqno_obj = obj;
4673         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4674
4675         return 0;
4676
4677 err_unpin:
4678         i915_gem_object_unpin(obj);
4679 err_unref:
4680         drm_gem_object_unreference(obj);
4681 err:
4682         return ret;
4683 }
4684
4685 static int
4686 i915_gem_init_hws(struct drm_device *dev)
4687 {
4688         drm_i915_private_t *dev_priv = dev->dev_private;
4689         struct drm_gem_object *obj;
4690         struct drm_i915_gem_object *obj_priv;
4691         int ret;
4692
4693         /* If we need a physical address for the status page, it's already
4694          * initialized at driver load time.
4695          */
4696         if (!I915_NEED_GFX_HWS(dev))
4697                 return 0;
4698
4699         obj = drm_gem_object_alloc(dev, 4096);
4700         if (obj == NULL) {
4701                 DRM_ERROR("Failed to allocate status page\n");
4702                 ret = -ENOMEM;
4703                 goto err;
4704         }
4705         obj_priv = obj->driver_private;
4706         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4707
4708         ret = i915_gem_object_pin(obj, 4096);
4709         if (ret != 0) {
4710                 drm_gem_object_unreference(obj);
4711                 goto err_unref;
4712         }
4713
4714         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4715
4716         dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4717         if (dev_priv->hw_status_page == NULL) {
4718                 DRM_ERROR("Failed to map status page.\n");
4719                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4720                 ret = -EINVAL;
4721                 goto err_unpin;
4722         }
4723
4724         if (HAS_PIPE_CONTROL(dev)) {
4725                 ret = i915_gem_init_pipe_control(dev);
4726                 if (ret)
4727                         goto err_unpin;
4728         }
4729
4730         dev_priv->hws_obj = obj;
4731         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4732         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4733         I915_READ(HWS_PGA); /* posting read */
4734         DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4735
4736         return 0;
4737
4738 err_unpin:
4739         i915_gem_object_unpin(obj);
4740 err_unref:
4741         drm_gem_object_unreference(obj);
4742 err:
4743         return 0;
4744 }
4745
4746 static void
4747 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4748 {
4749         drm_i915_private_t *dev_priv = dev->dev_private;
4750         struct drm_gem_object *obj;
4751         struct drm_i915_gem_object *obj_priv;
4752
4753         obj = dev_priv->seqno_obj;
4754         obj_priv = obj->driver_private;
4755         kunmap(obj_priv->pages[0]);
4756         i915_gem_object_unpin(obj);
4757         drm_gem_object_unreference(obj);
4758         dev_priv->seqno_obj = NULL;
4759
4760         dev_priv->seqno_page = NULL;
4761 }
4762
4763 static void
4764 i915_gem_cleanup_hws(struct drm_device *dev)
4765 {
4766         drm_i915_private_t *dev_priv = dev->dev_private;
4767         struct drm_gem_object *obj;
4768         struct drm_i915_gem_object *obj_priv;
4769
4770         if (dev_priv->hws_obj == NULL)
4771                 return;
4772
4773         obj = dev_priv->hws_obj;
4774         obj_priv = obj->driver_private;
4775
4776         kunmap(obj_priv->pages[0]);
4777         i915_gem_object_unpin(obj);
4778         drm_gem_object_unreference(obj);
4779         dev_priv->hws_obj = NULL;
4780
4781         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4782         dev_priv->hw_status_page = NULL;
4783
4784         if (HAS_PIPE_CONTROL(dev))
4785                 i915_gem_cleanup_pipe_control(dev);
4786
4787         /* Write high address into HWS_PGA when disabling. */
4788         I915_WRITE(HWS_PGA, 0x1ffff000);
4789 }
4790
4791 int
4792 i915_gem_init_ringbuffer(struct drm_device *dev)
4793 {
4794         drm_i915_private_t *dev_priv = dev->dev_private;
4795         struct drm_gem_object *obj;
4796         struct drm_i915_gem_object *obj_priv;
4797         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4798         int ret;
4799         u32 head;
4800
4801         ret = i915_gem_init_hws(dev);
4802         if (ret != 0)
4803                 return ret;
4804
4805         obj = drm_gem_object_alloc(dev, 128 * 1024);
4806         if (obj == NULL) {
4807                 DRM_ERROR("Failed to allocate ringbuffer\n");
4808                 i915_gem_cleanup_hws(dev);
4809                 return -ENOMEM;
4810         }
4811         obj_priv = obj->driver_private;
4812
4813         ret = i915_gem_object_pin(obj, 4096);
4814         if (ret != 0) {
4815                 drm_gem_object_unreference(obj);
4816                 i915_gem_cleanup_hws(dev);
4817                 return ret;
4818         }
4819
4820         /* Set up the kernel mapping for the ring. */
4821         ring->Size = obj->size;
4822
4823         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4824         ring->map.size = obj->size;
4825         ring->map.type = 0;
4826         ring->map.flags = 0;
4827         ring->map.mtrr = 0;
4828
4829         drm_core_ioremap_wc(&ring->map, dev);
4830         if (ring->map.handle == NULL) {
4831                 DRM_ERROR("Failed to map ringbuffer.\n");
4832                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4833                 i915_gem_object_unpin(obj);
4834                 drm_gem_object_unreference(obj);
4835                 i915_gem_cleanup_hws(dev);
4836                 return -EINVAL;
4837         }
4838         ring->ring_obj = obj;
4839         ring->virtual_start = ring->map.handle;
4840
4841         /* Stop the ring if it's running. */
4842         I915_WRITE(PRB0_CTL, 0);
4843         I915_WRITE(PRB0_TAIL, 0);
4844         I915_WRITE(PRB0_HEAD, 0);
4845
4846         /* Initialize the ring. */
4847         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4848         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4849
4850         /* G45 ring initialization fails to reset head to zero */
4851         if (head != 0) {
4852                 DRM_ERROR("Ring head not reset to zero "
4853                           "ctl %08x head %08x tail %08x start %08x\n",
4854                           I915_READ(PRB0_CTL),
4855                           I915_READ(PRB0_HEAD),
4856                           I915_READ(PRB0_TAIL),
4857                           I915_READ(PRB0_START));
4858                 I915_WRITE(PRB0_HEAD, 0);
4859
4860                 DRM_ERROR("Ring head forced to zero "
4861                           "ctl %08x head %08x tail %08x start %08x\n",
4862                           I915_READ(PRB0_CTL),
4863                           I915_READ(PRB0_HEAD),
4864                           I915_READ(PRB0_TAIL),
4865                           I915_READ(PRB0_START));
4866         }
4867
4868         I915_WRITE(PRB0_CTL,
4869                    ((obj->size - 4096) & RING_NR_PAGES) |
4870                    RING_NO_REPORT |
4871                    RING_VALID);
4872
4873         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4874
4875         /* If the head is still not zero, the ring is dead */
4876         if (head != 0) {
4877                 DRM_ERROR("Ring initialization failed "
4878                           "ctl %08x head %08x tail %08x start %08x\n",
4879                           I915_READ(PRB0_CTL),
4880                           I915_READ(PRB0_HEAD),
4881                           I915_READ(PRB0_TAIL),
4882                           I915_READ(PRB0_START));
4883                 return -EIO;
4884         }
4885
4886         /* Update our cache of the ring state */
4887         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4888                 i915_kernel_lost_context(dev);
4889         else {
4890                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4891                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4892                 ring->space = ring->head - (ring->tail + 8);
4893                 if (ring->space < 0)
4894                         ring->space += ring->Size;
4895         }
4896
4897         return 0;
4898 }
4899
4900 void
4901 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4902 {
4903         drm_i915_private_t *dev_priv = dev->dev_private;
4904
4905         if (dev_priv->ring.ring_obj == NULL)
4906                 return;
4907
4908         drm_core_ioremapfree(&dev_priv->ring.map, dev);
4909
4910         i915_gem_object_unpin(dev_priv->ring.ring_obj);
4911         drm_gem_object_unreference(dev_priv->ring.ring_obj);
4912         dev_priv->ring.ring_obj = NULL;
4913         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4914
4915         i915_gem_cleanup_hws(dev);
4916 }
4917
4918 int
4919 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4920                        struct drm_file *file_priv)
4921 {
4922         drm_i915_private_t *dev_priv = dev->dev_private;
4923         int ret;
4924
4925         if (drm_core_check_feature(dev, DRIVER_MODESET))
4926                 return 0;
4927
4928         if (atomic_read(&dev_priv->mm.wedged)) {
4929                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4930                 atomic_set(&dev_priv->mm.wedged, 0);
4931         }
4932
4933         mutex_lock(&dev->struct_mutex);
4934         dev_priv->mm.suspended = 0;
4935
4936         ret = i915_gem_init_ringbuffer(dev);
4937         if (ret != 0) {
4938                 mutex_unlock(&dev->struct_mutex);
4939                 return ret;
4940         }
4941
4942         spin_lock(&dev_priv->mm.active_list_lock);
4943         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4944         spin_unlock(&dev_priv->mm.active_list_lock);
4945
4946         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4947         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4948         BUG_ON(!list_empty(&dev_priv->mm.request_list));
4949         mutex_unlock(&dev->struct_mutex);
4950
4951         drm_irq_install(dev);
4952
4953         return 0;
4954 }
4955
4956 int
4957 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4958                        struct drm_file *file_priv)
4959 {
4960         if (drm_core_check_feature(dev, DRIVER_MODESET))
4961                 return 0;
4962
4963         drm_irq_uninstall(dev);
4964         return i915_gem_idle(dev);
4965 }
4966
4967 void
4968 i915_gem_lastclose(struct drm_device *dev)
4969 {
4970         int ret;
4971
4972         if (drm_core_check_feature(dev, DRIVER_MODESET))
4973                 return;
4974
4975         ret = i915_gem_idle(dev);
4976         if (ret)
4977                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4978 }
4979
4980 void
4981 i915_gem_load(struct drm_device *dev)
4982 {
4983         int i;
4984         drm_i915_private_t *dev_priv = dev->dev_private;
4985
4986         spin_lock_init(&dev_priv->mm.active_list_lock);
4987         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4988         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4989         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4990         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4991         INIT_LIST_HEAD(&dev_priv->mm.request_list);
4992         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4993         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4994                           i915_gem_retire_work_handler);
4995         dev_priv->mm.next_gem_seqno = 1;
4996
4997         spin_lock(&shrink_list_lock);
4998         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4999         spin_unlock(&shrink_list_lock);
5000
5001         /* Old X drivers will take 0-2 for front, back, depth buffers */
5002         dev_priv->fence_reg_start = 3;
5003
5004         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5005                 dev_priv->num_fence_regs = 16;
5006         else
5007                 dev_priv->num_fence_regs = 8;
5008
5009         /* Initialize fence registers to zero */
5010         if (IS_I965G(dev)) {
5011                 for (i = 0; i < 16; i++)
5012                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
5013         } else {
5014                 for (i = 0; i < 8; i++)
5015                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
5016                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5017                         for (i = 0; i < 8; i++)
5018                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
5019         }
5020         i915_gem_detect_bit_6_swizzle(dev);
5021         init_waitqueue_head(&dev_priv->pending_flip_queue);
5022 }
5023
5024 /*
5025  * Create a physically contiguous memory object for this object
5026  * e.g. for cursor + overlay regs
5027  */
5028 int i915_gem_init_phys_object(struct drm_device *dev,
5029                               int id, int size)
5030 {
5031         drm_i915_private_t *dev_priv = dev->dev_private;
5032         struct drm_i915_gem_phys_object *phys_obj;
5033         int ret;
5034
5035         if (dev_priv->mm.phys_objs[id - 1] || !size)
5036                 return 0;
5037
5038         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
5039         if (!phys_obj)
5040                 return -ENOMEM;
5041
5042         phys_obj->id = id;
5043
5044         phys_obj->handle = drm_pci_alloc(dev, size, 0);
5045         if (!phys_obj->handle) {
5046                 ret = -ENOMEM;
5047                 goto kfree_obj;
5048         }
5049 #ifdef CONFIG_X86
5050         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
5051 #endif
5052
5053         dev_priv->mm.phys_objs[id - 1] = phys_obj;
5054
5055         return 0;
5056 kfree_obj:
5057         kfree(phys_obj);
5058         return ret;
5059 }
5060
5061 void i915_gem_free_phys_object(struct drm_device *dev, int id)
5062 {
5063         drm_i915_private_t *dev_priv = dev->dev_private;
5064         struct drm_i915_gem_phys_object *phys_obj;
5065
5066         if (!dev_priv->mm.phys_objs[id - 1])
5067                 return;
5068
5069         phys_obj = dev_priv->mm.phys_objs[id - 1];
5070         if (phys_obj->cur_obj) {
5071                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
5072         }
5073
5074 #ifdef CONFIG_X86
5075         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
5076 #endif
5077         drm_pci_free(dev, phys_obj->handle);
5078         kfree(phys_obj);
5079         dev_priv->mm.phys_objs[id - 1] = NULL;
5080 }
5081
5082 void i915_gem_free_all_phys_object(struct drm_device *dev)
5083 {
5084         int i;
5085
5086         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
5087                 i915_gem_free_phys_object(dev, i);
5088 }
5089
5090 void i915_gem_detach_phys_object(struct drm_device *dev,
5091                                  struct drm_gem_object *obj)
5092 {
5093         struct drm_i915_gem_object *obj_priv;
5094         int i;
5095         int ret;
5096         int page_count;
5097
5098         obj_priv = obj->driver_private;
5099         if (!obj_priv->phys_obj)
5100                 return;
5101
5102         ret = i915_gem_object_get_pages(obj, 0);
5103         if (ret)
5104                 goto out;
5105
5106         page_count = obj->size / PAGE_SIZE;
5107
5108         for (i = 0; i < page_count; i++) {
5109                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
5110                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5111
5112                 memcpy(dst, src, PAGE_SIZE);
5113                 kunmap_atomic(dst, KM_USER0);
5114         }
5115         drm_clflush_pages(obj_priv->pages, page_count);
5116         drm_agp_chipset_flush(dev);
5117
5118         i915_gem_object_put_pages(obj);
5119 out:
5120         obj_priv->phys_obj->cur_obj = NULL;
5121         obj_priv->phys_obj = NULL;
5122 }
5123
5124 int
5125 i915_gem_attach_phys_object(struct drm_device *dev,
5126                             struct drm_gem_object *obj, int id)
5127 {
5128         drm_i915_private_t *dev_priv = dev->dev_private;
5129         struct drm_i915_gem_object *obj_priv;
5130         int ret = 0;
5131         int page_count;
5132         int i;
5133
5134         if (id > I915_MAX_PHYS_OBJECT)
5135                 return -EINVAL;
5136
5137         obj_priv = obj->driver_private;
5138
5139         if (obj_priv->phys_obj) {
5140                 if (obj_priv->phys_obj->id == id)
5141                         return 0;
5142                 i915_gem_detach_phys_object(dev, obj);
5143         }
5144
5145
5146         /* create a new object */
5147         if (!dev_priv->mm.phys_objs[id - 1]) {
5148                 ret = i915_gem_init_phys_object(dev, id,
5149                                                 obj->size);
5150                 if (ret) {
5151                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
5152                         goto out;
5153                 }
5154         }
5155
5156         /* bind to the object */
5157         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5158         obj_priv->phys_obj->cur_obj = obj;
5159
5160         ret = i915_gem_object_get_pages(obj, 0);
5161         if (ret) {
5162                 DRM_ERROR("failed to get page list\n");
5163                 goto out;
5164         }
5165
5166         page_count = obj->size / PAGE_SIZE;
5167
5168         for (i = 0; i < page_count; i++) {
5169                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5170                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5171
5172                 memcpy(dst, src, PAGE_SIZE);
5173                 kunmap_atomic(src, KM_USER0);
5174         }
5175
5176         i915_gem_object_put_pages(obj);
5177
5178         return 0;
5179 out:
5180         return ret;
5181 }
5182
5183 static int
5184 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5185                      struct drm_i915_gem_pwrite *args,
5186                      struct drm_file *file_priv)
5187 {
5188         struct drm_i915_gem_object *obj_priv = obj->driver_private;
5189         void *obj_addr;
5190         int ret;
5191         char __user *user_data;
5192
5193         user_data = (char __user *) (uintptr_t) args->data_ptr;
5194         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5195
5196         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5197         ret = copy_from_user(obj_addr, user_data, args->size);
5198         if (ret)
5199                 return -EFAULT;
5200
5201         drm_agp_chipset_flush(dev);
5202         return 0;
5203 }
5204
5205 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5206 {
5207         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5208
5209         /* Clean up our request list when the client is going away, so that
5210          * later retire_requests won't dereference our soon-to-be-gone
5211          * file_priv.
5212          */
5213         mutex_lock(&dev->struct_mutex);
5214         while (!list_empty(&i915_file_priv->mm.request_list))
5215                 list_del_init(i915_file_priv->mm.request_list.next);
5216         mutex_unlock(&dev->struct_mutex);
5217 }
5218
5219 static int
5220 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5221 {
5222         drm_i915_private_t *dev_priv, *next_dev;
5223         struct drm_i915_gem_object *obj_priv, *next_obj;
5224         int cnt = 0;
5225         int would_deadlock = 1;
5226
5227         /* "fast-path" to count number of available objects */
5228         if (nr_to_scan == 0) {
5229                 spin_lock(&shrink_list_lock);
5230                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5231                         struct drm_device *dev = dev_priv->dev;
5232
5233                         if (mutex_trylock(&dev->struct_mutex)) {
5234                                 list_for_each_entry(obj_priv,
5235                                                     &dev_priv->mm.inactive_list,
5236                                                     list)
5237                                         cnt++;
5238                                 mutex_unlock(&dev->struct_mutex);
5239                         }
5240                 }
5241                 spin_unlock(&shrink_list_lock);
5242
5243                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5244         }
5245
5246         spin_lock(&shrink_list_lock);
5247
5248         /* first scan for clean buffers */
5249         list_for_each_entry_safe(dev_priv, next_dev,
5250                                  &shrink_list, mm.shrink_list) {
5251                 struct drm_device *dev = dev_priv->dev;
5252
5253                 if (! mutex_trylock(&dev->struct_mutex))
5254                         continue;
5255
5256                 spin_unlock(&shrink_list_lock);
5257
5258                 i915_gem_retire_requests(dev);
5259
5260                 list_for_each_entry_safe(obj_priv, next_obj,
5261                                          &dev_priv->mm.inactive_list,
5262                                          list) {
5263                         if (i915_gem_object_is_purgeable(obj_priv)) {
5264                                 i915_gem_object_unbind(obj_priv->obj);
5265                                 if (--nr_to_scan <= 0)
5266                                         break;
5267                         }
5268                 }
5269
5270                 spin_lock(&shrink_list_lock);
5271                 mutex_unlock(&dev->struct_mutex);
5272
5273                 would_deadlock = 0;
5274
5275                 if (nr_to_scan <= 0)
5276                         break;
5277         }
5278
5279         /* second pass, evict/count anything still on the inactive list */
5280         list_for_each_entry_safe(dev_priv, next_dev,
5281                                  &shrink_list, mm.shrink_list) {
5282                 struct drm_device *dev = dev_priv->dev;
5283
5284                 if (! mutex_trylock(&dev->struct_mutex))
5285                         continue;
5286
5287                 spin_unlock(&shrink_list_lock);
5288
5289                 list_for_each_entry_safe(obj_priv, next_obj,
5290                                          &dev_priv->mm.inactive_list,
5291                                          list) {
5292                         if (nr_to_scan > 0) {
5293                                 i915_gem_object_unbind(obj_priv->obj);
5294                                 nr_to_scan--;
5295                         } else
5296                                 cnt++;
5297                 }
5298
5299                 spin_lock(&shrink_list_lock);
5300                 mutex_unlock(&dev->struct_mutex);
5301
5302                 would_deadlock = 0;
5303         }
5304
5305         spin_unlock(&shrink_list_lock);
5306
5307         if (would_deadlock)
5308                 return -1;
5309         else if (cnt > 0)
5310                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5311         else
5312                 return 0;
5313 }
5314
5315 static struct shrinker shrinker = {
5316         .shrink = i915_gem_shrink,
5317         .seeks = DEFAULT_SEEKS,
5318 };
5319
5320 __init void
5321 i915_gem_shrinker_init(void)
5322 {
5323     register_shrinker(&shrinker);
5324 }
5325
5326 __exit void
5327 i915_gem_shrinker_exit(void)
5328 {
5329     unregister_shrinker(&shrinker);
5330 }