2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(dev) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
60 return obj->pin_display;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
67 spin_lock(&dev_priv->mm.object_stat_lock);
68 dev_priv->mm.object_count++;
69 dev_priv->mm.object_memory += size;
70 spin_unlock(&dev_priv->mm.object_stat_lock);
73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
76 spin_lock(&dev_priv->mm.object_stat_lock);
77 dev_priv->mm.object_count--;
78 dev_priv->mm.object_memory -= size;
79 spin_unlock(&dev_priv->mm.object_stat_lock);
83 i915_gem_wait_for_error(struct i915_gpu_error *error)
87 if (!i915_reset_in_progress(error))
91 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
92 * userspace. If it takes that long something really bad is going on and
93 * we should simply try to bail out and fail as gracefully as possible.
95 ret = wait_event_interruptible_timeout(error->reset_queue,
96 !i915_reset_in_progress(error),
99 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
101 } else if (ret < 0) {
108 int i915_mutex_lock_interruptible(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
113 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
117 ret = mutex_lock_interruptible(&dev->struct_mutex);
121 WARN_ON(i915_verify_lists(dev));
126 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file)
129 struct drm_i915_private *dev_priv = to_i915(dev);
130 struct i915_ggtt *ggtt = &dev_priv->ggtt;
131 struct drm_i915_gem_get_aperture *args = data;
132 struct i915_vma *vma;
136 mutex_lock(&dev->struct_mutex);
137 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
139 pinned += vma->node.size;
140 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
142 pinned += vma->node.size;
143 mutex_unlock(&dev->struct_mutex);
145 args->aper_size = ggtt->base.total;
146 args->aper_available_size = args->aper_size - pinned;
152 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
154 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
155 char *vaddr = obj->phys_handle->vaddr;
157 struct scatterlist *sg;
160 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
163 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
167 page = shmem_read_mapping_page(mapping, i);
169 return PTR_ERR(page);
171 src = kmap_atomic(page);
172 memcpy(vaddr, src, PAGE_SIZE);
173 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 i915_gem_chipset_flush(obj->base.dev);
182 st = kmalloc(sizeof(*st), GFP_KERNEL);
186 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
193 sg->length = obj->base.size;
195 sg_dma_address(sg) = obj->phys_handle->busaddr;
196 sg_dma_len(sg) = obj->base.size;
203 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
207 BUG_ON(obj->madv == __I915_MADV_PURGED);
209 ret = i915_gem_object_set_to_cpu_domain(obj, true);
211 /* In the event of a disaster, abandon all caches and
214 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
217 if (obj->madv == I915_MADV_DONTNEED)
221 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
222 char *vaddr = obj->phys_handle->vaddr;
225 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
229 page = shmem_read_mapping_page(mapping, i);
233 dst = kmap_atomic(page);
234 drm_clflush_virt_range(vaddr, PAGE_SIZE);
235 memcpy(dst, vaddr, PAGE_SIZE);
238 set_page_dirty(page);
239 if (obj->madv == I915_MADV_WILLNEED)
240 mark_page_accessed(page);
247 sg_free_table(obj->pages);
252 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
254 drm_pci_free(obj->base.dev, obj->phys_handle);
257 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
258 .get_pages = i915_gem_object_get_pages_phys,
259 .put_pages = i915_gem_object_put_pages_phys,
260 .release = i915_gem_object_release_phys,
264 drop_pages(struct drm_i915_gem_object *obj)
266 struct i915_vma *vma, *next;
269 drm_gem_object_reference(&obj->base);
270 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
271 if (i915_vma_unbind(vma))
274 ret = i915_gem_object_put_pages(obj);
275 drm_gem_object_unreference(&obj->base);
281 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
284 drm_dma_handle_t *phys;
287 if (obj->phys_handle) {
288 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
294 if (obj->madv != I915_MADV_WILLNEED)
297 if (obj->base.filp == NULL)
300 ret = drop_pages(obj);
304 /* create a new object */
305 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
309 obj->phys_handle = phys;
310 obj->ops = &i915_gem_phys_ops;
312 return i915_gem_object_get_pages(obj);
316 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
317 struct drm_i915_gem_pwrite *args,
318 struct drm_file *file_priv)
320 struct drm_device *dev = obj->base.dev;
321 void *vaddr = obj->phys_handle->vaddr + args->offset;
322 char __user *user_data = to_user_ptr(args->data_ptr);
325 /* We manually control the domain here and pretend that it
326 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
328 ret = i915_gem_object_wait_rendering(obj, false);
332 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
333 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
334 unsigned long unwritten;
336 /* The physical object once assigned is fixed for the lifetime
337 * of the obj, so we can safely drop the lock and continue
340 mutex_unlock(&dev->struct_mutex);
341 unwritten = copy_from_user(vaddr, user_data, args->size);
342 mutex_lock(&dev->struct_mutex);
349 drm_clflush_virt_range(vaddr, args->size);
350 i915_gem_chipset_flush(dev);
353 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
357 void *i915_gem_object_alloc(struct drm_device *dev)
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
363 void i915_gem_object_free(struct drm_i915_gem_object *obj)
365 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
366 kmem_cache_free(dev_priv->objects, obj);
370 i915_gem_create(struct drm_file *file,
371 struct drm_device *dev,
375 struct drm_i915_gem_object *obj;
379 size = roundup(size, PAGE_SIZE);
383 /* Allocate the new object */
384 obj = i915_gem_alloc_object(dev, size);
388 ret = drm_gem_handle_create(file, &obj->base, &handle);
389 /* drop reference from allocate - handle holds it now */
390 drm_gem_object_unreference_unlocked(&obj->base);
399 i915_gem_dumb_create(struct drm_file *file,
400 struct drm_device *dev,
401 struct drm_mode_create_dumb *args)
403 /* have to work out size/pitch and return them */
404 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
405 args->size = args->pitch * args->height;
406 return i915_gem_create(file, dev,
407 args->size, &args->handle);
411 * Creates a new mm object and returns a handle to it.
414 i915_gem_create_ioctl(struct drm_device *dev, void *data,
415 struct drm_file *file)
417 struct drm_i915_gem_create *args = data;
419 return i915_gem_create(file, dev,
420 args->size, &args->handle);
424 __copy_to_user_swizzled(char __user *cpu_vaddr,
425 const char *gpu_vaddr, int gpu_offset,
428 int ret, cpu_offset = 0;
431 int cacheline_end = ALIGN(gpu_offset + 1, 64);
432 int this_length = min(cacheline_end - gpu_offset, length);
433 int swizzled_gpu_offset = gpu_offset ^ 64;
435 ret = __copy_to_user(cpu_vaddr + cpu_offset,
436 gpu_vaddr + swizzled_gpu_offset,
441 cpu_offset += this_length;
442 gpu_offset += this_length;
443 length -= this_length;
450 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
451 const char __user *cpu_vaddr,
454 int ret, cpu_offset = 0;
457 int cacheline_end = ALIGN(gpu_offset + 1, 64);
458 int this_length = min(cacheline_end - gpu_offset, length);
459 int swizzled_gpu_offset = gpu_offset ^ 64;
461 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
462 cpu_vaddr + cpu_offset,
467 cpu_offset += this_length;
468 gpu_offset += this_length;
469 length -= this_length;
476 * Pins the specified object's pages and synchronizes the object with
477 * GPU accesses. Sets needs_clflush to non-zero if the caller should
478 * flush the object from the CPU cache.
480 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
487 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
490 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
491 /* If we're not in the cpu read domain, set ourself into the gtt
492 * read domain and manually flush cachelines (if required). This
493 * optimizes for the case when the gpu will dirty the data
494 * anyway again before the next pread happens. */
495 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
497 ret = i915_gem_object_wait_rendering(obj, true);
502 ret = i915_gem_object_get_pages(obj);
506 i915_gem_object_pin_pages(obj);
511 /* Per-page copy function for the shmem pread fastpath.
512 * Flushes invalid cachelines before reading the target if
513 * needs_clflush is set. */
515 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
516 char __user *user_data,
517 bool page_do_bit17_swizzling, bool needs_clflush)
522 if (unlikely(page_do_bit17_swizzling))
525 vaddr = kmap_atomic(page);
527 drm_clflush_virt_range(vaddr + shmem_page_offset,
529 ret = __copy_to_user_inatomic(user_data,
530 vaddr + shmem_page_offset,
532 kunmap_atomic(vaddr);
534 return ret ? -EFAULT : 0;
538 shmem_clflush_swizzled_range(char *addr, unsigned long length,
541 if (unlikely(swizzled)) {
542 unsigned long start = (unsigned long) addr;
543 unsigned long end = (unsigned long) addr + length;
545 /* For swizzling simply ensure that we always flush both
546 * channels. Lame, but simple and it works. Swizzled
547 * pwrite/pread is far from a hotpath - current userspace
548 * doesn't use it at all. */
549 start = round_down(start, 128);
550 end = round_up(end, 128);
552 drm_clflush_virt_range((void *)start, end - start);
554 drm_clflush_virt_range(addr, length);
559 /* Only difference to the fast-path function is that this can handle bit17
560 * and uses non-atomic copy and kmap functions. */
562 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
563 char __user *user_data,
564 bool page_do_bit17_swizzling, bool needs_clflush)
571 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
573 page_do_bit17_swizzling);
575 if (page_do_bit17_swizzling)
576 ret = __copy_to_user_swizzled(user_data,
577 vaddr, shmem_page_offset,
580 ret = __copy_to_user(user_data,
581 vaddr + shmem_page_offset,
585 return ret ? - EFAULT : 0;
589 i915_gem_shmem_pread(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pread *args,
592 struct drm_file *file)
594 char __user *user_data;
597 int shmem_page_offset, page_length, ret = 0;
598 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
600 int needs_clflush = 0;
601 struct sg_page_iter sg_iter;
603 user_data = to_user_ptr(args->data_ptr);
606 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
608 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
612 offset = args->offset;
614 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
615 offset >> PAGE_SHIFT) {
616 struct page *page = sg_page_iter_page(&sg_iter);
621 /* Operation in this page
623 * shmem_page_offset = offset within page in shmem file
624 * page_length = bytes to copy for this page
626 shmem_page_offset = offset_in_page(offset);
627 page_length = remain;
628 if ((shmem_page_offset + page_length) > PAGE_SIZE)
629 page_length = PAGE_SIZE - shmem_page_offset;
631 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
632 (page_to_phys(page) & (1 << 17)) != 0;
634 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
635 user_data, page_do_bit17_swizzling,
640 mutex_unlock(&dev->struct_mutex);
642 if (likely(!i915.prefault_disable) && !prefaulted) {
643 ret = fault_in_multipages_writeable(user_data, remain);
644 /* Userspace is tricking us, but we've already clobbered
645 * its pages with the prefault and promised to write the
646 * data up to the first fault. Hence ignore any errors
647 * and just continue. */
652 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
653 user_data, page_do_bit17_swizzling,
656 mutex_lock(&dev->struct_mutex);
662 remain -= page_length;
663 user_data += page_length;
664 offset += page_length;
668 i915_gem_object_unpin_pages(obj);
674 * Reads data from the object referenced by handle.
676 * On error, the contents of *data are undefined.
679 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file)
682 struct drm_i915_gem_pread *args = data;
683 struct drm_i915_gem_object *obj;
689 if (!access_ok(VERIFY_WRITE,
690 to_user_ptr(args->data_ptr),
694 ret = i915_mutex_lock_interruptible(dev);
698 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
699 if (&obj->base == NULL) {
704 /* Bounds check source. */
705 if (args->offset > obj->base.size ||
706 args->size > obj->base.size - args->offset) {
711 /* prime objects have no backing filp to GEM pread/pwrite
714 if (!obj->base.filp) {
719 trace_i915_gem_object_pread(obj, args->offset, args->size);
721 ret = i915_gem_shmem_pread(dev, obj, args, file);
724 drm_gem_object_unreference(&obj->base);
726 mutex_unlock(&dev->struct_mutex);
730 /* This is the fast write path which cannot handle
731 * page faults in the source data
735 fast_user_write(struct io_mapping *mapping,
736 loff_t page_base, int page_offset,
737 char __user *user_data,
740 void __iomem *vaddr_atomic;
742 unsigned long unwritten;
744 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
745 /* We can use the cpu mem copy function because this is X86. */
746 vaddr = (void __force*)vaddr_atomic + page_offset;
747 unwritten = __copy_from_user_inatomic_nocache(vaddr,
749 io_mapping_unmap_atomic(vaddr_atomic);
754 * This is the fast pwrite path, where we copy the data directly from the
755 * user into the GTT, uncached.
758 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
759 struct drm_i915_gem_object *obj,
760 struct drm_i915_gem_pwrite *args,
761 struct drm_file *file)
763 struct drm_i915_private *dev_priv = to_i915(dev);
764 struct i915_ggtt *ggtt = &dev_priv->ggtt;
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length, ret;
770 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
774 ret = i915_gem_object_set_to_gtt_domain(obj, true);
778 ret = i915_gem_object_put_fence(obj);
782 user_data = to_user_ptr(args->data_ptr);
785 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
787 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base = offset & PAGE_MASK;
797 page_offset = offset_in_page(offset);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
802 /* If we get a fault while copying data, then (presumably) our
803 * source page isn't available. Return the error and we'll
804 * retry in the slow path.
806 if (fast_user_write(ggtt->mappable, page_base,
807 page_offset, user_data, page_length)) {
812 remain -= page_length;
813 user_data += page_length;
814 offset += page_length;
818 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
820 i915_gem_object_ggtt_unpin(obj);
825 /* Per-page copy function for the shmem pwrite fastpath.
826 * Flushes invalid cachelines before writing to the target if
827 * needs_clflush_before is set and flushes out any written cachelines after
828 * writing if needs_clflush is set. */
830 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
831 char __user *user_data,
832 bool page_do_bit17_swizzling,
833 bool needs_clflush_before,
834 bool needs_clflush_after)
839 if (unlikely(page_do_bit17_swizzling))
842 vaddr = kmap_atomic(page);
843 if (needs_clflush_before)
844 drm_clflush_virt_range(vaddr + shmem_page_offset,
846 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
847 user_data, page_length);
848 if (needs_clflush_after)
849 drm_clflush_virt_range(vaddr + shmem_page_offset,
851 kunmap_atomic(vaddr);
853 return ret ? -EFAULT : 0;
856 /* Only difference to the fast-path function is that this can handle bit17
857 * and uses non-atomic copy and kmap functions. */
859 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
860 char __user *user_data,
861 bool page_do_bit17_swizzling,
862 bool needs_clflush_before,
863 bool needs_clflush_after)
869 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
870 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
872 page_do_bit17_swizzling);
873 if (page_do_bit17_swizzling)
874 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
878 ret = __copy_from_user(vaddr + shmem_page_offset,
881 if (needs_clflush_after)
882 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
884 page_do_bit17_swizzling);
887 return ret ? -EFAULT : 0;
891 i915_gem_shmem_pwrite(struct drm_device *dev,
892 struct drm_i915_gem_object *obj,
893 struct drm_i915_gem_pwrite *args,
894 struct drm_file *file)
898 char __user *user_data;
899 int shmem_page_offset, page_length, ret = 0;
900 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
901 int hit_slowpath = 0;
902 int needs_clflush_after = 0;
903 int needs_clflush_before = 0;
904 struct sg_page_iter sg_iter;
906 user_data = to_user_ptr(args->data_ptr);
909 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
911 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
912 /* If we're not in the cpu write domain, set ourself into the gtt
913 * write domain and manually flush cachelines (if required). This
914 * optimizes for the case when the gpu will use the data
915 * right away and we therefore have to clflush anyway. */
916 needs_clflush_after = cpu_write_needs_clflush(obj);
917 ret = i915_gem_object_wait_rendering(obj, false);
921 /* Same trick applies to invalidate partially written cachelines read
923 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
924 needs_clflush_before =
925 !cpu_cache_is_coherent(dev, obj->cache_level);
927 ret = i915_gem_object_get_pages(obj);
931 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
933 i915_gem_object_pin_pages(obj);
935 offset = args->offset;
938 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
939 offset >> PAGE_SHIFT) {
940 struct page *page = sg_page_iter_page(&sg_iter);
941 int partial_cacheline_write;
946 /* Operation in this page
948 * shmem_page_offset = offset within page in shmem file
949 * page_length = bytes to copy for this page
951 shmem_page_offset = offset_in_page(offset);
953 page_length = remain;
954 if ((shmem_page_offset + page_length) > PAGE_SIZE)
955 page_length = PAGE_SIZE - shmem_page_offset;
957 /* If we don't overwrite a cacheline completely we need to be
958 * careful to have up-to-date data by first clflushing. Don't
959 * overcomplicate things and flush the entire patch. */
960 partial_cacheline_write = needs_clflush_before &&
961 ((shmem_page_offset | page_length)
962 & (boot_cpu_data.x86_clflush_size - 1));
964 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
965 (page_to_phys(page) & (1 << 17)) != 0;
967 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
968 user_data, page_do_bit17_swizzling,
969 partial_cacheline_write,
970 needs_clflush_after);
975 mutex_unlock(&dev->struct_mutex);
976 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
977 user_data, page_do_bit17_swizzling,
978 partial_cacheline_write,
979 needs_clflush_after);
981 mutex_lock(&dev->struct_mutex);
987 remain -= page_length;
988 user_data += page_length;
989 offset += page_length;
993 i915_gem_object_unpin_pages(obj);
997 * Fixup: Flush cpu caches in case we didn't flush the dirty
998 * cachelines in-line while writing and the object moved
999 * out of the cpu write domain while we've dropped the lock.
1001 if (!needs_clflush_after &&
1002 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1003 if (i915_gem_clflush_object(obj, obj->pin_display))
1004 needs_clflush_after = true;
1008 if (needs_clflush_after)
1009 i915_gem_chipset_flush(dev);
1011 obj->cache_dirty = true;
1013 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1018 * Writes data to the object referenced by handle.
1020 * On error, the contents of the buffer that were to be modified are undefined.
1023 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1024 struct drm_file *file)
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027 struct drm_i915_gem_pwrite *args = data;
1028 struct drm_i915_gem_object *obj;
1031 if (args->size == 0)
1034 if (!access_ok(VERIFY_READ,
1035 to_user_ptr(args->data_ptr),
1039 if (likely(!i915.prefault_disable)) {
1040 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1046 intel_runtime_pm_get(dev_priv);
1048 ret = i915_mutex_lock_interruptible(dev);
1052 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1053 if (&obj->base == NULL) {
1058 /* Bounds check destination. */
1059 if (args->offset > obj->base.size ||
1060 args->size > obj->base.size - args->offset) {
1065 /* prime objects have no backing filp to GEM pread/pwrite
1068 if (!obj->base.filp) {
1073 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj->tiling_mode == I915_TILING_NONE &&
1083 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1084 cpu_write_needs_clflush(obj)) {
1085 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1086 /* Note that the gtt paths might fail with non-page-backed user
1087 * pointers (e.g. gtt mappings when moving data between
1088 * textures). Fallback to the shmem path in that case. */
1091 if (ret == -EFAULT || ret == -ENOSPC) {
1092 if (obj->phys_handle)
1093 ret = i915_gem_phys_pwrite(obj, args, file);
1095 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1099 drm_gem_object_unreference(&obj->base);
1101 mutex_unlock(&dev->struct_mutex);
1103 intel_runtime_pm_put(dev_priv);
1109 i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
1111 if (__i915_terminally_wedged(reset_counter))
1114 if (__i915_reset_in_progress(reset_counter)) {
1115 /* Non-interruptible callers can't handle -EAGAIN, hence return
1116 * -EIO unconditionally for these. */
1126 static void fake_irq(unsigned long data)
1128 wake_up_process((struct task_struct *)data);
1131 static bool missed_irq(struct drm_i915_private *dev_priv,
1132 struct intel_engine_cs *engine)
1134 return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
1137 static unsigned long local_clock_us(unsigned *cpu)
1141 /* Cheaply and approximately convert from nanoseconds to microseconds.
1142 * The result and subsequent calculations are also defined in the same
1143 * approximate microseconds units. The principal source of timing
1144 * error here is from the simple truncation.
1146 * Note that local_clock() is only defined wrt to the current CPU;
1147 * the comparisons are no longer valid if we switch CPUs. Instead of
1148 * blocking preemption for the entire busywait, we can detect the CPU
1149 * switch and use that as indicator of system load and a reason to
1150 * stop busywaiting, see busywait_stop().
1153 t = local_clock() >> 10;
1159 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1163 if (time_after(local_clock_us(&this_cpu), timeout))
1166 return this_cpu != cpu;
1169 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1171 unsigned long timeout;
1174 /* When waiting for high frequency requests, e.g. during synchronous
1175 * rendering split between the CPU and GPU, the finite amount of time
1176 * required to set up the irq and wait upon it limits the response
1177 * rate. By busywaiting on the request completion for a short while we
1178 * can service the high frequency waits as quick as possible. However,
1179 * if it is a slow request, we want to sleep as quickly as possible.
1180 * The tradeoff between waiting and sleeping is roughly the time it
1181 * takes to sleep on a request, on the order of a microsecond.
1184 if (req->engine->irq_refcount)
1187 /* Only spin if we know the GPU is processing this request */
1188 if (!i915_gem_request_started(req, true))
1191 timeout = local_clock_us(&cpu) + 5;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(req, true))
1196 if (signal_pending_state(state, current))
1199 if (busywait_stop(timeout, cpu))
1202 cpu_relax_lowlatency();
1205 if (i915_gem_request_completed(req, false))
1212 * __i915_wait_request - wait until execution of request has finished
1214 * @interruptible: do an interruptible wait (normally yes)
1215 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1217 * Note: It is of utmost importance that the passed in seqno and reset_counter
1218 * values have been read by the caller in an smp safe manner. Where read-side
1219 * locks are involved, it is sufficient to read the reset_counter before
1220 * unlocking the lock that protects the seqno. For lockless tricks, the
1221 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1224 * Returns 0 if the request was found within the alloted time. Else returns the
1225 * errno with remaining time filled in timeout argument.
1227 int __i915_wait_request(struct drm_i915_gem_request *req,
1230 struct intel_rps_client *rps)
1232 struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1233 struct drm_device *dev = engine->dev;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 const bool irq_test_in_progress =
1236 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
1237 int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1239 unsigned long timeout_expire;
1240 s64 before = 0; /* Only to silence a compiler warning. */
1243 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1245 if (list_empty(&req->list))
1248 if (i915_gem_request_completed(req, true))
1253 if (WARN_ON(*timeout < 0))
1259 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1262 * Record current time in case interrupted by signal, or wedged.
1264 before = ktime_get_raw_ns();
1267 if (INTEL_INFO(dev_priv)->gen >= 6)
1268 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1270 trace_i915_gem_request_wait_begin(req);
1272 /* Optimistic spin for the next jiffie before touching IRQs */
1273 ret = __i915_spin_request(req, state);
1277 if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
1283 struct timer_list timer;
1285 prepare_to_wait(&engine->irq_queue, &wait, state);
1287 /* We need to check whether any gpu reset happened in between
1288 * the request being submitted and now. If a reset has occurred,
1289 * the request is effectively complete (we either are in the
1290 * process of or have discarded the rendering and completely
1291 * reset the GPU. The results of the request are lost and we
1292 * are free to continue on with the original operation.
1294 if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
1299 if (i915_gem_request_completed(req, false)) {
1304 if (signal_pending_state(state, current)) {
1309 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1314 timer.function = NULL;
1315 if (timeout || missed_irq(dev_priv, engine)) {
1316 unsigned long expire;
1318 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1319 expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
1320 mod_timer(&timer, expire);
1325 if (timer.function) {
1326 del_singleshot_timer_sync(&timer);
1327 destroy_timer_on_stack(&timer);
1330 if (!irq_test_in_progress)
1331 engine->irq_put(engine);
1333 finish_wait(&engine->irq_queue, &wait);
1336 trace_i915_gem_request_wait_end(req);
1339 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1341 *timeout = tres < 0 ? 0 : tres;
1344 * Apparently ktime isn't accurate enough and occasionally has a
1345 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1346 * things up to make the test happy. We allow up to 1 jiffy.
1348 * This is a regrssion from the timespec->ktime conversion.
1350 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1357 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1358 struct drm_file *file)
1360 struct drm_i915_file_private *file_priv;
1362 WARN_ON(!req || !file || req->file_priv);
1370 file_priv = file->driver_priv;
1372 spin_lock(&file_priv->mm.lock);
1373 req->file_priv = file_priv;
1374 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1375 spin_unlock(&file_priv->mm.lock);
1377 req->pid = get_pid(task_pid(current));
1383 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1385 struct drm_i915_file_private *file_priv = request->file_priv;
1390 spin_lock(&file_priv->mm.lock);
1391 list_del(&request->client_list);
1392 request->file_priv = NULL;
1393 spin_unlock(&file_priv->mm.lock);
1395 put_pid(request->pid);
1396 request->pid = NULL;
1399 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1401 trace_i915_gem_request_retire(request);
1403 /* We know the GPU must have read the request to have
1404 * sent us the seqno + interrupt, so use the position
1405 * of tail of the request to update the last known position
1408 * Note this requires that we are always called in request
1411 request->ringbuf->last_retired_head = request->postfix;
1413 list_del_init(&request->list);
1414 i915_gem_request_remove_from_client(request);
1416 i915_gem_request_unreference(request);
1420 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1422 struct intel_engine_cs *engine = req->engine;
1423 struct drm_i915_gem_request *tmp;
1425 lockdep_assert_held(&engine->dev->struct_mutex);
1427 if (list_empty(&req->list))
1431 tmp = list_first_entry(&engine->request_list,
1432 typeof(*tmp), list);
1434 i915_gem_request_retire(tmp);
1435 } while (tmp != req);
1437 WARN_ON(i915_verify_lists(engine->dev));
1441 * Waits for a request to be signaled, and cleans up the
1442 * request and object lists appropriately for that event.
1445 i915_wait_request(struct drm_i915_gem_request *req)
1447 struct drm_device *dev;
1448 struct drm_i915_private *dev_priv;
1452 BUG_ON(req == NULL);
1454 dev = req->engine->dev;
1455 dev_priv = dev->dev_private;
1456 interruptible = dev_priv->mm.interruptible;
1458 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1460 ret = __i915_wait_request(req, interruptible, NULL, NULL);
1464 __i915_gem_request_retire__upto(req);
1469 * Ensures that all rendering to the object has completed and the object is
1470 * safe to unbind from the GTT or access from the CPU.
1473 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1482 if (obj->last_write_req != NULL) {
1483 ret = i915_wait_request(obj->last_write_req);
1487 i = obj->last_write_req->engine->id;
1488 if (obj->last_read_req[i] == obj->last_write_req)
1489 i915_gem_object_retire__read(obj, i);
1491 i915_gem_object_retire__write(obj);
1494 for (i = 0; i < I915_NUM_ENGINES; i++) {
1495 if (obj->last_read_req[i] == NULL)
1498 ret = i915_wait_request(obj->last_read_req[i]);
1502 i915_gem_object_retire__read(obj, i);
1504 GEM_BUG_ON(obj->active);
1511 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1512 struct drm_i915_gem_request *req)
1514 int ring = req->engine->id;
1516 if (obj->last_read_req[ring] == req)
1517 i915_gem_object_retire__read(obj, ring);
1518 else if (obj->last_write_req == req)
1519 i915_gem_object_retire__write(obj);
1521 __i915_gem_request_retire__upto(req);
1524 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1525 * as the object state may change during this call.
1527 static __must_check int
1528 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1529 struct intel_rps_client *rps,
1532 struct drm_device *dev = obj->base.dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1537 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1538 BUG_ON(!dev_priv->mm.interruptible);
1544 struct drm_i915_gem_request *req;
1546 req = obj->last_write_req;
1550 requests[n++] = i915_gem_request_reference(req);
1552 for (i = 0; i < I915_NUM_ENGINES; i++) {
1553 struct drm_i915_gem_request *req;
1555 req = obj->last_read_req[i];
1559 requests[n++] = i915_gem_request_reference(req);
1563 mutex_unlock(&dev->struct_mutex);
1565 for (i = 0; ret == 0 && i < n; i++)
1566 ret = __i915_wait_request(requests[i], true, NULL, rps);
1567 mutex_lock(&dev->struct_mutex);
1569 for (i = 0; i < n; i++) {
1571 i915_gem_object_retire_request(obj, requests[i]);
1572 i915_gem_request_unreference(requests[i]);
1578 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1580 struct drm_i915_file_private *fpriv = file->driver_priv;
1585 * Called when user space prepares to use an object with the CPU, either
1586 * through the mmap ioctl's mapping or a GTT mapping.
1589 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1590 struct drm_file *file)
1592 struct drm_i915_gem_set_domain *args = data;
1593 struct drm_i915_gem_object *obj;
1594 uint32_t read_domains = args->read_domains;
1595 uint32_t write_domain = args->write_domain;
1598 /* Only handle setting domains to types used by the CPU. */
1599 if (write_domain & I915_GEM_GPU_DOMAINS)
1602 if (read_domains & I915_GEM_GPU_DOMAINS)
1605 /* Having something in the write domain implies it's in the read
1606 * domain, and only that read domain. Enforce that in the request.
1608 if (write_domain != 0 && read_domains != write_domain)
1611 ret = i915_mutex_lock_interruptible(dev);
1615 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1616 if (&obj->base == NULL) {
1621 /* Try to flush the object off the GPU without holding the lock.
1622 * We will repeat the flush holding the lock in the normal manner
1623 * to catch cases where we are gazumped.
1625 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1626 to_rps_client(file),
1631 if (read_domains & I915_GEM_DOMAIN_GTT)
1632 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1634 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1636 if (write_domain != 0)
1637 intel_fb_obj_invalidate(obj,
1638 write_domain == I915_GEM_DOMAIN_GTT ?
1639 ORIGIN_GTT : ORIGIN_CPU);
1642 drm_gem_object_unreference(&obj->base);
1644 mutex_unlock(&dev->struct_mutex);
1649 * Called when user space has done writes to this buffer
1652 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1653 struct drm_file *file)
1655 struct drm_i915_gem_sw_finish *args = data;
1656 struct drm_i915_gem_object *obj;
1659 ret = i915_mutex_lock_interruptible(dev);
1663 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1664 if (&obj->base == NULL) {
1669 /* Pinned buffers may be scanout, so flush the cache */
1670 if (obj->pin_display)
1671 i915_gem_object_flush_cpu_write_domain(obj);
1673 drm_gem_object_unreference(&obj->base);
1675 mutex_unlock(&dev->struct_mutex);
1680 * Maps the contents of an object, returning the address it is mapped
1683 * While the mapping holds a reference on the contents of the object, it doesn't
1684 * imply a ref on the object itself.
1688 * DRM driver writers who look a this function as an example for how to do GEM
1689 * mmap support, please don't implement mmap support like here. The modern way
1690 * to implement DRM mmap support is with an mmap offset ioctl (like
1691 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1692 * That way debug tooling like valgrind will understand what's going on, hiding
1693 * the mmap call in a driver private ioctl will break that. The i915 driver only
1694 * does cpu mmaps this way because we didn't know better.
1697 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1698 struct drm_file *file)
1700 struct drm_i915_gem_mmap *args = data;
1701 struct drm_gem_object *obj;
1704 if (args->flags & ~(I915_MMAP_WC))
1707 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1710 obj = drm_gem_object_lookup(dev, file, args->handle);
1714 /* prime objects have no backing filp to GEM mmap
1718 drm_gem_object_unreference_unlocked(obj);
1722 addr = vm_mmap(obj->filp, 0, args->size,
1723 PROT_READ | PROT_WRITE, MAP_SHARED,
1725 if (args->flags & I915_MMAP_WC) {
1726 struct mm_struct *mm = current->mm;
1727 struct vm_area_struct *vma;
1729 down_write(&mm->mmap_sem);
1730 vma = find_vma(mm, addr);
1733 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1736 up_write(&mm->mmap_sem);
1738 drm_gem_object_unreference_unlocked(obj);
1739 if (IS_ERR((void *)addr))
1742 args->addr_ptr = (uint64_t) addr;
1748 * i915_gem_fault - fault a page into the GTT
1749 * @vma: VMA in question
1752 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1753 * from userspace. The fault handler takes care of binding the object to
1754 * the GTT (if needed), allocating and programming a fence register (again,
1755 * only if needed based on whether the old reg is still valid or the object
1756 * is tiled) and inserting a new PTE into the faulting process.
1758 * Note that the faulting process may involve evicting existing objects
1759 * from the GTT and/or fence registers to make room. So performance may
1760 * suffer if the GTT working set is large or there are few fence registers
1763 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1765 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1766 struct drm_device *dev = obj->base.dev;
1767 struct drm_i915_private *dev_priv = to_i915(dev);
1768 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1769 struct i915_ggtt_view view = i915_ggtt_view_normal;
1770 pgoff_t page_offset;
1773 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1775 intel_runtime_pm_get(dev_priv);
1777 /* We don't use vmf->pgoff since that has the fake offset */
1778 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1781 ret = i915_mutex_lock_interruptible(dev);
1785 trace_i915_gem_object_fault(obj, page_offset, true, write);
1787 /* Try to flush the object off the GPU first without holding the lock.
1788 * Upon reacquiring the lock, we will perform our sanity checks and then
1789 * repeat the flush holding the lock in the normal manner to catch cases
1790 * where we are gazumped.
1792 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1796 /* Access to snoopable pages through the GTT is incoherent. */
1797 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1802 /* Use a partial view if the object is bigger than the aperture. */
1803 if (obj->base.size >= ggtt->mappable_end &&
1804 obj->tiling_mode == I915_TILING_NONE) {
1805 static const unsigned int chunk_size = 256; // 1 MiB
1807 memset(&view, 0, sizeof(view));
1808 view.type = I915_GGTT_VIEW_PARTIAL;
1809 view.params.partial.offset = rounddown(page_offset, chunk_size);
1810 view.params.partial.size =
1813 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1814 view.params.partial.offset);
1817 /* Now pin it into the GTT if needed */
1818 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1822 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1826 ret = i915_gem_object_get_fence(obj);
1830 /* Finally, remap it using the new GTT offset */
1831 pfn = ggtt->mappable_base +
1832 i915_gem_obj_ggtt_offset_view(obj, &view);
1835 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1836 /* Overriding existing pages in partial view does not cause
1837 * us any trouble as TLBs are still valid because the fault
1838 * is due to userspace losing part of the mapping or never
1839 * having accessed it before (at this partials' range).
1841 unsigned long base = vma->vm_start +
1842 (view.params.partial.offset << PAGE_SHIFT);
1845 for (i = 0; i < view.params.partial.size; i++) {
1846 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1851 obj->fault_mappable = true;
1853 if (!obj->fault_mappable) {
1854 unsigned long size = min_t(unsigned long,
1855 vma->vm_end - vma->vm_start,
1859 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1860 ret = vm_insert_pfn(vma,
1861 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1867 obj->fault_mappable = true;
1869 ret = vm_insert_pfn(vma,
1870 (unsigned long)vmf->virtual_address,
1874 i915_gem_object_ggtt_unpin_view(obj, &view);
1876 mutex_unlock(&dev->struct_mutex);
1881 * We eat errors when the gpu is terminally wedged to avoid
1882 * userspace unduly crashing (gl has no provisions for mmaps to
1883 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1884 * and so needs to be reported.
1886 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1887 ret = VM_FAULT_SIGBUS;
1892 * EAGAIN means the gpu is hung and we'll wait for the error
1893 * handler to reset everything when re-faulting in
1894 * i915_mutex_lock_interruptible.
1901 * EBUSY is ok: this just means that another thread
1902 * already did the job.
1904 ret = VM_FAULT_NOPAGE;
1911 ret = VM_FAULT_SIGBUS;
1914 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1915 ret = VM_FAULT_SIGBUS;
1919 intel_runtime_pm_put(dev_priv);
1924 * i915_gem_release_mmap - remove physical page mappings
1925 * @obj: obj in question
1927 * Preserve the reservation of the mmapping with the DRM core code, but
1928 * relinquish ownership of the pages back to the system.
1930 * It is vital that we remove the page mapping if we have mapped a tiled
1931 * object through the GTT and then lose the fence register due to
1932 * resource pressure. Similarly if the object has been moved out of the
1933 * aperture, than pages mapped into userspace must be revoked. Removing the
1934 * mapping will then trigger a page fault on the next user access, allowing
1935 * fixup by i915_gem_fault().
1938 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1940 /* Serialisation between user GTT access and our code depends upon
1941 * revoking the CPU's PTE whilst the mutex is held. The next user
1942 * pagefault then has to wait until we release the mutex.
1944 lockdep_assert_held(&obj->base.dev->struct_mutex);
1946 if (!obj->fault_mappable)
1949 drm_vma_node_unmap(&obj->base.vma_node,
1950 obj->base.dev->anon_inode->i_mapping);
1952 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1953 * memory transactions from userspace before we return. The TLB
1954 * flushing implied above by changing the PTE above *should* be
1955 * sufficient, an extra barrier here just provides us with a bit
1956 * of paranoid documentation about our requirement to serialise
1957 * memory writes before touching registers / GSM.
1961 obj->fault_mappable = false;
1965 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1967 struct drm_i915_gem_object *obj;
1969 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1970 i915_gem_release_mmap(obj);
1974 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1978 if (INTEL_INFO(dev)->gen >= 4 ||
1979 tiling_mode == I915_TILING_NONE)
1982 /* Previous chips need a power-of-two fence region when tiling */
1983 if (INTEL_INFO(dev)->gen == 3)
1984 gtt_size = 1024*1024;
1986 gtt_size = 512*1024;
1988 while (gtt_size < size)
1995 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1996 * @obj: object to check
1998 * Return the required GTT alignment for an object, taking into account
1999 * potential fence register mapping.
2002 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2003 int tiling_mode, bool fenced)
2006 * Minimum alignment is 4k (GTT page size), but might be greater
2007 * if a fence register is needed for the object.
2009 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2010 tiling_mode == I915_TILING_NONE)
2014 * Previous chips need to be aligned to the size of the smallest
2015 * fence register that can contain the object.
2017 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2020 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2022 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2025 if (drm_vma_node_has_offset(&obj->base.vma_node))
2028 dev_priv->mm.shrinker_no_lock_stealing = true;
2030 ret = drm_gem_create_mmap_offset(&obj->base);
2034 /* Badly fragmented mmap space? The only way we can recover
2035 * space is by destroying unwanted objects. We can't randomly release
2036 * mmap_offsets as userspace expects them to be persistent for the
2037 * lifetime of the objects. The closest we can is to release the
2038 * offsets on purgeable objects by truncating it and marking it purged,
2039 * which prevents userspace from ever using that object again.
2041 i915_gem_shrink(dev_priv,
2042 obj->base.size >> PAGE_SHIFT,
2044 I915_SHRINK_UNBOUND |
2045 I915_SHRINK_PURGEABLE);
2046 ret = drm_gem_create_mmap_offset(&obj->base);
2050 i915_gem_shrink_all(dev_priv);
2051 ret = drm_gem_create_mmap_offset(&obj->base);
2053 dev_priv->mm.shrinker_no_lock_stealing = false;
2058 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2060 drm_gem_free_mmap_offset(&obj->base);
2064 i915_gem_mmap_gtt(struct drm_file *file,
2065 struct drm_device *dev,
2069 struct drm_i915_gem_object *obj;
2072 ret = i915_mutex_lock_interruptible(dev);
2076 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2077 if (&obj->base == NULL) {
2082 if (obj->madv != I915_MADV_WILLNEED) {
2083 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2088 ret = i915_gem_object_create_mmap_offset(obj);
2092 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2095 drm_gem_object_unreference(&obj->base);
2097 mutex_unlock(&dev->struct_mutex);
2102 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2104 * @data: GTT mapping ioctl data
2105 * @file: GEM object info
2107 * Simply returns the fake offset to userspace so it can mmap it.
2108 * The mmap call will end up in drm_gem_mmap(), which will set things
2109 * up so we can get faults in the handler above.
2111 * The fault handler will take care of binding the object into the GTT
2112 * (since it may have been evicted to make room for something), allocating
2113 * a fence register, and mapping the appropriate aperture address into
2117 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2118 struct drm_file *file)
2120 struct drm_i915_gem_mmap_gtt *args = data;
2122 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2125 /* Immediately discard the backing storage */
2127 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2129 i915_gem_object_free_mmap_offset(obj);
2131 if (obj->base.filp == NULL)
2134 /* Our goal here is to return as much of the memory as
2135 * is possible back to the system as we are called from OOM.
2136 * To do this we must instruct the shmfs to drop all of its
2137 * backing pages, *now*.
2139 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2140 obj->madv = __I915_MADV_PURGED;
2143 /* Try to discard unwanted pages */
2145 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2147 struct address_space *mapping;
2149 switch (obj->madv) {
2150 case I915_MADV_DONTNEED:
2151 i915_gem_object_truncate(obj);
2152 case __I915_MADV_PURGED:
2156 if (obj->base.filp == NULL)
2159 mapping = file_inode(obj->base.filp)->i_mapping,
2160 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2164 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2166 struct sg_page_iter sg_iter;
2169 BUG_ON(obj->madv == __I915_MADV_PURGED);
2171 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2173 /* In the event of a disaster, abandon all caches and
2174 * hope for the best.
2176 i915_gem_clflush_object(obj, true);
2177 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2180 i915_gem_gtt_finish_object(obj);
2182 if (i915_gem_object_needs_bit17_swizzle(obj))
2183 i915_gem_object_save_bit_17_swizzle(obj);
2185 if (obj->madv == I915_MADV_DONTNEED)
2188 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2189 struct page *page = sg_page_iter_page(&sg_iter);
2192 set_page_dirty(page);
2194 if (obj->madv == I915_MADV_WILLNEED)
2195 mark_page_accessed(page);
2201 sg_free_table(obj->pages);
2206 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2208 const struct drm_i915_gem_object_ops *ops = obj->ops;
2210 if (obj->pages == NULL)
2213 if (obj->pages_pin_count)
2216 BUG_ON(i915_gem_obj_bound_any(obj));
2218 /* ->put_pages might need to allocate memory for the bit17 swizzle
2219 * array, hence protect them from being reaped by removing them from gtt
2221 list_del(&obj->global_list);
2224 if (is_vmalloc_addr(obj->mapping))
2225 vunmap(obj->mapping);
2227 kunmap(kmap_to_page(obj->mapping));
2228 obj->mapping = NULL;
2231 ops->put_pages(obj);
2234 i915_gem_object_invalidate(obj);
2240 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2242 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2244 struct address_space *mapping;
2245 struct sg_table *st;
2246 struct scatterlist *sg;
2247 struct sg_page_iter sg_iter;
2249 unsigned long last_pfn = 0; /* suppress gcc warning */
2253 /* Assert that the object is not currently in any GPU domain. As it
2254 * wasn't in the GTT, there shouldn't be any way it could have been in
2257 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2258 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2260 st = kmalloc(sizeof(*st), GFP_KERNEL);
2264 page_count = obj->base.size / PAGE_SIZE;
2265 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2270 /* Get the list of pages out of our struct file. They'll be pinned
2271 * at this point until we release them.
2273 * Fail silently without starting the shrinker
2275 mapping = file_inode(obj->base.filp)->i_mapping;
2276 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2277 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2280 for (i = 0; i < page_count; i++) {
2281 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2283 i915_gem_shrink(dev_priv,
2286 I915_SHRINK_UNBOUND |
2287 I915_SHRINK_PURGEABLE);
2288 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2291 /* We've tried hard to allocate the memory by reaping
2292 * our own buffer, now let the real VM do its job and
2293 * go down in flames if truly OOM.
2295 i915_gem_shrink_all(dev_priv);
2296 page = shmem_read_mapping_page(mapping, i);
2298 ret = PTR_ERR(page);
2302 #ifdef CONFIG_SWIOTLB
2303 if (swiotlb_nr_tbl()) {
2305 sg_set_page(sg, page, PAGE_SIZE, 0);
2310 if (!i || page_to_pfn(page) != last_pfn + 1) {
2314 sg_set_page(sg, page, PAGE_SIZE, 0);
2316 sg->length += PAGE_SIZE;
2318 last_pfn = page_to_pfn(page);
2320 /* Check that the i965g/gm workaround works. */
2321 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2323 #ifdef CONFIG_SWIOTLB
2324 if (!swiotlb_nr_tbl())
2329 ret = i915_gem_gtt_prepare_object(obj);
2333 if (i915_gem_object_needs_bit17_swizzle(obj))
2334 i915_gem_object_do_bit_17_swizzle(obj);
2336 if (obj->tiling_mode != I915_TILING_NONE &&
2337 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2338 i915_gem_object_pin_pages(obj);
2344 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2345 put_page(sg_page_iter_page(&sg_iter));
2349 /* shmemfs first checks if there is enough memory to allocate the page
2350 * and reports ENOSPC should there be insufficient, along with the usual
2351 * ENOMEM for a genuine allocation failure.
2353 * We use ENOSPC in our driver to mean that we have run out of aperture
2354 * space and so want to translate the error from shmemfs back to our
2355 * usual understanding of ENOMEM.
2363 /* Ensure that the associated pages are gathered from the backing storage
2364 * and pinned into our object. i915_gem_object_get_pages() may be called
2365 * multiple times before they are released by a single call to
2366 * i915_gem_object_put_pages() - once the pages are no longer referenced
2367 * either as a result of memory pressure (reaping pages under the shrinker)
2368 * or as the object is itself released.
2371 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2373 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2374 const struct drm_i915_gem_object_ops *ops = obj->ops;
2380 if (obj->madv != I915_MADV_WILLNEED) {
2381 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2385 BUG_ON(obj->pages_pin_count);
2387 ret = ops->get_pages(obj);
2391 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2393 obj->get_page.sg = obj->pages->sgl;
2394 obj->get_page.last = 0;
2399 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2403 lockdep_assert_held(&obj->base.dev->struct_mutex);
2405 ret = i915_gem_object_get_pages(obj);
2407 return ERR_PTR(ret);
2409 i915_gem_object_pin_pages(obj);
2411 if (obj->mapping == NULL) {
2412 struct page **pages;
2415 if (obj->base.size == PAGE_SIZE)
2416 obj->mapping = kmap(sg_page(obj->pages->sgl));
2418 pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT,
2421 if (pages != NULL) {
2422 struct sg_page_iter sg_iter;
2426 for_each_sg_page(obj->pages->sgl, &sg_iter,
2427 obj->pages->nents, 0)
2428 pages[n++] = sg_page_iter_page(&sg_iter);
2430 obj->mapping = vmap(pages, n, 0, PAGE_KERNEL);
2431 drm_free_large(pages);
2433 if (obj->mapping == NULL) {
2434 i915_gem_object_unpin_pages(obj);
2435 return ERR_PTR(-ENOMEM);
2439 return obj->mapping;
2442 void i915_vma_move_to_active(struct i915_vma *vma,
2443 struct drm_i915_gem_request *req)
2445 struct drm_i915_gem_object *obj = vma->obj;
2446 struct intel_engine_cs *engine;
2448 engine = i915_gem_request_get_engine(req);
2450 /* Add a reference if we're newly entering the active list. */
2451 if (obj->active == 0)
2452 drm_gem_object_reference(&obj->base);
2453 obj->active |= intel_engine_flag(engine);
2455 list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2456 i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2458 list_move_tail(&vma->vm_link, &vma->vm->active_list);
2462 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2464 GEM_BUG_ON(obj->last_write_req == NULL);
2465 GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2467 i915_gem_request_assign(&obj->last_write_req, NULL);
2468 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2472 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2474 struct i915_vma *vma;
2476 GEM_BUG_ON(obj->last_read_req[ring] == NULL);
2477 GEM_BUG_ON(!(obj->active & (1 << ring)));
2479 list_del_init(&obj->engine_list[ring]);
2480 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2482 if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2483 i915_gem_object_retire__write(obj);
2485 obj->active &= ~(1 << ring);
2489 /* Bump our place on the bound list to keep it roughly in LRU order
2490 * so that we don't steal from recently used but inactive objects
2491 * (unless we are forced to ofc!)
2493 list_move_tail(&obj->global_list,
2494 &to_i915(obj->base.dev)->mm.bound_list);
2496 list_for_each_entry(vma, &obj->vma_list, obj_link) {
2497 if (!list_empty(&vma->vm_link))
2498 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2501 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2502 drm_gem_object_unreference(&obj->base);
2506 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 struct intel_engine_cs *engine;
2512 /* Carefully retire all requests without writing to the rings */
2513 for_each_engine(engine, dev_priv) {
2514 ret = intel_engine_idle(engine);
2518 i915_gem_retire_requests(dev);
2520 /* Finally reset hw state */
2521 for_each_engine(engine, dev_priv)
2522 intel_ring_init_seqno(engine, seqno);
2527 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2535 /* HWS page needs to be set less than what we
2536 * will inject to ring
2538 ret = i915_gem_init_seqno(dev, seqno - 1);
2542 /* Carefully set the last_seqno value so that wrap
2543 * detection still works
2545 dev_priv->next_seqno = seqno;
2546 dev_priv->last_seqno = seqno - 1;
2547 if (dev_priv->last_seqno == 0)
2548 dev_priv->last_seqno--;
2554 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2558 /* reserve 0 for non-seqno */
2559 if (dev_priv->next_seqno == 0) {
2560 int ret = i915_gem_init_seqno(dev, 0);
2564 dev_priv->next_seqno = 1;
2567 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2572 * NB: This function is not allowed to fail. Doing so would mean the the
2573 * request is not being tracked for completion but the work itself is
2574 * going to happen on the hardware. This would be a Bad Thing(tm).
2576 void __i915_add_request(struct drm_i915_gem_request *request,
2577 struct drm_i915_gem_object *obj,
2580 struct intel_engine_cs *engine;
2581 struct drm_i915_private *dev_priv;
2582 struct intel_ringbuffer *ringbuf;
2586 if (WARN_ON(request == NULL))
2589 engine = request->engine;
2590 dev_priv = request->i915;
2591 ringbuf = request->ringbuf;
2594 * To ensure that this call will not fail, space for its emissions
2595 * should already have been reserved in the ring buffer. Let the ring
2596 * know that it is time to use that space up.
2598 intel_ring_reserved_space_use(ringbuf);
2600 request_start = intel_ring_get_tail(ringbuf);
2602 * Emit any outstanding flushes - execbuf can fail to emit the flush
2603 * after having emitted the batchbuffer command. Hence we need to fix
2604 * things up similar to emitting the lazy request. The difference here
2605 * is that the flush _must_ happen before the next request, no matter
2609 if (i915.enable_execlists)
2610 ret = logical_ring_flush_all_caches(request);
2612 ret = intel_ring_flush_all_caches(request);
2613 /* Not allowed to fail! */
2614 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2617 trace_i915_gem_request_add(request);
2619 request->head = request_start;
2621 /* Whilst this request exists, batch_obj will be on the
2622 * active_list, and so will hold the active reference. Only when this
2623 * request is retired will the the batch_obj be moved onto the
2624 * inactive_list and lose its active reference. Hence we do not need
2625 * to explicitly hold another reference here.
2627 request->batch_obj = obj;
2629 /* Seal the request and mark it as pending execution. Note that
2630 * we may inspect this state, without holding any locks, during
2631 * hangcheck. Hence we apply the barrier to ensure that we do not
2632 * see a more recent value in the hws than we are tracking.
2634 request->emitted_jiffies = jiffies;
2635 request->previous_seqno = engine->last_submitted_seqno;
2636 smp_store_mb(engine->last_submitted_seqno, request->seqno);
2637 list_add_tail(&request->list, &engine->request_list);
2639 /* Record the position of the start of the request so that
2640 * should we detect the updated seqno part-way through the
2641 * GPU processing the request, we never over-estimate the
2642 * position of the head.
2644 request->postfix = intel_ring_get_tail(ringbuf);
2646 if (i915.enable_execlists)
2647 ret = engine->emit_request(request);
2649 ret = engine->add_request(request);
2651 request->tail = intel_ring_get_tail(ringbuf);
2653 /* Not allowed to fail! */
2654 WARN(ret, "emit|add_request failed: %d!\n", ret);
2656 i915_queue_hangcheck(engine->dev);
2658 queue_delayed_work(dev_priv->wq,
2659 &dev_priv->mm.retire_work,
2660 round_jiffies_up_relative(HZ));
2661 intel_mark_busy(dev_priv->dev);
2663 /* Sanity check that the reserved size was large enough. */
2664 intel_ring_reserved_space_end(ringbuf);
2667 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2668 const struct intel_context *ctx)
2670 unsigned long elapsed;
2672 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2674 if (ctx->hang_stats.banned)
2677 if (ctx->hang_stats.ban_period_seconds &&
2678 elapsed <= ctx->hang_stats.ban_period_seconds) {
2679 if (!i915_gem_context_is_default(ctx)) {
2680 DRM_DEBUG("context hanging too fast, banning!\n");
2682 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2683 if (i915_stop_ring_allow_warn(dev_priv))
2684 DRM_ERROR("gpu hanging too fast, banning!\n");
2692 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2693 struct intel_context *ctx,
2696 struct i915_ctx_hang_stats *hs;
2701 hs = &ctx->hang_stats;
2704 hs->banned = i915_context_is_banned(dev_priv, ctx);
2706 hs->guilty_ts = get_seconds();
2708 hs->batch_pending++;
2712 void i915_gem_request_free(struct kref *req_ref)
2714 struct drm_i915_gem_request *req = container_of(req_ref,
2716 struct intel_context *ctx = req->ctx;
2719 i915_gem_request_remove_from_client(req);
2722 if (i915.enable_execlists && ctx != req->i915->kernel_context)
2723 intel_lr_context_unpin(ctx, req->engine);
2725 i915_gem_context_unreference(ctx);
2728 kmem_cache_free(req->i915->requests, req);
2732 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2733 struct intel_context *ctx,
2734 struct drm_i915_gem_request **req_out)
2736 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2737 unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
2738 struct drm_i915_gem_request *req;
2746 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2747 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2750 ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
2754 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2758 ret = i915_gem_get_seqno(engine->dev, &req->seqno);
2762 kref_init(&req->ref);
2763 req->i915 = dev_priv;
2764 req->engine = engine;
2765 req->reset_counter = reset_counter;
2767 i915_gem_context_reference(req->ctx);
2769 if (i915.enable_execlists)
2770 ret = intel_logical_ring_alloc_request_extras(req);
2772 ret = intel_ring_alloc_request_extras(req);
2774 i915_gem_context_unreference(req->ctx);
2779 * Reserve space in the ring buffer for all the commands required to
2780 * eventually emit this request. This is to guarantee that the
2781 * i915_add_request() call can't fail. Note that the reserve may need
2782 * to be redone if the request is not actually submitted straight
2783 * away, e.g. because a GPU scheduler has deferred it.
2785 if (i915.enable_execlists)
2786 ret = intel_logical_ring_reserve_space(req);
2788 ret = intel_ring_reserve_space(req);
2791 * At this point, the request is fully allocated even if not
2792 * fully prepared. Thus it can be cleaned up using the proper
2795 intel_ring_reserved_space_cancel(req->ringbuf);
2796 i915_gem_request_unreference(req);
2804 kmem_cache_free(dev_priv->requests, req);
2809 * i915_gem_request_alloc - allocate a request structure
2811 * @engine: engine that we wish to issue the request on.
2812 * @ctx: context that the request will be associated with.
2813 * This can be NULL if the request is not directly related to
2814 * any specific user context, in which case this function will
2815 * choose an appropriate context to use.
2817 * Returns a pointer to the allocated request if successful,
2818 * or an error code if not.
2820 struct drm_i915_gem_request *
2821 i915_gem_request_alloc(struct intel_engine_cs *engine,
2822 struct intel_context *ctx)
2824 struct drm_i915_gem_request *req;
2828 ctx = to_i915(engine->dev)->kernel_context;
2829 err = __i915_gem_request_alloc(engine, ctx, &req);
2830 return err ? ERR_PTR(err) : req;
2833 struct drm_i915_gem_request *
2834 i915_gem_find_active_request(struct intel_engine_cs *engine)
2836 struct drm_i915_gem_request *request;
2838 list_for_each_entry(request, &engine->request_list, list) {
2839 if (i915_gem_request_completed(request, false))
2848 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
2849 struct intel_engine_cs *engine)
2851 struct drm_i915_gem_request *request;
2854 request = i915_gem_find_active_request(engine);
2856 if (request == NULL)
2859 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2861 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2863 list_for_each_entry_continue(request, &engine->request_list, list)
2864 i915_set_reset_status(dev_priv, request->ctx, false);
2867 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
2868 struct intel_engine_cs *engine)
2870 struct intel_ringbuffer *buffer;
2872 while (!list_empty(&engine->active_list)) {
2873 struct drm_i915_gem_object *obj;
2875 obj = list_first_entry(&engine->active_list,
2876 struct drm_i915_gem_object,
2877 engine_list[engine->id]);
2879 i915_gem_object_retire__read(obj, engine->id);
2883 * Clear the execlists queue up before freeing the requests, as those
2884 * are the ones that keep the context and ringbuffer backing objects
2888 if (i915.enable_execlists) {
2889 /* Ensure irq handler finishes or is cancelled. */
2890 tasklet_kill(&engine->irq_tasklet);
2892 spin_lock_bh(&engine->execlist_lock);
2893 /* list_splice_tail_init checks for empty lists */
2894 list_splice_tail_init(&engine->execlist_queue,
2895 &engine->execlist_retired_req_list);
2896 spin_unlock_bh(&engine->execlist_lock);
2898 intel_execlists_retire_requests(engine);
2902 * We must free the requests after all the corresponding objects have
2903 * been moved off active lists. Which is the same order as the normal
2904 * retire_requests function does. This is important if object hold
2905 * implicit references on things like e.g. ppgtt address spaces through
2908 while (!list_empty(&engine->request_list)) {
2909 struct drm_i915_gem_request *request;
2911 request = list_first_entry(&engine->request_list,
2912 struct drm_i915_gem_request,
2915 i915_gem_request_retire(request);
2918 /* Having flushed all requests from all queues, we know that all
2919 * ringbuffers must now be empty. However, since we do not reclaim
2920 * all space when retiring the request (to prevent HEADs colliding
2921 * with rapid ringbuffer wraparound) the amount of available space
2922 * upon reset is less than when we start. Do one more pass over
2923 * all the ringbuffers to reset last_retired_head.
2925 list_for_each_entry(buffer, &engine->buffers, link) {
2926 buffer->last_retired_head = buffer->tail;
2927 intel_ring_update_space(buffer);
2930 intel_ring_init_seqno(engine, engine->last_submitted_seqno);
2933 void i915_gem_reset(struct drm_device *dev)
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct intel_engine_cs *engine;
2939 * Before we free the objects from the requests, we need to inspect
2940 * them for finding the guilty party. As the requests only borrow
2941 * their reference to the objects, the inspection must be done first.
2943 for_each_engine(engine, dev_priv)
2944 i915_gem_reset_engine_status(dev_priv, engine);
2946 for_each_engine(engine, dev_priv)
2947 i915_gem_reset_engine_cleanup(dev_priv, engine);
2949 i915_gem_context_reset(dev);
2951 i915_gem_restore_fences(dev);
2953 WARN_ON(i915_verify_lists(dev));
2957 * This function clears the request list as sequence numbers are passed.
2960 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
2962 WARN_ON(i915_verify_lists(engine->dev));
2964 /* Retire requests first as we use it above for the early return.
2965 * If we retire requests last, we may use a later seqno and so clear
2966 * the requests lists without clearing the active list, leading to
2969 while (!list_empty(&engine->request_list)) {
2970 struct drm_i915_gem_request *request;
2972 request = list_first_entry(&engine->request_list,
2973 struct drm_i915_gem_request,
2976 if (!i915_gem_request_completed(request, true))
2979 i915_gem_request_retire(request);
2982 /* Move any buffers on the active list that are no longer referenced
2983 * by the ringbuffer to the flushing/inactive lists as appropriate,
2984 * before we free the context associated with the requests.
2986 while (!list_empty(&engine->active_list)) {
2987 struct drm_i915_gem_object *obj;
2989 obj = list_first_entry(&engine->active_list,
2990 struct drm_i915_gem_object,
2991 engine_list[engine->id]);
2993 if (!list_empty(&obj->last_read_req[engine->id]->list))
2996 i915_gem_object_retire__read(obj, engine->id);
2999 if (unlikely(engine->trace_irq_req &&
3000 i915_gem_request_completed(engine->trace_irq_req, true))) {
3001 engine->irq_put(engine);
3002 i915_gem_request_assign(&engine->trace_irq_req, NULL);
3005 WARN_ON(i915_verify_lists(engine->dev));
3009 i915_gem_retire_requests(struct drm_device *dev)
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_engine_cs *engine;
3015 for_each_engine(engine, dev_priv) {
3016 i915_gem_retire_requests_ring(engine);
3017 idle &= list_empty(&engine->request_list);
3018 if (i915.enable_execlists) {
3019 spin_lock_bh(&engine->execlist_lock);
3020 idle &= list_empty(&engine->execlist_queue);
3021 spin_unlock_bh(&engine->execlist_lock);
3023 intel_execlists_retire_requests(engine);
3028 mod_delayed_work(dev_priv->wq,
3029 &dev_priv->mm.idle_work,
3030 msecs_to_jiffies(100));
3036 i915_gem_retire_work_handler(struct work_struct *work)
3038 struct drm_i915_private *dev_priv =
3039 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3040 struct drm_device *dev = dev_priv->dev;
3043 /* Come back later if the device is busy... */
3045 if (mutex_trylock(&dev->struct_mutex)) {
3046 idle = i915_gem_retire_requests(dev);
3047 mutex_unlock(&dev->struct_mutex);
3050 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3051 round_jiffies_up_relative(HZ));
3055 i915_gem_idle_work_handler(struct work_struct *work)
3057 struct drm_i915_private *dev_priv =
3058 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3059 struct drm_device *dev = dev_priv->dev;
3060 struct intel_engine_cs *engine;
3062 for_each_engine(engine, dev_priv)
3063 if (!list_empty(&engine->request_list))
3066 /* we probably should sync with hangcheck here, using cancel_work_sync.
3067 * Also locking seems to be fubar here, engine->request_list is protected
3068 * by dev->struct_mutex. */
3070 intel_mark_idle(dev);
3072 if (mutex_trylock(&dev->struct_mutex)) {
3073 for_each_engine(engine, dev_priv)
3074 i915_gem_batch_pool_fini(&engine->batch_pool);
3076 mutex_unlock(&dev->struct_mutex);
3081 * Ensures that an object will eventually get non-busy by flushing any required
3082 * write domains, emitting any outstanding lazy request and retiring and
3083 * completed requests.
3086 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3093 for (i = 0; i < I915_NUM_ENGINES; i++) {
3094 struct drm_i915_gem_request *req;
3096 req = obj->last_read_req[i];
3100 if (list_empty(&req->list))
3103 if (i915_gem_request_completed(req, true)) {
3104 __i915_gem_request_retire__upto(req);
3106 i915_gem_object_retire__read(obj, i);
3114 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3115 * @DRM_IOCTL_ARGS: standard ioctl arguments
3117 * Returns 0 if successful, else an error is returned with the remaining time in
3118 * the timeout parameter.
3119 * -ETIME: object is still busy after timeout
3120 * -ERESTARTSYS: signal interrupted the wait
3121 * -ENONENT: object doesn't exist
3122 * Also possible, but rare:
3123 * -EAGAIN: GPU wedged
3125 * -ENODEV: Internal IRQ fail
3126 * -E?: The add request failed
3128 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3129 * non-zero timeout parameter the wait ioctl will wait for the given number of
3130 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3131 * without holding struct_mutex the object may become re-busied before this
3132 * function completes. A similar but shorter * race condition exists in the busy
3136 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3138 struct drm_i915_gem_wait *args = data;
3139 struct drm_i915_gem_object *obj;
3140 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3144 if (args->flags != 0)
3147 ret = i915_mutex_lock_interruptible(dev);
3151 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3152 if (&obj->base == NULL) {
3153 mutex_unlock(&dev->struct_mutex);
3157 /* Need to make sure the object gets inactive eventually. */
3158 ret = i915_gem_object_flush_active(obj);
3165 /* Do this after OLR check to make sure we make forward progress polling
3166 * on this IOCTL with a timeout == 0 (like busy ioctl)
3168 if (args->timeout_ns == 0) {
3173 drm_gem_object_unreference(&obj->base);
3175 for (i = 0; i < I915_NUM_ENGINES; i++) {
3176 if (obj->last_read_req[i] == NULL)
3179 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3182 mutex_unlock(&dev->struct_mutex);
3184 for (i = 0; i < n; i++) {
3186 ret = __i915_wait_request(req[i], true,
3187 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3188 to_rps_client(file));
3189 i915_gem_request_unreference__unlocked(req[i]);
3194 drm_gem_object_unreference(&obj->base);
3195 mutex_unlock(&dev->struct_mutex);
3200 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3201 struct intel_engine_cs *to,
3202 struct drm_i915_gem_request *from_req,
3203 struct drm_i915_gem_request **to_req)
3205 struct intel_engine_cs *from;
3208 from = i915_gem_request_get_engine(from_req);
3212 if (i915_gem_request_completed(from_req, true))
3215 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3216 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3217 ret = __i915_wait_request(from_req,
3218 i915->mm.interruptible,
3220 &i915->rps.semaphores);
3224 i915_gem_object_retire_request(obj, from_req);
3226 int idx = intel_ring_sync_index(from, to);
3227 u32 seqno = i915_gem_request_get_seqno(from_req);
3231 if (seqno <= from->semaphore.sync_seqno[idx])
3234 if (*to_req == NULL) {
3235 struct drm_i915_gem_request *req;
3237 req = i915_gem_request_alloc(to, NULL);
3239 return PTR_ERR(req);
3244 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3245 ret = to->semaphore.sync_to(*to_req, from, seqno);
3249 /* We use last_read_req because sync_to()
3250 * might have just caused seqno wrap under
3253 from->semaphore.sync_seqno[idx] =
3254 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3261 * i915_gem_object_sync - sync an object to a ring.
3263 * @obj: object which may be in use on another ring.
3264 * @to: ring we wish to use the object on. May be NULL.
3265 * @to_req: request we wish to use the object for. See below.
3266 * This will be allocated and returned if a request is
3267 * required but not passed in.
3269 * This code is meant to abstract object synchronization with the GPU.
3270 * Calling with NULL implies synchronizing the object with the CPU
3271 * rather than a particular GPU ring. Conceptually we serialise writes
3272 * between engines inside the GPU. We only allow one engine to write
3273 * into a buffer at any time, but multiple readers. To ensure each has
3274 * a coherent view of memory, we must:
3276 * - If there is an outstanding write request to the object, the new
3277 * request must wait for it to complete (either CPU or in hw, requests
3278 * on the same ring will be naturally ordered).
3280 * - If we are a write request (pending_write_domain is set), the new
3281 * request must wait for outstanding read requests to complete.
3283 * For CPU synchronisation (NULL to) no request is required. For syncing with
3284 * rings to_req must be non-NULL. However, a request does not have to be
3285 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3286 * request will be allocated automatically and returned through *to_req. Note
3287 * that it is not guaranteed that commands will be emitted (because the system
3288 * might already be idle). Hence there is no need to create a request that
3289 * might never have any work submitted. Note further that if a request is
3290 * returned in *to_req, it is the responsibility of the caller to submit
3291 * that request (after potentially adding more work to it).
3293 * Returns 0 if successful, else propagates up the lower layer error.
3296 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3297 struct intel_engine_cs *to,
3298 struct drm_i915_gem_request **to_req)
3300 const bool readonly = obj->base.pending_write_domain == 0;
3301 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3308 return i915_gem_object_wait_rendering(obj, readonly);
3312 if (obj->last_write_req)
3313 req[n++] = obj->last_write_req;
3315 for (i = 0; i < I915_NUM_ENGINES; i++)
3316 if (obj->last_read_req[i])
3317 req[n++] = obj->last_read_req[i];
3319 for (i = 0; i < n; i++) {
3320 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3328 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3330 u32 old_write_domain, old_read_domains;
3332 /* Force a pagefault for domain tracking on next user access */
3333 i915_gem_release_mmap(obj);
3335 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3338 old_read_domains = obj->base.read_domains;
3339 old_write_domain = obj->base.write_domain;
3341 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3342 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3344 trace_i915_gem_object_change_domain(obj,
3349 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3351 struct drm_i915_gem_object *obj = vma->obj;
3352 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3355 if (list_empty(&vma->obj_link))
3358 if (!drm_mm_node_allocated(&vma->node)) {
3359 i915_gem_vma_destroy(vma);
3366 BUG_ON(obj->pages == NULL);
3369 ret = i915_gem_object_wait_rendering(obj, false);
3374 if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3375 i915_gem_object_finish_gtt(obj);
3377 /* release the fence reg _after_ flushing */
3378 ret = i915_gem_object_put_fence(obj);
3383 trace_i915_vma_unbind(vma);
3385 vma->vm->unbind_vma(vma);
3388 list_del_init(&vma->vm_link);
3390 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3391 obj->map_and_fenceable = false;
3392 } else if (vma->ggtt_view.pages) {
3393 sg_free_table(vma->ggtt_view.pages);
3394 kfree(vma->ggtt_view.pages);
3396 vma->ggtt_view.pages = NULL;
3399 drm_mm_remove_node(&vma->node);
3400 i915_gem_vma_destroy(vma);
3402 /* Since the unbound list is global, only move to that list if
3403 * no more VMAs exist. */
3404 if (list_empty(&obj->vma_list))
3405 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3407 /* And finally now the object is completely decoupled from this vma,
3408 * we can drop its hold on the backing storage and allow it to be
3409 * reaped by the shrinker.
3411 i915_gem_object_unpin_pages(obj);
3416 int i915_vma_unbind(struct i915_vma *vma)
3418 return __i915_vma_unbind(vma, true);
3421 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3423 return __i915_vma_unbind(vma, false);
3426 int i915_gpu_idle(struct drm_device *dev)
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 struct intel_engine_cs *engine;
3432 /* Flush everything onto the inactive list. */
3433 for_each_engine(engine, dev_priv) {
3434 if (!i915.enable_execlists) {
3435 struct drm_i915_gem_request *req;
3437 req = i915_gem_request_alloc(engine, NULL);
3439 return PTR_ERR(req);
3441 ret = i915_switch_context(req);
3442 i915_add_request_no_flush(req);
3447 ret = intel_engine_idle(engine);
3452 WARN_ON(i915_verify_lists(dev));
3456 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3457 unsigned long cache_level)
3459 struct drm_mm_node *gtt_space = &vma->node;
3460 struct drm_mm_node *other;
3463 * On some machines we have to be careful when putting differing types
3464 * of snoopable memory together to avoid the prefetcher crossing memory
3465 * domains and dying. During vm initialisation, we decide whether or not
3466 * these constraints apply and set the drm_mm.color_adjust
3469 if (vma->vm->mm.color_adjust == NULL)
3472 if (!drm_mm_node_allocated(gtt_space))
3475 if (list_empty(>t_space->node_list))
3478 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3479 if (other->allocated && !other->hole_follows && other->color != cache_level)
3482 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3483 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3490 * Finds free space in the GTT aperture and binds the object or a view of it
3493 static struct i915_vma *
3494 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3495 struct i915_address_space *vm,
3496 const struct i915_ggtt_view *ggtt_view,
3500 struct drm_device *dev = obj->base.dev;
3501 struct drm_i915_private *dev_priv = to_i915(dev);
3502 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3503 u32 fence_alignment, unfenced_alignment;
3504 u32 search_flag, alloc_flag;
3506 u64 size, fence_size;
3507 struct i915_vma *vma;
3510 if (i915_is_ggtt(vm)) {
3513 if (WARN_ON(!ggtt_view))
3514 return ERR_PTR(-EINVAL);
3516 view_size = i915_ggtt_view_size(obj, ggtt_view);
3518 fence_size = i915_gem_get_gtt_size(dev,
3521 fence_alignment = i915_gem_get_gtt_alignment(dev,
3525 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3529 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3531 fence_size = i915_gem_get_gtt_size(dev,
3534 fence_alignment = i915_gem_get_gtt_alignment(dev,
3538 unfenced_alignment =
3539 i915_gem_get_gtt_alignment(dev,
3543 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3546 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3548 if (flags & PIN_MAPPABLE)
3549 end = min_t(u64, end, ggtt->mappable_end);
3550 if (flags & PIN_ZONE_4G)
3551 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3554 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3556 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3557 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3558 ggtt_view ? ggtt_view->type : 0,
3560 return ERR_PTR(-EINVAL);
3563 /* If binding the object/GGTT view requires more space than the entire
3564 * aperture has, reject it early before evicting everything in a vain
3565 * attempt to find space.
3568 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3569 ggtt_view ? ggtt_view->type : 0,
3571 flags & PIN_MAPPABLE ? "mappable" : "total",
3573 return ERR_PTR(-E2BIG);
3576 ret = i915_gem_object_get_pages(obj);
3578 return ERR_PTR(ret);
3580 i915_gem_object_pin_pages(obj);
3582 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3583 i915_gem_obj_lookup_or_create_vma(obj, vm);
3588 if (flags & PIN_OFFSET_FIXED) {
3589 uint64_t offset = flags & PIN_OFFSET_MASK;
3591 if (offset & (alignment - 1) || offset + size > end) {
3595 vma->node.start = offset;
3596 vma->node.size = size;
3597 vma->node.color = obj->cache_level;
3598 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3600 ret = i915_gem_evict_for_vma(vma);
3602 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3607 if (flags & PIN_HIGH) {
3608 search_flag = DRM_MM_SEARCH_BELOW;
3609 alloc_flag = DRM_MM_CREATE_TOP;
3611 search_flag = DRM_MM_SEARCH_DEFAULT;
3612 alloc_flag = DRM_MM_CREATE_DEFAULT;
3616 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3623 ret = i915_gem_evict_something(dev, vm, size, alignment,
3633 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3635 goto err_remove_node;
3638 trace_i915_vma_bind(vma, flags);
3639 ret = i915_vma_bind(vma, obj->cache_level, flags);
3641 goto err_remove_node;
3643 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3644 list_add_tail(&vma->vm_link, &vm->inactive_list);
3649 drm_mm_remove_node(&vma->node);
3651 i915_gem_vma_destroy(vma);
3654 i915_gem_object_unpin_pages(obj);
3659 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3662 /* If we don't have a page list set up, then we're not pinned
3663 * to GPU, and we can ignore the cache flush because it'll happen
3664 * again at bind time.
3666 if (obj->pages == NULL)
3670 * Stolen memory is always coherent with the GPU as it is explicitly
3671 * marked as wc by the system, or the system is cache-coherent.
3673 if (obj->stolen || obj->phys_handle)
3676 /* If the GPU is snooping the contents of the CPU cache,
3677 * we do not need to manually clear the CPU cache lines. However,
3678 * the caches are only snooped when the render cache is
3679 * flushed/invalidated. As we always have to emit invalidations
3680 * and flushes when moving into and out of the RENDER domain, correct
3681 * snooping behaviour occurs naturally as the result of our domain
3684 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3685 obj->cache_dirty = true;
3689 trace_i915_gem_object_clflush(obj);
3690 drm_clflush_sg(obj->pages);
3691 obj->cache_dirty = false;
3696 /** Flushes the GTT write domain for the object if it's dirty. */
3698 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3700 uint32_t old_write_domain;
3702 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3705 /* No actual flushing is required for the GTT write domain. Writes
3706 * to it immediately go to main memory as far as we know, so there's
3707 * no chipset flush. It also doesn't land in render cache.
3709 * However, we do have to enforce the order so that all writes through
3710 * the GTT land before any writes to the device, such as updates to
3715 old_write_domain = obj->base.write_domain;
3716 obj->base.write_domain = 0;
3718 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3720 trace_i915_gem_object_change_domain(obj,
3721 obj->base.read_domains,
3725 /** Flushes the CPU write domain for the object if it's dirty. */
3727 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3729 uint32_t old_write_domain;
3731 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3734 if (i915_gem_clflush_object(obj, obj->pin_display))
3735 i915_gem_chipset_flush(obj->base.dev);
3737 old_write_domain = obj->base.write_domain;
3738 obj->base.write_domain = 0;
3740 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3742 trace_i915_gem_object_change_domain(obj,
3743 obj->base.read_domains,
3748 * Moves a single object to the GTT read, and possibly write domain.
3750 * This function returns when the move is complete, including waiting on
3754 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3756 struct drm_device *dev = obj->base.dev;
3757 struct drm_i915_private *dev_priv = to_i915(dev);
3758 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3759 uint32_t old_write_domain, old_read_domains;
3760 struct i915_vma *vma;
3763 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3766 ret = i915_gem_object_wait_rendering(obj, !write);
3770 /* Flush and acquire obj->pages so that we are coherent through
3771 * direct access in memory with previous cached writes through
3772 * shmemfs and that our cache domain tracking remains valid.
3773 * For example, if the obj->filp was moved to swap without us
3774 * being notified and releasing the pages, we would mistakenly
3775 * continue to assume that the obj remained out of the CPU cached
3778 ret = i915_gem_object_get_pages(obj);
3782 i915_gem_object_flush_cpu_write_domain(obj);
3784 /* Serialise direct access to this object with the barriers for
3785 * coherent writes from the GPU, by effectively invalidating the
3786 * GTT domain upon first access.
3788 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3791 old_write_domain = obj->base.write_domain;
3792 old_read_domains = obj->base.read_domains;
3794 /* It should now be out of any other write domains, and we can update
3795 * the domain values for our changes.
3797 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3798 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3800 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3801 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3805 trace_i915_gem_object_change_domain(obj,
3809 /* And bump the LRU for this access */
3810 vma = i915_gem_obj_to_ggtt(obj);
3811 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3812 list_move_tail(&vma->vm_link,
3813 &ggtt->base.inactive_list);
3819 * Changes the cache-level of an object across all VMA.
3821 * After this function returns, the object will be in the new cache-level
3822 * across all GTT and the contents of the backing storage will be coherent,
3823 * with respect to the new cache-level. In order to keep the backing storage
3824 * coherent for all users, we only allow a single cache level to be set
3825 * globally on the object and prevent it from being changed whilst the
3826 * hardware is reading from the object. That is if the object is currently
3827 * on the scanout it will be set to uncached (or equivalent display
3828 * cache coherency) and all non-MOCS GPU access will also be uncached so
3829 * that all direct access to the scanout remains coherent.
3831 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3832 enum i915_cache_level cache_level)
3834 struct drm_device *dev = obj->base.dev;
3835 struct i915_vma *vma, *next;
3839 if (obj->cache_level == cache_level)
3842 /* Inspect the list of currently bound VMA and unbind any that would
3843 * be invalid given the new cache-level. This is principally to
3844 * catch the issue of the CS prefetch crossing page boundaries and
3845 * reading an invalid PTE on older architectures.
3847 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
3848 if (!drm_mm_node_allocated(&vma->node))
3851 if (vma->pin_count) {
3852 DRM_DEBUG("can not change the cache level of pinned objects\n");
3856 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3857 ret = i915_vma_unbind(vma);
3864 /* We can reuse the existing drm_mm nodes but need to change the
3865 * cache-level on the PTE. We could simply unbind them all and
3866 * rebind with the correct cache-level on next use. However since
3867 * we already have a valid slot, dma mapping, pages etc, we may as
3868 * rewrite the PTE in the belief that doing so tramples upon less
3869 * state and so involves less work.
3872 /* Before we change the PTE, the GPU must not be accessing it.
3873 * If we wait upon the object, we know that all the bound
3874 * VMA are no longer active.
3876 ret = i915_gem_object_wait_rendering(obj, false);
3880 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3881 /* Access to snoopable pages through the GTT is
3882 * incoherent and on some machines causes a hard
3883 * lockup. Relinquish the CPU mmaping to force
3884 * userspace to refault in the pages and we can
3885 * then double check if the GTT mapping is still
3886 * valid for that pointer access.
3888 i915_gem_release_mmap(obj);
3890 /* As we no longer need a fence for GTT access,
3891 * we can relinquish it now (and so prevent having
3892 * to steal a fence from someone else on the next
3893 * fence request). Note GPU activity would have
3894 * dropped the fence as all snoopable access is
3895 * supposed to be linear.
3897 ret = i915_gem_object_put_fence(obj);
3901 /* We either have incoherent backing store and
3902 * so no GTT access or the architecture is fully
3903 * coherent. In such cases, existing GTT mmaps
3904 * ignore the cache bit in the PTE and we can
3905 * rewrite it without confusing the GPU or having
3906 * to force userspace to fault back in its mmaps.
3910 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3911 if (!drm_mm_node_allocated(&vma->node))
3914 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3920 list_for_each_entry(vma, &obj->vma_list, obj_link)
3921 vma->node.color = cache_level;
3922 obj->cache_level = cache_level;
3925 /* Flush the dirty CPU caches to the backing storage so that the
3926 * object is now coherent at its new cache level (with respect
3927 * to the access domain).
3929 if (obj->cache_dirty &&
3930 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3931 cpu_write_needs_clflush(obj)) {
3932 if (i915_gem_clflush_object(obj, true))
3933 i915_gem_chipset_flush(obj->base.dev);
3939 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3940 struct drm_file *file)
3942 struct drm_i915_gem_caching *args = data;
3943 struct drm_i915_gem_object *obj;
3945 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3946 if (&obj->base == NULL)
3949 switch (obj->cache_level) {
3950 case I915_CACHE_LLC:
3951 case I915_CACHE_L3_LLC:
3952 args->caching = I915_CACHING_CACHED;
3956 args->caching = I915_CACHING_DISPLAY;
3960 args->caching = I915_CACHING_NONE;
3964 drm_gem_object_unreference_unlocked(&obj->base);
3968 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3969 struct drm_file *file)
3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972 struct drm_i915_gem_caching *args = data;
3973 struct drm_i915_gem_object *obj;
3974 enum i915_cache_level level;
3977 switch (args->caching) {
3978 case I915_CACHING_NONE:
3979 level = I915_CACHE_NONE;
3981 case I915_CACHING_CACHED:
3983 * Due to a HW issue on BXT A stepping, GPU stores via a
3984 * snooped mapping may leave stale data in a corresponding CPU
3985 * cacheline, whereas normally such cachelines would get
3988 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
3991 level = I915_CACHE_LLC;
3993 case I915_CACHING_DISPLAY:
3994 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4000 intel_runtime_pm_get(dev_priv);
4002 ret = i915_mutex_lock_interruptible(dev);
4006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4007 if (&obj->base == NULL) {
4012 ret = i915_gem_object_set_cache_level(obj, level);
4014 drm_gem_object_unreference(&obj->base);
4016 mutex_unlock(&dev->struct_mutex);
4018 intel_runtime_pm_put(dev_priv);
4024 * Prepare buffer for display plane (scanout, cursors, etc).
4025 * Can be called from an uninterruptible phase (modesetting) and allows
4026 * any flushes to be pipelined (for pageflips).
4029 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4031 const struct i915_ggtt_view *view)
4033 u32 old_read_domains, old_write_domain;
4036 /* Mark the pin_display early so that we account for the
4037 * display coherency whilst setting up the cache domains.
4041 /* The display engine is not coherent with the LLC cache on gen6. As
4042 * a result, we make sure that the pinning that is about to occur is
4043 * done with uncached PTEs. This is lowest common denominator for all
4046 * However for gen6+, we could do better by using the GFDT bit instead
4047 * of uncaching, which would allow us to flush all the LLC-cached data
4048 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4050 ret = i915_gem_object_set_cache_level(obj,
4051 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4053 goto err_unpin_display;
4055 /* As the user may map the buffer once pinned in the display plane
4056 * (e.g. libkms for the bootup splash), we have to ensure that we
4057 * always use map_and_fenceable for all scanout buffers.
4059 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4060 view->type == I915_GGTT_VIEW_NORMAL ?
4063 goto err_unpin_display;
4065 i915_gem_object_flush_cpu_write_domain(obj);
4067 old_write_domain = obj->base.write_domain;
4068 old_read_domains = obj->base.read_domains;
4070 /* It should now be out of any other write domains, and we can update
4071 * the domain values for our changes.
4073 obj->base.write_domain = 0;
4074 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4076 trace_i915_gem_object_change_domain(obj,
4088 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4089 const struct i915_ggtt_view *view)
4091 if (WARN_ON(obj->pin_display == 0))
4094 i915_gem_object_ggtt_unpin_view(obj, view);
4100 * Moves a single object to the CPU read, and possibly write domain.
4102 * This function returns when the move is complete, including waiting on
4106 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4108 uint32_t old_write_domain, old_read_domains;
4111 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4114 ret = i915_gem_object_wait_rendering(obj, !write);
4118 i915_gem_object_flush_gtt_write_domain(obj);
4120 old_write_domain = obj->base.write_domain;
4121 old_read_domains = obj->base.read_domains;
4123 /* Flush the CPU cache if it's still invalid. */
4124 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4125 i915_gem_clflush_object(obj, false);
4127 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4130 /* It should now be out of any other write domains, and we can update
4131 * the domain values for our changes.
4133 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4135 /* If we're writing through the CPU, then the GPU read domains will
4136 * need to be invalidated at next use.
4139 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4140 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4143 trace_i915_gem_object_change_domain(obj,
4150 /* Throttle our rendering by waiting until the ring has completed our requests
4151 * emitted over 20 msec ago.
4153 * Note that if we were to use the current jiffies each time around the loop,
4154 * we wouldn't escape the function with any frames outstanding if the time to
4155 * render a frame was over 20ms.
4157 * This should get us reasonable parallelism between CPU and GPU but also
4158 * relatively low latency when blocking on a particular request to finish.
4161 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 struct drm_i915_file_private *file_priv = file->driver_priv;
4165 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4166 struct drm_i915_gem_request *request, *target = NULL;
4169 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4173 /* ABI: return -EIO if already wedged */
4174 if (i915_terminally_wedged(&dev_priv->gpu_error))
4177 spin_lock(&file_priv->mm.lock);
4178 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4179 if (time_after_eq(request->emitted_jiffies, recent_enough))
4183 * Note that the request might not have been submitted yet.
4184 * In which case emitted_jiffies will be zero.
4186 if (!request->emitted_jiffies)
4192 i915_gem_request_reference(target);
4193 spin_unlock(&file_priv->mm.lock);
4198 ret = __i915_wait_request(target, true, NULL, NULL);
4200 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4202 i915_gem_request_unreference__unlocked(target);
4208 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4210 struct drm_i915_gem_object *obj = vma->obj;
4213 vma->node.start & (alignment - 1))
4216 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4219 if (flags & PIN_OFFSET_BIAS &&
4220 vma->node.start < (flags & PIN_OFFSET_MASK))
4223 if (flags & PIN_OFFSET_FIXED &&
4224 vma->node.start != (flags & PIN_OFFSET_MASK))
4230 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4232 struct drm_i915_gem_object *obj = vma->obj;
4233 bool mappable, fenceable;
4234 u32 fence_size, fence_alignment;
4236 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4239 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4244 fenceable = (vma->node.size == fence_size &&
4245 (vma->node.start & (fence_alignment - 1)) == 0);
4247 mappable = (vma->node.start + fence_size <=
4248 to_i915(obj->base.dev)->ggtt.mappable_end);
4250 obj->map_and_fenceable = mappable && fenceable;
4254 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4255 struct i915_address_space *vm,
4256 const struct i915_ggtt_view *ggtt_view,
4260 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4261 struct i915_vma *vma;
4265 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4268 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4271 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4274 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4277 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4278 i915_gem_obj_to_vma(obj, vm);
4281 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4284 if (i915_vma_misplaced(vma, alignment, flags)) {
4285 WARN(vma->pin_count,
4286 "bo is already pinned in %s with incorrect alignment:"
4287 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4288 " obj->map_and_fenceable=%d\n",
4289 ggtt_view ? "ggtt" : "ppgtt",
4290 upper_32_bits(vma->node.start),
4291 lower_32_bits(vma->node.start),
4293 !!(flags & PIN_MAPPABLE),
4294 obj->map_and_fenceable);
4295 ret = i915_vma_unbind(vma);
4303 bound = vma ? vma->bound : 0;
4304 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4305 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4308 return PTR_ERR(vma);
4310 ret = i915_vma_bind(vma, obj->cache_level, flags);
4315 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4316 (bound ^ vma->bound) & GLOBAL_BIND) {
4317 __i915_vma_set_map_and_fenceable(vma);
4318 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4326 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4327 struct i915_address_space *vm,
4331 return i915_gem_object_do_pin(obj, vm,
4332 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4337 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4338 const struct i915_ggtt_view *view,
4342 struct drm_device *dev = obj->base.dev;
4343 struct drm_i915_private *dev_priv = to_i915(dev);
4344 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4348 return i915_gem_object_do_pin(obj, &ggtt->base, view,
4349 alignment, flags | PIN_GLOBAL);
4353 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4354 const struct i915_ggtt_view *view)
4356 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4359 WARN_ON(vma->pin_count == 0);
4360 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4366 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4367 struct drm_file *file)
4369 struct drm_i915_gem_busy *args = data;
4370 struct drm_i915_gem_object *obj;
4373 ret = i915_mutex_lock_interruptible(dev);
4377 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4378 if (&obj->base == NULL) {
4383 /* Count all active objects as busy, even if they are currently not used
4384 * by the gpu. Users of this interface expect objects to eventually
4385 * become non-busy without any further actions, therefore emit any
4386 * necessary flushes here.
4388 ret = i915_gem_object_flush_active(obj);
4396 for (i = 0; i < I915_NUM_ENGINES; i++) {
4397 struct drm_i915_gem_request *req;
4399 req = obj->last_read_req[i];
4401 args->busy |= 1 << (16 + req->engine->exec_id);
4403 if (obj->last_write_req)
4404 args->busy |= obj->last_write_req->engine->exec_id;
4408 drm_gem_object_unreference(&obj->base);
4410 mutex_unlock(&dev->struct_mutex);
4415 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4416 struct drm_file *file_priv)
4418 return i915_gem_ring_throttle(dev, file_priv);
4422 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4423 struct drm_file *file_priv)
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 struct drm_i915_gem_madvise *args = data;
4427 struct drm_i915_gem_object *obj;
4430 switch (args->madv) {
4431 case I915_MADV_DONTNEED:
4432 case I915_MADV_WILLNEED:
4438 ret = i915_mutex_lock_interruptible(dev);
4442 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4443 if (&obj->base == NULL) {
4448 if (i915_gem_obj_is_pinned(obj)) {
4454 obj->tiling_mode != I915_TILING_NONE &&
4455 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4456 if (obj->madv == I915_MADV_WILLNEED)
4457 i915_gem_object_unpin_pages(obj);
4458 if (args->madv == I915_MADV_WILLNEED)
4459 i915_gem_object_pin_pages(obj);
4462 if (obj->madv != __I915_MADV_PURGED)
4463 obj->madv = args->madv;
4465 /* if the object is no longer attached, discard its backing storage */
4466 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4467 i915_gem_object_truncate(obj);
4469 args->retained = obj->madv != __I915_MADV_PURGED;
4472 drm_gem_object_unreference(&obj->base);
4474 mutex_unlock(&dev->struct_mutex);
4478 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4479 const struct drm_i915_gem_object_ops *ops)
4483 INIT_LIST_HEAD(&obj->global_list);
4484 for (i = 0; i < I915_NUM_ENGINES; i++)
4485 INIT_LIST_HEAD(&obj->engine_list[i]);
4486 INIT_LIST_HEAD(&obj->obj_exec_link);
4487 INIT_LIST_HEAD(&obj->vma_list);
4488 INIT_LIST_HEAD(&obj->batch_pool_link);
4492 obj->fence_reg = I915_FENCE_REG_NONE;
4493 obj->madv = I915_MADV_WILLNEED;
4495 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4498 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4499 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4500 .get_pages = i915_gem_object_get_pages_gtt,
4501 .put_pages = i915_gem_object_put_pages_gtt,
4504 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4507 struct drm_i915_gem_object *obj;
4508 struct address_space *mapping;
4511 obj = i915_gem_object_alloc(dev);
4515 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4516 i915_gem_object_free(obj);
4520 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4521 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4522 /* 965gm cannot relocate objects above 4GiB. */
4523 mask &= ~__GFP_HIGHMEM;
4524 mask |= __GFP_DMA32;
4527 mapping = file_inode(obj->base.filp)->i_mapping;
4528 mapping_set_gfp_mask(mapping, mask);
4530 i915_gem_object_init(obj, &i915_gem_object_ops);
4532 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4533 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4536 /* On some devices, we can have the GPU use the LLC (the CPU
4537 * cache) for about a 10% performance improvement
4538 * compared to uncached. Graphics requests other than
4539 * display scanout are coherent with the CPU in
4540 * accessing this cache. This means in this mode we
4541 * don't need to clflush on the CPU side, and on the
4542 * GPU side we only need to flush internal caches to
4543 * get data visible to the CPU.
4545 * However, we maintain the display planes as UC, and so
4546 * need to rebind when first used as such.
4548 obj->cache_level = I915_CACHE_LLC;
4550 obj->cache_level = I915_CACHE_NONE;
4552 trace_i915_gem_object_create(obj);
4557 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4559 /* If we are the last user of the backing storage (be it shmemfs
4560 * pages or stolen etc), we know that the pages are going to be
4561 * immediately released. In this case, we can then skip copying
4562 * back the contents from the GPU.
4565 if (obj->madv != I915_MADV_WILLNEED)
4568 if (obj->base.filp == NULL)
4571 /* At first glance, this looks racy, but then again so would be
4572 * userspace racing mmap against close. However, the first external
4573 * reference to the filp can only be obtained through the
4574 * i915_gem_mmap_ioctl() which safeguards us against the user
4575 * acquiring such a reference whilst we are in the middle of
4576 * freeing the object.
4578 return atomic_long_read(&obj->base.filp->f_count) == 1;
4581 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4583 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4584 struct drm_device *dev = obj->base.dev;
4585 struct drm_i915_private *dev_priv = dev->dev_private;
4586 struct i915_vma *vma, *next;
4588 intel_runtime_pm_get(dev_priv);
4590 trace_i915_gem_object_destroy(obj);
4592 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4596 ret = i915_vma_unbind(vma);
4597 if (WARN_ON(ret == -ERESTARTSYS)) {
4598 bool was_interruptible;
4600 was_interruptible = dev_priv->mm.interruptible;
4601 dev_priv->mm.interruptible = false;
4603 WARN_ON(i915_vma_unbind(vma));
4605 dev_priv->mm.interruptible = was_interruptible;
4609 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4610 * before progressing. */
4612 i915_gem_object_unpin_pages(obj);
4614 WARN_ON(obj->frontbuffer_bits);
4616 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4617 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4618 obj->tiling_mode != I915_TILING_NONE)
4619 i915_gem_object_unpin_pages(obj);
4621 if (WARN_ON(obj->pages_pin_count))
4622 obj->pages_pin_count = 0;
4623 if (discard_backing_storage(obj))
4624 obj->madv = I915_MADV_DONTNEED;
4625 i915_gem_object_put_pages(obj);
4626 i915_gem_object_free_mmap_offset(obj);
4630 if (obj->base.import_attach)
4631 drm_prime_gem_destroy(&obj->base, NULL);
4633 if (obj->ops->release)
4634 obj->ops->release(obj);
4636 drm_gem_object_release(&obj->base);
4637 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4640 i915_gem_object_free(obj);
4642 intel_runtime_pm_put(dev_priv);
4645 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4646 struct i915_address_space *vm)
4648 struct i915_vma *vma;
4649 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4650 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4657 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4658 const struct i915_ggtt_view *view)
4660 struct drm_device *dev = obj->base.dev;
4661 struct drm_i915_private *dev_priv = to_i915(dev);
4662 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4663 struct i915_vma *vma;
4667 list_for_each_entry(vma, &obj->vma_list, obj_link)
4668 if (vma->vm == &ggtt->base &&
4669 i915_ggtt_view_equal(&vma->ggtt_view, view))
4674 void i915_gem_vma_destroy(struct i915_vma *vma)
4676 WARN_ON(vma->node.allocated);
4678 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4679 if (!list_empty(&vma->exec_list))
4683 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4685 list_del(&vma->obj_link);
4687 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4691 i915_gem_stop_engines(struct drm_device *dev)
4693 struct drm_i915_private *dev_priv = dev->dev_private;
4694 struct intel_engine_cs *engine;
4696 for_each_engine(engine, dev_priv)
4697 dev_priv->gt.stop_engine(engine);
4701 i915_gem_suspend(struct drm_device *dev)
4703 struct drm_i915_private *dev_priv = dev->dev_private;
4706 mutex_lock(&dev->struct_mutex);
4707 ret = i915_gpu_idle(dev);
4711 i915_gem_retire_requests(dev);
4713 i915_gem_stop_engines(dev);
4714 mutex_unlock(&dev->struct_mutex);
4716 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4717 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4718 flush_delayed_work(&dev_priv->mm.idle_work);
4720 /* Assert that we sucessfully flushed all the work and
4721 * reset the GPU back to its idle, low power state.
4723 WARN_ON(dev_priv->mm.busy);
4728 mutex_unlock(&dev->struct_mutex);
4732 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4734 struct intel_engine_cs *engine = req->engine;
4735 struct drm_device *dev = engine->dev;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4740 if (!HAS_L3_DPF(dev) || !remap_info)
4743 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4748 * Note: We do not worry about the concurrent register cacheline hang
4749 * here because no other code should access these registers other than
4750 * at initialization time.
4752 for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
4753 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
4754 intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
4755 intel_ring_emit(engine, remap_info[i]);
4758 intel_ring_advance(engine);
4763 void i915_gem_init_swizzling(struct drm_device *dev)
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4767 if (INTEL_INFO(dev)->gen < 5 ||
4768 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4771 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4772 DISP_TILE_SURFACE_SWIZZLING);
4777 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4779 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4780 else if (IS_GEN7(dev))
4781 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4782 else if (IS_GEN8(dev))
4783 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4788 static void init_unused_ring(struct drm_device *dev, u32 base)
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4792 I915_WRITE(RING_CTL(base), 0);
4793 I915_WRITE(RING_HEAD(base), 0);
4794 I915_WRITE(RING_TAIL(base), 0);
4795 I915_WRITE(RING_START(base), 0);
4798 static void init_unused_rings(struct drm_device *dev)
4801 init_unused_ring(dev, PRB1_BASE);
4802 init_unused_ring(dev, SRB0_BASE);
4803 init_unused_ring(dev, SRB1_BASE);
4804 init_unused_ring(dev, SRB2_BASE);
4805 init_unused_ring(dev, SRB3_BASE);
4806 } else if (IS_GEN2(dev)) {
4807 init_unused_ring(dev, SRB0_BASE);
4808 init_unused_ring(dev, SRB1_BASE);
4809 } else if (IS_GEN3(dev)) {
4810 init_unused_ring(dev, PRB1_BASE);
4811 init_unused_ring(dev, PRB2_BASE);
4815 int i915_gem_init_engines(struct drm_device *dev)
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4820 ret = intel_init_render_ring_buffer(dev);
4825 ret = intel_init_bsd_ring_buffer(dev);
4827 goto cleanup_render_ring;
4831 ret = intel_init_blt_ring_buffer(dev);
4833 goto cleanup_bsd_ring;
4836 if (HAS_VEBOX(dev)) {
4837 ret = intel_init_vebox_ring_buffer(dev);
4839 goto cleanup_blt_ring;
4842 if (HAS_BSD2(dev)) {
4843 ret = intel_init_bsd2_ring_buffer(dev);
4845 goto cleanup_vebox_ring;
4851 intel_cleanup_engine(&dev_priv->engine[VECS]);
4853 intel_cleanup_engine(&dev_priv->engine[BCS]);
4855 intel_cleanup_engine(&dev_priv->engine[VCS]);
4856 cleanup_render_ring:
4857 intel_cleanup_engine(&dev_priv->engine[RCS]);
4863 i915_gem_init_hw(struct drm_device *dev)
4865 struct drm_i915_private *dev_priv = dev->dev_private;
4866 struct intel_engine_cs *engine;
4869 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4872 /* Double layer security blanket, see i915_gem_init() */
4873 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4875 if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
4876 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4878 if (IS_HASWELL(dev))
4879 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4880 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4882 if (HAS_PCH_NOP(dev)) {
4883 if (IS_IVYBRIDGE(dev)) {
4884 u32 temp = I915_READ(GEN7_MSG_CTL);
4885 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4886 I915_WRITE(GEN7_MSG_CTL, temp);
4887 } else if (INTEL_INFO(dev)->gen >= 7) {
4888 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4889 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4890 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4894 i915_gem_init_swizzling(dev);
4897 * At least 830 can leave some of the unused rings
4898 * "active" (ie. head != tail) after resume which
4899 * will prevent c3 entry. Makes sure all unused rings
4902 init_unused_rings(dev);
4904 BUG_ON(!dev_priv->kernel_context);
4906 ret = i915_ppgtt_init_hw(dev);
4908 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4912 /* Need to do basic initialisation of all rings first: */
4913 for_each_engine(engine, dev_priv) {
4914 ret = engine->init_hw(engine);
4919 intel_mocs_init_l3cc_table(dev);
4921 /* We can't enable contexts until all firmware is loaded */
4922 if (HAS_GUC_UCODE(dev)) {
4923 ret = intel_guc_ucode_load(dev);
4925 DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4932 * Increment the next seqno by 0x100 so we have a visible break
4933 * on re-initialisation
4935 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4939 /* Now it is safe to go back round and do everything else: */
4940 for_each_engine(engine, dev_priv) {
4941 struct drm_i915_gem_request *req;
4943 req = i915_gem_request_alloc(engine, NULL);
4949 if (engine->id == RCS) {
4950 for (j = 0; j < NUM_L3_SLICES(dev); j++) {
4951 ret = i915_gem_l3_remap(req, j);
4957 ret = i915_ppgtt_init_ring(req);
4961 ret = i915_gem_context_enable(req);
4966 i915_add_request_no_flush(req);
4968 DRM_ERROR("Failed to enable %s, error=%d\n",
4970 i915_gem_cleanup_engines(dev);
4976 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4980 int i915_gem_init(struct drm_device *dev)
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4985 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4986 i915.enable_execlists);
4988 mutex_lock(&dev->struct_mutex);
4990 if (!i915.enable_execlists) {
4991 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4992 dev_priv->gt.init_engines = i915_gem_init_engines;
4993 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
4994 dev_priv->gt.stop_engine = intel_stop_engine;
4996 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4997 dev_priv->gt.init_engines = intel_logical_rings_init;
4998 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4999 dev_priv->gt.stop_engine = intel_logical_ring_stop;
5002 /* This is just a security blanket to placate dragons.
5003 * On some systems, we very sporadically observe that the first TLBs
5004 * used by the CS may be stale, despite us poking the TLB reset. If
5005 * we hold the forcewake during initialisation these problems
5006 * just magically go away.
5008 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5010 ret = i915_gem_init_userptr(dev);
5014 i915_gem_init_ggtt(dev);
5016 ret = i915_gem_context_init(dev);
5020 ret = dev_priv->gt.init_engines(dev);
5024 ret = i915_gem_init_hw(dev);
5026 /* Allow ring initialisation to fail by marking the GPU as
5027 * wedged. But we only want to do this where the GPU is angry,
5028 * for all other failure, such as an allocation failure, bail.
5030 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5031 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5036 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5037 mutex_unlock(&dev->struct_mutex);
5043 i915_gem_cleanup_engines(struct drm_device *dev)
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5046 struct intel_engine_cs *engine;
5048 for_each_engine(engine, dev_priv)
5049 dev_priv->gt.cleanup_engine(engine);
5051 if (i915.enable_execlists)
5053 * Neither the BIOS, ourselves or any other kernel
5054 * expects the system to be in execlists mode on startup,
5055 * so we need to reset the GPU back to legacy mode.
5057 intel_gpu_reset(dev, ALL_ENGINES);
5061 init_engine_lists(struct intel_engine_cs *engine)
5063 INIT_LIST_HEAD(&engine->active_list);
5064 INIT_LIST_HEAD(&engine->request_list);
5068 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5070 struct drm_device *dev = dev_priv->dev;
5072 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5073 !IS_CHERRYVIEW(dev_priv))
5074 dev_priv->num_fence_regs = 32;
5075 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
5076 IS_I945GM(dev_priv) || IS_G33(dev_priv))
5077 dev_priv->num_fence_regs = 16;
5079 dev_priv->num_fence_regs = 8;
5081 if (intel_vgpu_active(dev))
5082 dev_priv->num_fence_regs =
5083 I915_READ(vgtif_reg(avail_rs.fence_num));
5085 /* Initialize fence registers to zero */
5086 i915_gem_restore_fences(dev);
5088 i915_gem_detect_bit_6_swizzle(dev);
5092 i915_gem_load_init(struct drm_device *dev)
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5098 kmem_cache_create("i915_gem_object",
5099 sizeof(struct drm_i915_gem_object), 0,
5103 kmem_cache_create("i915_gem_vma",
5104 sizeof(struct i915_vma), 0,
5107 dev_priv->requests =
5108 kmem_cache_create("i915_gem_request",
5109 sizeof(struct drm_i915_gem_request), 0,
5113 INIT_LIST_HEAD(&dev_priv->vm_list);
5114 INIT_LIST_HEAD(&dev_priv->context_list);
5115 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5116 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5117 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5118 for (i = 0; i < I915_NUM_ENGINES; i++)
5119 init_engine_lists(&dev_priv->engine[i]);
5120 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5121 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5122 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5123 i915_gem_retire_work_handler);
5124 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5125 i915_gem_idle_work_handler);
5126 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5128 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5131 * Set initial sequence number for requests.
5132 * Using this number allows the wraparound to happen early,
5133 * catching any obvious problems.
5135 dev_priv->next_seqno = ((u32)~0 - 0x1100);
5136 dev_priv->last_seqno = ((u32)~0 - 0x1101);
5138 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5140 init_waitqueue_head(&dev_priv->pending_flip_queue);
5142 dev_priv->mm.interruptible = true;
5144 mutex_init(&dev_priv->fb_tracking.lock);
5147 void i915_gem_load_cleanup(struct drm_device *dev)
5149 struct drm_i915_private *dev_priv = to_i915(dev);
5151 kmem_cache_destroy(dev_priv->requests);
5152 kmem_cache_destroy(dev_priv->vmas);
5153 kmem_cache_destroy(dev_priv->objects);
5156 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5158 struct drm_i915_file_private *file_priv = file->driver_priv;
5160 /* Clean up our request list when the client is going away, so that
5161 * later retire_requests won't dereference our soon-to-be-gone
5164 spin_lock(&file_priv->mm.lock);
5165 while (!list_empty(&file_priv->mm.request_list)) {
5166 struct drm_i915_gem_request *request;
5168 request = list_first_entry(&file_priv->mm.request_list,
5169 struct drm_i915_gem_request,
5171 list_del(&request->client_list);
5172 request->file_priv = NULL;
5174 spin_unlock(&file_priv->mm.lock);
5176 if (!list_empty(&file_priv->rps.link)) {
5177 spin_lock(&to_i915(dev)->rps.client_lock);
5178 list_del(&file_priv->rps.link);
5179 spin_unlock(&to_i915(dev)->rps.client_lock);
5183 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5185 struct drm_i915_file_private *file_priv;
5188 DRM_DEBUG_DRIVER("\n");
5190 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5194 file->driver_priv = file_priv;
5195 file_priv->dev_priv = dev->dev_private;
5196 file_priv->file = file;
5197 INIT_LIST_HEAD(&file_priv->rps.link);
5199 spin_lock_init(&file_priv->mm.lock);
5200 INIT_LIST_HEAD(&file_priv->mm.request_list);
5202 file_priv->bsd_ring = -1;
5204 ret = i915_gem_context_open(dev, file);
5212 * i915_gem_track_fb - update frontbuffer tracking
5213 * @old: current GEM buffer for the frontbuffer slots
5214 * @new: new GEM buffer for the frontbuffer slots
5215 * @frontbuffer_bits: bitmask of frontbuffer slots
5217 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5218 * from @old and setting them in @new. Both @old and @new can be NULL.
5220 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5221 struct drm_i915_gem_object *new,
5222 unsigned frontbuffer_bits)
5225 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5226 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5227 old->frontbuffer_bits &= ~frontbuffer_bits;
5231 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5232 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5233 new->frontbuffer_bits |= frontbuffer_bits;
5237 /* All the new VM stuff */
5238 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5239 struct i915_address_space *vm)
5241 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5242 struct i915_vma *vma;
5244 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5246 list_for_each_entry(vma, &o->vma_list, obj_link) {
5248 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5251 return vma->node.start;
5254 WARN(1, "%s vma for this object not found.\n",
5255 i915_is_ggtt(vm) ? "global" : "ppgtt");
5259 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5260 const struct i915_ggtt_view *view)
5262 struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5263 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5264 struct i915_vma *vma;
5266 list_for_each_entry(vma, &o->vma_list, obj_link)
5267 if (vma->vm == &ggtt->base &&
5268 i915_ggtt_view_equal(&vma->ggtt_view, view))
5269 return vma->node.start;
5271 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5275 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5276 struct i915_address_space *vm)
5278 struct i915_vma *vma;
5280 list_for_each_entry(vma, &o->vma_list, obj_link) {
5282 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5284 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5291 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5292 const struct i915_ggtt_view *view)
5294 struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5295 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5296 struct i915_vma *vma;
5298 list_for_each_entry(vma, &o->vma_list, obj_link)
5299 if (vma->vm == &ggtt->base &&
5300 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5301 drm_mm_node_allocated(&vma->node))
5307 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5309 struct i915_vma *vma;
5311 list_for_each_entry(vma, &o->vma_list, obj_link)
5312 if (drm_mm_node_allocated(&vma->node))
5318 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5319 struct i915_address_space *vm)
5321 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5322 struct i915_vma *vma;
5324 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5326 BUG_ON(list_empty(&o->vma_list));
5328 list_for_each_entry(vma, &o->vma_list, obj_link) {
5330 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5333 return vma->node.size;
5338 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5340 struct i915_vma *vma;
5341 list_for_each_entry(vma, &obj->vma_list, obj_link)
5342 if (vma->pin_count > 0)
5348 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5350 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5354 /* Only default objects have per-page dirty tracking */
5355 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
5358 page = i915_gem_object_get_page(obj, n);
5359 set_page_dirty(page);
5363 /* Allocate a new GEM object and fill it with the supplied data */
5364 struct drm_i915_gem_object *
5365 i915_gem_object_create_from_data(struct drm_device *dev,
5366 const void *data, size_t size)
5368 struct drm_i915_gem_object *obj;
5369 struct sg_table *sg;
5373 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5374 if (IS_ERR_OR_NULL(obj))
5377 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5381 ret = i915_gem_object_get_pages(obj);
5385 i915_gem_object_pin_pages(obj);
5387 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5388 obj->dirty = 1; /* Backing store is now out of date */
5389 i915_gem_object_unpin_pages(obj);
5391 if (WARN_ON(bytes != size)) {
5392 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5400 drm_gem_object_unreference(&obj->base);
5401 return ERR_PTR(ret);