2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
46 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
47 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
56 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59 drm_i915_private_t *dev_priv = dev->dev_private;
62 (start & (PAGE_SIZE - 1)) != 0 ||
63 (end & (PAGE_SIZE - 1)) != 0) {
67 drm_mm_init(&dev_priv->mm.gtt_space, start,
70 dev->gtt_total = (uint32_t) (end - start);
76 i915_gem_init_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
79 struct drm_i915_gem_init *args = data;
82 mutex_lock(&dev->struct_mutex);
83 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
84 mutex_unlock(&dev->struct_mutex);
90 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
93 struct drm_i915_gem_get_aperture *args = data;
95 if (!(dev->driver->driver_features & DRIVER_GEM))
98 args->aper_size = dev->gtt_total;
99 args->aper_available_size = (args->aper_size -
100 atomic_read(&dev->pin_memory));
107 * Creates a new mm object and returns a handle to it.
110 i915_gem_create_ioctl(struct drm_device *dev, void *data,
111 struct drm_file *file_priv)
113 struct drm_i915_gem_create *args = data;
114 struct drm_gem_object *obj;
117 args->size = roundup(args->size, PAGE_SIZE);
119 /* Allocate the new object */
120 obj = drm_gem_object_alloc(dev, args->size);
124 ret = drm_gem_handle_create(file_priv, obj, &handle);
125 mutex_lock(&dev->struct_mutex);
126 drm_gem_object_handle_unreference(obj);
127 mutex_unlock(&dev->struct_mutex);
132 args->handle = handle;
138 fast_shmem_read(struct page **pages,
139 loff_t page_base, int page_offset,
146 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
149 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
150 kunmap_atomic(vaddr, KM_USER0);
158 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
160 drm_i915_private_t *dev_priv = obj->dev->dev_private;
161 struct drm_i915_gem_object *obj_priv = obj->driver_private;
163 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
164 obj_priv->tiling_mode != I915_TILING_NONE;
168 slow_shmem_copy(struct page *dst_page,
170 struct page *src_page,
174 char *dst_vaddr, *src_vaddr;
176 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
177 if (dst_vaddr == NULL)
180 src_vaddr = kmap_atomic(src_page, KM_USER1);
181 if (src_vaddr == NULL) {
182 kunmap_atomic(dst_vaddr, KM_USER0);
186 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
188 kunmap_atomic(src_vaddr, KM_USER1);
189 kunmap_atomic(dst_vaddr, KM_USER0);
195 slow_shmem_bit17_copy(struct page *gpu_page,
197 struct page *cpu_page,
202 char *gpu_vaddr, *cpu_vaddr;
204 /* Use the unswizzled path if this page isn't affected. */
205 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
207 return slow_shmem_copy(cpu_page, cpu_offset,
208 gpu_page, gpu_offset, length);
210 return slow_shmem_copy(gpu_page, gpu_offset,
211 cpu_page, cpu_offset, length);
214 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
215 if (gpu_vaddr == NULL)
218 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
219 if (cpu_vaddr == NULL) {
220 kunmap_atomic(gpu_vaddr, KM_USER0);
224 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
225 * XORing with the other bits (A9 for Y, A9 and A10 for X)
228 int cacheline_end = ALIGN(gpu_offset + 1, 64);
229 int this_length = min(cacheline_end - gpu_offset, length);
230 int swizzled_gpu_offset = gpu_offset ^ 64;
233 memcpy(cpu_vaddr + cpu_offset,
234 gpu_vaddr + swizzled_gpu_offset,
237 memcpy(gpu_vaddr + swizzled_gpu_offset,
238 cpu_vaddr + cpu_offset,
241 cpu_offset += this_length;
242 gpu_offset += this_length;
243 length -= this_length;
246 kunmap_atomic(cpu_vaddr, KM_USER1);
247 kunmap_atomic(gpu_vaddr, KM_USER0);
253 * This is the fast shmem pread path, which attempts to copy_from_user directly
254 * from the backing pages of the object to the user's address space. On a
255 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
258 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
259 struct drm_i915_gem_pread *args,
260 struct drm_file *file_priv)
262 struct drm_i915_gem_object *obj_priv = obj->driver_private;
264 loff_t offset, page_base;
265 char __user *user_data;
266 int page_offset, page_length;
269 user_data = (char __user *) (uintptr_t) args->data_ptr;
272 mutex_lock(&dev->struct_mutex);
274 ret = i915_gem_object_get_pages(obj);
278 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
283 obj_priv = obj->driver_private;
284 offset = args->offset;
287 /* Operation in this page
289 * page_base = page offset within aperture
290 * page_offset = offset within page
291 * page_length = bytes to copy for this page
293 page_base = (offset & ~(PAGE_SIZE-1));
294 page_offset = offset & (PAGE_SIZE-1);
295 page_length = remain;
296 if ((page_offset + remain) > PAGE_SIZE)
297 page_length = PAGE_SIZE - page_offset;
299 ret = fast_shmem_read(obj_priv->pages,
300 page_base, page_offset,
301 user_data, page_length);
305 remain -= page_length;
306 user_data += page_length;
307 offset += page_length;
311 i915_gem_object_put_pages(obj);
313 mutex_unlock(&dev->struct_mutex);
319 * This is the fallback shmem pread path, which allocates temporary storage
320 * in kernel space to copy_to_user into outside of the struct_mutex, so we
321 * can copy out of the object's backing pages while holding the struct mutex
322 * and not take page faults.
325 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
326 struct drm_i915_gem_pread *args,
327 struct drm_file *file_priv)
329 struct drm_i915_gem_object *obj_priv = obj->driver_private;
330 struct mm_struct *mm = current->mm;
331 struct page **user_pages;
333 loff_t offset, pinned_pages, i;
334 loff_t first_data_page, last_data_page, num_pages;
335 int shmem_page_index, shmem_page_offset;
336 int data_page_index, data_page_offset;
339 uint64_t data_ptr = args->data_ptr;
340 int do_bit17_swizzling;
344 /* Pin the user pages containing the data. We can't fault while
345 * holding the struct mutex, yet we want to hold it while
346 * dereferencing the user data.
348 first_data_page = data_ptr / PAGE_SIZE;
349 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
350 num_pages = last_data_page - first_data_page + 1;
352 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
353 if (user_pages == NULL)
356 down_read(&mm->mmap_sem);
357 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
358 num_pages, 1, 0, user_pages, NULL);
359 up_read(&mm->mmap_sem);
360 if (pinned_pages < num_pages) {
362 goto fail_put_user_pages;
365 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
367 mutex_lock(&dev->struct_mutex);
369 ret = i915_gem_object_get_pages(obj);
373 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
378 obj_priv = obj->driver_private;
379 offset = args->offset;
382 /* Operation in this page
384 * shmem_page_index = page number within shmem file
385 * shmem_page_offset = offset within page in shmem file
386 * data_page_index = page number in get_user_pages return
387 * data_page_offset = offset with data_page_index page.
388 * page_length = bytes to copy for this page
390 shmem_page_index = offset / PAGE_SIZE;
391 shmem_page_offset = offset & ~PAGE_MASK;
392 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
393 data_page_offset = data_ptr & ~PAGE_MASK;
395 page_length = remain;
396 if ((shmem_page_offset + page_length) > PAGE_SIZE)
397 page_length = PAGE_SIZE - shmem_page_offset;
398 if ((data_page_offset + page_length) > PAGE_SIZE)
399 page_length = PAGE_SIZE - data_page_offset;
401 if (do_bit17_swizzling) {
402 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
404 user_pages[data_page_index],
409 ret = slow_shmem_copy(user_pages[data_page_index],
411 obj_priv->pages[shmem_page_index],
418 remain -= page_length;
419 data_ptr += page_length;
420 offset += page_length;
424 i915_gem_object_put_pages(obj);
426 mutex_unlock(&dev->struct_mutex);
428 for (i = 0; i < pinned_pages; i++) {
429 SetPageDirty(user_pages[i]);
430 page_cache_release(user_pages[i]);
438 * Reads data from the object referenced by handle.
440 * On error, the contents of *data are undefined.
443 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
444 struct drm_file *file_priv)
446 struct drm_i915_gem_pread *args = data;
447 struct drm_gem_object *obj;
448 struct drm_i915_gem_object *obj_priv;
451 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
454 obj_priv = obj->driver_private;
456 /* Bounds check source.
458 * XXX: This could use review for overflow issues...
460 if (args->offset > obj->size || args->size > obj->size ||
461 args->offset + args->size > obj->size) {
462 drm_gem_object_unreference(obj);
466 if (i915_gem_object_needs_bit17_swizzle(obj)) {
467 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
469 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
471 ret = i915_gem_shmem_pread_slow(dev, obj, args,
475 drm_gem_object_unreference(obj);
480 /* This is the fast write path which cannot handle
481 * page faults in the source data
485 fast_user_write(struct io_mapping *mapping,
486 loff_t page_base, int page_offset,
487 char __user *user_data,
491 unsigned long unwritten;
493 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
494 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
496 io_mapping_unmap_atomic(vaddr_atomic);
502 /* Here's the write path which can sleep for
507 slow_kernel_write(struct io_mapping *mapping,
508 loff_t gtt_base, int gtt_offset,
509 struct page *user_page, int user_offset,
512 char *src_vaddr, *dst_vaddr;
513 unsigned long unwritten;
515 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
516 src_vaddr = kmap_atomic(user_page, KM_USER1);
517 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
518 src_vaddr + user_offset,
520 kunmap_atomic(src_vaddr, KM_USER1);
521 io_mapping_unmap_atomic(dst_vaddr);
528 fast_shmem_write(struct page **pages,
529 loff_t page_base, int page_offset,
534 unsigned long unwritten;
536 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
539 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
540 kunmap_atomic(vaddr, KM_USER0);
548 * This is the fast pwrite path, where we copy the data directly from the
549 * user into the GTT, uncached.
552 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
553 struct drm_i915_gem_pwrite *args,
554 struct drm_file *file_priv)
556 struct drm_i915_gem_object *obj_priv = obj->driver_private;
557 drm_i915_private_t *dev_priv = dev->dev_private;
559 loff_t offset, page_base;
560 char __user *user_data;
561 int page_offset, page_length;
564 user_data = (char __user *) (uintptr_t) args->data_ptr;
566 if (!access_ok(VERIFY_READ, user_data, remain))
570 mutex_lock(&dev->struct_mutex);
571 ret = i915_gem_object_pin(obj, 0);
573 mutex_unlock(&dev->struct_mutex);
576 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
580 obj_priv = obj->driver_private;
581 offset = obj_priv->gtt_offset + args->offset;
584 /* Operation in this page
586 * page_base = page offset within aperture
587 * page_offset = offset within page
588 * page_length = bytes to copy for this page
590 page_base = (offset & ~(PAGE_SIZE-1));
591 page_offset = offset & (PAGE_SIZE-1);
592 page_length = remain;
593 if ((page_offset + remain) > PAGE_SIZE)
594 page_length = PAGE_SIZE - page_offset;
596 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
597 page_offset, user_data, page_length);
599 /* If we get a fault while copying data, then (presumably) our
600 * source page isn't available. Return the error and we'll
601 * retry in the slow path.
606 remain -= page_length;
607 user_data += page_length;
608 offset += page_length;
612 i915_gem_object_unpin(obj);
613 mutex_unlock(&dev->struct_mutex);
619 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
620 * the memory and maps it using kmap_atomic for copying.
622 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
623 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
626 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
627 struct drm_i915_gem_pwrite *args,
628 struct drm_file *file_priv)
630 struct drm_i915_gem_object *obj_priv = obj->driver_private;
631 drm_i915_private_t *dev_priv = dev->dev_private;
633 loff_t gtt_page_base, offset;
634 loff_t first_data_page, last_data_page, num_pages;
635 loff_t pinned_pages, i;
636 struct page **user_pages;
637 struct mm_struct *mm = current->mm;
638 int gtt_page_offset, data_page_offset, data_page_index, page_length;
640 uint64_t data_ptr = args->data_ptr;
644 /* Pin the user pages containing the data. We can't fault while
645 * holding the struct mutex, and all of the pwrite implementations
646 * want to hold it while dereferencing the user data.
648 first_data_page = data_ptr / PAGE_SIZE;
649 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
650 num_pages = last_data_page - first_data_page + 1;
652 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
653 if (user_pages == NULL)
656 down_read(&mm->mmap_sem);
657 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
658 num_pages, 0, 0, user_pages, NULL);
659 up_read(&mm->mmap_sem);
660 if (pinned_pages < num_pages) {
662 goto out_unpin_pages;
665 mutex_lock(&dev->struct_mutex);
666 ret = i915_gem_object_pin(obj, 0);
670 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
672 goto out_unpin_object;
674 obj_priv = obj->driver_private;
675 offset = obj_priv->gtt_offset + args->offset;
678 /* Operation in this page
680 * gtt_page_base = page offset within aperture
681 * gtt_page_offset = offset within page in aperture
682 * data_page_index = page number in get_user_pages return
683 * data_page_offset = offset with data_page_index page.
684 * page_length = bytes to copy for this page
686 gtt_page_base = offset & PAGE_MASK;
687 gtt_page_offset = offset & ~PAGE_MASK;
688 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
689 data_page_offset = data_ptr & ~PAGE_MASK;
691 page_length = remain;
692 if ((gtt_page_offset + page_length) > PAGE_SIZE)
693 page_length = PAGE_SIZE - gtt_page_offset;
694 if ((data_page_offset + page_length) > PAGE_SIZE)
695 page_length = PAGE_SIZE - data_page_offset;
697 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
698 gtt_page_base, gtt_page_offset,
699 user_pages[data_page_index],
703 /* If we get a fault while copying data, then (presumably) our
704 * source page isn't available. Return the error and we'll
705 * retry in the slow path.
708 goto out_unpin_object;
710 remain -= page_length;
711 offset += page_length;
712 data_ptr += page_length;
716 i915_gem_object_unpin(obj);
718 mutex_unlock(&dev->struct_mutex);
720 for (i = 0; i < pinned_pages; i++)
721 page_cache_release(user_pages[i]);
728 * This is the fast shmem pwrite path, which attempts to directly
729 * copy_from_user into the kmapped pages backing the object.
732 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
733 struct drm_i915_gem_pwrite *args,
734 struct drm_file *file_priv)
736 struct drm_i915_gem_object *obj_priv = obj->driver_private;
738 loff_t offset, page_base;
739 char __user *user_data;
740 int page_offset, page_length;
743 user_data = (char __user *) (uintptr_t) args->data_ptr;
746 mutex_lock(&dev->struct_mutex);
748 ret = i915_gem_object_get_pages(obj);
752 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
756 obj_priv = obj->driver_private;
757 offset = args->offset;
761 /* Operation in this page
763 * page_base = page offset within aperture
764 * page_offset = offset within page
765 * page_length = bytes to copy for this page
767 page_base = (offset & ~(PAGE_SIZE-1));
768 page_offset = offset & (PAGE_SIZE-1);
769 page_length = remain;
770 if ((page_offset + remain) > PAGE_SIZE)
771 page_length = PAGE_SIZE - page_offset;
773 ret = fast_shmem_write(obj_priv->pages,
774 page_base, page_offset,
775 user_data, page_length);
779 remain -= page_length;
780 user_data += page_length;
781 offset += page_length;
785 i915_gem_object_put_pages(obj);
787 mutex_unlock(&dev->struct_mutex);
793 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
794 * the memory and maps it using kmap_atomic for copying.
796 * This avoids taking mmap_sem for faulting on the user's address while the
797 * struct_mutex is held.
800 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
801 struct drm_i915_gem_pwrite *args,
802 struct drm_file *file_priv)
804 struct drm_i915_gem_object *obj_priv = obj->driver_private;
805 struct mm_struct *mm = current->mm;
806 struct page **user_pages;
808 loff_t offset, pinned_pages, i;
809 loff_t first_data_page, last_data_page, num_pages;
810 int shmem_page_index, shmem_page_offset;
811 int data_page_index, data_page_offset;
814 uint64_t data_ptr = args->data_ptr;
815 int do_bit17_swizzling;
819 /* Pin the user pages containing the data. We can't fault while
820 * holding the struct mutex, and all of the pwrite implementations
821 * want to hold it while dereferencing the user data.
823 first_data_page = data_ptr / PAGE_SIZE;
824 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
825 num_pages = last_data_page - first_data_page + 1;
827 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
828 if (user_pages == NULL)
831 down_read(&mm->mmap_sem);
832 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
833 num_pages, 0, 0, user_pages, NULL);
834 up_read(&mm->mmap_sem);
835 if (pinned_pages < num_pages) {
837 goto fail_put_user_pages;
840 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
842 mutex_lock(&dev->struct_mutex);
844 ret = i915_gem_object_get_pages(obj);
848 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
852 obj_priv = obj->driver_private;
853 offset = args->offset;
857 /* Operation in this page
859 * shmem_page_index = page number within shmem file
860 * shmem_page_offset = offset within page in shmem file
861 * data_page_index = page number in get_user_pages return
862 * data_page_offset = offset with data_page_index page.
863 * page_length = bytes to copy for this page
865 shmem_page_index = offset / PAGE_SIZE;
866 shmem_page_offset = offset & ~PAGE_MASK;
867 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
868 data_page_offset = data_ptr & ~PAGE_MASK;
870 page_length = remain;
871 if ((shmem_page_offset + page_length) > PAGE_SIZE)
872 page_length = PAGE_SIZE - shmem_page_offset;
873 if ((data_page_offset + page_length) > PAGE_SIZE)
874 page_length = PAGE_SIZE - data_page_offset;
876 if (do_bit17_swizzling) {
877 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
879 user_pages[data_page_index],
884 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
886 user_pages[data_page_index],
893 remain -= page_length;
894 data_ptr += page_length;
895 offset += page_length;
899 i915_gem_object_put_pages(obj);
901 mutex_unlock(&dev->struct_mutex);
903 for (i = 0; i < pinned_pages; i++)
904 page_cache_release(user_pages[i]);
911 * Writes data to the object referenced by handle.
913 * On error, the contents of the buffer that were to be modified are undefined.
916 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
917 struct drm_file *file_priv)
919 struct drm_i915_gem_pwrite *args = data;
920 struct drm_gem_object *obj;
921 struct drm_i915_gem_object *obj_priv;
924 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
927 obj_priv = obj->driver_private;
929 /* Bounds check destination.
931 * XXX: This could use review for overflow issues...
933 if (args->offset > obj->size || args->size > obj->size ||
934 args->offset + args->size > obj->size) {
935 drm_gem_object_unreference(obj);
939 /* We can only do the GTT pwrite on untiled buffers, as otherwise
940 * it would end up going through the fenced access, and we'll get
941 * different detiling behavior between reading and writing.
942 * pread/pwrite currently are reading and writing from the CPU
943 * perspective, requiring manual detiling by the client.
945 if (obj_priv->phys_obj)
946 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
947 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
948 dev->gtt_total != 0) {
949 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
950 if (ret == -EFAULT) {
951 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
954 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
955 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
957 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
958 if (ret == -EFAULT) {
959 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
966 DRM_INFO("pwrite failed %d\n", ret);
969 drm_gem_object_unreference(obj);
975 * Called when user space prepares to use an object with the CPU, either
976 * through the mmap ioctl's mapping or a GTT mapping.
979 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
980 struct drm_file *file_priv)
982 struct drm_i915_gem_set_domain *args = data;
983 struct drm_gem_object *obj;
984 uint32_t read_domains = args->read_domains;
985 uint32_t write_domain = args->write_domain;
988 if (!(dev->driver->driver_features & DRIVER_GEM))
991 /* Only handle setting domains to types used by the CPU. */
992 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
995 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
998 /* Having something in the write domain implies it's in the read
999 * domain, and only that read domain. Enforce that in the request.
1001 if (write_domain != 0 && read_domains != write_domain)
1004 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1008 mutex_lock(&dev->struct_mutex);
1010 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
1011 obj, obj->size, read_domains, write_domain);
1013 if (read_domains & I915_GEM_DOMAIN_GTT) {
1014 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1016 /* Silently promote "you're not bound, there was nothing to do"
1017 * to success, since the client was just asking us to
1018 * make sure everything was done.
1023 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1026 drm_gem_object_unreference(obj);
1027 mutex_unlock(&dev->struct_mutex);
1032 * Called when user space has done writes to this buffer
1035 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1036 struct drm_file *file_priv)
1038 struct drm_i915_gem_sw_finish *args = data;
1039 struct drm_gem_object *obj;
1040 struct drm_i915_gem_object *obj_priv;
1043 if (!(dev->driver->driver_features & DRIVER_GEM))
1046 mutex_lock(&dev->struct_mutex);
1047 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1049 mutex_unlock(&dev->struct_mutex);
1054 DRM_INFO("%s: sw_finish %d (%p %d)\n",
1055 __func__, args->handle, obj, obj->size);
1057 obj_priv = obj->driver_private;
1059 /* Pinned buffers may be scanout, so flush the cache */
1060 if (obj_priv->pin_count)
1061 i915_gem_object_flush_cpu_write_domain(obj);
1063 drm_gem_object_unreference(obj);
1064 mutex_unlock(&dev->struct_mutex);
1069 * Maps the contents of an object, returning the address it is mapped
1072 * While the mapping holds a reference on the contents of the object, it doesn't
1073 * imply a ref on the object itself.
1076 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv)
1079 struct drm_i915_gem_mmap *args = data;
1080 struct drm_gem_object *obj;
1084 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 offset = args->offset;
1093 down_write(¤t->mm->mmap_sem);
1094 addr = do_mmap(obj->filp, 0, args->size,
1095 PROT_READ | PROT_WRITE, MAP_SHARED,
1097 up_write(¤t->mm->mmap_sem);
1098 mutex_lock(&dev->struct_mutex);
1099 drm_gem_object_unreference(obj);
1100 mutex_unlock(&dev->struct_mutex);
1101 if (IS_ERR((void *)addr))
1104 args->addr_ptr = (uint64_t) addr;
1110 * i915_gem_fault - fault a page into the GTT
1111 * vma: VMA in question
1114 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1115 * from userspace. The fault handler takes care of binding the object to
1116 * the GTT (if needed), allocating and programming a fence register (again,
1117 * only if needed based on whether the old reg is still valid or the object
1118 * is tiled) and inserting a new PTE into the faulting process.
1120 * Note that the faulting process may involve evicting existing objects
1121 * from the GTT and/or fence registers to make room. So performance may
1122 * suffer if the GTT working set is large or there are few fence registers
1125 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1127 struct drm_gem_object *obj = vma->vm_private_data;
1128 struct drm_device *dev = obj->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1131 pgoff_t page_offset;
1134 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1136 /* We don't use vmf->pgoff since that has the fake offset */
1137 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1140 /* Now bind it into the GTT if needed */
1141 mutex_lock(&dev->struct_mutex);
1142 if (!obj_priv->gtt_space) {
1143 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1145 mutex_unlock(&dev->struct_mutex);
1146 return VM_FAULT_SIGBUS;
1148 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
1151 /* Need a new fence register? */
1152 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1153 obj_priv->tiling_mode != I915_TILING_NONE) {
1154 ret = i915_gem_object_get_fence_reg(obj, write);
1156 mutex_unlock(&dev->struct_mutex);
1157 return VM_FAULT_SIGBUS;
1161 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1164 /* Finally, remap it using the new GTT offset */
1165 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1167 mutex_unlock(&dev->struct_mutex);
1172 return VM_FAULT_OOM;
1175 return VM_FAULT_SIGBUS;
1177 return VM_FAULT_NOPAGE;
1182 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1183 * @obj: obj in question
1185 * GEM memory mapping works by handing back to userspace a fake mmap offset
1186 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1187 * up the object based on the offset and sets up the various memory mapping
1190 * This routine allocates and attaches a fake offset for @obj.
1193 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1195 struct drm_device *dev = obj->dev;
1196 struct drm_gem_mm *mm = dev->mm_private;
1197 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1198 struct drm_map_list *list;
1199 struct drm_local_map *map;
1202 /* Set the object up for mmap'ing */
1203 list = &obj->map_list;
1204 list->map = drm_calloc(1, sizeof(struct drm_map_list),
1210 map->type = _DRM_GEM;
1211 map->size = obj->size;
1214 /* Get a DRM GEM mmap offset allocated... */
1215 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1216 obj->size / PAGE_SIZE, 0, 0);
1217 if (!list->file_offset_node) {
1218 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1223 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1224 obj->size / PAGE_SIZE, 0);
1225 if (!list->file_offset_node) {
1230 list->hash.key = list->file_offset_node->start;
1231 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1232 DRM_ERROR("failed to add to map hash\n");
1236 /* By now we should be all set, any drm_mmap request on the offset
1237 * below will get to our mmap & fault handler */
1238 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1243 drm_mm_put_block(list->file_offset_node);
1245 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
1251 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1253 struct drm_device *dev = obj->dev;
1254 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1255 struct drm_gem_mm *mm = dev->mm_private;
1256 struct drm_map_list *list;
1258 list = &obj->map_list;
1259 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1261 if (list->file_offset_node) {
1262 drm_mm_put_block(list->file_offset_node);
1263 list->file_offset_node = NULL;
1267 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
1271 obj_priv->mmap_offset = 0;
1275 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1276 * @obj: object to check
1278 * Return the required GTT alignment for an object, taking into account
1279 * potential fence register mapping if needed.
1282 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1284 struct drm_device *dev = obj->dev;
1285 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1289 * Minimum alignment is 4k (GTT page size), but might be greater
1290 * if a fence register is needed for the object.
1292 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1296 * Previous chips need to be aligned to the size of the smallest
1297 * fence register that can contain the object.
1304 for (i = start; i < obj->size; i <<= 1)
1311 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1313 * @data: GTT mapping ioctl data
1314 * @file_priv: GEM object info
1316 * Simply returns the fake offset to userspace so it can mmap it.
1317 * The mmap call will end up in drm_gem_mmap(), which will set things
1318 * up so we can get faults in the handler above.
1320 * The fault handler will take care of binding the object into the GTT
1321 * (since it may have been evicted to make room for something), allocating
1322 * a fence register, and mapping the appropriate aperture address into
1326 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *file_priv)
1329 struct drm_i915_gem_mmap_gtt *args = data;
1330 struct drm_i915_private *dev_priv = dev->dev_private;
1331 struct drm_gem_object *obj;
1332 struct drm_i915_gem_object *obj_priv;
1335 if (!(dev->driver->driver_features & DRIVER_GEM))
1338 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1342 mutex_lock(&dev->struct_mutex);
1344 obj_priv = obj->driver_private;
1346 if (!obj_priv->mmap_offset) {
1347 ret = i915_gem_create_mmap_offset(obj);
1349 drm_gem_object_unreference(obj);
1350 mutex_unlock(&dev->struct_mutex);
1355 args->offset = obj_priv->mmap_offset;
1357 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1359 /* Make sure the alignment is correct for fence regs etc */
1360 if (obj_priv->agp_mem &&
1361 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1362 drm_gem_object_unreference(obj);
1363 mutex_unlock(&dev->struct_mutex);
1368 * Pull it into the GTT so that we have a page list (makes the
1369 * initial fault faster and any subsequent flushing possible).
1371 if (!obj_priv->agp_mem) {
1372 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1374 drm_gem_object_unreference(obj);
1375 mutex_unlock(&dev->struct_mutex);
1378 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
1381 drm_gem_object_unreference(obj);
1382 mutex_unlock(&dev->struct_mutex);
1388 i915_gem_object_put_pages(struct drm_gem_object *obj)
1390 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1391 int page_count = obj->size / PAGE_SIZE;
1394 BUG_ON(obj_priv->pages_refcount == 0);
1396 if (--obj_priv->pages_refcount != 0)
1399 if (obj_priv->tiling_mode != I915_TILING_NONE)
1400 i915_gem_object_save_bit_17_swizzle(obj);
1402 for (i = 0; i < page_count; i++)
1403 if (obj_priv->pages[i] != NULL) {
1404 if (obj_priv->dirty)
1405 set_page_dirty(obj_priv->pages[i]);
1406 mark_page_accessed(obj_priv->pages[i]);
1407 page_cache_release(obj_priv->pages[i]);
1409 obj_priv->dirty = 0;
1411 drm_free(obj_priv->pages,
1412 page_count * sizeof(struct page *),
1414 obj_priv->pages = NULL;
1418 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1420 struct drm_device *dev = obj->dev;
1421 drm_i915_private_t *dev_priv = dev->dev_private;
1422 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1424 /* Add a reference if we're newly entering the active list. */
1425 if (!obj_priv->active) {
1426 drm_gem_object_reference(obj);
1427 obj_priv->active = 1;
1429 /* Move from whatever list we were on to the tail of execution. */
1430 spin_lock(&dev_priv->mm.active_list_lock);
1431 list_move_tail(&obj_priv->list,
1432 &dev_priv->mm.active_list);
1433 spin_unlock(&dev_priv->mm.active_list_lock);
1434 obj_priv->last_rendering_seqno = seqno;
1438 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1440 struct drm_device *dev = obj->dev;
1441 drm_i915_private_t *dev_priv = dev->dev_private;
1442 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1444 BUG_ON(!obj_priv->active);
1445 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1446 obj_priv->last_rendering_seqno = 0;
1450 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1452 struct drm_device *dev = obj->dev;
1453 drm_i915_private_t *dev_priv = dev->dev_private;
1454 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1456 i915_verify_inactive(dev, __FILE__, __LINE__);
1457 if (obj_priv->pin_count != 0)
1458 list_del_init(&obj_priv->list);
1460 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1462 obj_priv->last_rendering_seqno = 0;
1463 if (obj_priv->active) {
1464 obj_priv->active = 0;
1465 drm_gem_object_unreference(obj);
1467 i915_verify_inactive(dev, __FILE__, __LINE__);
1471 * Creates a new sequence number, emitting a write of it to the status page
1472 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1474 * Must be called with struct_lock held.
1476 * Returned sequence numbers are nonzero on success.
1479 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
1481 drm_i915_private_t *dev_priv = dev->dev_private;
1482 struct drm_i915_gem_request *request;
1487 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
1488 if (request == NULL)
1491 /* Grab the seqno we're going to make this request be, and bump the
1492 * next (skipping 0 so it can be the reserved no-seqno value).
1494 seqno = dev_priv->mm.next_gem_seqno;
1495 dev_priv->mm.next_gem_seqno++;
1496 if (dev_priv->mm.next_gem_seqno == 0)
1497 dev_priv->mm.next_gem_seqno++;
1500 OUT_RING(MI_STORE_DWORD_INDEX);
1501 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1504 OUT_RING(MI_USER_INTERRUPT);
1507 DRM_DEBUG("%d\n", seqno);
1509 request->seqno = seqno;
1510 request->emitted_jiffies = jiffies;
1511 was_empty = list_empty(&dev_priv->mm.request_list);
1512 list_add_tail(&request->list, &dev_priv->mm.request_list);
1514 /* Associate any objects on the flushing list matching the write
1515 * domain we're flushing with our flush.
1517 if (flush_domains != 0) {
1518 struct drm_i915_gem_object *obj_priv, *next;
1520 list_for_each_entry_safe(obj_priv, next,
1521 &dev_priv->mm.flushing_list, list) {
1522 struct drm_gem_object *obj = obj_priv->obj;
1524 if ((obj->write_domain & flush_domains) ==
1525 obj->write_domain) {
1526 obj->write_domain = 0;
1527 i915_gem_object_move_to_active(obj, seqno);
1533 if (was_empty && !dev_priv->mm.suspended)
1534 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1539 * Command execution barrier
1541 * Ensures that all commands in the ring are finished
1542 * before signalling the CPU
1545 i915_retire_commands(struct drm_device *dev)
1547 drm_i915_private_t *dev_priv = dev->dev_private;
1548 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1549 uint32_t flush_domains = 0;
1552 /* The sampler always gets flushed on i965 (sigh) */
1554 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1557 OUT_RING(0); /* noop */
1559 return flush_domains;
1563 * Moves buffers associated only with the given active seqno from the active
1564 * to inactive list, potentially freeing them.
1567 i915_gem_retire_request(struct drm_device *dev,
1568 struct drm_i915_gem_request *request)
1570 drm_i915_private_t *dev_priv = dev->dev_private;
1572 /* Move any buffers on the active list that are no longer referenced
1573 * by the ringbuffer to the flushing/inactive lists as appropriate.
1575 spin_lock(&dev_priv->mm.active_list_lock);
1576 while (!list_empty(&dev_priv->mm.active_list)) {
1577 struct drm_gem_object *obj;
1578 struct drm_i915_gem_object *obj_priv;
1580 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1581 struct drm_i915_gem_object,
1583 obj = obj_priv->obj;
1585 /* If the seqno being retired doesn't match the oldest in the
1586 * list, then the oldest in the list must still be newer than
1589 if (obj_priv->last_rendering_seqno != request->seqno)
1593 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1594 __func__, request->seqno, obj);
1597 if (obj->write_domain != 0)
1598 i915_gem_object_move_to_flushing(obj);
1600 i915_gem_object_move_to_inactive(obj);
1603 spin_unlock(&dev_priv->mm.active_list_lock);
1607 * Returns true if seq1 is later than seq2.
1610 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1612 return (int32_t)(seq1 - seq2) >= 0;
1616 i915_get_gem_seqno(struct drm_device *dev)
1618 drm_i915_private_t *dev_priv = dev->dev_private;
1620 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1624 * This function clears the request list as sequence numbers are passed.
1627 i915_gem_retire_requests(struct drm_device *dev)
1629 drm_i915_private_t *dev_priv = dev->dev_private;
1632 if (!dev_priv->hw_status_page)
1635 seqno = i915_get_gem_seqno(dev);
1637 while (!list_empty(&dev_priv->mm.request_list)) {
1638 struct drm_i915_gem_request *request;
1639 uint32_t retiring_seqno;
1641 request = list_first_entry(&dev_priv->mm.request_list,
1642 struct drm_i915_gem_request,
1644 retiring_seqno = request->seqno;
1646 if (i915_seqno_passed(seqno, retiring_seqno) ||
1647 dev_priv->mm.wedged) {
1648 i915_gem_retire_request(dev, request);
1650 list_del(&request->list);
1651 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1658 i915_gem_retire_work_handler(struct work_struct *work)
1660 drm_i915_private_t *dev_priv;
1661 struct drm_device *dev;
1663 dev_priv = container_of(work, drm_i915_private_t,
1664 mm.retire_work.work);
1665 dev = dev_priv->dev;
1667 mutex_lock(&dev->struct_mutex);
1668 i915_gem_retire_requests(dev);
1669 if (!dev_priv->mm.suspended &&
1670 !list_empty(&dev_priv->mm.request_list))
1671 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1672 mutex_unlock(&dev->struct_mutex);
1676 * Waits for a sequence number to be signaled, and cleans up the
1677 * request and object lists appropriately for that event.
1680 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1682 drm_i915_private_t *dev_priv = dev->dev_private;
1687 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1688 dev_priv->mm.waiting_gem_seqno = seqno;
1689 i915_user_irq_get(dev);
1690 ret = wait_event_interruptible(dev_priv->irq_queue,
1691 i915_seqno_passed(i915_get_gem_seqno(dev),
1693 dev_priv->mm.wedged);
1694 i915_user_irq_put(dev);
1695 dev_priv->mm.waiting_gem_seqno = 0;
1697 if (dev_priv->mm.wedged)
1700 if (ret && ret != -ERESTARTSYS)
1701 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1702 __func__, ret, seqno, i915_get_gem_seqno(dev));
1704 /* Directly dispatch request retiring. While we have the work queue
1705 * to handle this, the waiter on a request often wants an associated
1706 * buffer to have made it to the inactive list, and we would need
1707 * a separate wait queue to handle that.
1710 i915_gem_retire_requests(dev);
1716 i915_gem_flush(struct drm_device *dev,
1717 uint32_t invalidate_domains,
1718 uint32_t flush_domains)
1720 drm_i915_private_t *dev_priv = dev->dev_private;
1725 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1726 invalidate_domains, flush_domains);
1729 if (flush_domains & I915_GEM_DOMAIN_CPU)
1730 drm_agp_chipset_flush(dev);
1732 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1733 I915_GEM_DOMAIN_GTT)) {
1735 * read/write caches:
1737 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1738 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1739 * also flushed at 2d versus 3d pipeline switches.
1743 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1744 * MI_READ_FLUSH is set, and is always flushed on 965.
1746 * I915_GEM_DOMAIN_COMMAND may not exist?
1748 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1749 * invalidated when MI_EXE_FLUSH is set.
1751 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1752 * invalidated with every MI_FLUSH.
1756 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1757 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1758 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1759 * are flushed at any MI_FLUSH.
1762 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1763 if ((invalidate_domains|flush_domains) &
1764 I915_GEM_DOMAIN_RENDER)
1765 cmd &= ~MI_NO_WRITE_FLUSH;
1766 if (!IS_I965G(dev)) {
1768 * On the 965, the sampler cache always gets flushed
1769 * and this bit is reserved.
1771 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1772 cmd |= MI_READ_FLUSH;
1774 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1775 cmd |= MI_EXE_FLUSH;
1778 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1782 OUT_RING(0); /* noop */
1788 * Ensures that all rendering to the object has completed and the object is
1789 * safe to unbind from the GTT or access from the CPU.
1792 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1794 struct drm_device *dev = obj->dev;
1795 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1798 /* This function only exists to support waiting for existing rendering,
1799 * not for emitting required flushes.
1801 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1803 /* If there is rendering queued on the buffer being evicted, wait for
1806 if (obj_priv->active) {
1808 DRM_INFO("%s: object %p wait for seqno %08x\n",
1809 __func__, obj, obj_priv->last_rendering_seqno);
1811 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1820 * Unbinds an object from the GTT aperture.
1823 i915_gem_object_unbind(struct drm_gem_object *obj)
1825 struct drm_device *dev = obj->dev;
1826 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1831 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1832 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1834 if (obj_priv->gtt_space == NULL)
1837 if (obj_priv->pin_count != 0) {
1838 DRM_ERROR("Attempting to unbind pinned buffer\n");
1842 /* Move the object to the CPU domain to ensure that
1843 * any possible CPU writes while it's not in the GTT
1844 * are flushed when we go to remap it. This will
1845 * also ensure that all pending GPU writes are finished
1848 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1850 if (ret != -ERESTARTSYS)
1851 DRM_ERROR("set_domain failed: %d\n", ret);
1855 if (obj_priv->agp_mem != NULL) {
1856 drm_unbind_agp(obj_priv->agp_mem);
1857 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1858 obj_priv->agp_mem = NULL;
1861 BUG_ON(obj_priv->active);
1863 /* blow away mappings if mapped through GTT */
1864 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1865 if (dev->dev_mapping)
1866 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1868 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1869 i915_gem_clear_fence_reg(obj);
1871 i915_gem_object_put_pages(obj);
1873 if (obj_priv->gtt_space) {
1874 atomic_dec(&dev->gtt_count);
1875 atomic_sub(obj->size, &dev->gtt_memory);
1877 drm_mm_put_block(obj_priv->gtt_space);
1878 obj_priv->gtt_space = NULL;
1881 /* Remove ourselves from the LRU list if present. */
1882 if (!list_empty(&obj_priv->list))
1883 list_del_init(&obj_priv->list);
1889 i915_gem_evict_something(struct drm_device *dev)
1891 drm_i915_private_t *dev_priv = dev->dev_private;
1892 struct drm_gem_object *obj;
1893 struct drm_i915_gem_object *obj_priv;
1897 /* If there's an inactive buffer available now, grab it
1900 if (!list_empty(&dev_priv->mm.inactive_list)) {
1901 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1902 struct drm_i915_gem_object,
1904 obj = obj_priv->obj;
1905 BUG_ON(obj_priv->pin_count != 0);
1907 DRM_INFO("%s: evicting %p\n", __func__, obj);
1909 BUG_ON(obj_priv->active);
1911 /* Wait on the rendering and unbind the buffer. */
1912 ret = i915_gem_object_unbind(obj);
1916 /* If we didn't get anything, but the ring is still processing
1917 * things, wait for one of those things to finish and hopefully
1918 * leave us a buffer to evict.
1920 if (!list_empty(&dev_priv->mm.request_list)) {
1921 struct drm_i915_gem_request *request;
1923 request = list_first_entry(&dev_priv->mm.request_list,
1924 struct drm_i915_gem_request,
1927 ret = i915_wait_request(dev, request->seqno);
1931 /* if waiting caused an object to become inactive,
1932 * then loop around and wait for it. Otherwise, we
1933 * assume that waiting freed and unbound something,
1934 * so there should now be some space in the GTT
1936 if (!list_empty(&dev_priv->mm.inactive_list))
1941 /* If we didn't have anything on the request list but there
1942 * are buffers awaiting a flush, emit one and try again.
1943 * When we wait on it, those buffers waiting for that flush
1944 * will get moved to inactive.
1946 if (!list_empty(&dev_priv->mm.flushing_list)) {
1947 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1948 struct drm_i915_gem_object,
1950 obj = obj_priv->obj;
1955 i915_add_request(dev, obj->write_domain);
1961 DRM_ERROR("inactive empty %d request empty %d "
1962 "flushing empty %d\n",
1963 list_empty(&dev_priv->mm.inactive_list),
1964 list_empty(&dev_priv->mm.request_list),
1965 list_empty(&dev_priv->mm.flushing_list));
1966 /* If we didn't do any of the above, there's nothing to be done
1967 * and we just can't fit it in.
1975 i915_gem_evict_everything(struct drm_device *dev)
1980 ret = i915_gem_evict_something(dev);
1990 i915_gem_object_get_pages(struct drm_gem_object *obj)
1992 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1994 struct address_space *mapping;
1995 struct inode *inode;
1999 if (obj_priv->pages_refcount++ != 0)
2002 /* Get the list of pages out of our struct file. They'll be pinned
2003 * at this point until we release them.
2005 page_count = obj->size / PAGE_SIZE;
2006 BUG_ON(obj_priv->pages != NULL);
2007 obj_priv->pages = drm_calloc(page_count, sizeof(struct page *),
2009 if (obj_priv->pages == NULL) {
2010 DRM_ERROR("Faled to allocate page list\n");
2011 obj_priv->pages_refcount--;
2015 inode = obj->filp->f_path.dentry->d_inode;
2016 mapping = inode->i_mapping;
2017 for (i = 0; i < page_count; i++) {
2018 page = read_mapping_page(mapping, i, NULL);
2020 ret = PTR_ERR(page);
2021 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2022 i915_gem_object_put_pages(obj);
2025 obj_priv->pages[i] = page;
2028 if (obj_priv->tiling_mode != I915_TILING_NONE)
2029 i915_gem_object_do_bit_17_swizzle(obj);
2034 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2036 struct drm_gem_object *obj = reg->obj;
2037 struct drm_device *dev = obj->dev;
2038 drm_i915_private_t *dev_priv = dev->dev_private;
2039 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2040 int regnum = obj_priv->fence_reg;
2043 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2045 val |= obj_priv->gtt_offset & 0xfffff000;
2046 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2047 if (obj_priv->tiling_mode == I915_TILING_Y)
2048 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2049 val |= I965_FENCE_REG_VALID;
2051 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2054 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2056 struct drm_gem_object *obj = reg->obj;
2057 struct drm_device *dev = obj->dev;
2058 drm_i915_private_t *dev_priv = dev->dev_private;
2059 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2060 int regnum = obj_priv->fence_reg;
2062 uint32_t fence_reg, val;
2065 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2066 (obj_priv->gtt_offset & (obj->size - 1))) {
2067 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2068 __func__, obj_priv->gtt_offset, obj->size);
2072 if (obj_priv->tiling_mode == I915_TILING_Y &&
2073 HAS_128_BYTE_Y_TILING(dev))
2078 /* Note: pitch better be a power of two tile widths */
2079 pitch_val = obj_priv->stride / tile_width;
2080 pitch_val = ffs(pitch_val) - 1;
2082 val = obj_priv->gtt_offset;
2083 if (obj_priv->tiling_mode == I915_TILING_Y)
2084 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2085 val |= I915_FENCE_SIZE_BITS(obj->size);
2086 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2087 val |= I830_FENCE_REG_VALID;
2090 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2092 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2093 I915_WRITE(fence_reg, val);
2096 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2098 struct drm_gem_object *obj = reg->obj;
2099 struct drm_device *dev = obj->dev;
2100 drm_i915_private_t *dev_priv = dev->dev_private;
2101 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2102 int regnum = obj_priv->fence_reg;
2105 uint32_t fence_size_bits;
2107 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2108 (obj_priv->gtt_offset & (obj->size - 1))) {
2109 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2110 __func__, obj_priv->gtt_offset);
2114 pitch_val = (obj_priv->stride / 128) - 1;
2115 WARN_ON(pitch_val & ~0x0000000f);
2116 val = obj_priv->gtt_offset;
2117 if (obj_priv->tiling_mode == I915_TILING_Y)
2118 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2119 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2120 WARN_ON(fence_size_bits & ~0x00000f00);
2121 val |= fence_size_bits;
2122 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2123 val |= I830_FENCE_REG_VALID;
2125 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2130 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2131 * @obj: object to map through a fence reg
2132 * @write: object is about to be written
2134 * When mapping objects through the GTT, userspace wants to be able to write
2135 * to them without having to worry about swizzling if the object is tiled.
2137 * This function walks the fence regs looking for a free one for @obj,
2138 * stealing one if it can't find any.
2140 * It then sets up the reg based on the object's properties: address, pitch
2141 * and tiling format.
2144 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
2146 struct drm_device *dev = obj->dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2149 struct drm_i915_fence_reg *reg = NULL;
2150 struct drm_i915_gem_object *old_obj_priv = NULL;
2153 switch (obj_priv->tiling_mode) {
2154 case I915_TILING_NONE:
2155 WARN(1, "allocating a fence for non-tiled object?\n");
2158 if (!obj_priv->stride)
2160 WARN((obj_priv->stride & (512 - 1)),
2161 "object 0x%08x is X tiled but has non-512B pitch\n",
2162 obj_priv->gtt_offset);
2165 if (!obj_priv->stride)
2167 WARN((obj_priv->stride & (128 - 1)),
2168 "object 0x%08x is Y tiled but has non-128B pitch\n",
2169 obj_priv->gtt_offset);
2173 /* First try to find a free reg */
2176 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2177 reg = &dev_priv->fence_regs[i];
2181 old_obj_priv = reg->obj->driver_private;
2182 if (!old_obj_priv->pin_count)
2186 /* None available, try to steal one or wait for a user to finish */
2187 if (i == dev_priv->num_fence_regs) {
2188 uint32_t seqno = dev_priv->mm.next_gem_seqno;
2194 for (i = dev_priv->fence_reg_start;
2195 i < dev_priv->num_fence_regs; i++) {
2196 uint32_t this_seqno;
2198 reg = &dev_priv->fence_regs[i];
2199 old_obj_priv = reg->obj->driver_private;
2201 if (old_obj_priv->pin_count)
2204 /* i915 uses fences for GPU access to tiled buffers */
2205 if (IS_I965G(dev) || !old_obj_priv->active)
2208 /* find the seqno of the first available fence */
2209 this_seqno = old_obj_priv->last_rendering_seqno;
2210 if (this_seqno != 0 &&
2211 reg->obj->write_domain == 0 &&
2212 i915_seqno_passed(seqno, this_seqno))
2217 * Now things get ugly... we have to wait for one of the
2218 * objects to finish before trying again.
2220 if (i == dev_priv->num_fence_regs) {
2221 if (seqno == dev_priv->mm.next_gem_seqno) {
2223 I915_GEM_GPU_DOMAINS,
2224 I915_GEM_GPU_DOMAINS);
2225 seqno = i915_add_request(dev,
2226 I915_GEM_GPU_DOMAINS);
2231 ret = i915_wait_request(dev, seqno);
2237 BUG_ON(old_obj_priv->active ||
2238 (reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
2241 * Zap this virtual mapping so we can set up a fence again
2242 * for this object next time we need it.
2244 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
2245 if (dev->dev_mapping)
2246 unmap_mapping_range(dev->dev_mapping, offset,
2248 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2251 obj_priv->fence_reg = i;
2255 i965_write_fence_reg(reg);
2256 else if (IS_I9XX(dev))
2257 i915_write_fence_reg(reg);
2259 i830_write_fence_reg(reg);
2265 * i915_gem_clear_fence_reg - clear out fence register info
2266 * @obj: object to clear
2268 * Zeroes out the fence register itself and clears out the associated
2269 * data structures in dev_priv and obj_priv.
2272 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2274 struct drm_device *dev = obj->dev;
2275 drm_i915_private_t *dev_priv = dev->dev_private;
2276 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2279 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2283 if (obj_priv->fence_reg < 8)
2284 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2286 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2289 I915_WRITE(fence_reg, 0);
2292 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2293 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2297 * Finds free space in the GTT aperture and binds the object there.
2300 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2302 struct drm_device *dev = obj->dev;
2303 drm_i915_private_t *dev_priv = dev->dev_private;
2304 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2305 struct drm_mm_node *free_space;
2306 int page_count, ret;
2308 if (dev_priv->mm.suspended)
2311 alignment = i915_gem_get_gtt_alignment(obj);
2312 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2313 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2318 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2319 obj->size, alignment, 0);
2320 if (free_space != NULL) {
2321 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2323 if (obj_priv->gtt_space != NULL) {
2324 obj_priv->gtt_space->private = obj;
2325 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2328 if (obj_priv->gtt_space == NULL) {
2331 /* If the gtt is empty and we're still having trouble
2332 * fitting our object in, we're out of memory.
2335 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2337 spin_lock(&dev_priv->mm.active_list_lock);
2338 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2339 list_empty(&dev_priv->mm.flushing_list) &&
2340 list_empty(&dev_priv->mm.active_list));
2341 spin_unlock(&dev_priv->mm.active_list_lock);
2343 DRM_ERROR("GTT full, but LRU list empty\n");
2347 ret = i915_gem_evict_something(dev);
2349 if (ret != -ERESTARTSYS)
2350 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2357 DRM_INFO("Binding object of size %d at 0x%08x\n",
2358 obj->size, obj_priv->gtt_offset);
2360 ret = i915_gem_object_get_pages(obj);
2362 drm_mm_put_block(obj_priv->gtt_space);
2363 obj_priv->gtt_space = NULL;
2367 page_count = obj->size / PAGE_SIZE;
2368 /* Create an AGP memory structure pointing at our pages, and bind it
2371 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2374 obj_priv->gtt_offset,
2375 obj_priv->agp_type);
2376 if (obj_priv->agp_mem == NULL) {
2377 i915_gem_object_put_pages(obj);
2378 drm_mm_put_block(obj_priv->gtt_space);
2379 obj_priv->gtt_space = NULL;
2382 atomic_inc(&dev->gtt_count);
2383 atomic_add(obj->size, &dev->gtt_memory);
2385 /* Assert that the object is not currently in any GPU domain. As it
2386 * wasn't in the GTT, there shouldn't be any way it could have been in
2389 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2390 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2396 i915_gem_clflush_object(struct drm_gem_object *obj)
2398 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2400 /* If we don't have a page list set up, then we're not pinned
2401 * to GPU, and we can ignore the cache flush because it'll happen
2402 * again at bind time.
2404 if (obj_priv->pages == NULL)
2407 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2410 /** Flushes any GPU write domain for the object if it's dirty. */
2412 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2414 struct drm_device *dev = obj->dev;
2417 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2420 /* Queue the GPU write cache flushing we need. */
2421 i915_gem_flush(dev, 0, obj->write_domain);
2422 seqno = i915_add_request(dev, obj->write_domain);
2423 obj->write_domain = 0;
2424 i915_gem_object_move_to_active(obj, seqno);
2427 /** Flushes the GTT write domain for the object if it's dirty. */
2429 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2431 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2434 /* No actual flushing is required for the GTT write domain. Writes
2435 * to it immediately go to main memory as far as we know, so there's
2436 * no chipset flush. It also doesn't land in render cache.
2438 obj->write_domain = 0;
2441 /** Flushes the CPU write domain for the object if it's dirty. */
2443 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2445 struct drm_device *dev = obj->dev;
2447 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2450 i915_gem_clflush_object(obj);
2451 drm_agp_chipset_flush(dev);
2452 obj->write_domain = 0;
2456 * Moves a single object to the GTT read, and possibly write domain.
2458 * This function returns when the move is complete, including waiting on
2462 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2464 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2467 /* Not valid to be called on unbound objects. */
2468 if (obj_priv->gtt_space == NULL)
2471 i915_gem_object_flush_gpu_write_domain(obj);
2472 /* Wait on any GPU rendering and flushing to occur. */
2473 ret = i915_gem_object_wait_rendering(obj);
2477 /* If we're writing through the GTT domain, then CPU and GPU caches
2478 * will need to be invalidated at next use.
2481 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2483 i915_gem_object_flush_cpu_write_domain(obj);
2485 /* It should now be out of any other write domains, and we can update
2486 * the domain values for our changes.
2488 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2489 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2491 obj->write_domain = I915_GEM_DOMAIN_GTT;
2492 obj_priv->dirty = 1;
2499 * Moves a single object to the CPU read, and possibly write domain.
2501 * This function returns when the move is complete, including waiting on
2505 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2509 i915_gem_object_flush_gpu_write_domain(obj);
2510 /* Wait on any GPU rendering and flushing to occur. */
2511 ret = i915_gem_object_wait_rendering(obj);
2515 i915_gem_object_flush_gtt_write_domain(obj);
2517 /* If we have a partially-valid cache of the object in the CPU,
2518 * finish invalidating it and free the per-page flags.
2520 i915_gem_object_set_to_full_cpu_read_domain(obj);
2522 /* Flush the CPU cache if it's still invalid. */
2523 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2524 i915_gem_clflush_object(obj);
2526 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2529 /* It should now be out of any other write domains, and we can update
2530 * the domain values for our changes.
2532 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2534 /* If we're writing through the CPU, then the GPU read domains will
2535 * need to be invalidated at next use.
2538 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2539 obj->write_domain = I915_GEM_DOMAIN_CPU;
2546 * Set the next domain for the specified object. This
2547 * may not actually perform the necessary flushing/invaliding though,
2548 * as that may want to be batched with other set_domain operations
2550 * This is (we hope) the only really tricky part of gem. The goal
2551 * is fairly simple -- track which caches hold bits of the object
2552 * and make sure they remain coherent. A few concrete examples may
2553 * help to explain how it works. For shorthand, we use the notation
2554 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2555 * a pair of read and write domain masks.
2557 * Case 1: the batch buffer
2563 * 5. Unmapped from GTT
2566 * Let's take these a step at a time
2569 * Pages allocated from the kernel may still have
2570 * cache contents, so we set them to (CPU, CPU) always.
2571 * 2. Written by CPU (using pwrite)
2572 * The pwrite function calls set_domain (CPU, CPU) and
2573 * this function does nothing (as nothing changes)
2575 * This function asserts that the object is not
2576 * currently in any GPU-based read or write domains
2578 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2579 * As write_domain is zero, this function adds in the
2580 * current read domains (CPU+COMMAND, 0).
2581 * flush_domains is set to CPU.
2582 * invalidate_domains is set to COMMAND
2583 * clflush is run to get data out of the CPU caches
2584 * then i915_dev_set_domain calls i915_gem_flush to
2585 * emit an MI_FLUSH and drm_agp_chipset_flush
2586 * 5. Unmapped from GTT
2587 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2588 * flush_domains and invalidate_domains end up both zero
2589 * so no flushing/invalidating happens
2593 * Case 2: The shared render buffer
2597 * 3. Read/written by GPU
2598 * 4. set_domain to (CPU,CPU)
2599 * 5. Read/written by CPU
2600 * 6. Read/written by GPU
2603 * Same as last example, (CPU, CPU)
2605 * Nothing changes (assertions find that it is not in the GPU)
2606 * 3. Read/written by GPU
2607 * execbuffer calls set_domain (RENDER, RENDER)
2608 * flush_domains gets CPU
2609 * invalidate_domains gets GPU
2611 * MI_FLUSH and drm_agp_chipset_flush
2612 * 4. set_domain (CPU, CPU)
2613 * flush_domains gets GPU
2614 * invalidate_domains gets CPU
2615 * wait_rendering (obj) to make sure all drawing is complete.
2616 * This will include an MI_FLUSH to get the data from GPU
2618 * clflush (obj) to invalidate the CPU cache
2619 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2620 * 5. Read/written by CPU
2621 * cache lines are loaded and dirtied
2622 * 6. Read written by GPU
2623 * Same as last GPU access
2625 * Case 3: The constant buffer
2630 * 4. Updated (written) by CPU again
2639 * flush_domains = CPU
2640 * invalidate_domains = RENDER
2643 * drm_agp_chipset_flush
2644 * 4. Updated (written) by CPU again
2646 * flush_domains = 0 (no previous write domain)
2647 * invalidate_domains = 0 (no new read domains)
2650 * flush_domains = CPU
2651 * invalidate_domains = RENDER
2654 * drm_agp_chipset_flush
2657 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2659 struct drm_device *dev = obj->dev;
2660 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2661 uint32_t invalidate_domains = 0;
2662 uint32_t flush_domains = 0;
2664 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2665 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2668 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2670 obj->read_domains, obj->pending_read_domains,
2671 obj->write_domain, obj->pending_write_domain);
2674 * If the object isn't moving to a new write domain,
2675 * let the object stay in multiple read domains
2677 if (obj->pending_write_domain == 0)
2678 obj->pending_read_domains |= obj->read_domains;
2680 obj_priv->dirty = 1;
2683 * Flush the current write domain if
2684 * the new read domains don't match. Invalidate
2685 * any read domains which differ from the old
2688 if (obj->write_domain &&
2689 obj->write_domain != obj->pending_read_domains) {
2690 flush_domains |= obj->write_domain;
2691 invalidate_domains |=
2692 obj->pending_read_domains & ~obj->write_domain;
2695 * Invalidate any read caches which may have
2696 * stale data. That is, any new read domains.
2698 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2699 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2701 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2702 __func__, flush_domains, invalidate_domains);
2704 i915_gem_clflush_object(obj);
2707 /* The actual obj->write_domain will be updated with
2708 * pending_write_domain after we emit the accumulated flush for all
2709 * of our domain changes in execbuffers (which clears objects'
2710 * write_domains). So if we have a current write domain that we
2711 * aren't changing, set pending_write_domain to that.
2713 if (flush_domains == 0 && obj->pending_write_domain == 0)
2714 obj->pending_write_domain = obj->write_domain;
2715 obj->read_domains = obj->pending_read_domains;
2717 dev->invalidate_domains |= invalidate_domains;
2718 dev->flush_domains |= flush_domains;
2720 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2722 obj->read_domains, obj->write_domain,
2723 dev->invalidate_domains, dev->flush_domains);
2728 * Moves the object from a partially CPU read to a full one.
2730 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2731 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2734 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2736 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2738 if (!obj_priv->page_cpu_valid)
2741 /* If we're partially in the CPU read domain, finish moving it in.
2743 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2746 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2747 if (obj_priv->page_cpu_valid[i])
2749 drm_clflush_pages(obj_priv->pages + i, 1);
2753 /* Free the page_cpu_valid mappings which are now stale, whether
2754 * or not we've got I915_GEM_DOMAIN_CPU.
2756 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2758 obj_priv->page_cpu_valid = NULL;
2762 * Set the CPU read domain on a range of the object.
2764 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2765 * not entirely valid. The page_cpu_valid member of the object flags which
2766 * pages have been flushed, and will be respected by
2767 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2768 * of the whole object.
2770 * This function returns when the move is complete, including waiting on
2774 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2775 uint64_t offset, uint64_t size)
2777 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2780 if (offset == 0 && size == obj->size)
2781 return i915_gem_object_set_to_cpu_domain(obj, 0);
2783 i915_gem_object_flush_gpu_write_domain(obj);
2784 /* Wait on any GPU rendering and flushing to occur. */
2785 ret = i915_gem_object_wait_rendering(obj);
2788 i915_gem_object_flush_gtt_write_domain(obj);
2790 /* If we're already fully in the CPU read domain, we're done. */
2791 if (obj_priv->page_cpu_valid == NULL &&
2792 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2795 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2796 * newly adding I915_GEM_DOMAIN_CPU
2798 if (obj_priv->page_cpu_valid == NULL) {
2799 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2801 if (obj_priv->page_cpu_valid == NULL)
2803 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2804 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2806 /* Flush the cache on any pages that are still invalid from the CPU's
2809 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2811 if (obj_priv->page_cpu_valid[i])
2814 drm_clflush_pages(obj_priv->pages + i, 1);
2816 obj_priv->page_cpu_valid[i] = 1;
2819 /* It should now be out of any other write domains, and we can update
2820 * the domain values for our changes.
2822 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2824 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2830 * Pin an object to the GTT and evaluate the relocations landing in it.
2833 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2834 struct drm_file *file_priv,
2835 struct drm_i915_gem_exec_object *entry,
2836 struct drm_i915_gem_relocation_entry *relocs)
2838 struct drm_device *dev = obj->dev;
2839 drm_i915_private_t *dev_priv = dev->dev_private;
2840 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2842 void __iomem *reloc_page;
2844 /* Choose the GTT offset for our buffer and put it there. */
2845 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2849 entry->offset = obj_priv->gtt_offset;
2851 /* Apply the relocations, using the GTT aperture to avoid cache
2852 * flushing requirements.
2854 for (i = 0; i < entry->relocation_count; i++) {
2855 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2856 struct drm_gem_object *target_obj;
2857 struct drm_i915_gem_object *target_obj_priv;
2858 uint32_t reloc_val, reloc_offset;
2859 uint32_t __iomem *reloc_entry;
2861 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2862 reloc->target_handle);
2863 if (target_obj == NULL) {
2864 i915_gem_object_unpin(obj);
2867 target_obj_priv = target_obj->driver_private;
2869 /* The target buffer should have appeared before us in the
2870 * exec_object list, so it should have a GTT space bound by now.
2872 if (target_obj_priv->gtt_space == NULL) {
2873 DRM_ERROR("No GTT space found for object %d\n",
2874 reloc->target_handle);
2875 drm_gem_object_unreference(target_obj);
2876 i915_gem_object_unpin(obj);
2880 if (reloc->offset > obj->size - 4) {
2881 DRM_ERROR("Relocation beyond object bounds: "
2882 "obj %p target %d offset %d size %d.\n",
2883 obj, reloc->target_handle,
2884 (int) reloc->offset, (int) obj->size);
2885 drm_gem_object_unreference(target_obj);
2886 i915_gem_object_unpin(obj);
2889 if (reloc->offset & 3) {
2890 DRM_ERROR("Relocation not 4-byte aligned: "
2891 "obj %p target %d offset %d.\n",
2892 obj, reloc->target_handle,
2893 (int) reloc->offset);
2894 drm_gem_object_unreference(target_obj);
2895 i915_gem_object_unpin(obj);
2899 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
2900 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
2901 DRM_ERROR("reloc with read/write CPU domains: "
2902 "obj %p target %d offset %d "
2903 "read %08x write %08x",
2904 obj, reloc->target_handle,
2905 (int) reloc->offset,
2906 reloc->read_domains,
2907 reloc->write_domain);
2908 drm_gem_object_unreference(target_obj);
2909 i915_gem_object_unpin(obj);
2913 if (reloc->write_domain && target_obj->pending_write_domain &&
2914 reloc->write_domain != target_obj->pending_write_domain) {
2915 DRM_ERROR("Write domain conflict: "
2916 "obj %p target %d offset %d "
2917 "new %08x old %08x\n",
2918 obj, reloc->target_handle,
2919 (int) reloc->offset,
2920 reloc->write_domain,
2921 target_obj->pending_write_domain);
2922 drm_gem_object_unreference(target_obj);
2923 i915_gem_object_unpin(obj);
2928 DRM_INFO("%s: obj %p offset %08x target %d "
2929 "read %08x write %08x gtt %08x "
2930 "presumed %08x delta %08x\n",
2933 (int) reloc->offset,
2934 (int) reloc->target_handle,
2935 (int) reloc->read_domains,
2936 (int) reloc->write_domain,
2937 (int) target_obj_priv->gtt_offset,
2938 (int) reloc->presumed_offset,
2942 target_obj->pending_read_domains |= reloc->read_domains;
2943 target_obj->pending_write_domain |= reloc->write_domain;
2945 /* If the relocation already has the right value in it, no
2946 * more work needs to be done.
2948 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
2949 drm_gem_object_unreference(target_obj);
2953 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2955 drm_gem_object_unreference(target_obj);
2956 i915_gem_object_unpin(obj);
2960 /* Map the page containing the relocation we're going to
2963 reloc_offset = obj_priv->gtt_offset + reloc->offset;
2964 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2967 reloc_entry = (uint32_t __iomem *)(reloc_page +
2968 (reloc_offset & (PAGE_SIZE - 1)));
2969 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
2972 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2973 obj, (unsigned int) reloc->offset,
2974 readl(reloc_entry), reloc_val);
2976 writel(reloc_val, reloc_entry);
2977 io_mapping_unmap_atomic(reloc_page);
2979 /* The updated presumed offset for this entry will be
2980 * copied back out to the user.
2982 reloc->presumed_offset = target_obj_priv->gtt_offset;
2984 drm_gem_object_unreference(target_obj);
2989 i915_gem_dump_object(obj, 128, __func__, ~0);
2994 /** Dispatch a batchbuffer to the ring
2997 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2998 struct drm_i915_gem_execbuffer *exec,
2999 struct drm_clip_rect *cliprects,
3000 uint64_t exec_offset)
3002 drm_i915_private_t *dev_priv = dev->dev_private;
3003 int nbox = exec->num_cliprects;
3005 uint32_t exec_start, exec_len;
3008 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3009 exec_len = (uint32_t) exec->batch_len;
3011 if ((exec_start | exec_len) & 0x7) {
3012 DRM_ERROR("alignment\n");
3019 count = nbox ? nbox : 1;
3021 for (i = 0; i < count; i++) {
3023 int ret = i915_emit_box(dev, cliprects, i,
3024 exec->DR1, exec->DR4);
3029 if (IS_I830(dev) || IS_845G(dev)) {
3031 OUT_RING(MI_BATCH_BUFFER);
3032 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3033 OUT_RING(exec_start + exec_len - 4);
3038 if (IS_I965G(dev)) {
3039 OUT_RING(MI_BATCH_BUFFER_START |
3041 MI_BATCH_NON_SECURE_I965);
3042 OUT_RING(exec_start);
3044 OUT_RING(MI_BATCH_BUFFER_START |
3046 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3052 /* XXX breadcrumb */
3056 /* Throttle our rendering by waiting until the ring has completed our requests
3057 * emitted over 20 msec ago.
3059 * This should get us reasonable parallelism between CPU and GPU but also
3060 * relatively low latency when blocking on a particular request to finish.
3063 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3065 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3069 mutex_lock(&dev->struct_mutex);
3070 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
3071 i915_file_priv->mm.last_gem_throttle_seqno =
3072 i915_file_priv->mm.last_gem_seqno;
3074 ret = i915_wait_request(dev, seqno);
3075 mutex_unlock(&dev->struct_mutex);
3080 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3081 uint32_t buffer_count,
3082 struct drm_i915_gem_relocation_entry **relocs)
3084 uint32_t reloc_count = 0, reloc_index = 0, i;
3088 for (i = 0; i < buffer_count; i++) {
3089 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3091 reloc_count += exec_list[i].relocation_count;
3094 *relocs = drm_calloc(reloc_count, sizeof(**relocs), DRM_MEM_DRIVER);
3095 if (*relocs == NULL)
3098 for (i = 0; i < buffer_count; i++) {
3099 struct drm_i915_gem_relocation_entry __user *user_relocs;
3101 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3103 ret = copy_from_user(&(*relocs)[reloc_index],
3105 exec_list[i].relocation_count *
3108 drm_free(*relocs, reloc_count * sizeof(**relocs),
3114 reloc_index += exec_list[i].relocation_count;
3121 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3122 uint32_t buffer_count,
3123 struct drm_i915_gem_relocation_entry *relocs)
3125 uint32_t reloc_count = 0, i;
3128 for (i = 0; i < buffer_count; i++) {
3129 struct drm_i915_gem_relocation_entry __user *user_relocs;
3132 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3134 unwritten = copy_to_user(user_relocs,
3135 &relocs[reloc_count],
3136 exec_list[i].relocation_count *
3144 reloc_count += exec_list[i].relocation_count;
3148 drm_free(relocs, reloc_count * sizeof(*relocs), DRM_MEM_DRIVER);
3154 i915_gem_execbuffer(struct drm_device *dev, void *data,
3155 struct drm_file *file_priv)
3157 drm_i915_private_t *dev_priv = dev->dev_private;
3158 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3159 struct drm_i915_gem_execbuffer *args = data;
3160 struct drm_i915_gem_exec_object *exec_list = NULL;
3161 struct drm_gem_object **object_list = NULL;
3162 struct drm_gem_object *batch_obj;
3163 struct drm_i915_gem_object *obj_priv;
3164 struct drm_clip_rect *cliprects = NULL;
3165 struct drm_i915_gem_relocation_entry *relocs;
3166 int ret, ret2, i, pinned = 0;
3167 uint64_t exec_offset;
3168 uint32_t seqno, flush_domains, reloc_index;
3172 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3173 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3176 if (args->buffer_count < 1) {
3177 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3180 /* Copy in the exec list from userland */
3181 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
3183 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
3185 if (exec_list == NULL || object_list == NULL) {
3186 DRM_ERROR("Failed to allocate exec or object list "
3188 args->buffer_count);
3192 ret = copy_from_user(exec_list,
3193 (struct drm_i915_relocation_entry __user *)
3194 (uintptr_t) args->buffers_ptr,
3195 sizeof(*exec_list) * args->buffer_count);
3197 DRM_ERROR("copy %d exec entries failed %d\n",
3198 args->buffer_count, ret);
3202 if (args->num_cliprects != 0) {
3203 cliprects = drm_calloc(args->num_cliprects, sizeof(*cliprects),
3205 if (cliprects == NULL)
3208 ret = copy_from_user(cliprects,
3209 (struct drm_clip_rect __user *)
3210 (uintptr_t) args->cliprects_ptr,
3211 sizeof(*cliprects) * args->num_cliprects);
3213 DRM_ERROR("copy %d cliprects failed: %d\n",
3214 args->num_cliprects, ret);
3219 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3224 mutex_lock(&dev->struct_mutex);
3226 i915_verify_inactive(dev, __FILE__, __LINE__);
3228 if (dev_priv->mm.wedged) {
3229 DRM_ERROR("Execbuf while wedged\n");
3230 mutex_unlock(&dev->struct_mutex);
3235 if (dev_priv->mm.suspended) {
3236 DRM_ERROR("Execbuf while VT-switched.\n");
3237 mutex_unlock(&dev->struct_mutex);
3242 /* Look up object handles */
3243 for (i = 0; i < args->buffer_count; i++) {
3244 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3245 exec_list[i].handle);
3246 if (object_list[i] == NULL) {
3247 DRM_ERROR("Invalid object handle %d at index %d\n",
3248 exec_list[i].handle, i);
3253 obj_priv = object_list[i]->driver_private;
3254 if (obj_priv->in_execbuffer) {
3255 DRM_ERROR("Object %p appears more than once in object list\n",
3260 obj_priv->in_execbuffer = true;
3263 /* Pin and relocate */
3264 for (pin_tries = 0; ; pin_tries++) {
3268 for (i = 0; i < args->buffer_count; i++) {
3269 object_list[i]->pending_read_domains = 0;
3270 object_list[i]->pending_write_domain = 0;
3271 ret = i915_gem_object_pin_and_relocate(object_list[i],
3274 &relocs[reloc_index]);
3278 reloc_index += exec_list[i].relocation_count;
3284 /* error other than GTT full, or we've already tried again */
3285 if (ret != -ENOMEM || pin_tries >= 1) {
3286 if (ret != -ERESTARTSYS)
3287 DRM_ERROR("Failed to pin buffers %d\n", ret);
3291 /* unpin all of our buffers */
3292 for (i = 0; i < pinned; i++)
3293 i915_gem_object_unpin(object_list[i]);
3296 /* evict everyone we can from the aperture */
3297 ret = i915_gem_evict_everything(dev);
3302 /* Set the pending read domains for the batch buffer to COMMAND */
3303 batch_obj = object_list[args->buffer_count-1];
3304 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
3305 batch_obj->pending_write_domain = 0;
3307 i915_verify_inactive(dev, __FILE__, __LINE__);
3309 /* Zero the global flush/invalidate flags. These
3310 * will be modified as new domains are computed
3313 dev->invalidate_domains = 0;
3314 dev->flush_domains = 0;
3316 for (i = 0; i < args->buffer_count; i++) {
3317 struct drm_gem_object *obj = object_list[i];
3319 /* Compute new gpu domains and update invalidate/flush */
3320 i915_gem_object_set_to_gpu_domain(obj);
3323 i915_verify_inactive(dev, __FILE__, __LINE__);
3325 if (dev->invalidate_domains | dev->flush_domains) {
3327 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3329 dev->invalidate_domains,
3330 dev->flush_domains);
3333 dev->invalidate_domains,
3334 dev->flush_domains);
3335 if (dev->flush_domains)
3336 (void)i915_add_request(dev, dev->flush_domains);
3339 for (i = 0; i < args->buffer_count; i++) {
3340 struct drm_gem_object *obj = object_list[i];
3342 obj->write_domain = obj->pending_write_domain;
3345 i915_verify_inactive(dev, __FILE__, __LINE__);
3348 for (i = 0; i < args->buffer_count; i++) {
3349 i915_gem_object_check_coherency(object_list[i],
3350 exec_list[i].handle);
3354 exec_offset = exec_list[args->buffer_count - 1].offset;
3357 i915_gem_dump_object(batch_obj,
3363 /* Exec the batchbuffer */
3364 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3366 DRM_ERROR("dispatch failed %d\n", ret);
3371 * Ensure that the commands in the batch buffer are
3372 * finished before the interrupt fires
3374 flush_domains = i915_retire_commands(dev);
3376 i915_verify_inactive(dev, __FILE__, __LINE__);
3379 * Get a seqno representing the execution of the current buffer,
3380 * which we can wait on. We would like to mitigate these interrupts,
3381 * likely by only creating seqnos occasionally (so that we have
3382 * *some* interrupts representing completion of buffers that we can
3383 * wait on when trying to clear up gtt space).
3385 seqno = i915_add_request(dev, flush_domains);
3387 i915_file_priv->mm.last_gem_seqno = seqno;
3388 for (i = 0; i < args->buffer_count; i++) {
3389 struct drm_gem_object *obj = object_list[i];
3391 i915_gem_object_move_to_active(obj, seqno);
3393 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3397 i915_dump_lru(dev, __func__);
3400 i915_verify_inactive(dev, __FILE__, __LINE__);
3403 for (i = 0; i < pinned; i++)
3404 i915_gem_object_unpin(object_list[i]);
3406 for (i = 0; i < args->buffer_count; i++) {
3407 if (object_list[i]) {
3408 obj_priv = object_list[i]->driver_private;
3409 obj_priv->in_execbuffer = false;
3411 drm_gem_object_unreference(object_list[i]);
3414 mutex_unlock(&dev->struct_mutex);
3417 /* Copy the new buffer offsets back to the user's exec list. */
3418 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3419 (uintptr_t) args->buffers_ptr,
3421 sizeof(*exec_list) * args->buffer_count);
3424 DRM_ERROR("failed to copy %d exec entries "
3425 "back to user (%d)\n",
3426 args->buffer_count, ret);
3430 /* Copy the updated relocations out regardless of current error
3431 * state. Failure to update the relocs would mean that the next
3432 * time userland calls execbuf, it would do so with presumed offset
3433 * state that didn't match the actual object state.
3435 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3438 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3445 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
3447 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
3449 drm_free(cliprects, sizeof(*cliprects) * args->num_cliprects,
3456 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3458 struct drm_device *dev = obj->dev;
3459 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3462 i915_verify_inactive(dev, __FILE__, __LINE__);
3463 if (obj_priv->gtt_space == NULL) {
3464 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3466 if (ret != -EBUSY && ret != -ERESTARTSYS)
3467 DRM_ERROR("Failure to bind: %d\n", ret);
3472 * Pre-965 chips need a fence register set up in order to
3473 * properly handle tiled surfaces.
3475 if (!IS_I965G(dev) &&
3476 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
3477 obj_priv->tiling_mode != I915_TILING_NONE) {
3478 ret = i915_gem_object_get_fence_reg(obj, true);
3480 if (ret != -EBUSY && ret != -ERESTARTSYS)
3481 DRM_ERROR("Failure to install fence: %d\n",
3486 obj_priv->pin_count++;
3488 /* If the object is not active and not pending a flush,
3489 * remove it from the inactive list
3491 if (obj_priv->pin_count == 1) {
3492 atomic_inc(&dev->pin_count);
3493 atomic_add(obj->size, &dev->pin_memory);
3494 if (!obj_priv->active &&
3495 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3496 I915_GEM_DOMAIN_GTT)) == 0 &&
3497 !list_empty(&obj_priv->list))
3498 list_del_init(&obj_priv->list);
3500 i915_verify_inactive(dev, __FILE__, __LINE__);
3506 i915_gem_object_unpin(struct drm_gem_object *obj)
3508 struct drm_device *dev = obj->dev;
3509 drm_i915_private_t *dev_priv = dev->dev_private;
3510 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3512 i915_verify_inactive(dev, __FILE__, __LINE__);
3513 obj_priv->pin_count--;
3514 BUG_ON(obj_priv->pin_count < 0);
3515 BUG_ON(obj_priv->gtt_space == NULL);
3517 /* If the object is no longer pinned, and is
3518 * neither active nor being flushed, then stick it on
3521 if (obj_priv->pin_count == 0) {
3522 if (!obj_priv->active &&
3523 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3524 I915_GEM_DOMAIN_GTT)) == 0)
3525 list_move_tail(&obj_priv->list,
3526 &dev_priv->mm.inactive_list);
3527 atomic_dec(&dev->pin_count);
3528 atomic_sub(obj->size, &dev->pin_memory);
3530 i915_verify_inactive(dev, __FILE__, __LINE__);
3534 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3535 struct drm_file *file_priv)
3537 struct drm_i915_gem_pin *args = data;
3538 struct drm_gem_object *obj;
3539 struct drm_i915_gem_object *obj_priv;
3542 mutex_lock(&dev->struct_mutex);
3544 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3546 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3548 mutex_unlock(&dev->struct_mutex);
3551 obj_priv = obj->driver_private;
3553 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3554 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3556 drm_gem_object_unreference(obj);
3557 mutex_unlock(&dev->struct_mutex);
3561 obj_priv->user_pin_count++;
3562 obj_priv->pin_filp = file_priv;
3563 if (obj_priv->user_pin_count == 1) {
3564 ret = i915_gem_object_pin(obj, args->alignment);
3566 drm_gem_object_unreference(obj);
3567 mutex_unlock(&dev->struct_mutex);
3572 /* XXX - flush the CPU caches for pinned objects
3573 * as the X server doesn't manage domains yet
3575 i915_gem_object_flush_cpu_write_domain(obj);
3576 args->offset = obj_priv->gtt_offset;
3577 drm_gem_object_unreference(obj);
3578 mutex_unlock(&dev->struct_mutex);
3584 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3585 struct drm_file *file_priv)
3587 struct drm_i915_gem_pin *args = data;
3588 struct drm_gem_object *obj;
3589 struct drm_i915_gem_object *obj_priv;
3591 mutex_lock(&dev->struct_mutex);
3593 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3595 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3597 mutex_unlock(&dev->struct_mutex);
3601 obj_priv = obj->driver_private;
3602 if (obj_priv->pin_filp != file_priv) {
3603 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3605 drm_gem_object_unreference(obj);
3606 mutex_unlock(&dev->struct_mutex);
3609 obj_priv->user_pin_count--;
3610 if (obj_priv->user_pin_count == 0) {
3611 obj_priv->pin_filp = NULL;
3612 i915_gem_object_unpin(obj);
3615 drm_gem_object_unreference(obj);
3616 mutex_unlock(&dev->struct_mutex);
3621 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3622 struct drm_file *file_priv)
3624 struct drm_i915_gem_busy *args = data;
3625 struct drm_gem_object *obj;
3626 struct drm_i915_gem_object *obj_priv;
3628 mutex_lock(&dev->struct_mutex);
3629 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3631 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3633 mutex_unlock(&dev->struct_mutex);
3637 /* Update the active list for the hardware's current position.
3638 * Otherwise this only updates on a delayed timer or when irqs are
3639 * actually unmasked, and our working set ends up being larger than
3642 i915_gem_retire_requests(dev);
3644 obj_priv = obj->driver_private;
3645 /* Don't count being on the flushing list against the object being
3646 * done. Otherwise, a buffer left on the flushing list but not getting
3647 * flushed (because nobody's flushing that domain) won't ever return
3648 * unbusy and get reused by libdrm's bo cache. The other expected
3649 * consumer of this interface, OpenGL's occlusion queries, also specs
3650 * that the objects get unbusy "eventually" without any interference.
3652 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3654 drm_gem_object_unreference(obj);
3655 mutex_unlock(&dev->struct_mutex);
3660 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3661 struct drm_file *file_priv)
3663 return i915_gem_ring_throttle(dev, file_priv);
3666 int i915_gem_init_object(struct drm_gem_object *obj)
3668 struct drm_i915_gem_object *obj_priv;
3670 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
3671 if (obj_priv == NULL)
3675 * We've just allocated pages from the kernel,
3676 * so they've just been written by the CPU with
3677 * zeros. They'll need to be clflushed before we
3678 * use them with the GPU.
3680 obj->write_domain = I915_GEM_DOMAIN_CPU;
3681 obj->read_domains = I915_GEM_DOMAIN_CPU;
3683 obj_priv->agp_type = AGP_USER_MEMORY;
3685 obj->driver_private = obj_priv;
3686 obj_priv->obj = obj;
3687 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3688 INIT_LIST_HEAD(&obj_priv->list);
3693 void i915_gem_free_object(struct drm_gem_object *obj)
3695 struct drm_device *dev = obj->dev;
3696 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3698 while (obj_priv->pin_count > 0)
3699 i915_gem_object_unpin(obj);
3701 if (obj_priv->phys_obj)
3702 i915_gem_detach_phys_object(dev, obj);
3704 i915_gem_object_unbind(obj);
3706 i915_gem_free_mmap_offset(obj);
3708 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3709 kfree(obj_priv->bit_17);
3710 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3713 /** Unbinds all objects that are on the given buffer list. */
3715 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3717 struct drm_gem_object *obj;
3718 struct drm_i915_gem_object *obj_priv;
3721 while (!list_empty(head)) {
3722 obj_priv = list_first_entry(head,
3723 struct drm_i915_gem_object,
3725 obj = obj_priv->obj;
3727 if (obj_priv->pin_count != 0) {
3728 DRM_ERROR("Pinned object in unbind list\n");
3729 mutex_unlock(&dev->struct_mutex);
3733 ret = i915_gem_object_unbind(obj);
3735 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3737 mutex_unlock(&dev->struct_mutex);
3747 i915_gem_idle(struct drm_device *dev)
3749 drm_i915_private_t *dev_priv = dev->dev_private;
3750 uint32_t seqno, cur_seqno, last_seqno;
3753 mutex_lock(&dev->struct_mutex);
3755 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3756 mutex_unlock(&dev->struct_mutex);
3760 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3761 * We need to replace this with a semaphore, or something.
3763 dev_priv->mm.suspended = 1;
3765 /* Cancel the retire work handler, wait for it to finish if running
3767 mutex_unlock(&dev->struct_mutex);
3768 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3769 mutex_lock(&dev->struct_mutex);
3771 i915_kernel_lost_context(dev);
3773 /* Flush the GPU along with all non-CPU write domains
3775 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3776 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
3777 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
3780 mutex_unlock(&dev->struct_mutex);
3784 dev_priv->mm.waiting_gem_seqno = seqno;
3788 cur_seqno = i915_get_gem_seqno(dev);
3789 if (i915_seqno_passed(cur_seqno, seqno))
3791 if (last_seqno == cur_seqno) {
3792 if (stuck++ > 100) {
3793 DRM_ERROR("hardware wedged\n");
3794 dev_priv->mm.wedged = 1;
3795 DRM_WAKEUP(&dev_priv->irq_queue);
3800 last_seqno = cur_seqno;
3802 dev_priv->mm.waiting_gem_seqno = 0;
3804 i915_gem_retire_requests(dev);
3806 spin_lock(&dev_priv->mm.active_list_lock);
3807 if (!dev_priv->mm.wedged) {
3808 /* Active and flushing should now be empty as we've
3809 * waited for a sequence higher than any pending execbuffer
3811 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3812 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3813 /* Request should now be empty as we've also waited
3814 * for the last request in the list
3816 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3819 /* Empty the active and flushing lists to inactive. If there's
3820 * anything left at this point, it means that we're wedged and
3821 * nothing good's going to happen by leaving them there. So strip
3822 * the GPU domains and just stuff them onto inactive.
3824 while (!list_empty(&dev_priv->mm.active_list)) {
3825 struct drm_i915_gem_object *obj_priv;
3827 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3828 struct drm_i915_gem_object,
3830 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3831 i915_gem_object_move_to_inactive(obj_priv->obj);
3833 spin_unlock(&dev_priv->mm.active_list_lock);
3835 while (!list_empty(&dev_priv->mm.flushing_list)) {
3836 struct drm_i915_gem_object *obj_priv;
3838 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3839 struct drm_i915_gem_object,
3841 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3842 i915_gem_object_move_to_inactive(obj_priv->obj);
3846 /* Move all inactive buffers out of the GTT. */
3847 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3848 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3850 mutex_unlock(&dev->struct_mutex);
3854 i915_gem_cleanup_ringbuffer(dev);
3855 mutex_unlock(&dev->struct_mutex);
3861 i915_gem_init_hws(struct drm_device *dev)
3863 drm_i915_private_t *dev_priv = dev->dev_private;
3864 struct drm_gem_object *obj;
3865 struct drm_i915_gem_object *obj_priv;
3868 /* If we need a physical address for the status page, it's already
3869 * initialized at driver load time.
3871 if (!I915_NEED_GFX_HWS(dev))
3874 obj = drm_gem_object_alloc(dev, 4096);
3876 DRM_ERROR("Failed to allocate status page\n");
3879 obj_priv = obj->driver_private;
3880 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3882 ret = i915_gem_object_pin(obj, 4096);
3884 drm_gem_object_unreference(obj);
3888 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3890 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
3891 if (dev_priv->hw_status_page == NULL) {
3892 DRM_ERROR("Failed to map status page.\n");
3893 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3894 i915_gem_object_unpin(obj);
3895 drm_gem_object_unreference(obj);
3898 dev_priv->hws_obj = obj;
3899 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3900 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3901 I915_READ(HWS_PGA); /* posting read */
3902 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3908 i915_gem_cleanup_hws(struct drm_device *dev)
3910 drm_i915_private_t *dev_priv = dev->dev_private;
3911 struct drm_gem_object *obj;
3912 struct drm_i915_gem_object *obj_priv;
3914 if (dev_priv->hws_obj == NULL)
3917 obj = dev_priv->hws_obj;
3918 obj_priv = obj->driver_private;
3920 kunmap(obj_priv->pages[0]);
3921 i915_gem_object_unpin(obj);
3922 drm_gem_object_unreference(obj);
3923 dev_priv->hws_obj = NULL;
3925 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3926 dev_priv->hw_status_page = NULL;
3928 /* Write high address into HWS_PGA when disabling. */
3929 I915_WRITE(HWS_PGA, 0x1ffff000);
3933 i915_gem_init_ringbuffer(struct drm_device *dev)
3935 drm_i915_private_t *dev_priv = dev->dev_private;
3936 struct drm_gem_object *obj;
3937 struct drm_i915_gem_object *obj_priv;
3938 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3942 ret = i915_gem_init_hws(dev);
3946 obj = drm_gem_object_alloc(dev, 128 * 1024);
3948 DRM_ERROR("Failed to allocate ringbuffer\n");
3949 i915_gem_cleanup_hws(dev);
3952 obj_priv = obj->driver_private;
3954 ret = i915_gem_object_pin(obj, 4096);
3956 drm_gem_object_unreference(obj);
3957 i915_gem_cleanup_hws(dev);
3961 /* Set up the kernel mapping for the ring. */
3962 ring->Size = obj->size;
3963 ring->tail_mask = obj->size - 1;
3965 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3966 ring->map.size = obj->size;
3968 ring->map.flags = 0;
3971 drm_core_ioremap_wc(&ring->map, dev);
3972 if (ring->map.handle == NULL) {
3973 DRM_ERROR("Failed to map ringbuffer.\n");
3974 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3975 i915_gem_object_unpin(obj);
3976 drm_gem_object_unreference(obj);
3977 i915_gem_cleanup_hws(dev);
3980 ring->ring_obj = obj;
3981 ring->virtual_start = ring->map.handle;
3983 /* Stop the ring if it's running. */
3984 I915_WRITE(PRB0_CTL, 0);
3985 I915_WRITE(PRB0_TAIL, 0);
3986 I915_WRITE(PRB0_HEAD, 0);
3988 /* Initialize the ring. */
3989 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3990 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3992 /* G45 ring initialization fails to reset head to zero */
3994 DRM_ERROR("Ring head not reset to zero "
3995 "ctl %08x head %08x tail %08x start %08x\n",
3996 I915_READ(PRB0_CTL),
3997 I915_READ(PRB0_HEAD),
3998 I915_READ(PRB0_TAIL),
3999 I915_READ(PRB0_START));
4000 I915_WRITE(PRB0_HEAD, 0);
4002 DRM_ERROR("Ring head forced to zero "
4003 "ctl %08x head %08x tail %08x start %08x\n",
4004 I915_READ(PRB0_CTL),
4005 I915_READ(PRB0_HEAD),
4006 I915_READ(PRB0_TAIL),
4007 I915_READ(PRB0_START));
4010 I915_WRITE(PRB0_CTL,
4011 ((obj->size - 4096) & RING_NR_PAGES) |
4015 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4017 /* If the head is still not zero, the ring is dead */
4019 DRM_ERROR("Ring initialization failed "
4020 "ctl %08x head %08x tail %08x start %08x\n",
4021 I915_READ(PRB0_CTL),
4022 I915_READ(PRB0_HEAD),
4023 I915_READ(PRB0_TAIL),
4024 I915_READ(PRB0_START));
4028 /* Update our cache of the ring state */
4029 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4030 i915_kernel_lost_context(dev);
4032 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4033 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4034 ring->space = ring->head - (ring->tail + 8);
4035 if (ring->space < 0)
4036 ring->space += ring->Size;
4043 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4045 drm_i915_private_t *dev_priv = dev->dev_private;
4047 if (dev_priv->ring.ring_obj == NULL)
4050 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4052 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4053 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4054 dev_priv->ring.ring_obj = NULL;
4055 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4057 i915_gem_cleanup_hws(dev);
4061 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4062 struct drm_file *file_priv)
4064 drm_i915_private_t *dev_priv = dev->dev_private;
4067 if (drm_core_check_feature(dev, DRIVER_MODESET))
4070 if (dev_priv->mm.wedged) {
4071 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4072 dev_priv->mm.wedged = 0;
4075 mutex_lock(&dev->struct_mutex);
4076 dev_priv->mm.suspended = 0;
4078 ret = i915_gem_init_ringbuffer(dev);
4082 spin_lock(&dev_priv->mm.active_list_lock);
4083 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4084 spin_unlock(&dev_priv->mm.active_list_lock);
4086 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4087 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4088 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4089 mutex_unlock(&dev->struct_mutex);
4091 drm_irq_install(dev);
4097 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4098 struct drm_file *file_priv)
4102 if (drm_core_check_feature(dev, DRIVER_MODESET))
4105 ret = i915_gem_idle(dev);
4106 drm_irq_uninstall(dev);
4112 i915_gem_lastclose(struct drm_device *dev)
4116 if (drm_core_check_feature(dev, DRIVER_MODESET))
4119 ret = i915_gem_idle(dev);
4121 DRM_ERROR("failed to idle hardware: %d\n", ret);
4125 i915_gem_load(struct drm_device *dev)
4127 drm_i915_private_t *dev_priv = dev->dev_private;
4129 spin_lock_init(&dev_priv->mm.active_list_lock);
4130 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4131 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4132 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4133 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4134 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4135 i915_gem_retire_work_handler);
4136 dev_priv->mm.next_gem_seqno = 1;
4138 /* Old X drivers will take 0-2 for front, back, depth buffers */
4139 dev_priv->fence_reg_start = 3;
4141 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4142 dev_priv->num_fence_regs = 16;
4144 dev_priv->num_fence_regs = 8;
4146 i915_gem_detect_bit_6_swizzle(dev);
4150 * Create a physically contiguous memory object for this object
4151 * e.g. for cursor + overlay regs
4153 int i915_gem_init_phys_object(struct drm_device *dev,
4156 drm_i915_private_t *dev_priv = dev->dev_private;
4157 struct drm_i915_gem_phys_object *phys_obj;
4160 if (dev_priv->mm.phys_objs[id - 1] || !size)
4163 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4169 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4170 if (!phys_obj->handle) {
4175 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4178 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4182 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4186 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4188 drm_i915_private_t *dev_priv = dev->dev_private;
4189 struct drm_i915_gem_phys_object *phys_obj;
4191 if (!dev_priv->mm.phys_objs[id - 1])
4194 phys_obj = dev_priv->mm.phys_objs[id - 1];
4195 if (phys_obj->cur_obj) {
4196 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4200 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4202 drm_pci_free(dev, phys_obj->handle);
4204 dev_priv->mm.phys_objs[id - 1] = NULL;
4207 void i915_gem_free_all_phys_object(struct drm_device *dev)
4211 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4212 i915_gem_free_phys_object(dev, i);
4215 void i915_gem_detach_phys_object(struct drm_device *dev,
4216 struct drm_gem_object *obj)
4218 struct drm_i915_gem_object *obj_priv;
4223 obj_priv = obj->driver_private;
4224 if (!obj_priv->phys_obj)
4227 ret = i915_gem_object_get_pages(obj);
4231 page_count = obj->size / PAGE_SIZE;
4233 for (i = 0; i < page_count; i++) {
4234 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4235 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4237 memcpy(dst, src, PAGE_SIZE);
4238 kunmap_atomic(dst, KM_USER0);
4240 drm_clflush_pages(obj_priv->pages, page_count);
4241 drm_agp_chipset_flush(dev);
4243 obj_priv->phys_obj->cur_obj = NULL;
4244 obj_priv->phys_obj = NULL;
4248 i915_gem_attach_phys_object(struct drm_device *dev,
4249 struct drm_gem_object *obj, int id)
4251 drm_i915_private_t *dev_priv = dev->dev_private;
4252 struct drm_i915_gem_object *obj_priv;
4257 if (id > I915_MAX_PHYS_OBJECT)
4260 obj_priv = obj->driver_private;
4262 if (obj_priv->phys_obj) {
4263 if (obj_priv->phys_obj->id == id)
4265 i915_gem_detach_phys_object(dev, obj);
4269 /* create a new object */
4270 if (!dev_priv->mm.phys_objs[id - 1]) {
4271 ret = i915_gem_init_phys_object(dev, id,
4274 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4279 /* bind to the object */
4280 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4281 obj_priv->phys_obj->cur_obj = obj;
4283 ret = i915_gem_object_get_pages(obj);
4285 DRM_ERROR("failed to get page list\n");
4289 page_count = obj->size / PAGE_SIZE;
4291 for (i = 0; i < page_count; i++) {
4292 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4293 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4295 memcpy(dst, src, PAGE_SIZE);
4296 kunmap_atomic(src, KM_USER0);
4305 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4306 struct drm_i915_gem_pwrite *args,
4307 struct drm_file *file_priv)
4309 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4312 char __user *user_data;
4314 user_data = (char __user *) (uintptr_t) args->data_ptr;
4315 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4317 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4318 ret = copy_from_user(obj_addr, user_data, args->size);
4322 drm_agp_chipset_flush(dev);