2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment, bool mappable);
55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
57 struct drm_i915_gem_pwrite *args,
58 struct drm_file *file_priv);
59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
61 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
66 /* some bookkeeping */
67 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
70 dev_priv->mm.object_count++;
71 dev_priv->mm.object_memory += size;
74 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
77 dev_priv->mm.object_count--;
78 dev_priv->mm.object_memory -= size;
81 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
82 struct drm_gem_object *obj)
84 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
85 dev_priv->mm.gtt_count++;
86 dev_priv->mm.gtt_memory += obj->size;
87 if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) {
88 dev_priv->mm.mappable_gtt_used +=
89 min_t(size_t, obj->size,
90 dev_priv->mm.gtt_mappable_end
91 - obj_priv->gtt_offset);
95 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
96 struct drm_gem_object *obj)
98 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
99 dev_priv->mm.gtt_count--;
100 dev_priv->mm.gtt_memory -= obj->size;
101 if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) {
102 dev_priv->mm.mappable_gtt_used -=
103 min_t(size_t, obj->size,
104 dev_priv->mm.gtt_mappable_end
105 - obj_priv->gtt_offset);
110 * Update the mappable working set counters. Call _only_ when there is a change
111 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
112 * @mappable: new state the changed mappable flag (either pin_ or fault_).
115 i915_gem_info_update_mappable(struct drm_i915_private *dev_priv,
116 struct drm_gem_object *obj,
119 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
122 if (obj_priv->pin_mappable && obj_priv->fault_mappable)
123 /* Combined state was already mappable. */
125 dev_priv->mm.gtt_mappable_count++;
126 dev_priv->mm.gtt_mappable_memory += obj->size;
128 if (obj_priv->pin_mappable || obj_priv->fault_mappable)
129 /* Combined state still mappable. */
131 dev_priv->mm.gtt_mappable_count--;
132 dev_priv->mm.gtt_mappable_memory -= obj->size;
136 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
137 struct drm_gem_object *obj,
140 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
141 dev_priv->mm.pin_count++;
142 dev_priv->mm.pin_memory += obj->size;
144 obj_priv->pin_mappable = true;
145 i915_gem_info_update_mappable(dev_priv, obj, true);
149 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
150 struct drm_gem_object *obj)
152 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
153 dev_priv->mm.pin_count--;
154 dev_priv->mm.pin_memory -= obj->size;
155 if (obj_priv->pin_mappable) {
156 obj_priv->pin_mappable = false;
157 i915_gem_info_update_mappable(dev_priv, obj, false);
162 i915_gem_check_is_wedged(struct drm_device *dev)
164 struct drm_i915_private *dev_priv = dev->dev_private;
165 struct completion *x = &dev_priv->error_completion;
169 if (!atomic_read(&dev_priv->mm.wedged))
172 ret = wait_for_completion_interruptible(x);
176 /* Success, we reset the GPU! */
177 if (!atomic_read(&dev_priv->mm.wedged))
180 /* GPU is hung, bump the completion count to account for
181 * the token we just consumed so that we never hit zero and
182 * end up waiting upon a subsequent completion event that
185 spin_lock_irqsave(&x->wait.lock, flags);
187 spin_unlock_irqrestore(&x->wait.lock, flags);
191 static int i915_mutex_lock_interruptible(struct drm_device *dev)
193 struct drm_i915_private *dev_priv = dev->dev_private;
196 ret = i915_gem_check_is_wedged(dev);
200 ret = mutex_lock_interruptible(&dev->struct_mutex);
204 if (atomic_read(&dev_priv->mm.wedged)) {
205 mutex_unlock(&dev->struct_mutex);
209 WARN_ON(i915_verify_lists(dev));
214 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
216 return obj_priv->gtt_space &&
218 obj_priv->pin_count == 0;
221 int i915_gem_do_init(struct drm_device *dev,
223 unsigned long mappable_end,
226 drm_i915_private_t *dev_priv = dev->dev_private;
229 (start & (PAGE_SIZE - 1)) != 0 ||
230 (end & (PAGE_SIZE - 1)) != 0) {
234 drm_mm_init(&dev_priv->mm.gtt_space, start,
237 dev_priv->mm.gtt_total = end - start;
238 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
239 dev_priv->mm.gtt_mappable_end = mappable_end;
245 i915_gem_init_ioctl(struct drm_device *dev, void *data,
246 struct drm_file *file_priv)
248 struct drm_i915_gem_init *args = data;
251 mutex_lock(&dev->struct_mutex);
252 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
253 mutex_unlock(&dev->struct_mutex);
259 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
260 struct drm_file *file_priv)
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_i915_gem_get_aperture *args = data;
265 if (!(dev->driver->driver_features & DRIVER_GEM))
268 mutex_lock(&dev->struct_mutex);
269 args->aper_size = dev_priv->mm.gtt_total;
270 args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
271 mutex_unlock(&dev->struct_mutex);
278 * Creates a new mm object and returns a handle to it.
281 i915_gem_create_ioctl(struct drm_device *dev, void *data,
282 struct drm_file *file_priv)
284 struct drm_i915_gem_create *args = data;
285 struct drm_gem_object *obj;
289 args->size = roundup(args->size, PAGE_SIZE);
291 /* Allocate the new object */
292 obj = i915_gem_alloc_object(dev, args->size);
296 ret = drm_gem_handle_create(file_priv, obj, &handle);
298 drm_gem_object_release(obj);
299 i915_gem_info_remove_obj(dev->dev_private, obj->size);
304 /* drop reference from allocate - handle holds it now */
305 drm_gem_object_unreference(obj);
306 trace_i915_gem_object_create(obj);
308 args->handle = handle;
313 i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj)
315 struct drm_device *dev = obj->base.dev;
316 drm_i915_private_t *dev_priv = dev->dev_private;
318 return obj->gtt_space == NULL ||
319 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
322 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
324 drm_i915_private_t *dev_priv = obj->dev->dev_private;
325 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
327 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
328 obj_priv->tiling_mode != I915_TILING_NONE;
332 slow_shmem_copy(struct page *dst_page,
334 struct page *src_page,
338 char *dst_vaddr, *src_vaddr;
340 dst_vaddr = kmap(dst_page);
341 src_vaddr = kmap(src_page);
343 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
350 slow_shmem_bit17_copy(struct page *gpu_page,
352 struct page *cpu_page,
357 char *gpu_vaddr, *cpu_vaddr;
359 /* Use the unswizzled path if this page isn't affected. */
360 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
362 return slow_shmem_copy(cpu_page, cpu_offset,
363 gpu_page, gpu_offset, length);
365 return slow_shmem_copy(gpu_page, gpu_offset,
366 cpu_page, cpu_offset, length);
369 gpu_vaddr = kmap(gpu_page);
370 cpu_vaddr = kmap(cpu_page);
372 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
373 * XORing with the other bits (A9 for Y, A9 and A10 for X)
376 int cacheline_end = ALIGN(gpu_offset + 1, 64);
377 int this_length = min(cacheline_end - gpu_offset, length);
378 int swizzled_gpu_offset = gpu_offset ^ 64;
381 memcpy(cpu_vaddr + cpu_offset,
382 gpu_vaddr + swizzled_gpu_offset,
385 memcpy(gpu_vaddr + swizzled_gpu_offset,
386 cpu_vaddr + cpu_offset,
389 cpu_offset += this_length;
390 gpu_offset += this_length;
391 length -= this_length;
399 * This is the fast shmem pread path, which attempts to copy_from_user directly
400 * from the backing pages of the object to the user's address space. On a
401 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
404 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
405 struct drm_i915_gem_pread *args,
406 struct drm_file *file_priv)
408 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
409 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
412 char __user *user_data;
413 int page_offset, page_length;
415 user_data = (char __user *) (uintptr_t) args->data_ptr;
418 obj_priv = to_intel_bo(obj);
419 offset = args->offset;
426 /* Operation in this page
428 * page_offset = offset within page
429 * page_length = bytes to copy for this page
431 page_offset = offset & (PAGE_SIZE-1);
432 page_length = remain;
433 if ((page_offset + remain) > PAGE_SIZE)
434 page_length = PAGE_SIZE - page_offset;
436 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
437 GFP_HIGHUSER | __GFP_RECLAIMABLE);
439 return PTR_ERR(page);
441 vaddr = kmap_atomic(page);
442 ret = __copy_to_user_inatomic(user_data,
445 kunmap_atomic(vaddr);
447 mark_page_accessed(page);
448 page_cache_release(page);
452 remain -= page_length;
453 user_data += page_length;
454 offset += page_length;
461 * This is the fallback shmem pread path, which allocates temporary storage
462 * in kernel space to copy_to_user into outside of the struct_mutex, so we
463 * can copy out of the object's backing pages while holding the struct mutex
464 * and not take page faults.
467 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
468 struct drm_i915_gem_pread *args,
469 struct drm_file *file_priv)
471 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
472 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
473 struct mm_struct *mm = current->mm;
474 struct page **user_pages;
476 loff_t offset, pinned_pages, i;
477 loff_t first_data_page, last_data_page, num_pages;
478 int shmem_page_offset;
479 int data_page_index, data_page_offset;
482 uint64_t data_ptr = args->data_ptr;
483 int do_bit17_swizzling;
487 /* Pin the user pages containing the data. We can't fault while
488 * holding the struct mutex, yet we want to hold it while
489 * dereferencing the user data.
491 first_data_page = data_ptr / PAGE_SIZE;
492 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
493 num_pages = last_data_page - first_data_page + 1;
495 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
496 if (user_pages == NULL)
499 mutex_unlock(&dev->struct_mutex);
500 down_read(&mm->mmap_sem);
501 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
502 num_pages, 1, 0, user_pages, NULL);
503 up_read(&mm->mmap_sem);
504 mutex_lock(&dev->struct_mutex);
505 if (pinned_pages < num_pages) {
510 ret = i915_gem_object_set_cpu_read_domain_range(obj,
516 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
518 obj_priv = to_intel_bo(obj);
519 offset = args->offset;
524 /* Operation in this page
526 * shmem_page_offset = offset within page in shmem file
527 * data_page_index = page number in get_user_pages return
528 * data_page_offset = offset with data_page_index page.
529 * page_length = bytes to copy for this page
531 shmem_page_offset = offset & ~PAGE_MASK;
532 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
533 data_page_offset = data_ptr & ~PAGE_MASK;
535 page_length = remain;
536 if ((shmem_page_offset + page_length) > PAGE_SIZE)
537 page_length = PAGE_SIZE - shmem_page_offset;
538 if ((data_page_offset + page_length) > PAGE_SIZE)
539 page_length = PAGE_SIZE - data_page_offset;
541 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
542 GFP_HIGHUSER | __GFP_RECLAIMABLE);
544 return PTR_ERR(page);
546 if (do_bit17_swizzling) {
547 slow_shmem_bit17_copy(page,
549 user_pages[data_page_index],
554 slow_shmem_copy(user_pages[data_page_index],
561 mark_page_accessed(page);
562 page_cache_release(page);
564 remain -= page_length;
565 data_ptr += page_length;
566 offset += page_length;
570 for (i = 0; i < pinned_pages; i++) {
571 SetPageDirty(user_pages[i]);
572 mark_page_accessed(user_pages[i]);
573 page_cache_release(user_pages[i]);
575 drm_free_large(user_pages);
581 * Reads data from the object referenced by handle.
583 * On error, the contents of *data are undefined.
586 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
587 struct drm_file *file_priv)
589 struct drm_i915_gem_pread *args = data;
590 struct drm_gem_object *obj;
591 struct drm_i915_gem_object *obj_priv;
594 ret = i915_mutex_lock_interruptible(dev);
598 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
603 obj_priv = to_intel_bo(obj);
605 /* Bounds check source. */
606 if (args->offset > obj->size || args->size > obj->size - args->offset) {
614 if (!access_ok(VERIFY_WRITE,
615 (char __user *)(uintptr_t)args->data_ptr,
621 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
628 ret = i915_gem_object_set_cpu_read_domain_range(obj,
635 if (!i915_gem_object_needs_bit17_swizzle(obj))
636 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
638 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
641 drm_gem_object_unreference(obj);
643 mutex_unlock(&dev->struct_mutex);
647 /* This is the fast write path which cannot handle
648 * page faults in the source data
652 fast_user_write(struct io_mapping *mapping,
653 loff_t page_base, int page_offset,
654 char __user *user_data,
658 unsigned long unwritten;
660 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
661 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
663 io_mapping_unmap_atomic(vaddr_atomic);
667 /* Here's the write path which can sleep for
672 slow_kernel_write(struct io_mapping *mapping,
673 loff_t gtt_base, int gtt_offset,
674 struct page *user_page, int user_offset,
677 char __iomem *dst_vaddr;
680 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
681 src_vaddr = kmap(user_page);
683 memcpy_toio(dst_vaddr + gtt_offset,
684 src_vaddr + user_offset,
688 io_mapping_unmap(dst_vaddr);
692 * This is the fast pwrite path, where we copy the data directly from the
693 * user into the GTT, uncached.
696 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
697 struct drm_i915_gem_pwrite *args,
698 struct drm_file *file_priv)
700 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
701 drm_i915_private_t *dev_priv = dev->dev_private;
703 loff_t offset, page_base;
704 char __user *user_data;
705 int page_offset, page_length;
707 user_data = (char __user *) (uintptr_t) args->data_ptr;
710 obj_priv = to_intel_bo(obj);
711 offset = obj_priv->gtt_offset + args->offset;
714 /* Operation in this page
716 * page_base = page offset within aperture
717 * page_offset = offset within page
718 * page_length = bytes to copy for this page
720 page_base = (offset & ~(PAGE_SIZE-1));
721 page_offset = offset & (PAGE_SIZE-1);
722 page_length = remain;
723 if ((page_offset + remain) > PAGE_SIZE)
724 page_length = PAGE_SIZE - page_offset;
726 /* If we get a fault while copying data, then (presumably) our
727 * source page isn't available. Return the error and we'll
728 * retry in the slow path.
730 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
731 page_offset, user_data, page_length))
735 remain -= page_length;
736 user_data += page_length;
737 offset += page_length;
744 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
745 * the memory and maps it using kmap_atomic for copying.
747 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
748 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
751 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
752 struct drm_i915_gem_pwrite *args,
753 struct drm_file *file_priv)
755 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
756 drm_i915_private_t *dev_priv = dev->dev_private;
758 loff_t gtt_page_base, offset;
759 loff_t first_data_page, last_data_page, num_pages;
760 loff_t pinned_pages, i;
761 struct page **user_pages;
762 struct mm_struct *mm = current->mm;
763 int gtt_page_offset, data_page_offset, data_page_index, page_length;
765 uint64_t data_ptr = args->data_ptr;
769 /* Pin the user pages containing the data. We can't fault while
770 * holding the struct mutex, and all of the pwrite implementations
771 * want to hold it while dereferencing the user data.
773 first_data_page = data_ptr / PAGE_SIZE;
774 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
775 num_pages = last_data_page - first_data_page + 1;
777 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
778 if (user_pages == NULL)
781 mutex_unlock(&dev->struct_mutex);
782 down_read(&mm->mmap_sem);
783 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
784 num_pages, 0, 0, user_pages, NULL);
785 up_read(&mm->mmap_sem);
786 mutex_lock(&dev->struct_mutex);
787 if (pinned_pages < num_pages) {
789 goto out_unpin_pages;
792 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
794 goto out_unpin_pages;
796 obj_priv = to_intel_bo(obj);
797 offset = obj_priv->gtt_offset + args->offset;
800 /* Operation in this page
802 * gtt_page_base = page offset within aperture
803 * gtt_page_offset = offset within page in aperture
804 * data_page_index = page number in get_user_pages return
805 * data_page_offset = offset with data_page_index page.
806 * page_length = bytes to copy for this page
808 gtt_page_base = offset & PAGE_MASK;
809 gtt_page_offset = offset & ~PAGE_MASK;
810 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
811 data_page_offset = data_ptr & ~PAGE_MASK;
813 page_length = remain;
814 if ((gtt_page_offset + page_length) > PAGE_SIZE)
815 page_length = PAGE_SIZE - gtt_page_offset;
816 if ((data_page_offset + page_length) > PAGE_SIZE)
817 page_length = PAGE_SIZE - data_page_offset;
819 slow_kernel_write(dev_priv->mm.gtt_mapping,
820 gtt_page_base, gtt_page_offset,
821 user_pages[data_page_index],
825 remain -= page_length;
826 offset += page_length;
827 data_ptr += page_length;
831 for (i = 0; i < pinned_pages; i++)
832 page_cache_release(user_pages[i]);
833 drm_free_large(user_pages);
839 * This is the fast shmem pwrite path, which attempts to directly
840 * copy_from_user into the kmapped pages backing the object.
843 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
844 struct drm_i915_gem_pwrite *args,
845 struct drm_file *file_priv)
847 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
848 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
851 char __user *user_data;
852 int page_offset, page_length;
854 user_data = (char __user *) (uintptr_t) args->data_ptr;
857 obj_priv = to_intel_bo(obj);
858 offset = args->offset;
866 /* Operation in this page
868 * page_offset = offset within page
869 * page_length = bytes to copy for this page
871 page_offset = offset & (PAGE_SIZE-1);
872 page_length = remain;
873 if ((page_offset + remain) > PAGE_SIZE)
874 page_length = PAGE_SIZE - page_offset;
876 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
877 GFP_HIGHUSER | __GFP_RECLAIMABLE);
879 return PTR_ERR(page);
881 vaddr = kmap_atomic(page, KM_USER0);
882 ret = __copy_from_user_inatomic(vaddr + page_offset,
885 kunmap_atomic(vaddr, KM_USER0);
887 set_page_dirty(page);
888 mark_page_accessed(page);
889 page_cache_release(page);
891 /* If we get a fault while copying data, then (presumably) our
892 * source page isn't available. Return the error and we'll
893 * retry in the slow path.
898 remain -= page_length;
899 user_data += page_length;
900 offset += page_length;
907 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
908 * the memory and maps it using kmap_atomic for copying.
910 * This avoids taking mmap_sem for faulting on the user's address while the
911 * struct_mutex is held.
914 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
915 struct drm_i915_gem_pwrite *args,
916 struct drm_file *file_priv)
918 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
919 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
920 struct mm_struct *mm = current->mm;
921 struct page **user_pages;
923 loff_t offset, pinned_pages, i;
924 loff_t first_data_page, last_data_page, num_pages;
925 int shmem_page_offset;
926 int data_page_index, data_page_offset;
929 uint64_t data_ptr = args->data_ptr;
930 int do_bit17_swizzling;
934 /* Pin the user pages containing the data. We can't fault while
935 * holding the struct mutex, and all of the pwrite implementations
936 * want to hold it while dereferencing the user data.
938 first_data_page = data_ptr / PAGE_SIZE;
939 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
940 num_pages = last_data_page - first_data_page + 1;
942 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
943 if (user_pages == NULL)
946 mutex_unlock(&dev->struct_mutex);
947 down_read(&mm->mmap_sem);
948 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
949 num_pages, 0, 0, user_pages, NULL);
950 up_read(&mm->mmap_sem);
951 mutex_lock(&dev->struct_mutex);
952 if (pinned_pages < num_pages) {
957 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
961 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
963 obj_priv = to_intel_bo(obj);
964 offset = args->offset;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * data_page_index = page number in get_user_pages return
974 * data_page_offset = offset with data_page_index page.
975 * page_length = bytes to copy for this page
977 shmem_page_offset = offset & ~PAGE_MASK;
978 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
979 data_page_offset = data_ptr & ~PAGE_MASK;
981 page_length = remain;
982 if ((shmem_page_offset + page_length) > PAGE_SIZE)
983 page_length = PAGE_SIZE - shmem_page_offset;
984 if ((data_page_offset + page_length) > PAGE_SIZE)
985 page_length = PAGE_SIZE - data_page_offset;
987 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
988 GFP_HIGHUSER | __GFP_RECLAIMABLE);
994 if (do_bit17_swizzling) {
995 slow_shmem_bit17_copy(page,
997 user_pages[data_page_index],
1002 slow_shmem_copy(page,
1004 user_pages[data_page_index],
1009 set_page_dirty(page);
1010 mark_page_accessed(page);
1011 page_cache_release(page);
1013 remain -= page_length;
1014 data_ptr += page_length;
1015 offset += page_length;
1019 for (i = 0; i < pinned_pages; i++)
1020 page_cache_release(user_pages[i]);
1021 drm_free_large(user_pages);
1027 * Writes data to the object referenced by handle.
1029 * On error, the contents of the buffer that were to be modified are undefined.
1032 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1033 struct drm_file *file)
1035 struct drm_i915_gem_pwrite *args = data;
1036 struct drm_gem_object *obj;
1037 struct drm_i915_gem_object *obj_priv;
1040 ret = i915_mutex_lock_interruptible(dev);
1044 obj = drm_gem_object_lookup(dev, file, args->handle);
1049 obj_priv = to_intel_bo(obj);
1052 /* Bounds check destination. */
1053 if (args->offset > obj->size || args->size > obj->size - args->offset) {
1058 if (args->size == 0)
1061 if (!access_ok(VERIFY_READ,
1062 (char __user *)(uintptr_t)args->data_ptr,
1068 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1075 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1076 * it would end up going through the fenced access, and we'll get
1077 * different detiling behavior between reading and writing.
1078 * pread/pwrite currently are reading and writing from the CPU
1079 * perspective, requiring manual detiling by the client.
1081 if (obj_priv->phys_obj)
1082 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1083 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1084 obj_priv->gtt_space &&
1085 obj->write_domain != I915_GEM_DOMAIN_CPU) {
1086 ret = i915_gem_object_pin(obj, 0, true);
1090 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1094 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1096 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1099 i915_gem_object_unpin(obj);
1101 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1106 if (!i915_gem_object_needs_bit17_swizzle(obj))
1107 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1109 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1113 drm_gem_object_unreference(obj);
1115 mutex_unlock(&dev->struct_mutex);
1120 * Called when user space prepares to use an object with the CPU, either
1121 * through the mmap ioctl's mapping or a GTT mapping.
1124 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv)
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 struct drm_i915_gem_set_domain *args = data;
1129 struct drm_gem_object *obj;
1130 struct drm_i915_gem_object *obj_priv;
1131 uint32_t read_domains = args->read_domains;
1132 uint32_t write_domain = args->write_domain;
1135 if (!(dev->driver->driver_features & DRIVER_GEM))
1138 /* Only handle setting domains to types used by the CPU. */
1139 if (write_domain & I915_GEM_GPU_DOMAINS)
1142 if (read_domains & I915_GEM_GPU_DOMAINS)
1145 /* Having something in the write domain implies it's in the read
1146 * domain, and only that read domain. Enforce that in the request.
1148 if (write_domain != 0 && read_domains != write_domain)
1151 ret = i915_mutex_lock_interruptible(dev);
1155 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1160 obj_priv = to_intel_bo(obj);
1162 intel_mark_busy(dev, obj);
1164 if (read_domains & I915_GEM_DOMAIN_GTT) {
1165 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1167 /* Update the LRU on the fence for the CPU access that's
1170 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1171 struct drm_i915_fence_reg *reg =
1172 &dev_priv->fence_regs[obj_priv->fence_reg];
1173 list_move_tail(®->lru_list,
1174 &dev_priv->mm.fence_list);
1177 /* Silently promote "you're not bound, there was nothing to do"
1178 * to success, since the client was just asking us to
1179 * make sure everything was done.
1184 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1187 /* Maintain LRU order of "inactive" objects */
1188 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1189 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1191 drm_gem_object_unreference(obj);
1193 mutex_unlock(&dev->struct_mutex);
1198 * Called when user space has done writes to this buffer
1201 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1202 struct drm_file *file_priv)
1204 struct drm_i915_gem_sw_finish *args = data;
1205 struct drm_gem_object *obj;
1208 if (!(dev->driver->driver_features & DRIVER_GEM))
1211 ret = i915_mutex_lock_interruptible(dev);
1215 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1221 /* Pinned buffers may be scanout, so flush the cache */
1222 if (to_intel_bo(obj)->pin_count)
1223 i915_gem_object_flush_cpu_write_domain(obj);
1225 drm_gem_object_unreference(obj);
1227 mutex_unlock(&dev->struct_mutex);
1232 * Maps the contents of an object, returning the address it is mapped
1235 * While the mapping holds a reference on the contents of the object, it doesn't
1236 * imply a ref on the object itself.
1239 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1240 struct drm_file *file_priv)
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 struct drm_i915_gem_mmap *args = data;
1244 struct drm_gem_object *obj;
1248 if (!(dev->driver->driver_features & DRIVER_GEM))
1251 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1255 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1256 drm_gem_object_unreference_unlocked(obj);
1260 offset = args->offset;
1262 down_write(¤t->mm->mmap_sem);
1263 addr = do_mmap(obj->filp, 0, args->size,
1264 PROT_READ | PROT_WRITE, MAP_SHARED,
1266 up_write(¤t->mm->mmap_sem);
1267 drm_gem_object_unreference_unlocked(obj);
1268 if (IS_ERR((void *)addr))
1271 args->addr_ptr = (uint64_t) addr;
1277 * i915_gem_fault - fault a page into the GTT
1278 * vma: VMA in question
1281 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1282 * from userspace. The fault handler takes care of binding the object to
1283 * the GTT (if needed), allocating and programming a fence register (again,
1284 * only if needed based on whether the old reg is still valid or the object
1285 * is tiled) and inserting a new PTE into the faulting process.
1287 * Note that the faulting process may involve evicting existing objects
1288 * from the GTT and/or fence registers to make room. So performance may
1289 * suffer if the GTT working set is large or there are few fence registers
1292 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1294 struct drm_gem_object *obj = vma->vm_private_data;
1295 struct drm_device *dev = obj->dev;
1296 drm_i915_private_t *dev_priv = dev->dev_private;
1297 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1298 pgoff_t page_offset;
1301 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1303 /* We don't use vmf->pgoff since that has the fake offset */
1304 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1307 /* Now bind it into the GTT if needed */
1308 mutex_lock(&dev->struct_mutex);
1309 BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable);
1310 if (!i915_gem_object_cpu_accessible(obj_priv))
1311 i915_gem_object_unbind(obj);
1313 if (!obj_priv->gtt_space) {
1314 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1319 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1323 if (!obj_priv->fault_mappable) {
1324 obj_priv->fault_mappable = true;
1325 i915_gem_info_update_mappable(dev_priv, obj, true);
1328 /* Need a new fence register? */
1329 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1330 ret = i915_gem_object_get_fence_reg(obj, true);
1335 if (i915_gem_object_is_inactive(obj_priv))
1336 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1338 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1341 /* Finally, remap it using the new GTT offset */
1342 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1344 mutex_unlock(&dev->struct_mutex);
1349 return VM_FAULT_NOPAGE;
1352 return VM_FAULT_OOM;
1354 return VM_FAULT_SIGBUS;
1359 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1360 * @obj: obj in question
1362 * GEM memory mapping works by handing back to userspace a fake mmap offset
1363 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1364 * up the object based on the offset and sets up the various memory mapping
1367 * This routine allocates and attaches a fake offset for @obj.
1370 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1372 struct drm_device *dev = obj->dev;
1373 struct drm_gem_mm *mm = dev->mm_private;
1374 struct drm_map_list *list;
1375 struct drm_local_map *map;
1378 /* Set the object up for mmap'ing */
1379 list = &obj->map_list;
1380 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1385 map->type = _DRM_GEM;
1386 map->size = obj->size;
1389 /* Get a DRM GEM mmap offset allocated... */
1390 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1391 obj->size / PAGE_SIZE, 0, 0);
1392 if (!list->file_offset_node) {
1393 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1398 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1399 obj->size / PAGE_SIZE, 0);
1400 if (!list->file_offset_node) {
1405 list->hash.key = list->file_offset_node->start;
1406 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1408 DRM_ERROR("failed to add to map hash\n");
1415 drm_mm_put_block(list->file_offset_node);
1424 * i915_gem_release_mmap - remove physical page mappings
1425 * @obj: obj in question
1427 * Preserve the reservation of the mmapping with the DRM core code, but
1428 * relinquish ownership of the pages back to the system.
1430 * It is vital that we remove the page mapping if we have mapped a tiled
1431 * object through the GTT and then lose the fence register due to
1432 * resource pressure. Similarly if the object has been moved out of the
1433 * aperture, than pages mapped into userspace must be revoked. Removing the
1434 * mapping will then trigger a page fault on the next user access, allowing
1435 * fixup by i915_gem_fault().
1438 i915_gem_release_mmap(struct drm_gem_object *obj)
1440 struct drm_device *dev = obj->dev;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1444 if (unlikely(obj->map_list.map && dev->dev_mapping))
1445 unmap_mapping_range(dev->dev_mapping,
1446 (loff_t)obj->map_list.hash.key<<PAGE_SHIFT,
1449 if (obj_priv->fault_mappable) {
1450 obj_priv->fault_mappable = false;
1451 i915_gem_info_update_mappable(dev_priv, obj, false);
1456 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1458 struct drm_device *dev = obj->dev;
1459 struct drm_gem_mm *mm = dev->mm_private;
1460 struct drm_map_list *list = &obj->map_list;
1462 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1463 drm_mm_put_block(list->file_offset_node);
1469 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1470 * @obj: object to check
1472 * Return the required GTT alignment for an object, taking into account
1473 * potential fence register mapping if needed.
1476 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1478 struct drm_device *dev = obj->dev;
1479 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1483 * Minimum alignment is 4k (GTT page size), but might be greater
1484 * if a fence register is needed for the object.
1486 if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1490 * Previous chips need to be aligned to the size of the smallest
1491 * fence register that can contain the object.
1493 if (INTEL_INFO(dev)->gen == 3)
1498 for (i = start; i < obj->size; i <<= 1)
1505 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1507 * @data: GTT mapping ioctl data
1508 * @file_priv: GEM object info
1510 * Simply returns the fake offset to userspace so it can mmap it.
1511 * The mmap call will end up in drm_gem_mmap(), which will set things
1512 * up so we can get faults in the handler above.
1514 * The fault handler will take care of binding the object into the GTT
1515 * (since it may have been evicted to make room for something), allocating
1516 * a fence register, and mapping the appropriate aperture address into
1520 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1521 struct drm_file *file_priv)
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 struct drm_i915_gem_mmap_gtt *args = data;
1525 struct drm_gem_object *obj;
1526 struct drm_i915_gem_object *obj_priv;
1529 if (!(dev->driver->driver_features & DRIVER_GEM))
1532 ret = i915_mutex_lock_interruptible(dev);
1536 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1541 obj_priv = to_intel_bo(obj);
1543 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1548 if (obj_priv->madv != I915_MADV_WILLNEED) {
1549 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1554 if (!obj->map_list.map) {
1555 ret = i915_gem_create_mmap_offset(obj);
1560 args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
1563 drm_gem_object_unreference(obj);
1565 mutex_unlock(&dev->struct_mutex);
1570 i915_gem_object_get_pages_gtt(struct drm_gem_object *obj,
1573 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1575 struct address_space *mapping;
1576 struct inode *inode;
1579 /* Get the list of pages out of our struct file. They'll be pinned
1580 * at this point until we release them.
1582 page_count = obj->size / PAGE_SIZE;
1583 BUG_ON(obj_priv->pages != NULL);
1584 obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1585 if (obj_priv->pages == NULL)
1588 inode = obj->filp->f_path.dentry->d_inode;
1589 mapping = inode->i_mapping;
1590 for (i = 0; i < page_count; i++) {
1591 page = read_cache_page_gfp(mapping, i,
1599 obj_priv->pages[i] = page;
1602 if (obj_priv->tiling_mode != I915_TILING_NONE)
1603 i915_gem_object_do_bit_17_swizzle(obj);
1609 page_cache_release(obj_priv->pages[i]);
1611 drm_free_large(obj_priv->pages);
1612 obj_priv->pages = NULL;
1613 return PTR_ERR(page);
1617 i915_gem_object_put_pages_gtt(struct drm_gem_object *obj)
1619 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1620 int page_count = obj->size / PAGE_SIZE;
1623 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1625 if (obj_priv->tiling_mode != I915_TILING_NONE)
1626 i915_gem_object_save_bit_17_swizzle(obj);
1628 if (obj_priv->madv == I915_MADV_DONTNEED)
1629 obj_priv->dirty = 0;
1631 for (i = 0; i < page_count; i++) {
1632 if (obj_priv->dirty)
1633 set_page_dirty(obj_priv->pages[i]);
1635 if (obj_priv->madv == I915_MADV_WILLNEED)
1636 mark_page_accessed(obj_priv->pages[i]);
1638 page_cache_release(obj_priv->pages[i]);
1640 obj_priv->dirty = 0;
1642 drm_free_large(obj_priv->pages);
1643 obj_priv->pages = NULL;
1647 i915_gem_next_request_seqno(struct drm_device *dev,
1648 struct intel_ring_buffer *ring)
1650 drm_i915_private_t *dev_priv = dev->dev_private;
1652 ring->outstanding_lazy_request = true;
1653 return dev_priv->next_seqno;
1657 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1658 struct intel_ring_buffer *ring)
1660 struct drm_device *dev = obj->dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1663 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1665 BUG_ON(ring == NULL);
1666 obj_priv->ring = ring;
1668 /* Add a reference if we're newly entering the active list. */
1669 if (!obj_priv->active) {
1670 drm_gem_object_reference(obj);
1671 obj_priv->active = 1;
1674 /* Move from whatever list we were on to the tail of execution. */
1675 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1676 list_move_tail(&obj_priv->ring_list, &ring->active_list);
1677 obj_priv->last_rendering_seqno = seqno;
1681 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1683 struct drm_device *dev = obj->dev;
1684 drm_i915_private_t *dev_priv = dev->dev_private;
1685 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1687 BUG_ON(!obj_priv->active);
1688 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1689 list_del_init(&obj_priv->ring_list);
1690 obj_priv->last_rendering_seqno = 0;
1693 /* Immediately discard the backing storage */
1695 i915_gem_object_truncate(struct drm_gem_object *obj)
1697 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1698 struct inode *inode;
1700 /* Our goal here is to return as much of the memory as
1701 * is possible back to the system as we are called from OOM.
1702 * To do this we must instruct the shmfs to drop all of its
1703 * backing pages, *now*. Here we mirror the actions taken
1704 * when by shmem_delete_inode() to release the backing store.
1706 inode = obj->filp->f_path.dentry->d_inode;
1707 truncate_inode_pages(inode->i_mapping, 0);
1708 if (inode->i_op->truncate_range)
1709 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1711 obj_priv->madv = __I915_MADV_PURGED;
1715 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1717 return obj_priv->madv == I915_MADV_DONTNEED;
1721 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1723 struct drm_device *dev = obj->dev;
1724 drm_i915_private_t *dev_priv = dev->dev_private;
1725 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1727 if (obj_priv->pin_count != 0)
1728 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1730 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1731 list_del_init(&obj_priv->ring_list);
1733 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1735 obj_priv->last_rendering_seqno = 0;
1736 obj_priv->ring = NULL;
1737 if (obj_priv->active) {
1738 obj_priv->active = 0;
1739 drm_gem_object_unreference(obj);
1741 WARN_ON(i915_verify_lists(dev));
1745 i915_gem_process_flushing_list(struct drm_device *dev,
1746 uint32_t flush_domains,
1747 struct intel_ring_buffer *ring)
1749 drm_i915_private_t *dev_priv = dev->dev_private;
1750 struct drm_i915_gem_object *obj_priv, *next;
1752 list_for_each_entry_safe(obj_priv, next,
1753 &ring->gpu_write_list,
1755 struct drm_gem_object *obj = &obj_priv->base;
1757 if (obj->write_domain & flush_domains) {
1758 uint32_t old_write_domain = obj->write_domain;
1760 obj->write_domain = 0;
1761 list_del_init(&obj_priv->gpu_write_list);
1762 i915_gem_object_move_to_active(obj, ring);
1764 /* update the fence lru list */
1765 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1766 struct drm_i915_fence_reg *reg =
1767 &dev_priv->fence_regs[obj_priv->fence_reg];
1768 list_move_tail(®->lru_list,
1769 &dev_priv->mm.fence_list);
1772 trace_i915_gem_object_change_domain(obj,
1780 i915_add_request(struct drm_device *dev,
1781 struct drm_file *file,
1782 struct drm_i915_gem_request *request,
1783 struct intel_ring_buffer *ring)
1785 drm_i915_private_t *dev_priv = dev->dev_private;
1786 struct drm_i915_file_private *file_priv = NULL;
1791 BUG_ON(request == NULL);
1794 file_priv = file->driver_priv;
1796 ret = ring->add_request(ring, &seqno);
1800 ring->outstanding_lazy_request = false;
1802 request->seqno = seqno;
1803 request->ring = ring;
1804 request->emitted_jiffies = jiffies;
1805 was_empty = list_empty(&ring->request_list);
1806 list_add_tail(&request->list, &ring->request_list);
1809 spin_lock(&file_priv->mm.lock);
1810 request->file_priv = file_priv;
1811 list_add_tail(&request->client_list,
1812 &file_priv->mm.request_list);
1813 spin_unlock(&file_priv->mm.lock);
1816 if (!dev_priv->mm.suspended) {
1817 mod_timer(&dev_priv->hangcheck_timer,
1818 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1820 queue_delayed_work(dev_priv->wq,
1821 &dev_priv->mm.retire_work, HZ);
1827 * Command execution barrier
1829 * Ensures that all commands in the ring are finished
1830 * before signalling the CPU
1833 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1835 uint32_t flush_domains = 0;
1837 /* The sampler always gets flushed on i965 (sigh) */
1838 if (INTEL_INFO(dev)->gen >= 4)
1839 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1841 ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains);
1845 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1847 struct drm_i915_file_private *file_priv = request->file_priv;
1852 spin_lock(&file_priv->mm.lock);
1853 list_del(&request->client_list);
1854 request->file_priv = NULL;
1855 spin_unlock(&file_priv->mm.lock);
1858 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1859 struct intel_ring_buffer *ring)
1861 while (!list_empty(&ring->request_list)) {
1862 struct drm_i915_gem_request *request;
1864 request = list_first_entry(&ring->request_list,
1865 struct drm_i915_gem_request,
1868 list_del(&request->list);
1869 i915_gem_request_remove_from_client(request);
1873 while (!list_empty(&ring->active_list)) {
1874 struct drm_i915_gem_object *obj_priv;
1876 obj_priv = list_first_entry(&ring->active_list,
1877 struct drm_i915_gem_object,
1880 obj_priv->base.write_domain = 0;
1881 list_del_init(&obj_priv->gpu_write_list);
1882 i915_gem_object_move_to_inactive(&obj_priv->base);
1886 void i915_gem_reset(struct drm_device *dev)
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct drm_i915_gem_object *obj_priv;
1892 i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1893 i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1894 i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1896 /* Remove anything from the flushing lists. The GPU cache is likely
1897 * to be lost on reset along with the data, so simply move the
1898 * lost bo to the inactive list.
1900 while (!list_empty(&dev_priv->mm.flushing_list)) {
1901 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1902 struct drm_i915_gem_object,
1905 obj_priv->base.write_domain = 0;
1906 list_del_init(&obj_priv->gpu_write_list);
1907 i915_gem_object_move_to_inactive(&obj_priv->base);
1910 /* Move everything out of the GPU domains to ensure we do any
1911 * necessary invalidation upon reuse.
1913 list_for_each_entry(obj_priv,
1914 &dev_priv->mm.inactive_list,
1917 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1920 /* The fence registers are invalidated so clear them out */
1921 for (i = 0; i < 16; i++) {
1922 struct drm_i915_fence_reg *reg;
1924 reg = &dev_priv->fence_regs[i];
1928 i915_gem_clear_fence_reg(reg->obj);
1933 * This function clears the request list as sequence numbers are passed.
1936 i915_gem_retire_requests_ring(struct drm_device *dev,
1937 struct intel_ring_buffer *ring)
1939 drm_i915_private_t *dev_priv = dev->dev_private;
1942 if (!ring->status_page.page_addr ||
1943 list_empty(&ring->request_list))
1946 WARN_ON(i915_verify_lists(dev));
1948 seqno = ring->get_seqno(ring);
1949 while (!list_empty(&ring->request_list)) {
1950 struct drm_i915_gem_request *request;
1952 request = list_first_entry(&ring->request_list,
1953 struct drm_i915_gem_request,
1956 if (!i915_seqno_passed(seqno, request->seqno))
1959 trace_i915_gem_request_retire(dev, request->seqno);
1961 list_del(&request->list);
1962 i915_gem_request_remove_from_client(request);
1966 /* Move any buffers on the active list that are no longer referenced
1967 * by the ringbuffer to the flushing/inactive lists as appropriate.
1969 while (!list_empty(&ring->active_list)) {
1970 struct drm_gem_object *obj;
1971 struct drm_i915_gem_object *obj_priv;
1973 obj_priv = list_first_entry(&ring->active_list,
1974 struct drm_i915_gem_object,
1977 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1980 obj = &obj_priv->base;
1981 if (obj->write_domain != 0)
1982 i915_gem_object_move_to_flushing(obj);
1984 i915_gem_object_move_to_inactive(obj);
1987 if (unlikely (dev_priv->trace_irq_seqno &&
1988 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1989 ring->user_irq_put(ring);
1990 dev_priv->trace_irq_seqno = 0;
1993 WARN_ON(i915_verify_lists(dev));
1997 i915_gem_retire_requests(struct drm_device *dev)
1999 drm_i915_private_t *dev_priv = dev->dev_private;
2001 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2002 struct drm_i915_gem_object *obj_priv, *tmp;
2004 /* We must be careful that during unbind() we do not
2005 * accidentally infinitely recurse into retire requests.
2007 * retire -> free -> unbind -> wait -> retire_ring
2009 list_for_each_entry_safe(obj_priv, tmp,
2010 &dev_priv->mm.deferred_free_list,
2012 i915_gem_free_object_tail(&obj_priv->base);
2015 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
2016 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
2017 i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
2021 i915_gem_retire_work_handler(struct work_struct *work)
2023 drm_i915_private_t *dev_priv;
2024 struct drm_device *dev;
2026 dev_priv = container_of(work, drm_i915_private_t,
2027 mm.retire_work.work);
2028 dev = dev_priv->dev;
2030 /* Come back later if the device is busy... */
2031 if (!mutex_trylock(&dev->struct_mutex)) {
2032 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2036 i915_gem_retire_requests(dev);
2038 if (!dev_priv->mm.suspended &&
2039 (!list_empty(&dev_priv->render_ring.request_list) ||
2040 !list_empty(&dev_priv->bsd_ring.request_list) ||
2041 !list_empty(&dev_priv->blt_ring.request_list)))
2042 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2043 mutex_unlock(&dev->struct_mutex);
2047 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2048 bool interruptible, struct intel_ring_buffer *ring)
2050 drm_i915_private_t *dev_priv = dev->dev_private;
2056 if (atomic_read(&dev_priv->mm.wedged))
2059 if (ring->outstanding_lazy_request) {
2060 struct drm_i915_gem_request *request;
2062 request = kzalloc(sizeof(*request), GFP_KERNEL);
2063 if (request == NULL)
2066 ret = i915_add_request(dev, NULL, request, ring);
2072 seqno = request->seqno;
2074 BUG_ON(seqno == dev_priv->next_seqno);
2076 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2077 if (HAS_PCH_SPLIT(dev))
2078 ier = I915_READ(DEIER) | I915_READ(GTIER);
2080 ier = I915_READ(IER);
2082 DRM_ERROR("something (likely vbetool) disabled "
2083 "interrupts, re-enabling\n");
2084 i915_driver_irq_preinstall(dev);
2085 i915_driver_irq_postinstall(dev);
2088 trace_i915_gem_request_wait_begin(dev, seqno);
2090 ring->waiting_seqno = seqno;
2091 ring->user_irq_get(ring);
2093 ret = wait_event_interruptible(ring->irq_queue,
2094 i915_seqno_passed(ring->get_seqno(ring), seqno)
2095 || atomic_read(&dev_priv->mm.wedged));
2097 wait_event(ring->irq_queue,
2098 i915_seqno_passed(ring->get_seqno(ring), seqno)
2099 || atomic_read(&dev_priv->mm.wedged));
2101 ring->user_irq_put(ring);
2102 ring->waiting_seqno = 0;
2104 trace_i915_gem_request_wait_end(dev, seqno);
2106 if (atomic_read(&dev_priv->mm.wedged))
2109 if (ret && ret != -ERESTARTSYS)
2110 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2111 __func__, ret, seqno, ring->get_seqno(ring),
2112 dev_priv->next_seqno);
2114 /* Directly dispatch request retiring. While we have the work queue
2115 * to handle this, the waiter on a request often wants an associated
2116 * buffer to have made it to the inactive list, and we would need
2117 * a separate wait queue to handle that.
2120 i915_gem_retire_requests_ring(dev, ring);
2126 * Waits for a sequence number to be signaled, and cleans up the
2127 * request and object lists appropriately for that event.
2130 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2131 struct intel_ring_buffer *ring)
2133 return i915_do_wait_request(dev, seqno, 1, ring);
2137 i915_gem_flush_ring(struct drm_device *dev,
2138 struct drm_file *file_priv,
2139 struct intel_ring_buffer *ring,
2140 uint32_t invalidate_domains,
2141 uint32_t flush_domains)
2143 ring->flush(ring, invalidate_domains, flush_domains);
2144 i915_gem_process_flushing_list(dev, flush_domains, ring);
2148 i915_gem_flush(struct drm_device *dev,
2149 struct drm_file *file_priv,
2150 uint32_t invalidate_domains,
2151 uint32_t flush_domains,
2152 uint32_t flush_rings)
2154 drm_i915_private_t *dev_priv = dev->dev_private;
2156 if (flush_domains & I915_GEM_DOMAIN_CPU)
2157 drm_agp_chipset_flush(dev);
2159 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2160 if (flush_rings & RING_RENDER)
2161 i915_gem_flush_ring(dev, file_priv,
2162 &dev_priv->render_ring,
2163 invalidate_domains, flush_domains);
2164 if (flush_rings & RING_BSD)
2165 i915_gem_flush_ring(dev, file_priv,
2166 &dev_priv->bsd_ring,
2167 invalidate_domains, flush_domains);
2168 if (flush_rings & RING_BLT)
2169 i915_gem_flush_ring(dev, file_priv,
2170 &dev_priv->blt_ring,
2171 invalidate_domains, flush_domains);
2176 * Ensures that all rendering to the object has completed and the object is
2177 * safe to unbind from the GTT or access from the CPU.
2180 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2183 struct drm_device *dev = obj->dev;
2184 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2187 /* This function only exists to support waiting for existing rendering,
2188 * not for emitting required flushes.
2190 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2192 /* If there is rendering queued on the buffer being evicted, wait for
2195 if (obj_priv->active) {
2196 ret = i915_do_wait_request(dev,
2197 obj_priv->last_rendering_seqno,
2208 * Unbinds an object from the GTT aperture.
2211 i915_gem_object_unbind(struct drm_gem_object *obj)
2213 struct drm_device *dev = obj->dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2218 if (obj_priv->gtt_space == NULL)
2221 if (obj_priv->pin_count != 0) {
2222 DRM_ERROR("Attempting to unbind pinned buffer\n");
2226 /* blow away mappings if mapped through GTT */
2227 i915_gem_release_mmap(obj);
2229 /* Move the object to the CPU domain to ensure that
2230 * any possible CPU writes while it's not in the GTT
2231 * are flushed when we go to remap it. This will
2232 * also ensure that all pending GPU writes are finished
2235 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2236 if (ret == -ERESTARTSYS)
2238 /* Continue on if we fail due to EIO, the GPU is hung so we
2239 * should be safe and we need to cleanup or else we might
2240 * cause memory corruption through use-after-free.
2243 i915_gem_clflush_object(obj);
2244 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2247 /* release the fence reg _after_ flushing */
2248 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2249 i915_gem_clear_fence_reg(obj);
2251 drm_unbind_agp(obj_priv->agp_mem);
2252 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2254 i915_gem_object_put_pages_gtt(obj);
2256 i915_gem_info_remove_gtt(dev_priv, obj);
2257 list_del_init(&obj_priv->mm_list);
2259 drm_mm_put_block(obj_priv->gtt_space);
2260 obj_priv->gtt_space = NULL;
2261 obj_priv->gtt_offset = 0;
2263 if (i915_gem_object_is_purgeable(obj_priv))
2264 i915_gem_object_truncate(obj);
2266 trace_i915_gem_object_unbind(obj);
2271 static int i915_ring_idle(struct drm_device *dev,
2272 struct intel_ring_buffer *ring)
2274 if (list_empty(&ring->gpu_write_list))
2277 i915_gem_flush_ring(dev, NULL, ring,
2278 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2279 return i915_wait_request(dev,
2280 i915_gem_next_request_seqno(dev, ring),
2285 i915_gpu_idle(struct drm_device *dev)
2287 drm_i915_private_t *dev_priv = dev->dev_private;
2291 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2292 list_empty(&dev_priv->render_ring.active_list) &&
2293 list_empty(&dev_priv->bsd_ring.active_list) &&
2294 list_empty(&dev_priv->blt_ring.active_list));
2298 /* Flush everything onto the inactive list. */
2299 ret = i915_ring_idle(dev, &dev_priv->render_ring);
2303 ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2307 ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2314 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2316 struct drm_gem_object *obj = reg->obj;
2317 struct drm_device *dev = obj->dev;
2318 drm_i915_private_t *dev_priv = dev->dev_private;
2319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2320 int regnum = obj_priv->fence_reg;
2323 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2325 val |= obj_priv->gtt_offset & 0xfffff000;
2326 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2327 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2329 if (obj_priv->tiling_mode == I915_TILING_Y)
2330 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2331 val |= I965_FENCE_REG_VALID;
2333 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2336 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2338 struct drm_gem_object *obj = reg->obj;
2339 struct drm_device *dev = obj->dev;
2340 drm_i915_private_t *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2342 int regnum = obj_priv->fence_reg;
2345 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2347 val |= obj_priv->gtt_offset & 0xfffff000;
2348 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2349 if (obj_priv->tiling_mode == I915_TILING_Y)
2350 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2351 val |= I965_FENCE_REG_VALID;
2353 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2356 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2358 struct drm_gem_object *obj = reg->obj;
2359 struct drm_device *dev = obj->dev;
2360 drm_i915_private_t *dev_priv = dev->dev_private;
2361 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2362 int regnum = obj_priv->fence_reg;
2364 uint32_t fence_reg, val;
2367 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2368 (obj_priv->gtt_offset & (obj->size - 1))) {
2369 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2370 __func__, obj_priv->gtt_offset, obj->size);
2374 if (obj_priv->tiling_mode == I915_TILING_Y &&
2375 HAS_128_BYTE_Y_TILING(dev))
2380 /* Note: pitch better be a power of two tile widths */
2381 pitch_val = obj_priv->stride / tile_width;
2382 pitch_val = ffs(pitch_val) - 1;
2384 if (obj_priv->tiling_mode == I915_TILING_Y &&
2385 HAS_128_BYTE_Y_TILING(dev))
2386 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2388 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2390 val = obj_priv->gtt_offset;
2391 if (obj_priv->tiling_mode == I915_TILING_Y)
2392 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2393 val |= I915_FENCE_SIZE_BITS(obj->size);
2394 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2395 val |= I830_FENCE_REG_VALID;
2398 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2400 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2401 I915_WRITE(fence_reg, val);
2404 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2406 struct drm_gem_object *obj = reg->obj;
2407 struct drm_device *dev = obj->dev;
2408 drm_i915_private_t *dev_priv = dev->dev_private;
2409 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2410 int regnum = obj_priv->fence_reg;
2413 uint32_t fence_size_bits;
2415 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2416 (obj_priv->gtt_offset & (obj->size - 1))) {
2417 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2418 __func__, obj_priv->gtt_offset);
2422 pitch_val = obj_priv->stride / 128;
2423 pitch_val = ffs(pitch_val) - 1;
2424 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2426 val = obj_priv->gtt_offset;
2427 if (obj_priv->tiling_mode == I915_TILING_Y)
2428 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2429 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2430 WARN_ON(fence_size_bits & ~0x00000f00);
2431 val |= fence_size_bits;
2432 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2433 val |= I830_FENCE_REG_VALID;
2435 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2438 static int i915_find_fence_reg(struct drm_device *dev,
2441 struct drm_i915_fence_reg *reg = NULL;
2442 struct drm_i915_gem_object *obj_priv = NULL;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct drm_gem_object *obj = NULL;
2447 /* First try to find a free reg */
2449 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2450 reg = &dev_priv->fence_regs[i];
2454 obj_priv = to_intel_bo(reg->obj);
2455 if (!obj_priv->pin_count)
2462 /* None available, try to steal one or wait for a user to finish */
2463 i = I915_FENCE_REG_NONE;
2464 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2467 obj_priv = to_intel_bo(obj);
2469 if (obj_priv->pin_count)
2473 i = obj_priv->fence_reg;
2477 BUG_ON(i == I915_FENCE_REG_NONE);
2479 /* We only have a reference on obj from the active list. put_fence_reg
2480 * might drop that one, causing a use-after-free in it. So hold a
2481 * private reference to obj like the other callers of put_fence_reg
2482 * (set_tiling ioctl) do. */
2483 drm_gem_object_reference(obj);
2484 ret = i915_gem_object_put_fence_reg(obj, interruptible);
2485 drm_gem_object_unreference(obj);
2493 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2494 * @obj: object to map through a fence reg
2496 * When mapping objects through the GTT, userspace wants to be able to write
2497 * to them without having to worry about swizzling if the object is tiled.
2499 * This function walks the fence regs looking for a free one for @obj,
2500 * stealing one if it can't find any.
2502 * It then sets up the reg based on the object's properties: address, pitch
2503 * and tiling format.
2506 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2509 struct drm_device *dev = obj->dev;
2510 struct drm_i915_private *dev_priv = dev->dev_private;
2511 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2512 struct drm_i915_fence_reg *reg = NULL;
2515 /* Just update our place in the LRU if our fence is getting used. */
2516 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2517 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2518 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2522 switch (obj_priv->tiling_mode) {
2523 case I915_TILING_NONE:
2524 WARN(1, "allocating a fence for non-tiled object?\n");
2527 if (!obj_priv->stride)
2529 WARN((obj_priv->stride & (512 - 1)),
2530 "object 0x%08x is X tiled but has non-512B pitch\n",
2531 obj_priv->gtt_offset);
2534 if (!obj_priv->stride)
2536 WARN((obj_priv->stride & (128 - 1)),
2537 "object 0x%08x is Y tiled but has non-128B pitch\n",
2538 obj_priv->gtt_offset);
2542 ret = i915_find_fence_reg(dev, interruptible);
2546 obj_priv->fence_reg = ret;
2547 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2548 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2552 switch (INTEL_INFO(dev)->gen) {
2554 sandybridge_write_fence_reg(reg);
2558 i965_write_fence_reg(reg);
2561 i915_write_fence_reg(reg);
2564 i830_write_fence_reg(reg);
2568 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2569 obj_priv->tiling_mode);
2575 * i915_gem_clear_fence_reg - clear out fence register info
2576 * @obj: object to clear
2578 * Zeroes out the fence register itself and clears out the associated
2579 * data structures in dev_priv and obj_priv.
2582 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2584 struct drm_device *dev = obj->dev;
2585 drm_i915_private_t *dev_priv = dev->dev_private;
2586 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2587 struct drm_i915_fence_reg *reg =
2588 &dev_priv->fence_regs[obj_priv->fence_reg];
2591 switch (INTEL_INFO(dev)->gen) {
2593 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2594 (obj_priv->fence_reg * 8), 0);
2598 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2601 if (obj_priv->fence_reg >= 8)
2602 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2605 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2607 I915_WRITE(fence_reg, 0);
2612 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2613 list_del_init(®->lru_list);
2617 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2618 * to the buffer to finish, and then resets the fence register.
2619 * @obj: tiled object holding a fence register.
2620 * @bool: whether the wait upon the fence is interruptible
2622 * Zeroes out the fence register itself and clears out the associated
2623 * data structures in dev_priv and obj_priv.
2626 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2629 struct drm_device *dev = obj->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2632 struct drm_i915_fence_reg *reg;
2634 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2637 /* If we've changed tiling, GTT-mappings of the object
2638 * need to re-fault to ensure that the correct fence register
2639 * setup is in place.
2641 i915_gem_release_mmap(obj);
2643 /* On the i915, GPU access to tiled buffers is via a fence,
2644 * therefore we must wait for any outstanding access to complete
2645 * before clearing the fence.
2647 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2651 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2655 ret = i915_gem_object_wait_rendering(obj, interruptible);
2662 i915_gem_object_flush_gtt_write_domain(obj);
2663 i915_gem_clear_fence_reg(obj);
2669 * Finds free space in the GTT aperture and binds the object there.
2672 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
2676 struct drm_device *dev = obj->dev;
2677 drm_i915_private_t *dev_priv = dev->dev_private;
2678 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2679 struct drm_mm_node *free_space;
2680 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2683 if (obj_priv->madv != I915_MADV_WILLNEED) {
2684 DRM_ERROR("Attempting to bind a purgeable object\n");
2689 alignment = i915_gem_get_gtt_alignment(obj);
2690 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2691 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2695 /* If the object is bigger than the entire aperture, reject it early
2696 * before evicting everything in a vain attempt to find space.
2699 (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2700 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2707 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2708 obj->size, alignment, 0,
2709 dev_priv->mm.gtt_mappable_end,
2712 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2713 obj->size, alignment, 0);
2715 if (free_space != NULL) {
2717 obj_priv->gtt_space =
2718 drm_mm_get_block_range_generic(free_space,
2721 dev_priv->mm.gtt_mappable_end,
2724 obj_priv->gtt_space =
2725 drm_mm_get_block(free_space, obj->size,
2728 if (obj_priv->gtt_space == NULL) {
2729 /* If the gtt is empty and we're still having trouble
2730 * fitting our object in, we're out of memory.
2732 ret = i915_gem_evict_something(dev, obj->size, alignment,
2740 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2742 drm_mm_put_block(obj_priv->gtt_space);
2743 obj_priv->gtt_space = NULL;
2745 if (ret == -ENOMEM) {
2746 /* first try to clear up some space from the GTT */
2747 ret = i915_gem_evict_something(dev, obj->size,
2748 alignment, mappable);
2750 /* now try to shrink everyone else */
2765 /* Create an AGP memory structure pointing at our pages, and bind it
2768 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2770 obj->size >> PAGE_SHIFT,
2771 obj_priv->gtt_space->start,
2772 obj_priv->agp_type);
2773 if (obj_priv->agp_mem == NULL) {
2774 i915_gem_object_put_pages_gtt(obj);
2775 drm_mm_put_block(obj_priv->gtt_space);
2776 obj_priv->gtt_space = NULL;
2778 ret = i915_gem_evict_something(dev, obj->size, alignment,
2786 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2788 /* keep track of bounds object by adding it to the inactive list */
2789 list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2790 i915_gem_info_add_gtt(dev_priv, obj);
2792 /* Assert that the object is not currently in any GPU domain. As it
2793 * wasn't in the GTT, there shouldn't be any way it could have been in
2796 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2797 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2799 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable);
2805 i915_gem_clflush_object(struct drm_gem_object *obj)
2807 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2809 /* If we don't have a page list set up, then we're not pinned
2810 * to GPU, and we can ignore the cache flush because it'll happen
2811 * again at bind time.
2813 if (obj_priv->pages == NULL)
2816 trace_i915_gem_object_clflush(obj);
2818 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2821 /** Flushes any GPU write domain for the object if it's dirty. */
2823 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2826 struct drm_device *dev = obj->dev;
2827 uint32_t old_write_domain;
2829 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2832 /* Queue the GPU write cache flushing we need. */
2833 old_write_domain = obj->write_domain;
2834 i915_gem_flush_ring(dev, NULL,
2835 to_intel_bo(obj)->ring,
2836 0, obj->write_domain);
2837 BUG_ON(obj->write_domain);
2839 trace_i915_gem_object_change_domain(obj,
2846 return i915_gem_object_wait_rendering(obj, true);
2849 /** Flushes the GTT write domain for the object if it's dirty. */
2851 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2853 uint32_t old_write_domain;
2855 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2858 /* No actual flushing is required for the GTT write domain. Writes
2859 * to it immediately go to main memory as far as we know, so there's
2860 * no chipset flush. It also doesn't land in render cache.
2862 i915_gem_release_mmap(obj);
2864 old_write_domain = obj->write_domain;
2865 obj->write_domain = 0;
2867 trace_i915_gem_object_change_domain(obj,
2872 /** Flushes the CPU write domain for the object if it's dirty. */
2874 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2876 struct drm_device *dev = obj->dev;
2877 uint32_t old_write_domain;
2879 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2882 i915_gem_clflush_object(obj);
2883 drm_agp_chipset_flush(dev);
2884 old_write_domain = obj->write_domain;
2885 obj->write_domain = 0;
2887 trace_i915_gem_object_change_domain(obj,
2893 * Moves a single object to the GTT read, and possibly write domain.
2895 * This function returns when the move is complete, including waiting on
2899 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2901 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2902 uint32_t old_write_domain, old_read_domains;
2905 /* Not valid to be called on unbound objects. */
2906 if (obj_priv->gtt_space == NULL)
2909 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2913 i915_gem_object_flush_cpu_write_domain(obj);
2916 ret = i915_gem_object_wait_rendering(obj, true);
2921 old_write_domain = obj->write_domain;
2922 old_read_domains = obj->read_domains;
2924 /* It should now be out of any other write domains, and we can update
2925 * the domain values for our changes.
2927 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2928 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2930 obj->read_domains = I915_GEM_DOMAIN_GTT;
2931 obj->write_domain = I915_GEM_DOMAIN_GTT;
2932 obj_priv->dirty = 1;
2935 trace_i915_gem_object_change_domain(obj,
2943 * Prepare buffer for display plane. Use uninterruptible for possible flush
2944 * wait, as in modesetting process we're not supposed to be interrupted.
2947 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2950 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2951 uint32_t old_read_domains;
2954 /* Not valid to be called on unbound objects. */
2955 if (obj_priv->gtt_space == NULL)
2958 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2962 /* Currently, we are always called from an non-interruptible context. */
2964 ret = i915_gem_object_wait_rendering(obj, false);
2969 i915_gem_object_flush_cpu_write_domain(obj);
2971 old_read_domains = obj->read_domains;
2972 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2974 trace_i915_gem_object_change_domain(obj,
2982 * Moves a single object to the CPU read, and possibly write domain.
2984 * This function returns when the move is complete, including waiting on
2988 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2990 uint32_t old_write_domain, old_read_domains;
2993 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2997 i915_gem_object_flush_gtt_write_domain(obj);
2999 /* If we have a partially-valid cache of the object in the CPU,
3000 * finish invalidating it and free the per-page flags.
3002 i915_gem_object_set_to_full_cpu_read_domain(obj);
3005 ret = i915_gem_object_wait_rendering(obj, true);
3010 old_write_domain = obj->write_domain;
3011 old_read_domains = obj->read_domains;
3013 /* Flush the CPU cache if it's still invalid. */
3014 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3015 i915_gem_clflush_object(obj);
3017 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3020 /* It should now be out of any other write domains, and we can update
3021 * the domain values for our changes.
3023 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3025 /* If we're writing through the CPU, then the GPU read domains will
3026 * need to be invalidated at next use.
3029 obj->read_domains = I915_GEM_DOMAIN_CPU;
3030 obj->write_domain = I915_GEM_DOMAIN_CPU;
3033 trace_i915_gem_object_change_domain(obj,
3041 * Set the next domain for the specified object. This
3042 * may not actually perform the necessary flushing/invaliding though,
3043 * as that may want to be batched with other set_domain operations
3045 * This is (we hope) the only really tricky part of gem. The goal
3046 * is fairly simple -- track which caches hold bits of the object
3047 * and make sure they remain coherent. A few concrete examples may
3048 * help to explain how it works. For shorthand, we use the notation
3049 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3050 * a pair of read and write domain masks.
3052 * Case 1: the batch buffer
3058 * 5. Unmapped from GTT
3061 * Let's take these a step at a time
3064 * Pages allocated from the kernel may still have
3065 * cache contents, so we set them to (CPU, CPU) always.
3066 * 2. Written by CPU (using pwrite)
3067 * The pwrite function calls set_domain (CPU, CPU) and
3068 * this function does nothing (as nothing changes)
3070 * This function asserts that the object is not
3071 * currently in any GPU-based read or write domains
3073 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3074 * As write_domain is zero, this function adds in the
3075 * current read domains (CPU+COMMAND, 0).
3076 * flush_domains is set to CPU.
3077 * invalidate_domains is set to COMMAND
3078 * clflush is run to get data out of the CPU caches
3079 * then i915_dev_set_domain calls i915_gem_flush to
3080 * emit an MI_FLUSH and drm_agp_chipset_flush
3081 * 5. Unmapped from GTT
3082 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3083 * flush_domains and invalidate_domains end up both zero
3084 * so no flushing/invalidating happens
3088 * Case 2: The shared render buffer
3092 * 3. Read/written by GPU
3093 * 4. set_domain to (CPU,CPU)
3094 * 5. Read/written by CPU
3095 * 6. Read/written by GPU
3098 * Same as last example, (CPU, CPU)
3100 * Nothing changes (assertions find that it is not in the GPU)
3101 * 3. Read/written by GPU
3102 * execbuffer calls set_domain (RENDER, RENDER)
3103 * flush_domains gets CPU
3104 * invalidate_domains gets GPU
3106 * MI_FLUSH and drm_agp_chipset_flush
3107 * 4. set_domain (CPU, CPU)
3108 * flush_domains gets GPU
3109 * invalidate_domains gets CPU
3110 * wait_rendering (obj) to make sure all drawing is complete.
3111 * This will include an MI_FLUSH to get the data from GPU
3113 * clflush (obj) to invalidate the CPU cache
3114 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3115 * 5. Read/written by CPU
3116 * cache lines are loaded and dirtied
3117 * 6. Read written by GPU
3118 * Same as last GPU access
3120 * Case 3: The constant buffer
3125 * 4. Updated (written) by CPU again
3134 * flush_domains = CPU
3135 * invalidate_domains = RENDER
3138 * drm_agp_chipset_flush
3139 * 4. Updated (written) by CPU again
3141 * flush_domains = 0 (no previous write domain)
3142 * invalidate_domains = 0 (no new read domains)
3145 * flush_domains = CPU
3146 * invalidate_domains = RENDER
3149 * drm_agp_chipset_flush
3152 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
3153 struct intel_ring_buffer *ring)
3155 struct drm_device *dev = obj->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3158 uint32_t invalidate_domains = 0;
3159 uint32_t flush_domains = 0;
3162 * If the object isn't moving to a new write domain,
3163 * let the object stay in multiple read domains
3165 if (obj->pending_write_domain == 0)
3166 obj->pending_read_domains |= obj->read_domains;
3169 * Flush the current write domain if
3170 * the new read domains don't match. Invalidate
3171 * any read domains which differ from the old
3174 if (obj->write_domain &&
3175 obj->write_domain != obj->pending_read_domains) {
3176 flush_domains |= obj->write_domain;
3177 invalidate_domains |=
3178 obj->pending_read_domains & ~obj->write_domain;
3181 * Invalidate any read caches which may have
3182 * stale data. That is, any new read domains.
3184 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3185 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3186 i915_gem_clflush_object(obj);
3188 /* blow away mappings if mapped through GTT */
3189 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
3190 i915_gem_release_mmap(obj);
3192 /* The actual obj->write_domain will be updated with
3193 * pending_write_domain after we emit the accumulated flush for all
3194 * of our domain changes in execbuffers (which clears objects'
3195 * write_domains). So if we have a current write domain that we
3196 * aren't changing, set pending_write_domain to that.
3198 if (flush_domains == 0 && obj->pending_write_domain == 0)
3199 obj->pending_write_domain = obj->write_domain;
3201 dev->invalidate_domains |= invalidate_domains;
3202 dev->flush_domains |= flush_domains;
3203 if (flush_domains & I915_GEM_GPU_DOMAINS)
3204 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3205 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
3206 dev_priv->mm.flush_rings |= ring->id;
3210 * Moves the object from a partially CPU read to a full one.
3212 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3213 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3216 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3218 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3220 if (!obj_priv->page_cpu_valid)
3223 /* If we're partially in the CPU read domain, finish moving it in.
3225 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3228 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3229 if (obj_priv->page_cpu_valid[i])
3231 drm_clflush_pages(obj_priv->pages + i, 1);
3235 /* Free the page_cpu_valid mappings which are now stale, whether
3236 * or not we've got I915_GEM_DOMAIN_CPU.
3238 kfree(obj_priv->page_cpu_valid);
3239 obj_priv->page_cpu_valid = NULL;
3243 * Set the CPU read domain on a range of the object.
3245 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3246 * not entirely valid. The page_cpu_valid member of the object flags which
3247 * pages have been flushed, and will be respected by
3248 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3249 * of the whole object.
3251 * This function returns when the move is complete, including waiting on
3255 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3256 uint64_t offset, uint64_t size)
3258 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3259 uint32_t old_read_domains;
3262 if (offset == 0 && size == obj->size)
3263 return i915_gem_object_set_to_cpu_domain(obj, 0);
3265 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3268 i915_gem_object_flush_gtt_write_domain(obj);
3270 /* If we're already fully in the CPU read domain, we're done. */
3271 if (obj_priv->page_cpu_valid == NULL &&
3272 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3275 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3276 * newly adding I915_GEM_DOMAIN_CPU
3278 if (obj_priv->page_cpu_valid == NULL) {
3279 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3281 if (obj_priv->page_cpu_valid == NULL)
3283 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3284 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3286 /* Flush the cache on any pages that are still invalid from the CPU's
3289 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3291 if (obj_priv->page_cpu_valid[i])
3294 drm_clflush_pages(obj_priv->pages + i, 1);
3296 obj_priv->page_cpu_valid[i] = 1;
3299 /* It should now be out of any other write domains, and we can update
3300 * the domain values for our changes.
3302 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3304 old_read_domains = obj->read_domains;
3305 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3307 trace_i915_gem_object_change_domain(obj,
3315 * Pin an object to the GTT and evaluate the relocations landing in it.
3318 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3319 struct drm_file *file_priv,
3320 struct drm_i915_gem_exec_object2 *entry)
3322 struct drm_device *dev = obj->base.dev;
3323 drm_i915_private_t *dev_priv = dev->dev_private;
3324 struct drm_i915_gem_relocation_entry __user *user_relocs;
3325 struct drm_gem_object *target_obj = NULL;
3326 uint32_t target_handle = 0;
3329 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3330 for (i = 0; i < entry->relocation_count; i++) {
3331 struct drm_i915_gem_relocation_entry reloc;
3332 uint32_t target_offset;
3334 if (__copy_from_user_inatomic(&reloc,
3341 if (reloc.target_handle != target_handle) {
3342 drm_gem_object_unreference(target_obj);
3344 target_obj = drm_gem_object_lookup(dev, file_priv,
3345 reloc.target_handle);
3346 if (target_obj == NULL) {
3351 target_handle = reloc.target_handle;
3353 target_offset = to_intel_bo(target_obj)->gtt_offset;
3356 DRM_INFO("%s: obj %p offset %08x target %d "
3357 "read %08x write %08x gtt %08x "
3358 "presumed %08x delta %08x\n",
3362 (int) reloc.target_handle,
3363 (int) reloc.read_domains,
3364 (int) reloc.write_domain,
3365 (int) target_offset,
3366 (int) reloc.presumed_offset,
3370 /* The target buffer should have appeared before us in the
3371 * exec_object list, so it should have a GTT space bound by now.
3373 if (target_offset == 0) {
3374 DRM_ERROR("No GTT space found for object %d\n",
3375 reloc.target_handle);
3380 /* Validate that the target is in a valid r/w GPU domain */
3381 if (reloc.write_domain & (reloc.write_domain - 1)) {
3382 DRM_ERROR("reloc with multiple write domains: "
3383 "obj %p target %d offset %d "
3384 "read %08x write %08x",
3385 obj, reloc.target_handle,
3388 reloc.write_domain);
3392 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3393 reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3394 DRM_ERROR("reloc with read/write CPU domains: "
3395 "obj %p target %d offset %d "
3396 "read %08x write %08x",
3397 obj, reloc.target_handle,
3400 reloc.write_domain);
3404 if (reloc.write_domain && target_obj->pending_write_domain &&
3405 reloc.write_domain != target_obj->pending_write_domain) {
3406 DRM_ERROR("Write domain conflict: "
3407 "obj %p target %d offset %d "
3408 "new %08x old %08x\n",
3409 obj, reloc.target_handle,
3412 target_obj->pending_write_domain);
3417 target_obj->pending_read_domains |= reloc.read_domains;
3418 target_obj->pending_write_domain |= reloc.write_domain;
3420 /* If the relocation already has the right value in it, no
3421 * more work needs to be done.
3423 if (target_offset == reloc.presumed_offset)
3426 /* Check that the relocation address is valid... */
3427 if (reloc.offset > obj->base.size - 4) {
3428 DRM_ERROR("Relocation beyond object bounds: "
3429 "obj %p target %d offset %d size %d.\n",
3430 obj, reloc.target_handle,
3431 (int) reloc.offset, (int) obj->base.size);
3435 if (reloc.offset & 3) {
3436 DRM_ERROR("Relocation not 4-byte aligned: "
3437 "obj %p target %d offset %d.\n",
3438 obj, reloc.target_handle,
3439 (int) reloc.offset);
3444 /* and points to somewhere within the target object. */
3445 if (reloc.delta >= target_obj->size) {
3446 DRM_ERROR("Relocation beyond target object bounds: "
3447 "obj %p target %d delta %d size %d.\n",
3448 obj, reloc.target_handle,
3449 (int) reloc.delta, (int) target_obj->size);
3454 reloc.delta += target_offset;
3455 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3456 uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3459 vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]);
3460 *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3461 kunmap_atomic(vaddr);
3463 uint32_t __iomem *reloc_entry;
3464 void __iomem *reloc_page;
3466 ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3470 /* Map the page containing the relocation we're going to perform. */
3471 reloc.offset += obj->gtt_offset;
3472 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3473 reloc.offset & PAGE_MASK);
3474 reloc_entry = (uint32_t __iomem *)
3475 (reloc_page + (reloc.offset & ~PAGE_MASK));
3476 iowrite32(reloc.delta, reloc_entry);
3477 io_mapping_unmap_atomic(reloc_page);
3480 /* and update the user's relocation entry */
3481 reloc.presumed_offset = target_offset;
3482 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
3483 &reloc.presumed_offset,
3484 sizeof(reloc.presumed_offset))) {
3490 drm_gem_object_unreference(target_obj);
3495 i915_gem_execbuffer_pin(struct drm_device *dev,
3496 struct drm_file *file,
3497 struct drm_gem_object **object_list,
3498 struct drm_i915_gem_exec_object2 *exec_list,
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3504 /* attempt to pin all of the buffers into the GTT */
3505 for (retry = 0; retry < 2; retry++) {
3507 for (i = 0; i < count; i++) {
3508 struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3509 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3511 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3512 obj->tiling_mode != I915_TILING_NONE;
3514 /* g33/pnv can't fence buffers in the unmappable part */
3515 bool need_mappable =
3516 entry->relocation_count ? true : need_fence;
3518 /* Check fence reg constraints and rebind if necessary */
3520 !i915_gem_object_fence_offset_ok(&obj->base,
3521 obj->tiling_mode)) {
3522 ret = i915_gem_object_unbind(&obj->base);
3527 ret = i915_gem_object_pin(&obj->base,
3534 * Pre-965 chips need a fence register set up in order
3535 * to properly handle blits to/from tiled surfaces.
3538 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3540 i915_gem_object_unpin(&obj->base);
3544 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3547 entry->offset = obj->gtt_offset;
3551 i915_gem_object_unpin(object_list[i]);
3556 if (ret != -ENOSPC || retry)
3559 ret = i915_gem_evict_everything(dev);
3567 /* Throttle our rendering by waiting until the ring has completed our requests
3568 * emitted over 20 msec ago.
3570 * Note that if we were to use the current jiffies each time around the loop,
3571 * we wouldn't escape the function with any frames outstanding if the time to
3572 * render a frame was over 20ms.
3574 * This should get us reasonable parallelism between CPU and GPU but also
3575 * relatively low latency when blocking on a particular request to finish.
3578 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct drm_i915_file_private *file_priv = file->driver_priv;
3582 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3583 struct drm_i915_gem_request *request;
3584 struct intel_ring_buffer *ring = NULL;
3588 spin_lock(&file_priv->mm.lock);
3589 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3590 if (time_after_eq(request->emitted_jiffies, recent_enough))
3593 ring = request->ring;
3594 seqno = request->seqno;
3596 spin_unlock(&file_priv->mm.lock);
3602 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3603 /* And wait for the seqno passing without holding any locks and
3604 * causing extra latency for others. This is safe as the irq
3605 * generation is designed to be run atomically and so is
3608 ring->user_irq_get(ring);
3609 ret = wait_event_interruptible(ring->irq_queue,
3610 i915_seqno_passed(ring->get_seqno(ring), seqno)
3611 || atomic_read(&dev_priv->mm.wedged));
3612 ring->user_irq_put(ring);
3614 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3619 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3625 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3626 uint64_t exec_offset)
3628 uint32_t exec_start, exec_len;
3630 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3631 exec_len = (uint32_t) exec->batch_len;
3633 if ((exec_start | exec_len) & 0x7)
3643 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3648 for (i = 0; i < count; i++) {
3649 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3650 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3652 if (!access_ok(VERIFY_READ, ptr, length))
3655 /* we may also need to update the presumed offsets */
3656 if (!access_ok(VERIFY_WRITE, ptr, length))
3659 if (fault_in_pages_readable(ptr, length))
3667 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3668 struct drm_file *file,
3669 struct drm_i915_gem_execbuffer2 *args,
3670 struct drm_i915_gem_exec_object2 *exec_list)
3672 drm_i915_private_t *dev_priv = dev->dev_private;
3673 struct drm_gem_object **object_list = NULL;
3674 struct drm_gem_object *batch_obj;
3675 struct drm_clip_rect *cliprects = NULL;
3676 struct drm_i915_gem_request *request = NULL;
3678 uint64_t exec_offset;
3680 struct intel_ring_buffer *ring = NULL;
3682 ret = i915_gem_check_is_wedged(dev);
3686 ret = validate_exec_list(exec_list, args->buffer_count);
3691 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3692 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3694 switch (args->flags & I915_EXEC_RING_MASK) {
3695 case I915_EXEC_DEFAULT:
3696 case I915_EXEC_RENDER:
3697 ring = &dev_priv->render_ring;
3700 if (!HAS_BSD(dev)) {
3701 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3704 ring = &dev_priv->bsd_ring;
3707 if (!HAS_BLT(dev)) {
3708 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3711 ring = &dev_priv->blt_ring;
3714 DRM_ERROR("execbuf with unknown ring: %d\n",
3715 (int)(args->flags & I915_EXEC_RING_MASK));
3719 if (args->buffer_count < 1) {
3720 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3723 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3724 if (object_list == NULL) {
3725 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3726 args->buffer_count);
3731 if (args->num_cliprects != 0) {
3732 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3734 if (cliprects == NULL) {
3739 ret = copy_from_user(cliprects,
3740 (struct drm_clip_rect __user *)
3741 (uintptr_t) args->cliprects_ptr,
3742 sizeof(*cliprects) * args->num_cliprects);
3744 DRM_ERROR("copy %d cliprects failed: %d\n",
3745 args->num_cliprects, ret);
3751 request = kzalloc(sizeof(*request), GFP_KERNEL);
3752 if (request == NULL) {
3757 ret = i915_mutex_lock_interruptible(dev);
3761 if (dev_priv->mm.suspended) {
3762 mutex_unlock(&dev->struct_mutex);
3767 /* Look up object handles */
3768 for (i = 0; i < args->buffer_count; i++) {
3769 struct drm_i915_gem_object *obj_priv;
3771 object_list[i] = drm_gem_object_lookup(dev, file,
3772 exec_list[i].handle);
3773 if (object_list[i] == NULL) {
3774 DRM_ERROR("Invalid object handle %d at index %d\n",
3775 exec_list[i].handle, i);
3776 /* prevent error path from reading uninitialized data */
3777 args->buffer_count = i + 1;
3782 obj_priv = to_intel_bo(object_list[i]);
3783 if (obj_priv->in_execbuffer) {
3784 DRM_ERROR("Object %p appears more than once in object list\n",
3786 /* prevent error path from reading uninitialized data */
3787 args->buffer_count = i + 1;
3791 obj_priv->in_execbuffer = true;
3794 /* Move the objects en-masse into the GTT, evicting if necessary. */
3795 ret = i915_gem_execbuffer_pin(dev, file,
3796 object_list, exec_list,
3797 args->buffer_count);
3801 /* The objects are in their final locations, apply the relocations. */
3802 for (i = 0; i < args->buffer_count; i++) {
3803 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3804 obj->base.pending_read_domains = 0;
3805 obj->base.pending_write_domain = 0;
3806 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3811 /* Set the pending read domains for the batch buffer to COMMAND */
3812 batch_obj = object_list[args->buffer_count-1];
3813 if (batch_obj->pending_write_domain) {
3814 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3818 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3820 /* Sanity check the batch buffer */
3821 exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3822 ret = i915_gem_check_execbuffer(args, exec_offset);
3824 DRM_ERROR("execbuf with invalid offset/length\n");
3828 /* Zero the global flush/invalidate flags. These
3829 * will be modified as new domains are computed
3832 dev->invalidate_domains = 0;
3833 dev->flush_domains = 0;
3834 dev_priv->mm.flush_rings = 0;
3835 for (i = 0; i < args->buffer_count; i++)
3836 i915_gem_object_set_to_gpu_domain(object_list[i], ring);
3838 if (dev->invalidate_domains | dev->flush_domains) {
3840 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3842 dev->invalidate_domains,
3843 dev->flush_domains);
3845 i915_gem_flush(dev, file,
3846 dev->invalidate_domains,
3848 dev_priv->mm.flush_rings);
3852 for (i = 0; i < args->buffer_count; i++) {
3853 i915_gem_object_check_coherency(object_list[i],
3854 exec_list[i].handle);
3859 i915_gem_dump_object(batch_obj,
3865 /* Check for any pending flips. As we only maintain a flip queue depth
3866 * of 1, we can simply insert a WAIT for the next display flip prior
3867 * to executing the batch and avoid stalling the CPU.
3870 for (i = 0; i < args->buffer_count; i++) {
3871 if (object_list[i]->write_domain)
3872 flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3875 int plane, flip_mask;
3877 for (plane = 0; flips >> plane; plane++) {
3878 if (((flips >> plane) & 1) == 0)
3882 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3884 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3886 ret = intel_ring_begin(ring, 2);
3890 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
3891 intel_ring_emit(ring, MI_NOOP);
3892 intel_ring_advance(ring);
3896 /* Exec the batchbuffer */
3897 ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset);
3899 DRM_ERROR("dispatch failed %d\n", ret);
3903 for (i = 0; i < args->buffer_count; i++) {
3904 struct drm_gem_object *obj = object_list[i];
3906 obj->read_domains = obj->pending_read_domains;
3907 obj->write_domain = obj->pending_write_domain;
3909 i915_gem_object_move_to_active(obj, ring);
3910 if (obj->write_domain) {
3911 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3912 obj_priv->dirty = 1;
3913 list_move_tail(&obj_priv->gpu_write_list,
3914 &ring->gpu_write_list);
3915 intel_mark_busy(dev, obj);
3918 trace_i915_gem_object_change_domain(obj,
3924 * Ensure that the commands in the batch buffer are
3925 * finished before the interrupt fires
3927 i915_retire_commands(dev, ring);
3929 if (i915_add_request(dev, file, request, ring))
3930 ring->outstanding_lazy_request = true;
3935 for (i = 0; i < args->buffer_count; i++) {
3936 if (object_list[i] == NULL)
3939 to_intel_bo(object_list[i])->in_execbuffer = false;
3940 drm_gem_object_unreference(object_list[i]);
3943 mutex_unlock(&dev->struct_mutex);
3946 drm_free_large(object_list);
3954 * Legacy execbuffer just creates an exec2 list from the original exec object
3955 * list array and passes it to the real function.
3958 i915_gem_execbuffer(struct drm_device *dev, void *data,
3959 struct drm_file *file_priv)
3961 struct drm_i915_gem_execbuffer *args = data;
3962 struct drm_i915_gem_execbuffer2 exec2;
3963 struct drm_i915_gem_exec_object *exec_list = NULL;
3964 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3968 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3969 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3972 if (args->buffer_count < 1) {
3973 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3977 /* Copy in the exec list from userland */
3978 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3979 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3980 if (exec_list == NULL || exec2_list == NULL) {
3981 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3982 args->buffer_count);
3983 drm_free_large(exec_list);
3984 drm_free_large(exec2_list);
3987 ret = copy_from_user(exec_list,
3988 (struct drm_i915_relocation_entry __user *)
3989 (uintptr_t) args->buffers_ptr,
3990 sizeof(*exec_list) * args->buffer_count);
3992 DRM_ERROR("copy %d exec entries failed %d\n",
3993 args->buffer_count, ret);
3994 drm_free_large(exec_list);
3995 drm_free_large(exec2_list);
3999 for (i = 0; i < args->buffer_count; i++) {
4000 exec2_list[i].handle = exec_list[i].handle;
4001 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4002 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4003 exec2_list[i].alignment = exec_list[i].alignment;
4004 exec2_list[i].offset = exec_list[i].offset;
4005 if (INTEL_INFO(dev)->gen < 4)
4006 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4008 exec2_list[i].flags = 0;
4011 exec2.buffers_ptr = args->buffers_ptr;
4012 exec2.buffer_count = args->buffer_count;
4013 exec2.batch_start_offset = args->batch_start_offset;
4014 exec2.batch_len = args->batch_len;
4015 exec2.DR1 = args->DR1;
4016 exec2.DR4 = args->DR4;
4017 exec2.num_cliprects = args->num_cliprects;
4018 exec2.cliprects_ptr = args->cliprects_ptr;
4019 exec2.flags = I915_EXEC_RENDER;
4021 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4023 /* Copy the new buffer offsets back to the user's exec list. */
4024 for (i = 0; i < args->buffer_count; i++)
4025 exec_list[i].offset = exec2_list[i].offset;
4026 /* ... and back out to userspace */
4027 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4028 (uintptr_t) args->buffers_ptr,
4030 sizeof(*exec_list) * args->buffer_count);
4033 DRM_ERROR("failed to copy %d exec entries "
4034 "back to user (%d)\n",
4035 args->buffer_count, ret);
4039 drm_free_large(exec_list);
4040 drm_free_large(exec2_list);
4045 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4046 struct drm_file *file_priv)
4048 struct drm_i915_gem_execbuffer2 *args = data;
4049 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4053 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4054 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4057 if (args->buffer_count < 1) {
4058 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4062 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4063 if (exec2_list == NULL) {
4064 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4065 args->buffer_count);
4068 ret = copy_from_user(exec2_list,
4069 (struct drm_i915_relocation_entry __user *)
4070 (uintptr_t) args->buffers_ptr,
4071 sizeof(*exec2_list) * args->buffer_count);
4073 DRM_ERROR("copy %d exec entries failed %d\n",
4074 args->buffer_count, ret);
4075 drm_free_large(exec2_list);
4079 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4081 /* Copy the new buffer offsets back to the user's exec list. */
4082 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4083 (uintptr_t) args->buffers_ptr,
4085 sizeof(*exec2_list) * args->buffer_count);
4088 DRM_ERROR("failed to copy %d exec entries "
4089 "back to user (%d)\n",
4090 args->buffer_count, ret);
4094 drm_free_large(exec2_list);
4099 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
4102 struct drm_device *dev = obj->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4107 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4108 WARN_ON(i915_verify_lists(dev));
4110 if (obj_priv->gtt_space != NULL) {
4112 alignment = i915_gem_get_gtt_alignment(obj);
4113 if (obj_priv->gtt_offset & (alignment - 1) ||
4114 (mappable && !i915_gem_object_cpu_accessible(obj_priv))) {
4115 WARN(obj_priv->pin_count,
4116 "bo is already pinned with incorrect alignment:"
4117 " offset=%x, req.alignment=%x\n",
4118 obj_priv->gtt_offset, alignment);
4119 ret = i915_gem_object_unbind(obj);
4125 if (obj_priv->gtt_space == NULL) {
4126 ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable);
4131 obj_priv->pin_count++;
4133 /* If the object is not active and not pending a flush,
4134 * remove it from the inactive list
4136 if (obj_priv->pin_count == 1) {
4137 i915_gem_info_add_pin(dev_priv, obj, mappable);
4138 if (!obj_priv->active)
4139 list_move_tail(&obj_priv->mm_list,
4140 &dev_priv->mm.pinned_list);
4142 BUG_ON(!obj_priv->pin_mappable && mappable);
4144 WARN_ON(i915_verify_lists(dev));
4149 i915_gem_object_unpin(struct drm_gem_object *obj)
4151 struct drm_device *dev = obj->dev;
4152 drm_i915_private_t *dev_priv = dev->dev_private;
4153 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4155 WARN_ON(i915_verify_lists(dev));
4156 obj_priv->pin_count--;
4157 BUG_ON(obj_priv->pin_count < 0);
4158 BUG_ON(obj_priv->gtt_space == NULL);
4160 /* If the object is no longer pinned, and is
4161 * neither active nor being flushed, then stick it on
4164 if (obj_priv->pin_count == 0) {
4165 if (!obj_priv->active)
4166 list_move_tail(&obj_priv->mm_list,
4167 &dev_priv->mm.inactive_list);
4168 i915_gem_info_remove_pin(dev_priv, obj);
4170 WARN_ON(i915_verify_lists(dev));
4174 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4175 struct drm_file *file_priv)
4177 struct drm_i915_gem_pin *args = data;
4178 struct drm_gem_object *obj;
4179 struct drm_i915_gem_object *obj_priv;
4182 ret = i915_mutex_lock_interruptible(dev);
4186 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4191 obj_priv = to_intel_bo(obj);
4193 if (obj_priv->madv != I915_MADV_WILLNEED) {
4194 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4199 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4200 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4206 obj_priv->user_pin_count++;
4207 obj_priv->pin_filp = file_priv;
4208 if (obj_priv->user_pin_count == 1) {
4209 ret = i915_gem_object_pin(obj, args->alignment, true);
4214 /* XXX - flush the CPU caches for pinned objects
4215 * as the X server doesn't manage domains yet
4217 i915_gem_object_flush_cpu_write_domain(obj);
4218 args->offset = obj_priv->gtt_offset;
4220 drm_gem_object_unreference(obj);
4222 mutex_unlock(&dev->struct_mutex);
4227 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4228 struct drm_file *file_priv)
4230 struct drm_i915_gem_pin *args = data;
4231 struct drm_gem_object *obj;
4232 struct drm_i915_gem_object *obj_priv;
4235 ret = i915_mutex_lock_interruptible(dev);
4239 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4244 obj_priv = to_intel_bo(obj);
4246 if (obj_priv->pin_filp != file_priv) {
4247 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4252 obj_priv->user_pin_count--;
4253 if (obj_priv->user_pin_count == 0) {
4254 obj_priv->pin_filp = NULL;
4255 i915_gem_object_unpin(obj);
4259 drm_gem_object_unreference(obj);
4261 mutex_unlock(&dev->struct_mutex);
4266 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4267 struct drm_file *file_priv)
4269 struct drm_i915_gem_busy *args = data;
4270 struct drm_gem_object *obj;
4271 struct drm_i915_gem_object *obj_priv;
4274 ret = i915_mutex_lock_interruptible(dev);
4278 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4283 obj_priv = to_intel_bo(obj);
4285 /* Count all active objects as busy, even if they are currently not used
4286 * by the gpu. Users of this interface expect objects to eventually
4287 * become non-busy without any further actions, therefore emit any
4288 * necessary flushes here.
4290 args->busy = obj_priv->active;
4292 /* Unconditionally flush objects, even when the gpu still uses this
4293 * object. Userspace calling this function indicates that it wants to
4294 * use this buffer rather sooner than later, so issuing the required
4295 * flush earlier is beneficial.
4297 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4298 i915_gem_flush_ring(dev, file_priv,
4300 0, obj->write_domain);
4302 /* Update the active list for the hardware's current position.
4303 * Otherwise this only updates on a delayed timer or when irqs
4304 * are actually unmasked, and our working set ends up being
4305 * larger than required.
4307 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4309 args->busy = obj_priv->active;
4312 drm_gem_object_unreference(obj);
4314 mutex_unlock(&dev->struct_mutex);
4319 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4320 struct drm_file *file_priv)
4322 return i915_gem_ring_throttle(dev, file_priv);
4326 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4327 struct drm_file *file_priv)
4329 struct drm_i915_gem_madvise *args = data;
4330 struct drm_gem_object *obj;
4331 struct drm_i915_gem_object *obj_priv;
4334 switch (args->madv) {
4335 case I915_MADV_DONTNEED:
4336 case I915_MADV_WILLNEED:
4342 ret = i915_mutex_lock_interruptible(dev);
4346 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4351 obj_priv = to_intel_bo(obj);
4353 if (obj_priv->pin_count) {
4358 if (obj_priv->madv != __I915_MADV_PURGED)
4359 obj_priv->madv = args->madv;
4361 /* if the object is no longer bound, discard its backing storage */
4362 if (i915_gem_object_is_purgeable(obj_priv) &&
4363 obj_priv->gtt_space == NULL)
4364 i915_gem_object_truncate(obj);
4366 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4369 drm_gem_object_unreference(obj);
4371 mutex_unlock(&dev->struct_mutex);
4375 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 struct drm_i915_gem_object *obj;
4381 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4385 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4390 i915_gem_info_add_obj(dev_priv, size);
4392 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4393 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4395 obj->agp_type = AGP_USER_MEMORY;
4396 obj->base.driver_private = NULL;
4397 obj->fence_reg = I915_FENCE_REG_NONE;
4398 INIT_LIST_HEAD(&obj->mm_list);
4399 INIT_LIST_HEAD(&obj->ring_list);
4400 INIT_LIST_HEAD(&obj->gpu_write_list);
4401 obj->madv = I915_MADV_WILLNEED;
4406 int i915_gem_init_object(struct drm_gem_object *obj)
4413 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4415 struct drm_device *dev = obj->dev;
4416 drm_i915_private_t *dev_priv = dev->dev_private;
4417 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4420 ret = i915_gem_object_unbind(obj);
4421 if (ret == -ERESTARTSYS) {
4422 list_move(&obj_priv->mm_list,
4423 &dev_priv->mm.deferred_free_list);
4427 if (obj->map_list.map)
4428 i915_gem_free_mmap_offset(obj);
4430 drm_gem_object_release(obj);
4431 i915_gem_info_remove_obj(dev_priv, obj->size);
4433 kfree(obj_priv->page_cpu_valid);
4434 kfree(obj_priv->bit_17);
4438 void i915_gem_free_object(struct drm_gem_object *obj)
4440 struct drm_device *dev = obj->dev;
4441 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4443 trace_i915_gem_object_destroy(obj);
4445 while (obj_priv->pin_count > 0)
4446 i915_gem_object_unpin(obj);
4448 if (obj_priv->phys_obj)
4449 i915_gem_detach_phys_object(dev, obj);
4451 i915_gem_free_object_tail(obj);
4455 i915_gem_idle(struct drm_device *dev)
4457 drm_i915_private_t *dev_priv = dev->dev_private;
4460 mutex_lock(&dev->struct_mutex);
4462 if (dev_priv->mm.suspended) {
4463 mutex_unlock(&dev->struct_mutex);
4467 ret = i915_gpu_idle(dev);
4469 mutex_unlock(&dev->struct_mutex);
4473 /* Under UMS, be paranoid and evict. */
4474 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4475 ret = i915_gem_evict_inactive(dev);
4477 mutex_unlock(&dev->struct_mutex);
4482 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4483 * We need to replace this with a semaphore, or something.
4484 * And not confound mm.suspended!
4486 dev_priv->mm.suspended = 1;
4487 del_timer_sync(&dev_priv->hangcheck_timer);
4489 i915_kernel_lost_context(dev);
4490 i915_gem_cleanup_ringbuffer(dev);
4492 mutex_unlock(&dev->struct_mutex);
4494 /* Cancel the retire work handler, which should be idle now. */
4495 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4501 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4502 * over cache flushing.
4505 i915_gem_init_pipe_control(struct drm_device *dev)
4507 drm_i915_private_t *dev_priv = dev->dev_private;
4508 struct drm_gem_object *obj;
4509 struct drm_i915_gem_object *obj_priv;
4512 obj = i915_gem_alloc_object(dev, 4096);
4514 DRM_ERROR("Failed to allocate seqno page\n");
4518 obj_priv = to_intel_bo(obj);
4519 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4521 ret = i915_gem_object_pin(obj, 4096, true);
4525 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4526 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4527 if (dev_priv->seqno_page == NULL)
4530 dev_priv->seqno_obj = obj;
4531 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4536 i915_gem_object_unpin(obj);
4538 drm_gem_object_unreference(obj);
4545 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4547 drm_i915_private_t *dev_priv = dev->dev_private;
4548 struct drm_gem_object *obj;
4549 struct drm_i915_gem_object *obj_priv;
4551 obj = dev_priv->seqno_obj;
4552 obj_priv = to_intel_bo(obj);
4553 kunmap(obj_priv->pages[0]);
4554 i915_gem_object_unpin(obj);
4555 drm_gem_object_unreference(obj);
4556 dev_priv->seqno_obj = NULL;
4558 dev_priv->seqno_page = NULL;
4562 i915_gem_init_ringbuffer(struct drm_device *dev)
4564 drm_i915_private_t *dev_priv = dev->dev_private;
4567 if (HAS_PIPE_CONTROL(dev)) {
4568 ret = i915_gem_init_pipe_control(dev);
4573 ret = intel_init_render_ring_buffer(dev);
4575 goto cleanup_pipe_control;
4578 ret = intel_init_bsd_ring_buffer(dev);
4580 goto cleanup_render_ring;
4584 ret = intel_init_blt_ring_buffer(dev);
4586 goto cleanup_bsd_ring;
4589 dev_priv->next_seqno = 1;
4594 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4595 cleanup_render_ring:
4596 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4597 cleanup_pipe_control:
4598 if (HAS_PIPE_CONTROL(dev))
4599 i915_gem_cleanup_pipe_control(dev);
4604 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4606 drm_i915_private_t *dev_priv = dev->dev_private;
4608 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4609 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4610 intel_cleanup_ring_buffer(&dev_priv->blt_ring);
4611 if (HAS_PIPE_CONTROL(dev))
4612 i915_gem_cleanup_pipe_control(dev);
4616 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4617 struct drm_file *file_priv)
4619 drm_i915_private_t *dev_priv = dev->dev_private;
4622 if (drm_core_check_feature(dev, DRIVER_MODESET))
4625 if (atomic_read(&dev_priv->mm.wedged)) {
4626 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4627 atomic_set(&dev_priv->mm.wedged, 0);
4630 mutex_lock(&dev->struct_mutex);
4631 dev_priv->mm.suspended = 0;
4633 ret = i915_gem_init_ringbuffer(dev);
4635 mutex_unlock(&dev->struct_mutex);
4639 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4640 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4641 BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
4642 BUG_ON(!list_empty(&dev_priv->blt_ring.active_list));
4643 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4644 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4645 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4646 BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
4647 BUG_ON(!list_empty(&dev_priv->blt_ring.request_list));
4648 mutex_unlock(&dev->struct_mutex);
4650 ret = drm_irq_install(dev);
4652 goto cleanup_ringbuffer;
4657 mutex_lock(&dev->struct_mutex);
4658 i915_gem_cleanup_ringbuffer(dev);
4659 dev_priv->mm.suspended = 1;
4660 mutex_unlock(&dev->struct_mutex);
4666 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4667 struct drm_file *file_priv)
4669 if (drm_core_check_feature(dev, DRIVER_MODESET))
4672 drm_irq_uninstall(dev);
4673 return i915_gem_idle(dev);
4677 i915_gem_lastclose(struct drm_device *dev)
4681 if (drm_core_check_feature(dev, DRIVER_MODESET))
4684 ret = i915_gem_idle(dev);
4686 DRM_ERROR("failed to idle hardware: %d\n", ret);
4690 init_ring_lists(struct intel_ring_buffer *ring)
4692 INIT_LIST_HEAD(&ring->active_list);
4693 INIT_LIST_HEAD(&ring->request_list);
4694 INIT_LIST_HEAD(&ring->gpu_write_list);
4698 i915_gem_load(struct drm_device *dev)
4701 drm_i915_private_t *dev_priv = dev->dev_private;
4703 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4704 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4705 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4706 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4707 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4708 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4709 init_ring_lists(&dev_priv->render_ring);
4710 init_ring_lists(&dev_priv->bsd_ring);
4711 init_ring_lists(&dev_priv->blt_ring);
4712 for (i = 0; i < 16; i++)
4713 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4714 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4715 i915_gem_retire_work_handler);
4716 init_completion(&dev_priv->error_completion);
4718 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4720 u32 tmp = I915_READ(MI_ARB_STATE);
4721 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4722 /* arb state is a masked write, so set bit + bit in mask */
4723 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4724 I915_WRITE(MI_ARB_STATE, tmp);
4728 /* Old X drivers will take 0-2 for front, back, depth buffers */
4729 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4730 dev_priv->fence_reg_start = 3;
4732 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4733 dev_priv->num_fence_regs = 16;
4735 dev_priv->num_fence_regs = 8;
4737 /* Initialize fence registers to zero */
4738 switch (INTEL_INFO(dev)->gen) {
4740 for (i = 0; i < 16; i++)
4741 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4745 for (i = 0; i < 16; i++)
4746 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4749 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4750 for (i = 0; i < 8; i++)
4751 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4753 for (i = 0; i < 8; i++)
4754 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4757 i915_gem_detect_bit_6_swizzle(dev);
4758 init_waitqueue_head(&dev_priv->pending_flip_queue);
4760 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4761 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4762 register_shrinker(&dev_priv->mm.inactive_shrinker);
4766 * Create a physically contiguous memory object for this object
4767 * e.g. for cursor + overlay regs
4769 static int i915_gem_init_phys_object(struct drm_device *dev,
4770 int id, int size, int align)
4772 drm_i915_private_t *dev_priv = dev->dev_private;
4773 struct drm_i915_gem_phys_object *phys_obj;
4776 if (dev_priv->mm.phys_objs[id - 1] || !size)
4779 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4785 phys_obj->handle = drm_pci_alloc(dev, size, align);
4786 if (!phys_obj->handle) {
4791 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4794 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4802 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4804 drm_i915_private_t *dev_priv = dev->dev_private;
4805 struct drm_i915_gem_phys_object *phys_obj;
4807 if (!dev_priv->mm.phys_objs[id - 1])
4810 phys_obj = dev_priv->mm.phys_objs[id - 1];
4811 if (phys_obj->cur_obj) {
4812 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4816 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4818 drm_pci_free(dev, phys_obj->handle);
4820 dev_priv->mm.phys_objs[id - 1] = NULL;
4823 void i915_gem_free_all_phys_object(struct drm_device *dev)
4827 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4828 i915_gem_free_phys_object(dev, i);
4831 void i915_gem_detach_phys_object(struct drm_device *dev,
4832 struct drm_gem_object *obj)
4834 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
4835 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4840 if (!obj_priv->phys_obj)
4842 vaddr = obj_priv->phys_obj->handle->vaddr;
4844 page_count = obj->size / PAGE_SIZE;
4846 for (i = 0; i < page_count; i++) {
4847 struct page *page = read_cache_page_gfp(mapping, i,
4848 GFP_HIGHUSER | __GFP_RECLAIMABLE);
4849 if (!IS_ERR(page)) {
4850 char *dst = kmap_atomic(page);
4851 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4854 drm_clflush_pages(&page, 1);
4856 set_page_dirty(page);
4857 mark_page_accessed(page);
4858 page_cache_release(page);
4861 drm_agp_chipset_flush(dev);
4863 obj_priv->phys_obj->cur_obj = NULL;
4864 obj_priv->phys_obj = NULL;
4868 i915_gem_attach_phys_object(struct drm_device *dev,
4869 struct drm_gem_object *obj,
4873 struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping;
4874 drm_i915_private_t *dev_priv = dev->dev_private;
4875 struct drm_i915_gem_object *obj_priv;
4880 if (id > I915_MAX_PHYS_OBJECT)
4883 obj_priv = to_intel_bo(obj);
4885 if (obj_priv->phys_obj) {
4886 if (obj_priv->phys_obj->id == id)
4888 i915_gem_detach_phys_object(dev, obj);
4891 /* create a new object */
4892 if (!dev_priv->mm.phys_objs[id - 1]) {
4893 ret = i915_gem_init_phys_object(dev, id,
4896 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4901 /* bind to the object */
4902 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4903 obj_priv->phys_obj->cur_obj = obj;
4905 page_count = obj->size / PAGE_SIZE;
4907 for (i = 0; i < page_count; i++) {
4911 page = read_cache_page_gfp(mapping, i,
4912 GFP_HIGHUSER | __GFP_RECLAIMABLE);
4914 return PTR_ERR(page);
4916 src = kmap_atomic(obj_priv->pages[i]);
4917 dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4918 memcpy(dst, src, PAGE_SIZE);
4921 mark_page_accessed(page);
4922 page_cache_release(page);
4929 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4930 struct drm_i915_gem_pwrite *args,
4931 struct drm_file *file_priv)
4933 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4936 char __user *user_data;
4938 user_data = (char __user *) (uintptr_t) args->data_ptr;
4939 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4941 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4942 ret = copy_from_user(obj_addr, user_data, args->size);
4946 drm_agp_chipset_flush(dev);
4950 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4952 struct drm_i915_file_private *file_priv = file->driver_priv;
4954 /* Clean up our request list when the client is going away, so that
4955 * later retire_requests won't dereference our soon-to-be-gone
4958 spin_lock(&file_priv->mm.lock);
4959 while (!list_empty(&file_priv->mm.request_list)) {
4960 struct drm_i915_gem_request *request;
4962 request = list_first_entry(&file_priv->mm.request_list,
4963 struct drm_i915_gem_request,
4965 list_del(&request->client_list);
4966 request->file_priv = NULL;
4968 spin_unlock(&file_priv->mm.lock);
4972 i915_gpu_is_active(struct drm_device *dev)
4974 drm_i915_private_t *dev_priv = dev->dev_private;
4977 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4978 list_empty(&dev_priv->mm.active_list);
4980 return !lists_empty;
4984 i915_gem_inactive_shrink(struct shrinker *shrinker,
4988 struct drm_i915_private *dev_priv =
4989 container_of(shrinker,
4990 struct drm_i915_private,
4991 mm.inactive_shrinker);
4992 struct drm_device *dev = dev_priv->dev;
4993 struct drm_i915_gem_object *obj, *next;
4996 if (!mutex_trylock(&dev->struct_mutex))
4999 /* "fast-path" to count number of available objects */
5000 if (nr_to_scan == 0) {
5002 list_for_each_entry(obj,
5003 &dev_priv->mm.inactive_list,
5006 mutex_unlock(&dev->struct_mutex);
5007 return cnt / 100 * sysctl_vfs_cache_pressure;
5011 /* first scan for clean buffers */
5012 i915_gem_retire_requests(dev);
5014 list_for_each_entry_safe(obj, next,
5015 &dev_priv->mm.inactive_list,
5017 if (i915_gem_object_is_purgeable(obj)) {
5018 i915_gem_object_unbind(&obj->base);
5019 if (--nr_to_scan == 0)
5024 /* second pass, evict/count anything still on the inactive list */
5026 list_for_each_entry_safe(obj, next,
5027 &dev_priv->mm.inactive_list,
5030 i915_gem_object_unbind(&obj->base);
5036 if (nr_to_scan && i915_gpu_is_active(dev)) {
5038 * We are desperate for pages, so as a last resort, wait
5039 * for the GPU to finish and discard whatever we can.
5040 * This has a dramatic impact to reduce the number of
5041 * OOM-killer events whilst running the GPU aggressively.
5043 if (i915_gpu_idle(dev) == 0)
5046 mutex_unlock(&dev->struct_mutex);
5047 return cnt / 100 * sysctl_vfs_cache_pressure;