2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
49 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
50 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
52 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
54 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
57 if (!i915_gem_object_is_coherent(obj))
60 return obj->pin_display;
64 insert_mappable_node(struct i915_ggtt *ggtt,
65 struct drm_mm_node *node, u32 size)
67 memset(node, 0, sizeof(*node));
68 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
69 size, 0, I915_COLOR_UNEVICTABLE,
70 0, ggtt->mappable_end,
75 remove_mappable_node(struct drm_mm_node *node)
77 drm_mm_remove_node(node);
80 /* some bookkeeping */
81 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
84 spin_lock(&dev_priv->mm.object_stat_lock);
85 dev_priv->mm.object_count++;
86 dev_priv->mm.object_memory += size;
87 spin_unlock(&dev_priv->mm.object_stat_lock);
90 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
93 spin_lock(&dev_priv->mm.object_stat_lock);
94 dev_priv->mm.object_count--;
95 dev_priv->mm.object_memory -= size;
96 spin_unlock(&dev_priv->mm.object_stat_lock);
100 i915_gem_wait_for_error(struct i915_gpu_error *error)
107 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
108 * userspace. If it takes that long something really bad is going on and
109 * we should simply try to bail out and fail as gracefully as possible.
111 ret = wait_event_interruptible_timeout(error->reset_queue,
112 !i915_reset_backoff(error),
115 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
117 } else if (ret < 0) {
124 int i915_mutex_lock_interruptible(struct drm_device *dev)
126 struct drm_i915_private *dev_priv = to_i915(dev);
129 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
133 ret = mutex_lock_interruptible(&dev->struct_mutex);
141 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
142 struct drm_file *file)
144 struct drm_i915_private *dev_priv = to_i915(dev);
145 struct i915_ggtt *ggtt = &dev_priv->ggtt;
146 struct drm_i915_gem_get_aperture *args = data;
147 struct i915_vma *vma;
151 mutex_lock(&dev->struct_mutex);
152 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
153 if (i915_vma_is_pinned(vma))
154 pinned += vma->node.size;
155 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
156 if (i915_vma_is_pinned(vma))
157 pinned += vma->node.size;
158 mutex_unlock(&dev->struct_mutex);
160 args->aper_size = ggtt->base.total;
161 args->aper_available_size = args->aper_size - pinned;
166 static struct sg_table *
167 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
169 struct address_space *mapping = obj->base.filp->f_mapping;
170 drm_dma_handle_t *phys;
172 struct scatterlist *sg;
176 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
177 return ERR_PTR(-EINVAL);
179 /* Always aligning to the object size, allows a single allocation
180 * to handle all possible callers, and given typical object sizes,
181 * the alignment of the buddy allocation will naturally match.
183 phys = drm_pci_alloc(obj->base.dev,
185 roundup_pow_of_two(obj->base.size));
187 return ERR_PTR(-ENOMEM);
190 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
194 page = shmem_read_mapping_page(mapping, i);
200 src = kmap_atomic(page);
201 memcpy(vaddr, src, PAGE_SIZE);
202 drm_clflush_virt_range(vaddr, PAGE_SIZE);
209 i915_gem_chipset_flush(to_i915(obj->base.dev));
211 st = kmalloc(sizeof(*st), GFP_KERNEL);
213 st = ERR_PTR(-ENOMEM);
217 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
219 st = ERR_PTR(-ENOMEM);
225 sg->length = obj->base.size;
227 sg_dma_address(sg) = phys->busaddr;
228 sg_dma_len(sg) = obj->base.size;
230 obj->phys_handle = phys;
234 drm_pci_free(obj->base.dev, phys);
239 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
240 struct sg_table *pages,
243 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
245 if (obj->mm.madv == I915_MADV_DONTNEED)
246 obj->mm.dirty = false;
249 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
250 !i915_gem_object_is_coherent(obj))
251 drm_clflush_sg(pages);
253 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
254 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
258 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
259 struct sg_table *pages)
261 __i915_gem_object_release_shmem(obj, pages, false);
264 struct address_space *mapping = obj->base.filp->f_mapping;
265 char *vaddr = obj->phys_handle->vaddr;
268 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
272 page = shmem_read_mapping_page(mapping, i);
276 dst = kmap_atomic(page);
277 drm_clflush_virt_range(vaddr, PAGE_SIZE);
278 memcpy(dst, vaddr, PAGE_SIZE);
281 set_page_dirty(page);
282 if (obj->mm.madv == I915_MADV_WILLNEED)
283 mark_page_accessed(page);
287 obj->mm.dirty = false;
290 sg_free_table(pages);
293 drm_pci_free(obj->base.dev, obj->phys_handle);
297 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
299 i915_gem_object_unpin_pages(obj);
302 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
303 .get_pages = i915_gem_object_get_pages_phys,
304 .put_pages = i915_gem_object_put_pages_phys,
305 .release = i915_gem_object_release_phys,
308 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
310 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
312 struct i915_vma *vma;
313 LIST_HEAD(still_in_list);
316 lockdep_assert_held(&obj->base.dev->struct_mutex);
318 /* Closed vma are removed from the obj->vma_list - but they may
319 * still have an active binding on the object. To remove those we
320 * must wait for all rendering to complete to the object (as unbinding
321 * must anyway), and retire the requests.
323 ret = i915_gem_object_wait(obj,
324 I915_WAIT_INTERRUPTIBLE |
327 MAX_SCHEDULE_TIMEOUT,
332 i915_gem_retire_requests(to_i915(obj->base.dev));
334 while ((vma = list_first_entry_or_null(&obj->vma_list,
337 list_move_tail(&vma->obj_link, &still_in_list);
338 ret = i915_vma_unbind(vma);
342 list_splice(&still_in_list, &obj->vma_list);
348 i915_gem_object_wait_fence(struct dma_fence *fence,
351 struct intel_rps_client *rps)
353 struct drm_i915_gem_request *rq;
355 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
357 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
360 if (!dma_fence_is_i915(fence))
361 return dma_fence_wait_timeout(fence,
362 flags & I915_WAIT_INTERRUPTIBLE,
365 rq = to_request(fence);
366 if (i915_gem_request_completed(rq))
369 /* This client is about to stall waiting for the GPU. In many cases
370 * this is undesirable and limits the throughput of the system, as
371 * many clients cannot continue processing user input/output whilst
372 * blocked. RPS autotuning may take tens of milliseconds to respond
373 * to the GPU load and thus incurs additional latency for the client.
374 * We can circumvent that by promoting the GPU frequency to maximum
375 * before we wait. This makes the GPU throttle up much more quickly
376 * (good for benchmarks and user experience, e.g. window animations),
377 * but at a cost of spending more power processing the workload
378 * (bad for battery). Not all clients even want their results
379 * immediately and for them we should just let the GPU select its own
380 * frequency to maximise efficiency. To prevent a single client from
381 * forcing the clocks too high for the whole system, we only allow
382 * each client to waitboost once in a busy period.
385 if (INTEL_GEN(rq->i915) >= 6)
386 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
391 timeout = i915_wait_request(rq, flags, timeout);
394 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
395 i915_gem_request_retire_upto(rq);
397 if (rps && i915_gem_request_global_seqno(rq) == intel_engine_last_submit(rq->engine)) {
398 /* The GPU is now idle and this client has stalled.
399 * Since no other client has submitted a request in the
400 * meantime, assume that this client is the only one
401 * supplying work to the GPU but is unable to keep that
402 * work supplied because it is waiting. Since the GPU is
403 * then never kept fully busy, RPS autoclocking will
404 * keep the clocks relatively low, causing further delays.
405 * Compensate by giving the synchronous client credit for
406 * a waitboost next time.
408 spin_lock(&rq->i915->rps.client_lock);
409 list_del_init(&rps->link);
410 spin_unlock(&rq->i915->rps.client_lock);
417 i915_gem_object_wait_reservation(struct reservation_object *resv,
420 struct intel_rps_client *rps)
422 unsigned int seq = __read_seqcount_begin(&resv->seq);
423 struct dma_fence *excl;
424 bool prune_fences = false;
426 if (flags & I915_WAIT_ALL) {
427 struct dma_fence **shared;
428 unsigned int count, i;
431 ret = reservation_object_get_fences_rcu(resv,
432 &excl, &count, &shared);
436 for (i = 0; i < count; i++) {
437 timeout = i915_gem_object_wait_fence(shared[i],
443 dma_fence_put(shared[i]);
446 for (; i < count; i++)
447 dma_fence_put(shared[i]);
450 prune_fences = count && timeout >= 0;
452 excl = reservation_object_get_excl_rcu(resv);
455 if (excl && timeout >= 0) {
456 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
457 prune_fences = timeout >= 0;
462 /* Oportunistically prune the fences iff we know they have *all* been
463 * signaled and that the reservation object has not been changed (i.e.
464 * no new fences have been added).
466 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
467 if (reservation_object_trylock(resv)) {
468 if (!__read_seqcount_retry(&resv->seq, seq))
469 reservation_object_add_excl_fence(resv, NULL);
470 reservation_object_unlock(resv);
477 static void __fence_set_priority(struct dma_fence *fence, int prio)
479 struct drm_i915_gem_request *rq;
480 struct intel_engine_cs *engine;
482 if (!dma_fence_is_i915(fence))
485 rq = to_request(fence);
487 if (!engine->schedule)
490 engine->schedule(rq, prio);
493 static void fence_set_priority(struct dma_fence *fence, int prio)
495 /* Recurse once into a fence-array */
496 if (dma_fence_is_array(fence)) {
497 struct dma_fence_array *array = to_dma_fence_array(fence);
500 for (i = 0; i < array->num_fences; i++)
501 __fence_set_priority(array->fences[i], prio);
503 __fence_set_priority(fence, prio);
508 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
512 struct dma_fence *excl;
514 if (flags & I915_WAIT_ALL) {
515 struct dma_fence **shared;
516 unsigned int count, i;
519 ret = reservation_object_get_fences_rcu(obj->resv,
520 &excl, &count, &shared);
524 for (i = 0; i < count; i++) {
525 fence_set_priority(shared[i], prio);
526 dma_fence_put(shared[i]);
531 excl = reservation_object_get_excl_rcu(obj->resv);
535 fence_set_priority(excl, prio);
542 * Waits for rendering to the object to be completed
543 * @obj: i915 gem object
544 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
545 * @timeout: how long to wait
546 * @rps: client (user process) to charge for any waitboosting
549 i915_gem_object_wait(struct drm_i915_gem_object *obj,
552 struct intel_rps_client *rps)
555 #if IS_ENABLED(CONFIG_LOCKDEP)
556 GEM_BUG_ON(debug_locks &&
557 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
558 !!(flags & I915_WAIT_LOCKED));
560 GEM_BUG_ON(timeout < 0);
562 timeout = i915_gem_object_wait_reservation(obj->resv,
565 return timeout < 0 ? timeout : 0;
568 static struct intel_rps_client *to_rps_client(struct drm_file *file)
570 struct drm_i915_file_private *fpriv = file->driver_priv;
576 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
581 if (align > obj->base.size)
584 if (obj->ops == &i915_gem_phys_ops)
587 if (obj->mm.madv != I915_MADV_WILLNEED)
590 if (obj->base.filp == NULL)
593 ret = i915_gem_object_unbind(obj);
597 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
601 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
602 obj->ops = &i915_gem_phys_ops;
604 ret = i915_gem_object_pin_pages(obj);
611 obj->ops = &i915_gem_object_ops;
616 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
617 struct drm_i915_gem_pwrite *args,
618 struct drm_file *file)
620 void *vaddr = obj->phys_handle->vaddr + args->offset;
621 char __user *user_data = u64_to_user_ptr(args->data_ptr);
623 /* We manually control the domain here and pretend that it
624 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
626 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
627 if (copy_from_user(vaddr, user_data, args->size))
630 drm_clflush_virt_range(vaddr, args->size);
631 i915_gem_chipset_flush(to_i915(obj->base.dev));
633 intel_fb_obj_flush(obj, ORIGIN_CPU);
637 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
639 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
642 void i915_gem_object_free(struct drm_i915_gem_object *obj)
644 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
645 kmem_cache_free(dev_priv->objects, obj);
649 i915_gem_create(struct drm_file *file,
650 struct drm_i915_private *dev_priv,
654 struct drm_i915_gem_object *obj;
658 size = roundup(size, PAGE_SIZE);
662 /* Allocate the new object */
663 obj = i915_gem_object_create(dev_priv, size);
667 ret = drm_gem_handle_create(file, &obj->base, &handle);
668 /* drop reference from allocate - handle holds it now */
669 i915_gem_object_put(obj);
678 i915_gem_dumb_create(struct drm_file *file,
679 struct drm_device *dev,
680 struct drm_mode_create_dumb *args)
682 /* have to work out size/pitch and return them */
683 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
684 args->size = args->pitch * args->height;
685 return i915_gem_create(file, to_i915(dev),
686 args->size, &args->handle);
690 * Creates a new mm object and returns a handle to it.
691 * @dev: drm device pointer
692 * @data: ioctl data blob
693 * @file: drm file pointer
696 i915_gem_create_ioctl(struct drm_device *dev, void *data,
697 struct drm_file *file)
699 struct drm_i915_private *dev_priv = to_i915(dev);
700 struct drm_i915_gem_create *args = data;
702 i915_gem_flush_free_objects(dev_priv);
704 return i915_gem_create(file, dev_priv,
705 args->size, &args->handle);
709 __copy_to_user_swizzled(char __user *cpu_vaddr,
710 const char *gpu_vaddr, int gpu_offset,
713 int ret, cpu_offset = 0;
716 int cacheline_end = ALIGN(gpu_offset + 1, 64);
717 int this_length = min(cacheline_end - gpu_offset, length);
718 int swizzled_gpu_offset = gpu_offset ^ 64;
720 ret = __copy_to_user(cpu_vaddr + cpu_offset,
721 gpu_vaddr + swizzled_gpu_offset,
726 cpu_offset += this_length;
727 gpu_offset += this_length;
728 length -= this_length;
735 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
736 const char __user *cpu_vaddr,
739 int ret, cpu_offset = 0;
742 int cacheline_end = ALIGN(gpu_offset + 1, 64);
743 int this_length = min(cacheline_end - gpu_offset, length);
744 int swizzled_gpu_offset = gpu_offset ^ 64;
746 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
747 cpu_vaddr + cpu_offset,
752 cpu_offset += this_length;
753 gpu_offset += this_length;
754 length -= this_length;
761 * Pins the specified object's pages and synchronizes the object with
762 * GPU accesses. Sets needs_clflush to non-zero if the caller should
763 * flush the object from the CPU cache.
765 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
766 unsigned int *needs_clflush)
770 lockdep_assert_held(&obj->base.dev->struct_mutex);
773 if (!i915_gem_object_has_struct_page(obj))
776 ret = i915_gem_object_wait(obj,
777 I915_WAIT_INTERRUPTIBLE |
779 MAX_SCHEDULE_TIMEOUT,
784 ret = i915_gem_object_pin_pages(obj);
788 if (i915_gem_object_is_coherent(obj) ||
789 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
790 ret = i915_gem_object_set_to_cpu_domain(obj, false);
797 i915_gem_object_flush_gtt_write_domain(obj);
799 /* If we're not in the cpu read domain, set ourself into the gtt
800 * read domain and manually flush cachelines (if required). This
801 * optimizes for the case when the gpu will dirty the data
802 * anyway again before the next pread happens.
804 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
805 *needs_clflush = CLFLUSH_BEFORE;
808 /* return with the pages pinned */
812 i915_gem_object_unpin_pages(obj);
816 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
817 unsigned int *needs_clflush)
821 lockdep_assert_held(&obj->base.dev->struct_mutex);
824 if (!i915_gem_object_has_struct_page(obj))
827 ret = i915_gem_object_wait(obj,
828 I915_WAIT_INTERRUPTIBLE |
831 MAX_SCHEDULE_TIMEOUT,
836 ret = i915_gem_object_pin_pages(obj);
840 if (i915_gem_object_is_coherent(obj) ||
841 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
842 ret = i915_gem_object_set_to_cpu_domain(obj, true);
849 i915_gem_object_flush_gtt_write_domain(obj);
851 /* If we're not in the cpu write domain, set ourself into the
852 * gtt write domain and manually flush cachelines (as required).
853 * This optimizes for the case when the gpu will use the data
854 * right away and we therefore have to clflush anyway.
856 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
857 *needs_clflush |= CLFLUSH_AFTER;
859 /* Same trick applies to invalidate partially written cachelines read
862 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
863 *needs_clflush |= CLFLUSH_BEFORE;
866 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
867 obj->mm.dirty = true;
868 /* return with the pages pinned */
872 i915_gem_object_unpin_pages(obj);
877 shmem_clflush_swizzled_range(char *addr, unsigned long length,
880 if (unlikely(swizzled)) {
881 unsigned long start = (unsigned long) addr;
882 unsigned long end = (unsigned long) addr + length;
884 /* For swizzling simply ensure that we always flush both
885 * channels. Lame, but simple and it works. Swizzled
886 * pwrite/pread is far from a hotpath - current userspace
887 * doesn't use it at all. */
888 start = round_down(start, 128);
889 end = round_up(end, 128);
891 drm_clflush_virt_range((void *)start, end - start);
893 drm_clflush_virt_range(addr, length);
898 /* Only difference to the fast-path function is that this can handle bit17
899 * and uses non-atomic copy and kmap functions. */
901 shmem_pread_slow(struct page *page, int offset, int length,
902 char __user *user_data,
903 bool page_do_bit17_swizzling, bool needs_clflush)
910 shmem_clflush_swizzled_range(vaddr + offset, length,
911 page_do_bit17_swizzling);
913 if (page_do_bit17_swizzling)
914 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
916 ret = __copy_to_user(user_data, vaddr + offset, length);
919 return ret ? - EFAULT : 0;
923 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
924 bool page_do_bit17_swizzling, bool needs_clflush)
929 if (!page_do_bit17_swizzling) {
930 char *vaddr = kmap_atomic(page);
933 drm_clflush_virt_range(vaddr + offset, length);
934 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
935 kunmap_atomic(vaddr);
940 return shmem_pread_slow(page, offset, length, user_data,
941 page_do_bit17_swizzling, needs_clflush);
945 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
946 struct drm_i915_gem_pread *args)
948 char __user *user_data;
950 unsigned int obj_do_bit17_swizzling;
951 unsigned int needs_clflush;
952 unsigned int idx, offset;
955 obj_do_bit17_swizzling = 0;
956 if (i915_gem_object_needs_bit17_swizzle(obj))
957 obj_do_bit17_swizzling = BIT(17);
959 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
963 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
964 mutex_unlock(&obj->base.dev->struct_mutex);
969 user_data = u64_to_user_ptr(args->data_ptr);
970 offset = offset_in_page(args->offset);
971 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
972 struct page *page = i915_gem_object_get_page(obj, idx);
976 if (offset + length > PAGE_SIZE)
977 length = PAGE_SIZE - offset;
979 ret = shmem_pread(page, offset, length, user_data,
980 page_to_phys(page) & obj_do_bit17_swizzling,
990 i915_gem_obj_finish_shmem_access(obj);
995 gtt_user_read(struct io_mapping *mapping,
996 loff_t base, int offset,
997 char __user *user_data, int length)
1000 unsigned long unwritten;
1002 /* We can use the cpu mem copy function because this is X86. */
1003 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1004 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1005 io_mapping_unmap_atomic(vaddr);
1007 vaddr = (void __force *)
1008 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1009 unwritten = copy_to_user(user_data, vaddr + offset, length);
1010 io_mapping_unmap(vaddr);
1016 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1017 const struct drm_i915_gem_pread *args)
1019 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1020 struct i915_ggtt *ggtt = &i915->ggtt;
1021 struct drm_mm_node node;
1022 struct i915_vma *vma;
1023 void __user *user_data;
1027 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1031 intel_runtime_pm_get(i915);
1032 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1033 PIN_MAPPABLE | PIN_NONBLOCK);
1035 node.start = i915_ggtt_offset(vma);
1036 node.allocated = false;
1037 ret = i915_vma_put_fence(vma);
1039 i915_vma_unpin(vma);
1044 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1047 GEM_BUG_ON(!node.allocated);
1050 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1054 mutex_unlock(&i915->drm.struct_mutex);
1056 user_data = u64_to_user_ptr(args->data_ptr);
1057 remain = args->size;
1058 offset = args->offset;
1060 while (remain > 0) {
1061 /* Operation in this page
1063 * page_base = page offset within aperture
1064 * page_offset = offset within page
1065 * page_length = bytes to copy for this page
1067 u32 page_base = node.start;
1068 unsigned page_offset = offset_in_page(offset);
1069 unsigned page_length = PAGE_SIZE - page_offset;
1070 page_length = remain < page_length ? remain : page_length;
1071 if (node.allocated) {
1073 ggtt->base.insert_page(&ggtt->base,
1074 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1075 node.start, I915_CACHE_NONE, 0);
1078 page_base += offset & PAGE_MASK;
1081 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1082 user_data, page_length)) {
1087 remain -= page_length;
1088 user_data += page_length;
1089 offset += page_length;
1092 mutex_lock(&i915->drm.struct_mutex);
1094 if (node.allocated) {
1096 ggtt->base.clear_range(&ggtt->base,
1097 node.start, node.size);
1098 remove_mappable_node(&node);
1100 i915_vma_unpin(vma);
1103 intel_runtime_pm_put(i915);
1104 mutex_unlock(&i915->drm.struct_mutex);
1110 * Reads data from the object referenced by handle.
1111 * @dev: drm device pointer
1112 * @data: ioctl data blob
1113 * @file: drm file pointer
1115 * On error, the contents of *data are undefined.
1118 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file)
1121 struct drm_i915_gem_pread *args = data;
1122 struct drm_i915_gem_object *obj;
1125 if (args->size == 0)
1128 if (!access_ok(VERIFY_WRITE,
1129 u64_to_user_ptr(args->data_ptr),
1133 obj = i915_gem_object_lookup(file, args->handle);
1137 /* Bounds check source. */
1138 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1143 trace_i915_gem_object_pread(obj, args->offset, args->size);
1145 ret = i915_gem_object_wait(obj,
1146 I915_WAIT_INTERRUPTIBLE,
1147 MAX_SCHEDULE_TIMEOUT,
1148 to_rps_client(file));
1152 ret = i915_gem_object_pin_pages(obj);
1156 ret = i915_gem_shmem_pread(obj, args);
1157 if (ret == -EFAULT || ret == -ENODEV)
1158 ret = i915_gem_gtt_pread(obj, args);
1160 i915_gem_object_unpin_pages(obj);
1162 i915_gem_object_put(obj);
1166 /* This is the fast write path which cannot handle
1167 * page faults in the source data
1171 ggtt_write(struct io_mapping *mapping,
1172 loff_t base, int offset,
1173 char __user *user_data, int length)
1176 unsigned long unwritten;
1178 /* We can use the cpu mem copy function because this is X86. */
1179 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1180 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1182 io_mapping_unmap_atomic(vaddr);
1184 vaddr = (void __force *)
1185 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1186 unwritten = copy_from_user(vaddr + offset, user_data, length);
1187 io_mapping_unmap(vaddr);
1194 * This is the fast pwrite path, where we copy the data directly from the
1195 * user into the GTT, uncached.
1196 * @obj: i915 GEM object
1197 * @args: pwrite arguments structure
1200 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1201 const struct drm_i915_gem_pwrite *args)
1203 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1204 struct i915_ggtt *ggtt = &i915->ggtt;
1205 struct drm_mm_node node;
1206 struct i915_vma *vma;
1208 void __user *user_data;
1211 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1215 intel_runtime_pm_get(i915);
1216 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1217 PIN_MAPPABLE | PIN_NONBLOCK);
1219 node.start = i915_ggtt_offset(vma);
1220 node.allocated = false;
1221 ret = i915_vma_put_fence(vma);
1223 i915_vma_unpin(vma);
1228 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1231 GEM_BUG_ON(!node.allocated);
1234 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1238 mutex_unlock(&i915->drm.struct_mutex);
1240 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1242 user_data = u64_to_user_ptr(args->data_ptr);
1243 offset = args->offset;
1244 remain = args->size;
1246 /* Operation in this page
1248 * page_base = page offset within aperture
1249 * page_offset = offset within page
1250 * page_length = bytes to copy for this page
1252 u32 page_base = node.start;
1253 unsigned int page_offset = offset_in_page(offset);
1254 unsigned int page_length = PAGE_SIZE - page_offset;
1255 page_length = remain < page_length ? remain : page_length;
1256 if (node.allocated) {
1257 wmb(); /* flush the write before we modify the GGTT */
1258 ggtt->base.insert_page(&ggtt->base,
1259 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1260 node.start, I915_CACHE_NONE, 0);
1261 wmb(); /* flush modifications to the GGTT (insert_page) */
1263 page_base += offset & PAGE_MASK;
1265 /* If we get a fault while copying data, then (presumably) our
1266 * source page isn't available. Return the error and we'll
1267 * retry in the slow path.
1268 * If the object is non-shmem backed, we retry again with the
1269 * path that handles page fault.
1271 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1272 user_data, page_length)) {
1277 remain -= page_length;
1278 user_data += page_length;
1279 offset += page_length;
1281 intel_fb_obj_flush(obj, ORIGIN_CPU);
1283 mutex_lock(&i915->drm.struct_mutex);
1285 if (node.allocated) {
1287 ggtt->base.clear_range(&ggtt->base,
1288 node.start, node.size);
1289 remove_mappable_node(&node);
1291 i915_vma_unpin(vma);
1294 intel_runtime_pm_put(i915);
1295 mutex_unlock(&i915->drm.struct_mutex);
1300 shmem_pwrite_slow(struct page *page, int offset, int length,
1301 char __user *user_data,
1302 bool page_do_bit17_swizzling,
1303 bool needs_clflush_before,
1304 bool needs_clflush_after)
1310 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1311 shmem_clflush_swizzled_range(vaddr + offset, length,
1312 page_do_bit17_swizzling);
1313 if (page_do_bit17_swizzling)
1314 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1317 ret = __copy_from_user(vaddr + offset, user_data, length);
1318 if (needs_clflush_after)
1319 shmem_clflush_swizzled_range(vaddr + offset, length,
1320 page_do_bit17_swizzling);
1323 return ret ? -EFAULT : 0;
1326 /* Per-page copy function for the shmem pwrite fastpath.
1327 * Flushes invalid cachelines before writing to the target if
1328 * needs_clflush_before is set and flushes out any written cachelines after
1329 * writing if needs_clflush is set.
1332 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1333 bool page_do_bit17_swizzling,
1334 bool needs_clflush_before,
1335 bool needs_clflush_after)
1340 if (!page_do_bit17_swizzling) {
1341 char *vaddr = kmap_atomic(page);
1343 if (needs_clflush_before)
1344 drm_clflush_virt_range(vaddr + offset, len);
1345 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1346 if (needs_clflush_after)
1347 drm_clflush_virt_range(vaddr + offset, len);
1349 kunmap_atomic(vaddr);
1354 return shmem_pwrite_slow(page, offset, len, user_data,
1355 page_do_bit17_swizzling,
1356 needs_clflush_before,
1357 needs_clflush_after);
1361 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1362 const struct drm_i915_gem_pwrite *args)
1364 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1365 void __user *user_data;
1367 unsigned int obj_do_bit17_swizzling;
1368 unsigned int partial_cacheline_write;
1369 unsigned int needs_clflush;
1370 unsigned int offset, idx;
1373 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1377 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1378 mutex_unlock(&i915->drm.struct_mutex);
1382 obj_do_bit17_swizzling = 0;
1383 if (i915_gem_object_needs_bit17_swizzle(obj))
1384 obj_do_bit17_swizzling = BIT(17);
1386 /* If we don't overwrite a cacheline completely we need to be
1387 * careful to have up-to-date data by first clflushing. Don't
1388 * overcomplicate things and flush the entire patch.
1390 partial_cacheline_write = 0;
1391 if (needs_clflush & CLFLUSH_BEFORE)
1392 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1394 user_data = u64_to_user_ptr(args->data_ptr);
1395 remain = args->size;
1396 offset = offset_in_page(args->offset);
1397 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1398 struct page *page = i915_gem_object_get_page(obj, idx);
1402 if (offset + length > PAGE_SIZE)
1403 length = PAGE_SIZE - offset;
1405 ret = shmem_pwrite(page, offset, length, user_data,
1406 page_to_phys(page) & obj_do_bit17_swizzling,
1407 (offset | length) & partial_cacheline_write,
1408 needs_clflush & CLFLUSH_AFTER);
1413 user_data += length;
1417 intel_fb_obj_flush(obj, ORIGIN_CPU);
1418 i915_gem_obj_finish_shmem_access(obj);
1423 * Writes data to the object referenced by handle.
1425 * @data: ioctl data blob
1428 * On error, the contents of the buffer that were to be modified are undefined.
1431 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1432 struct drm_file *file)
1434 struct drm_i915_gem_pwrite *args = data;
1435 struct drm_i915_gem_object *obj;
1438 if (args->size == 0)
1441 if (!access_ok(VERIFY_READ,
1442 u64_to_user_ptr(args->data_ptr),
1446 obj = i915_gem_object_lookup(file, args->handle);
1450 /* Bounds check destination. */
1451 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1456 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1459 if (obj->ops->pwrite)
1460 ret = obj->ops->pwrite(obj, args);
1464 ret = i915_gem_object_wait(obj,
1465 I915_WAIT_INTERRUPTIBLE |
1467 MAX_SCHEDULE_TIMEOUT,
1468 to_rps_client(file));
1472 ret = i915_gem_object_pin_pages(obj);
1477 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1478 * it would end up going through the fenced access, and we'll get
1479 * different detiling behavior between reading and writing.
1480 * pread/pwrite currently are reading and writing from the CPU
1481 * perspective, requiring manual detiling by the client.
1483 if (!i915_gem_object_has_struct_page(obj) ||
1484 cpu_write_needs_clflush(obj))
1485 /* Note that the gtt paths might fail with non-page-backed user
1486 * pointers (e.g. gtt mappings when moving data between
1487 * textures). Fallback to the shmem path in that case.
1489 ret = i915_gem_gtt_pwrite_fast(obj, args);
1491 if (ret == -EFAULT || ret == -ENOSPC) {
1492 if (obj->phys_handle)
1493 ret = i915_gem_phys_pwrite(obj, args, file);
1495 ret = i915_gem_shmem_pwrite(obj, args);
1498 i915_gem_object_unpin_pages(obj);
1500 i915_gem_object_put(obj);
1504 static inline enum fb_op_origin
1505 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1507 return (domain == I915_GEM_DOMAIN_GTT ?
1508 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1511 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1513 struct drm_i915_private *i915;
1514 struct list_head *list;
1515 struct i915_vma *vma;
1517 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1518 if (!i915_vma_is_ggtt(vma))
1521 if (i915_vma_is_active(vma))
1524 if (!drm_mm_node_allocated(&vma->node))
1527 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1530 i915 = to_i915(obj->base.dev);
1531 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1532 list_move_tail(&obj->global_link, list);
1536 * Called when user space prepares to use an object with the CPU, either
1537 * through the mmap ioctl's mapping or a GTT mapping.
1539 * @data: ioctl data blob
1543 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1544 struct drm_file *file)
1546 struct drm_i915_gem_set_domain *args = data;
1547 struct drm_i915_gem_object *obj;
1548 uint32_t read_domains = args->read_domains;
1549 uint32_t write_domain = args->write_domain;
1552 /* Only handle setting domains to types used by the CPU. */
1553 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1556 /* Having something in the write domain implies it's in the read
1557 * domain, and only that read domain. Enforce that in the request.
1559 if (write_domain != 0 && read_domains != write_domain)
1562 obj = i915_gem_object_lookup(file, args->handle);
1566 /* Try to flush the object off the GPU without holding the lock.
1567 * We will repeat the flush holding the lock in the normal manner
1568 * to catch cases where we are gazumped.
1570 err = i915_gem_object_wait(obj,
1571 I915_WAIT_INTERRUPTIBLE |
1572 (write_domain ? I915_WAIT_ALL : 0),
1573 MAX_SCHEDULE_TIMEOUT,
1574 to_rps_client(file));
1578 /* Flush and acquire obj->pages so that we are coherent through
1579 * direct access in memory with previous cached writes through
1580 * shmemfs and that our cache domain tracking remains valid.
1581 * For example, if the obj->filp was moved to swap without us
1582 * being notified and releasing the pages, we would mistakenly
1583 * continue to assume that the obj remained out of the CPU cached
1586 err = i915_gem_object_pin_pages(obj);
1590 err = i915_mutex_lock_interruptible(dev);
1594 if (read_domains & I915_GEM_DOMAIN_GTT)
1595 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1597 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1599 /* And bump the LRU for this access */
1600 i915_gem_object_bump_inactive_ggtt(obj);
1602 mutex_unlock(&dev->struct_mutex);
1604 if (write_domain != 0)
1605 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1608 i915_gem_object_unpin_pages(obj);
1610 i915_gem_object_put(obj);
1615 * Called when user space has done writes to this buffer
1617 * @data: ioctl data blob
1621 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1622 struct drm_file *file)
1624 struct drm_i915_gem_sw_finish *args = data;
1625 struct drm_i915_gem_object *obj;
1627 obj = i915_gem_object_lookup(file, args->handle);
1631 /* Pinned buffers may be scanout, so flush the cache */
1632 i915_gem_object_flush_if_display(obj);
1633 i915_gem_object_put(obj);
1639 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1642 * @data: ioctl data blob
1645 * While the mapping holds a reference on the contents of the object, it doesn't
1646 * imply a ref on the object itself.
1650 * DRM driver writers who look a this function as an example for how to do GEM
1651 * mmap support, please don't implement mmap support like here. The modern way
1652 * to implement DRM mmap support is with an mmap offset ioctl (like
1653 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1654 * That way debug tooling like valgrind will understand what's going on, hiding
1655 * the mmap call in a driver private ioctl will break that. The i915 driver only
1656 * does cpu mmaps this way because we didn't know better.
1659 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1660 struct drm_file *file)
1662 struct drm_i915_gem_mmap *args = data;
1663 struct drm_i915_gem_object *obj;
1666 if (args->flags & ~(I915_MMAP_WC))
1669 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1672 obj = i915_gem_object_lookup(file, args->handle);
1676 /* prime objects have no backing filp to GEM mmap
1679 if (!obj->base.filp) {
1680 i915_gem_object_put(obj);
1684 addr = vm_mmap(obj->base.filp, 0, args->size,
1685 PROT_READ | PROT_WRITE, MAP_SHARED,
1687 if (args->flags & I915_MMAP_WC) {
1688 struct mm_struct *mm = current->mm;
1689 struct vm_area_struct *vma;
1691 if (down_write_killable(&mm->mmap_sem)) {
1692 i915_gem_object_put(obj);
1695 vma = find_vma(mm, addr);
1698 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1701 up_write(&mm->mmap_sem);
1703 /* This may race, but that's ok, it only gets set */
1704 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1706 i915_gem_object_put(obj);
1707 if (IS_ERR((void *)addr))
1710 args->addr_ptr = (uint64_t) addr;
1715 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1717 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1721 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1723 * A history of the GTT mmap interface:
1725 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1726 * aligned and suitable for fencing, and still fit into the available
1727 * mappable space left by the pinned display objects. A classic problem
1728 * we called the page-fault-of-doom where we would ping-pong between
1729 * two objects that could not fit inside the GTT and so the memcpy
1730 * would page one object in at the expense of the other between every
1733 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1734 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1735 * object is too large for the available space (or simply too large
1736 * for the mappable aperture!), a view is created instead and faulted
1737 * into userspace. (This view is aligned and sized appropriately for
1742 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1743 * hangs on some architectures, corruption on others. An attempt to service
1744 * a GTT page fault from a snoopable object will generate a SIGBUS.
1746 * * the object must be able to fit into RAM (physical memory, though no
1747 * limited to the mappable aperture).
1752 * * a new GTT page fault will synchronize rendering from the GPU and flush
1753 * all data to system memory. Subsequent access will not be synchronized.
1755 * * all mappings are revoked on runtime device suspend.
1757 * * there are only 8, 16 or 32 fence registers to share between all users
1758 * (older machines require fence register for display and blitter access
1759 * as well). Contention of the fence registers will cause the previous users
1760 * to be unmapped and any new access will generate new page faults.
1762 * * running out of memory while servicing a fault may generate a SIGBUS,
1763 * rather than the expected SIGSEGV.
1765 int i915_gem_mmap_gtt_version(void)
1770 static inline struct i915_ggtt_view
1771 compute_partial_view(struct drm_i915_gem_object *obj,
1772 pgoff_t page_offset,
1775 struct i915_ggtt_view view;
1777 if (i915_gem_object_is_tiled(obj))
1778 chunk = roundup(chunk, tile_row_pages(obj));
1780 view.type = I915_GGTT_VIEW_PARTIAL;
1781 view.partial.offset = rounddown(page_offset, chunk);
1783 min_t(unsigned int, chunk,
1784 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1786 /* If the partial covers the entire object, just create a normal VMA. */
1787 if (chunk >= obj->base.size >> PAGE_SHIFT)
1788 view.type = I915_GGTT_VIEW_NORMAL;
1794 * i915_gem_fault - fault a page into the GTT
1797 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1798 * from userspace. The fault handler takes care of binding the object to
1799 * the GTT (if needed), allocating and programming a fence register (again,
1800 * only if needed based on whether the old reg is still valid or the object
1801 * is tiled) and inserting a new PTE into the faulting process.
1803 * Note that the faulting process may involve evicting existing objects
1804 * from the GTT and/or fence registers to make room. So performance may
1805 * suffer if the GTT working set is large or there are few fence registers
1808 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1809 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1811 int i915_gem_fault(struct vm_fault *vmf)
1813 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1814 struct vm_area_struct *area = vmf->vma;
1815 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1816 struct drm_device *dev = obj->base.dev;
1817 struct drm_i915_private *dev_priv = to_i915(dev);
1818 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1819 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1820 struct i915_vma *vma;
1821 pgoff_t page_offset;
1825 /* We don't use vmf->pgoff since that has the fake offset */
1826 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1828 trace_i915_gem_object_fault(obj, page_offset, true, write);
1830 /* Try to flush the object off the GPU first without holding the lock.
1831 * Upon acquiring the lock, we will perform our sanity checks and then
1832 * repeat the flush holding the lock in the normal manner to catch cases
1833 * where we are gazumped.
1835 ret = i915_gem_object_wait(obj,
1836 I915_WAIT_INTERRUPTIBLE,
1837 MAX_SCHEDULE_TIMEOUT,
1842 ret = i915_gem_object_pin_pages(obj);
1846 intel_runtime_pm_get(dev_priv);
1848 ret = i915_mutex_lock_interruptible(dev);
1852 /* Access to snoopable pages through the GTT is incoherent. */
1853 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1858 /* If the object is smaller than a couple of partial vma, it is
1859 * not worth only creating a single partial vma - we may as well
1860 * clear enough space for the full object.
1862 flags = PIN_MAPPABLE;
1863 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1864 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1866 /* Now pin it into the GTT as needed */
1867 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1869 /* Use a partial view if it is bigger than available space */
1870 struct i915_ggtt_view view =
1871 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1873 /* Userspace is now writing through an untracked VMA, abandon
1874 * all hope that the hardware is able to track future writes.
1876 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1878 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1885 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1889 ret = i915_vma_get_fence(vma);
1893 /* Mark as being mmapped into userspace for later revocation */
1894 assert_rpm_wakelock_held(dev_priv);
1895 if (list_empty(&obj->userfault_link))
1896 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1898 /* Finally, remap it using the new GTT offset */
1899 ret = remap_io_mapping(area,
1900 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1901 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1902 min_t(u64, vma->size, area->vm_end - area->vm_start),
1906 __i915_vma_unpin(vma);
1908 mutex_unlock(&dev->struct_mutex);
1910 intel_runtime_pm_put(dev_priv);
1911 i915_gem_object_unpin_pages(obj);
1916 * We eat errors when the gpu is terminally wedged to avoid
1917 * userspace unduly crashing (gl has no provisions for mmaps to
1918 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1919 * and so needs to be reported.
1921 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1922 ret = VM_FAULT_SIGBUS;
1927 * EAGAIN means the gpu is hung and we'll wait for the error
1928 * handler to reset everything when re-faulting in
1929 * i915_mutex_lock_interruptible.
1936 * EBUSY is ok: this just means that another thread
1937 * already did the job.
1939 ret = VM_FAULT_NOPAGE;
1946 ret = VM_FAULT_SIGBUS;
1949 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1950 ret = VM_FAULT_SIGBUS;
1957 * i915_gem_release_mmap - remove physical page mappings
1958 * @obj: obj in question
1960 * Preserve the reservation of the mmapping with the DRM core code, but
1961 * relinquish ownership of the pages back to the system.
1963 * It is vital that we remove the page mapping if we have mapped a tiled
1964 * object through the GTT and then lose the fence register due to
1965 * resource pressure. Similarly if the object has been moved out of the
1966 * aperture, than pages mapped into userspace must be revoked. Removing the
1967 * mapping will then trigger a page fault on the next user access, allowing
1968 * fixup by i915_gem_fault().
1971 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1973 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1975 /* Serialisation between user GTT access and our code depends upon
1976 * revoking the CPU's PTE whilst the mutex is held. The next user
1977 * pagefault then has to wait until we release the mutex.
1979 * Note that RPM complicates somewhat by adding an additional
1980 * requirement that operations to the GGTT be made holding the RPM
1983 lockdep_assert_held(&i915->drm.struct_mutex);
1984 intel_runtime_pm_get(i915);
1986 if (list_empty(&obj->userfault_link))
1989 list_del_init(&obj->userfault_link);
1990 drm_vma_node_unmap(&obj->base.vma_node,
1991 obj->base.dev->anon_inode->i_mapping);
1993 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1994 * memory transactions from userspace before we return. The TLB
1995 * flushing implied above by changing the PTE above *should* be
1996 * sufficient, an extra barrier here just provides us with a bit
1997 * of paranoid documentation about our requirement to serialise
1998 * memory writes before touching registers / GSM.
2003 intel_runtime_pm_put(i915);
2006 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2008 struct drm_i915_gem_object *obj, *on;
2012 * Only called during RPM suspend. All users of the userfault_list
2013 * must be holding an RPM wakeref to ensure that this can not
2014 * run concurrently with themselves (and use the struct_mutex for
2015 * protection between themselves).
2018 list_for_each_entry_safe(obj, on,
2019 &dev_priv->mm.userfault_list, userfault_link) {
2020 list_del_init(&obj->userfault_link);
2021 drm_vma_node_unmap(&obj->base.vma_node,
2022 obj->base.dev->anon_inode->i_mapping);
2025 /* The fence will be lost when the device powers down. If any were
2026 * in use by hardware (i.e. they are pinned), we should not be powering
2027 * down! All other fences will be reacquired by the user upon waking.
2029 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2030 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2032 /* Ideally we want to assert that the fence register is not
2033 * live at this point (i.e. that no piece of code will be
2034 * trying to write through fence + GTT, as that both violates
2035 * our tracking of activity and associated locking/barriers,
2036 * but also is illegal given that the hw is powered down).
2038 * Previously we used reg->pin_count as a "liveness" indicator.
2039 * That is not sufficient, and we need a more fine-grained
2040 * tool if we want to have a sanity check here.
2046 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2051 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2053 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2056 err = drm_gem_create_mmap_offset(&obj->base);
2060 /* Attempt to reap some mmap space from dead objects */
2062 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2066 i915_gem_drain_freed_objects(dev_priv);
2067 err = drm_gem_create_mmap_offset(&obj->base);
2071 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2076 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2078 drm_gem_free_mmap_offset(&obj->base);
2082 i915_gem_mmap_gtt(struct drm_file *file,
2083 struct drm_device *dev,
2087 struct drm_i915_gem_object *obj;
2090 obj = i915_gem_object_lookup(file, handle);
2094 ret = i915_gem_object_create_mmap_offset(obj);
2096 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2098 i915_gem_object_put(obj);
2103 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2105 * @data: GTT mapping ioctl data
2106 * @file: GEM object info
2108 * Simply returns the fake offset to userspace so it can mmap it.
2109 * The mmap call will end up in drm_gem_mmap(), which will set things
2110 * up so we can get faults in the handler above.
2112 * The fault handler will take care of binding the object into the GTT
2113 * (since it may have been evicted to make room for something), allocating
2114 * a fence register, and mapping the appropriate aperture address into
2118 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file)
2121 struct drm_i915_gem_mmap_gtt *args = data;
2123 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2126 /* Immediately discard the backing storage */
2128 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2130 i915_gem_object_free_mmap_offset(obj);
2132 if (obj->base.filp == NULL)
2135 /* Our goal here is to return as much of the memory as
2136 * is possible back to the system as we are called from OOM.
2137 * To do this we must instruct the shmfs to drop all of its
2138 * backing pages, *now*.
2140 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2141 obj->mm.madv = __I915_MADV_PURGED;
2142 obj->mm.pages = ERR_PTR(-EFAULT);
2145 /* Try to discard unwanted pages */
2146 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2148 struct address_space *mapping;
2150 lockdep_assert_held(&obj->mm.lock);
2151 GEM_BUG_ON(obj->mm.pages);
2153 switch (obj->mm.madv) {
2154 case I915_MADV_DONTNEED:
2155 i915_gem_object_truncate(obj);
2156 case __I915_MADV_PURGED:
2160 if (obj->base.filp == NULL)
2163 mapping = obj->base.filp->f_mapping,
2164 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2168 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2169 struct sg_table *pages)
2171 struct sgt_iter sgt_iter;
2174 __i915_gem_object_release_shmem(obj, pages, true);
2176 i915_gem_gtt_finish_pages(obj, pages);
2178 if (i915_gem_object_needs_bit17_swizzle(obj))
2179 i915_gem_object_save_bit_17_swizzle(obj, pages);
2181 for_each_sgt_page(page, sgt_iter, pages) {
2183 set_page_dirty(page);
2185 if (obj->mm.madv == I915_MADV_WILLNEED)
2186 mark_page_accessed(page);
2190 obj->mm.dirty = false;
2192 sg_free_table(pages);
2196 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2198 struct radix_tree_iter iter;
2201 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2202 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2205 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2206 enum i915_mm_subclass subclass)
2208 struct sg_table *pages;
2210 if (i915_gem_object_has_pinned_pages(obj))
2213 GEM_BUG_ON(obj->bind_count);
2214 if (!READ_ONCE(obj->mm.pages))
2217 /* May be called by shrinker from within get_pages() (on another bo) */
2218 mutex_lock_nested(&obj->mm.lock, subclass);
2219 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2222 /* ->put_pages might need to allocate memory for the bit17 swizzle
2223 * array, hence protect them from being reaped by removing them from gtt
2225 pages = fetch_and_zero(&obj->mm.pages);
2228 if (obj->mm.mapping) {
2231 ptr = ptr_mask_bits(obj->mm.mapping);
2232 if (is_vmalloc_addr(ptr))
2235 kunmap(kmap_to_page(ptr));
2237 obj->mm.mapping = NULL;
2240 __i915_gem_object_reset_page_iter(obj);
2243 obj->ops->put_pages(obj, pages);
2246 mutex_unlock(&obj->mm.lock);
2249 static bool i915_sg_trim(struct sg_table *orig_st)
2251 struct sg_table new_st;
2252 struct scatterlist *sg, *new_sg;
2255 if (orig_st->nents == orig_st->orig_nents)
2258 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2261 new_sg = new_st.sgl;
2262 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2263 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2264 /* called before being DMA mapped, no need to copy sg->dma_* */
2265 new_sg = sg_next(new_sg);
2267 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2269 sg_free_table(orig_st);
2275 static struct sg_table *
2276 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2278 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2279 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2281 struct address_space *mapping;
2282 struct sg_table *st;
2283 struct scatterlist *sg;
2284 struct sgt_iter sgt_iter;
2286 unsigned long last_pfn = 0; /* suppress gcc warning */
2287 unsigned int max_segment;
2291 /* Assert that the object is not currently in any GPU domain. As it
2292 * wasn't in the GTT, there shouldn't be any way it could have been in
2295 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2296 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2298 max_segment = swiotlb_max_segment();
2300 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2302 st = kmalloc(sizeof(*st), GFP_KERNEL);
2304 return ERR_PTR(-ENOMEM);
2307 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2309 return ERR_PTR(-ENOMEM);
2312 /* Get the list of pages out of our struct file. They'll be pinned
2313 * at this point until we release them.
2315 * Fail silently without starting the shrinker
2317 mapping = obj->base.filp->f_mapping;
2318 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2319 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2322 for (i = 0; i < page_count; i++) {
2323 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2324 if (unlikely(IS_ERR(page))) {
2325 i915_gem_shrink(dev_priv,
2328 I915_SHRINK_UNBOUND |
2329 I915_SHRINK_PURGEABLE);
2330 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2332 if (unlikely(IS_ERR(page))) {
2335 /* We've tried hard to allocate the memory by reaping
2336 * our own buffer, now let the real VM do its job and
2337 * go down in flames if truly OOM.
2339 * However, since graphics tend to be disposable,
2340 * defer the oom here by reporting the ENOMEM back
2343 reclaim = mapping_gfp_constraint(mapping, 0);
2344 reclaim |= __GFP_NORETRY; /* reclaim, but no oom */
2346 page = shmem_read_mapping_page_gfp(mapping, i, reclaim);
2348 ret = PTR_ERR(page);
2353 sg->length >= max_segment ||
2354 page_to_pfn(page) != last_pfn + 1) {
2358 sg_set_page(sg, page, PAGE_SIZE, 0);
2360 sg->length += PAGE_SIZE;
2362 last_pfn = page_to_pfn(page);
2364 /* Check that the i965g/gm workaround works. */
2365 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2367 if (sg) /* loop terminated early; short sg table */
2370 /* Trim unused sg entries to avoid wasting memory. */
2373 ret = i915_gem_gtt_prepare_pages(obj, st);
2375 /* DMA remapping failed? One possible cause is that
2376 * it could not reserve enough large entries, asking
2377 * for PAGE_SIZE chunks instead may be helpful.
2379 if (max_segment > PAGE_SIZE) {
2380 for_each_sgt_page(page, sgt_iter, st)
2384 max_segment = PAGE_SIZE;
2387 dev_warn(&dev_priv->drm.pdev->dev,
2388 "Failed to DMA remap %lu pages\n",
2394 if (i915_gem_object_needs_bit17_swizzle(obj))
2395 i915_gem_object_do_bit_17_swizzle(obj, st);
2402 for_each_sgt_page(page, sgt_iter, st)
2407 /* shmemfs first checks if there is enough memory to allocate the page
2408 * and reports ENOSPC should there be insufficient, along with the usual
2409 * ENOMEM for a genuine allocation failure.
2411 * We use ENOSPC in our driver to mean that we have run out of aperture
2412 * space and so want to translate the error from shmemfs back to our
2413 * usual understanding of ENOMEM.
2418 return ERR_PTR(ret);
2421 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2422 struct sg_table *pages)
2424 lockdep_assert_held(&obj->mm.lock);
2426 obj->mm.get_page.sg_pos = pages->sgl;
2427 obj->mm.get_page.sg_idx = 0;
2429 obj->mm.pages = pages;
2431 if (i915_gem_object_is_tiled(obj) &&
2432 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2433 GEM_BUG_ON(obj->mm.quirked);
2434 __i915_gem_object_pin_pages(obj);
2435 obj->mm.quirked = true;
2439 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2441 struct sg_table *pages;
2443 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2445 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2446 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2450 pages = obj->ops->get_pages(obj);
2451 if (unlikely(IS_ERR(pages)))
2452 return PTR_ERR(pages);
2454 __i915_gem_object_set_pages(obj, pages);
2458 /* Ensure that the associated pages are gathered from the backing storage
2459 * and pinned into our object. i915_gem_object_pin_pages() may be called
2460 * multiple times before they are released by a single call to
2461 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2462 * either as a result of memory pressure (reaping pages under the shrinker)
2463 * or as the object is itself released.
2465 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2469 err = mutex_lock_interruptible(&obj->mm.lock);
2473 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2474 err = ____i915_gem_object_get_pages(obj);
2478 smp_mb__before_atomic();
2480 atomic_inc(&obj->mm.pages_pin_count);
2483 mutex_unlock(&obj->mm.lock);
2487 /* The 'mapping' part of i915_gem_object_pin_map() below */
2488 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2489 enum i915_map_type type)
2491 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2492 struct sg_table *sgt = obj->mm.pages;
2493 struct sgt_iter sgt_iter;
2495 struct page *stack_pages[32];
2496 struct page **pages = stack_pages;
2497 unsigned long i = 0;
2501 /* A single page can always be kmapped */
2502 if (n_pages == 1 && type == I915_MAP_WB)
2503 return kmap(sg_page(sgt->sgl));
2505 if (n_pages > ARRAY_SIZE(stack_pages)) {
2506 /* Too big for stack -- allocate temporary array instead */
2507 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2512 for_each_sgt_page(page, sgt_iter, sgt)
2515 /* Check that we have the expected number of pages */
2516 GEM_BUG_ON(i != n_pages);
2520 pgprot = PAGE_KERNEL;
2523 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2526 addr = vmap(pages, n_pages, 0, pgprot);
2528 if (pages != stack_pages)
2529 drm_free_large(pages);
2534 /* get, pin, and map the pages of the object into kernel space */
2535 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2536 enum i915_map_type type)
2538 enum i915_map_type has_type;
2543 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2545 ret = mutex_lock_interruptible(&obj->mm.lock);
2547 return ERR_PTR(ret);
2550 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2551 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2552 ret = ____i915_gem_object_get_pages(obj);
2556 smp_mb__before_atomic();
2558 atomic_inc(&obj->mm.pages_pin_count);
2561 GEM_BUG_ON(!obj->mm.pages);
2563 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2564 if (ptr && has_type != type) {
2570 if (is_vmalloc_addr(ptr))
2573 kunmap(kmap_to_page(ptr));
2575 ptr = obj->mm.mapping = NULL;
2579 ptr = i915_gem_object_map(obj, type);
2585 obj->mm.mapping = ptr_pack_bits(ptr, type);
2589 mutex_unlock(&obj->mm.lock);
2593 atomic_dec(&obj->mm.pages_pin_count);
2600 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2601 const struct drm_i915_gem_pwrite *arg)
2603 struct address_space *mapping = obj->base.filp->f_mapping;
2604 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2608 /* Before we instantiate/pin the backing store for our use, we
2609 * can prepopulate the shmemfs filp efficiently using a write into
2610 * the pagecache. We avoid the penalty of instantiating all the
2611 * pages, important if the user is just writing to a few and never
2612 * uses the object on the GPU, and using a direct write into shmemfs
2613 * allows it to avoid the cost of retrieving a page (either swapin
2614 * or clearing-before-use) before it is overwritten.
2616 if (READ_ONCE(obj->mm.pages))
2619 /* Before the pages are instantiated the object is treated as being
2620 * in the CPU domain. The pages will be clflushed as required before
2621 * use, and we can freely write into the pages directly. If userspace
2622 * races pwrite with any other operation; corruption will ensue -
2623 * that is userspace's prerogative!
2627 offset = arg->offset;
2628 pg = offset_in_page(offset);
2631 unsigned int len, unwritten;
2636 len = PAGE_SIZE - pg;
2640 err = pagecache_write_begin(obj->base.filp, mapping,
2647 unwritten = copy_from_user(vaddr + pg, user_data, len);
2650 err = pagecache_write_end(obj->base.filp, mapping,
2651 offset, len, len - unwritten,
2668 static bool ban_context(const struct i915_gem_context *ctx)
2670 return (i915_gem_context_is_bannable(ctx) &&
2671 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2674 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2676 ctx->guilty_count++;
2677 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2678 if (ban_context(ctx))
2679 i915_gem_context_set_banned(ctx);
2681 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2682 ctx->name, ctx->ban_score,
2683 yesno(i915_gem_context_is_banned(ctx)));
2685 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2688 ctx->file_priv->context_bans++;
2689 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2690 ctx->name, ctx->file_priv->context_bans);
2693 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2695 ctx->active_count++;
2698 struct drm_i915_gem_request *
2699 i915_gem_find_active_request(struct intel_engine_cs *engine)
2701 struct drm_i915_gem_request *request, *active = NULL;
2702 unsigned long flags;
2704 /* We are called by the error capture and reset at a random
2705 * point in time. In particular, note that neither is crucially
2706 * ordered with an interrupt. After a hang, the GPU is dead and we
2707 * assume that no more writes can happen (we waited long enough for
2708 * all writes that were in transaction to be flushed) - adding an
2709 * extra delay for a recent interrupt is pointless. Hence, we do
2710 * not need an engine->irq_seqno_barrier() before the seqno reads.
2712 spin_lock_irqsave(&engine->timeline->lock, flags);
2713 list_for_each_entry(request, &engine->timeline->requests, link) {
2714 if (__i915_gem_request_completed(request,
2715 request->global_seqno))
2718 GEM_BUG_ON(request->engine != engine);
2719 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2720 &request->fence.flags));
2725 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2730 static bool engine_stalled(struct intel_engine_cs *engine)
2732 if (!engine->hangcheck.stalled)
2735 /* Check for possible seqno movement after hang declaration */
2736 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2737 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2744 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2746 struct intel_engine_cs *engine;
2747 enum intel_engine_id id;
2750 /* Ensure irq handler finishes, and not run again. */
2751 for_each_engine(engine, dev_priv, id) {
2752 struct drm_i915_gem_request *request;
2754 /* Prevent the signaler thread from updating the request
2755 * state (by calling dma_fence_signal) as we are processing
2756 * the reset. The write from the GPU of the seqno is
2757 * asynchronous and the signaler thread may see a different
2758 * value to us and declare the request complete, even though
2759 * the reset routine have picked that request as the active
2760 * (incomplete) request. This conflict is not handled
2763 kthread_park(engine->breadcrumbs.signaler);
2765 /* Prevent request submission to the hardware until we have
2766 * completed the reset in i915_gem_reset_finish(). If a request
2767 * is completed by one engine, it may then queue a request
2768 * to a second via its engine->irq_tasklet *just* as we are
2769 * calling engine->init_hw() and also writing the ELSP.
2770 * Turning off the engine->irq_tasklet until the reset is over
2771 * prevents the race.
2773 tasklet_kill(&engine->irq_tasklet);
2774 tasklet_disable(&engine->irq_tasklet);
2776 if (engine->irq_seqno_barrier)
2777 engine->irq_seqno_barrier(engine);
2779 if (engine_stalled(engine)) {
2780 request = i915_gem_find_active_request(engine);
2781 if (request && request->fence.error == -EIO)
2782 err = -EIO; /* Previous reset failed! */
2786 i915_gem_revoke_fences(dev_priv);
2791 static void skip_request(struct drm_i915_gem_request *request)
2793 void *vaddr = request->ring->vaddr;
2796 /* As this request likely depends on state from the lost
2797 * context, clear out all the user operations leaving the
2798 * breadcrumb at the end (so we get the fence notifications).
2800 head = request->head;
2801 if (request->postfix < head) {
2802 memset(vaddr + head, 0, request->ring->size - head);
2805 memset(vaddr + head, 0, request->postfix - head);
2807 dma_fence_set_error(&request->fence, -EIO);
2810 static void engine_skip_context(struct drm_i915_gem_request *request)
2812 struct intel_engine_cs *engine = request->engine;
2813 struct i915_gem_context *hung_ctx = request->ctx;
2814 struct intel_timeline *timeline;
2815 unsigned long flags;
2817 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2819 spin_lock_irqsave(&engine->timeline->lock, flags);
2820 spin_lock(&timeline->lock);
2822 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2823 if (request->ctx == hung_ctx)
2824 skip_request(request);
2826 list_for_each_entry(request, &timeline->requests, link)
2827 skip_request(request);
2829 spin_unlock(&timeline->lock);
2830 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2833 /* Returns true if the request was guilty of hang */
2834 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2836 /* Read once and return the resolution */
2837 const bool guilty = engine_stalled(request->engine);
2839 /* The guilty request will get skipped on a hung engine.
2841 * Users of client default contexts do not rely on logical
2842 * state preserved between batches so it is safe to execute
2843 * queued requests following the hang. Non default contexts
2844 * rely on preserved state, so skipping a batch loses the
2845 * evolution of the state and it needs to be considered corrupted.
2846 * Executing more queued batches on top of corrupted state is
2847 * risky. But we take the risk by trying to advance through
2848 * the queued requests in order to make the client behaviour
2849 * more predictable around resets, by not throwing away random
2850 * amount of batches it has prepared for execution. Sophisticated
2851 * clients can use gem_reset_stats_ioctl and dma fence status
2852 * (exported via sync_file info ioctl on explicit fences) to observe
2853 * when it loses the context state and should rebuild accordingly.
2855 * The context ban, and ultimately the client ban, mechanism are safety
2856 * valves if client submission ends up resulting in nothing more than
2861 i915_gem_context_mark_guilty(request->ctx);
2862 skip_request(request);
2864 i915_gem_context_mark_innocent(request->ctx);
2865 dma_fence_set_error(&request->fence, -EAGAIN);
2871 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2873 struct drm_i915_gem_request *request;
2875 request = i915_gem_find_active_request(engine);
2876 if (request && i915_gem_reset_request(request)) {
2877 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2878 engine->name, request->global_seqno);
2880 /* If this context is now banned, skip all pending requests. */
2881 if (i915_gem_context_is_banned(request->ctx))
2882 engine_skip_context(request);
2885 /* Setup the CS to resume from the breadcrumb of the hung request */
2886 engine->reset_hw(engine, request);
2889 void i915_gem_reset(struct drm_i915_private *dev_priv)
2891 struct intel_engine_cs *engine;
2892 enum intel_engine_id id;
2894 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2896 i915_gem_retire_requests(dev_priv);
2898 for_each_engine(engine, dev_priv, id) {
2899 struct i915_gem_context *ctx;
2901 i915_gem_reset_engine(engine);
2902 ctx = fetch_and_zero(&engine->last_retired_context);
2904 engine->context_unpin(engine, ctx);
2907 i915_gem_restore_fences(dev_priv);
2909 if (dev_priv->gt.awake) {
2910 intel_sanitize_gt_powersave(dev_priv);
2911 intel_enable_gt_powersave(dev_priv);
2912 if (INTEL_GEN(dev_priv) >= 6)
2913 gen6_rps_busy(dev_priv);
2917 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
2919 struct intel_engine_cs *engine;
2920 enum intel_engine_id id;
2922 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2924 for_each_engine(engine, dev_priv, id) {
2925 tasklet_enable(&engine->irq_tasklet);
2926 kthread_unpark(engine->breadcrumbs.signaler);
2930 static void nop_submit_request(struct drm_i915_gem_request *request)
2932 dma_fence_set_error(&request->fence, -EIO);
2933 i915_gem_request_submit(request);
2934 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2937 static void engine_set_wedged(struct intel_engine_cs *engine)
2939 struct drm_i915_gem_request *request;
2940 unsigned long flags;
2942 /* We need to be sure that no thread is running the old callback as
2943 * we install the nop handler (otherwise we would submit a request
2944 * to hardware that will never complete). In order to prevent this
2945 * race, we wait until the machine is idle before making the swap
2946 * (using stop_machine()).
2948 engine->submit_request = nop_submit_request;
2950 /* Mark all executing requests as skipped */
2951 spin_lock_irqsave(&engine->timeline->lock, flags);
2952 list_for_each_entry(request, &engine->timeline->requests, link)
2953 dma_fence_set_error(&request->fence, -EIO);
2954 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2956 /* Mark all pending requests as complete so that any concurrent
2957 * (lockless) lookup doesn't try and wait upon the request as we
2960 intel_engine_init_global_seqno(engine,
2961 intel_engine_last_submit(engine));
2964 * Clear the execlists queue up before freeing the requests, as those
2965 * are the ones that keep the context and ringbuffer backing objects
2969 if (i915.enable_execlists) {
2970 unsigned long flags;
2972 spin_lock_irqsave(&engine->timeline->lock, flags);
2974 i915_gem_request_put(engine->execlist_port[0].request);
2975 i915_gem_request_put(engine->execlist_port[1].request);
2976 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2977 engine->execlist_queue = RB_ROOT;
2978 engine->execlist_first = NULL;
2980 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2984 static int __i915_gem_set_wedged_BKL(void *data)
2986 struct drm_i915_private *i915 = data;
2987 struct intel_engine_cs *engine;
2988 enum intel_engine_id id;
2990 for_each_engine(engine, i915, id)
2991 engine_set_wedged(engine);
2996 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2998 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2999 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
3001 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3003 i915_gem_context_lost(dev_priv);
3004 i915_gem_retire_requests(dev_priv);
3006 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
3009 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3011 struct i915_gem_timeline *tl;
3014 lockdep_assert_held(&i915->drm.struct_mutex);
3015 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3018 /* Before unwedging, make sure that all pending operations
3019 * are flushed and errored out - we may have requests waiting upon
3020 * third party fences. We marked all inflight requests as EIO, and
3021 * every execbuf since returned EIO, for consistency we want all
3022 * the currently pending requests to also be marked as EIO, which
3023 * is done inside our nop_submit_request - and so we must wait.
3025 * No more can be submitted until we reset the wedged bit.
3027 list_for_each_entry(tl, &i915->gt.timelines, link) {
3028 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3029 struct drm_i915_gem_request *rq;
3031 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3032 &i915->drm.struct_mutex);
3036 /* We can't use our normal waiter as we want to
3037 * avoid recursively trying to handle the current
3038 * reset. The basic dma_fence_default_wait() installs
3039 * a callback for dma_fence_signal(), which is
3040 * triggered by our nop handler (indirectly, the
3041 * callback enables the signaler thread which is
3042 * woken by the nop_submit_request() advancing the seqno
3043 * and when the seqno passes the fence, the signaler
3044 * then signals the fence waking us up).
3046 if (dma_fence_default_wait(&rq->fence, true,
3047 MAX_SCHEDULE_TIMEOUT) < 0)
3052 /* Undo nop_submit_request. We prevent all new i915 requests from
3053 * being queued (by disallowing execbuf whilst wedged) so having
3054 * waited for all active requests above, we know the system is idle
3055 * and do not have to worry about a thread being inside
3056 * engine->submit_request() as we swap over. So unlike installing
3057 * the nop_submit_request on reset, we can do this from normal
3058 * context and do not require stop_machine().
3060 intel_engines_reset_default_submission(i915);
3062 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3063 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3069 i915_gem_retire_work_handler(struct work_struct *work)
3071 struct drm_i915_private *dev_priv =
3072 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3073 struct drm_device *dev = &dev_priv->drm;
3075 /* Come back later if the device is busy... */
3076 if (mutex_trylock(&dev->struct_mutex)) {
3077 i915_gem_retire_requests(dev_priv);
3078 mutex_unlock(&dev->struct_mutex);
3081 /* Keep the retire handler running until we are finally idle.
3082 * We do not need to do this test under locking as in the worst-case
3083 * we queue the retire worker once too often.
3085 if (READ_ONCE(dev_priv->gt.awake)) {
3086 i915_queue_hangcheck(dev_priv);
3087 queue_delayed_work(dev_priv->wq,
3088 &dev_priv->gt.retire_work,
3089 round_jiffies_up_relative(HZ));
3094 i915_gem_idle_work_handler(struct work_struct *work)
3096 struct drm_i915_private *dev_priv =
3097 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3098 struct drm_device *dev = &dev_priv->drm;
3099 struct intel_engine_cs *engine;
3100 enum intel_engine_id id;
3101 bool rearm_hangcheck;
3103 if (!READ_ONCE(dev_priv->gt.awake))
3107 * Wait for last execlists context complete, but bail out in case a
3108 * new request is submitted.
3110 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
3111 intel_engines_are_idle(dev_priv),
3113 if (READ_ONCE(dev_priv->gt.active_requests))
3117 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3119 if (!mutex_trylock(&dev->struct_mutex)) {
3120 /* Currently busy, come back later */
3121 mod_delayed_work(dev_priv->wq,
3122 &dev_priv->gt.idle_work,
3123 msecs_to_jiffies(50));
3128 * New request retired after this work handler started, extend active
3129 * period until next instance of the work.
3131 if (work_pending(work))
3134 if (dev_priv->gt.active_requests)
3137 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3138 DRM_ERROR("Timeout waiting for engines to idle\n");
3140 for_each_engine(engine, dev_priv, id) {
3141 intel_engine_disarm_breadcrumbs(engine);
3142 i915_gem_batch_pool_fini(&engine->batch_pool);
3145 GEM_BUG_ON(!dev_priv->gt.awake);
3146 dev_priv->gt.awake = false;
3147 rearm_hangcheck = false;
3149 if (INTEL_GEN(dev_priv) >= 6)
3150 gen6_rps_idle(dev_priv);
3151 intel_runtime_pm_put(dev_priv);
3153 mutex_unlock(&dev->struct_mutex);
3156 if (rearm_hangcheck) {
3157 GEM_BUG_ON(!dev_priv->gt.awake);
3158 i915_queue_hangcheck(dev_priv);
3162 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3164 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3165 struct drm_i915_file_private *fpriv = file->driver_priv;
3166 struct i915_vma *vma, *vn;
3168 mutex_lock(&obj->base.dev->struct_mutex);
3169 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3170 if (vma->vm->file == fpriv)
3171 i915_vma_close(vma);
3173 if (i915_gem_object_is_active(obj) &&
3174 !i915_gem_object_has_active_reference(obj)) {
3175 i915_gem_object_set_active_reference(obj);
3176 i915_gem_object_get(obj);
3178 mutex_unlock(&obj->base.dev->struct_mutex);
3181 static unsigned long to_wait_timeout(s64 timeout_ns)
3184 return MAX_SCHEDULE_TIMEOUT;
3186 if (timeout_ns == 0)
3189 return nsecs_to_jiffies_timeout(timeout_ns);
3193 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3194 * @dev: drm device pointer
3195 * @data: ioctl data blob
3196 * @file: drm file pointer
3198 * Returns 0 if successful, else an error is returned with the remaining time in
3199 * the timeout parameter.
3200 * -ETIME: object is still busy after timeout
3201 * -ERESTARTSYS: signal interrupted the wait
3202 * -ENONENT: object doesn't exist
3203 * Also possible, but rare:
3204 * -EAGAIN: GPU wedged
3206 * -ENODEV: Internal IRQ fail
3207 * -E?: The add request failed
3209 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3210 * non-zero timeout parameter the wait ioctl will wait for the given number of
3211 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3212 * without holding struct_mutex the object may become re-busied before this
3213 * function completes. A similar but shorter * race condition exists in the busy
3217 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3219 struct drm_i915_gem_wait *args = data;
3220 struct drm_i915_gem_object *obj;
3224 if (args->flags != 0)
3227 obj = i915_gem_object_lookup(file, args->bo_handle);
3231 start = ktime_get();
3233 ret = i915_gem_object_wait(obj,
3234 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3235 to_wait_timeout(args->timeout_ns),
3236 to_rps_client(file));
3238 if (args->timeout_ns > 0) {
3239 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3240 if (args->timeout_ns < 0)
3241 args->timeout_ns = 0;
3244 * Apparently ktime isn't accurate enough and occasionally has a
3245 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3246 * things up to make the test happy. We allow up to 1 jiffy.
3248 * This is a regression from the timespec->ktime conversion.
3250 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3251 args->timeout_ns = 0;
3254 i915_gem_object_put(obj);
3258 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3262 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3263 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3271 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3275 if (flags & I915_WAIT_LOCKED) {
3276 struct i915_gem_timeline *tl;
3278 lockdep_assert_held(&i915->drm.struct_mutex);
3280 list_for_each_entry(tl, &i915->gt.timelines, link) {
3281 ret = wait_for_timeline(tl, flags);
3286 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3294 /** Flushes the GTT write domain for the object if it's dirty. */
3296 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3298 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3300 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3303 /* No actual flushing is required for the GTT write domain. Writes
3304 * to it "immediately" go to main memory as far as we know, so there's
3305 * no chipset flush. It also doesn't land in render cache.
3307 * However, we do have to enforce the order so that all writes through
3308 * the GTT land before any writes to the device, such as updates to
3311 * We also have to wait a bit for the writes to land from the GTT.
3312 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3313 * timing. This issue has only been observed when switching quickly
3314 * between GTT writes and CPU reads from inside the kernel on recent hw,
3315 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3316 * system agents we cannot reproduce this behaviour).
3319 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
3320 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
3321 spin_lock_irq(&dev_priv->uncore.lock);
3322 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3323 spin_unlock_irq(&dev_priv->uncore.lock);
3324 intel_runtime_pm_put(dev_priv);
3328 intel_fb_obj_flush(obj, write_origin(obj, I915_GEM_DOMAIN_GTT));
3330 obj->base.write_domain = 0;
3333 /** Flushes the CPU write domain for the object if it's dirty. */
3335 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3337 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3340 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3341 obj->base.write_domain = 0;
3344 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3346 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU && !obj->cache_dirty)
3349 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3350 obj->base.write_domain = 0;
3353 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3355 if (!READ_ONCE(obj->pin_display))
3358 mutex_lock(&obj->base.dev->struct_mutex);
3359 __i915_gem_object_flush_for_display(obj);
3360 mutex_unlock(&obj->base.dev->struct_mutex);
3364 * Moves a single object to the GTT read, and possibly write domain.
3365 * @obj: object to act on
3366 * @write: ask for write access or read only
3368 * This function returns when the move is complete, including waiting on
3372 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3376 lockdep_assert_held(&obj->base.dev->struct_mutex);
3378 ret = i915_gem_object_wait(obj,
3379 I915_WAIT_INTERRUPTIBLE |
3381 (write ? I915_WAIT_ALL : 0),
3382 MAX_SCHEDULE_TIMEOUT,
3387 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3390 /* Flush and acquire obj->pages so that we are coherent through
3391 * direct access in memory with previous cached writes through
3392 * shmemfs and that our cache domain tracking remains valid.
3393 * For example, if the obj->filp was moved to swap without us
3394 * being notified and releasing the pages, we would mistakenly
3395 * continue to assume that the obj remained out of the CPU cached
3398 ret = i915_gem_object_pin_pages(obj);
3402 i915_gem_object_flush_cpu_write_domain(obj);
3404 /* Serialise direct access to this object with the barriers for
3405 * coherent writes from the GPU, by effectively invalidating the
3406 * GTT domain upon first access.
3408 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3411 /* It should now be out of any other write domains, and we can update
3412 * the domain values for our changes.
3414 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3415 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3417 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3418 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3419 obj->mm.dirty = true;
3422 i915_gem_object_unpin_pages(obj);
3427 * Changes the cache-level of an object across all VMA.
3428 * @obj: object to act on
3429 * @cache_level: new cache level to set for the object
3431 * After this function returns, the object will be in the new cache-level
3432 * across all GTT and the contents of the backing storage will be coherent,
3433 * with respect to the new cache-level. In order to keep the backing storage
3434 * coherent for all users, we only allow a single cache level to be set
3435 * globally on the object and prevent it from being changed whilst the
3436 * hardware is reading from the object. That is if the object is currently
3437 * on the scanout it will be set to uncached (or equivalent display
3438 * cache coherency) and all non-MOCS GPU access will also be uncached so
3439 * that all direct access to the scanout remains coherent.
3441 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3442 enum i915_cache_level cache_level)
3444 struct i915_vma *vma;
3447 lockdep_assert_held(&obj->base.dev->struct_mutex);
3449 if (obj->cache_level == cache_level)
3452 /* Inspect the list of currently bound VMA and unbind any that would
3453 * be invalid given the new cache-level. This is principally to
3454 * catch the issue of the CS prefetch crossing page boundaries and
3455 * reading an invalid PTE on older architectures.
3458 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3459 if (!drm_mm_node_allocated(&vma->node))
3462 if (i915_vma_is_pinned(vma)) {
3463 DRM_DEBUG("can not change the cache level of pinned objects\n");
3467 if (i915_gem_valid_gtt_space(vma, cache_level))
3470 ret = i915_vma_unbind(vma);
3474 /* As unbinding may affect other elements in the
3475 * obj->vma_list (due to side-effects from retiring
3476 * an active vma), play safe and restart the iterator.
3481 /* We can reuse the existing drm_mm nodes but need to change the
3482 * cache-level on the PTE. We could simply unbind them all and
3483 * rebind with the correct cache-level on next use. However since
3484 * we already have a valid slot, dma mapping, pages etc, we may as
3485 * rewrite the PTE in the belief that doing so tramples upon less
3486 * state and so involves less work.
3488 if (obj->bind_count) {
3489 /* Before we change the PTE, the GPU must not be accessing it.
3490 * If we wait upon the object, we know that all the bound
3491 * VMA are no longer active.
3493 ret = i915_gem_object_wait(obj,
3494 I915_WAIT_INTERRUPTIBLE |
3497 MAX_SCHEDULE_TIMEOUT,
3502 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3503 cache_level != I915_CACHE_NONE) {
3504 /* Access to snoopable pages through the GTT is
3505 * incoherent and on some machines causes a hard
3506 * lockup. Relinquish the CPU mmaping to force
3507 * userspace to refault in the pages and we can
3508 * then double check if the GTT mapping is still
3509 * valid for that pointer access.
3511 i915_gem_release_mmap(obj);
3513 /* As we no longer need a fence for GTT access,
3514 * we can relinquish it now (and so prevent having
3515 * to steal a fence from someone else on the next
3516 * fence request). Note GPU activity would have
3517 * dropped the fence as all snoopable access is
3518 * supposed to be linear.
3520 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3521 ret = i915_vma_put_fence(vma);
3526 /* We either have incoherent backing store and
3527 * so no GTT access or the architecture is fully
3528 * coherent. In such cases, existing GTT mmaps
3529 * ignore the cache bit in the PTE and we can
3530 * rewrite it without confusing the GPU or having
3531 * to force userspace to fault back in its mmaps.
3535 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3536 if (!drm_mm_node_allocated(&vma->node))
3539 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3545 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3546 i915_gem_object_is_coherent(obj))
3547 obj->cache_dirty = true;
3549 list_for_each_entry(vma, &obj->vma_list, obj_link)
3550 vma->node.color = cache_level;
3551 obj->cache_level = cache_level;
3556 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3557 struct drm_file *file)
3559 struct drm_i915_gem_caching *args = data;
3560 struct drm_i915_gem_object *obj;
3564 obj = i915_gem_object_lookup_rcu(file, args->handle);
3570 switch (obj->cache_level) {
3571 case I915_CACHE_LLC:
3572 case I915_CACHE_L3_LLC:
3573 args->caching = I915_CACHING_CACHED;
3577 args->caching = I915_CACHING_DISPLAY;
3581 args->caching = I915_CACHING_NONE;
3589 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3590 struct drm_file *file)
3592 struct drm_i915_private *i915 = to_i915(dev);
3593 struct drm_i915_gem_caching *args = data;
3594 struct drm_i915_gem_object *obj;
3595 enum i915_cache_level level;
3598 switch (args->caching) {
3599 case I915_CACHING_NONE:
3600 level = I915_CACHE_NONE;
3602 case I915_CACHING_CACHED:
3604 * Due to a HW issue on BXT A stepping, GPU stores via a
3605 * snooped mapping may leave stale data in a corresponding CPU
3606 * cacheline, whereas normally such cachelines would get
3609 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3612 level = I915_CACHE_LLC;
3614 case I915_CACHING_DISPLAY:
3615 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3621 obj = i915_gem_object_lookup(file, args->handle);
3625 if (obj->cache_level == level)
3628 ret = i915_gem_object_wait(obj,
3629 I915_WAIT_INTERRUPTIBLE,
3630 MAX_SCHEDULE_TIMEOUT,
3631 to_rps_client(file));
3635 ret = i915_mutex_lock_interruptible(dev);
3639 ret = i915_gem_object_set_cache_level(obj, level);
3640 mutex_unlock(&dev->struct_mutex);
3643 i915_gem_object_put(obj);
3648 * Prepare buffer for display plane (scanout, cursors, etc).
3649 * Can be called from an uninterruptible phase (modesetting) and allows
3650 * any flushes to be pipelined (for pageflips).
3653 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3655 const struct i915_ggtt_view *view)
3657 struct i915_vma *vma;
3660 lockdep_assert_held(&obj->base.dev->struct_mutex);
3662 /* Mark the pin_display early so that we account for the
3663 * display coherency whilst setting up the cache domains.
3667 /* The display engine is not coherent with the LLC cache on gen6. As
3668 * a result, we make sure that the pinning that is about to occur is
3669 * done with uncached PTEs. This is lowest common denominator for all
3672 * However for gen6+, we could do better by using the GFDT bit instead
3673 * of uncaching, which would allow us to flush all the LLC-cached data
3674 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3676 ret = i915_gem_object_set_cache_level(obj,
3677 HAS_WT(to_i915(obj->base.dev)) ?
3678 I915_CACHE_WT : I915_CACHE_NONE);
3681 goto err_unpin_display;
3684 /* As the user may map the buffer once pinned in the display plane
3685 * (e.g. libkms for the bootup splash), we have to ensure that we
3686 * always use map_and_fenceable for all scanout buffers. However,
3687 * it may simply be too big to fit into mappable, in which case
3688 * put it anyway and hope that userspace can cope (but always first
3689 * try to preserve the existing ABI).
3691 vma = ERR_PTR(-ENOSPC);
3692 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3693 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3694 PIN_MAPPABLE | PIN_NONBLOCK);
3696 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3699 /* Valleyview is definitely limited to scanning out the first
3700 * 512MiB. Lets presume this behaviour was inherited from the
3701 * g4x display engine and that all earlier gen are similarly
3702 * limited. Testing suggests that it is a little more
3703 * complicated than this. For example, Cherryview appears quite
3704 * happy to scanout from anywhere within its global aperture.
3707 if (HAS_GMCH_DISPLAY(i915))
3708 flags = PIN_MAPPABLE;
3709 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3712 goto err_unpin_display;
3714 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3716 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3717 __i915_gem_object_flush_for_display(obj);
3718 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3720 /* It should now be out of any other write domains, and we can update
3721 * the domain values for our changes.
3723 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3733 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3735 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3737 if (WARN_ON(vma->obj->pin_display == 0))
3740 if (--vma->obj->pin_display == 0)
3741 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3743 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3744 i915_gem_object_bump_inactive_ggtt(vma->obj);
3746 i915_vma_unpin(vma);
3750 * Moves a single object to the CPU read, and possibly write domain.
3751 * @obj: object to act on
3752 * @write: requesting write or read-only access
3754 * This function returns when the move is complete, including waiting on
3758 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3762 lockdep_assert_held(&obj->base.dev->struct_mutex);
3764 ret = i915_gem_object_wait(obj,
3765 I915_WAIT_INTERRUPTIBLE |
3767 (write ? I915_WAIT_ALL : 0),
3768 MAX_SCHEDULE_TIMEOUT,
3773 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3776 i915_gem_object_flush_gtt_write_domain(obj);
3778 /* Flush the CPU cache if it's still invalid. */
3779 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3780 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3781 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3784 /* It should now be out of any other write domains, and we can update
3785 * the domain values for our changes.
3787 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3789 /* If we're writing through the CPU, then the GPU read domains will
3790 * need to be invalidated at next use.
3793 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3794 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3800 /* Throttle our rendering by waiting until the ring has completed our requests
3801 * emitted over 20 msec ago.
3803 * Note that if we were to use the current jiffies each time around the loop,
3804 * we wouldn't escape the function with any frames outstanding if the time to
3805 * render a frame was over 20ms.
3807 * This should get us reasonable parallelism between CPU and GPU but also
3808 * relatively low latency when blocking on a particular request to finish.
3811 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3813 struct drm_i915_private *dev_priv = to_i915(dev);
3814 struct drm_i915_file_private *file_priv = file->driver_priv;
3815 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3816 struct drm_i915_gem_request *request, *target = NULL;
3819 /* ABI: return -EIO if already wedged */
3820 if (i915_terminally_wedged(&dev_priv->gpu_error))
3823 spin_lock(&file_priv->mm.lock);
3824 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3825 if (time_after_eq(request->emitted_jiffies, recent_enough))
3829 list_del(&target->client_link);
3830 target->file_priv = NULL;
3836 i915_gem_request_get(target);
3837 spin_unlock(&file_priv->mm.lock);
3842 ret = i915_wait_request(target,
3843 I915_WAIT_INTERRUPTIBLE,
3844 MAX_SCHEDULE_TIMEOUT);
3845 i915_gem_request_put(target);
3847 return ret < 0 ? ret : 0;
3851 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3852 const struct i915_ggtt_view *view,
3857 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3858 struct i915_address_space *vm = &dev_priv->ggtt.base;
3859 struct i915_vma *vma;
3862 lockdep_assert_held(&obj->base.dev->struct_mutex);
3864 vma = i915_vma_instance(obj, vm, view);
3865 if (unlikely(IS_ERR(vma)))
3868 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3869 if (flags & PIN_NONBLOCK &&
3870 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3871 return ERR_PTR(-ENOSPC);
3873 if (flags & PIN_MAPPABLE) {
3874 /* If the required space is larger than the available
3875 * aperture, we will not able to find a slot for the
3876 * object and unbinding the object now will be in
3877 * vain. Worse, doing so may cause us to ping-pong
3878 * the object in and out of the Global GTT and
3879 * waste a lot of cycles under the mutex.
3881 if (vma->fence_size > dev_priv->ggtt.mappable_end)
3882 return ERR_PTR(-E2BIG);
3884 /* If NONBLOCK is set the caller is optimistically
3885 * trying to cache the full object within the mappable
3886 * aperture, and *must* have a fallback in place for
3887 * situations where we cannot bind the object. We
3888 * can be a little more lax here and use the fallback
3889 * more often to avoid costly migrations of ourselves
3890 * and other objects within the aperture.
3892 * Half-the-aperture is used as a simple heuristic.
3893 * More interesting would to do search for a free
3894 * block prior to making the commitment to unbind.
3895 * That caters for the self-harm case, and with a
3896 * little more heuristics (e.g. NOFAULT, NOEVICT)
3897 * we could try to minimise harm to others.
3899 if (flags & PIN_NONBLOCK &&
3900 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
3901 return ERR_PTR(-ENOSPC);
3904 WARN(i915_vma_is_pinned(vma),
3905 "bo is already pinned in ggtt with incorrect alignment:"
3906 " offset=%08x, req.alignment=%llx,"
3907 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3908 i915_ggtt_offset(vma), alignment,
3909 !!(flags & PIN_MAPPABLE),
3910 i915_vma_is_map_and_fenceable(vma));
3911 ret = i915_vma_unbind(vma);
3913 return ERR_PTR(ret);
3916 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3918 return ERR_PTR(ret);
3923 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3925 /* Note that we could alias engines in the execbuf API, but
3926 * that would be very unwise as it prevents userspace from
3927 * fine control over engine selection. Ahem.
3929 * This should be something like EXEC_MAX_ENGINE instead of
3932 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3933 return 0x10000 << id;
3936 static __always_inline unsigned int __busy_write_id(unsigned int id)
3938 /* The uABI guarantees an active writer is also amongst the read
3939 * engines. This would be true if we accessed the activity tracking
3940 * under the lock, but as we perform the lookup of the object and
3941 * its activity locklessly we can not guarantee that the last_write
3942 * being active implies that we have set the same engine flag from
3943 * last_read - hence we always set both read and write busy for
3946 return id | __busy_read_flag(id);
3949 static __always_inline unsigned int
3950 __busy_set_if_active(const struct dma_fence *fence,
3951 unsigned int (*flag)(unsigned int id))
3953 struct drm_i915_gem_request *rq;
3955 /* We have to check the current hw status of the fence as the uABI
3956 * guarantees forward progress. We could rely on the idle worker
3957 * to eventually flush us, but to minimise latency just ask the
3960 * Note we only report on the status of native fences.
3962 if (!dma_fence_is_i915(fence))
3965 /* opencode to_request() in order to avoid const warnings */
3966 rq = container_of(fence, struct drm_i915_gem_request, fence);
3967 if (i915_gem_request_completed(rq))
3970 return flag(rq->engine->exec_id);
3973 static __always_inline unsigned int
3974 busy_check_reader(const struct dma_fence *fence)
3976 return __busy_set_if_active(fence, __busy_read_flag);
3979 static __always_inline unsigned int
3980 busy_check_writer(const struct dma_fence *fence)
3985 return __busy_set_if_active(fence, __busy_write_id);
3989 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3990 struct drm_file *file)
3992 struct drm_i915_gem_busy *args = data;
3993 struct drm_i915_gem_object *obj;
3994 struct reservation_object_list *list;
4000 obj = i915_gem_object_lookup_rcu(file, args->handle);
4004 /* A discrepancy here is that we do not report the status of
4005 * non-i915 fences, i.e. even though we may report the object as idle,
4006 * a call to set-domain may still stall waiting for foreign rendering.
4007 * This also means that wait-ioctl may report an object as busy,
4008 * where busy-ioctl considers it idle.
4010 * We trade the ability to warn of foreign fences to report on which
4011 * i915 engines are active for the object.
4013 * Alternatively, we can trade that extra information on read/write
4016 * !reservation_object_test_signaled_rcu(obj->resv, true);
4017 * to report the overall busyness. This is what the wait-ioctl does.
4021 seq = raw_read_seqcount(&obj->resv->seq);
4023 /* Translate the exclusive fence to the READ *and* WRITE engine */
4024 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4026 /* Translate shared fences to READ set of engines */
4027 list = rcu_dereference(obj->resv->fence);
4029 unsigned int shared_count = list->shared_count, i;
4031 for (i = 0; i < shared_count; ++i) {
4032 struct dma_fence *fence =
4033 rcu_dereference(list->shared[i]);
4035 args->busy |= busy_check_reader(fence);
4039 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4049 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4050 struct drm_file *file_priv)
4052 return i915_gem_ring_throttle(dev, file_priv);
4056 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4057 struct drm_file *file_priv)
4059 struct drm_i915_private *dev_priv = to_i915(dev);
4060 struct drm_i915_gem_madvise *args = data;
4061 struct drm_i915_gem_object *obj;
4064 switch (args->madv) {
4065 case I915_MADV_DONTNEED:
4066 case I915_MADV_WILLNEED:
4072 obj = i915_gem_object_lookup(file_priv, args->handle);
4076 err = mutex_lock_interruptible(&obj->mm.lock);
4080 if (obj->mm.pages &&
4081 i915_gem_object_is_tiled(obj) &&
4082 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4083 if (obj->mm.madv == I915_MADV_WILLNEED) {
4084 GEM_BUG_ON(!obj->mm.quirked);
4085 __i915_gem_object_unpin_pages(obj);
4086 obj->mm.quirked = false;
4088 if (args->madv == I915_MADV_WILLNEED) {
4089 GEM_BUG_ON(obj->mm.quirked);
4090 __i915_gem_object_pin_pages(obj);
4091 obj->mm.quirked = true;
4095 if (obj->mm.madv != __I915_MADV_PURGED)
4096 obj->mm.madv = args->madv;
4098 /* if the object is no longer attached, discard its backing storage */
4099 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4100 i915_gem_object_truncate(obj);
4102 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4103 mutex_unlock(&obj->mm.lock);
4106 i915_gem_object_put(obj);
4111 frontbuffer_retire(struct i915_gem_active *active,
4112 struct drm_i915_gem_request *request)
4114 struct drm_i915_gem_object *obj =
4115 container_of(active, typeof(*obj), frontbuffer_write);
4117 intel_fb_obj_flush(obj, ORIGIN_CS);
4120 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4121 const struct drm_i915_gem_object_ops *ops)
4123 mutex_init(&obj->mm.lock);
4125 INIT_LIST_HEAD(&obj->global_link);
4126 INIT_LIST_HEAD(&obj->userfault_link);
4127 INIT_LIST_HEAD(&obj->obj_exec_link);
4128 INIT_LIST_HEAD(&obj->vma_list);
4129 INIT_LIST_HEAD(&obj->batch_pool_link);
4133 reservation_object_init(&obj->__builtin_resv);
4134 obj->resv = &obj->__builtin_resv;
4136 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4137 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4139 obj->mm.madv = I915_MADV_WILLNEED;
4140 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4141 mutex_init(&obj->mm.get_page.lock);
4143 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4146 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4147 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4148 I915_GEM_OBJECT_IS_SHRINKABLE,
4150 .get_pages = i915_gem_object_get_pages_gtt,
4151 .put_pages = i915_gem_object_put_pages_gtt,
4153 .pwrite = i915_gem_object_pwrite_gtt,
4156 struct drm_i915_gem_object *
4157 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4159 struct drm_i915_gem_object *obj;
4160 struct address_space *mapping;
4164 /* There is a prevalence of the assumption that we fit the object's
4165 * page count inside a 32bit _signed_ variable. Let's document this and
4166 * catch if we ever need to fix it. In the meantime, if you do spot
4167 * such a local variable, please consider fixing!
4169 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
4170 return ERR_PTR(-E2BIG);
4172 if (overflows_type(size, obj->base.size))
4173 return ERR_PTR(-E2BIG);
4175 obj = i915_gem_object_alloc(dev_priv);
4177 return ERR_PTR(-ENOMEM);
4179 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4183 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4184 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4185 /* 965gm cannot relocate objects above 4GiB. */
4186 mask &= ~__GFP_HIGHMEM;
4187 mask |= __GFP_DMA32;
4190 mapping = obj->base.filp->f_mapping;
4191 mapping_set_gfp_mask(mapping, mask);
4193 i915_gem_object_init(obj, &i915_gem_object_ops);
4195 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4196 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4198 if (HAS_LLC(dev_priv)) {
4199 /* On some devices, we can have the GPU use the LLC (the CPU
4200 * cache) for about a 10% performance improvement
4201 * compared to uncached. Graphics requests other than
4202 * display scanout are coherent with the CPU in
4203 * accessing this cache. This means in this mode we
4204 * don't need to clflush on the CPU side, and on the
4205 * GPU side we only need to flush internal caches to
4206 * get data visible to the CPU.
4208 * However, we maintain the display planes as UC, and so
4209 * need to rebind when first used as such.
4211 obj->cache_level = I915_CACHE_LLC;
4213 obj->cache_level = I915_CACHE_NONE;
4215 trace_i915_gem_object_create(obj);
4220 i915_gem_object_free(obj);
4221 return ERR_PTR(ret);
4224 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4226 /* If we are the last user of the backing storage (be it shmemfs
4227 * pages or stolen etc), we know that the pages are going to be
4228 * immediately released. In this case, we can then skip copying
4229 * back the contents from the GPU.
4232 if (obj->mm.madv != I915_MADV_WILLNEED)
4235 if (obj->base.filp == NULL)
4238 /* At first glance, this looks racy, but then again so would be
4239 * userspace racing mmap against close. However, the first external
4240 * reference to the filp can only be obtained through the
4241 * i915_gem_mmap_ioctl() which safeguards us against the user
4242 * acquiring such a reference whilst we are in the middle of
4243 * freeing the object.
4245 return atomic_long_read(&obj->base.filp->f_count) == 1;
4248 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4249 struct llist_node *freed)
4251 struct drm_i915_gem_object *obj, *on;
4253 mutex_lock(&i915->drm.struct_mutex);
4254 intel_runtime_pm_get(i915);
4255 llist_for_each_entry(obj, freed, freed) {
4256 struct i915_vma *vma, *vn;
4258 trace_i915_gem_object_destroy(obj);
4260 GEM_BUG_ON(i915_gem_object_is_active(obj));
4261 list_for_each_entry_safe(vma, vn,
4262 &obj->vma_list, obj_link) {
4263 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4264 GEM_BUG_ON(i915_vma_is_active(vma));
4265 vma->flags &= ~I915_VMA_PIN_MASK;
4266 i915_vma_close(vma);
4268 GEM_BUG_ON(!list_empty(&obj->vma_list));
4269 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4271 list_del(&obj->global_link);
4273 intel_runtime_pm_put(i915);
4274 mutex_unlock(&i915->drm.struct_mutex);
4276 llist_for_each_entry_safe(obj, on, freed, freed) {
4277 GEM_BUG_ON(obj->bind_count);
4278 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4280 if (obj->ops->release)
4281 obj->ops->release(obj);
4283 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4284 atomic_set(&obj->mm.pages_pin_count, 0);
4285 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4286 GEM_BUG_ON(obj->mm.pages);
4288 if (obj->base.import_attach)
4289 drm_prime_gem_destroy(&obj->base, NULL);
4291 reservation_object_fini(&obj->__builtin_resv);
4292 drm_gem_object_release(&obj->base);
4293 i915_gem_info_remove_obj(i915, obj->base.size);
4296 i915_gem_object_free(obj);
4300 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4302 struct llist_node *freed;
4304 freed = llist_del_all(&i915->mm.free_list);
4305 if (unlikely(freed))
4306 __i915_gem_free_objects(i915, freed);
4309 static void __i915_gem_free_work(struct work_struct *work)
4311 struct drm_i915_private *i915 =
4312 container_of(work, struct drm_i915_private, mm.free_work);
4313 struct llist_node *freed;
4315 /* All file-owned VMA should have been released by this point through
4316 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4317 * However, the object may also be bound into the global GTT (e.g.
4318 * older GPUs without per-process support, or for direct access through
4319 * the GTT either for the user or for scanout). Those VMA still need to
4323 while ((freed = llist_del_all(&i915->mm.free_list)))
4324 __i915_gem_free_objects(i915, freed);
4327 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4329 struct drm_i915_gem_object *obj =
4330 container_of(head, typeof(*obj), rcu);
4331 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4333 /* We can't simply use call_rcu() from i915_gem_free_object()
4334 * as we need to block whilst unbinding, and the call_rcu
4335 * task may be called from softirq context. So we take a
4336 * detour through a worker.
4338 if (llist_add(&obj->freed, &i915->mm.free_list))
4339 schedule_work(&i915->mm.free_work);
4342 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4344 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4346 if (obj->mm.quirked)
4347 __i915_gem_object_unpin_pages(obj);
4349 if (discard_backing_storage(obj))
4350 obj->mm.madv = I915_MADV_DONTNEED;
4352 /* Before we free the object, make sure any pure RCU-only
4353 * read-side critical sections are complete, e.g.
4354 * i915_gem_busy_ioctl(). For the corresponding synchronized
4355 * lookup see i915_gem_object_lookup_rcu().
4357 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4360 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4362 lockdep_assert_held(&obj->base.dev->struct_mutex);
4364 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4365 if (i915_gem_object_is_active(obj))
4366 i915_gem_object_set_active_reference(obj);
4368 i915_gem_object_put(obj);
4371 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4373 struct intel_engine_cs *engine;
4374 enum intel_engine_id id;
4376 for_each_engine(engine, dev_priv, id)
4377 GEM_BUG_ON(engine->last_retired_context &&
4378 !i915_gem_context_is_kernel(engine->last_retired_context));
4381 void i915_gem_sanitize(struct drm_i915_private *i915)
4384 * If we inherit context state from the BIOS or earlier occupants
4385 * of the GPU, the GPU may be in an inconsistent state when we
4386 * try to take over. The only way to remove the earlier state
4387 * is by resetting. However, resetting on earlier gen is tricky as
4388 * it may impact the display and we are uncertain about the stability
4389 * of the reset, so we only reset recent machines with logical
4390 * context support (that must be reset to remove any stray contexts).
4392 if (HAS_HW_CONTEXTS(i915)) {
4393 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4394 WARN_ON(reset && reset != -ENODEV);
4398 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4400 struct drm_device *dev = &dev_priv->drm;
4403 intel_runtime_pm_get(dev_priv);
4404 intel_suspend_gt_powersave(dev_priv);
4406 mutex_lock(&dev->struct_mutex);
4408 /* We have to flush all the executing contexts to main memory so
4409 * that they can saved in the hibernation image. To ensure the last
4410 * context image is coherent, we have to switch away from it. That
4411 * leaves the dev_priv->kernel_context still active when
4412 * we actually suspend, and its image in memory may not match the GPU
4413 * state. Fortunately, the kernel_context is disposable and we do
4414 * not rely on its state.
4416 ret = i915_gem_switch_to_kernel_context(dev_priv);
4420 ret = i915_gem_wait_for_idle(dev_priv,
4421 I915_WAIT_INTERRUPTIBLE |
4426 i915_gem_retire_requests(dev_priv);
4427 GEM_BUG_ON(dev_priv->gt.active_requests);
4429 assert_kernel_context_is_current(dev_priv);
4430 i915_gem_context_lost(dev_priv);
4431 mutex_unlock(&dev->struct_mutex);
4433 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4434 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4436 /* As the idle_work is rearming if it detects a race, play safe and
4437 * repeat the flush until it is definitely idle.
4439 while (flush_delayed_work(&dev_priv->gt.idle_work))
4442 i915_gem_drain_freed_objects(dev_priv);
4444 /* Assert that we sucessfully flushed all the work and
4445 * reset the GPU back to its idle, low power state.
4447 WARN_ON(dev_priv->gt.awake);
4448 WARN_ON(!intel_engines_are_idle(dev_priv));
4451 * Neither the BIOS, ourselves or any other kernel
4452 * expects the system to be in execlists mode on startup,
4453 * so we need to reset the GPU back to legacy mode. And the only
4454 * known way to disable logical contexts is through a GPU reset.
4456 * So in order to leave the system in a known default configuration,
4457 * always reset the GPU upon unload and suspend. Afterwards we then
4458 * clean up the GEM state tracking, flushing off the requests and
4459 * leaving the system in a known idle state.
4461 * Note that is of the upmost importance that the GPU is idle and
4462 * all stray writes are flushed *before* we dismantle the backing
4463 * storage for the pinned objects.
4465 * However, since we are uncertain that resetting the GPU on older
4466 * machines is a good idea, we don't - just in case it leaves the
4467 * machine in an unusable condition.
4469 i915_gem_sanitize(dev_priv);
4473 mutex_unlock(&dev->struct_mutex);
4475 intel_runtime_pm_put(dev_priv);
4479 void i915_gem_resume(struct drm_i915_private *dev_priv)
4481 struct drm_device *dev = &dev_priv->drm;
4483 WARN_ON(dev_priv->gt.awake);
4485 mutex_lock(&dev->struct_mutex);
4486 i915_gem_restore_gtt_mappings(dev_priv);
4488 /* As we didn't flush the kernel context before suspend, we cannot
4489 * guarantee that the context image is complete. So let's just reset
4490 * it and start again.
4492 dev_priv->gt.resume(dev_priv);
4494 mutex_unlock(&dev->struct_mutex);
4497 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4499 if (INTEL_GEN(dev_priv) < 5 ||
4500 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4503 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4504 DISP_TILE_SURFACE_SWIZZLING);
4506 if (IS_GEN5(dev_priv))
4509 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4510 if (IS_GEN6(dev_priv))
4511 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4512 else if (IS_GEN7(dev_priv))
4513 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4514 else if (IS_GEN8(dev_priv))
4515 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4520 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4522 I915_WRITE(RING_CTL(base), 0);
4523 I915_WRITE(RING_HEAD(base), 0);
4524 I915_WRITE(RING_TAIL(base), 0);
4525 I915_WRITE(RING_START(base), 0);
4528 static void init_unused_rings(struct drm_i915_private *dev_priv)
4530 if (IS_I830(dev_priv)) {
4531 init_unused_ring(dev_priv, PRB1_BASE);
4532 init_unused_ring(dev_priv, SRB0_BASE);
4533 init_unused_ring(dev_priv, SRB1_BASE);
4534 init_unused_ring(dev_priv, SRB2_BASE);
4535 init_unused_ring(dev_priv, SRB3_BASE);
4536 } else if (IS_GEN2(dev_priv)) {
4537 init_unused_ring(dev_priv, SRB0_BASE);
4538 init_unused_ring(dev_priv, SRB1_BASE);
4539 } else if (IS_GEN3(dev_priv)) {
4540 init_unused_ring(dev_priv, PRB1_BASE);
4541 init_unused_ring(dev_priv, PRB2_BASE);
4545 static int __i915_gem_restart_engines(void *data)
4547 struct drm_i915_private *i915 = data;
4548 struct intel_engine_cs *engine;
4549 enum intel_engine_id id;
4552 for_each_engine(engine, i915, id) {
4553 err = engine->init_hw(engine);
4561 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4565 dev_priv->gt.last_init_time = ktime_get();
4567 /* Double layer security blanket, see i915_gem_init() */
4568 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4570 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4571 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4573 if (IS_HASWELL(dev_priv))
4574 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4575 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4577 if (HAS_PCH_NOP(dev_priv)) {
4578 if (IS_IVYBRIDGE(dev_priv)) {
4579 u32 temp = I915_READ(GEN7_MSG_CTL);
4580 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4581 I915_WRITE(GEN7_MSG_CTL, temp);
4582 } else if (INTEL_GEN(dev_priv) >= 7) {
4583 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4584 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4585 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4589 i915_gem_init_swizzling(dev_priv);
4592 * At least 830 can leave some of the unused rings
4593 * "active" (ie. head != tail) after resume which
4594 * will prevent c3 entry. Makes sure all unused rings
4597 init_unused_rings(dev_priv);
4599 BUG_ON(!dev_priv->kernel_context);
4601 ret = i915_ppgtt_init_hw(dev_priv);
4603 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4607 /* Need to do basic initialisation of all rings first: */
4608 ret = __i915_gem_restart_engines(dev_priv);
4612 intel_mocs_init_l3cc_table(dev_priv);
4614 if (i915.enable_guc_loading) {
4615 /* We can't enable contexts until all firmware is loaded */
4616 ret = intel_uc_init_hw(dev_priv);
4622 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4626 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4628 if (INTEL_INFO(dev_priv)->gen < 6)
4631 /* TODO: make semaphores and Execlists play nicely together */
4632 if (i915.enable_execlists)
4638 #ifdef CONFIG_INTEL_IOMMU
4639 /* Enable semaphores on SNB when IO remapping is off */
4640 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4647 int i915_gem_init(struct drm_i915_private *dev_priv)
4651 mutex_lock(&dev_priv->drm.struct_mutex);
4653 i915_gem_clflush_init(dev_priv);
4655 if (!i915.enable_execlists) {
4656 dev_priv->gt.resume = intel_legacy_submission_resume;
4657 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4659 dev_priv->gt.resume = intel_lr_context_resume;
4660 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4663 /* This is just a security blanket to placate dragons.
4664 * On some systems, we very sporadically observe that the first TLBs
4665 * used by the CS may be stale, despite us poking the TLB reset. If
4666 * we hold the forcewake during initialisation these problems
4667 * just magically go away.
4669 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4671 i915_gem_init_userptr(dev_priv);
4673 ret = i915_gem_init_ggtt(dev_priv);
4677 ret = i915_gem_context_init(dev_priv);
4681 ret = intel_engines_init(dev_priv);
4685 ret = i915_gem_init_hw(dev_priv);
4687 /* Allow engine initialisation to fail by marking the GPU as
4688 * wedged. But we only want to do this where the GPU is angry,
4689 * for all other failure, such as an allocation failure, bail.
4691 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4692 i915_gem_set_wedged(dev_priv);
4697 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4698 mutex_unlock(&dev_priv->drm.struct_mutex);
4703 void i915_gem_init_mmio(struct drm_i915_private *i915)
4705 i915_gem_sanitize(i915);
4709 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4711 struct intel_engine_cs *engine;
4712 enum intel_engine_id id;
4714 for_each_engine(engine, dev_priv, id)
4715 dev_priv->gt.cleanup_engine(engine);
4719 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4723 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4724 !IS_CHERRYVIEW(dev_priv))
4725 dev_priv->num_fence_regs = 32;
4726 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4727 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4728 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4729 dev_priv->num_fence_regs = 16;
4731 dev_priv->num_fence_regs = 8;
4733 if (intel_vgpu_active(dev_priv))
4734 dev_priv->num_fence_regs =
4735 I915_READ(vgtif_reg(avail_rs.fence_num));
4737 /* Initialize fence registers to zero */
4738 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4739 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4741 fence->i915 = dev_priv;
4743 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4745 i915_gem_restore_fences(dev_priv);
4747 i915_gem_detect_bit_6_swizzle(dev_priv);
4751 i915_gem_load_init(struct drm_i915_private *dev_priv)
4755 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4756 if (!dev_priv->objects)
4759 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4760 if (!dev_priv->vmas)
4763 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4764 SLAB_HWCACHE_ALIGN |
4765 SLAB_RECLAIM_ACCOUNT |
4766 SLAB_DESTROY_BY_RCU);
4767 if (!dev_priv->requests)
4770 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4771 SLAB_HWCACHE_ALIGN |
4772 SLAB_RECLAIM_ACCOUNT);
4773 if (!dev_priv->dependencies)
4776 mutex_lock(&dev_priv->drm.struct_mutex);
4777 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4778 err = i915_gem_timeline_init__global(dev_priv);
4779 mutex_unlock(&dev_priv->drm.struct_mutex);
4781 goto err_dependencies;
4783 INIT_LIST_HEAD(&dev_priv->context_list);
4784 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4785 init_llist_head(&dev_priv->mm.free_list);
4786 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4787 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4788 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4789 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4790 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4791 i915_gem_retire_work_handler);
4792 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4793 i915_gem_idle_work_handler);
4794 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4795 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4797 init_waitqueue_head(&dev_priv->pending_flip_queue);
4799 dev_priv->mm.interruptible = true;
4801 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4803 spin_lock_init(&dev_priv->fb_tracking.lock);
4808 kmem_cache_destroy(dev_priv->dependencies);
4810 kmem_cache_destroy(dev_priv->requests);
4812 kmem_cache_destroy(dev_priv->vmas);
4814 kmem_cache_destroy(dev_priv->objects);
4819 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4821 i915_gem_drain_freed_objects(dev_priv);
4822 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4823 WARN_ON(dev_priv->mm.object_count);
4825 mutex_lock(&dev_priv->drm.struct_mutex);
4826 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4827 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4828 mutex_unlock(&dev_priv->drm.struct_mutex);
4830 kmem_cache_destroy(dev_priv->dependencies);
4831 kmem_cache_destroy(dev_priv->requests);
4832 kmem_cache_destroy(dev_priv->vmas);
4833 kmem_cache_destroy(dev_priv->objects);
4835 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4839 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4841 mutex_lock(&dev_priv->drm.struct_mutex);
4842 i915_gem_shrink_all(dev_priv);
4843 mutex_unlock(&dev_priv->drm.struct_mutex);
4848 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4850 struct drm_i915_gem_object *obj;
4851 struct list_head *phases[] = {
4852 &dev_priv->mm.unbound_list,
4853 &dev_priv->mm.bound_list,
4857 /* Called just before we write the hibernation image.
4859 * We need to update the domain tracking to reflect that the CPU
4860 * will be accessing all the pages to create and restore from the
4861 * hibernation, and so upon restoration those pages will be in the
4864 * To make sure the hibernation image contains the latest state,
4865 * we update that state just before writing out the image.
4867 * To try and reduce the hibernation image, we manually shrink
4868 * the objects as well.
4871 mutex_lock(&dev_priv->drm.struct_mutex);
4872 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4874 for (p = phases; *p; p++) {
4875 list_for_each_entry(obj, *p, global_link) {
4876 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4877 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4880 mutex_unlock(&dev_priv->drm.struct_mutex);
4885 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4887 struct drm_i915_file_private *file_priv = file->driver_priv;
4888 struct drm_i915_gem_request *request;
4890 /* Clean up our request list when the client is going away, so that
4891 * later retire_requests won't dereference our soon-to-be-gone
4894 spin_lock(&file_priv->mm.lock);
4895 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
4896 request->file_priv = NULL;
4897 spin_unlock(&file_priv->mm.lock);
4899 if (!list_empty(&file_priv->rps.link)) {
4900 spin_lock(&to_i915(dev)->rps.client_lock);
4901 list_del(&file_priv->rps.link);
4902 spin_unlock(&to_i915(dev)->rps.client_lock);
4906 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4908 struct drm_i915_file_private *file_priv;
4913 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4917 file->driver_priv = file_priv;
4918 file_priv->dev_priv = to_i915(dev);
4919 file_priv->file = file;
4920 INIT_LIST_HEAD(&file_priv->rps.link);
4922 spin_lock_init(&file_priv->mm.lock);
4923 INIT_LIST_HEAD(&file_priv->mm.request_list);
4925 file_priv->bsd_engine = -1;
4927 ret = i915_gem_context_open(dev, file);
4935 * i915_gem_track_fb - update frontbuffer tracking
4936 * @old: current GEM buffer for the frontbuffer slots
4937 * @new: new GEM buffer for the frontbuffer slots
4938 * @frontbuffer_bits: bitmask of frontbuffer slots
4940 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4941 * from @old and setting them in @new. Both @old and @new can be NULL.
4943 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4944 struct drm_i915_gem_object *new,
4945 unsigned frontbuffer_bits)
4947 /* Control of individual bits within the mask are guarded by
4948 * the owning plane->mutex, i.e. we can never see concurrent
4949 * manipulation of individual bits. But since the bitfield as a whole
4950 * is updated using RMW, we need to use atomics in order to update
4953 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4954 sizeof(atomic_t) * BITS_PER_BYTE);
4957 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4958 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4962 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4963 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4967 /* Allocate a new GEM object and fill it with the supplied data */
4968 struct drm_i915_gem_object *
4969 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
4970 const void *data, size_t size)
4972 struct drm_i915_gem_object *obj;
4977 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
4981 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
4983 file = obj->base.filp;
4986 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
4988 void *pgdata, *vaddr;
4990 err = pagecache_write_begin(file, file->f_mapping,
4997 memcpy(vaddr, data, len);
5000 err = pagecache_write_end(file, file->f_mapping,
5014 i915_gem_object_put(obj);
5015 return ERR_PTR(err);
5018 struct scatterlist *
5019 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5021 unsigned int *offset)
5023 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5024 struct scatterlist *sg;
5025 unsigned int idx, count;
5028 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5029 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5031 /* As we iterate forward through the sg, we record each entry in a
5032 * radixtree for quick repeated (backwards) lookups. If we have seen
5033 * this index previously, we will have an entry for it.
5035 * Initial lookup is O(N), but this is amortized to O(1) for
5036 * sequential page access (where each new request is consecutive
5037 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5038 * i.e. O(1) with a large constant!
5040 if (n < READ_ONCE(iter->sg_idx))
5043 mutex_lock(&iter->lock);
5045 /* We prefer to reuse the last sg so that repeated lookup of this
5046 * (or the subsequent) sg are fast - comparing against the last
5047 * sg is faster than going through the radixtree.
5052 count = __sg_page_count(sg);
5054 while (idx + count <= n) {
5055 unsigned long exception, i;
5058 /* If we cannot allocate and insert this entry, or the
5059 * individual pages from this range, cancel updating the
5060 * sg_idx so that on this lookup we are forced to linearly
5061 * scan onwards, but on future lookups we will try the
5062 * insertion again (in which case we need to be careful of
5063 * the error return reporting that we have already inserted
5066 ret = radix_tree_insert(&iter->radix, idx, sg);
5067 if (ret && ret != -EEXIST)
5071 RADIX_TREE_EXCEPTIONAL_ENTRY |
5072 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5073 for (i = 1; i < count; i++) {
5074 ret = radix_tree_insert(&iter->radix, idx + i,
5076 if (ret && ret != -EEXIST)
5081 sg = ____sg_next(sg);
5082 count = __sg_page_count(sg);
5089 mutex_unlock(&iter->lock);
5091 if (unlikely(n < idx)) /* insertion completed by another thread */
5094 /* In case we failed to insert the entry into the radixtree, we need
5095 * to look beyond the current sg.
5097 while (idx + count <= n) {
5099 sg = ____sg_next(sg);
5100 count = __sg_page_count(sg);
5109 sg = radix_tree_lookup(&iter->radix, n);
5112 /* If this index is in the middle of multi-page sg entry,
5113 * the radixtree will contain an exceptional entry that points
5114 * to the start of that range. We will return the pointer to
5115 * the base page and the offset of this page within the
5119 if (unlikely(radix_tree_exception(sg))) {
5120 unsigned long base =
5121 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5123 sg = radix_tree_lookup(&iter->radix, base);
5135 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5137 struct scatterlist *sg;
5138 unsigned int offset;
5140 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5142 sg = i915_gem_object_get_sg(obj, n, &offset);
5143 return nth_page(sg_page(sg), offset);
5146 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5148 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5153 page = i915_gem_object_get_page(obj, n);
5155 set_page_dirty(page);
5161 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5164 struct scatterlist *sg;
5165 unsigned int offset;
5167 sg = i915_gem_object_get_sg(obj, n, &offset);
5168 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5171 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5172 #include "selftests/scatterlist.c"
5173 #include "selftests/mock_gem_device.c"
5174 #include "selftests/huge_gem_object.c"
5175 #include "selftests/i915_gem_object.c"
5176 #include "selftests/i915_gem_coherency.c"