2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
50 static bool cpu_cache_is_coherent(struct drm_device *dev,
51 enum i915_cache_level level)
53 return HAS_LLC(dev) || level != I915_CACHE_NONE;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
58 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
61 return obj->pin_display;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
68 spin_lock(&dev_priv->mm.object_stat_lock);
69 dev_priv->mm.object_count++;
70 dev_priv->mm.object_memory += size;
71 spin_unlock(&dev_priv->mm.object_stat_lock);
74 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
77 spin_lock(&dev_priv->mm.object_stat_lock);
78 dev_priv->mm.object_count--;
79 dev_priv->mm.object_memory -= size;
80 spin_unlock(&dev_priv->mm.object_stat_lock);
84 i915_gem_wait_for_error(struct i915_gpu_error *error)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret = wait_event_interruptible_timeout(error->reset_queue,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret < 0) {
112 int i915_mutex_lock_interruptible(struct drm_device *dev)
114 struct drm_i915_private *dev_priv = dev->dev_private;
117 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
121 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 WARN_ON(i915_verify_lists(dev));
130 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
131 struct drm_file *file)
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 struct drm_i915_gem_get_aperture *args = data;
135 struct i915_gtt *ggtt = &dev_priv->gtt;
136 struct i915_vma *vma;
140 mutex_lock(&dev->struct_mutex);
141 list_for_each_entry(vma, &ggtt->base.active_list, mm_list)
143 pinned += vma->node.size;
144 list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list)
146 pinned += vma->node.size;
147 mutex_unlock(&dev->struct_mutex);
149 args->aper_size = dev_priv->gtt.base.total;
150 args->aper_available_size = args->aper_size - pinned;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
159 char *vaddr = obj->phys_handle->vaddr;
161 struct scatterlist *sg;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
171 page = shmem_read_mapping_page(mapping, i);
173 return PTR_ERR(page);
175 src = kmap_atomic(page);
176 memcpy(vaddr, src, PAGE_SIZE);
177 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 page_cache_release(page);
184 i915_gem_chipset_flush(obj->base.dev);
186 st = kmalloc(sizeof(*st), GFP_KERNEL);
190 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
197 sg->length = obj->base.size;
199 sg_dma_address(sg) = obj->phys_handle->busaddr;
200 sg_dma_len(sg) = obj->base.size;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
211 BUG_ON(obj->madv == __I915_MADV_PURGED);
213 ret = i915_gem_object_set_to_cpu_domain(obj, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret != -EIO);
219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
222 if (obj->madv == I915_MADV_DONTNEED)
226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
227 char *vaddr = obj->phys_handle->vaddr;
230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
234 page = shmem_read_mapping_page(mapping, i);
238 dst = kmap_atomic(page);
239 drm_clflush_virt_range(vaddr, PAGE_SIZE);
240 memcpy(dst, vaddr, PAGE_SIZE);
243 set_page_dirty(page);
244 if (obj->madv == I915_MADV_WILLNEED)
245 mark_page_accessed(page);
246 page_cache_release(page);
252 sg_free_table(obj->pages);
257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
259 drm_pci_free(obj->base.dev, obj->phys_handle);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
263 .get_pages = i915_gem_object_get_pages_phys,
264 .put_pages = i915_gem_object_put_pages_phys,
265 .release = i915_gem_object_release_phys,
269 drop_pages(struct drm_i915_gem_object *obj)
271 struct i915_vma *vma, *next;
274 drm_gem_object_reference(&obj->base);
275 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
276 if (i915_vma_unbind(vma))
279 ret = i915_gem_object_put_pages(obj);
280 drm_gem_object_unreference(&obj->base);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
289 drm_dma_handle_t *phys;
292 if (obj->phys_handle) {
293 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
299 if (obj->madv != I915_MADV_WILLNEED)
302 if (obj->base.filp == NULL)
305 ret = drop_pages(obj);
309 /* create a new object */
310 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
314 obj->phys_handle = phys;
315 obj->ops = &i915_gem_phys_ops;
317 return i915_gem_object_get_pages(obj);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
322 struct drm_i915_gem_pwrite *args,
323 struct drm_file *file_priv)
325 struct drm_device *dev = obj->base.dev;
326 void *vaddr = obj->phys_handle->vaddr + args->offset;
327 char __user *user_data = to_user_ptr(args->data_ptr);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret = i915_gem_object_wait_rendering(obj, false);
337 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
338 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
339 unsigned long unwritten;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev->struct_mutex);
346 unwritten = copy_from_user(vaddr, user_data, args->size);
347 mutex_lock(&dev->struct_mutex);
354 drm_clflush_virt_range(vaddr, args->size);
355 i915_gem_chipset_flush(dev);
358 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
362 void *i915_gem_object_alloc(struct drm_device *dev)
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
368 void i915_gem_object_free(struct drm_i915_gem_object *obj)
370 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
371 kmem_cache_free(dev_priv->objects, obj);
375 i915_gem_create(struct drm_file *file,
376 struct drm_device *dev,
380 struct drm_i915_gem_object *obj;
384 size = roundup(size, PAGE_SIZE);
388 /* Allocate the new object */
389 obj = i915_gem_alloc_object(dev, size);
393 ret = drm_gem_handle_create(file, &obj->base, &handle);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj->base);
404 i915_gem_dumb_create(struct drm_file *file,
405 struct drm_device *dev,
406 struct drm_mode_create_dumb *args)
408 /* have to work out size/pitch and return them */
409 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
410 args->size = args->pitch * args->height;
411 return i915_gem_create(file, dev,
412 args->size, &args->handle);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device *dev, void *data,
420 struct drm_file *file)
422 struct drm_i915_gem_create *args = data;
424 return i915_gem_create(file, dev,
425 args->size, &args->handle);
429 __copy_to_user_swizzled(char __user *cpu_vaddr,
430 const char *gpu_vaddr, int gpu_offset,
433 int ret, cpu_offset = 0;
436 int cacheline_end = ALIGN(gpu_offset + 1, 64);
437 int this_length = min(cacheline_end - gpu_offset, length);
438 int swizzled_gpu_offset = gpu_offset ^ 64;
440 ret = __copy_to_user(cpu_vaddr + cpu_offset,
441 gpu_vaddr + swizzled_gpu_offset,
446 cpu_offset += this_length;
447 gpu_offset += this_length;
448 length -= this_length;
455 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
456 const char __user *cpu_vaddr,
459 int ret, cpu_offset = 0;
462 int cacheline_end = ALIGN(gpu_offset + 1, 64);
463 int this_length = min(cacheline_end - gpu_offset, length);
464 int swizzled_gpu_offset = gpu_offset ^ 64;
466 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
467 cpu_vaddr + cpu_offset,
472 cpu_offset += this_length;
473 gpu_offset += this_length;
474 length -= this_length;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
495 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
502 ret = i915_gem_object_wait_rendering(obj, true);
507 ret = i915_gem_object_get_pages(obj);
511 i915_gem_object_pin_pages(obj);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
521 char __user *user_data,
522 bool page_do_bit17_swizzling, bool needs_clflush)
527 if (unlikely(page_do_bit17_swizzling))
530 vaddr = kmap_atomic(page);
532 drm_clflush_virt_range(vaddr + shmem_page_offset,
534 ret = __copy_to_user_inatomic(user_data,
535 vaddr + shmem_page_offset,
537 kunmap_atomic(vaddr);
539 return ret ? -EFAULT : 0;
543 shmem_clflush_swizzled_range(char *addr, unsigned long length,
546 if (unlikely(swizzled)) {
547 unsigned long start = (unsigned long) addr;
548 unsigned long end = (unsigned long) addr + length;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start = round_down(start, 128);
555 end = round_up(end, 128);
557 drm_clflush_virt_range((void *)start, end - start);
559 drm_clflush_virt_range(addr, length);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
568 char __user *user_data,
569 bool page_do_bit17_swizzling, bool needs_clflush)
576 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
578 page_do_bit17_swizzling);
580 if (page_do_bit17_swizzling)
581 ret = __copy_to_user_swizzled(user_data,
582 vaddr, shmem_page_offset,
585 ret = __copy_to_user(user_data,
586 vaddr + shmem_page_offset,
590 return ret ? - EFAULT : 0;
594 i915_gem_shmem_pread(struct drm_device *dev,
595 struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pread *args,
597 struct drm_file *file)
599 char __user *user_data;
602 int shmem_page_offset, page_length, ret = 0;
603 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
605 int needs_clflush = 0;
606 struct sg_page_iter sg_iter;
608 user_data = to_user_ptr(args->data_ptr);
611 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
613 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
617 offset = args->offset;
619 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
620 offset >> PAGE_SHIFT) {
621 struct page *page = sg_page_iter_page(&sg_iter);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((shmem_page_offset + page_length) > PAGE_SIZE)
634 page_length = PAGE_SIZE - shmem_page_offset;
636 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
637 (page_to_phys(page) & (1 << 17)) != 0;
639 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
640 user_data, page_do_bit17_swizzling,
645 mutex_unlock(&dev->struct_mutex);
647 if (likely(!i915.prefault_disable) && !prefaulted) {
648 ret = fault_in_multipages_writeable(user_data, remain);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
661 mutex_lock(&dev->struct_mutex);
667 remain -= page_length;
668 user_data += page_length;
669 offset += page_length;
673 i915_gem_object_unpin_pages(obj);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
685 struct drm_file *file)
687 struct drm_i915_gem_pread *args = data;
688 struct drm_i915_gem_object *obj;
694 if (!access_ok(VERIFY_WRITE,
695 to_user_ptr(args->data_ptr),
699 ret = i915_mutex_lock_interruptible(dev);
703 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
704 if (&obj->base == NULL) {
709 /* Bounds check source. */
710 if (args->offset > obj->base.size ||
711 args->size > obj->base.size - args->offset) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj->base.filp) {
724 trace_i915_gem_object_pread(obj, args->offset, args->size);
726 ret = i915_gem_shmem_pread(dev, obj, args, file);
729 drm_gem_object_unreference(&obj->base);
731 mutex_unlock(&dev->struct_mutex);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping *mapping,
741 loff_t page_base, int page_offset,
742 char __user *user_data,
745 void __iomem *vaddr_atomic;
747 unsigned long unwritten;
749 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr = (void __force*)vaddr_atomic + page_offset;
752 unwritten = __copy_from_user_inatomic_nocache(vaddr,
754 io_mapping_unmap_atomic(vaddr_atomic);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
764 struct drm_i915_gem_object *obj,
765 struct drm_i915_gem_pwrite *args,
766 struct drm_file *file)
768 struct drm_i915_private *dev_priv = dev->dev_private;
770 loff_t offset, page_base;
771 char __user *user_data;
772 int page_offset, page_length, ret;
774 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
778 ret = i915_gem_object_set_to_gtt_domain(obj, true);
782 ret = i915_gem_object_put_fence(obj);
786 user_data = to_user_ptr(args->data_ptr);
789 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
791 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base = offset & PAGE_MASK;
801 page_offset = offset_in_page(offset);
802 page_length = remain;
803 if ((page_offset + remain) > PAGE_SIZE)
804 page_length = PAGE_SIZE - page_offset;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv->gtt.mappable, page_base,
811 page_offset, user_data, page_length)) {
816 remain -= page_length;
817 user_data += page_length;
818 offset += page_length;
822 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
824 i915_gem_object_ggtt_unpin(obj);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
835 char __user *user_data,
836 bool page_do_bit17_swizzling,
837 bool needs_clflush_before,
838 bool needs_clflush_after)
843 if (unlikely(page_do_bit17_swizzling))
846 vaddr = kmap_atomic(page);
847 if (needs_clflush_before)
848 drm_clflush_virt_range(vaddr + shmem_page_offset,
850 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
851 user_data, page_length);
852 if (needs_clflush_after)
853 drm_clflush_virt_range(vaddr + shmem_page_offset,
855 kunmap_atomic(vaddr);
857 return ret ? -EFAULT : 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
864 char __user *user_data,
865 bool page_do_bit17_swizzling,
866 bool needs_clflush_before,
867 bool needs_clflush_after)
873 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
874 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
876 page_do_bit17_swizzling);
877 if (page_do_bit17_swizzling)
878 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
882 ret = __copy_from_user(vaddr + shmem_page_offset,
885 if (needs_clflush_after)
886 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
888 page_do_bit17_swizzling);
891 return ret ? -EFAULT : 0;
895 i915_gem_shmem_pwrite(struct drm_device *dev,
896 struct drm_i915_gem_object *obj,
897 struct drm_i915_gem_pwrite *args,
898 struct drm_file *file)
902 char __user *user_data;
903 int shmem_page_offset, page_length, ret = 0;
904 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
905 int hit_slowpath = 0;
906 int needs_clflush_after = 0;
907 int needs_clflush_before = 0;
908 struct sg_page_iter sg_iter;
910 user_data = to_user_ptr(args->data_ptr);
913 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
915 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after = cpu_write_needs_clflush(obj);
921 ret = i915_gem_object_wait_rendering(obj, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
928 needs_clflush_before =
929 !cpu_cache_is_coherent(dev, obj->cache_level);
931 ret = i915_gem_object_get_pages(obj);
935 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
937 i915_gem_object_pin_pages(obj);
939 offset = args->offset;
942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
943 offset >> PAGE_SHIFT) {
944 struct page *page = sg_page_iter_page(&sg_iter);
945 int partial_cacheline_write;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset = offset_in_page(offset);
957 page_length = remain;
958 if ((shmem_page_offset + page_length) > PAGE_SIZE)
959 page_length = PAGE_SIZE - shmem_page_offset;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write = needs_clflush_before &&
965 ((shmem_page_offset | page_length)
966 & (boot_cpu_data.x86_clflush_size - 1));
968 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
969 (page_to_phys(page) & (1 << 17)) != 0;
971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
972 user_data, page_do_bit17_swizzling,
973 partial_cacheline_write,
974 needs_clflush_after);
979 mutex_unlock(&dev->struct_mutex);
980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
981 user_data, page_do_bit17_swizzling,
982 partial_cacheline_write,
983 needs_clflush_after);
985 mutex_lock(&dev->struct_mutex);
991 remain -= page_length;
992 user_data += page_length;
993 offset += page_length;
997 i915_gem_object_unpin_pages(obj);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after &&
1006 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1007 if (i915_gem_clflush_object(obj, obj->pin_display))
1008 needs_clflush_after = true;
1012 if (needs_clflush_after)
1013 i915_gem_chipset_flush(dev);
1015 obj->cache_dirty = true;
1017 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *file)
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_i915_gem_pwrite *args = data;
1032 struct drm_i915_gem_object *obj;
1035 if (args->size == 0)
1038 if (!access_ok(VERIFY_READ,
1039 to_user_ptr(args->data_ptr),
1043 if (likely(!i915.prefault_disable)) {
1044 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1050 intel_runtime_pm_get(dev_priv);
1052 ret = i915_mutex_lock_interruptible(dev);
1056 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1057 if (&obj->base == NULL) {
1062 /* Bounds check destination. */
1063 if (args->offset > obj->base.size ||
1064 args->size > obj->base.size - args->offset) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj->base.filp) {
1077 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj->tiling_mode == I915_TILING_NONE &&
1087 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1088 cpu_write_needs_clflush(obj)) {
1089 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret == -EFAULT || ret == -ENOSPC) {
1096 if (obj->phys_handle)
1097 ret = i915_gem_phys_pwrite(obj, args, file);
1099 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1103 drm_gem_object_unreference(&obj->base);
1105 mutex_unlock(&dev->struct_mutex);
1107 intel_runtime_pm_put(dev_priv);
1113 i915_gem_check_wedge(struct i915_gpu_error *error,
1116 if (i915_reset_in_progress(error)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error->reload_in_reset)
1138 static void fake_irq(unsigned long data)
1140 wake_up_process((struct task_struct *)data);
1143 static bool missed_irq(struct drm_i915_private *dev_priv,
1144 struct intel_engine_cs *ring)
1146 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1149 static int __i915_spin_request(struct drm_i915_gem_request *req)
1151 unsigned long timeout;
1153 if (i915_gem_request_get_ring(req)->irq_refcount)
1156 timeout = jiffies + 1;
1157 while (!need_resched()) {
1158 if (i915_gem_request_completed(req, true))
1161 if (time_after_eq(jiffies, timeout))
1164 cpu_relax_lowlatency();
1166 if (i915_gem_request_completed(req, false))
1173 * __i915_wait_request - wait until execution of request has finished
1175 * @reset_counter: reset sequence associated with the given request
1176 * @interruptible: do an interruptible wait (normally yes)
1177 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1179 * Note: It is of utmost importance that the passed in seqno and reset_counter
1180 * values have been read by the caller in an smp safe manner. Where read-side
1181 * locks are involved, it is sufficient to read the reset_counter before
1182 * unlocking the lock that protects the seqno. For lockless tricks, the
1183 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1186 * Returns 0 if the request was found within the alloted time. Else returns the
1187 * errno with remaining time filled in timeout argument.
1189 int __i915_wait_request(struct drm_i915_gem_request *req,
1190 unsigned reset_counter,
1193 struct intel_rps_client *rps)
1195 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1196 struct drm_device *dev = ring->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 const bool irq_test_in_progress =
1199 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1201 unsigned long timeout_expire;
1205 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1207 if (list_empty(&req->list))
1210 if (i915_gem_request_completed(req, true))
1213 timeout_expire = timeout ?
1214 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1216 if (INTEL_INFO(dev_priv)->gen >= 6)
1217 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1219 /* Record current time in case interrupted by signal, or wedged */
1220 trace_i915_gem_request_wait_begin(req);
1221 before = ktime_get_raw_ns();
1223 /* Optimistic spin for the next jiffie before touching IRQs */
1224 ret = __i915_spin_request(req);
1228 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1234 struct timer_list timer;
1236 prepare_to_wait(&ring->irq_queue, &wait,
1237 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1239 /* We need to check whether any gpu reset happened in between
1240 * the caller grabbing the seqno and now ... */
1241 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1242 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1243 * is truely gone. */
1244 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1250 if (i915_gem_request_completed(req, false)) {
1255 if (interruptible && signal_pending(current)) {
1260 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1265 timer.function = NULL;
1266 if (timeout || missed_irq(dev_priv, ring)) {
1267 unsigned long expire;
1269 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1270 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1271 mod_timer(&timer, expire);
1276 if (timer.function) {
1277 del_singleshot_timer_sync(&timer);
1278 destroy_timer_on_stack(&timer);
1281 if (!irq_test_in_progress)
1282 ring->irq_put(ring);
1284 finish_wait(&ring->irq_queue, &wait);
1287 now = ktime_get_raw_ns();
1288 trace_i915_gem_request_wait_end(req);
1291 s64 tres = *timeout - (now - before);
1293 *timeout = tres < 0 ? 0 : tres;
1296 * Apparently ktime isn't accurate enough and occasionally has a
1297 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1298 * things up to make the test happy. We allow up to 1 jiffy.
1300 * This is a regrssion from the timespec->ktime conversion.
1302 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1309 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1310 struct drm_file *file)
1312 struct drm_i915_private *dev_private;
1313 struct drm_i915_file_private *file_priv;
1315 WARN_ON(!req || !file || req->file_priv);
1323 dev_private = req->ring->dev->dev_private;
1324 file_priv = file->driver_priv;
1326 spin_lock(&file_priv->mm.lock);
1327 req->file_priv = file_priv;
1328 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1329 spin_unlock(&file_priv->mm.lock);
1331 req->pid = get_pid(task_pid(current));
1337 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1339 struct drm_i915_file_private *file_priv = request->file_priv;
1344 spin_lock(&file_priv->mm.lock);
1345 list_del(&request->client_list);
1346 request->file_priv = NULL;
1347 spin_unlock(&file_priv->mm.lock);
1349 put_pid(request->pid);
1350 request->pid = NULL;
1353 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1355 trace_i915_gem_request_retire(request);
1357 /* We know the GPU must have read the request to have
1358 * sent us the seqno + interrupt, so use the position
1359 * of tail of the request to update the last known position
1362 * Note this requires that we are always called in request
1365 request->ringbuf->last_retired_head = request->postfix;
1367 list_del_init(&request->list);
1368 i915_gem_request_remove_from_client(request);
1370 i915_gem_request_unreference(request);
1374 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1376 struct intel_engine_cs *engine = req->ring;
1377 struct drm_i915_gem_request *tmp;
1379 lockdep_assert_held(&engine->dev->struct_mutex);
1381 if (list_empty(&req->list))
1385 tmp = list_first_entry(&engine->request_list,
1386 typeof(*tmp), list);
1388 i915_gem_request_retire(tmp);
1389 } while (tmp != req);
1391 WARN_ON(i915_verify_lists(engine->dev));
1395 * Waits for a request to be signaled, and cleans up the
1396 * request and object lists appropriately for that event.
1399 i915_wait_request(struct drm_i915_gem_request *req)
1401 struct drm_device *dev;
1402 struct drm_i915_private *dev_priv;
1406 BUG_ON(req == NULL);
1408 dev = req->ring->dev;
1409 dev_priv = dev->dev_private;
1410 interruptible = dev_priv->mm.interruptible;
1412 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1414 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1418 ret = __i915_wait_request(req,
1419 atomic_read(&dev_priv->gpu_error.reset_counter),
1420 interruptible, NULL, NULL);
1424 __i915_gem_request_retire__upto(req);
1429 * Ensures that all rendering to the object has completed and the object is
1430 * safe to unbind from the GTT or access from the CPU.
1433 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1442 if (obj->last_write_req != NULL) {
1443 ret = i915_wait_request(obj->last_write_req);
1447 i = obj->last_write_req->ring->id;
1448 if (obj->last_read_req[i] == obj->last_write_req)
1449 i915_gem_object_retire__read(obj, i);
1451 i915_gem_object_retire__write(obj);
1454 for (i = 0; i < I915_NUM_RINGS; i++) {
1455 if (obj->last_read_req[i] == NULL)
1458 ret = i915_wait_request(obj->last_read_req[i]);
1462 i915_gem_object_retire__read(obj, i);
1464 RQ_BUG_ON(obj->active);
1471 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1472 struct drm_i915_gem_request *req)
1474 int ring = req->ring->id;
1476 if (obj->last_read_req[ring] == req)
1477 i915_gem_object_retire__read(obj, ring);
1478 else if (obj->last_write_req == req)
1479 i915_gem_object_retire__write(obj);
1481 __i915_gem_request_retire__upto(req);
1484 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1485 * as the object state may change during this call.
1487 static __must_check int
1488 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1489 struct intel_rps_client *rps,
1492 struct drm_device *dev = obj->base.dev;
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1495 unsigned reset_counter;
1498 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1499 BUG_ON(!dev_priv->mm.interruptible);
1504 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1508 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1511 struct drm_i915_gem_request *req;
1513 req = obj->last_write_req;
1517 requests[n++] = i915_gem_request_reference(req);
1519 for (i = 0; i < I915_NUM_RINGS; i++) {
1520 struct drm_i915_gem_request *req;
1522 req = obj->last_read_req[i];
1526 requests[n++] = i915_gem_request_reference(req);
1530 mutex_unlock(&dev->struct_mutex);
1531 for (i = 0; ret == 0 && i < n; i++)
1532 ret = __i915_wait_request(requests[i], reset_counter, true,
1534 mutex_lock(&dev->struct_mutex);
1536 for (i = 0; i < n; i++) {
1538 i915_gem_object_retire_request(obj, requests[i]);
1539 i915_gem_request_unreference(requests[i]);
1545 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1547 struct drm_i915_file_private *fpriv = file->driver_priv;
1552 * Called when user space prepares to use an object with the CPU, either
1553 * through the mmap ioctl's mapping or a GTT mapping.
1556 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1557 struct drm_file *file)
1559 struct drm_i915_gem_set_domain *args = data;
1560 struct drm_i915_gem_object *obj;
1561 uint32_t read_domains = args->read_domains;
1562 uint32_t write_domain = args->write_domain;
1565 /* Only handle setting domains to types used by the CPU. */
1566 if (write_domain & I915_GEM_GPU_DOMAINS)
1569 if (read_domains & I915_GEM_GPU_DOMAINS)
1572 /* Having something in the write domain implies it's in the read
1573 * domain, and only that read domain. Enforce that in the request.
1575 if (write_domain != 0 && read_domains != write_domain)
1578 ret = i915_mutex_lock_interruptible(dev);
1582 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1583 if (&obj->base == NULL) {
1588 /* Try to flush the object off the GPU without holding the lock.
1589 * We will repeat the flush holding the lock in the normal manner
1590 * to catch cases where we are gazumped.
1592 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1593 to_rps_client(file),
1598 if (read_domains & I915_GEM_DOMAIN_GTT)
1599 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1601 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1603 if (write_domain != 0)
1604 intel_fb_obj_invalidate(obj,
1605 write_domain == I915_GEM_DOMAIN_GTT ?
1606 ORIGIN_GTT : ORIGIN_CPU);
1609 drm_gem_object_unreference(&obj->base);
1611 mutex_unlock(&dev->struct_mutex);
1616 * Called when user space has done writes to this buffer
1619 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1620 struct drm_file *file)
1622 struct drm_i915_gem_sw_finish *args = data;
1623 struct drm_i915_gem_object *obj;
1626 ret = i915_mutex_lock_interruptible(dev);
1630 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1631 if (&obj->base == NULL) {
1636 /* Pinned buffers may be scanout, so flush the cache */
1637 if (obj->pin_display)
1638 i915_gem_object_flush_cpu_write_domain(obj);
1640 drm_gem_object_unreference(&obj->base);
1642 mutex_unlock(&dev->struct_mutex);
1647 * Maps the contents of an object, returning the address it is mapped
1650 * While the mapping holds a reference on the contents of the object, it doesn't
1651 * imply a ref on the object itself.
1655 * DRM driver writers who look a this function as an example for how to do GEM
1656 * mmap support, please don't implement mmap support like here. The modern way
1657 * to implement DRM mmap support is with an mmap offset ioctl (like
1658 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1659 * That way debug tooling like valgrind will understand what's going on, hiding
1660 * the mmap call in a driver private ioctl will break that. The i915 driver only
1661 * does cpu mmaps this way because we didn't know better.
1664 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1665 struct drm_file *file)
1667 struct drm_i915_gem_mmap *args = data;
1668 struct drm_gem_object *obj;
1671 if (args->flags & ~(I915_MMAP_WC))
1674 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1677 obj = drm_gem_object_lookup(dev, file, args->handle);
1681 /* prime objects have no backing filp to GEM mmap
1685 drm_gem_object_unreference_unlocked(obj);
1689 addr = vm_mmap(obj->filp, 0, args->size,
1690 PROT_READ | PROT_WRITE, MAP_SHARED,
1692 if (args->flags & I915_MMAP_WC) {
1693 struct mm_struct *mm = current->mm;
1694 struct vm_area_struct *vma;
1696 down_write(&mm->mmap_sem);
1697 vma = find_vma(mm, addr);
1700 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1703 up_write(&mm->mmap_sem);
1705 drm_gem_object_unreference_unlocked(obj);
1706 if (IS_ERR((void *)addr))
1709 args->addr_ptr = (uint64_t) addr;
1715 * i915_gem_fault - fault a page into the GTT
1716 * @vma: VMA in question
1719 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1720 * from userspace. The fault handler takes care of binding the object to
1721 * the GTT (if needed), allocating and programming a fence register (again,
1722 * only if needed based on whether the old reg is still valid or the object
1723 * is tiled) and inserting a new PTE into the faulting process.
1725 * Note that the faulting process may involve evicting existing objects
1726 * from the GTT and/or fence registers to make room. So performance may
1727 * suffer if the GTT working set is large or there are few fence registers
1730 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1732 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1733 struct drm_device *dev = obj->base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 struct i915_ggtt_view view = i915_ggtt_view_normal;
1736 pgoff_t page_offset;
1739 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1741 intel_runtime_pm_get(dev_priv);
1743 /* We don't use vmf->pgoff since that has the fake offset */
1744 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1747 ret = i915_mutex_lock_interruptible(dev);
1751 trace_i915_gem_object_fault(obj, page_offset, true, write);
1753 /* Try to flush the object off the GPU first without holding the lock.
1754 * Upon reacquiring the lock, we will perform our sanity checks and then
1755 * repeat the flush holding the lock in the normal manner to catch cases
1756 * where we are gazumped.
1758 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1762 /* Access to snoopable pages through the GTT is incoherent. */
1763 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1768 /* Use a partial view if the object is bigger than the aperture. */
1769 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1770 obj->tiling_mode == I915_TILING_NONE) {
1771 static const unsigned int chunk_size = 256; // 1 MiB
1773 memset(&view, 0, sizeof(view));
1774 view.type = I915_GGTT_VIEW_PARTIAL;
1775 view.params.partial.offset = rounddown(page_offset, chunk_size);
1776 view.params.partial.size =
1779 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1780 view.params.partial.offset);
1783 /* Now pin it into the GTT if needed */
1784 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1788 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1792 ret = i915_gem_object_get_fence(obj);
1796 /* Finally, remap it using the new GTT offset */
1797 pfn = dev_priv->gtt.mappable_base +
1798 i915_gem_obj_ggtt_offset_view(obj, &view);
1801 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1802 /* Overriding existing pages in partial view does not cause
1803 * us any trouble as TLBs are still valid because the fault
1804 * is due to userspace losing part of the mapping or never
1805 * having accessed it before (at this partials' range).
1807 unsigned long base = vma->vm_start +
1808 (view.params.partial.offset << PAGE_SHIFT);
1811 for (i = 0; i < view.params.partial.size; i++) {
1812 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1817 obj->fault_mappable = true;
1819 if (!obj->fault_mappable) {
1820 unsigned long size = min_t(unsigned long,
1821 vma->vm_end - vma->vm_start,
1825 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1826 ret = vm_insert_pfn(vma,
1827 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1833 obj->fault_mappable = true;
1835 ret = vm_insert_pfn(vma,
1836 (unsigned long)vmf->virtual_address,
1840 i915_gem_object_ggtt_unpin_view(obj, &view);
1842 mutex_unlock(&dev->struct_mutex);
1847 * We eat errors when the gpu is terminally wedged to avoid
1848 * userspace unduly crashing (gl has no provisions for mmaps to
1849 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1850 * and so needs to be reported.
1852 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1853 ret = VM_FAULT_SIGBUS;
1858 * EAGAIN means the gpu is hung and we'll wait for the error
1859 * handler to reset everything when re-faulting in
1860 * i915_mutex_lock_interruptible.
1867 * EBUSY is ok: this just means that another thread
1868 * already did the job.
1870 ret = VM_FAULT_NOPAGE;
1877 ret = VM_FAULT_SIGBUS;
1880 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1881 ret = VM_FAULT_SIGBUS;
1885 intel_runtime_pm_put(dev_priv);
1890 * i915_gem_release_mmap - remove physical page mappings
1891 * @obj: obj in question
1893 * Preserve the reservation of the mmapping with the DRM core code, but
1894 * relinquish ownership of the pages back to the system.
1896 * It is vital that we remove the page mapping if we have mapped a tiled
1897 * object through the GTT and then lose the fence register due to
1898 * resource pressure. Similarly if the object has been moved out of the
1899 * aperture, than pages mapped into userspace must be revoked. Removing the
1900 * mapping will then trigger a page fault on the next user access, allowing
1901 * fixup by i915_gem_fault().
1904 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1906 if (!obj->fault_mappable)
1909 drm_vma_node_unmap(&obj->base.vma_node,
1910 obj->base.dev->anon_inode->i_mapping);
1911 obj->fault_mappable = false;
1915 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1917 struct drm_i915_gem_object *obj;
1919 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1920 i915_gem_release_mmap(obj);
1924 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1928 if (INTEL_INFO(dev)->gen >= 4 ||
1929 tiling_mode == I915_TILING_NONE)
1932 /* Previous chips need a power-of-two fence region when tiling */
1933 if (INTEL_INFO(dev)->gen == 3)
1934 gtt_size = 1024*1024;
1936 gtt_size = 512*1024;
1938 while (gtt_size < size)
1945 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1946 * @obj: object to check
1948 * Return the required GTT alignment for an object, taking into account
1949 * potential fence register mapping.
1952 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1953 int tiling_mode, bool fenced)
1956 * Minimum alignment is 4k (GTT page size), but might be greater
1957 * if a fence register is needed for the object.
1959 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1960 tiling_mode == I915_TILING_NONE)
1964 * Previous chips need to be aligned to the size of the smallest
1965 * fence register that can contain the object.
1967 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1970 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1972 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1975 if (drm_vma_node_has_offset(&obj->base.vma_node))
1978 dev_priv->mm.shrinker_no_lock_stealing = true;
1980 ret = drm_gem_create_mmap_offset(&obj->base);
1984 /* Badly fragmented mmap space? The only way we can recover
1985 * space is by destroying unwanted objects. We can't randomly release
1986 * mmap_offsets as userspace expects them to be persistent for the
1987 * lifetime of the objects. The closest we can is to release the
1988 * offsets on purgeable objects by truncating it and marking it purged,
1989 * which prevents userspace from ever using that object again.
1991 i915_gem_shrink(dev_priv,
1992 obj->base.size >> PAGE_SHIFT,
1994 I915_SHRINK_UNBOUND |
1995 I915_SHRINK_PURGEABLE);
1996 ret = drm_gem_create_mmap_offset(&obj->base);
2000 i915_gem_shrink_all(dev_priv);
2001 ret = drm_gem_create_mmap_offset(&obj->base);
2003 dev_priv->mm.shrinker_no_lock_stealing = false;
2008 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2010 drm_gem_free_mmap_offset(&obj->base);
2014 i915_gem_mmap_gtt(struct drm_file *file,
2015 struct drm_device *dev,
2019 struct drm_i915_gem_object *obj;
2022 ret = i915_mutex_lock_interruptible(dev);
2026 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2027 if (&obj->base == NULL) {
2032 if (obj->madv != I915_MADV_WILLNEED) {
2033 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2038 ret = i915_gem_object_create_mmap_offset(obj);
2042 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2045 drm_gem_object_unreference(&obj->base);
2047 mutex_unlock(&dev->struct_mutex);
2052 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2054 * @data: GTT mapping ioctl data
2055 * @file: GEM object info
2057 * Simply returns the fake offset to userspace so it can mmap it.
2058 * The mmap call will end up in drm_gem_mmap(), which will set things
2059 * up so we can get faults in the handler above.
2061 * The fault handler will take care of binding the object into the GTT
2062 * (since it may have been evicted to make room for something), allocating
2063 * a fence register, and mapping the appropriate aperture address into
2067 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2068 struct drm_file *file)
2070 struct drm_i915_gem_mmap_gtt *args = data;
2072 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2075 /* Immediately discard the backing storage */
2077 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2079 i915_gem_object_free_mmap_offset(obj);
2081 if (obj->base.filp == NULL)
2084 /* Our goal here is to return as much of the memory as
2085 * is possible back to the system as we are called from OOM.
2086 * To do this we must instruct the shmfs to drop all of its
2087 * backing pages, *now*.
2089 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2090 obj->madv = __I915_MADV_PURGED;
2093 /* Try to discard unwanted pages */
2095 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2097 struct address_space *mapping;
2099 switch (obj->madv) {
2100 case I915_MADV_DONTNEED:
2101 i915_gem_object_truncate(obj);
2102 case __I915_MADV_PURGED:
2106 if (obj->base.filp == NULL)
2109 mapping = file_inode(obj->base.filp)->i_mapping,
2110 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2114 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2116 struct sg_page_iter sg_iter;
2119 BUG_ON(obj->madv == __I915_MADV_PURGED);
2121 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2123 /* In the event of a disaster, abandon all caches and
2124 * hope for the best.
2126 WARN_ON(ret != -EIO);
2127 i915_gem_clflush_object(obj, true);
2128 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2131 i915_gem_gtt_finish_object(obj);
2133 if (i915_gem_object_needs_bit17_swizzle(obj))
2134 i915_gem_object_save_bit_17_swizzle(obj);
2136 if (obj->madv == I915_MADV_DONTNEED)
2139 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2140 struct page *page = sg_page_iter_page(&sg_iter);
2143 set_page_dirty(page);
2145 if (obj->madv == I915_MADV_WILLNEED)
2146 mark_page_accessed(page);
2148 page_cache_release(page);
2152 sg_free_table(obj->pages);
2157 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2159 const struct drm_i915_gem_object_ops *ops = obj->ops;
2161 if (obj->pages == NULL)
2164 if (obj->pages_pin_count)
2167 BUG_ON(i915_gem_obj_bound_any(obj));
2169 /* ->put_pages might need to allocate memory for the bit17 swizzle
2170 * array, hence protect them from being reaped by removing them from gtt
2172 list_del(&obj->global_list);
2174 ops->put_pages(obj);
2177 i915_gem_object_invalidate(obj);
2183 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2185 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2187 struct address_space *mapping;
2188 struct sg_table *st;
2189 struct scatterlist *sg;
2190 struct sg_page_iter sg_iter;
2192 unsigned long last_pfn = 0; /* suppress gcc warning */
2196 /* Assert that the object is not currently in any GPU domain. As it
2197 * wasn't in the GTT, there shouldn't be any way it could have been in
2200 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2201 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2203 st = kmalloc(sizeof(*st), GFP_KERNEL);
2207 page_count = obj->base.size / PAGE_SIZE;
2208 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2213 /* Get the list of pages out of our struct file. They'll be pinned
2214 * at this point until we release them.
2216 * Fail silently without starting the shrinker
2218 mapping = file_inode(obj->base.filp)->i_mapping;
2219 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2220 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2223 for (i = 0; i < page_count; i++) {
2224 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2226 i915_gem_shrink(dev_priv,
2229 I915_SHRINK_UNBOUND |
2230 I915_SHRINK_PURGEABLE);
2231 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2234 /* We've tried hard to allocate the memory by reaping
2235 * our own buffer, now let the real VM do its job and
2236 * go down in flames if truly OOM.
2238 i915_gem_shrink_all(dev_priv);
2239 page = shmem_read_mapping_page(mapping, i);
2241 ret = PTR_ERR(page);
2245 #ifdef CONFIG_SWIOTLB
2246 if (swiotlb_nr_tbl()) {
2248 sg_set_page(sg, page, PAGE_SIZE, 0);
2253 if (!i || page_to_pfn(page) != last_pfn + 1) {
2257 sg_set_page(sg, page, PAGE_SIZE, 0);
2259 sg->length += PAGE_SIZE;
2261 last_pfn = page_to_pfn(page);
2263 /* Check that the i965g/gm workaround works. */
2264 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2266 #ifdef CONFIG_SWIOTLB
2267 if (!swiotlb_nr_tbl())
2272 ret = i915_gem_gtt_prepare_object(obj);
2276 if (i915_gem_object_needs_bit17_swizzle(obj))
2277 i915_gem_object_do_bit_17_swizzle(obj);
2279 if (obj->tiling_mode != I915_TILING_NONE &&
2280 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2281 i915_gem_object_pin_pages(obj);
2287 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2288 page_cache_release(sg_page_iter_page(&sg_iter));
2292 /* shmemfs first checks if there is enough memory to allocate the page
2293 * and reports ENOSPC should there be insufficient, along with the usual
2294 * ENOMEM for a genuine allocation failure.
2296 * We use ENOSPC in our driver to mean that we have run out of aperture
2297 * space and so want to translate the error from shmemfs back to our
2298 * usual understanding of ENOMEM.
2306 /* Ensure that the associated pages are gathered from the backing storage
2307 * and pinned into our object. i915_gem_object_get_pages() may be called
2308 * multiple times before they are released by a single call to
2309 * i915_gem_object_put_pages() - once the pages are no longer referenced
2310 * either as a result of memory pressure (reaping pages under the shrinker)
2311 * or as the object is itself released.
2314 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2316 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2317 const struct drm_i915_gem_object_ops *ops = obj->ops;
2323 if (obj->madv != I915_MADV_WILLNEED) {
2324 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2328 BUG_ON(obj->pages_pin_count);
2330 ret = ops->get_pages(obj);
2334 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2336 obj->get_page.sg = obj->pages->sgl;
2337 obj->get_page.last = 0;
2342 void i915_vma_move_to_active(struct i915_vma *vma,
2343 struct drm_i915_gem_request *req)
2345 struct drm_i915_gem_object *obj = vma->obj;
2346 struct intel_engine_cs *ring;
2348 ring = i915_gem_request_get_ring(req);
2350 /* Add a reference if we're newly entering the active list. */
2351 if (obj->active == 0)
2352 drm_gem_object_reference(&obj->base);
2353 obj->active |= intel_ring_flag(ring);
2355 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2356 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2358 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2362 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2364 RQ_BUG_ON(obj->last_write_req == NULL);
2365 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2367 i915_gem_request_assign(&obj->last_write_req, NULL);
2368 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2372 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2374 struct i915_vma *vma;
2376 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2377 RQ_BUG_ON(!(obj->active & (1 << ring)));
2379 list_del_init(&obj->ring_list[ring]);
2380 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2382 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2383 i915_gem_object_retire__write(obj);
2385 obj->active &= ~(1 << ring);
2389 /* Bump our place on the bound list to keep it roughly in LRU order
2390 * so that we don't steal from recently used but inactive objects
2391 * (unless we are forced to ofc!)
2393 list_move_tail(&obj->global_list,
2394 &to_i915(obj->base.dev)->mm.bound_list);
2396 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2397 if (!list_empty(&vma->mm_list))
2398 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2401 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2402 drm_gem_object_unreference(&obj->base);
2406 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_engine_cs *ring;
2412 /* Carefully retire all requests without writing to the rings */
2413 for_each_ring(ring, dev_priv, i) {
2414 ret = intel_ring_idle(ring);
2418 i915_gem_retire_requests(dev);
2420 /* Finally reset hw state */
2421 for_each_ring(ring, dev_priv, i) {
2422 intel_ring_init_seqno(ring, seqno);
2424 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2425 ring->semaphore.sync_seqno[j] = 0;
2431 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2439 /* HWS page needs to be set less than what we
2440 * will inject to ring
2442 ret = i915_gem_init_seqno(dev, seqno - 1);
2446 /* Carefully set the last_seqno value so that wrap
2447 * detection still works
2449 dev_priv->next_seqno = seqno;
2450 dev_priv->last_seqno = seqno - 1;
2451 if (dev_priv->last_seqno == 0)
2452 dev_priv->last_seqno--;
2458 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2462 /* reserve 0 for non-seqno */
2463 if (dev_priv->next_seqno == 0) {
2464 int ret = i915_gem_init_seqno(dev, 0);
2468 dev_priv->next_seqno = 1;
2471 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2476 * NB: This function is not allowed to fail. Doing so would mean the the
2477 * request is not being tracked for completion but the work itself is
2478 * going to happen on the hardware. This would be a Bad Thing(tm).
2480 void __i915_add_request(struct drm_i915_gem_request *request,
2481 struct drm_i915_gem_object *obj,
2484 struct intel_engine_cs *ring;
2485 struct drm_i915_private *dev_priv;
2486 struct intel_ringbuffer *ringbuf;
2490 if (WARN_ON(request == NULL))
2493 ring = request->ring;
2494 dev_priv = ring->dev->dev_private;
2495 ringbuf = request->ringbuf;
2498 * To ensure that this call will not fail, space for its emissions
2499 * should already have been reserved in the ring buffer. Let the ring
2500 * know that it is time to use that space up.
2502 intel_ring_reserved_space_use(ringbuf);
2504 request_start = intel_ring_get_tail(ringbuf);
2506 * Emit any outstanding flushes - execbuf can fail to emit the flush
2507 * after having emitted the batchbuffer command. Hence we need to fix
2508 * things up similar to emitting the lazy request. The difference here
2509 * is that the flush _must_ happen before the next request, no matter
2513 if (i915.enable_execlists)
2514 ret = logical_ring_flush_all_caches(request);
2516 ret = intel_ring_flush_all_caches(request);
2517 /* Not allowed to fail! */
2518 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2521 /* Record the position of the start of the request so that
2522 * should we detect the updated seqno part-way through the
2523 * GPU processing the request, we never over-estimate the
2524 * position of the head.
2526 request->postfix = intel_ring_get_tail(ringbuf);
2528 if (i915.enable_execlists)
2529 ret = ring->emit_request(request);
2531 ret = ring->add_request(request);
2533 request->tail = intel_ring_get_tail(ringbuf);
2535 /* Not allowed to fail! */
2536 WARN(ret, "emit|add_request failed: %d!\n", ret);
2538 request->head = request_start;
2540 /* Whilst this request exists, batch_obj will be on the
2541 * active_list, and so will hold the active reference. Only when this
2542 * request is retired will the the batch_obj be moved onto the
2543 * inactive_list and lose its active reference. Hence we do not need
2544 * to explicitly hold another reference here.
2546 request->batch_obj = obj;
2548 request->emitted_jiffies = jiffies;
2549 ring->last_submitted_seqno = request->seqno;
2550 list_add_tail(&request->list, &ring->request_list);
2552 trace_i915_gem_request_add(request);
2554 i915_queue_hangcheck(ring->dev);
2556 queue_delayed_work(dev_priv->wq,
2557 &dev_priv->mm.retire_work,
2558 round_jiffies_up_relative(HZ));
2559 intel_mark_busy(dev_priv->dev);
2561 /* Sanity check that the reserved size was large enough. */
2562 intel_ring_reserved_space_end(ringbuf);
2565 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2566 const struct intel_context *ctx)
2568 unsigned long elapsed;
2570 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2572 if (ctx->hang_stats.banned)
2575 if (ctx->hang_stats.ban_period_seconds &&
2576 elapsed <= ctx->hang_stats.ban_period_seconds) {
2577 if (!i915_gem_context_is_default(ctx)) {
2578 DRM_DEBUG("context hanging too fast, banning!\n");
2580 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2581 if (i915_stop_ring_allow_warn(dev_priv))
2582 DRM_ERROR("gpu hanging too fast, banning!\n");
2590 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2591 struct intel_context *ctx,
2594 struct i915_ctx_hang_stats *hs;
2599 hs = &ctx->hang_stats;
2602 hs->banned = i915_context_is_banned(dev_priv, ctx);
2604 hs->guilty_ts = get_seconds();
2606 hs->batch_pending++;
2610 void i915_gem_request_free(struct kref *req_ref)
2612 struct drm_i915_gem_request *req = container_of(req_ref,
2614 struct intel_context *ctx = req->ctx;
2617 i915_gem_request_remove_from_client(req);
2620 if (i915.enable_execlists) {
2621 if (ctx != req->ring->default_context)
2622 intel_lr_context_unpin(req);
2625 i915_gem_context_unreference(ctx);
2628 kmem_cache_free(req->i915->requests, req);
2631 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2632 struct intel_context *ctx,
2633 struct drm_i915_gem_request **req_out)
2635 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2636 struct drm_i915_gem_request *req;
2644 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2648 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2652 kref_init(&req->ref);
2653 req->i915 = dev_priv;
2656 i915_gem_context_reference(req->ctx);
2658 if (i915.enable_execlists)
2659 ret = intel_logical_ring_alloc_request_extras(req);
2661 ret = intel_ring_alloc_request_extras(req);
2663 i915_gem_context_unreference(req->ctx);
2668 * Reserve space in the ring buffer for all the commands required to
2669 * eventually emit this request. This is to guarantee that the
2670 * i915_add_request() call can't fail. Note that the reserve may need
2671 * to be redone if the request is not actually submitted straight
2672 * away, e.g. because a GPU scheduler has deferred it.
2674 if (i915.enable_execlists)
2675 ret = intel_logical_ring_reserve_space(req);
2677 ret = intel_ring_reserve_space(req);
2680 * At this point, the request is fully allocated even if not
2681 * fully prepared. Thus it can be cleaned up using the proper
2684 i915_gem_request_cancel(req);
2692 kmem_cache_free(dev_priv->requests, req);
2696 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2698 intel_ring_reserved_space_cancel(req->ringbuf);
2700 i915_gem_request_unreference(req);
2703 struct drm_i915_gem_request *
2704 i915_gem_find_active_request(struct intel_engine_cs *ring)
2706 struct drm_i915_gem_request *request;
2708 list_for_each_entry(request, &ring->request_list, list) {
2709 if (i915_gem_request_completed(request, false))
2718 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2719 struct intel_engine_cs *ring)
2721 struct drm_i915_gem_request *request;
2724 request = i915_gem_find_active_request(ring);
2726 if (request == NULL)
2729 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2731 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2733 list_for_each_entry_continue(request, &ring->request_list, list)
2734 i915_set_reset_status(dev_priv, request->ctx, false);
2737 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2738 struct intel_engine_cs *ring)
2740 struct intel_ringbuffer *buffer;
2742 while (!list_empty(&ring->active_list)) {
2743 struct drm_i915_gem_object *obj;
2745 obj = list_first_entry(&ring->active_list,
2746 struct drm_i915_gem_object,
2747 ring_list[ring->id]);
2749 i915_gem_object_retire__read(obj, ring->id);
2753 * Clear the execlists queue up before freeing the requests, as those
2754 * are the ones that keep the context and ringbuffer backing objects
2758 if (i915.enable_execlists) {
2759 spin_lock_irq(&ring->execlist_lock);
2760 while (!list_empty(&ring->execlist_queue)) {
2761 struct drm_i915_gem_request *submit_req;
2763 submit_req = list_first_entry(&ring->execlist_queue,
2764 struct drm_i915_gem_request,
2766 list_del(&submit_req->execlist_link);
2768 if (submit_req->ctx != ring->default_context)
2769 intel_lr_context_unpin(submit_req);
2771 i915_gem_request_unreference(submit_req);
2773 spin_unlock_irq(&ring->execlist_lock);
2777 * We must free the requests after all the corresponding objects have
2778 * been moved off active lists. Which is the same order as the normal
2779 * retire_requests function does. This is important if object hold
2780 * implicit references on things like e.g. ppgtt address spaces through
2783 while (!list_empty(&ring->request_list)) {
2784 struct drm_i915_gem_request *request;
2786 request = list_first_entry(&ring->request_list,
2787 struct drm_i915_gem_request,
2790 i915_gem_request_retire(request);
2793 /* Having flushed all requests from all queues, we know that all
2794 * ringbuffers must now be empty. However, since we do not reclaim
2795 * all space when retiring the request (to prevent HEADs colliding
2796 * with rapid ringbuffer wraparound) the amount of available space
2797 * upon reset is less than when we start. Do one more pass over
2798 * all the ringbuffers to reset last_retired_head.
2800 list_for_each_entry(buffer, &ring->buffers, link) {
2801 buffer->last_retired_head = buffer->tail;
2802 intel_ring_update_space(buffer);
2806 void i915_gem_reset(struct drm_device *dev)
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_engine_cs *ring;
2813 * Before we free the objects from the requests, we need to inspect
2814 * them for finding the guilty party. As the requests only borrow
2815 * their reference to the objects, the inspection must be done first.
2817 for_each_ring(ring, dev_priv, i)
2818 i915_gem_reset_ring_status(dev_priv, ring);
2820 for_each_ring(ring, dev_priv, i)
2821 i915_gem_reset_ring_cleanup(dev_priv, ring);
2823 i915_gem_context_reset(dev);
2825 i915_gem_restore_fences(dev);
2827 WARN_ON(i915_verify_lists(dev));
2831 * This function clears the request list as sequence numbers are passed.
2834 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2836 WARN_ON(i915_verify_lists(ring->dev));
2838 /* Retire requests first as we use it above for the early return.
2839 * If we retire requests last, we may use a later seqno and so clear
2840 * the requests lists without clearing the active list, leading to
2843 while (!list_empty(&ring->request_list)) {
2844 struct drm_i915_gem_request *request;
2846 request = list_first_entry(&ring->request_list,
2847 struct drm_i915_gem_request,
2850 if (!i915_gem_request_completed(request, true))
2853 i915_gem_request_retire(request);
2856 /* Move any buffers on the active list that are no longer referenced
2857 * by the ringbuffer to the flushing/inactive lists as appropriate,
2858 * before we free the context associated with the requests.
2860 while (!list_empty(&ring->active_list)) {
2861 struct drm_i915_gem_object *obj;
2863 obj = list_first_entry(&ring->active_list,
2864 struct drm_i915_gem_object,
2865 ring_list[ring->id]);
2867 if (!list_empty(&obj->last_read_req[ring->id]->list))
2870 i915_gem_object_retire__read(obj, ring->id);
2873 if (unlikely(ring->trace_irq_req &&
2874 i915_gem_request_completed(ring->trace_irq_req, true))) {
2875 ring->irq_put(ring);
2876 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2879 WARN_ON(i915_verify_lists(ring->dev));
2883 i915_gem_retire_requests(struct drm_device *dev)
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886 struct intel_engine_cs *ring;
2890 for_each_ring(ring, dev_priv, i) {
2891 i915_gem_retire_requests_ring(ring);
2892 idle &= list_empty(&ring->request_list);
2893 if (i915.enable_execlists) {
2894 unsigned long flags;
2896 spin_lock_irqsave(&ring->execlist_lock, flags);
2897 idle &= list_empty(&ring->execlist_queue);
2898 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2900 intel_execlists_retire_requests(ring);
2905 mod_delayed_work(dev_priv->wq,
2906 &dev_priv->mm.idle_work,
2907 msecs_to_jiffies(100));
2913 i915_gem_retire_work_handler(struct work_struct *work)
2915 struct drm_i915_private *dev_priv =
2916 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2917 struct drm_device *dev = dev_priv->dev;
2920 /* Come back later if the device is busy... */
2922 if (mutex_trylock(&dev->struct_mutex)) {
2923 idle = i915_gem_retire_requests(dev);
2924 mutex_unlock(&dev->struct_mutex);
2927 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2928 round_jiffies_up_relative(HZ));
2932 i915_gem_idle_work_handler(struct work_struct *work)
2934 struct drm_i915_private *dev_priv =
2935 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2936 struct drm_device *dev = dev_priv->dev;
2937 struct intel_engine_cs *ring;
2940 for_each_ring(ring, dev_priv, i)
2941 if (!list_empty(&ring->request_list))
2944 intel_mark_idle(dev);
2946 if (mutex_trylock(&dev->struct_mutex)) {
2947 struct intel_engine_cs *ring;
2950 for_each_ring(ring, dev_priv, i)
2951 i915_gem_batch_pool_fini(&ring->batch_pool);
2953 mutex_unlock(&dev->struct_mutex);
2958 * Ensures that an object will eventually get non-busy by flushing any required
2959 * write domains, emitting any outstanding lazy request and retiring and
2960 * completed requests.
2963 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2970 for (i = 0; i < I915_NUM_RINGS; i++) {
2971 struct drm_i915_gem_request *req;
2973 req = obj->last_read_req[i];
2977 if (list_empty(&req->list))
2980 if (i915_gem_request_completed(req, true)) {
2981 __i915_gem_request_retire__upto(req);
2983 i915_gem_object_retire__read(obj, i);
2991 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2992 * @DRM_IOCTL_ARGS: standard ioctl arguments
2994 * Returns 0 if successful, else an error is returned with the remaining time in
2995 * the timeout parameter.
2996 * -ETIME: object is still busy after timeout
2997 * -ERESTARTSYS: signal interrupted the wait
2998 * -ENONENT: object doesn't exist
2999 * Also possible, but rare:
3000 * -EAGAIN: GPU wedged
3002 * -ENODEV: Internal IRQ fail
3003 * -E?: The add request failed
3005 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3006 * non-zero timeout parameter the wait ioctl will wait for the given number of
3007 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3008 * without holding struct_mutex the object may become re-busied before this
3009 * function completes. A similar but shorter * race condition exists in the busy
3013 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3015 struct drm_i915_private *dev_priv = dev->dev_private;
3016 struct drm_i915_gem_wait *args = data;
3017 struct drm_i915_gem_object *obj;
3018 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3019 unsigned reset_counter;
3023 if (args->flags != 0)
3026 ret = i915_mutex_lock_interruptible(dev);
3030 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3031 if (&obj->base == NULL) {
3032 mutex_unlock(&dev->struct_mutex);
3036 /* Need to make sure the object gets inactive eventually. */
3037 ret = i915_gem_object_flush_active(obj);
3044 /* Do this after OLR check to make sure we make forward progress polling
3045 * on this IOCTL with a timeout == 0 (like busy ioctl)
3047 if (args->timeout_ns == 0) {
3052 drm_gem_object_unreference(&obj->base);
3053 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3055 for (i = 0; i < I915_NUM_RINGS; i++) {
3056 if (obj->last_read_req[i] == NULL)
3059 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3062 mutex_unlock(&dev->struct_mutex);
3064 for (i = 0; i < n; i++) {
3066 ret = __i915_wait_request(req[i], reset_counter, true,
3067 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3068 to_rps_client(file));
3069 i915_gem_request_unreference__unlocked(req[i]);
3074 drm_gem_object_unreference(&obj->base);
3075 mutex_unlock(&dev->struct_mutex);
3080 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3081 struct intel_engine_cs *to,
3082 struct drm_i915_gem_request *from_req,
3083 struct drm_i915_gem_request **to_req)
3085 struct intel_engine_cs *from;
3088 from = i915_gem_request_get_ring(from_req);
3092 if (i915_gem_request_completed(from_req, true))
3095 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3096 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3097 ret = __i915_wait_request(from_req,
3098 atomic_read(&i915->gpu_error.reset_counter),
3099 i915->mm.interruptible,
3101 &i915->rps.semaphores);
3105 i915_gem_object_retire_request(obj, from_req);
3107 int idx = intel_ring_sync_index(from, to);
3108 u32 seqno = i915_gem_request_get_seqno(from_req);
3112 if (seqno <= from->semaphore.sync_seqno[idx])
3115 if (*to_req == NULL) {
3116 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3121 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3122 ret = to->semaphore.sync_to(*to_req, from, seqno);
3126 /* We use last_read_req because sync_to()
3127 * might have just caused seqno wrap under
3130 from->semaphore.sync_seqno[idx] =
3131 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3138 * i915_gem_object_sync - sync an object to a ring.
3140 * @obj: object which may be in use on another ring.
3141 * @to: ring we wish to use the object on. May be NULL.
3142 * @to_req: request we wish to use the object for. See below.
3143 * This will be allocated and returned if a request is
3144 * required but not passed in.
3146 * This code is meant to abstract object synchronization with the GPU.
3147 * Calling with NULL implies synchronizing the object with the CPU
3148 * rather than a particular GPU ring. Conceptually we serialise writes
3149 * between engines inside the GPU. We only allow one engine to write
3150 * into a buffer at any time, but multiple readers. To ensure each has
3151 * a coherent view of memory, we must:
3153 * - If there is an outstanding write request to the object, the new
3154 * request must wait for it to complete (either CPU or in hw, requests
3155 * on the same ring will be naturally ordered).
3157 * - If we are a write request (pending_write_domain is set), the new
3158 * request must wait for outstanding read requests to complete.
3160 * For CPU synchronisation (NULL to) no request is required. For syncing with
3161 * rings to_req must be non-NULL. However, a request does not have to be
3162 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3163 * request will be allocated automatically and returned through *to_req. Note
3164 * that it is not guaranteed that commands will be emitted (because the system
3165 * might already be idle). Hence there is no need to create a request that
3166 * might never have any work submitted. Note further that if a request is
3167 * returned in *to_req, it is the responsibility of the caller to submit
3168 * that request (after potentially adding more work to it).
3170 * Returns 0 if successful, else propagates up the lower layer error.
3173 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3174 struct intel_engine_cs *to,
3175 struct drm_i915_gem_request **to_req)
3177 const bool readonly = obj->base.pending_write_domain == 0;
3178 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3185 return i915_gem_object_wait_rendering(obj, readonly);
3189 if (obj->last_write_req)
3190 req[n++] = obj->last_write_req;
3192 for (i = 0; i < I915_NUM_RINGS; i++)
3193 if (obj->last_read_req[i])
3194 req[n++] = obj->last_read_req[i];
3196 for (i = 0; i < n; i++) {
3197 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3205 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3207 u32 old_write_domain, old_read_domains;
3209 /* Force a pagefault for domain tracking on next user access */
3210 i915_gem_release_mmap(obj);
3212 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3215 /* Wait for any direct GTT access to complete */
3218 old_read_domains = obj->base.read_domains;
3219 old_write_domain = obj->base.write_domain;
3221 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3222 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3224 trace_i915_gem_object_change_domain(obj,
3229 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3231 struct drm_i915_gem_object *obj = vma->obj;
3232 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3235 if (list_empty(&vma->vma_link))
3238 if (!drm_mm_node_allocated(&vma->node)) {
3239 i915_gem_vma_destroy(vma);
3246 BUG_ON(obj->pages == NULL);
3249 ret = i915_gem_object_wait_rendering(obj, false);
3254 if (i915_is_ggtt(vma->vm) &&
3255 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3256 i915_gem_object_finish_gtt(obj);
3258 /* release the fence reg _after_ flushing */
3259 ret = i915_gem_object_put_fence(obj);
3264 trace_i915_vma_unbind(vma);
3266 vma->vm->unbind_vma(vma);
3269 list_del_init(&vma->mm_list);
3270 if (i915_is_ggtt(vma->vm)) {
3271 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3272 obj->map_and_fenceable = false;
3273 } else if (vma->ggtt_view.pages) {
3274 sg_free_table(vma->ggtt_view.pages);
3275 kfree(vma->ggtt_view.pages);
3277 vma->ggtt_view.pages = NULL;
3280 drm_mm_remove_node(&vma->node);
3281 i915_gem_vma_destroy(vma);
3283 /* Since the unbound list is global, only move to that list if
3284 * no more VMAs exist. */
3285 if (list_empty(&obj->vma_list))
3286 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3288 /* And finally now the object is completely decoupled from this vma,
3289 * we can drop its hold on the backing storage and allow it to be
3290 * reaped by the shrinker.
3292 i915_gem_object_unpin_pages(obj);
3297 int i915_vma_unbind(struct i915_vma *vma)
3299 return __i915_vma_unbind(vma, true);
3302 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3304 return __i915_vma_unbind(vma, false);
3307 int i915_gpu_idle(struct drm_device *dev)
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 struct intel_engine_cs *ring;
3313 /* Flush everything onto the inactive list. */
3314 for_each_ring(ring, dev_priv, i) {
3315 if (!i915.enable_execlists) {
3316 struct drm_i915_gem_request *req;
3318 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3322 ret = i915_switch_context(req);
3324 i915_gem_request_cancel(req);
3328 i915_add_request_no_flush(req);
3331 ret = intel_ring_idle(ring);
3336 WARN_ON(i915_verify_lists(dev));
3340 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3341 unsigned long cache_level)
3343 struct drm_mm_node *gtt_space = &vma->node;
3344 struct drm_mm_node *other;
3347 * On some machines we have to be careful when putting differing types
3348 * of snoopable memory together to avoid the prefetcher crossing memory
3349 * domains and dying. During vm initialisation, we decide whether or not
3350 * these constraints apply and set the drm_mm.color_adjust
3353 if (vma->vm->mm.color_adjust == NULL)
3356 if (!drm_mm_node_allocated(gtt_space))
3359 if (list_empty(>t_space->node_list))
3362 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3363 if (other->allocated && !other->hole_follows && other->color != cache_level)
3366 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3367 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3374 * Finds free space in the GTT aperture and binds the object or a view of it
3377 static struct i915_vma *
3378 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3379 struct i915_address_space *vm,
3380 const struct i915_ggtt_view *ggtt_view,
3384 struct drm_device *dev = obj->base.dev;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 u32 fence_alignment, unfenced_alignment;
3387 u32 search_flag, alloc_flag;
3389 u64 size, fence_size;
3390 struct i915_vma *vma;
3393 if (i915_is_ggtt(vm)) {
3396 if (WARN_ON(!ggtt_view))
3397 return ERR_PTR(-EINVAL);
3399 view_size = i915_ggtt_view_size(obj, ggtt_view);
3401 fence_size = i915_gem_get_gtt_size(dev,
3404 fence_alignment = i915_gem_get_gtt_alignment(dev,
3408 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3412 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3414 fence_size = i915_gem_get_gtt_size(dev,
3417 fence_alignment = i915_gem_get_gtt_alignment(dev,
3421 unfenced_alignment =
3422 i915_gem_get_gtt_alignment(dev,
3426 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3429 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3431 if (flags & PIN_MAPPABLE)
3432 end = min_t(u64, end, dev_priv->gtt.mappable_end);
3433 if (flags & PIN_ZONE_4G)
3434 end = min_t(u64, end, (1ULL << 32));
3437 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3439 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3440 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3441 ggtt_view ? ggtt_view->type : 0,
3443 return ERR_PTR(-EINVAL);
3446 /* If binding the object/GGTT view requires more space than the entire
3447 * aperture has, reject it early before evicting everything in a vain
3448 * attempt to find space.
3451 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3452 ggtt_view ? ggtt_view->type : 0,
3454 flags & PIN_MAPPABLE ? "mappable" : "total",
3456 return ERR_PTR(-E2BIG);
3459 ret = i915_gem_object_get_pages(obj);
3461 return ERR_PTR(ret);
3463 i915_gem_object_pin_pages(obj);
3465 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3466 i915_gem_obj_lookup_or_create_vma(obj, vm);
3471 if (flags & PIN_OFFSET_FIXED) {
3472 uint64_t offset = flags & PIN_OFFSET_MASK;
3474 if (offset & (alignment - 1) || offset + size > end) {
3478 vma->node.start = offset;
3479 vma->node.size = size;
3480 vma->node.color = obj->cache_level;
3481 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3483 ret = i915_gem_evict_for_vma(vma);
3485 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3490 if (flags & PIN_HIGH) {
3491 search_flag = DRM_MM_SEARCH_BELOW;
3492 alloc_flag = DRM_MM_CREATE_TOP;
3494 search_flag = DRM_MM_SEARCH_DEFAULT;
3495 alloc_flag = DRM_MM_CREATE_DEFAULT;
3499 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3506 ret = i915_gem_evict_something(dev, vm, size, alignment,
3516 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3518 goto err_remove_node;
3521 trace_i915_vma_bind(vma, flags);
3522 ret = i915_vma_bind(vma, obj->cache_level, flags);
3524 goto err_remove_node;
3526 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3527 list_add_tail(&vma->mm_list, &vm->inactive_list);
3532 drm_mm_remove_node(&vma->node);
3534 i915_gem_vma_destroy(vma);
3537 i915_gem_object_unpin_pages(obj);
3542 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3545 /* If we don't have a page list set up, then we're not pinned
3546 * to GPU, and we can ignore the cache flush because it'll happen
3547 * again at bind time.
3549 if (obj->pages == NULL)
3553 * Stolen memory is always coherent with the GPU as it is explicitly
3554 * marked as wc by the system, or the system is cache-coherent.
3556 if (obj->stolen || obj->phys_handle)
3559 /* If the GPU is snooping the contents of the CPU cache,
3560 * we do not need to manually clear the CPU cache lines. However,
3561 * the caches are only snooped when the render cache is
3562 * flushed/invalidated. As we always have to emit invalidations
3563 * and flushes when moving into and out of the RENDER domain, correct
3564 * snooping behaviour occurs naturally as the result of our domain
3567 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3568 obj->cache_dirty = true;
3572 trace_i915_gem_object_clflush(obj);
3573 drm_clflush_sg(obj->pages);
3574 obj->cache_dirty = false;
3579 /** Flushes the GTT write domain for the object if it's dirty. */
3581 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3583 uint32_t old_write_domain;
3585 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3588 /* No actual flushing is required for the GTT write domain. Writes
3589 * to it immediately go to main memory as far as we know, so there's
3590 * no chipset flush. It also doesn't land in render cache.
3592 * However, we do have to enforce the order so that all writes through
3593 * the GTT land before any writes to the device, such as updates to
3598 old_write_domain = obj->base.write_domain;
3599 obj->base.write_domain = 0;
3601 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3603 trace_i915_gem_object_change_domain(obj,
3604 obj->base.read_domains,
3608 /** Flushes the CPU write domain for the object if it's dirty. */
3610 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3612 uint32_t old_write_domain;
3614 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3617 if (i915_gem_clflush_object(obj, obj->pin_display))
3618 i915_gem_chipset_flush(obj->base.dev);
3620 old_write_domain = obj->base.write_domain;
3621 obj->base.write_domain = 0;
3623 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3625 trace_i915_gem_object_change_domain(obj,
3626 obj->base.read_domains,
3631 * Moves a single object to the GTT read, and possibly write domain.
3633 * This function returns when the move is complete, including waiting on
3637 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3639 uint32_t old_write_domain, old_read_domains;
3640 struct i915_vma *vma;
3643 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3646 ret = i915_gem_object_wait_rendering(obj, !write);
3650 /* Flush and acquire obj->pages so that we are coherent through
3651 * direct access in memory with previous cached writes through
3652 * shmemfs and that our cache domain tracking remains valid.
3653 * For example, if the obj->filp was moved to swap without us
3654 * being notified and releasing the pages, we would mistakenly
3655 * continue to assume that the obj remained out of the CPU cached
3658 ret = i915_gem_object_get_pages(obj);
3662 i915_gem_object_flush_cpu_write_domain(obj);
3664 /* Serialise direct access to this object with the barriers for
3665 * coherent writes from the GPU, by effectively invalidating the
3666 * GTT domain upon first access.
3668 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3671 old_write_domain = obj->base.write_domain;
3672 old_read_domains = obj->base.read_domains;
3674 /* It should now be out of any other write domains, and we can update
3675 * the domain values for our changes.
3677 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3678 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3680 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3681 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3685 trace_i915_gem_object_change_domain(obj,
3689 /* And bump the LRU for this access */
3690 vma = i915_gem_obj_to_ggtt(obj);
3691 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3692 list_move_tail(&vma->mm_list,
3693 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3699 * Changes the cache-level of an object across all VMA.
3701 * After this function returns, the object will be in the new cache-level
3702 * across all GTT and the contents of the backing storage will be coherent,
3703 * with respect to the new cache-level. In order to keep the backing storage
3704 * coherent for all users, we only allow a single cache level to be set
3705 * globally on the object and prevent it from being changed whilst the
3706 * hardware is reading from the object. That is if the object is currently
3707 * on the scanout it will be set to uncached (or equivalent display
3708 * cache coherency) and all non-MOCS GPU access will also be uncached so
3709 * that all direct access to the scanout remains coherent.
3711 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3712 enum i915_cache_level cache_level)
3714 struct drm_device *dev = obj->base.dev;
3715 struct i915_vma *vma, *next;
3719 if (obj->cache_level == cache_level)
3722 /* Inspect the list of currently bound VMA and unbind any that would
3723 * be invalid given the new cache-level. This is principally to
3724 * catch the issue of the CS prefetch crossing page boundaries and
3725 * reading an invalid PTE on older architectures.
3727 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3728 if (!drm_mm_node_allocated(&vma->node))
3731 if (vma->pin_count) {
3732 DRM_DEBUG("can not change the cache level of pinned objects\n");
3736 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3737 ret = i915_vma_unbind(vma);
3744 /* We can reuse the existing drm_mm nodes but need to change the
3745 * cache-level on the PTE. We could simply unbind them all and
3746 * rebind with the correct cache-level on next use. However since
3747 * we already have a valid slot, dma mapping, pages etc, we may as
3748 * rewrite the PTE in the belief that doing so tramples upon less
3749 * state and so involves less work.
3752 /* Before we change the PTE, the GPU must not be accessing it.
3753 * If we wait upon the object, we know that all the bound
3754 * VMA are no longer active.
3756 ret = i915_gem_object_wait_rendering(obj, false);
3760 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3761 /* Access to snoopable pages through the GTT is
3762 * incoherent and on some machines causes a hard
3763 * lockup. Relinquish the CPU mmaping to force
3764 * userspace to refault in the pages and we can
3765 * then double check if the GTT mapping is still
3766 * valid for that pointer access.
3768 i915_gem_release_mmap(obj);
3770 /* As we no longer need a fence for GTT access,
3771 * we can relinquish it now (and so prevent having
3772 * to steal a fence from someone else on the next
3773 * fence request). Note GPU activity would have
3774 * dropped the fence as all snoopable access is
3775 * supposed to be linear.
3777 ret = i915_gem_object_put_fence(obj);
3781 /* We either have incoherent backing store and
3782 * so no GTT access or the architecture is fully
3783 * coherent. In such cases, existing GTT mmaps
3784 * ignore the cache bit in the PTE and we can
3785 * rewrite it without confusing the GPU or having
3786 * to force userspace to fault back in its mmaps.
3790 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3791 if (!drm_mm_node_allocated(&vma->node))
3794 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3800 list_for_each_entry(vma, &obj->vma_list, vma_link)
3801 vma->node.color = cache_level;
3802 obj->cache_level = cache_level;
3805 /* Flush the dirty CPU caches to the backing storage so that the
3806 * object is now coherent at its new cache level (with respect
3807 * to the access domain).
3809 if (obj->cache_dirty &&
3810 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3811 cpu_write_needs_clflush(obj)) {
3812 if (i915_gem_clflush_object(obj, true))
3813 i915_gem_chipset_flush(obj->base.dev);
3819 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3820 struct drm_file *file)
3822 struct drm_i915_gem_caching *args = data;
3823 struct drm_i915_gem_object *obj;
3825 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3826 if (&obj->base == NULL)
3829 switch (obj->cache_level) {
3830 case I915_CACHE_LLC:
3831 case I915_CACHE_L3_LLC:
3832 args->caching = I915_CACHING_CACHED;
3836 args->caching = I915_CACHING_DISPLAY;
3840 args->caching = I915_CACHING_NONE;
3844 drm_gem_object_unreference_unlocked(&obj->base);
3848 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3849 struct drm_file *file)
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 struct drm_i915_gem_caching *args = data;
3853 struct drm_i915_gem_object *obj;
3854 enum i915_cache_level level;
3857 switch (args->caching) {
3858 case I915_CACHING_NONE:
3859 level = I915_CACHE_NONE;
3861 case I915_CACHING_CACHED:
3863 * Due to a HW issue on BXT A stepping, GPU stores via a
3864 * snooped mapping may leave stale data in a corresponding CPU
3865 * cacheline, whereas normally such cachelines would get
3868 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
3871 level = I915_CACHE_LLC;
3873 case I915_CACHING_DISPLAY:
3874 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3880 intel_runtime_pm_get(dev_priv);
3882 ret = i915_mutex_lock_interruptible(dev);
3886 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3887 if (&obj->base == NULL) {
3892 ret = i915_gem_object_set_cache_level(obj, level);
3894 drm_gem_object_unreference(&obj->base);
3896 mutex_unlock(&dev->struct_mutex);
3898 intel_runtime_pm_put(dev_priv);
3904 * Prepare buffer for display plane (scanout, cursors, etc).
3905 * Can be called from an uninterruptible phase (modesetting) and allows
3906 * any flushes to be pipelined (for pageflips).
3909 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3911 const struct i915_ggtt_view *view)
3913 u32 old_read_domains, old_write_domain;
3916 /* Mark the pin_display early so that we account for the
3917 * display coherency whilst setting up the cache domains.
3921 /* The display engine is not coherent with the LLC cache on gen6. As
3922 * a result, we make sure that the pinning that is about to occur is
3923 * done with uncached PTEs. This is lowest common denominator for all
3926 * However for gen6+, we could do better by using the GFDT bit instead
3927 * of uncaching, which would allow us to flush all the LLC-cached data
3928 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3930 ret = i915_gem_object_set_cache_level(obj,
3931 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3933 goto err_unpin_display;
3935 /* As the user may map the buffer once pinned in the display plane
3936 * (e.g. libkms for the bootup splash), we have to ensure that we
3937 * always use map_and_fenceable for all scanout buffers.
3939 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
3940 view->type == I915_GGTT_VIEW_NORMAL ?
3943 goto err_unpin_display;
3945 i915_gem_object_flush_cpu_write_domain(obj);
3947 old_write_domain = obj->base.write_domain;
3948 old_read_domains = obj->base.read_domains;
3950 /* It should now be out of any other write domains, and we can update
3951 * the domain values for our changes.
3953 obj->base.write_domain = 0;
3954 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3956 trace_i915_gem_object_change_domain(obj,
3968 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3969 const struct i915_ggtt_view *view)
3971 if (WARN_ON(obj->pin_display == 0))
3974 i915_gem_object_ggtt_unpin_view(obj, view);
3980 * Moves a single object to the CPU read, and possibly write domain.
3982 * This function returns when the move is complete, including waiting on
3986 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3988 uint32_t old_write_domain, old_read_domains;
3991 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3994 ret = i915_gem_object_wait_rendering(obj, !write);
3998 i915_gem_object_flush_gtt_write_domain(obj);
4000 old_write_domain = obj->base.write_domain;
4001 old_read_domains = obj->base.read_domains;
4003 /* Flush the CPU cache if it's still invalid. */
4004 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4005 i915_gem_clflush_object(obj, false);
4007 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4010 /* It should now be out of any other write domains, and we can update
4011 * the domain values for our changes.
4013 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4015 /* If we're writing through the CPU, then the GPU read domains will
4016 * need to be invalidated at next use.
4019 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4020 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4023 trace_i915_gem_object_change_domain(obj,
4030 /* Throttle our rendering by waiting until the ring has completed our requests
4031 * emitted over 20 msec ago.
4033 * Note that if we were to use the current jiffies each time around the loop,
4034 * we wouldn't escape the function with any frames outstanding if the time to
4035 * render a frame was over 20ms.
4037 * This should get us reasonable parallelism between CPU and GPU but also
4038 * relatively low latency when blocking on a particular request to finish.
4041 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4043 struct drm_i915_private *dev_priv = dev->dev_private;
4044 struct drm_i915_file_private *file_priv = file->driver_priv;
4045 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4046 struct drm_i915_gem_request *request, *target = NULL;
4047 unsigned reset_counter;
4050 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4054 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4058 spin_lock(&file_priv->mm.lock);
4059 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4060 if (time_after_eq(request->emitted_jiffies, recent_enough))
4064 * Note that the request might not have been submitted yet.
4065 * In which case emitted_jiffies will be zero.
4067 if (!request->emitted_jiffies)
4072 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4074 i915_gem_request_reference(target);
4075 spin_unlock(&file_priv->mm.lock);
4080 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4082 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4084 i915_gem_request_unreference__unlocked(target);
4090 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4092 struct drm_i915_gem_object *obj = vma->obj;
4095 vma->node.start & (alignment - 1))
4098 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4101 if (flags & PIN_OFFSET_BIAS &&
4102 vma->node.start < (flags & PIN_OFFSET_MASK))
4105 if (flags & PIN_OFFSET_FIXED &&
4106 vma->node.start != (flags & PIN_OFFSET_MASK))
4113 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4114 struct i915_address_space *vm,
4115 const struct i915_ggtt_view *ggtt_view,
4119 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4120 struct i915_vma *vma;
4124 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4127 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4130 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4133 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4136 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4137 i915_gem_obj_to_vma(obj, vm);
4140 return PTR_ERR(vma);
4143 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4146 if (i915_vma_misplaced(vma, alignment, flags)) {
4147 WARN(vma->pin_count,
4148 "bo is already pinned in %s with incorrect alignment:"
4149 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4150 " obj->map_and_fenceable=%d\n",
4151 ggtt_view ? "ggtt" : "ppgtt",
4152 upper_32_bits(vma->node.start),
4153 lower_32_bits(vma->node.start),
4155 !!(flags & PIN_MAPPABLE),
4156 obj->map_and_fenceable);
4157 ret = i915_vma_unbind(vma);
4165 bound = vma ? vma->bound : 0;
4166 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4167 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4170 return PTR_ERR(vma);
4172 ret = i915_vma_bind(vma, obj->cache_level, flags);
4177 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4178 (bound ^ vma->bound) & GLOBAL_BIND) {
4179 bool mappable, fenceable;
4180 u32 fence_size, fence_alignment;
4182 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4185 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4190 fenceable = (vma->node.size == fence_size &&
4191 (vma->node.start & (fence_alignment - 1)) == 0);
4193 mappable = (vma->node.start + fence_size <=
4194 dev_priv->gtt.mappable_end);
4196 obj->map_and_fenceable = mappable && fenceable;
4198 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4206 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4207 struct i915_address_space *vm,
4211 return i915_gem_object_do_pin(obj, vm,
4212 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4217 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4218 const struct i915_ggtt_view *view,
4222 if (WARN_ONCE(!view, "no view specified"))
4225 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4226 alignment, flags | PIN_GLOBAL);
4230 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4231 const struct i915_ggtt_view *view)
4233 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4236 WARN_ON(vma->pin_count == 0);
4237 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4243 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4244 struct drm_file *file)
4246 struct drm_i915_gem_busy *args = data;
4247 struct drm_i915_gem_object *obj;
4250 ret = i915_mutex_lock_interruptible(dev);
4254 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4255 if (&obj->base == NULL) {
4260 /* Count all active objects as busy, even if they are currently not used
4261 * by the gpu. Users of this interface expect objects to eventually
4262 * become non-busy without any further actions, therefore emit any
4263 * necessary flushes here.
4265 ret = i915_gem_object_flush_active(obj);
4269 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4270 args->busy = obj->active << 16;
4271 if (obj->last_write_req)
4272 args->busy |= obj->last_write_req->ring->id;
4275 drm_gem_object_unreference(&obj->base);
4277 mutex_unlock(&dev->struct_mutex);
4282 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4283 struct drm_file *file_priv)
4285 return i915_gem_ring_throttle(dev, file_priv);
4289 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4290 struct drm_file *file_priv)
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 struct drm_i915_gem_madvise *args = data;
4294 struct drm_i915_gem_object *obj;
4297 switch (args->madv) {
4298 case I915_MADV_DONTNEED:
4299 case I915_MADV_WILLNEED:
4305 ret = i915_mutex_lock_interruptible(dev);
4309 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4310 if (&obj->base == NULL) {
4315 if (i915_gem_obj_is_pinned(obj)) {
4321 obj->tiling_mode != I915_TILING_NONE &&
4322 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4323 if (obj->madv == I915_MADV_WILLNEED)
4324 i915_gem_object_unpin_pages(obj);
4325 if (args->madv == I915_MADV_WILLNEED)
4326 i915_gem_object_pin_pages(obj);
4329 if (obj->madv != __I915_MADV_PURGED)
4330 obj->madv = args->madv;
4332 /* if the object is no longer attached, discard its backing storage */
4333 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4334 i915_gem_object_truncate(obj);
4336 args->retained = obj->madv != __I915_MADV_PURGED;
4339 drm_gem_object_unreference(&obj->base);
4341 mutex_unlock(&dev->struct_mutex);
4345 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4346 const struct drm_i915_gem_object_ops *ops)
4350 INIT_LIST_HEAD(&obj->global_list);
4351 for (i = 0; i < I915_NUM_RINGS; i++)
4352 INIT_LIST_HEAD(&obj->ring_list[i]);
4353 INIT_LIST_HEAD(&obj->obj_exec_link);
4354 INIT_LIST_HEAD(&obj->vma_list);
4355 INIT_LIST_HEAD(&obj->batch_pool_link);
4359 obj->fence_reg = I915_FENCE_REG_NONE;
4360 obj->madv = I915_MADV_WILLNEED;
4362 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4365 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4366 .get_pages = i915_gem_object_get_pages_gtt,
4367 .put_pages = i915_gem_object_put_pages_gtt,
4370 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4373 struct drm_i915_gem_object *obj;
4374 struct address_space *mapping;
4377 obj = i915_gem_object_alloc(dev);
4381 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4382 i915_gem_object_free(obj);
4386 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4387 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4388 /* 965gm cannot relocate objects above 4GiB. */
4389 mask &= ~__GFP_HIGHMEM;
4390 mask |= __GFP_DMA32;
4393 mapping = file_inode(obj->base.filp)->i_mapping;
4394 mapping_set_gfp_mask(mapping, mask);
4396 i915_gem_object_init(obj, &i915_gem_object_ops);
4398 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4399 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4402 /* On some devices, we can have the GPU use the LLC (the CPU
4403 * cache) for about a 10% performance improvement
4404 * compared to uncached. Graphics requests other than
4405 * display scanout are coherent with the CPU in
4406 * accessing this cache. This means in this mode we
4407 * don't need to clflush on the CPU side, and on the
4408 * GPU side we only need to flush internal caches to
4409 * get data visible to the CPU.
4411 * However, we maintain the display planes as UC, and so
4412 * need to rebind when first used as such.
4414 obj->cache_level = I915_CACHE_LLC;
4416 obj->cache_level = I915_CACHE_NONE;
4418 trace_i915_gem_object_create(obj);
4423 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4425 /* If we are the last user of the backing storage (be it shmemfs
4426 * pages or stolen etc), we know that the pages are going to be
4427 * immediately released. In this case, we can then skip copying
4428 * back the contents from the GPU.
4431 if (obj->madv != I915_MADV_WILLNEED)
4434 if (obj->base.filp == NULL)
4437 /* At first glance, this looks racy, but then again so would be
4438 * userspace racing mmap against close. However, the first external
4439 * reference to the filp can only be obtained through the
4440 * i915_gem_mmap_ioctl() which safeguards us against the user
4441 * acquiring such a reference whilst we are in the middle of
4442 * freeing the object.
4444 return atomic_long_read(&obj->base.filp->f_count) == 1;
4447 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4449 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4450 struct drm_device *dev = obj->base.dev;
4451 struct drm_i915_private *dev_priv = dev->dev_private;
4452 struct i915_vma *vma, *next;
4454 intel_runtime_pm_get(dev_priv);
4456 trace_i915_gem_object_destroy(obj);
4458 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4462 ret = i915_vma_unbind(vma);
4463 if (WARN_ON(ret == -ERESTARTSYS)) {
4464 bool was_interruptible;
4466 was_interruptible = dev_priv->mm.interruptible;
4467 dev_priv->mm.interruptible = false;
4469 WARN_ON(i915_vma_unbind(vma));
4471 dev_priv->mm.interruptible = was_interruptible;
4475 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4476 * before progressing. */
4478 i915_gem_object_unpin_pages(obj);
4480 WARN_ON(obj->frontbuffer_bits);
4482 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4483 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4484 obj->tiling_mode != I915_TILING_NONE)
4485 i915_gem_object_unpin_pages(obj);
4487 if (WARN_ON(obj->pages_pin_count))
4488 obj->pages_pin_count = 0;
4489 if (discard_backing_storage(obj))
4490 obj->madv = I915_MADV_DONTNEED;
4491 i915_gem_object_put_pages(obj);
4492 i915_gem_object_free_mmap_offset(obj);
4496 if (obj->base.import_attach)
4497 drm_prime_gem_destroy(&obj->base, NULL);
4499 if (obj->ops->release)
4500 obj->ops->release(obj);
4502 drm_gem_object_release(&obj->base);
4503 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4506 i915_gem_object_free(obj);
4508 intel_runtime_pm_put(dev_priv);
4511 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4512 struct i915_address_space *vm)
4514 struct i915_vma *vma;
4515 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4516 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4523 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4524 const struct i915_ggtt_view *view)
4526 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4527 struct i915_vma *vma;
4529 if (WARN_ONCE(!view, "no view specified"))
4530 return ERR_PTR(-EINVAL);
4532 list_for_each_entry(vma, &obj->vma_list, vma_link)
4533 if (vma->vm == ggtt &&
4534 i915_ggtt_view_equal(&vma->ggtt_view, view))
4539 void i915_gem_vma_destroy(struct i915_vma *vma)
4541 struct i915_address_space *vm = NULL;
4542 WARN_ON(vma->node.allocated);
4544 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4545 if (!list_empty(&vma->exec_list))
4550 if (!i915_is_ggtt(vm))
4551 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4553 list_del(&vma->vma_link);
4555 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4559 i915_gem_stop_ringbuffers(struct drm_device *dev)
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 struct intel_engine_cs *ring;
4565 for_each_ring(ring, dev_priv, i)
4566 dev_priv->gt.stop_ring(ring);
4570 i915_gem_suspend(struct drm_device *dev)
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4575 mutex_lock(&dev->struct_mutex);
4576 ret = i915_gpu_idle(dev);
4580 i915_gem_retire_requests(dev);
4582 i915_gem_stop_ringbuffers(dev);
4583 mutex_unlock(&dev->struct_mutex);
4585 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4586 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4587 flush_delayed_work(&dev_priv->mm.idle_work);
4589 /* Assert that we sucessfully flushed all the work and
4590 * reset the GPU back to its idle, low power state.
4592 WARN_ON(dev_priv->mm.busy);
4597 mutex_unlock(&dev->struct_mutex);
4601 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4603 struct intel_engine_cs *ring = req->ring;
4604 struct drm_device *dev = ring->dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4609 if (!HAS_L3_DPF(dev) || !remap_info)
4612 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4617 * Note: We do not worry about the concurrent register cacheline hang
4618 * here because no other code should access these registers other than
4619 * at initialization time.
4621 for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
4622 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4623 intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
4624 intel_ring_emit(ring, remap_info[i]);
4627 intel_ring_advance(ring);
4632 void i915_gem_init_swizzling(struct drm_device *dev)
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4636 if (INTEL_INFO(dev)->gen < 5 ||
4637 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4640 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4641 DISP_TILE_SURFACE_SWIZZLING);
4646 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4648 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4649 else if (IS_GEN7(dev))
4650 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4651 else if (IS_GEN8(dev))
4652 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4657 static void init_unused_ring(struct drm_device *dev, u32 base)
4659 struct drm_i915_private *dev_priv = dev->dev_private;
4661 I915_WRITE(RING_CTL(base), 0);
4662 I915_WRITE(RING_HEAD(base), 0);
4663 I915_WRITE(RING_TAIL(base), 0);
4664 I915_WRITE(RING_START(base), 0);
4667 static void init_unused_rings(struct drm_device *dev)
4670 init_unused_ring(dev, PRB1_BASE);
4671 init_unused_ring(dev, SRB0_BASE);
4672 init_unused_ring(dev, SRB1_BASE);
4673 init_unused_ring(dev, SRB2_BASE);
4674 init_unused_ring(dev, SRB3_BASE);
4675 } else if (IS_GEN2(dev)) {
4676 init_unused_ring(dev, SRB0_BASE);
4677 init_unused_ring(dev, SRB1_BASE);
4678 } else if (IS_GEN3(dev)) {
4679 init_unused_ring(dev, PRB1_BASE);
4680 init_unused_ring(dev, PRB2_BASE);
4684 int i915_gem_init_rings(struct drm_device *dev)
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4689 ret = intel_init_render_ring_buffer(dev);
4694 ret = intel_init_bsd_ring_buffer(dev);
4696 goto cleanup_render_ring;
4700 ret = intel_init_blt_ring_buffer(dev);
4702 goto cleanup_bsd_ring;
4705 if (HAS_VEBOX(dev)) {
4706 ret = intel_init_vebox_ring_buffer(dev);
4708 goto cleanup_blt_ring;
4711 if (HAS_BSD2(dev)) {
4712 ret = intel_init_bsd2_ring_buffer(dev);
4714 goto cleanup_vebox_ring;
4720 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4722 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4724 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4725 cleanup_render_ring:
4726 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4732 i915_gem_init_hw(struct drm_device *dev)
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735 struct intel_engine_cs *ring;
4738 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4741 /* Double layer security blanket, see i915_gem_init() */
4742 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4744 if (dev_priv->ellc_size)
4745 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4747 if (IS_HASWELL(dev))
4748 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4749 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4751 if (HAS_PCH_NOP(dev)) {
4752 if (IS_IVYBRIDGE(dev)) {
4753 u32 temp = I915_READ(GEN7_MSG_CTL);
4754 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4755 I915_WRITE(GEN7_MSG_CTL, temp);
4756 } else if (INTEL_INFO(dev)->gen >= 7) {
4757 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4758 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4759 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4763 i915_gem_init_swizzling(dev);
4766 * At least 830 can leave some of the unused rings
4767 * "active" (ie. head != tail) after resume which
4768 * will prevent c3 entry. Makes sure all unused rings
4771 init_unused_rings(dev);
4773 BUG_ON(!dev_priv->ring[RCS].default_context);
4775 ret = i915_ppgtt_init_hw(dev);
4777 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4781 /* Need to do basic initialisation of all rings first: */
4782 for_each_ring(ring, dev_priv, i) {
4783 ret = ring->init_hw(ring);
4788 /* We can't enable contexts until all firmware is loaded */
4789 if (HAS_GUC_UCODE(dev)) {
4790 ret = intel_guc_ucode_load(dev);
4792 DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4799 * Increment the next seqno by 0x100 so we have a visible break
4800 * on re-initialisation
4802 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4806 /* Now it is safe to go back round and do everything else: */
4807 for_each_ring(ring, dev_priv, i) {
4808 struct drm_i915_gem_request *req;
4810 WARN_ON(!ring->default_context);
4812 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
4814 i915_gem_cleanup_ringbuffer(dev);
4818 if (ring->id == RCS) {
4819 for (j = 0; j < NUM_L3_SLICES(dev); j++)
4820 i915_gem_l3_remap(req, j);
4823 ret = i915_ppgtt_init_ring(req);
4824 if (ret && ret != -EIO) {
4825 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
4826 i915_gem_request_cancel(req);
4827 i915_gem_cleanup_ringbuffer(dev);
4831 ret = i915_gem_context_enable(req);
4832 if (ret && ret != -EIO) {
4833 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
4834 i915_gem_request_cancel(req);
4835 i915_gem_cleanup_ringbuffer(dev);
4839 i915_add_request_no_flush(req);
4843 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4847 int i915_gem_init(struct drm_device *dev)
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4852 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4853 i915.enable_execlists);
4855 mutex_lock(&dev->struct_mutex);
4857 if (!i915.enable_execlists) {
4858 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4859 dev_priv->gt.init_rings = i915_gem_init_rings;
4860 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4861 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4863 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4864 dev_priv->gt.init_rings = intel_logical_rings_init;
4865 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4866 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4869 /* This is just a security blanket to placate dragons.
4870 * On some systems, we very sporadically observe that the first TLBs
4871 * used by the CS may be stale, despite us poking the TLB reset. If
4872 * we hold the forcewake during initialisation these problems
4873 * just magically go away.
4875 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4877 ret = i915_gem_init_userptr(dev);
4881 i915_gem_init_global_gtt(dev);
4883 ret = i915_gem_context_init(dev);
4887 ret = dev_priv->gt.init_rings(dev);
4891 ret = i915_gem_init_hw(dev);
4893 /* Allow ring initialisation to fail by marking the GPU as
4894 * wedged. But we only want to do this where the GPU is angry,
4895 * for all other failure, such as an allocation failure, bail.
4897 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4898 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4903 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4904 mutex_unlock(&dev->struct_mutex);
4910 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 struct intel_engine_cs *ring;
4916 for_each_ring(ring, dev_priv, i)
4917 dev_priv->gt.cleanup_ring(ring);
4919 if (i915.enable_execlists)
4921 * Neither the BIOS, ourselves or any other kernel
4922 * expects the system to be in execlists mode on startup,
4923 * so we need to reset the GPU back to legacy mode.
4925 intel_gpu_reset(dev);
4929 init_ring_lists(struct intel_engine_cs *ring)
4931 INIT_LIST_HEAD(&ring->active_list);
4932 INIT_LIST_HEAD(&ring->request_list);
4936 i915_gem_load(struct drm_device *dev)
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4942 kmem_cache_create("i915_gem_object",
4943 sizeof(struct drm_i915_gem_object), 0,
4947 kmem_cache_create("i915_gem_vma",
4948 sizeof(struct i915_vma), 0,
4951 dev_priv->requests =
4952 kmem_cache_create("i915_gem_request",
4953 sizeof(struct drm_i915_gem_request), 0,
4957 INIT_LIST_HEAD(&dev_priv->vm_list);
4958 INIT_LIST_HEAD(&dev_priv->context_list);
4959 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4960 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4961 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4962 for (i = 0; i < I915_NUM_RINGS; i++)
4963 init_ring_lists(&dev_priv->ring[i]);
4964 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4965 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4966 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4967 i915_gem_retire_work_handler);
4968 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4969 i915_gem_idle_work_handler);
4970 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4972 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4974 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
4975 dev_priv->num_fence_regs = 32;
4976 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4977 dev_priv->num_fence_regs = 16;
4979 dev_priv->num_fence_regs = 8;
4981 if (intel_vgpu_active(dev))
4982 dev_priv->num_fence_regs =
4983 I915_READ(vgtif_reg(avail_rs.fence_num));
4986 * Set initial sequence number for requests.
4987 * Using this number allows the wraparound to happen early,
4988 * catching any obvious problems.
4990 dev_priv->next_seqno = ((u32)~0 - 0x1100);
4991 dev_priv->last_seqno = ((u32)~0 - 0x1101);
4993 /* Initialize fence registers to zero */
4994 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4995 i915_gem_restore_fences(dev);
4997 i915_gem_detect_bit_6_swizzle(dev);
4998 init_waitqueue_head(&dev_priv->pending_flip_queue);
5000 dev_priv->mm.interruptible = true;
5002 i915_gem_shrinker_init(dev_priv);
5004 mutex_init(&dev_priv->fb_tracking.lock);
5007 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5009 struct drm_i915_file_private *file_priv = file->driver_priv;
5011 /* Clean up our request list when the client is going away, so that
5012 * later retire_requests won't dereference our soon-to-be-gone
5015 spin_lock(&file_priv->mm.lock);
5016 while (!list_empty(&file_priv->mm.request_list)) {
5017 struct drm_i915_gem_request *request;
5019 request = list_first_entry(&file_priv->mm.request_list,
5020 struct drm_i915_gem_request,
5022 list_del(&request->client_list);
5023 request->file_priv = NULL;
5025 spin_unlock(&file_priv->mm.lock);
5027 if (!list_empty(&file_priv->rps.link)) {
5028 spin_lock(&to_i915(dev)->rps.client_lock);
5029 list_del(&file_priv->rps.link);
5030 spin_unlock(&to_i915(dev)->rps.client_lock);
5034 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5036 struct drm_i915_file_private *file_priv;
5039 DRM_DEBUG_DRIVER("\n");
5041 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5045 file->driver_priv = file_priv;
5046 file_priv->dev_priv = dev->dev_private;
5047 file_priv->file = file;
5048 INIT_LIST_HEAD(&file_priv->rps.link);
5050 spin_lock_init(&file_priv->mm.lock);
5051 INIT_LIST_HEAD(&file_priv->mm.request_list);
5053 ret = i915_gem_context_open(dev, file);
5061 * i915_gem_track_fb - update frontbuffer tracking
5062 * @old: current GEM buffer for the frontbuffer slots
5063 * @new: new GEM buffer for the frontbuffer slots
5064 * @frontbuffer_bits: bitmask of frontbuffer slots
5066 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5067 * from @old and setting them in @new. Both @old and @new can be NULL.
5069 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5070 struct drm_i915_gem_object *new,
5071 unsigned frontbuffer_bits)
5074 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5075 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5076 old->frontbuffer_bits &= ~frontbuffer_bits;
5080 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5081 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5082 new->frontbuffer_bits |= frontbuffer_bits;
5086 /* All the new VM stuff */
5087 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5088 struct i915_address_space *vm)
5090 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5091 struct i915_vma *vma;
5093 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5095 list_for_each_entry(vma, &o->vma_list, vma_link) {
5096 if (i915_is_ggtt(vma->vm) &&
5097 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5100 return vma->node.start;
5103 WARN(1, "%s vma for this object not found.\n",
5104 i915_is_ggtt(vm) ? "global" : "ppgtt");
5108 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5109 const struct i915_ggtt_view *view)
5111 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5112 struct i915_vma *vma;
5114 list_for_each_entry(vma, &o->vma_list, vma_link)
5115 if (vma->vm == ggtt &&
5116 i915_ggtt_view_equal(&vma->ggtt_view, view))
5117 return vma->node.start;
5119 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5123 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5124 struct i915_address_space *vm)
5126 struct i915_vma *vma;
5128 list_for_each_entry(vma, &o->vma_list, vma_link) {
5129 if (i915_is_ggtt(vma->vm) &&
5130 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5132 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5139 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5140 const struct i915_ggtt_view *view)
5142 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5143 struct i915_vma *vma;
5145 list_for_each_entry(vma, &o->vma_list, vma_link)
5146 if (vma->vm == ggtt &&
5147 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5148 drm_mm_node_allocated(&vma->node))
5154 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5156 struct i915_vma *vma;
5158 list_for_each_entry(vma, &o->vma_list, vma_link)
5159 if (drm_mm_node_allocated(&vma->node))
5165 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5166 struct i915_address_space *vm)
5168 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5169 struct i915_vma *vma;
5171 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5173 BUG_ON(list_empty(&o->vma_list));
5175 list_for_each_entry(vma, &o->vma_list, vma_link) {
5176 if (i915_is_ggtt(vma->vm) &&
5177 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5180 return vma->node.size;
5185 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5187 struct i915_vma *vma;
5188 list_for_each_entry(vma, &obj->vma_list, vma_link)
5189 if (vma->pin_count > 0)
5195 /* Allocate a new GEM object and fill it with the supplied data */
5196 struct drm_i915_gem_object *
5197 i915_gem_object_create_from_data(struct drm_device *dev,
5198 const void *data, size_t size)
5200 struct drm_i915_gem_object *obj;
5201 struct sg_table *sg;
5205 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5206 if (IS_ERR_OR_NULL(obj))
5209 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5213 ret = i915_gem_object_get_pages(obj);
5217 i915_gem_object_pin_pages(obj);
5219 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5220 i915_gem_object_unpin_pages(obj);
5222 if (WARN_ON(bytes != size)) {
5223 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5231 drm_gem_object_unreference(&obj->base);
5232 return ERR_PTR(ret);