2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error))
98 /* GPU is already declared terminally dead, give up. */
99 if (i915_terminally_wedged(error))
103 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
104 * userspace. If it takes that long something really bad is going on and
105 * we should simply try to bail out and fail as gracefully as possible.
107 ret = wait_event_interruptible_timeout(error->reset_queue,
111 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
113 } else if (ret < 0) {
121 int i915_mutex_lock_interruptible(struct drm_device *dev)
123 struct drm_i915_private *dev_priv = dev->dev_private;
126 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
130 ret = mutex_lock_interruptible(&dev->struct_mutex);
134 WARN_ON(i915_verify_lists(dev));
139 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
141 return obj->gtt_space && !obj->active;
145 i915_gem_init_ioctl(struct drm_device *dev, void *data,
146 struct drm_file *file)
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 struct drm_i915_gem_init *args = data;
151 if (drm_core_check_feature(dev, DRIVER_MODESET))
154 if (args->gtt_start >= args->gtt_end ||
155 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
158 /* GEM with user mode setting was never supported on ilk and later. */
159 if (INTEL_INFO(dev)->gen >= 5)
162 mutex_lock(&dev->struct_mutex);
163 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
165 dev_priv->gtt.mappable_end = args->gtt_end;
166 mutex_unlock(&dev->struct_mutex);
172 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
173 struct drm_file *file)
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_i915_gem_get_aperture *args = data;
177 struct drm_i915_gem_object *obj;
181 mutex_lock(&dev->struct_mutex);
182 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
184 pinned += obj->gtt_space->size;
185 mutex_unlock(&dev->struct_mutex);
187 args->aper_size = dev_priv->gtt.total;
188 args->aper_available_size = args->aper_size - pinned;
193 void *i915_gem_object_alloc(struct drm_device *dev)
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
199 void i915_gem_object_free(struct drm_i915_gem_object *obj)
201 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
202 kmem_cache_free(dev_priv->slab, obj);
206 i915_gem_create(struct drm_file *file,
207 struct drm_device *dev,
211 struct drm_i915_gem_object *obj;
215 size = roundup(size, PAGE_SIZE);
219 /* Allocate the new object */
220 obj = i915_gem_alloc_object(dev, size);
224 ret = drm_gem_handle_create(file, &obj->base, &handle);
226 drm_gem_object_release(&obj->base);
227 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
228 i915_gem_object_free(obj);
232 /* drop reference from allocate - handle holds it now */
233 drm_gem_object_unreference(&obj->base);
234 trace_i915_gem_object_create(obj);
241 i915_gem_dumb_create(struct drm_file *file,
242 struct drm_device *dev,
243 struct drm_mode_create_dumb *args)
245 /* have to work out size/pitch and return them */
246 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
247 args->size = args->pitch * args->height;
248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
252 int i915_gem_dumb_destroy(struct drm_file *file,
253 struct drm_device *dev,
256 return drm_gem_handle_delete(file, handle);
260 * Creates a new mm object and returns a handle to it.
263 i915_gem_create_ioctl(struct drm_device *dev, void *data,
264 struct drm_file *file)
266 struct drm_i915_gem_create *args = data;
268 return i915_gem_create(file, dev,
269 args->size, &args->handle);
273 __copy_to_user_swizzled(char __user *cpu_vaddr,
274 const char *gpu_vaddr, int gpu_offset,
277 int ret, cpu_offset = 0;
280 int cacheline_end = ALIGN(gpu_offset + 1, 64);
281 int this_length = min(cacheline_end - gpu_offset, length);
282 int swizzled_gpu_offset = gpu_offset ^ 64;
284 ret = __copy_to_user(cpu_vaddr + cpu_offset,
285 gpu_vaddr + swizzled_gpu_offset,
290 cpu_offset += this_length;
291 gpu_offset += this_length;
292 length -= this_length;
299 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
300 const char __user *cpu_vaddr,
303 int ret, cpu_offset = 0;
306 int cacheline_end = ALIGN(gpu_offset + 1, 64);
307 int this_length = min(cacheline_end - gpu_offset, length);
308 int swizzled_gpu_offset = gpu_offset ^ 64;
310 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
311 cpu_vaddr + cpu_offset,
316 cpu_offset += this_length;
317 gpu_offset += this_length;
318 length -= this_length;
324 /* Per-page copy function for the shmem pread fastpath.
325 * Flushes invalid cachelines before reading the target if
326 * needs_clflush is set. */
328 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
329 char __user *user_data,
330 bool page_do_bit17_swizzling, bool needs_clflush)
335 if (unlikely(page_do_bit17_swizzling))
338 vaddr = kmap_atomic(page);
340 drm_clflush_virt_range(vaddr + shmem_page_offset,
342 ret = __copy_to_user_inatomic(user_data,
343 vaddr + shmem_page_offset,
345 kunmap_atomic(vaddr);
347 return ret ? -EFAULT : 0;
351 shmem_clflush_swizzled_range(char *addr, unsigned long length,
354 if (unlikely(swizzled)) {
355 unsigned long start = (unsigned long) addr;
356 unsigned long end = (unsigned long) addr + length;
358 /* For swizzling simply ensure that we always flush both
359 * channels. Lame, but simple and it works. Swizzled
360 * pwrite/pread is far from a hotpath - current userspace
361 * doesn't use it at all. */
362 start = round_down(start, 128);
363 end = round_up(end, 128);
365 drm_clflush_virt_range((void *)start, end - start);
367 drm_clflush_virt_range(addr, length);
372 /* Only difference to the fast-path function is that this can handle bit17
373 * and uses non-atomic copy and kmap functions. */
375 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
376 char __user *user_data,
377 bool page_do_bit17_swizzling, bool needs_clflush)
384 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
386 page_do_bit17_swizzling);
388 if (page_do_bit17_swizzling)
389 ret = __copy_to_user_swizzled(user_data,
390 vaddr, shmem_page_offset,
393 ret = __copy_to_user(user_data,
394 vaddr + shmem_page_offset,
398 return ret ? - EFAULT : 0;
402 i915_gem_shmem_pread(struct drm_device *dev,
403 struct drm_i915_gem_object *obj,
404 struct drm_i915_gem_pread *args,
405 struct drm_file *file)
407 char __user *user_data;
410 int shmem_page_offset, page_length, ret = 0;
411 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
413 int needs_clflush = 0;
414 struct sg_page_iter sg_iter;
416 user_data = to_user_ptr(args->data_ptr);
419 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
421 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj->cache_level == I915_CACHE_NONE)
428 if (obj->gtt_space) {
429 ret = i915_gem_object_set_to_gtt_domain(obj, false);
435 ret = i915_gem_object_get_pages(obj);
439 i915_gem_object_pin_pages(obj);
441 offset = args->offset;
443 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
444 offset >> PAGE_SHIFT) {
445 struct page *page = sg_page_iter_page(&sg_iter);
450 /* Operation in this page
452 * shmem_page_offset = offset within page in shmem file
453 * page_length = bytes to copy for this page
455 shmem_page_offset = offset_in_page(offset);
456 page_length = remain;
457 if ((shmem_page_offset + page_length) > PAGE_SIZE)
458 page_length = PAGE_SIZE - shmem_page_offset;
460 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
461 (page_to_phys(page) & (1 << 17)) != 0;
463 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
464 user_data, page_do_bit17_swizzling,
469 mutex_unlock(&dev->struct_mutex);
472 ret = fault_in_multipages_writeable(user_data, remain);
473 /* Userspace is tricking us, but we've already clobbered
474 * its pages with the prefault and promised to write the
475 * data up to the first fault. Hence ignore any errors
476 * and just continue. */
481 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
482 user_data, page_do_bit17_swizzling,
485 mutex_lock(&dev->struct_mutex);
488 mark_page_accessed(page);
493 remain -= page_length;
494 user_data += page_length;
495 offset += page_length;
499 i915_gem_object_unpin_pages(obj);
505 * Reads data from the object referenced by handle.
507 * On error, the contents of *data are undefined.
510 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file)
513 struct drm_i915_gem_pread *args = data;
514 struct drm_i915_gem_object *obj;
520 if (!access_ok(VERIFY_WRITE,
521 to_user_ptr(args->data_ptr),
525 ret = i915_mutex_lock_interruptible(dev);
529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
530 if (&obj->base == NULL) {
535 /* Bounds check source. */
536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
542 /* prime objects have no backing filp to GEM pread/pwrite
545 if (!obj->base.filp) {
550 trace_i915_gem_object_pread(obj, args->offset, args->size);
552 ret = i915_gem_shmem_pread(dev, obj, args, file);
555 drm_gem_object_unreference(&obj->base);
557 mutex_unlock(&dev->struct_mutex);
561 /* This is the fast write path which cannot handle
562 * page faults in the source data
566 fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
571 void __iomem *vaddr_atomic;
573 unsigned long unwritten;
575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
580 io_mapping_unmap_atomic(vaddr_atomic);
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
589 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pwrite *args,
592 struct drm_file *file)
594 drm_i915_private_t *dev_priv = dev->dev_private;
596 loff_t offset, page_base;
597 char __user *user_data;
598 int page_offset, page_length, ret;
600 ret = i915_gem_object_pin(obj, 0, true, true);
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
608 ret = i915_gem_object_put_fence(obj);
612 user_data = to_user_ptr(args->data_ptr);
615 offset = obj->gtt_offset + args->offset;
618 /* Operation in this page
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
634 if (fast_user_write(dev_priv->gtt.mappable, page_base,
635 page_offset, user_data, page_length)) {
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
646 i915_gem_object_unpin(obj);
651 /* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
656 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
665 if (unlikely(page_do_bit17_swizzling))
668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
678 kunmap_atomic(vaddr);
680 return ret ? -EFAULT : 0;
683 /* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
686 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
699 page_do_bit17_swizzling);
700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
705 ret = __copy_from_user(vaddr + shmem_page_offset,
708 if (needs_clflush_after)
709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
711 page_do_bit17_swizzling);
714 return ret ? -EFAULT : 0;
718 i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
725 char __user *user_data;
726 int shmem_page_offset, page_length, ret = 0;
727 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
728 int hit_slowpath = 0;
729 int needs_clflush_after = 0;
730 int needs_clflush_before = 0;
731 struct sg_page_iter sg_iter;
733 user_data = to_user_ptr(args->data_ptr);
736 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
738 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
739 /* If we're not in the cpu write domain, set ourself into the gtt
740 * write domain and manually flush cachelines (if required). This
741 * optimizes for the case when the gpu will use the data
742 * right away and we therefore have to clflush anyway. */
743 if (obj->cache_level == I915_CACHE_NONE)
744 needs_clflush_after = 1;
745 if (obj->gtt_space) {
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
751 /* Same trick applies for invalidate partially written cachelines before
753 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
754 && obj->cache_level == I915_CACHE_NONE)
755 needs_clflush_before = 1;
757 ret = i915_gem_object_get_pages(obj);
761 i915_gem_object_pin_pages(obj);
763 offset = args->offset;
766 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
767 offset >> PAGE_SHIFT) {
768 struct page *page = sg_page_iter_page(&sg_iter);
769 int partial_cacheline_write;
774 /* Operation in this page
776 * shmem_page_offset = offset within page in shmem file
777 * page_length = bytes to copy for this page
779 shmem_page_offset = offset_in_page(offset);
781 page_length = remain;
782 if ((shmem_page_offset + page_length) > PAGE_SIZE)
783 page_length = PAGE_SIZE - shmem_page_offset;
785 /* If we don't overwrite a cacheline completely we need to be
786 * careful to have up-to-date data by first clflushing. Don't
787 * overcomplicate things and flush the entire patch. */
788 partial_cacheline_write = needs_clflush_before &&
789 ((shmem_page_offset | page_length)
790 & (boot_cpu_data.x86_clflush_size - 1));
792 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
793 (page_to_phys(page) & (1 << 17)) != 0;
795 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
796 user_data, page_do_bit17_swizzling,
797 partial_cacheline_write,
798 needs_clflush_after);
803 mutex_unlock(&dev->struct_mutex);
804 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
805 user_data, page_do_bit17_swizzling,
806 partial_cacheline_write,
807 needs_clflush_after);
809 mutex_lock(&dev->struct_mutex);
812 set_page_dirty(page);
813 mark_page_accessed(page);
818 remain -= page_length;
819 user_data += page_length;
820 offset += page_length;
824 i915_gem_object_unpin_pages(obj);
828 * Fixup: Flush cpu caches in case we didn't flush the dirty
829 * cachelines in-line while writing and the object moved
830 * out of the cpu write domain while we've dropped the lock.
832 if (!needs_clflush_after &&
833 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
834 i915_gem_clflush_object(obj);
835 i915_gem_chipset_flush(dev);
839 if (needs_clflush_after)
840 i915_gem_chipset_flush(dev);
846 * Writes data to the object referenced by handle.
848 * On error, the contents of the buffer that were to be modified are undefined.
851 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
852 struct drm_file *file)
854 struct drm_i915_gem_pwrite *args = data;
855 struct drm_i915_gem_object *obj;
861 if (!access_ok(VERIFY_READ,
862 to_user_ptr(args->data_ptr),
866 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
871 ret = i915_mutex_lock_interruptible(dev);
875 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
876 if (&obj->base == NULL) {
881 /* Bounds check destination. */
882 if (args->offset > obj->base.size ||
883 args->size > obj->base.size - args->offset) {
888 /* prime objects have no backing filp to GEM pread/pwrite
891 if (!obj->base.filp) {
896 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
899 /* We can only do the GTT pwrite on untiled buffers, as otherwise
900 * it would end up going through the fenced access, and we'll get
901 * different detiling behavior between reading and writing.
902 * pread/pwrite currently are reading and writing from the CPU
903 * perspective, requiring manual detiling by the client.
906 ret = i915_gem_phys_pwrite(dev, obj, args, file);
910 if (obj->cache_level == I915_CACHE_NONE &&
911 obj->tiling_mode == I915_TILING_NONE &&
912 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
913 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
914 /* Note that the gtt paths might fail with non-page-backed user
915 * pointers (e.g. gtt mappings when moving data between
916 * textures). Fallback to the shmem path in that case. */
919 if (ret == -EFAULT || ret == -ENOSPC)
920 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
923 drm_gem_object_unreference(&obj->base);
925 mutex_unlock(&dev->struct_mutex);
930 i915_gem_check_wedge(struct i915_gpu_error *error,
933 if (i915_reset_in_progress(error)) {
934 /* Non-interruptible callers can't handle -EAGAIN, hence return
935 * -EIO unconditionally for these. */
939 /* Recovery complete, but the reset failed ... */
940 if (i915_terminally_wedged(error))
950 * Compare seqno against outstanding lazy request. Emit a request if they are
954 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
958 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
961 if (seqno == ring->outstanding_lazy_request)
962 ret = i915_add_request(ring, NULL, NULL);
968 * __wait_seqno - wait until execution of seqno has finished
969 * @ring: the ring expected to report seqno
971 * @reset_counter: reset sequence associated with the given seqno
972 * @interruptible: do an interruptible wait (normally yes)
973 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
975 * Note: It is of utmost importance that the passed in seqno and reset_counter
976 * values have been read by the caller in an smp safe manner. Where read-side
977 * locks are involved, it is sufficient to read the reset_counter before
978 * unlocking the lock that protects the seqno. For lockless tricks, the
979 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
982 * Returns 0 if the seqno was found within the alloted time. Else returns the
983 * errno with remaining time filled in timeout argument.
985 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
986 unsigned reset_counter,
987 bool interruptible, struct timespec *timeout)
989 drm_i915_private_t *dev_priv = ring->dev->dev_private;
990 struct timespec before, now, wait_time={1,0};
991 unsigned long timeout_jiffies;
993 bool wait_forever = true;
996 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
999 trace_i915_gem_request_wait_begin(ring, seqno);
1001 if (timeout != NULL) {
1002 wait_time = *timeout;
1003 wait_forever = false;
1006 timeout_jiffies = timespec_to_jiffies(&wait_time);
1008 if (WARN_ON(!ring->irq_get(ring)))
1011 /* Record current time in case interrupted by signal, or wedged * */
1012 getrawmonotonic(&before);
1015 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1016 i915_reset_in_progress(&dev_priv->gpu_error) || \
1017 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1020 end = wait_event_interruptible_timeout(ring->irq_queue,
1024 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1027 /* We need to check whether any gpu reset happened in between
1028 * the caller grabbing the seqno and now ... */
1029 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1032 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1034 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1037 } while (end == 0 && wait_forever);
1039 getrawmonotonic(&now);
1041 ring->irq_put(ring);
1042 trace_i915_gem_request_wait_end(ring, seqno);
1046 struct timespec sleep_time = timespec_sub(now, before);
1047 *timeout = timespec_sub(*timeout, sleep_time);
1052 case -EAGAIN: /* Wedged */
1053 case -ERESTARTSYS: /* Signal */
1055 case 0: /* Timeout */
1057 set_normalized_timespec(timeout, 0, 0);
1059 default: /* Completed */
1060 WARN_ON(end < 0); /* We're not aware of other errors */
1066 * Waits for a sequence number to be signaled, and cleans up the
1067 * request and object lists appropriately for that event.
1070 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1072 struct drm_device *dev = ring->dev;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 bool interruptible = dev_priv->mm.interruptible;
1077 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1080 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1084 ret = i915_gem_check_olr(ring, seqno);
1088 return __wait_seqno(ring, seqno,
1089 atomic_read(&dev_priv->gpu_error.reset_counter),
1090 interruptible, NULL);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1101 struct intel_ring_buffer *ring = obj->ring;
1105 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109 ret = i915_wait_seqno(ring, seqno);
1113 i915_gem_retire_requests_ring(ring);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj->last_write_seqno &&
1119 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1120 obj->last_write_seqno = 0;
1121 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1134 struct drm_device *dev = obj->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 struct intel_ring_buffer *ring = obj->ring;
1137 unsigned reset_counter;
1141 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1142 BUG_ON(!dev_priv->mm.interruptible);
1144 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1148 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1152 ret = i915_gem_check_olr(ring, seqno);
1156 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1157 mutex_unlock(&dev->struct_mutex);
1158 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1159 mutex_lock(&dev->struct_mutex);
1161 i915_gem_retire_requests_ring(ring);
1163 /* Manually manage the write flush as we may have not yet
1164 * retired the buffer.
1166 if (obj->last_write_seqno &&
1167 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1168 obj->last_write_seqno = 0;
1169 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1176 * Called when user space prepares to use an object with the CPU, either
1177 * through the mmap ioctl's mapping or a GTT mapping.
1180 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1181 struct drm_file *file)
1183 struct drm_i915_gem_set_domain *args = data;
1184 struct drm_i915_gem_object *obj;
1185 uint32_t read_domains = args->read_domains;
1186 uint32_t write_domain = args->write_domain;
1189 /* Only handle setting domains to types used by the CPU. */
1190 if (write_domain & I915_GEM_GPU_DOMAINS)
1193 if (read_domains & I915_GEM_GPU_DOMAINS)
1196 /* Having something in the write domain implies it's in the read
1197 * domain, and only that read domain. Enforce that in the request.
1199 if (write_domain != 0 && read_domains != write_domain)
1202 ret = i915_mutex_lock_interruptible(dev);
1206 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1207 if (&obj->base == NULL) {
1212 /* Try to flush the object off the GPU without holding the lock.
1213 * We will repeat the flush holding the lock in the normal manner
1214 * to catch cases where we are gazumped.
1216 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1220 if (read_domains & I915_GEM_DOMAIN_GTT) {
1221 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223 /* Silently promote "you're not bound, there was nothing to do"
1224 * to success, since the client was just asking us to
1225 * make sure everything was done.
1230 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1234 drm_gem_object_unreference(&obj->base);
1236 mutex_unlock(&dev->struct_mutex);
1241 * Called when user space has done writes to this buffer
1244 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1245 struct drm_file *file)
1247 struct drm_i915_gem_sw_finish *args = data;
1248 struct drm_i915_gem_object *obj;
1251 ret = i915_mutex_lock_interruptible(dev);
1255 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1256 if (&obj->base == NULL) {
1261 /* Pinned buffers may be scanout, so flush the cache */
1263 i915_gem_object_flush_cpu_write_domain(obj);
1265 drm_gem_object_unreference(&obj->base);
1267 mutex_unlock(&dev->struct_mutex);
1272 * Maps the contents of an object, returning the address it is mapped
1275 * While the mapping holds a reference on the contents of the object, it doesn't
1276 * imply a ref on the object itself.
1279 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1280 struct drm_file *file)
1282 struct drm_i915_gem_mmap *args = data;
1283 struct drm_gem_object *obj;
1286 obj = drm_gem_object_lookup(dev, file, args->handle);
1290 /* prime objects have no backing filp to GEM mmap
1294 drm_gem_object_unreference_unlocked(obj);
1298 addr = vm_mmap(obj->filp, 0, args->size,
1299 PROT_READ | PROT_WRITE, MAP_SHARED,
1301 drm_gem_object_unreference_unlocked(obj);
1302 if (IS_ERR((void *)addr))
1305 args->addr_ptr = (uint64_t) addr;
1311 * i915_gem_fault - fault a page into the GTT
1312 * vma: VMA in question
1315 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1316 * from userspace. The fault handler takes care of binding the object to
1317 * the GTT (if needed), allocating and programming a fence register (again,
1318 * only if needed based on whether the old reg is still valid or the object
1319 * is tiled) and inserting a new PTE into the faulting process.
1321 * Note that the faulting process may involve evicting existing objects
1322 * from the GTT and/or fence registers to make room. So performance may
1323 * suffer if the GTT working set is large or there are few fence registers
1326 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1328 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1329 struct drm_device *dev = obj->base.dev;
1330 drm_i915_private_t *dev_priv = dev->dev_private;
1331 pgoff_t page_offset;
1334 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336 /* We don't use vmf->pgoff since that has the fake offset */
1337 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1340 ret = i915_mutex_lock_interruptible(dev);
1344 trace_i915_gem_object_fault(obj, page_offset, true, write);
1346 /* Access to snoopable pages through the GTT is incoherent. */
1347 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1352 /* Now bind it into the GTT if needed */
1353 ret = i915_gem_object_pin(obj, 0, true, false);
1357 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1361 ret = i915_gem_object_get_fence(obj);
1365 obj->fault_mappable = true;
1367 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1370 /* Finally, remap it using the new GTT offset */
1371 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1373 i915_gem_object_unpin(obj);
1375 mutex_unlock(&dev->struct_mutex);
1379 /* If this -EIO is due to a gpu hang, give the reset code a
1380 * chance to clean up the mess. Otherwise return the proper
1382 if (i915_terminally_wedged(&dev_priv->gpu_error))
1383 return VM_FAULT_SIGBUS;
1385 /* Give the error handler a chance to run and move the
1386 * objects off the GPU active list. Next time we service the
1387 * fault, we should be able to transition the page into the
1388 * GTT without touching the GPU (and so avoid further
1389 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1390 * with coherency, just lost writes.
1398 * EBUSY is ok: this just means that another thread
1399 * already did the job.
1401 return VM_FAULT_NOPAGE;
1403 return VM_FAULT_OOM;
1405 return VM_FAULT_SIGBUS;
1407 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1408 return VM_FAULT_SIGBUS;
1413 * i915_gem_release_mmap - remove physical page mappings
1414 * @obj: obj in question
1416 * Preserve the reservation of the mmapping with the DRM core code, but
1417 * relinquish ownership of the pages back to the system.
1419 * It is vital that we remove the page mapping if we have mapped a tiled
1420 * object through the GTT and then lose the fence register due to
1421 * resource pressure. Similarly if the object has been moved out of the
1422 * aperture, than pages mapped into userspace must be revoked. Removing the
1423 * mapping will then trigger a page fault on the next user access, allowing
1424 * fixup by i915_gem_fault().
1427 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1429 if (!obj->fault_mappable)
1432 if (obj->base.dev->dev_mapping)
1433 unmap_mapping_range(obj->base.dev->dev_mapping,
1434 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1437 obj->fault_mappable = false;
1441 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1445 if (INTEL_INFO(dev)->gen >= 4 ||
1446 tiling_mode == I915_TILING_NONE)
1449 /* Previous chips need a power-of-two fence region when tiling */
1450 if (INTEL_INFO(dev)->gen == 3)
1451 gtt_size = 1024*1024;
1453 gtt_size = 512*1024;
1455 while (gtt_size < size)
1462 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1463 * @obj: object to check
1465 * Return the required GTT alignment for an object, taking into account
1466 * potential fence register mapping.
1469 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1470 int tiling_mode, bool fenced)
1473 * Minimum alignment is 4k (GTT page size), but might be greater
1474 * if a fence register is needed for the object.
1476 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1477 tiling_mode == I915_TILING_NONE)
1481 * Previous chips need to be aligned to the size of the smallest
1482 * fence register that can contain the object.
1484 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1487 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1489 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1492 if (obj->base.map_list.map)
1495 dev_priv->mm.shrinker_no_lock_stealing = true;
1497 ret = drm_gem_create_mmap_offset(&obj->base);
1501 /* Badly fragmented mmap space? The only way we can recover
1502 * space is by destroying unwanted objects. We can't randomly release
1503 * mmap_offsets as userspace expects them to be persistent for the
1504 * lifetime of the objects. The closest we can is to release the
1505 * offsets on purgeable objects by truncating it and marking it purged,
1506 * which prevents userspace from ever using that object again.
1508 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1509 ret = drm_gem_create_mmap_offset(&obj->base);
1513 i915_gem_shrink_all(dev_priv);
1514 ret = drm_gem_create_mmap_offset(&obj->base);
1516 dev_priv->mm.shrinker_no_lock_stealing = false;
1521 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1523 if (!obj->base.map_list.map)
1526 drm_gem_free_mmap_offset(&obj->base);
1530 i915_gem_mmap_gtt(struct drm_file *file,
1531 struct drm_device *dev,
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 struct drm_i915_gem_object *obj;
1539 ret = i915_mutex_lock_interruptible(dev);
1543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1544 if (&obj->base == NULL) {
1549 if (obj->base.size > dev_priv->gtt.mappable_end) {
1554 if (obj->madv != I915_MADV_WILLNEED) {
1555 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1560 ret = i915_gem_object_create_mmap_offset(obj);
1564 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1567 drm_gem_object_unreference(&obj->base);
1569 mutex_unlock(&dev->struct_mutex);
1574 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1576 * @data: GTT mapping ioctl data
1577 * @file: GEM object info
1579 * Simply returns the fake offset to userspace so it can mmap it.
1580 * The mmap call will end up in drm_gem_mmap(), which will set things
1581 * up so we can get faults in the handler above.
1583 * The fault handler will take care of binding the object into the GTT
1584 * (since it may have been evicted to make room for something), allocating
1585 * a fence register, and mapping the appropriate aperture address into
1589 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1590 struct drm_file *file)
1592 struct drm_i915_gem_mmap_gtt *args = data;
1594 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1597 /* Immediately discard the backing storage */
1599 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1601 struct inode *inode;
1603 i915_gem_object_free_mmap_offset(obj);
1605 if (obj->base.filp == NULL)
1608 /* Our goal here is to return as much of the memory as
1609 * is possible back to the system as we are called from OOM.
1610 * To do this we must instruct the shmfs to drop all of its
1611 * backing pages, *now*.
1613 inode = file_inode(obj->base.filp);
1614 shmem_truncate_range(inode, 0, (loff_t)-1);
1616 obj->madv = __I915_MADV_PURGED;
1620 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1622 return obj->madv == I915_MADV_DONTNEED;
1626 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1628 struct sg_page_iter sg_iter;
1631 BUG_ON(obj->madv == __I915_MADV_PURGED);
1633 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1635 /* In the event of a disaster, abandon all caches and
1636 * hope for the best.
1638 WARN_ON(ret != -EIO);
1639 i915_gem_clflush_object(obj);
1640 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1643 if (i915_gem_object_needs_bit17_swizzle(obj))
1644 i915_gem_object_save_bit_17_swizzle(obj);
1646 if (obj->madv == I915_MADV_DONTNEED)
1649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1650 struct page *page = sg_page_iter_page(&sg_iter);
1653 set_page_dirty(page);
1655 if (obj->madv == I915_MADV_WILLNEED)
1656 mark_page_accessed(page);
1658 page_cache_release(page);
1662 sg_free_table(obj->pages);
1667 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1669 const struct drm_i915_gem_object_ops *ops = obj->ops;
1671 if (obj->pages == NULL)
1674 BUG_ON(obj->gtt_space);
1676 if (obj->pages_pin_count)
1679 /* ->put_pages might need to allocate memory for the bit17 swizzle
1680 * array, hence protect them from being reaped by removing them from gtt
1682 list_del(&obj->gtt_list);
1684 ops->put_pages(obj);
1687 if (i915_gem_object_is_purgeable(obj))
1688 i915_gem_object_truncate(obj);
1694 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1695 bool purgeable_only)
1697 struct drm_i915_gem_object *obj, *next;
1700 list_for_each_entry_safe(obj, next,
1701 &dev_priv->mm.unbound_list,
1703 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1704 i915_gem_object_put_pages(obj) == 0) {
1705 count += obj->base.size >> PAGE_SHIFT;
1706 if (count >= target)
1711 list_for_each_entry_safe(obj, next,
1712 &dev_priv->mm.inactive_list,
1714 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1715 i915_gem_object_unbind(obj) == 0 &&
1716 i915_gem_object_put_pages(obj) == 0) {
1717 count += obj->base.size >> PAGE_SHIFT;
1718 if (count >= target)
1727 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1729 return __i915_gem_shrink(dev_priv, target, true);
1733 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1735 struct drm_i915_gem_object *obj, *next;
1737 i915_gem_evict_everything(dev_priv->dev);
1739 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1740 i915_gem_object_put_pages(obj);
1744 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1746 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1748 struct address_space *mapping;
1749 struct sg_table *st;
1750 struct scatterlist *sg;
1751 struct sg_page_iter sg_iter;
1753 unsigned long last_pfn = 0; /* suppress gcc warning */
1756 /* Assert that the object is not currently in any GPU domain. As it
1757 * wasn't in the GTT, there shouldn't be any way it could have been in
1760 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1761 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1763 st = kmalloc(sizeof(*st), GFP_KERNEL);
1767 page_count = obj->base.size / PAGE_SIZE;
1768 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1774 /* Get the list of pages out of our struct file. They'll be pinned
1775 * at this point until we release them.
1777 * Fail silently without starting the shrinker
1779 mapping = file_inode(obj->base.filp)->i_mapping;
1780 gfp = mapping_gfp_mask(mapping);
1781 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1782 gfp &= ~(__GFP_IO | __GFP_WAIT);
1785 for (i = 0; i < page_count; i++) {
1786 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1788 i915_gem_purge(dev_priv, page_count);
1789 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1792 /* We've tried hard to allocate the memory by reaping
1793 * our own buffer, now let the real VM do its job and
1794 * go down in flames if truly OOM.
1796 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1797 gfp |= __GFP_IO | __GFP_WAIT;
1799 i915_gem_shrink_all(dev_priv);
1800 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1804 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1805 gfp &= ~(__GFP_IO | __GFP_WAIT);
1808 if (!i || page_to_pfn(page) != last_pfn + 1) {
1812 sg_set_page(sg, page, PAGE_SIZE, 0);
1814 sg->length += PAGE_SIZE;
1816 last_pfn = page_to_pfn(page);
1822 if (i915_gem_object_needs_bit17_swizzle(obj))
1823 i915_gem_object_do_bit_17_swizzle(obj);
1829 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1830 page_cache_release(sg_page_iter_page(&sg_iter));
1833 return PTR_ERR(page);
1836 /* Ensure that the associated pages are gathered from the backing storage
1837 * and pinned into our object. i915_gem_object_get_pages() may be called
1838 * multiple times before they are released by a single call to
1839 * i915_gem_object_put_pages() - once the pages are no longer referenced
1840 * either as a result of memory pressure (reaping pages under the shrinker)
1841 * or as the object is itself released.
1844 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1846 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1847 const struct drm_i915_gem_object_ops *ops = obj->ops;
1853 if (obj->madv != I915_MADV_WILLNEED) {
1854 DRM_ERROR("Attempting to obtain a purgeable object\n");
1858 BUG_ON(obj->pages_pin_count);
1860 ret = ops->get_pages(obj);
1864 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1869 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1870 struct intel_ring_buffer *ring)
1872 struct drm_device *dev = obj->base.dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 u32 seqno = intel_ring_get_seqno(ring);
1876 BUG_ON(ring == NULL);
1879 /* Add a reference if we're newly entering the active list. */
1881 drm_gem_object_reference(&obj->base);
1885 /* Move from whatever list we were on to the tail of execution. */
1886 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1887 list_move_tail(&obj->ring_list, &ring->active_list);
1889 obj->last_read_seqno = seqno;
1891 if (obj->fenced_gpu_access) {
1892 obj->last_fenced_seqno = seqno;
1894 /* Bump MRU to take account of the delayed flush */
1895 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1896 struct drm_i915_fence_reg *reg;
1898 reg = &dev_priv->fence_regs[obj->fence_reg];
1899 list_move_tail(®->lru_list,
1900 &dev_priv->mm.fence_list);
1906 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1908 struct drm_device *dev = obj->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1911 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1912 BUG_ON(!obj->active);
1914 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1916 list_del_init(&obj->ring_list);
1919 obj->last_read_seqno = 0;
1920 obj->last_write_seqno = 0;
1921 obj->base.write_domain = 0;
1923 obj->last_fenced_seqno = 0;
1924 obj->fenced_gpu_access = false;
1927 drm_gem_object_unreference(&obj->base);
1929 WARN_ON(i915_verify_lists(dev));
1933 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_ring_buffer *ring;
1939 /* Carefully retire all requests without writing to the rings */
1940 for_each_ring(ring, dev_priv, i) {
1941 ret = intel_ring_idle(ring);
1945 i915_gem_retire_requests(dev);
1947 /* Finally reset hw state */
1948 for_each_ring(ring, dev_priv, i) {
1949 intel_ring_init_seqno(ring, seqno);
1951 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1952 ring->sync_seqno[j] = 0;
1958 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1966 /* HWS page needs to be set less than what we
1967 * will inject to ring
1969 ret = i915_gem_init_seqno(dev, seqno - 1);
1973 /* Carefully set the last_seqno value so that wrap
1974 * detection still works
1976 dev_priv->next_seqno = seqno;
1977 dev_priv->last_seqno = seqno - 1;
1978 if (dev_priv->last_seqno == 0)
1979 dev_priv->last_seqno--;
1985 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1989 /* reserve 0 for non-seqno */
1990 if (dev_priv->next_seqno == 0) {
1991 int ret = i915_gem_init_seqno(dev, 0);
1995 dev_priv->next_seqno = 1;
1998 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2003 i915_add_request(struct intel_ring_buffer *ring,
2004 struct drm_file *file,
2007 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2008 struct drm_i915_gem_request *request;
2009 u32 request_ring_position;
2014 * Emit any outstanding flushes - execbuf can fail to emit the flush
2015 * after having emitted the batchbuffer command. Hence we need to fix
2016 * things up similar to emitting the lazy request. The difference here
2017 * is that the flush _must_ happen before the next request, no matter
2020 ret = intel_ring_flush_all_caches(ring);
2024 request = kmalloc(sizeof(*request), GFP_KERNEL);
2025 if (request == NULL)
2029 /* Record the position of the start of the request so that
2030 * should we detect the updated seqno part-way through the
2031 * GPU processing the request, we never over-estimate the
2032 * position of the head.
2034 request_ring_position = intel_ring_get_tail(ring);
2036 ret = ring->add_request(ring);
2042 request->seqno = intel_ring_get_seqno(ring);
2043 request->ring = ring;
2044 request->tail = request_ring_position;
2045 request->ctx = ring->last_context;
2048 i915_gem_context_reference(request->ctx);
2050 request->emitted_jiffies = jiffies;
2051 was_empty = list_empty(&ring->request_list);
2052 list_add_tail(&request->list, &ring->request_list);
2053 request->file_priv = NULL;
2056 struct drm_i915_file_private *file_priv = file->driver_priv;
2058 spin_lock(&file_priv->mm.lock);
2059 request->file_priv = file_priv;
2060 list_add_tail(&request->client_list,
2061 &file_priv->mm.request_list);
2062 spin_unlock(&file_priv->mm.lock);
2065 trace_i915_gem_request_add(ring, request->seqno);
2066 ring->outstanding_lazy_request = 0;
2068 if (!dev_priv->mm.suspended) {
2069 if (i915_enable_hangcheck) {
2070 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2071 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2074 queue_delayed_work(dev_priv->wq,
2075 &dev_priv->mm.retire_work,
2076 round_jiffies_up_relative(HZ));
2077 intel_mark_busy(dev_priv->dev);
2082 *out_seqno = request->seqno;
2087 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2089 struct drm_i915_file_private *file_priv = request->file_priv;
2094 spin_lock(&file_priv->mm.lock);
2095 if (request->file_priv) {
2096 list_del(&request->client_list);
2097 request->file_priv = NULL;
2099 spin_unlock(&file_priv->mm.lock);
2102 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2104 list_del(&request->list);
2105 i915_gem_request_remove_from_client(request);
2108 i915_gem_context_unreference(request->ctx);
2113 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2114 struct intel_ring_buffer *ring)
2116 while (!list_empty(&ring->request_list)) {
2117 struct drm_i915_gem_request *request;
2119 request = list_first_entry(&ring->request_list,
2120 struct drm_i915_gem_request,
2123 i915_gem_free_request(request);
2126 while (!list_empty(&ring->active_list)) {
2127 struct drm_i915_gem_object *obj;
2129 obj = list_first_entry(&ring->active_list,
2130 struct drm_i915_gem_object,
2133 i915_gem_object_move_to_inactive(obj);
2137 static void i915_gem_reset_fences(struct drm_device *dev)
2139 struct drm_i915_private *dev_priv = dev->dev_private;
2142 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2143 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2146 i915_gem_object_fence_lost(reg->obj);
2148 i915_gem_write_fence(dev, i, NULL);
2152 INIT_LIST_HEAD(®->lru_list);
2155 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2158 void i915_gem_reset(struct drm_device *dev)
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 struct drm_i915_gem_object *obj;
2162 struct intel_ring_buffer *ring;
2165 for_each_ring(ring, dev_priv, i)
2166 i915_gem_reset_ring_lists(dev_priv, ring);
2168 /* Move everything out of the GPU domains to ensure we do any
2169 * necessary invalidation upon reuse.
2171 list_for_each_entry(obj,
2172 &dev_priv->mm.inactive_list,
2175 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2178 /* The fence registers are invalidated so clear them out */
2179 i915_gem_reset_fences(dev);
2183 * This function clears the request list as sequence numbers are passed.
2186 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2190 if (list_empty(&ring->request_list))
2193 WARN_ON(i915_verify_lists(ring->dev));
2195 seqno = ring->get_seqno(ring, true);
2197 while (!list_empty(&ring->request_list)) {
2198 struct drm_i915_gem_request *request;
2200 request = list_first_entry(&ring->request_list,
2201 struct drm_i915_gem_request,
2204 if (!i915_seqno_passed(seqno, request->seqno))
2207 trace_i915_gem_request_retire(ring, request->seqno);
2208 /* We know the GPU must have read the request to have
2209 * sent us the seqno + interrupt, so use the position
2210 * of tail of the request to update the last known position
2213 ring->last_retired_head = request->tail;
2215 i915_gem_free_request(request);
2218 /* Move any buffers on the active list that are no longer referenced
2219 * by the ringbuffer to the flushing/inactive lists as appropriate.
2221 while (!list_empty(&ring->active_list)) {
2222 struct drm_i915_gem_object *obj;
2224 obj = list_first_entry(&ring->active_list,
2225 struct drm_i915_gem_object,
2228 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2231 i915_gem_object_move_to_inactive(obj);
2234 if (unlikely(ring->trace_irq_seqno &&
2235 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2236 ring->irq_put(ring);
2237 ring->trace_irq_seqno = 0;
2240 WARN_ON(i915_verify_lists(ring->dev));
2244 i915_gem_retire_requests(struct drm_device *dev)
2246 drm_i915_private_t *dev_priv = dev->dev_private;
2247 struct intel_ring_buffer *ring;
2250 for_each_ring(ring, dev_priv, i)
2251 i915_gem_retire_requests_ring(ring);
2255 i915_gem_retire_work_handler(struct work_struct *work)
2257 drm_i915_private_t *dev_priv;
2258 struct drm_device *dev;
2259 struct intel_ring_buffer *ring;
2263 dev_priv = container_of(work, drm_i915_private_t,
2264 mm.retire_work.work);
2265 dev = dev_priv->dev;
2267 /* Come back later if the device is busy... */
2268 if (!mutex_trylock(&dev->struct_mutex)) {
2269 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2270 round_jiffies_up_relative(HZ));
2274 i915_gem_retire_requests(dev);
2276 /* Send a periodic flush down the ring so we don't hold onto GEM
2277 * objects indefinitely.
2280 for_each_ring(ring, dev_priv, i) {
2281 if (ring->gpu_caches_dirty)
2282 i915_add_request(ring, NULL, NULL);
2284 idle &= list_empty(&ring->request_list);
2287 if (!dev_priv->mm.suspended && !idle)
2288 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2289 round_jiffies_up_relative(HZ));
2291 intel_mark_idle(dev);
2293 mutex_unlock(&dev->struct_mutex);
2297 * Ensures that an object will eventually get non-busy by flushing any required
2298 * write domains, emitting any outstanding lazy request and retiring and
2299 * completed requests.
2302 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2307 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2311 i915_gem_retire_requests_ring(obj->ring);
2318 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2319 * @DRM_IOCTL_ARGS: standard ioctl arguments
2321 * Returns 0 if successful, else an error is returned with the remaining time in
2322 * the timeout parameter.
2323 * -ETIME: object is still busy after timeout
2324 * -ERESTARTSYS: signal interrupted the wait
2325 * -ENONENT: object doesn't exist
2326 * Also possible, but rare:
2327 * -EAGAIN: GPU wedged
2329 * -ENODEV: Internal IRQ fail
2330 * -E?: The add request failed
2332 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2333 * non-zero timeout parameter the wait ioctl will wait for the given number of
2334 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2335 * without holding struct_mutex the object may become re-busied before this
2336 * function completes. A similar but shorter * race condition exists in the busy
2340 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2342 drm_i915_private_t *dev_priv = dev->dev_private;
2343 struct drm_i915_gem_wait *args = data;
2344 struct drm_i915_gem_object *obj;
2345 struct intel_ring_buffer *ring = NULL;
2346 struct timespec timeout_stack, *timeout = NULL;
2347 unsigned reset_counter;
2351 if (args->timeout_ns >= 0) {
2352 timeout_stack = ns_to_timespec(args->timeout_ns);
2353 timeout = &timeout_stack;
2356 ret = i915_mutex_lock_interruptible(dev);
2360 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2361 if (&obj->base == NULL) {
2362 mutex_unlock(&dev->struct_mutex);
2366 /* Need to make sure the object gets inactive eventually. */
2367 ret = i915_gem_object_flush_active(obj);
2372 seqno = obj->last_read_seqno;
2379 /* Do this after OLR check to make sure we make forward progress polling
2380 * on this IOCTL with a 0 timeout (like busy ioctl)
2382 if (!args->timeout_ns) {
2387 drm_gem_object_unreference(&obj->base);
2388 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2389 mutex_unlock(&dev->struct_mutex);
2391 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2393 WARN_ON(!timespec_valid(timeout));
2394 args->timeout_ns = timespec_to_ns(timeout);
2399 drm_gem_object_unreference(&obj->base);
2400 mutex_unlock(&dev->struct_mutex);
2405 * i915_gem_object_sync - sync an object to a ring.
2407 * @obj: object which may be in use on another ring.
2408 * @to: ring we wish to use the object on. May be NULL.
2410 * This code is meant to abstract object synchronization with the GPU.
2411 * Calling with NULL implies synchronizing the object with the CPU
2412 * rather than a particular GPU ring.
2414 * Returns 0 if successful, else propagates up the lower layer error.
2417 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2418 struct intel_ring_buffer *to)
2420 struct intel_ring_buffer *from = obj->ring;
2424 if (from == NULL || to == from)
2427 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2428 return i915_gem_object_wait_rendering(obj, false);
2430 idx = intel_ring_sync_index(from, to);
2432 seqno = obj->last_read_seqno;
2433 if (seqno <= from->sync_seqno[idx])
2436 ret = i915_gem_check_olr(obj->ring, seqno);
2440 ret = to->sync_to(to, from, seqno);
2442 /* We use last_read_seqno because sync_to()
2443 * might have just caused seqno wrap under
2446 from->sync_seqno[idx] = obj->last_read_seqno;
2451 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2453 u32 old_write_domain, old_read_domains;
2455 /* Force a pagefault for domain tracking on next user access */
2456 i915_gem_release_mmap(obj);
2458 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2461 /* Wait for any direct GTT access to complete */
2464 old_read_domains = obj->base.read_domains;
2465 old_write_domain = obj->base.write_domain;
2467 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2468 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2470 trace_i915_gem_object_change_domain(obj,
2476 * Unbinds an object from the GTT aperture.
2479 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2481 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2484 if (obj->gtt_space == NULL)
2490 BUG_ON(obj->pages == NULL);
2492 ret = i915_gem_object_finish_gpu(obj);
2495 /* Continue on if we fail due to EIO, the GPU is hung so we
2496 * should be safe and we need to cleanup or else we might
2497 * cause memory corruption through use-after-free.
2500 i915_gem_object_finish_gtt(obj);
2502 /* release the fence reg _after_ flushing */
2503 ret = i915_gem_object_put_fence(obj);
2507 trace_i915_gem_object_unbind(obj);
2509 if (obj->has_global_gtt_mapping)
2510 i915_gem_gtt_unbind_object(obj);
2511 if (obj->has_aliasing_ppgtt_mapping) {
2512 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2513 obj->has_aliasing_ppgtt_mapping = 0;
2515 i915_gem_gtt_finish_object(obj);
2517 list_del(&obj->mm_list);
2518 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2519 /* Avoid an unnecessary call to unbind on rebind. */
2520 obj->map_and_fenceable = true;
2522 drm_mm_put_block(obj->gtt_space);
2523 obj->gtt_space = NULL;
2524 obj->gtt_offset = 0;
2529 int i915_gpu_idle(struct drm_device *dev)
2531 drm_i915_private_t *dev_priv = dev->dev_private;
2532 struct intel_ring_buffer *ring;
2535 /* Flush everything onto the inactive list. */
2536 for_each_ring(ring, dev_priv, i) {
2537 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2541 ret = intel_ring_idle(ring);
2549 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2550 struct drm_i915_gem_object *obj)
2552 drm_i915_private_t *dev_priv = dev->dev_private;
2554 int fence_pitch_shift;
2557 if (INTEL_INFO(dev)->gen >= 6) {
2558 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2559 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2561 fence_reg = FENCE_REG_965_0;
2562 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2566 u32 size = obj->gtt_space->size;
2568 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2570 val |= obj->gtt_offset & 0xfffff000;
2571 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2572 if (obj->tiling_mode == I915_TILING_Y)
2573 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2574 val |= I965_FENCE_REG_VALID;
2578 fence_reg += reg * 8;
2579 I915_WRITE64(fence_reg, val);
2580 POSTING_READ(fence_reg);
2583 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2584 struct drm_i915_gem_object *obj)
2586 drm_i915_private_t *dev_priv = dev->dev_private;
2590 u32 size = obj->gtt_space->size;
2594 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2595 (size & -size) != size ||
2596 (obj->gtt_offset & (size - 1)),
2597 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2598 obj->gtt_offset, obj->map_and_fenceable, size);
2600 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2605 /* Note: pitch better be a power of two tile widths */
2606 pitch_val = obj->stride / tile_width;
2607 pitch_val = ffs(pitch_val) - 1;
2609 val = obj->gtt_offset;
2610 if (obj->tiling_mode == I915_TILING_Y)
2611 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2612 val |= I915_FENCE_SIZE_BITS(size);
2613 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2614 val |= I830_FENCE_REG_VALID;
2619 reg = FENCE_REG_830_0 + reg * 4;
2621 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2623 I915_WRITE(reg, val);
2627 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2628 struct drm_i915_gem_object *obj)
2630 drm_i915_private_t *dev_priv = dev->dev_private;
2634 u32 size = obj->gtt_space->size;
2637 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2638 (size & -size) != size ||
2639 (obj->gtt_offset & (size - 1)),
2640 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2641 obj->gtt_offset, size);
2643 pitch_val = obj->stride / 128;
2644 pitch_val = ffs(pitch_val) - 1;
2646 val = obj->gtt_offset;
2647 if (obj->tiling_mode == I915_TILING_Y)
2648 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2649 val |= I830_FENCE_SIZE_BITS(size);
2650 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2651 val |= I830_FENCE_REG_VALID;
2655 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2656 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2659 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2661 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2664 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2665 struct drm_i915_gem_object *obj)
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2669 /* Ensure that all CPU reads are completed before installing a fence
2670 * and all writes before removing the fence.
2672 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2675 switch (INTEL_INFO(dev)->gen) {
2679 case 4: i965_write_fence_reg(dev, reg, obj); break;
2680 case 3: i915_write_fence_reg(dev, reg, obj); break;
2681 case 2: i830_write_fence_reg(dev, reg, obj); break;
2685 /* And similarly be paranoid that no direct access to this region
2686 * is reordered to before the fence is installed.
2688 if (i915_gem_object_needs_mb(obj))
2692 static inline int fence_number(struct drm_i915_private *dev_priv,
2693 struct drm_i915_fence_reg *fence)
2695 return fence - dev_priv->fence_regs;
2698 static void i915_gem_write_fence__ipi(void *data)
2703 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2704 struct drm_i915_fence_reg *fence,
2707 struct drm_device *dev = obj->base.dev;
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709 int fence_reg = fence_number(dev_priv, fence);
2711 /* In order to fully serialize access to the fenced region and
2712 * the update to the fence register we need to take extreme
2713 * measures on SNB+. In theory, the write to the fence register
2714 * flushes all memory transactions before, and coupled with the
2715 * mb() placed around the register write we serialise all memory
2716 * operations with respect to the changes in the tiler. Yet, on
2717 * SNB+ we need to take a step further and emit an explicit wbinvd()
2718 * on each processor in order to manually flush all memory
2719 * transactions before updating the fence register.
2721 if (HAS_LLC(obj->base.dev))
2722 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
2723 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2726 obj->fence_reg = fence_reg;
2728 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2730 obj->fence_reg = I915_FENCE_REG_NONE;
2732 list_del_init(&fence->lru_list);
2737 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2739 if (obj->last_fenced_seqno) {
2740 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2744 obj->last_fenced_seqno = 0;
2747 obj->fenced_gpu_access = false;
2752 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2754 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2755 struct drm_i915_fence_reg *fence;
2758 ret = i915_gem_object_wait_fence(obj);
2762 if (obj->fence_reg == I915_FENCE_REG_NONE)
2765 fence = &dev_priv->fence_regs[obj->fence_reg];
2767 i915_gem_object_fence_lost(obj);
2768 i915_gem_object_update_fence(obj, fence, false);
2773 static struct drm_i915_fence_reg *
2774 i915_find_fence_reg(struct drm_device *dev)
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct drm_i915_fence_reg *reg, *avail;
2780 /* First try to find a free reg */
2782 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2783 reg = &dev_priv->fence_regs[i];
2787 if (!reg->pin_count)
2794 /* None available, try to steal one or wait for a user to finish */
2795 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2806 * i915_gem_object_get_fence - set up fencing for an object
2807 * @obj: object to map through a fence reg
2809 * When mapping objects through the GTT, userspace wants to be able to write
2810 * to them without having to worry about swizzling if the object is tiled.
2811 * This function walks the fence regs looking for a free one for @obj,
2812 * stealing one if it can't find any.
2814 * It then sets up the reg based on the object's properties: address, pitch
2815 * and tiling format.
2817 * For an untiled surface, this removes any existing fence.
2820 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2822 struct drm_device *dev = obj->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 bool enable = obj->tiling_mode != I915_TILING_NONE;
2825 struct drm_i915_fence_reg *reg;
2828 /* Have we updated the tiling parameters upon the object and so
2829 * will need to serialise the write to the associated fence register?
2831 if (obj->fence_dirty) {
2832 ret = i915_gem_object_wait_fence(obj);
2837 /* Just update our place in the LRU if our fence is getting reused. */
2838 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2839 reg = &dev_priv->fence_regs[obj->fence_reg];
2840 if (!obj->fence_dirty) {
2841 list_move_tail(®->lru_list,
2842 &dev_priv->mm.fence_list);
2845 } else if (enable) {
2846 reg = i915_find_fence_reg(dev);
2851 struct drm_i915_gem_object *old = reg->obj;
2853 ret = i915_gem_object_wait_fence(old);
2857 i915_gem_object_fence_lost(old);
2862 i915_gem_object_update_fence(obj, reg, enable);
2863 obj->fence_dirty = false;
2868 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2869 struct drm_mm_node *gtt_space,
2870 unsigned long cache_level)
2872 struct drm_mm_node *other;
2874 /* On non-LLC machines we have to be careful when putting differing
2875 * types of snoopable memory together to avoid the prefetcher
2876 * crossing memory domains and dying.
2881 if (gtt_space == NULL)
2884 if (list_empty(>t_space->node_list))
2887 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2888 if (other->allocated && !other->hole_follows && other->color != cache_level)
2891 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2892 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2898 static void i915_gem_verify_gtt(struct drm_device *dev)
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct drm_i915_gem_object *obj;
2905 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2906 if (obj->gtt_space == NULL) {
2907 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2912 if (obj->cache_level != obj->gtt_space->color) {
2913 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2914 obj->gtt_space->start,
2915 obj->gtt_space->start + obj->gtt_space->size,
2917 obj->gtt_space->color);
2922 if (!i915_gem_valid_gtt_space(dev,
2924 obj->cache_level)) {
2925 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2926 obj->gtt_space->start,
2927 obj->gtt_space->start + obj->gtt_space->size,
2939 * Finds free space in the GTT aperture and binds the object there.
2942 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2944 bool map_and_fenceable,
2947 struct drm_device *dev = obj->base.dev;
2948 drm_i915_private_t *dev_priv = dev->dev_private;
2949 struct drm_mm_node *node;
2950 u32 size, fence_size, fence_alignment, unfenced_alignment;
2951 bool mappable, fenceable;
2954 fence_size = i915_gem_get_gtt_size(dev,
2957 fence_alignment = i915_gem_get_gtt_alignment(dev,
2959 obj->tiling_mode, true);
2960 unfenced_alignment =
2961 i915_gem_get_gtt_alignment(dev,
2963 obj->tiling_mode, false);
2966 alignment = map_and_fenceable ? fence_alignment :
2968 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2969 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2973 size = map_and_fenceable ? fence_size : obj->base.size;
2975 /* If the object is bigger than the entire aperture, reject it early
2976 * before evicting everything in a vain attempt to find space.
2978 if (obj->base.size >
2979 (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {
2980 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2984 ret = i915_gem_object_get_pages(obj);
2988 i915_gem_object_pin_pages(obj);
2990 node = kzalloc(sizeof(*node), GFP_KERNEL);
2992 i915_gem_object_unpin_pages(obj);
2997 if (map_and_fenceable)
2998 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
2999 size, alignment, obj->cache_level,
3000 0, dev_priv->gtt.mappable_end);
3002 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
3003 size, alignment, obj->cache_level);
3005 ret = i915_gem_evict_something(dev, size, alignment,
3012 i915_gem_object_unpin_pages(obj);
3016 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3017 i915_gem_object_unpin_pages(obj);
3018 drm_mm_put_block(node);
3022 ret = i915_gem_gtt_prepare_object(obj);
3024 i915_gem_object_unpin_pages(obj);
3025 drm_mm_put_block(node);
3029 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3030 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3032 obj->gtt_space = node;
3033 obj->gtt_offset = node->start;
3036 node->size == fence_size &&
3037 (node->start & (fence_alignment - 1)) == 0;
3040 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3042 obj->map_and_fenceable = mappable && fenceable;
3044 i915_gem_object_unpin_pages(obj);
3045 trace_i915_gem_object_bind(obj, map_and_fenceable);
3046 i915_gem_verify_gtt(dev);
3051 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3053 /* If we don't have a page list set up, then we're not pinned
3054 * to GPU, and we can ignore the cache flush because it'll happen
3055 * again at bind time.
3057 if (obj->pages == NULL)
3061 * Stolen memory is always coherent with the GPU as it is explicitly
3062 * marked as wc by the system, or the system is cache-coherent.
3067 /* If the GPU is snooping the contents of the CPU cache,
3068 * we do not need to manually clear the CPU cache lines. However,
3069 * the caches are only snooped when the render cache is
3070 * flushed/invalidated. As we always have to emit invalidations
3071 * and flushes when moving into and out of the RENDER domain, correct
3072 * snooping behaviour occurs naturally as the result of our domain
3075 if (obj->cache_level != I915_CACHE_NONE)
3078 trace_i915_gem_object_clflush(obj);
3080 drm_clflush_sg(obj->pages);
3083 /** Flushes the GTT write domain for the object if it's dirty. */
3085 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3087 uint32_t old_write_domain;
3089 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3092 /* No actual flushing is required for the GTT write domain. Writes
3093 * to it immediately go to main memory as far as we know, so there's
3094 * no chipset flush. It also doesn't land in render cache.
3096 * However, we do have to enforce the order so that all writes through
3097 * the GTT land before any writes to the device, such as updates to
3102 old_write_domain = obj->base.write_domain;
3103 obj->base.write_domain = 0;
3105 trace_i915_gem_object_change_domain(obj,
3106 obj->base.read_domains,
3110 /** Flushes the CPU write domain for the object if it's dirty. */
3112 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3114 uint32_t old_write_domain;
3116 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3119 i915_gem_clflush_object(obj);
3120 i915_gem_chipset_flush(obj->base.dev);
3121 old_write_domain = obj->base.write_domain;
3122 obj->base.write_domain = 0;
3124 trace_i915_gem_object_change_domain(obj,
3125 obj->base.read_domains,
3130 * Moves a single object to the GTT read, and possibly write domain.
3132 * This function returns when the move is complete, including waiting on
3136 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3138 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3139 uint32_t old_write_domain, old_read_domains;
3142 /* Not valid to be called on unbound objects. */
3143 if (obj->gtt_space == NULL)
3146 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3149 ret = i915_gem_object_wait_rendering(obj, !write);
3153 i915_gem_object_flush_cpu_write_domain(obj);
3155 /* Serialise direct access to this object with the barriers for
3156 * coherent writes from the GPU, by effectively invalidating the
3157 * GTT domain upon first access.
3159 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3162 old_write_domain = obj->base.write_domain;
3163 old_read_domains = obj->base.read_domains;
3165 /* It should now be out of any other write domains, and we can update
3166 * the domain values for our changes.
3168 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3169 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3171 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3172 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3176 trace_i915_gem_object_change_domain(obj,
3180 /* And bump the LRU for this access */
3181 if (i915_gem_object_is_inactive(obj))
3182 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3187 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3188 enum i915_cache_level cache_level)
3190 struct drm_device *dev = obj->base.dev;
3191 drm_i915_private_t *dev_priv = dev->dev_private;
3194 if (obj->cache_level == cache_level)
3197 if (obj->pin_count) {
3198 DRM_DEBUG("can not change the cache level of pinned objects\n");
3202 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3203 ret = i915_gem_object_unbind(obj);
3208 if (obj->gtt_space) {
3209 ret = i915_gem_object_finish_gpu(obj);
3213 i915_gem_object_finish_gtt(obj);
3215 /* Before SandyBridge, you could not use tiling or fence
3216 * registers with snooped memory, so relinquish any fences
3217 * currently pointing to our region in the aperture.
3219 if (INTEL_INFO(dev)->gen < 6) {
3220 ret = i915_gem_object_put_fence(obj);
3225 if (obj->has_global_gtt_mapping)
3226 i915_gem_gtt_bind_object(obj, cache_level);
3227 if (obj->has_aliasing_ppgtt_mapping)
3228 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3231 obj->gtt_space->color = cache_level;
3234 if (cache_level == I915_CACHE_NONE) {
3235 u32 old_read_domains, old_write_domain;
3237 /* If we're coming from LLC cached, then we haven't
3238 * actually been tracking whether the data is in the
3239 * CPU cache or not, since we only allow one bit set
3240 * in obj->write_domain and have been skipping the clflushes.
3241 * Just set it to the CPU cache for now.
3243 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3244 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3246 old_read_domains = obj->base.read_domains;
3247 old_write_domain = obj->base.write_domain;
3249 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3250 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3252 trace_i915_gem_object_change_domain(obj,
3257 obj->cache_level = cache_level;
3258 i915_gem_verify_gtt(dev);
3262 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3263 struct drm_file *file)
3265 struct drm_i915_gem_caching *args = data;
3266 struct drm_i915_gem_object *obj;
3269 ret = i915_mutex_lock_interruptible(dev);
3273 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3274 if (&obj->base == NULL) {
3279 args->caching = obj->cache_level != I915_CACHE_NONE;
3281 drm_gem_object_unreference(&obj->base);
3283 mutex_unlock(&dev->struct_mutex);
3287 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3288 struct drm_file *file)
3290 struct drm_i915_gem_caching *args = data;
3291 struct drm_i915_gem_object *obj;
3292 enum i915_cache_level level;
3295 switch (args->caching) {
3296 case I915_CACHING_NONE:
3297 level = I915_CACHE_NONE;
3299 case I915_CACHING_CACHED:
3300 level = I915_CACHE_LLC;
3306 ret = i915_mutex_lock_interruptible(dev);
3310 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3311 if (&obj->base == NULL) {
3316 ret = i915_gem_object_set_cache_level(obj, level);
3318 drm_gem_object_unreference(&obj->base);
3320 mutex_unlock(&dev->struct_mutex);
3325 * Prepare buffer for display plane (scanout, cursors, etc).
3326 * Can be called from an uninterruptible phase (modesetting) and allows
3327 * any flushes to be pipelined (for pageflips).
3330 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3332 struct intel_ring_buffer *pipelined)
3334 u32 old_read_domains, old_write_domain;
3337 if (pipelined != obj->ring) {
3338 ret = i915_gem_object_sync(obj, pipelined);
3343 /* The display engine is not coherent with the LLC cache on gen6. As
3344 * a result, we make sure that the pinning that is about to occur is
3345 * done with uncached PTEs. This is lowest common denominator for all
3348 * However for gen6+, we could do better by using the GFDT bit instead
3349 * of uncaching, which would allow us to flush all the LLC-cached data
3350 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3352 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3356 /* As the user may map the buffer once pinned in the display plane
3357 * (e.g. libkms for the bootup splash), we have to ensure that we
3358 * always use map_and_fenceable for all scanout buffers.
3360 ret = i915_gem_object_pin(obj, alignment, true, false);
3364 i915_gem_object_flush_cpu_write_domain(obj);
3366 old_write_domain = obj->base.write_domain;
3367 old_read_domains = obj->base.read_domains;
3369 /* It should now be out of any other write domains, and we can update
3370 * the domain values for our changes.
3372 obj->base.write_domain = 0;
3373 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3375 trace_i915_gem_object_change_domain(obj,
3383 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3387 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3390 ret = i915_gem_object_wait_rendering(obj, false);
3394 /* Ensure that we invalidate the GPU's caches and TLBs. */
3395 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3400 * Moves a single object to the CPU read, and possibly write domain.
3402 * This function returns when the move is complete, including waiting on
3406 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3408 uint32_t old_write_domain, old_read_domains;
3411 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3414 ret = i915_gem_object_wait_rendering(obj, !write);
3418 i915_gem_object_flush_gtt_write_domain(obj);
3420 old_write_domain = obj->base.write_domain;
3421 old_read_domains = obj->base.read_domains;
3423 /* Flush the CPU cache if it's still invalid. */
3424 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3425 i915_gem_clflush_object(obj);
3427 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3430 /* It should now be out of any other write domains, and we can update
3431 * the domain values for our changes.
3433 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3435 /* If we're writing through the CPU, then the GPU read domains will
3436 * need to be invalidated at next use.
3439 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3440 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3443 trace_i915_gem_object_change_domain(obj,
3450 /* Throttle our rendering by waiting until the ring has completed our requests
3451 * emitted over 20 msec ago.
3453 * Note that if we were to use the current jiffies each time around the loop,
3454 * we wouldn't escape the function with any frames outstanding if the time to
3455 * render a frame was over 20ms.
3457 * This should get us reasonable parallelism between CPU and GPU but also
3458 * relatively low latency when blocking on a particular request to finish.
3461 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct drm_i915_file_private *file_priv = file->driver_priv;
3465 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3466 struct drm_i915_gem_request *request;
3467 struct intel_ring_buffer *ring = NULL;
3468 unsigned reset_counter;
3472 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3476 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3480 spin_lock(&file_priv->mm.lock);
3481 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3482 if (time_after_eq(request->emitted_jiffies, recent_enough))
3485 ring = request->ring;
3486 seqno = request->seqno;
3488 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3489 spin_unlock(&file_priv->mm.lock);
3494 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3496 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3502 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3504 bool map_and_fenceable,
3509 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3512 if (obj->gtt_space != NULL) {
3513 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3514 (map_and_fenceable && !obj->map_and_fenceable)) {
3515 WARN(obj->pin_count,
3516 "bo is already pinned with incorrect alignment:"
3517 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3518 " obj->map_and_fenceable=%d\n",
3519 obj->gtt_offset, alignment,
3521 obj->map_and_fenceable);
3522 ret = i915_gem_object_unbind(obj);
3528 if (obj->gtt_space == NULL) {
3529 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3531 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3537 if (!dev_priv->mm.aliasing_ppgtt)
3538 i915_gem_gtt_bind_object(obj, obj->cache_level);
3541 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3542 i915_gem_gtt_bind_object(obj, obj->cache_level);
3545 obj->pin_mappable |= map_and_fenceable;
3551 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3553 BUG_ON(obj->pin_count == 0);
3554 BUG_ON(obj->gtt_space == NULL);
3556 if (--obj->pin_count == 0)
3557 obj->pin_mappable = false;
3561 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3562 struct drm_file *file)
3564 struct drm_i915_gem_pin *args = data;
3565 struct drm_i915_gem_object *obj;
3568 ret = i915_mutex_lock_interruptible(dev);
3572 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3573 if (&obj->base == NULL) {
3578 if (obj->madv != I915_MADV_WILLNEED) {
3579 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3584 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3585 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3591 if (obj->user_pin_count == 0) {
3592 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3597 obj->user_pin_count++;
3598 obj->pin_filp = file;
3600 /* XXX - flush the CPU caches for pinned objects
3601 * as the X server doesn't manage domains yet
3603 i915_gem_object_flush_cpu_write_domain(obj);
3604 args->offset = obj->gtt_offset;
3606 drm_gem_object_unreference(&obj->base);
3608 mutex_unlock(&dev->struct_mutex);
3613 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3614 struct drm_file *file)
3616 struct drm_i915_gem_pin *args = data;
3617 struct drm_i915_gem_object *obj;
3620 ret = i915_mutex_lock_interruptible(dev);
3624 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3625 if (&obj->base == NULL) {
3630 if (obj->pin_filp != file) {
3631 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3636 obj->user_pin_count--;
3637 if (obj->user_pin_count == 0) {
3638 obj->pin_filp = NULL;
3639 i915_gem_object_unpin(obj);
3643 drm_gem_object_unreference(&obj->base);
3645 mutex_unlock(&dev->struct_mutex);
3650 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3651 struct drm_file *file)
3653 struct drm_i915_gem_busy *args = data;
3654 struct drm_i915_gem_object *obj;
3657 ret = i915_mutex_lock_interruptible(dev);
3661 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3662 if (&obj->base == NULL) {
3667 /* Count all active objects as busy, even if they are currently not used
3668 * by the gpu. Users of this interface expect objects to eventually
3669 * become non-busy without any further actions, therefore emit any
3670 * necessary flushes here.
3672 ret = i915_gem_object_flush_active(obj);
3674 args->busy = obj->active;
3676 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3677 args->busy |= intel_ring_flag(obj->ring) << 16;
3680 drm_gem_object_unreference(&obj->base);
3682 mutex_unlock(&dev->struct_mutex);
3687 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3688 struct drm_file *file_priv)
3690 return i915_gem_ring_throttle(dev, file_priv);
3694 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3695 struct drm_file *file_priv)
3697 struct drm_i915_gem_madvise *args = data;
3698 struct drm_i915_gem_object *obj;
3701 switch (args->madv) {
3702 case I915_MADV_DONTNEED:
3703 case I915_MADV_WILLNEED:
3709 ret = i915_mutex_lock_interruptible(dev);
3713 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3714 if (&obj->base == NULL) {
3719 if (obj->pin_count) {
3724 if (obj->madv != __I915_MADV_PURGED)
3725 obj->madv = args->madv;
3727 /* if the object is no longer attached, discard its backing storage */
3728 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3729 i915_gem_object_truncate(obj);
3731 args->retained = obj->madv != __I915_MADV_PURGED;
3734 drm_gem_object_unreference(&obj->base);
3736 mutex_unlock(&dev->struct_mutex);
3740 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3741 const struct drm_i915_gem_object_ops *ops)
3743 INIT_LIST_HEAD(&obj->mm_list);
3744 INIT_LIST_HEAD(&obj->gtt_list);
3745 INIT_LIST_HEAD(&obj->ring_list);
3746 INIT_LIST_HEAD(&obj->exec_list);
3750 obj->fence_reg = I915_FENCE_REG_NONE;
3751 obj->madv = I915_MADV_WILLNEED;
3752 /* Avoid an unnecessary call to unbind on the first bind. */
3753 obj->map_and_fenceable = true;
3755 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3758 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3759 .get_pages = i915_gem_object_get_pages_gtt,
3760 .put_pages = i915_gem_object_put_pages_gtt,
3763 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3766 struct drm_i915_gem_object *obj;
3767 struct address_space *mapping;
3770 obj = i915_gem_object_alloc(dev);
3774 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3775 i915_gem_object_free(obj);
3779 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3780 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3781 /* 965gm cannot relocate objects above 4GiB. */
3782 mask &= ~__GFP_HIGHMEM;
3783 mask |= __GFP_DMA32;
3786 mapping = file_inode(obj->base.filp)->i_mapping;
3787 mapping_set_gfp_mask(mapping, mask);
3789 i915_gem_object_init(obj, &i915_gem_object_ops);
3791 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3792 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3795 /* On some devices, we can have the GPU use the LLC (the CPU
3796 * cache) for about a 10% performance improvement
3797 * compared to uncached. Graphics requests other than
3798 * display scanout are coherent with the CPU in
3799 * accessing this cache. This means in this mode we
3800 * don't need to clflush on the CPU side, and on the
3801 * GPU side we only need to flush internal caches to
3802 * get data visible to the CPU.
3804 * However, we maintain the display planes as UC, and so
3805 * need to rebind when first used as such.
3807 obj->cache_level = I915_CACHE_LLC;
3809 obj->cache_level = I915_CACHE_NONE;
3814 int i915_gem_init_object(struct drm_gem_object *obj)
3821 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3823 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3824 struct drm_device *dev = obj->base.dev;
3825 drm_i915_private_t *dev_priv = dev->dev_private;
3827 trace_i915_gem_object_destroy(obj);
3830 i915_gem_detach_phys_object(dev, obj);
3833 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3834 bool was_interruptible;
3836 was_interruptible = dev_priv->mm.interruptible;
3837 dev_priv->mm.interruptible = false;
3839 WARN_ON(i915_gem_object_unbind(obj));
3841 dev_priv->mm.interruptible = was_interruptible;
3844 obj->pages_pin_count = 0;
3845 i915_gem_object_put_pages(obj);
3846 i915_gem_object_free_mmap_offset(obj);
3847 i915_gem_object_release_stolen(obj);
3851 if (obj->base.import_attach)
3852 drm_prime_gem_destroy(&obj->base, NULL);
3854 drm_gem_object_release(&obj->base);
3855 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3858 i915_gem_object_free(obj);
3862 i915_gem_idle(struct drm_device *dev)
3864 drm_i915_private_t *dev_priv = dev->dev_private;
3867 mutex_lock(&dev->struct_mutex);
3869 if (dev_priv->mm.suspended) {
3870 mutex_unlock(&dev->struct_mutex);
3874 ret = i915_gpu_idle(dev);
3876 mutex_unlock(&dev->struct_mutex);
3879 i915_gem_retire_requests(dev);
3881 /* Under UMS, be paranoid and evict. */
3882 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3883 i915_gem_evict_everything(dev);
3885 i915_gem_reset_fences(dev);
3887 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3888 * We need to replace this with a semaphore, or something.
3889 * And not confound mm.suspended!
3891 dev_priv->mm.suspended = 1;
3892 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3894 i915_kernel_lost_context(dev);
3895 i915_gem_cleanup_ringbuffer(dev);
3897 mutex_unlock(&dev->struct_mutex);
3899 /* Cancel the retire work handler, which should be idle now. */
3900 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3905 void i915_gem_l3_remap(struct drm_device *dev)
3907 drm_i915_private_t *dev_priv = dev->dev_private;
3911 if (!HAS_L3_GPU_CACHE(dev))
3914 if (!dev_priv->l3_parity.remap_info)
3917 misccpctl = I915_READ(GEN7_MISCCPCTL);
3918 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3919 POSTING_READ(GEN7_MISCCPCTL);
3921 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3922 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3923 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3924 DRM_DEBUG("0x%x was already programmed to %x\n",
3925 GEN7_L3LOG_BASE + i, remap);
3926 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3927 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3928 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3931 /* Make sure all the writes land before disabling dop clock gating */
3932 POSTING_READ(GEN7_L3LOG_BASE);
3934 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3937 void i915_gem_init_swizzling(struct drm_device *dev)
3939 drm_i915_private_t *dev_priv = dev->dev_private;
3941 if (INTEL_INFO(dev)->gen < 5 ||
3942 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3945 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3946 DISP_TILE_SURFACE_SWIZZLING);
3951 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3953 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3954 else if (IS_GEN7(dev))
3955 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3961 intel_enable_blt(struct drm_device *dev)
3966 /* The blitter was dysfunctional on early prototypes */
3967 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3968 DRM_INFO("BLT not supported on this pre-production hardware;"
3969 " graphics performance will be degraded.\n");
3976 static int i915_gem_init_rings(struct drm_device *dev)
3978 struct drm_i915_private *dev_priv = dev->dev_private;
3981 ret = intel_init_render_ring_buffer(dev);
3986 ret = intel_init_bsd_ring_buffer(dev);
3988 goto cleanup_render_ring;
3991 if (intel_enable_blt(dev)) {
3992 ret = intel_init_blt_ring_buffer(dev);
3994 goto cleanup_bsd_ring;
3997 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
3999 goto cleanup_blt_ring;
4004 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4006 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4007 cleanup_render_ring:
4008 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4014 i915_gem_init_hw(struct drm_device *dev)
4016 drm_i915_private_t *dev_priv = dev->dev_private;
4019 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4022 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4023 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4025 if (HAS_PCH_NOP(dev)) {
4026 u32 temp = I915_READ(GEN7_MSG_CTL);
4027 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4028 I915_WRITE(GEN7_MSG_CTL, temp);
4031 i915_gem_l3_remap(dev);
4033 i915_gem_init_swizzling(dev);
4035 ret = i915_gem_init_rings(dev);
4040 * XXX: There was some w/a described somewhere suggesting loading
4041 * contexts before PPGTT.
4043 i915_gem_context_init(dev);
4044 if (dev_priv->mm.aliasing_ppgtt) {
4045 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4047 i915_gem_cleanup_aliasing_ppgtt(dev);
4048 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4055 int i915_gem_init(struct drm_device *dev)
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4060 mutex_lock(&dev->struct_mutex);
4062 if (IS_VALLEYVIEW(dev)) {
4063 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4064 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4065 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4066 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4069 i915_gem_init_global_gtt(dev);
4071 ret = i915_gem_init_hw(dev);
4072 mutex_unlock(&dev->struct_mutex);
4074 i915_gem_cleanup_aliasing_ppgtt(dev);
4078 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4079 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4080 dev_priv->dri1.allow_batchbuffer = 1;
4085 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4087 drm_i915_private_t *dev_priv = dev->dev_private;
4088 struct intel_ring_buffer *ring;
4091 for_each_ring(ring, dev_priv, i)
4092 intel_cleanup_ring_buffer(ring);
4096 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4097 struct drm_file *file_priv)
4099 drm_i915_private_t *dev_priv = dev->dev_private;
4102 if (drm_core_check_feature(dev, DRIVER_MODESET))
4105 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4106 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4107 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4110 mutex_lock(&dev->struct_mutex);
4111 dev_priv->mm.suspended = 0;
4113 ret = i915_gem_init_hw(dev);
4115 mutex_unlock(&dev->struct_mutex);
4119 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4120 mutex_unlock(&dev->struct_mutex);
4122 ret = drm_irq_install(dev);
4124 goto cleanup_ringbuffer;
4129 mutex_lock(&dev->struct_mutex);
4130 i915_gem_cleanup_ringbuffer(dev);
4131 dev_priv->mm.suspended = 1;
4132 mutex_unlock(&dev->struct_mutex);
4138 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4139 struct drm_file *file_priv)
4141 if (drm_core_check_feature(dev, DRIVER_MODESET))
4144 drm_irq_uninstall(dev);
4145 return i915_gem_idle(dev);
4149 i915_gem_lastclose(struct drm_device *dev)
4153 if (drm_core_check_feature(dev, DRIVER_MODESET))
4156 ret = i915_gem_idle(dev);
4158 DRM_ERROR("failed to idle hardware: %d\n", ret);
4162 init_ring_lists(struct intel_ring_buffer *ring)
4164 INIT_LIST_HEAD(&ring->active_list);
4165 INIT_LIST_HEAD(&ring->request_list);
4169 i915_gem_load(struct drm_device *dev)
4171 drm_i915_private_t *dev_priv = dev->dev_private;
4175 kmem_cache_create("i915_gem_object",
4176 sizeof(struct drm_i915_gem_object), 0,
4180 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4181 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4182 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4183 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4184 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4185 for (i = 0; i < I915_NUM_RINGS; i++)
4186 init_ring_lists(&dev_priv->ring[i]);
4187 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4188 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4189 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4190 i915_gem_retire_work_handler);
4191 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4193 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4195 I915_WRITE(MI_ARB_STATE,
4196 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4199 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4201 /* Old X drivers will take 0-2 for front, back, depth buffers */
4202 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4203 dev_priv->fence_reg_start = 3;
4205 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4206 dev_priv->num_fence_regs = 32;
4207 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4208 dev_priv->num_fence_regs = 16;
4210 dev_priv->num_fence_regs = 8;
4212 /* Initialize fence registers to zero */
4213 i915_gem_reset_fences(dev);
4215 i915_gem_detect_bit_6_swizzle(dev);
4216 init_waitqueue_head(&dev_priv->pending_flip_queue);
4218 dev_priv->mm.interruptible = true;
4220 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4221 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4222 register_shrinker(&dev_priv->mm.inactive_shrinker);
4226 * Create a physically contiguous memory object for this object
4227 * e.g. for cursor + overlay regs
4229 static int i915_gem_init_phys_object(struct drm_device *dev,
4230 int id, int size, int align)
4232 drm_i915_private_t *dev_priv = dev->dev_private;
4233 struct drm_i915_gem_phys_object *phys_obj;
4236 if (dev_priv->mm.phys_objs[id - 1] || !size)
4239 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4245 phys_obj->handle = drm_pci_alloc(dev, size, align);
4246 if (!phys_obj->handle) {
4251 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4254 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4262 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4264 drm_i915_private_t *dev_priv = dev->dev_private;
4265 struct drm_i915_gem_phys_object *phys_obj;
4267 if (!dev_priv->mm.phys_objs[id - 1])
4270 phys_obj = dev_priv->mm.phys_objs[id - 1];
4271 if (phys_obj->cur_obj) {
4272 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4276 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4278 drm_pci_free(dev, phys_obj->handle);
4280 dev_priv->mm.phys_objs[id - 1] = NULL;
4283 void i915_gem_free_all_phys_object(struct drm_device *dev)
4287 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4288 i915_gem_free_phys_object(dev, i);
4291 void i915_gem_detach_phys_object(struct drm_device *dev,
4292 struct drm_i915_gem_object *obj)
4294 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4301 vaddr = obj->phys_obj->handle->vaddr;
4303 page_count = obj->base.size / PAGE_SIZE;
4304 for (i = 0; i < page_count; i++) {
4305 struct page *page = shmem_read_mapping_page(mapping, i);
4306 if (!IS_ERR(page)) {
4307 char *dst = kmap_atomic(page);
4308 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4311 drm_clflush_pages(&page, 1);
4313 set_page_dirty(page);
4314 mark_page_accessed(page);
4315 page_cache_release(page);
4318 i915_gem_chipset_flush(dev);
4320 obj->phys_obj->cur_obj = NULL;
4321 obj->phys_obj = NULL;
4325 i915_gem_attach_phys_object(struct drm_device *dev,
4326 struct drm_i915_gem_object *obj,
4330 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4331 drm_i915_private_t *dev_priv = dev->dev_private;
4336 if (id > I915_MAX_PHYS_OBJECT)
4339 if (obj->phys_obj) {
4340 if (obj->phys_obj->id == id)
4342 i915_gem_detach_phys_object(dev, obj);
4345 /* create a new object */
4346 if (!dev_priv->mm.phys_objs[id - 1]) {
4347 ret = i915_gem_init_phys_object(dev, id,
4348 obj->base.size, align);
4350 DRM_ERROR("failed to init phys object %d size: %zu\n",
4351 id, obj->base.size);
4356 /* bind to the object */
4357 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4358 obj->phys_obj->cur_obj = obj;
4360 page_count = obj->base.size / PAGE_SIZE;
4362 for (i = 0; i < page_count; i++) {
4366 page = shmem_read_mapping_page(mapping, i);
4368 return PTR_ERR(page);
4370 src = kmap_atomic(page);
4371 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4372 memcpy(dst, src, PAGE_SIZE);
4375 mark_page_accessed(page);
4376 page_cache_release(page);
4383 i915_gem_phys_pwrite(struct drm_device *dev,
4384 struct drm_i915_gem_object *obj,
4385 struct drm_i915_gem_pwrite *args,
4386 struct drm_file *file_priv)
4388 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4389 char __user *user_data = to_user_ptr(args->data_ptr);
4391 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4392 unsigned long unwritten;
4394 /* The physical object once assigned is fixed for the lifetime
4395 * of the obj, so we can safely drop the lock and continue
4398 mutex_unlock(&dev->struct_mutex);
4399 unwritten = copy_from_user(vaddr, user_data, args->size);
4400 mutex_lock(&dev->struct_mutex);
4405 i915_gem_chipset_flush(dev);
4409 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4411 struct drm_i915_file_private *file_priv = file->driver_priv;
4413 /* Clean up our request list when the client is going away, so that
4414 * later retire_requests won't dereference our soon-to-be-gone
4417 spin_lock(&file_priv->mm.lock);
4418 while (!list_empty(&file_priv->mm.request_list)) {
4419 struct drm_i915_gem_request *request;
4421 request = list_first_entry(&file_priv->mm.request_list,
4422 struct drm_i915_gem_request,
4424 list_del(&request->client_list);
4425 request->file_priv = NULL;
4427 spin_unlock(&file_priv->mm.lock);
4430 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4432 if (!mutex_is_locked(mutex))
4435 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4436 return mutex->owner == task;
4438 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4444 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4446 struct drm_i915_private *dev_priv =
4447 container_of(shrinker,
4448 struct drm_i915_private,
4449 mm.inactive_shrinker);
4450 struct drm_device *dev = dev_priv->dev;
4451 struct drm_i915_gem_object *obj;
4452 int nr_to_scan = sc->nr_to_scan;
4456 if (!mutex_trylock(&dev->struct_mutex)) {
4457 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4460 if (dev_priv->mm.shrinker_no_lock_stealing)
4467 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4469 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4472 i915_gem_shrink_all(dev_priv);
4476 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4477 if (obj->pages_pin_count == 0)
4478 cnt += obj->base.size >> PAGE_SHIFT;
4479 list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list)
4480 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4481 cnt += obj->base.size >> PAGE_SHIFT;
4484 mutex_unlock(&dev->struct_mutex);