drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     struct shrink_control *sc);
  60
  61 /* some bookkeeping */
  62 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  63                                   size_t size)
  64 {
  65         dev_priv->mm.object_count++;
  66         dev_priv->mm.object_memory += size;
  67 }
  68
  69 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  70                                      size_t size)
  71 {
  72         dev_priv->mm.object_count--;
  73         dev_priv->mm.object_memory -= size;
  74 }
  75
  76 static int
  77 i915_gem_wait_for_error(struct drm_device *dev)
  78 {
  79         struct drm_i915_private *dev_priv = dev->dev_private;
  80         struct completion *x = &dev_priv->error_completion;
  81         unsigned long flags;
  82         int ret;
  83
  84         if (!atomic_read(&dev_priv->mm.wedged))
  85                 return 0;
  86
  87         ret = wait_for_completion_interruptible(x);
  88         if (ret)
  89                 return ret;
  90
  91         if (atomic_read(&dev_priv->mm.wedged)) {
  92                 /* GPU is hung, bump the completion count to account for
  93                  * the token we just consumed so that we never hit zero and
  94                  * end up waiting upon a subsequent completion event that
  95                  * will never happen.
  96                  */
  97                 spin_lock_irqsave(&x->wait.lock, flags);
  98                 x->done++;
  99                 spin_unlock_irqrestore(&x->wait.lock, flags);
 100         }
 101         return 0;
 102 }
 103
 104 int i915_mutex_lock_interruptible(struct drm_device *dev)
 105 {
 106         int ret;
 107
 108         ret = i915_gem_wait_for_error(dev);
 109         if (ret)
 110                 return ret;
 111
 112         ret = mutex_lock_interruptible(&dev->struct_mutex);
 113         if (ret)
 114                 return ret;
 115
 116         WARN_ON(i915_verify_lists(dev));
 117         return 0;
 118 }
 119
 120 static inline bool
 121 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 122 {
 123         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 124 }
 125
 126 void i915_gem_do_init(struct drm_device *dev,
 127                       unsigned long start,
 128                       unsigned long mappable_end,
 129                       unsigned long end)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132
 133         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 134
 135         dev_priv->mm.gtt_start = start;
 136         dev_priv->mm.gtt_mappable_end = mappable_end;
 137         dev_priv->mm.gtt_end = end;
 138         dev_priv->mm.gtt_total = end - start;
 139         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 140
 141         /* Take over this portion of the GTT */
 142         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 143 }
 144
 145 int
 146 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 147                     struct drm_file *file)
 148 {
 149         struct drm_i915_gem_init *args = data;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         mutex_lock(&dev->struct_mutex);
 156         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 157         mutex_unlock(&dev->struct_mutex);
 158
 159         return 0;
 160 }
 161
 162 int
 163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 164                             struct drm_file *file)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct drm_i915_gem_get_aperture *args = data;
 168         struct drm_i915_gem_object *obj;
 169         size_t pinned;
 170
 171         if (!(dev->driver->driver_features & DRIVER_GEM))
 172                 return -ENODEV;
 173
 174         pinned = 0;
 175         mutex_lock(&dev->struct_mutex);
 176         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 177                 pinned += obj->gtt_space->size;
 178         mutex_unlock(&dev->struct_mutex);
 179
 180         args->aper_size = dev_priv->mm.gtt_total;
 181         args->aper_available_size = args->aper_size -pinned;
 182
 183         return 0;
 184 }
 185
 186 static int
 187 i915_gem_create(struct drm_file *file,
 188                 struct drm_device *dev,
 189                 uint64_t size,
 190                 uint32_t *handle_p)
 191 {
 192         struct drm_i915_gem_object *obj;
 193         int ret;
 194         u32 handle;
 195
 196         size = roundup(size, PAGE_SIZE);
 197
 198         /* Allocate the new object */
 199         obj = i915_gem_alloc_object(dev, size);
 200         if (obj == NULL)
 201                 return -ENOMEM;
 202
 203         ret = drm_gem_handle_create(file, &obj->base, &handle);
 204         if (ret) {
 205                 drm_gem_object_release(&obj->base);
 206                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 207                 kfree(obj);
 208                 return ret;
 209         }
 210
 211         /* drop reference from allocate - handle holds it now */
 212         drm_gem_object_unreference(&obj->base);
 213         trace_i915_gem_object_create(obj);
 214
 215         *handle_p = handle;
 216         return 0;
 217 }
 218
 219 int
 220 i915_gem_dumb_create(struct drm_file *file,
 221                      struct drm_device *dev,
 222                      struct drm_mode_create_dumb *args)
 223 {
 224         /* have to work out size/pitch and return them */
 225         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 226         args->size = args->pitch * args->height;
 227         return i915_gem_create(file, dev,
 228                                args->size, &args->handle);
 229 }
 230
 231 int i915_gem_dumb_destroy(struct drm_file *file,
 232                           struct drm_device *dev,
 233                           uint32_t handle)
 234 {
 235         return drm_gem_handle_delete(file, handle);
 236 }
 237
 238 /**
 239  * Creates a new mm object and returns a handle to it.
 240  */
 241 int
 242 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 243                       struct drm_file *file)
 244 {
 245         struct drm_i915_gem_create *args = data;
 246         return i915_gem_create(file, dev,
 247                                args->size, &args->handle);
 248 }
 249
 250 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 251 {
 252         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 253
 254         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 255                 obj->tiling_mode != I915_TILING_NONE;
 256 }
 257
 258 static inline void
 259 slow_shmem_copy(struct page *dst_page,
 260                 int dst_offset,
 261                 struct page *src_page,
 262                 int src_offset,
 263                 int length)
 264 {
 265         char *dst_vaddr, *src_vaddr;
 266
 267         dst_vaddr = kmap(dst_page);
 268         src_vaddr = kmap(src_page);
 269
 270         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 271
 272         kunmap(src_page);
 273         kunmap(dst_page);
 274 }
 275
 276 static inline void
 277 slow_shmem_bit17_copy(struct page *gpu_page,
 278                       int gpu_offset,
 279                       struct page *cpu_page,
 280                       int cpu_offset,
 281                       int length,
 282                       int is_read)
 283 {
 284         char *gpu_vaddr, *cpu_vaddr;
 285
 286         /* Use the unswizzled path if this page isn't affected. */
 287         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 288                 if (is_read)
 289                         return slow_shmem_copy(cpu_page, cpu_offset,
 290                                                gpu_page, gpu_offset, length);
 291                 else
 292                         return slow_shmem_copy(gpu_page, gpu_offset,
 293                                                cpu_page, cpu_offset, length);
 294         }
 295
 296         gpu_vaddr = kmap(gpu_page);
 297         cpu_vaddr = kmap(cpu_page);
 298
 299         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 300          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 301          */
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 if (is_read) {
 308                         memcpy(cpu_vaddr + cpu_offset,
 309                                gpu_vaddr + swizzled_gpu_offset,
 310                                this_length);
 311                 } else {
 312                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 313                                cpu_vaddr + cpu_offset,
 314                                this_length);
 315                 }
 316                 cpu_offset += this_length;
 317                 gpu_offset += this_length;
 318                 length -= this_length;
 319         }
 320
 321         kunmap(cpu_page);
 322         kunmap(gpu_page);
 323 }
 324
 325 /**
 326  * This is the fast shmem pread path, which attempts to copy_from_user directly
 327  * from the backing pages of the object to the user's address space.  On a
 328  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 329  */
 330 static int
 331 i915_gem_shmem_pread_fast(struct drm_device *dev,
 332                           struct drm_i915_gem_object *obj,
 333                           struct drm_i915_gem_pread *args,
 334                           struct drm_file *file)
 335 {
 336         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 337         ssize_t remain;
 338         loff_t offset;
 339         char __user *user_data;
 340         int page_offset, page_length;
 341
 342         user_data = (char __user *) (uintptr_t) args->data_ptr;
 343         remain = args->size;
 344
 345         offset = args->offset;
 346
 347         while (remain > 0) {
 348                 struct page *page;
 349                 char *vaddr;
 350                 int ret;
 351
 352                 /* Operation in this page
 353                  *
 354                  * page_offset = offset within page
 355                  * page_length = bytes to copy for this page
 356                  */
 357                 page_offset = offset_in_page(offset);
 358                 page_length = remain;
 359                 if ((page_offset + remain) > PAGE_SIZE)
 360                         page_length = PAGE_SIZE - page_offset;
 361
 362                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 363                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 364                 if (IS_ERR(page))
 365                         return PTR_ERR(page);
 366
 367                 vaddr = kmap_atomic(page);
 368                 ret = __copy_to_user_inatomic(user_data,
 369                                               vaddr + page_offset,
 370                                               page_length);
 371                 kunmap_atomic(vaddr);
 372
 373                 mark_page_accessed(page);
 374                 page_cache_release(page);
 375                 if (ret)
 376                         return -EFAULT;
 377
 378                 remain -= page_length;
 379                 user_data += page_length;
 380                 offset += page_length;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * This is the fallback shmem pread path, which allocates temporary storage
 388  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 389  * can copy out of the object's backing pages while holding the struct mutex
 390  * and not take page faults.
 391  */
 392 static int
 393 i915_gem_shmem_pread_slow(struct drm_device *dev,
 394                           struct drm_i915_gem_object *obj,
 395                           struct drm_i915_gem_pread *args,
 396                           struct drm_file *file)
 397 {
 398         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 399         struct mm_struct *mm = current->mm;
 400         struct page **user_pages;
 401         ssize_t remain;
 402         loff_t offset, pinned_pages, i;
 403         loff_t first_data_page, last_data_page, num_pages;
 404         int shmem_page_offset;
 405         int data_page_index, data_page_offset;
 406         int page_length;
 407         int ret;
 408         uint64_t data_ptr = args->data_ptr;
 409         int do_bit17_swizzling;
 410
 411         remain = args->size;
 412
 413         /* Pin the user pages containing the data.  We can't fault while
 414          * holding the struct mutex, yet we want to hold it while
 415          * dereferencing the user data.
 416          */
 417         first_data_page = data_ptr / PAGE_SIZE;
 418         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 419         num_pages = last_data_page - first_data_page + 1;
 420
 421         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 422         if (user_pages == NULL)
 423                 return -ENOMEM;
 424
 425         mutex_unlock(&dev->struct_mutex);
 426         down_read(&mm->mmap_sem);
 427         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 428                                       num_pages, 1, 0, user_pages, NULL);
 429         up_read(&mm->mmap_sem);
 430         mutex_lock(&dev->struct_mutex);
 431         if (pinned_pages < num_pages) {
 432                 ret = -EFAULT;
 433                 goto out;
 434         }
 435
 436         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 437                                                         args->offset,
 438                                                         args->size);
 439         if (ret)
 440                 goto out;
 441
 442         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 443
 444         offset = args->offset;
 445
 446         while (remain > 0) {
 447                 struct page *page;
 448
 449                 /* Operation in this page
 450                  *
 451                  * shmem_page_offset = offset within page in shmem file
 452                  * data_page_index = page number in get_user_pages return
 453                  * data_page_offset = offset with data_page_index page.
 454                  * page_length = bytes to copy for this page
 455                  */
 456                 shmem_page_offset = offset_in_page(offset);
 457                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 458                 data_page_offset = offset_in_page(data_ptr);
 459
 460                 page_length = remain;
 461                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 462                         page_length = PAGE_SIZE - shmem_page_offset;
 463                 if ((data_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - data_page_offset;
 465
 466                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 467                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 468                 if (IS_ERR(page)) {
 469                         ret = PTR_ERR(page);
 470                         goto out;
 471                 }
 472
 473                 if (do_bit17_swizzling) {
 474                         slow_shmem_bit17_copy(page,
 475                                               shmem_page_offset,
 476                                               user_pages[data_page_index],
 477                                               data_page_offset,
 478                                               page_length,
 479                                               1);
 480                 } else {
 481                         slow_shmem_copy(user_pages[data_page_index],
 482                                         data_page_offset,
 483                                         page,
 484                                         shmem_page_offset,
 485                                         page_length);
 486                 }
 487
 488                 mark_page_accessed(page);
 489                 page_cache_release(page);
 490
 491                 remain -= page_length;
 492                 data_ptr += page_length;
 493                 offset += page_length;
 494         }
 495
 496 out:
 497         for (i = 0; i < pinned_pages; i++) {
 498                 SetPageDirty(user_pages[i]);
 499                 mark_page_accessed(user_pages[i]);
 500                 page_cache_release(user_pages[i]);
 501         }
 502         drm_free_large(user_pages);
 503
 504         return ret;
 505 }
 506
 507 /**
 508  * Reads data from the object referenced by handle.
 509  *
 510  * On error, the contents of *data are undefined.
 511  */
 512 int
 513 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 514                      struct drm_file *file)
 515 {
 516         struct drm_i915_gem_pread *args = data;
 517         struct drm_i915_gem_object *obj;
 518         int ret = 0;
 519
 520         if (args->size == 0)
 521                 return 0;
 522
 523         if (!access_ok(VERIFY_WRITE,
 524                        (char __user *)(uintptr_t)args->data_ptr,
 525                        args->size))
 526                 return -EFAULT;
 527
 528         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 529                                        args->size);
 530         if (ret)
 531                 return -EFAULT;
 532
 533         ret = i915_mutex_lock_interruptible(dev);
 534         if (ret)
 535                 return ret;
 536
 537         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 538         if (&obj->base == NULL) {
 539                 ret = -ENOENT;
 540                 goto unlock;
 541         }
 542
 543         /* Bounds check source.  */
 544         if (args->offset > obj->base.size ||
 545             args->size > obj->base.size - args->offset) {
 546                 ret = -EINVAL;
 547                 goto out;
 548         }
 549
 550         trace_i915_gem_object_pread(obj, args->offset, args->size);
 551
 552         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 553                                                         args->offset,
 554                                                         args->size);
 555         if (ret)
 556                 goto out;
 557
 558         ret = -EFAULT;
 559         if (!i915_gem_object_needs_bit17_swizzle(obj))
 560                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 561         if (ret == -EFAULT)
 562                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 563
 564 out:
 565         drm_gem_object_unreference(&obj->base);
 566 unlock:
 567         mutex_unlock(&dev->struct_mutex);
 568         return ret;
 569 }
 570
 571 /* This is the fast write path which cannot handle
 572  * page faults in the source data
 573  */
 574
 575 static inline int
 576 fast_user_write(struct io_mapping *mapping,
 577                 loff_t page_base, int page_offset,
 578                 char __user *user_data,
 579                 int length)
 580 {
 581         char *vaddr_atomic;
 582         unsigned long unwritten;
 583
 584         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 585         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 586                                                       user_data, length);
 587         io_mapping_unmap_atomic(vaddr_atomic);
 588         return unwritten;
 589 }
 590
 591 /* Here's the write path which can sleep for
 592  * page faults
 593  */
 594
 595 static inline void
 596 slow_kernel_write(struct io_mapping *mapping,
 597                   loff_t gtt_base, int gtt_offset,
 598                   struct page *user_page, int user_offset,
 599                   int length)
 600 {
 601         char __iomem *dst_vaddr;
 602         char *src_vaddr;
 603
 604         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 605         src_vaddr = kmap(user_page);
 606
 607         memcpy_toio(dst_vaddr + gtt_offset,
 608                     src_vaddr + user_offset,
 609                     length);
 610
 611         kunmap(user_page);
 612         io_mapping_unmap(dst_vaddr);
 613 }
 614
 615 /**
 616  * This is the fast pwrite path, where we copy the data directly from the
 617  * user into the GTT, uncached.
 618  */
 619 static int
 620 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 621                          struct drm_i915_gem_object *obj,
 622                          struct drm_i915_gem_pwrite *args,
 623                          struct drm_file *file)
 624 {
 625         drm_i915_private_t *dev_priv = dev->dev_private;
 626         ssize_t remain;
 627         loff_t offset, page_base;
 628         char __user *user_data;
 629         int page_offset, page_length;
 630
 631         user_data = (char __user *) (uintptr_t) args->data_ptr;
 632         remain = args->size;
 633
 634         offset = obj->gtt_offset + args->offset;
 635
 636         while (remain > 0) {
 637                 /* Operation in this page
 638                  *
 639                  * page_base = page offset within aperture
 640                  * page_offset = offset within page
 641                  * page_length = bytes to copy for this page
 642                  */
 643                 page_base = offset & PAGE_MASK;
 644                 page_offset = offset_in_page(offset);
 645                 page_length = remain;
 646                 if ((page_offset + remain) > PAGE_SIZE)
 647                         page_length = PAGE_SIZE - page_offset;
 648
 649                 /* If we get a fault while copying data, then (presumably) our
 650                  * source page isn't available.  Return the error and we'll
 651                  * retry in the slow path.
 652                  */
 653                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 654                                     page_offset, user_data, page_length))
 655                         return -EFAULT;
 656
 657                 remain -= page_length;
 658                 user_data += page_length;
 659                 offset += page_length;
 660         }
 661
 662         return 0;
 663 }
 664
 665 /**
 666  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 667  * the memory and maps it using kmap_atomic for copying.
 668  *
 669  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 670  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 671  */
 672 static int
 673 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 674                          struct drm_i915_gem_object *obj,
 675                          struct drm_i915_gem_pwrite *args,
 676                          struct drm_file *file)
 677 {
 678         drm_i915_private_t *dev_priv = dev->dev_private;
 679         ssize_t remain;
 680         loff_t gtt_page_base, offset;
 681         loff_t first_data_page, last_data_page, num_pages;
 682         loff_t pinned_pages, i;
 683         struct page **user_pages;
 684         struct mm_struct *mm = current->mm;
 685         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 686         int ret;
 687         uint64_t data_ptr = args->data_ptr;
 688
 689         remain = args->size;
 690
 691         /* Pin the user pages containing the data.  We can't fault while
 692          * holding the struct mutex, and all of the pwrite implementations
 693          * want to hold it while dereferencing the user data.
 694          */
 695         first_data_page = data_ptr / PAGE_SIZE;
 696         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 697         num_pages = last_data_page - first_data_page + 1;
 698
 699         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 700         if (user_pages == NULL)
 701                 return -ENOMEM;
 702
 703         mutex_unlock(&dev->struct_mutex);
 704         down_read(&mm->mmap_sem);
 705         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 706                                       num_pages, 0, 0, user_pages, NULL);
 707         up_read(&mm->mmap_sem);
 708         mutex_lock(&dev->struct_mutex);
 709         if (pinned_pages < num_pages) {
 710                 ret = -EFAULT;
 711                 goto out_unpin_pages;
 712         }
 713
 714         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 715         if (ret)
 716                 goto out_unpin_pages;
 717
 718         ret = i915_gem_object_put_fence(obj);
 719         if (ret)
 720                 goto out_unpin_pages;
 721
 722         offset = obj->gtt_offset + args->offset;
 723
 724         while (remain > 0) {
 725                 /* Operation in this page
 726                  *
 727                  * gtt_page_base = page offset within aperture
 728                  * gtt_page_offset = offset within page in aperture
 729                  * data_page_index = page number in get_user_pages return
 730                  * data_page_offset = offset with data_page_index page.
 731                  * page_length = bytes to copy for this page
 732                  */
 733                 gtt_page_base = offset & PAGE_MASK;
 734                 gtt_page_offset = offset_in_page(offset);
 735                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 736                 data_page_offset = offset_in_page(data_ptr);
 737
 738                 page_length = remain;
 739                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 740                         page_length = PAGE_SIZE - gtt_page_offset;
 741                 if ((data_page_offset + page_length) > PAGE_SIZE)
 742                         page_length = PAGE_SIZE - data_page_offset;
 743
 744                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 745                                   gtt_page_base, gtt_page_offset,
 746                                   user_pages[data_page_index],
 747                                   data_page_offset,
 748                                   page_length);
 749
 750                 remain -= page_length;
 751                 offset += page_length;
 752                 data_ptr += page_length;
 753         }
 754
 755 out_unpin_pages:
 756         for (i = 0; i < pinned_pages; i++)
 757                 page_cache_release(user_pages[i]);
 758         drm_free_large(user_pages);
 759
 760         return ret;
 761 }
 762
 763 /**
 764  * This is the fast shmem pwrite path, which attempts to directly
 765  * copy_from_user into the kmapped pages backing the object.
 766  */
 767 static int
 768 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 769                            struct drm_i915_gem_object *obj,
 770                            struct drm_i915_gem_pwrite *args,
 771                            struct drm_file *file)
 772 {
 773         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 774         ssize_t remain;
 775         loff_t offset;
 776         char __user *user_data;
 777         int page_offset, page_length;
 778
 779         user_data = (char __user *) (uintptr_t) args->data_ptr;
 780         remain = args->size;
 781
 782         offset = args->offset;
 783         obj->dirty = 1;
 784
 785         while (remain > 0) {
 786                 struct page *page;
 787                 char *vaddr;
 788                 int ret;
 789
 790                 /* Operation in this page
 791                  *
 792                  * page_offset = offset within page
 793                  * page_length = bytes to copy for this page
 794                  */
 795                 page_offset = offset_in_page(offset);
 796                 page_length = remain;
 797                 if ((page_offset + remain) > PAGE_SIZE)
 798                         page_length = PAGE_SIZE - page_offset;
 799
 800                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 801                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 802                 if (IS_ERR(page))
 803                         return PTR_ERR(page);
 804
 805                 vaddr = kmap_atomic(page, KM_USER0);
 806                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 807                                                 user_data,
 808                                                 page_length);
 809                 kunmap_atomic(vaddr, KM_USER0);
 810
 811                 set_page_dirty(page);
 812                 mark_page_accessed(page);
 813                 page_cache_release(page);
 814
 815                 /* If we get a fault while copying data, then (presumably) our
 816                  * source page isn't available.  Return the error and we'll
 817                  * retry in the slow path.
 818                  */
 819                 if (ret)
 820                         return -EFAULT;
 821
 822                 remain -= page_length;
 823                 user_data += page_length;
 824                 offset += page_length;
 825         }
 826
 827         return 0;
 828 }
 829
 830 /**
 831  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 832  * the memory and maps it using kmap_atomic for copying.
 833  *
 834  * This avoids taking mmap_sem for faulting on the user's address while the
 835  * struct_mutex is held.
 836  */
 837 static int
 838 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 839                            struct drm_i915_gem_object *obj,
 840                            struct drm_i915_gem_pwrite *args,
 841                            struct drm_file *file)
 842 {
 843         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 844         struct mm_struct *mm = current->mm;
 845         struct page **user_pages;
 846         ssize_t remain;
 847         loff_t offset, pinned_pages, i;
 848         loff_t first_data_page, last_data_page, num_pages;
 849         int shmem_page_offset;
 850         int data_page_index,  data_page_offset;
 851         int page_length;
 852         int ret;
 853         uint64_t data_ptr = args->data_ptr;
 854         int do_bit17_swizzling;
 855
 856         remain = args->size;
 857
 858         /* Pin the user pages containing the data.  We can't fault while
 859          * holding the struct mutex, and all of the pwrite implementations
 860          * want to hold it while dereferencing the user data.
 861          */
 862         first_data_page = data_ptr / PAGE_SIZE;
 863         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 864         num_pages = last_data_page - first_data_page + 1;
 865
 866         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 867         if (user_pages == NULL)
 868                 return -ENOMEM;
 869
 870         mutex_unlock(&dev->struct_mutex);
 871         down_read(&mm->mmap_sem);
 872         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 873                                       num_pages, 0, 0, user_pages, NULL);
 874         up_read(&mm->mmap_sem);
 875         mutex_lock(&dev->struct_mutex);
 876         if (pinned_pages < num_pages) {
 877                 ret = -EFAULT;
 878                 goto out;
 879         }
 880
 881         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 882         if (ret)
 883                 goto out;
 884
 885         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 886
 887         offset = args->offset;
 888         obj->dirty = 1;
 889
 890         while (remain > 0) {
 891                 struct page *page;
 892
 893                 /* Operation in this page
 894                  *
 895                  * shmem_page_offset = offset within page in shmem file
 896                  * data_page_index = page number in get_user_pages return
 897                  * data_page_offset = offset with data_page_index page.
 898                  * page_length = bytes to copy for this page
 899                  */
 900                 shmem_page_offset = offset_in_page(offset);
 901                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 902                 data_page_offset = offset_in_page(data_ptr);
 903
 904                 page_length = remain;
 905                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 906                         page_length = PAGE_SIZE - shmem_page_offset;
 907                 if ((data_page_offset + page_length) > PAGE_SIZE)
 908                         page_length = PAGE_SIZE - data_page_offset;
 909
 910                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 911                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 912                 if (IS_ERR(page)) {
 913                         ret = PTR_ERR(page);
 914                         goto out;
 915                 }
 916
 917                 if (do_bit17_swizzling) {
 918                         slow_shmem_bit17_copy(page,
 919                                               shmem_page_offset,
 920                                               user_pages[data_page_index],
 921                                               data_page_offset,
 922                                               page_length,
 923                                               0);
 924                 } else {
 925                         slow_shmem_copy(page,
 926                                         shmem_page_offset,
 927                                         user_pages[data_page_index],
 928                                         data_page_offset,
 929                                         page_length);
 930                 }
 931
 932                 set_page_dirty(page);
 933                 mark_page_accessed(page);
 934                 page_cache_release(page);
 935
 936                 remain -= page_length;
 937                 data_ptr += page_length;
 938                 offset += page_length;
 939         }
 940
 941 out:
 942         for (i = 0; i < pinned_pages; i++)
 943                 page_cache_release(user_pages[i]);
 944         drm_free_large(user_pages);
 945
 946         return ret;
 947 }
 948
 949 /**
 950  * Writes data to the object referenced by handle.
 951  *
 952  * On error, the contents of the buffer that were to be modified are undefined.
 953  */
 954 int
 955 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 956                       struct drm_file *file)
 957 {
 958         struct drm_i915_gem_pwrite *args = data;
 959         struct drm_i915_gem_object *obj;
 960         int ret;
 961
 962         if (args->size == 0)
 963                 return 0;
 964
 965         if (!access_ok(VERIFY_READ,
 966                        (char __user *)(uintptr_t)args->data_ptr,
 967                        args->size))
 968                 return -EFAULT;
 969
 970         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 971                                       args->size);
 972         if (ret)
 973                 return -EFAULT;
 974
 975         ret = i915_mutex_lock_interruptible(dev);
 976         if (ret)
 977                 return ret;
 978
 979         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 980         if (&obj->base == NULL) {
 981                 ret = -ENOENT;
 982                 goto unlock;
 983         }
 984
 985         /* Bounds check destination. */
 986         if (args->offset > obj->base.size ||
 987             args->size > obj->base.size - args->offset) {
 988                 ret = -EINVAL;
 989                 goto out;
 990         }
 991
 992         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 993
 994         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 995          * it would end up going through the fenced access, and we'll get
 996          * different detiling behavior between reading and writing.
 997          * pread/pwrite currently are reading and writing from the CPU
 998          * perspective, requiring manual detiling by the client.
 999          */
1000         if (obj->phys_obj)
1001                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1002         else if (obj->gtt_space &&
1003                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1004                 ret = i915_gem_object_pin(obj, 0, true);
1005                 if (ret)
1006                         goto out;
1007
1008                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1009                 if (ret)
1010                         goto out_unpin;
1011
1012                 ret = i915_gem_object_put_fence(obj);
1013                 if (ret)
1014                         goto out_unpin;
1015
1016                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1017                 if (ret == -EFAULT)
1018                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1019
1020 out_unpin:
1021                 i915_gem_object_unpin(obj);
1022         } else {
1023                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1024                 if (ret)
1025                         goto out;
1026
1027                 ret = -EFAULT;
1028                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1029                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1030                 if (ret == -EFAULT)
1031                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1032         }
1033
1034 out:
1035         drm_gem_object_unreference(&obj->base);
1036 unlock:
1037         mutex_unlock(&dev->struct_mutex);
1038         return ret;
1039 }
1040
1041 /**
1042  * Called when user space prepares to use an object with the CPU, either
1043  * through the mmap ioctl's mapping or a GTT mapping.
1044  */
1045 int
1046 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1047                           struct drm_file *file)
1048 {
1049         struct drm_i915_gem_set_domain *args = data;
1050         struct drm_i915_gem_object *obj;
1051         uint32_t read_domains = args->read_domains;
1052         uint32_t write_domain = args->write_domain;
1053         int ret;
1054
1055         if (!(dev->driver->driver_features & DRIVER_GEM))
1056                 return -ENODEV;
1057
1058         /* Only handle setting domains to types used by the CPU. */
1059         if (write_domain & I915_GEM_GPU_DOMAINS)
1060                 return -EINVAL;
1061
1062         if (read_domains & I915_GEM_GPU_DOMAINS)
1063                 return -EINVAL;
1064
1065         /* Having something in the write domain implies it's in the read
1066          * domain, and only that read domain.  Enforce that in the request.
1067          */
1068         if (write_domain != 0 && read_domains != write_domain)
1069                 return -EINVAL;
1070
1071         ret = i915_mutex_lock_interruptible(dev);
1072         if (ret)
1073                 return ret;
1074
1075         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1076         if (&obj->base == NULL) {
1077                 ret = -ENOENT;
1078                 goto unlock;
1079         }
1080
1081         if (read_domains & I915_GEM_DOMAIN_GTT) {
1082                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1083
1084                 /* Silently promote "you're not bound, there was nothing to do"
1085                  * to success, since the client was just asking us to
1086                  * make sure everything was done.
1087                  */
1088                 if (ret == -EINVAL)
1089                         ret = 0;
1090         } else {
1091                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1092         }
1093
1094         drm_gem_object_unreference(&obj->base);
1095 unlock:
1096         mutex_unlock(&dev->struct_mutex);
1097         return ret;
1098 }
1099
1100 /**
1101  * Called when user space has done writes to this buffer
1102  */
1103 int
1104 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1105                          struct drm_file *file)
1106 {
1107         struct drm_i915_gem_sw_finish *args = data;
1108         struct drm_i915_gem_object *obj;
1109         int ret = 0;
1110
1111         if (!(dev->driver->driver_features & DRIVER_GEM))
1112                 return -ENODEV;
1113
1114         ret = i915_mutex_lock_interruptible(dev);
1115         if (ret)
1116                 return ret;
1117
1118         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1119         if (&obj->base == NULL) {
1120                 ret = -ENOENT;
1121                 goto unlock;
1122         }
1123
1124         /* Pinned buffers may be scanout, so flush the cache */
1125         if (obj->pin_count)
1126                 i915_gem_object_flush_cpu_write_domain(obj);
1127
1128         drm_gem_object_unreference(&obj->base);
1129 unlock:
1130         mutex_unlock(&dev->struct_mutex);
1131         return ret;
1132 }
1133
1134 /**
1135  * Maps the contents of an object, returning the address it is mapped
1136  * into.
1137  *
1138  * While the mapping holds a reference on the contents of the object, it doesn't
1139  * imply a ref on the object itself.
1140  */
1141 int
1142 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1143                     struct drm_file *file)
1144 {
1145         struct drm_i915_private *dev_priv = dev->dev_private;
1146         struct drm_i915_gem_mmap *args = data;
1147         struct drm_gem_object *obj;
1148         unsigned long addr;
1149
1150         if (!(dev->driver->driver_features & DRIVER_GEM))
1151                 return -ENODEV;
1152
1153         obj = drm_gem_object_lookup(dev, file, args->handle);
1154         if (obj == NULL)
1155                 return -ENOENT;
1156
1157         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1158                 drm_gem_object_unreference_unlocked(obj);
1159                 return -E2BIG;
1160         }
1161
1162         down_write(&current->mm->mmap_sem);
1163         addr = do_mmap(obj->filp, 0, args->size,
1164                        PROT_READ | PROT_WRITE, MAP_SHARED,
1165                        args->offset);
1166         up_write(&current->mm->mmap_sem);
1167         drm_gem_object_unreference_unlocked(obj);
1168         if (IS_ERR((void *)addr))
1169                 return addr;
1170
1171         args->addr_ptr = (uint64_t) addr;
1172
1173         return 0;
1174 }
1175
1176 /**
1177  * i915_gem_fault - fault a page into the GTT
1178  * vma: VMA in question
1179  * vmf: fault info
1180  *
1181  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1182  * from userspace.  The fault handler takes care of binding the object to
1183  * the GTT (if needed), allocating and programming a fence register (again,
1184  * only if needed based on whether the old reg is still valid or the object
1185  * is tiled) and inserting a new PTE into the faulting process.
1186  *
1187  * Note that the faulting process may involve evicting existing objects
1188  * from the GTT and/or fence registers to make room.  So performance may
1189  * suffer if the GTT working set is large or there are few fence registers
1190  * left.
1191  */
1192 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1193 {
1194         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1195         struct drm_device *dev = obj->base.dev;
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         pgoff_t page_offset;
1198         unsigned long pfn;
1199         int ret = 0;
1200         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1201
1202         /* We don't use vmf->pgoff since that has the fake offset */
1203         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1204                 PAGE_SHIFT;
1205
1206         ret = i915_mutex_lock_interruptible(dev);
1207         if (ret)
1208                 goto out;
1209
1210         trace_i915_gem_object_fault(obj, page_offset, true, write);
1211
1212         /* Now bind it into the GTT if needed */
1213         if (!obj->map_and_fenceable) {
1214                 ret = i915_gem_object_unbind(obj);
1215                 if (ret)
1216                         goto unlock;
1217         }
1218         if (!obj->gtt_space) {
1219                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1220                 if (ret)
1221                         goto unlock;
1222
1223                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1224                 if (ret)
1225                         goto unlock;
1226         }
1227
1228         if (obj->tiling_mode == I915_TILING_NONE)
1229                 ret = i915_gem_object_put_fence(obj);
1230         else
1231                 ret = i915_gem_object_get_fence(obj, NULL);
1232         if (ret)
1233                 goto unlock;
1234
1235         if (i915_gem_object_is_inactive(obj))
1236                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1237
1238         obj->fault_mappable = true;
1239
1240         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1241                 page_offset;
1242
1243         /* Finally, remap it using the new GTT offset */
1244         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1245 unlock:
1246         mutex_unlock(&dev->struct_mutex);
1247 out:
1248         switch (ret) {
1249         case -EIO:
1250         case -EAGAIN:
1251                 /* Give the error handler a chance to run and move the
1252                  * objects off the GPU active list. Next time we service the
1253                  * fault, we should be able to transition the page into the
1254                  * GTT without touching the GPU (and so avoid further
1255                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1256                  * with coherency, just lost writes.
1257                  */
1258                 set_need_resched();
1259         case 0:
1260         case -ERESTARTSYS:
1261         case -EINTR:
1262                 return VM_FAULT_NOPAGE;
1263         case -ENOMEM:
1264                 return VM_FAULT_OOM;
1265         default:
1266                 return VM_FAULT_SIGBUS;
1267         }
1268 }
1269
1270 /**
1271  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1272  * @obj: obj in question
1273  *
1274  * GEM memory mapping works by handing back to userspace a fake mmap offset
1275  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1276  * up the object based on the offset and sets up the various memory mapping
1277  * structures.
1278  *
1279  * This routine allocates and attaches a fake offset for @obj.
1280  */
1281 static int
1282 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1283 {
1284         struct drm_device *dev = obj->base.dev;
1285         struct drm_gem_mm *mm = dev->mm_private;
1286         struct drm_map_list *list;
1287         struct drm_local_map *map;
1288         int ret = 0;
1289
1290         /* Set the object up for mmap'ing */
1291         list = &obj->base.map_list;
1292         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1293         if (!list->map)
1294                 return -ENOMEM;
1295
1296         map = list->map;
1297         map->type = _DRM_GEM;
1298         map->size = obj->base.size;
1299         map->handle = obj;
1300
1301         /* Get a DRM GEM mmap offset allocated... */
1302         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1303                                                     obj->base.size / PAGE_SIZE,
1304                                                     0, 0);
1305         if (!list->file_offset_node) {
1306                 DRM_ERROR("failed to allocate offset for bo %d\n",
1307                           obj->base.name);
1308                 ret = -ENOSPC;
1309                 goto out_free_list;
1310         }
1311
1312         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1313                                                   obj->base.size / PAGE_SIZE,
1314                                                   0);
1315         if (!list->file_offset_node) {
1316                 ret = -ENOMEM;
1317                 goto out_free_list;
1318         }
1319
1320         list->hash.key = list->file_offset_node->start;
1321         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1322         if (ret) {
1323                 DRM_ERROR("failed to add to map hash\n");
1324                 goto out_free_mm;
1325         }
1326
1327         return 0;
1328
1329 out_free_mm:
1330         drm_mm_put_block(list->file_offset_node);
1331 out_free_list:
1332         kfree(list->map);
1333         list->map = NULL;
1334
1335         return ret;
1336 }
1337
1338 /**
1339  * i915_gem_release_mmap - remove physical page mappings
1340  * @obj: obj in question
1341  *
1342  * Preserve the reservation of the mmapping with the DRM core code, but
1343  * relinquish ownership of the pages back to the system.
1344  *
1345  * It is vital that we remove the page mapping if we have mapped a tiled
1346  * object through the GTT and then lose the fence register due to
1347  * resource pressure. Similarly if the object has been moved out of the
1348  * aperture, than pages mapped into userspace must be revoked. Removing the
1349  * mapping will then trigger a page fault on the next user access, allowing
1350  * fixup by i915_gem_fault().
1351  */
1352 void
1353 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1354 {
1355         if (!obj->fault_mappable)
1356                 return;
1357
1358         if (obj->base.dev->dev_mapping)
1359                 unmap_mapping_range(obj->base.dev->dev_mapping,
1360                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1361                                     obj->base.size, 1);
1362
1363         obj->fault_mappable = false;
1364 }
1365
1366 static void
1367 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1368 {
1369         struct drm_device *dev = obj->base.dev;
1370         struct drm_gem_mm *mm = dev->mm_private;
1371         struct drm_map_list *list = &obj->base.map_list;
1372
1373         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1374         drm_mm_put_block(list->file_offset_node);
1375         kfree(list->map);
1376         list->map = NULL;
1377 }
1378
1379 static uint32_t
1380 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->base.dev;
1383         uint32_t size;
1384
1385         if (INTEL_INFO(dev)->gen >= 4 ||
1386             obj->tiling_mode == I915_TILING_NONE)
1387                 return obj->base.size;
1388
1389         /* Previous chips need a power-of-two fence region when tiling */
1390         if (INTEL_INFO(dev)->gen == 3)
1391                 size = 1024*1024;
1392         else
1393                 size = 512*1024;
1394
1395         while (size < obj->base.size)
1396                 size <<= 1;
1397
1398         return size;
1399 }
1400
1401 /**
1402  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1403  * @obj: object to check
1404  *
1405  * Return the required GTT alignment for an object, taking into account
1406  * potential fence register mapping.
1407  */
1408 static uint32_t
1409 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1410 {
1411         struct drm_device *dev = obj->base.dev;
1412
1413         /*
1414          * Minimum alignment is 4k (GTT page size), but might be greater
1415          * if a fence register is needed for the object.
1416          */
1417         if (INTEL_INFO(dev)->gen >= 4 ||
1418             obj->tiling_mode == I915_TILING_NONE)
1419                 return 4096;
1420
1421         /*
1422          * Previous chips need to be aligned to the size of the smallest
1423          * fence register that can contain the object.
1424          */
1425         return i915_gem_get_gtt_size(obj);
1426 }
1427
1428 /**
1429  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1430  *                                       unfenced object
1431  * @obj: object to check
1432  *
1433  * Return the required GTT alignment for an object, only taking into account
1434  * unfenced tiled surface requirements.
1435  */
1436 uint32_t
1437 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1438 {
1439         struct drm_device *dev = obj->base.dev;
1440         int tile_height;
1441
1442         /*
1443          * Minimum alignment is 4k (GTT page size) for sane hw.
1444          */
1445         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1446             obj->tiling_mode == I915_TILING_NONE)
1447                 return 4096;
1448
1449         /*
1450          * Older chips need unfenced tiled buffers to be aligned to the left
1451          * edge of an even tile row (where tile rows are counted as if the bo is
1452          * placed in a fenced gtt region).
1453          */
1454         if (IS_GEN2(dev))
1455                 tile_height = 16;
1456         else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1457                 tile_height = 32;
1458         else
1459                 tile_height = 8;
1460
1461         return tile_height * obj->stride * 2;
1462 }
1463
1464 int
1465 i915_gem_mmap_gtt(struct drm_file *file,
1466                   struct drm_device *dev,
1467                   uint32_t handle,
1468                   uint64_t *offset)
1469 {
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         struct drm_i915_gem_object *obj;
1472         int ret;
1473
1474         if (!(dev->driver->driver_features & DRIVER_GEM))
1475                 return -ENODEV;
1476
1477         ret = i915_mutex_lock_interruptible(dev);
1478         if (ret)
1479                 return ret;
1480
1481         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1482         if (&obj->base == NULL) {
1483                 ret = -ENOENT;
1484                 goto unlock;
1485         }
1486
1487         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1488                 ret = -E2BIG;
1489                 goto unlock;
1490         }
1491
1492         if (obj->madv != I915_MADV_WILLNEED) {
1493                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1494                 ret = -EINVAL;
1495                 goto out;
1496         }
1497
1498         if (!obj->base.map_list.map) {
1499                 ret = i915_gem_create_mmap_offset(obj);
1500                 if (ret)
1501                         goto out;
1502         }
1503
1504         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1505
1506 out:
1507         drm_gem_object_unreference(&obj->base);
1508 unlock:
1509         mutex_unlock(&dev->struct_mutex);
1510         return ret;
1511 }
1512
1513 /**
1514  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1515  * @dev: DRM device
1516  * @data: GTT mapping ioctl data
1517  * @file: GEM object info
1518  *
1519  * Simply returns the fake offset to userspace so it can mmap it.
1520  * The mmap call will end up in drm_gem_mmap(), which will set things
1521  * up so we can get faults in the handler above.
1522  *
1523  * The fault handler will take care of binding the object into the GTT
1524  * (since it may have been evicted to make room for something), allocating
1525  * a fence register, and mapping the appropriate aperture address into
1526  * userspace.
1527  */
1528 int
1529 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1530                         struct drm_file *file)
1531 {
1532         struct drm_i915_gem_mmap_gtt *args = data;
1533
1534         if (!(dev->driver->driver_features & DRIVER_GEM))
1535                 return -ENODEV;
1536
1537         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1538 }
1539
1540
1541 static int
1542 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1543                               gfp_t gfpmask)
1544 {
1545         int page_count, i;
1546         struct address_space *mapping;
1547         struct inode *inode;
1548         struct page *page;
1549
1550         /* Get the list of pages out of our struct file.  They'll be pinned
1551          * at this point until we release them.
1552          */
1553         page_count = obj->base.size / PAGE_SIZE;
1554         BUG_ON(obj->pages != NULL);
1555         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1556         if (obj->pages == NULL)
1557                 return -ENOMEM;
1558
1559         inode = obj->base.filp->f_path.dentry->d_inode;
1560         mapping = inode->i_mapping;
1561         for (i = 0; i < page_count; i++) {
1562                 page = read_cache_page_gfp(mapping, i,
1563                                            GFP_HIGHUSER |
1564                                            __GFP_COLD |
1565                                            __GFP_RECLAIMABLE |
1566                                            gfpmask);
1567                 if (IS_ERR(page))
1568                         goto err_pages;
1569
1570                 obj->pages[i] = page;
1571         }
1572
1573         if (obj->tiling_mode != I915_TILING_NONE)
1574                 i915_gem_object_do_bit_17_swizzle(obj);
1575
1576         return 0;
1577
1578 err_pages:
1579         while (i--)
1580                 page_cache_release(obj->pages[i]);
1581
1582         drm_free_large(obj->pages);
1583         obj->pages = NULL;
1584         return PTR_ERR(page);
1585 }
1586
1587 static void
1588 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1589 {
1590         int page_count = obj->base.size / PAGE_SIZE;
1591         int i;
1592
1593         BUG_ON(obj->madv == __I915_MADV_PURGED);
1594
1595         if (obj->tiling_mode != I915_TILING_NONE)
1596                 i915_gem_object_save_bit_17_swizzle(obj);
1597
1598         if (obj->madv == I915_MADV_DONTNEED)
1599                 obj->dirty = 0;
1600
1601         for (i = 0; i < page_count; i++) {
1602                 if (obj->dirty)
1603                         set_page_dirty(obj->pages[i]);
1604
1605                 if (obj->madv == I915_MADV_WILLNEED)
1606                         mark_page_accessed(obj->pages[i]);
1607
1608                 page_cache_release(obj->pages[i]);
1609         }
1610         obj->dirty = 0;
1611
1612         drm_free_large(obj->pages);
1613         obj->pages = NULL;
1614 }
1615
1616 void
1617 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1618                                struct intel_ring_buffer *ring,
1619                                u32 seqno)
1620 {
1621         struct drm_device *dev = obj->base.dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624         BUG_ON(ring == NULL);
1625         obj->ring = ring;
1626
1627         /* Add a reference if we're newly entering the active list. */
1628         if (!obj->active) {
1629                 drm_gem_object_reference(&obj->base);
1630                 obj->active = 1;
1631         }
1632
1633         /* Move from whatever list we were on to the tail of execution. */
1634         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1635         list_move_tail(&obj->ring_list, &ring->active_list);
1636
1637         obj->last_rendering_seqno = seqno;
1638         if (obj->fenced_gpu_access) {
1639                 struct drm_i915_fence_reg *reg;
1640
1641                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1642
1643                 obj->last_fenced_seqno = seqno;
1644                 obj->last_fenced_ring = ring;
1645
1646                 reg = &dev_priv->fence_regs[obj->fence_reg];
1647                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1648         }
1649 }
1650
1651 static void
1652 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1653 {
1654         list_del_init(&obj->ring_list);
1655         obj->last_rendering_seqno = 0;
1656 }
1657
1658 static void
1659 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1660 {
1661         struct drm_device *dev = obj->base.dev;
1662         drm_i915_private_t *dev_priv = dev->dev_private;
1663
1664         BUG_ON(!obj->active);
1665         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1666
1667         i915_gem_object_move_off_active(obj);
1668 }
1669
1670 static void
1671 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1672 {
1673         struct drm_device *dev = obj->base.dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675
1676         if (obj->pin_count != 0)
1677                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1678         else
1679                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1680
1681         BUG_ON(!list_empty(&obj->gpu_write_list));
1682         BUG_ON(!obj->active);
1683         obj->ring = NULL;
1684
1685         i915_gem_object_move_off_active(obj);
1686         obj->fenced_gpu_access = false;
1687
1688         obj->active = 0;
1689         obj->pending_gpu_write = false;
1690         drm_gem_object_unreference(&obj->base);
1691
1692         WARN_ON(i915_verify_lists(dev));
1693 }
1694
1695 /* Immediately discard the backing storage */
1696 static void
1697 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1698 {
1699         struct inode *inode;
1700
1701         /* Our goal here is to return as much of the memory as
1702          * is possible back to the system as we are called from OOM.
1703          * To do this we must instruct the shmfs to drop all of its
1704          * backing pages, *now*. Here we mirror the actions taken
1705          * when by shmem_delete_inode() to release the backing store.
1706          */
1707         inode = obj->base.filp->f_path.dentry->d_inode;
1708         truncate_inode_pages(inode->i_mapping, 0);
1709         if (inode->i_op->truncate_range)
1710                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1711
1712         obj->madv = __I915_MADV_PURGED;
1713 }
1714
1715 static inline int
1716 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1717 {
1718         return obj->madv == I915_MADV_DONTNEED;
1719 }
1720
1721 static void
1722 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1723                                uint32_t flush_domains)
1724 {
1725         struct drm_i915_gem_object *obj, *next;
1726
1727         list_for_each_entry_safe(obj, next,
1728                                  &ring->gpu_write_list,
1729                                  gpu_write_list) {
1730                 if (obj->base.write_domain & flush_domains) {
1731                         uint32_t old_write_domain = obj->base.write_domain;
1732
1733                         obj->base.write_domain = 0;
1734                         list_del_init(&obj->gpu_write_list);
1735                         i915_gem_object_move_to_active(obj, ring,
1736                                                        i915_gem_next_request_seqno(ring));
1737
1738                         trace_i915_gem_object_change_domain(obj,
1739                                                             obj->base.read_domains,
1740                                                             old_write_domain);
1741                 }
1742         }
1743 }
1744
1745 int
1746 i915_add_request(struct intel_ring_buffer *ring,
1747                  struct drm_file *file,
1748                  struct drm_i915_gem_request *request)
1749 {
1750         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1751         uint32_t seqno;
1752         int was_empty;
1753         int ret;
1754
1755         BUG_ON(request == NULL);
1756
1757         ret = ring->add_request(ring, &seqno);
1758         if (ret)
1759             return ret;
1760
1761         trace_i915_gem_request_add(ring, seqno);
1762
1763         request->seqno = seqno;
1764         request->ring = ring;
1765         request->emitted_jiffies = jiffies;
1766         was_empty = list_empty(&ring->request_list);
1767         list_add_tail(&request->list, &ring->request_list);
1768
1769         if (file) {
1770                 struct drm_i915_file_private *file_priv = file->driver_priv;
1771
1772                 spin_lock(&file_priv->mm.lock);
1773                 request->file_priv = file_priv;
1774                 list_add_tail(&request->client_list,
1775                               &file_priv->mm.request_list);
1776                 spin_unlock(&file_priv->mm.lock);
1777         }
1778
1779         ring->outstanding_lazy_request = false;
1780
1781         if (!dev_priv->mm.suspended) {
1782                 mod_timer(&dev_priv->hangcheck_timer,
1783                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1784                 if (was_empty)
1785                         queue_delayed_work(dev_priv->wq,
1786                                            &dev_priv->mm.retire_work, HZ);
1787         }
1788         return 0;
1789 }
1790
1791 static inline void
1792 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1793 {
1794         struct drm_i915_file_private *file_priv = request->file_priv;
1795
1796         if (!file_priv)
1797                 return;
1798
1799         spin_lock(&file_priv->mm.lock);
1800         if (request->file_priv) {
1801                 list_del(&request->client_list);
1802                 request->file_priv = NULL;
1803         }
1804         spin_unlock(&file_priv->mm.lock);
1805 }
1806
1807 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1808                                       struct intel_ring_buffer *ring)
1809 {
1810         while (!list_empty(&ring->request_list)) {
1811                 struct drm_i915_gem_request *request;
1812
1813                 request = list_first_entry(&ring->request_list,
1814                                            struct drm_i915_gem_request,
1815                                            list);
1816
1817                 list_del(&request->list);
1818                 i915_gem_request_remove_from_client(request);
1819                 kfree(request);
1820         }
1821
1822         while (!list_empty(&ring->active_list)) {
1823                 struct drm_i915_gem_object *obj;
1824
1825                 obj = list_first_entry(&ring->active_list,
1826                                        struct drm_i915_gem_object,
1827                                        ring_list);
1828
1829                 obj->base.write_domain = 0;
1830                 list_del_init(&obj->gpu_write_list);
1831                 i915_gem_object_move_to_inactive(obj);
1832         }
1833 }
1834
1835 static void i915_gem_reset_fences(struct drm_device *dev)
1836 {
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         int i;
1839
1840         for (i = 0; i < 16; i++) {
1841                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1842                 struct drm_i915_gem_object *obj = reg->obj;
1843
1844                 if (!obj)
1845                         continue;
1846
1847                 if (obj->tiling_mode)
1848                         i915_gem_release_mmap(obj);
1849
1850                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1851                 reg->obj->fenced_gpu_access = false;
1852                 reg->obj->last_fenced_seqno = 0;
1853                 reg->obj->last_fenced_ring = NULL;
1854                 i915_gem_clear_fence_reg(dev, reg);
1855         }
1856 }
1857
1858 void i915_gem_reset(struct drm_device *dev)
1859 {
1860         struct drm_i915_private *dev_priv = dev->dev_private;
1861         struct drm_i915_gem_object *obj;
1862         int i;
1863
1864         for (i = 0; i < I915_NUM_RINGS; i++)
1865                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1866
1867         /* Remove anything from the flushing lists. The GPU cache is likely
1868          * to be lost on reset along with the data, so simply move the
1869          * lost bo to the inactive list.
1870          */
1871         while (!list_empty(&dev_priv->mm.flushing_list)) {
1872                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1873                                       struct drm_i915_gem_object,
1874                                       mm_list);
1875
1876                 obj->base.write_domain = 0;
1877                 list_del_init(&obj->gpu_write_list);
1878                 i915_gem_object_move_to_inactive(obj);
1879         }
1880
1881         /* Move everything out of the GPU domains to ensure we do any
1882          * necessary invalidation upon reuse.
1883          */
1884         list_for_each_entry(obj,
1885                             &dev_priv->mm.inactive_list,
1886                             mm_list)
1887         {
1888                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1889         }
1890
1891         /* The fence registers are invalidated so clear them out */
1892         i915_gem_reset_fences(dev);
1893 }
1894
1895 /**
1896  * This function clears the request list as sequence numbers are passed.
1897  */
1898 static void
1899 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1900 {
1901         uint32_t seqno;
1902         int i;
1903
1904         if (list_empty(&ring->request_list))
1905                 return;
1906
1907         WARN_ON(i915_verify_lists(ring->dev));
1908
1909         seqno = ring->get_seqno(ring);
1910
1911         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1912                 if (seqno >= ring->sync_seqno[i])
1913                         ring->sync_seqno[i] = 0;
1914
1915         while (!list_empty(&ring->request_list)) {
1916                 struct drm_i915_gem_request *request;
1917
1918                 request = list_first_entry(&ring->request_list,
1919                                            struct drm_i915_gem_request,
1920                                            list);
1921
1922                 if (!i915_seqno_passed(seqno, request->seqno))
1923                         break;
1924
1925                 trace_i915_gem_request_retire(ring, request->seqno);
1926
1927                 list_del(&request->list);
1928                 i915_gem_request_remove_from_client(request);
1929                 kfree(request);
1930         }
1931
1932         /* Move any buffers on the active list that are no longer referenced
1933          * by the ringbuffer to the flushing/inactive lists as appropriate.
1934          */
1935         while (!list_empty(&ring->active_list)) {
1936                 struct drm_i915_gem_object *obj;
1937
1938                 obj= list_first_entry(&ring->active_list,
1939                                       struct drm_i915_gem_object,
1940                                       ring_list);
1941
1942                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1943                         break;
1944
1945                 if (obj->base.write_domain != 0)
1946                         i915_gem_object_move_to_flushing(obj);
1947                 else
1948                         i915_gem_object_move_to_inactive(obj);
1949         }
1950
1951         if (unlikely(ring->trace_irq_seqno &&
1952                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1953                 ring->irq_put(ring);
1954                 ring->trace_irq_seqno = 0;
1955         }
1956
1957         WARN_ON(i915_verify_lists(ring->dev));
1958 }
1959
1960 void
1961 i915_gem_retire_requests(struct drm_device *dev)
1962 {
1963         drm_i915_private_t *dev_priv = dev->dev_private;
1964         int i;
1965
1966         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1967             struct drm_i915_gem_object *obj, *next;
1968
1969             /* We must be careful that during unbind() we do not
1970              * accidentally infinitely recurse into retire requests.
1971              * Currently:
1972              *   retire -> free -> unbind -> wait -> retire_ring
1973              */
1974             list_for_each_entry_safe(obj, next,
1975                                      &dev_priv->mm.deferred_free_list,
1976                                      mm_list)
1977                     i915_gem_free_object_tail(obj);
1978         }
1979
1980         for (i = 0; i < I915_NUM_RINGS; i++)
1981                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1982 }
1983
1984 static void
1985 i915_gem_retire_work_handler(struct work_struct *work)
1986 {
1987         drm_i915_private_t *dev_priv;
1988         struct drm_device *dev;
1989         bool idle;
1990         int i;
1991
1992         dev_priv = container_of(work, drm_i915_private_t,
1993                                 mm.retire_work.work);
1994         dev = dev_priv->dev;
1995
1996         /* Come back later if the device is busy... */
1997         if (!mutex_trylock(&dev->struct_mutex)) {
1998                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1999                 return;
2000         }
2001
2002         i915_gem_retire_requests(dev);
2003
2004         /* Send a periodic flush down the ring so we don't hold onto GEM
2005          * objects indefinitely.
2006          */
2007         idle = true;
2008         for (i = 0; i < I915_NUM_RINGS; i++) {
2009                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2010
2011                 if (!list_empty(&ring->gpu_write_list)) {
2012                         struct drm_i915_gem_request *request;
2013                         int ret;
2014
2015                         ret = i915_gem_flush_ring(ring,
2016                                                   0, I915_GEM_GPU_DOMAINS);
2017                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2018                         if (ret || request == NULL ||
2019                             i915_add_request(ring, NULL, request))
2020                             kfree(request);
2021                 }
2022
2023                 idle &= list_empty(&ring->request_list);
2024         }
2025
2026         if (!dev_priv->mm.suspended && !idle)
2027                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2028
2029         mutex_unlock(&dev->struct_mutex);
2030 }
2031
2032 /**
2033  * Waits for a sequence number to be signaled, and cleans up the
2034  * request and object lists appropriately for that event.
2035  */
2036 int
2037 i915_wait_request(struct intel_ring_buffer *ring,
2038                   uint32_t seqno)
2039 {
2040         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2041         u32 ier;
2042         int ret = 0;
2043
2044         BUG_ON(seqno == 0);
2045
2046         if (atomic_read(&dev_priv->mm.wedged)) {
2047                 struct completion *x = &dev_priv->error_completion;
2048                 bool recovery_complete;
2049                 unsigned long flags;
2050
2051                 /* Give the error handler a chance to run. */
2052                 spin_lock_irqsave(&x->wait.lock, flags);
2053                 recovery_complete = x->done > 0;
2054                 spin_unlock_irqrestore(&x->wait.lock, flags);
2055
2056                 return recovery_complete ? -EIO : -EAGAIN;
2057         }
2058
2059         if (seqno == ring->outstanding_lazy_request) {
2060                 struct drm_i915_gem_request *request;
2061
2062                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2063                 if (request == NULL)
2064                         return -ENOMEM;
2065
2066                 ret = i915_add_request(ring, NULL, request);
2067                 if (ret) {
2068                         kfree(request);
2069                         return ret;
2070                 }
2071
2072                 seqno = request->seqno;
2073         }
2074
2075         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2076                 if (HAS_PCH_SPLIT(ring->dev))
2077                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2078                 else
2079                         ier = I915_READ(IER);
2080                 if (!ier) {
2081                         DRM_ERROR("something (likely vbetool) disabled "
2082                                   "interrupts, re-enabling\n");
2083                         i915_driver_irq_preinstall(ring->dev);
2084                         i915_driver_irq_postinstall(ring->dev);
2085                 }
2086
2087                 trace_i915_gem_request_wait_begin(ring, seqno);
2088
2089                 ring->waiting_seqno = seqno;
2090                 if (ring->irq_get(ring)) {
2091                         if (dev_priv->mm.interruptible)
2092                                 ret = wait_event_interruptible(ring->irq_queue,
2093                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2094                                                                || atomic_read(&dev_priv->mm.wedged));
2095                         else
2096                                 wait_event(ring->irq_queue,
2097                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2098                                            || atomic_read(&dev_priv->mm.wedged));
2099
2100                         ring->irq_put(ring);
2101                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2102                                                       seqno) ||
2103                                     atomic_read(&dev_priv->mm.wedged), 3000))
2104                         ret = -EBUSY;
2105                 ring->waiting_seqno = 0;
2106
2107                 trace_i915_gem_request_wait_end(ring, seqno);
2108         }
2109         if (atomic_read(&dev_priv->mm.wedged))
2110                 ret = -EAGAIN;
2111
2112         if (ret && ret != -ERESTARTSYS)
2113                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2114                           __func__, ret, seqno, ring->get_seqno(ring),
2115                           dev_priv->next_seqno);
2116
2117         /* Directly dispatch request retiring.  While we have the work queue
2118          * to handle this, the waiter on a request often wants an associated
2119          * buffer to have made it to the inactive list, and we would need
2120          * a separate wait queue to handle that.
2121          */
2122         if (ret == 0)
2123                 i915_gem_retire_requests_ring(ring);
2124
2125         return ret;
2126 }
2127
2128 /**
2129  * Ensures that all rendering to the object has completed and the object is
2130  * safe to unbind from the GTT or access from the CPU.
2131  */
2132 int
2133 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2134 {
2135         int ret;
2136
2137         /* This function only exists to support waiting for existing rendering,
2138          * not for emitting required flushes.
2139          */
2140         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2141
2142         /* If there is rendering queued on the buffer being evicted, wait for
2143          * it.
2144          */
2145         if (obj->active) {
2146                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2147                 if (ret)
2148                         return ret;
2149         }
2150
2151         return 0;
2152 }
2153
2154 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2155 {
2156         u32 old_write_domain, old_read_domains;
2157
2158         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2159                 return;
2160
2161         /* Act a barrier for all accesses through the GTT */
2162         mb();
2163
2164         /* Force a pagefault for domain tracking on next user access */
2165         i915_gem_release_mmap(obj);
2166
2167         old_read_domains = obj->base.read_domains;
2168         old_write_domain = obj->base.write_domain;
2169
2170         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2171         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2172
2173         trace_i915_gem_object_change_domain(obj,
2174                                             old_read_domains,
2175                                             old_write_domain);
2176 }
2177
2178 /**
2179  * Unbinds an object from the GTT aperture.
2180  */
2181 int
2182 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2183 {
2184         int ret = 0;
2185
2186         if (obj->gtt_space == NULL)
2187                 return 0;
2188
2189         if (obj->pin_count != 0) {
2190                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2191                 return -EINVAL;
2192         }
2193
2194         ret = i915_gem_object_finish_gpu(obj);
2195         if (ret == -ERESTARTSYS)
2196                 return ret;
2197         /* Continue on if we fail due to EIO, the GPU is hung so we
2198          * should be safe and we need to cleanup or else we might
2199          * cause memory corruption through use-after-free.
2200          */
2201
2202         i915_gem_object_finish_gtt(obj);
2203
2204         /* Move the object to the CPU domain to ensure that
2205          * any possible CPU writes while it's not in the GTT
2206          * are flushed when we go to remap it.
2207          */
2208         if (ret == 0)
2209                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2210         if (ret == -ERESTARTSYS)
2211                 return ret;
2212         if (ret) {
2213                 /* In the event of a disaster, abandon all caches and
2214                  * hope for the best.
2215                  */
2216                 i915_gem_clflush_object(obj);
2217                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2218         }
2219
2220         /* release the fence reg _after_ flushing */
2221         ret = i915_gem_object_put_fence(obj);
2222         if (ret == -ERESTARTSYS)
2223                 return ret;
2224
2225         trace_i915_gem_object_unbind(obj);
2226
2227         i915_gem_gtt_unbind_object(obj);
2228         i915_gem_object_put_pages_gtt(obj);
2229
2230         list_del_init(&obj->gtt_list);
2231         list_del_init(&obj->mm_list);
2232         /* Avoid an unnecessary call to unbind on rebind. */
2233         obj->map_and_fenceable = true;
2234
2235         drm_mm_put_block(obj->gtt_space);
2236         obj->gtt_space = NULL;
2237         obj->gtt_offset = 0;
2238
2239         if (i915_gem_object_is_purgeable(obj))
2240                 i915_gem_object_truncate(obj);
2241
2242         return ret;
2243 }
2244
2245 int
2246 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2247                     uint32_t invalidate_domains,
2248                     uint32_t flush_domains)
2249 {
2250         int ret;
2251
2252         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2253                 return 0;
2254
2255         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2256
2257         ret = ring->flush(ring, invalidate_domains, flush_domains);
2258         if (ret)
2259                 return ret;
2260
2261         if (flush_domains & I915_GEM_GPU_DOMAINS)
2262                 i915_gem_process_flushing_list(ring, flush_domains);
2263
2264         return 0;
2265 }
2266
2267 static int i915_ring_idle(struct intel_ring_buffer *ring)
2268 {
2269         int ret;
2270
2271         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2272                 return 0;
2273
2274         if (!list_empty(&ring->gpu_write_list)) {
2275                 ret = i915_gem_flush_ring(ring,
2276                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2277                 if (ret)
2278                         return ret;
2279         }
2280
2281         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2282 }
2283
2284 int
2285 i915_gpu_idle(struct drm_device *dev)
2286 {
2287         drm_i915_private_t *dev_priv = dev->dev_private;
2288         bool lists_empty;
2289         int ret, i;
2290
2291         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2292                        list_empty(&dev_priv->mm.active_list));
2293         if (lists_empty)
2294                 return 0;
2295
2296         /* Flush everything onto the inactive list. */
2297         for (i = 0; i < I915_NUM_RINGS; i++) {
2298                 ret = i915_ring_idle(&dev_priv->ring[i]);
2299                 if (ret)
2300                         return ret;
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2307                                        struct intel_ring_buffer *pipelined)
2308 {
2309         struct drm_device *dev = obj->base.dev;
2310         drm_i915_private_t *dev_priv = dev->dev_private;
2311         u32 size = obj->gtt_space->size;
2312         int regnum = obj->fence_reg;
2313         uint64_t val;
2314
2315         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2316                          0xfffff000) << 32;
2317         val |= obj->gtt_offset & 0xfffff000;
2318         val |= (uint64_t)((obj->stride / 128) - 1) <<
2319                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2320
2321         if (obj->tiling_mode == I915_TILING_Y)
2322                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2323         val |= I965_FENCE_REG_VALID;
2324
2325         if (pipelined) {
2326                 int ret = intel_ring_begin(pipelined, 6);
2327                 if (ret)
2328                         return ret;
2329
2330                 intel_ring_emit(pipelined, MI_NOOP);
2331                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2332                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2333                 intel_ring_emit(pipelined, (u32)val);
2334                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2335                 intel_ring_emit(pipelined, (u32)(val >> 32));
2336                 intel_ring_advance(pipelined);
2337         } else
2338                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2339
2340         return 0;
2341 }
2342
2343 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2344                                 struct intel_ring_buffer *pipelined)
2345 {
2346         struct drm_device *dev = obj->base.dev;
2347         drm_i915_private_t *dev_priv = dev->dev_private;
2348         u32 size = obj->gtt_space->size;
2349         int regnum = obj->fence_reg;
2350         uint64_t val;
2351
2352         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2353                     0xfffff000) << 32;
2354         val |= obj->gtt_offset & 0xfffff000;
2355         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2356         if (obj->tiling_mode == I915_TILING_Y)
2357                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2358         val |= I965_FENCE_REG_VALID;
2359
2360         if (pipelined) {
2361                 int ret = intel_ring_begin(pipelined, 6);
2362                 if (ret)
2363                         return ret;
2364
2365                 intel_ring_emit(pipelined, MI_NOOP);
2366                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2367                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2368                 intel_ring_emit(pipelined, (u32)val);
2369                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2370                 intel_ring_emit(pipelined, (u32)(val >> 32));
2371                 intel_ring_advance(pipelined);
2372         } else
2373                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2374
2375         return 0;
2376 }
2377
2378 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2379                                 struct intel_ring_buffer *pipelined)
2380 {
2381         struct drm_device *dev = obj->base.dev;
2382         drm_i915_private_t *dev_priv = dev->dev_private;
2383         u32 size = obj->gtt_space->size;
2384         u32 fence_reg, val, pitch_val;
2385         int tile_width;
2386
2387         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2388                  (size & -size) != size ||
2389                  (obj->gtt_offset & (size - 1)),
2390                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2391                  obj->gtt_offset, obj->map_and_fenceable, size))
2392                 return -EINVAL;
2393
2394         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2395                 tile_width = 128;
2396         else
2397                 tile_width = 512;
2398
2399         /* Note: pitch better be a power of two tile widths */
2400         pitch_val = obj->stride / tile_width;
2401         pitch_val = ffs(pitch_val) - 1;
2402
2403         val = obj->gtt_offset;
2404         if (obj->tiling_mode == I915_TILING_Y)
2405                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2406         val |= I915_FENCE_SIZE_BITS(size);
2407         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2408         val |= I830_FENCE_REG_VALID;
2409
2410         fence_reg = obj->fence_reg;
2411         if (fence_reg < 8)
2412                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2413         else
2414                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2415
2416         if (pipelined) {
2417                 int ret = intel_ring_begin(pipelined, 4);
2418                 if (ret)
2419                         return ret;
2420
2421                 intel_ring_emit(pipelined, MI_NOOP);
2422                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2423                 intel_ring_emit(pipelined, fence_reg);
2424                 intel_ring_emit(pipelined, val);
2425                 intel_ring_advance(pipelined);
2426         } else
2427                 I915_WRITE(fence_reg, val);
2428
2429         return 0;
2430 }
2431
2432 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2433                                 struct intel_ring_buffer *pipelined)
2434 {
2435         struct drm_device *dev = obj->base.dev;
2436         drm_i915_private_t *dev_priv = dev->dev_private;
2437         u32 size = obj->gtt_space->size;
2438         int regnum = obj->fence_reg;
2439         uint32_t val;
2440         uint32_t pitch_val;
2441
2442         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2443                  (size & -size) != size ||
2444                  (obj->gtt_offset & (size - 1)),
2445                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2446                  obj->gtt_offset, size))
2447                 return -EINVAL;
2448
2449         pitch_val = obj->stride / 128;
2450         pitch_val = ffs(pitch_val) - 1;
2451
2452         val = obj->gtt_offset;
2453         if (obj->tiling_mode == I915_TILING_Y)
2454                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2455         val |= I830_FENCE_SIZE_BITS(size);
2456         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2457         val |= I830_FENCE_REG_VALID;
2458
2459         if (pipelined) {
2460                 int ret = intel_ring_begin(pipelined, 4);
2461                 if (ret)
2462                         return ret;
2463
2464                 intel_ring_emit(pipelined, MI_NOOP);
2465                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2466                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2467                 intel_ring_emit(pipelined, val);
2468                 intel_ring_advance(pipelined);
2469         } else
2470                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2471
2472         return 0;
2473 }
2474
2475 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2476 {
2477         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2478 }
2479
2480 static int
2481 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2482                             struct intel_ring_buffer *pipelined)
2483 {
2484         int ret;
2485
2486         if (obj->fenced_gpu_access) {
2487                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2488                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2489                                                   0, obj->base.write_domain);
2490                         if (ret)
2491                                 return ret;
2492                 }
2493
2494                 obj->fenced_gpu_access = false;
2495         }
2496
2497         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2498                 if (!ring_passed_seqno(obj->last_fenced_ring,
2499                                        obj->last_fenced_seqno)) {
2500                         ret = i915_wait_request(obj->last_fenced_ring,
2501                                                 obj->last_fenced_seqno);
2502                         if (ret)
2503                                 return ret;
2504                 }
2505
2506                 obj->last_fenced_seqno = 0;
2507                 obj->last_fenced_ring = NULL;
2508         }
2509
2510         /* Ensure that all CPU reads are completed before installing a fence
2511          * and all writes before removing the fence.
2512          */
2513         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2514                 mb();
2515
2516         return 0;
2517 }
2518
2519 int
2520 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2521 {
2522         int ret;
2523
2524         if (obj->tiling_mode)
2525                 i915_gem_release_mmap(obj);
2526
2527         ret = i915_gem_object_flush_fence(obj, NULL);
2528         if (ret)
2529                 return ret;
2530
2531         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2532                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2533                 i915_gem_clear_fence_reg(obj->base.dev,
2534                                          &dev_priv->fence_regs[obj->fence_reg]);
2535
2536                 obj->fence_reg = I915_FENCE_REG_NONE;
2537         }
2538
2539         return 0;
2540 }
2541
2542 static struct drm_i915_fence_reg *
2543 i915_find_fence_reg(struct drm_device *dev,
2544                     struct intel_ring_buffer *pipelined)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct drm_i915_fence_reg *reg, *first, *avail;
2548         int i;
2549
2550         /* First try to find a free reg */
2551         avail = NULL;
2552         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2553                 reg = &dev_priv->fence_regs[i];
2554                 if (!reg->obj)
2555                         return reg;
2556
2557                 if (!reg->obj->pin_count)
2558                         avail = reg;
2559         }
2560
2561         if (avail == NULL)
2562                 return NULL;
2563
2564         /* None available, try to steal one or wait for a user to finish */
2565         avail = first = NULL;
2566         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2567                 if (reg->obj->pin_count)
2568                         continue;
2569
2570                 if (first == NULL)
2571                         first = reg;
2572
2573                 if (!pipelined ||
2574                     !reg->obj->last_fenced_ring ||
2575                     reg->obj->last_fenced_ring == pipelined) {
2576                         avail = reg;
2577                         break;
2578                 }
2579         }
2580
2581         if (avail == NULL)
2582                 avail = first;
2583
2584         return avail;
2585 }
2586
2587 /**
2588  * i915_gem_object_get_fence - set up a fence reg for an object
2589  * @obj: object to map through a fence reg
2590  * @pipelined: ring on which to queue the change, or NULL for CPU access
2591  * @interruptible: must we wait uninterruptibly for the register to retire?
2592  *
2593  * When mapping objects through the GTT, userspace wants to be able to write
2594  * to them without having to worry about swizzling if the object is tiled.
2595  *
2596  * This function walks the fence regs looking for a free one for @obj,
2597  * stealing one if it can't find any.
2598  *
2599  * It then sets up the reg based on the object's properties: address, pitch
2600  * and tiling format.
2601  */
2602 int
2603 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2604                           struct intel_ring_buffer *pipelined)
2605 {
2606         struct drm_device *dev = obj->base.dev;
2607         struct drm_i915_private *dev_priv = dev->dev_private;
2608         struct drm_i915_fence_reg *reg;
2609         int ret;
2610
2611         /* XXX disable pipelining. There are bugs. Shocking. */
2612         pipelined = NULL;
2613
2614         /* Just update our place in the LRU if our fence is getting reused. */
2615         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2616                 reg = &dev_priv->fence_regs[obj->fence_reg];
2617                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2618
2619                 if (obj->tiling_changed) {
2620                         ret = i915_gem_object_flush_fence(obj, pipelined);
2621                         if (ret)
2622                                 return ret;
2623
2624                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2625                                 pipelined = NULL;
2626
2627                         if (pipelined) {
2628                                 reg->setup_seqno =
2629                                         i915_gem_next_request_seqno(pipelined);
2630                                 obj->last_fenced_seqno = reg->setup_seqno;
2631                                 obj->last_fenced_ring = pipelined;
2632                         }
2633
2634                         goto update;
2635                 }
2636
2637                 if (!pipelined) {
2638                         if (reg->setup_seqno) {
2639                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2640                                                        reg->setup_seqno)) {
2641                                         ret = i915_wait_request(obj->last_fenced_ring,
2642                                                                 reg->setup_seqno);
2643                                         if (ret)
2644                                                 return ret;
2645                                 }
2646
2647                                 reg->setup_seqno = 0;
2648                         }
2649                 } else if (obj->last_fenced_ring &&
2650                            obj->last_fenced_ring != pipelined) {
2651                         ret = i915_gem_object_flush_fence(obj, pipelined);
2652                         if (ret)
2653                                 return ret;
2654                 }
2655
2656                 return 0;
2657         }
2658
2659         reg = i915_find_fence_reg(dev, pipelined);
2660         if (reg == NULL)
2661                 return -ENOSPC;
2662
2663         ret = i915_gem_object_flush_fence(obj, pipelined);
2664         if (ret)
2665                 return ret;
2666
2667         if (reg->obj) {
2668                 struct drm_i915_gem_object *old = reg->obj;
2669
2670                 drm_gem_object_reference(&old->base);
2671
2672                 if (old->tiling_mode)
2673                         i915_gem_release_mmap(old);
2674
2675                 ret = i915_gem_object_flush_fence(old, pipelined);
2676                 if (ret) {
2677                         drm_gem_object_unreference(&old->base);
2678                         return ret;
2679                 }
2680
2681                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2682                         pipelined = NULL;
2683
2684                 old->fence_reg = I915_FENCE_REG_NONE;
2685                 old->last_fenced_ring = pipelined;
2686                 old->last_fenced_seqno =
2687                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2688
2689                 drm_gem_object_unreference(&old->base);
2690         } else if (obj->last_fenced_seqno == 0)
2691                 pipelined = NULL;
2692
2693         reg->obj = obj;
2694         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2695         obj->fence_reg = reg - dev_priv->fence_regs;
2696         obj->last_fenced_ring = pipelined;
2697
2698         reg->setup_seqno =
2699                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2700         obj->last_fenced_seqno = reg->setup_seqno;
2701
2702 update:
2703         obj->tiling_changed = false;
2704         switch (INTEL_INFO(dev)->gen) {
2705         case 7:
2706         case 6:
2707                 ret = sandybridge_write_fence_reg(obj, pipelined);
2708                 break;
2709         case 5:
2710         case 4:
2711                 ret = i965_write_fence_reg(obj, pipelined);
2712                 break;
2713         case 3:
2714                 ret = i915_write_fence_reg(obj, pipelined);
2715                 break;
2716         case 2:
2717                 ret = i830_write_fence_reg(obj, pipelined);
2718                 break;
2719         }
2720
2721         return ret;
2722 }
2723
2724 /**
2725  * i915_gem_clear_fence_reg - clear out fence register info
2726  * @obj: object to clear
2727  *
2728  * Zeroes out the fence register itself and clears out the associated
2729  * data structures in dev_priv and obj.
2730  */
2731 static void
2732 i915_gem_clear_fence_reg(struct drm_device *dev,
2733                          struct drm_i915_fence_reg *reg)
2734 {
2735         drm_i915_private_t *dev_priv = dev->dev_private;
2736         uint32_t fence_reg = reg - dev_priv->fence_regs;
2737
2738         switch (INTEL_INFO(dev)->gen) {
2739         case 7:
2740         case 6:
2741                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2742                 break;
2743         case 5:
2744         case 4:
2745                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2746                 break;
2747         case 3:
2748                 if (fence_reg >= 8)
2749                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2750                 else
2751         case 2:
2752                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2753
2754                 I915_WRITE(fence_reg, 0);
2755                 break;
2756         }
2757
2758         list_del_init(&reg->lru_list);
2759         reg->obj = NULL;
2760         reg->setup_seqno = 0;
2761 }
2762
2763 /**
2764  * Finds free space in the GTT aperture and binds the object there.
2765  */
2766 static int
2767 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2768                             unsigned alignment,
2769                             bool map_and_fenceable)
2770 {
2771         struct drm_device *dev = obj->base.dev;
2772         drm_i915_private_t *dev_priv = dev->dev_private;
2773         struct drm_mm_node *free_space;
2774         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2775         u32 size, fence_size, fence_alignment, unfenced_alignment;
2776         bool mappable, fenceable;
2777         int ret;
2778
2779         if (obj->madv != I915_MADV_WILLNEED) {
2780                 DRM_ERROR("Attempting to bind a purgeable object\n");
2781                 return -EINVAL;
2782         }
2783
2784         fence_size = i915_gem_get_gtt_size(obj);
2785         fence_alignment = i915_gem_get_gtt_alignment(obj);
2786         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2787
2788         if (alignment == 0)
2789                 alignment = map_and_fenceable ? fence_alignment :
2790                                                 unfenced_alignment;
2791         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2792                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2793                 return -EINVAL;
2794         }
2795
2796         size = map_and_fenceable ? fence_size : obj->base.size;
2797
2798         /* If the object is bigger than the entire aperture, reject it early
2799          * before evicting everything in a vain attempt to find space.
2800          */
2801         if (obj->base.size >
2802             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2803                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2804                 return -E2BIG;
2805         }
2806
2807  search_free:
2808         if (map_and_fenceable)
2809                 free_space =
2810                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2811                                                     size, alignment, 0,
2812                                                     dev_priv->mm.gtt_mappable_end,
2813                                                     0);
2814         else
2815                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2816                                                 size, alignment, 0);
2817
2818         if (free_space != NULL) {
2819                 if (map_and_fenceable)
2820                         obj->gtt_space =
2821                                 drm_mm_get_block_range_generic(free_space,
2822                                                                size, alignment, 0,
2823                                                                dev_priv->mm.gtt_mappable_end,
2824                                                                0);
2825                 else
2826                         obj->gtt_space =
2827                                 drm_mm_get_block(free_space, size, alignment);
2828         }
2829         if (obj->gtt_space == NULL) {
2830                 /* If the gtt is empty and we're still having trouble
2831                  * fitting our object in, we're out of memory.
2832                  */
2833                 ret = i915_gem_evict_something(dev, size, alignment,
2834                                                map_and_fenceable);
2835                 if (ret)
2836                         return ret;
2837
2838                 goto search_free;
2839         }
2840
2841         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2842         if (ret) {
2843                 drm_mm_put_block(obj->gtt_space);
2844                 obj->gtt_space = NULL;
2845
2846                 if (ret == -ENOMEM) {
2847                         /* first try to reclaim some memory by clearing the GTT */
2848                         ret = i915_gem_evict_everything(dev, false);
2849                         if (ret) {
2850                                 /* now try to shrink everyone else */
2851                                 if (gfpmask) {
2852                                         gfpmask = 0;
2853                                         goto search_free;
2854                                 }
2855
2856                                 return -ENOMEM;
2857                         }
2858
2859                         goto search_free;
2860                 }
2861
2862                 return ret;
2863         }
2864
2865         ret = i915_gem_gtt_bind_object(obj);
2866         if (ret) {
2867                 i915_gem_object_put_pages_gtt(obj);
2868                 drm_mm_put_block(obj->gtt_space);
2869                 obj->gtt_space = NULL;
2870
2871                 if (i915_gem_evict_everything(dev, false))
2872                         return ret;
2873
2874                 goto search_free;
2875         }
2876
2877         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2878         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2879
2880         /* Assert that the object is not currently in any GPU domain. As it
2881          * wasn't in the GTT, there shouldn't be any way it could have been in
2882          * a GPU cache
2883          */
2884         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2885         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2886
2887         obj->gtt_offset = obj->gtt_space->start;
2888
2889         fenceable =
2890                 obj->gtt_space->size == fence_size &&
2891                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2892
2893         mappable =
2894                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2895
2896         obj->map_and_fenceable = mappable && fenceable;
2897
2898         trace_i915_gem_object_bind(obj, map_and_fenceable);
2899         return 0;
2900 }
2901
2902 void
2903 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2904 {
2905         /* If we don't have a page list set up, then we're not pinned
2906          * to GPU, and we can ignore the cache flush because it'll happen
2907          * again at bind time.
2908          */
2909         if (obj->pages == NULL)
2910                 return;
2911
2912         /* If the GPU is snooping the contents of the CPU cache,
2913          * we do not need to manually clear the CPU cache lines.  However,
2914          * the caches are only snooped when the render cache is
2915          * flushed/invalidated.  As we always have to emit invalidations
2916          * and flushes when moving into and out of the RENDER domain, correct
2917          * snooping behaviour occurs naturally as the result of our domain
2918          * tracking.
2919          */
2920         if (obj->cache_level != I915_CACHE_NONE)
2921                 return;
2922
2923         trace_i915_gem_object_clflush(obj);
2924
2925         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2926 }
2927
2928 /** Flushes any GPU write domain for the object if it's dirty. */
2929 static int
2930 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2931 {
2932         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2933                 return 0;
2934
2935         /* Queue the GPU write cache flushing we need. */
2936         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2937 }
2938
2939 /** Flushes the GTT write domain for the object if it's dirty. */
2940 static void
2941 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2942 {
2943         uint32_t old_write_domain;
2944
2945         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2946                 return;
2947
2948         /* No actual flushing is required for the GTT write domain.  Writes
2949          * to it immediately go to main memory as far as we know, so there's
2950          * no chipset flush.  It also doesn't land in render cache.
2951          *
2952          * However, we do have to enforce the order so that all writes through
2953          * the GTT land before any writes to the device, such as updates to
2954          * the GATT itself.
2955          */
2956         wmb();
2957
2958         old_write_domain = obj->base.write_domain;
2959         obj->base.write_domain = 0;
2960
2961         trace_i915_gem_object_change_domain(obj,
2962                                             obj->base.read_domains,
2963                                             old_write_domain);
2964 }
2965
2966 /** Flushes the CPU write domain for the object if it's dirty. */
2967 static void
2968 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2969 {
2970         uint32_t old_write_domain;
2971
2972         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2973                 return;
2974
2975         i915_gem_clflush_object(obj);
2976         intel_gtt_chipset_flush();
2977         old_write_domain = obj->base.write_domain;
2978         obj->base.write_domain = 0;
2979
2980         trace_i915_gem_object_change_domain(obj,
2981                                             obj->base.read_domains,
2982                                             old_write_domain);
2983 }
2984
2985 /**
2986  * Moves a single object to the GTT read, and possibly write domain.
2987  *
2988  * This function returns when the move is complete, including waiting on
2989  * flushes to occur.
2990  */
2991 int
2992 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2993 {
2994         uint32_t old_write_domain, old_read_domains;
2995         int ret;
2996
2997         /* Not valid to be called on unbound objects. */
2998         if (obj->gtt_space == NULL)
2999                 return -EINVAL;
3000
3001         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3002                 return 0;
3003
3004         ret = i915_gem_object_flush_gpu_write_domain(obj);
3005         if (ret)
3006                 return ret;
3007
3008         if (obj->pending_gpu_write || write) {
3009                 ret = i915_gem_object_wait_rendering(obj);
3010                 if (ret)
3011                         return ret;
3012         }
3013
3014         i915_gem_object_flush_cpu_write_domain(obj);
3015
3016         old_write_domain = obj->base.write_domain;
3017         old_read_domains = obj->base.read_domains;
3018
3019         /* It should now be out of any other write domains, and we can update
3020          * the domain values for our changes.
3021          */
3022         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3023         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3024         if (write) {
3025                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3026                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3027                 obj->dirty = 1;
3028         }
3029
3030         trace_i915_gem_object_change_domain(obj,
3031                                             old_read_domains,
3032                                             old_write_domain);
3033
3034         return 0;
3035 }
3036
3037 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3038                                     enum i915_cache_level cache_level)
3039 {
3040         int ret;
3041
3042         if (obj->cache_level == cache_level)
3043                 return 0;
3044
3045         if (obj->pin_count) {
3046                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3047                 return -EBUSY;
3048         }
3049
3050         if (obj->gtt_space) {
3051                 ret = i915_gem_object_finish_gpu(obj);
3052                 if (ret)
3053                         return ret;
3054
3055                 i915_gem_object_finish_gtt(obj);
3056
3057                 /* Before SandyBridge, you could not use tiling or fence
3058                  * registers with snooped memory, so relinquish any fences
3059                  * currently pointing to our region in the aperture.
3060                  */
3061                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3062                         ret = i915_gem_object_put_fence(obj);
3063                         if (ret)
3064                                 return ret;
3065                 }
3066
3067                 i915_gem_gtt_rebind_object(obj, cache_level);
3068         }
3069
3070         if (cache_level == I915_CACHE_NONE) {
3071                 u32 old_read_domains, old_write_domain;
3072
3073                 /* If we're coming from LLC cached, then we haven't
3074                  * actually been tracking whether the data is in the
3075                  * CPU cache or not, since we only allow one bit set
3076                  * in obj->write_domain and have been skipping the clflushes.
3077                  * Just set it to the CPU cache for now.
3078                  */
3079                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3080                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3081
3082                 old_read_domains = obj->base.read_domains;
3083                 old_write_domain = obj->base.write_domain;
3084
3085                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3086                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3087
3088                 trace_i915_gem_object_change_domain(obj,
3089                                                     old_read_domains,
3090                                                     old_write_domain);
3091         }
3092
3093         obj->cache_level = cache_level;
3094         return 0;
3095 }
3096
3097 /*
3098  * Prepare buffer for display plane (scanout, cursors, etc).
3099  * Can be called from an uninterruptible phase (modesetting) and allows
3100  * any flushes to be pipelined (for pageflips).
3101  *
3102  * For the display plane, we want to be in the GTT but out of any write
3103  * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3104  * ability to pipeline the waits, pinning and any additional subtleties
3105  * that may differentiate the display plane from ordinary buffers.
3106  */
3107 int
3108 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3109                                      u32 alignment,
3110                                      struct intel_ring_buffer *pipelined)
3111 {
3112         u32 old_read_domains, old_write_domain;
3113         int ret;
3114
3115         ret = i915_gem_object_flush_gpu_write_domain(obj);
3116         if (ret)
3117                 return ret;
3118
3119         if (pipelined != obj->ring) {
3120                 ret = i915_gem_object_wait_rendering(obj);
3121                 if (ret)
3122                         return ret;
3123         }
3124
3125         /* The display engine is not coherent with the LLC cache on gen6.  As
3126          * a result, we make sure that the pinning that is about to occur is
3127          * done with uncached PTEs. This is lowest common denominator for all
3128          * chipsets.
3129          *
3130          * However for gen6+, we could do better by using the GFDT bit instead
3131          * of uncaching, which would allow us to flush all the LLC-cached data
3132          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3133          */
3134         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3135         if (ret)
3136                 return ret;
3137
3138         /* As the user may map the buffer once pinned in the display plane
3139          * (e.g. libkms for the bootup splash), we have to ensure that we
3140          * always use map_and_fenceable for all scanout buffers.
3141          */
3142         ret = i915_gem_object_pin(obj, alignment, true);
3143         if (ret)
3144                 return ret;
3145
3146         i915_gem_object_flush_cpu_write_domain(obj);
3147
3148         old_write_domain = obj->base.write_domain;
3149         old_read_domains = obj->base.read_domains;
3150
3151         /* It should now be out of any other write domains, and we can update
3152          * the domain values for our changes.
3153          */
3154         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3155         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3156
3157         trace_i915_gem_object_change_domain(obj,
3158                                             old_read_domains,
3159                                             old_write_domain);
3160
3161         return 0;
3162 }
3163
3164 int
3165 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3166 {
3167         int ret;
3168
3169         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3170                 return 0;
3171
3172         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3173                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3174                 if (ret)
3175                         return ret;
3176         }
3177
3178         /* Ensure that we invalidate the GPU's caches and TLBs. */
3179         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3180
3181         return i915_gem_object_wait_rendering(obj);
3182 }
3183
3184 /**
3185  * Moves a single object to the CPU read, and possibly write domain.
3186  *
3187  * This function returns when the move is complete, including waiting on
3188  * flushes to occur.
3189  */
3190 static int
3191 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3192 {
3193         uint32_t old_write_domain, old_read_domains;
3194         int ret;
3195
3196         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3197                 return 0;
3198
3199         ret = i915_gem_object_flush_gpu_write_domain(obj);
3200         if (ret)
3201                 return ret;
3202
3203         ret = i915_gem_object_wait_rendering(obj);
3204         if (ret)
3205                 return ret;
3206
3207         i915_gem_object_flush_gtt_write_domain(obj);
3208
3209         /* If we have a partially-valid cache of the object in the CPU,
3210          * finish invalidating it and free the per-page flags.
3211          */
3212         i915_gem_object_set_to_full_cpu_read_domain(obj);
3213
3214         old_write_domain = obj->base.write_domain;
3215         old_read_domains = obj->base.read_domains;
3216
3217         /* Flush the CPU cache if it's still invalid. */
3218         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3219                 i915_gem_clflush_object(obj);
3220
3221                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3222         }
3223
3224         /* It should now be out of any other write domains, and we can update
3225          * the domain values for our changes.
3226          */
3227         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3228
3229         /* If we're writing through the CPU, then the GPU read domains will
3230          * need to be invalidated at next use.
3231          */
3232         if (write) {
3233                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3234                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3235         }
3236
3237         trace_i915_gem_object_change_domain(obj,
3238                                             old_read_domains,
3239                                             old_write_domain);
3240
3241         return 0;
3242 }
3243
3244 /**
3245  * Moves the object from a partially CPU read to a full one.
3246  *
3247  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3248  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3249  */
3250 static void
3251 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3252 {
3253         if (!obj->page_cpu_valid)
3254                 return;
3255
3256         /* If we're partially in the CPU read domain, finish moving it in.
3257          */
3258         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3259                 int i;
3260
3261                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3262                         if (obj->page_cpu_valid[i])
3263                                 continue;
3264                         drm_clflush_pages(obj->pages + i, 1);
3265                 }
3266         }
3267
3268         /* Free the page_cpu_valid mappings which are now stale, whether
3269          * or not we've got I915_GEM_DOMAIN_CPU.
3270          */
3271         kfree(obj->page_cpu_valid);
3272         obj->page_cpu_valid = NULL;
3273 }
3274
3275 /**
3276  * Set the CPU read domain on a range of the object.
3277  *
3278  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3279  * not entirely valid.  The page_cpu_valid member of the object flags which
3280  * pages have been flushed, and will be respected by
3281  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3282  * of the whole object.
3283  *
3284  * This function returns when the move is complete, including waiting on
3285  * flushes to occur.
3286  */
3287 static int
3288 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3289                                           uint64_t offset, uint64_t size)
3290 {
3291         uint32_t old_read_domains;
3292         int i, ret;
3293
3294         if (offset == 0 && size == obj->base.size)
3295                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3296
3297         ret = i915_gem_object_flush_gpu_write_domain(obj);
3298         if (ret)
3299                 return ret;
3300
3301         ret = i915_gem_object_wait_rendering(obj);
3302         if (ret)
3303                 return ret;
3304
3305         i915_gem_object_flush_gtt_write_domain(obj);
3306
3307         /* If we're already fully in the CPU read domain, we're done. */
3308         if (obj->page_cpu_valid == NULL &&
3309             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3310                 return 0;
3311
3312         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3313          * newly adding I915_GEM_DOMAIN_CPU
3314          */
3315         if (obj->page_cpu_valid == NULL) {
3316                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3317                                               GFP_KERNEL);
3318                 if (obj->page_cpu_valid == NULL)
3319                         return -ENOMEM;
3320         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3321                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3322
3323         /* Flush the cache on any pages that are still invalid from the CPU's
3324          * perspective.
3325          */
3326         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3327              i++) {
3328                 if (obj->page_cpu_valid[i])
3329                         continue;
3330
3331                 drm_clflush_pages(obj->pages + i, 1);
3332
3333                 obj->page_cpu_valid[i] = 1;
3334         }
3335
3336         /* It should now be out of any other write domains, and we can update
3337          * the domain values for our changes.
3338          */
3339         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3340
3341         old_read_domains = obj->base.read_domains;
3342         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3343
3344         trace_i915_gem_object_change_domain(obj,
3345                                             old_read_domains,
3346                                             obj->base.write_domain);
3347
3348         return 0;
3349 }
3350
3351 /* Throttle our rendering by waiting until the ring has completed our requests
3352  * emitted over 20 msec ago.
3353  *
3354  * Note that if we were to use the current jiffies each time around the loop,
3355  * we wouldn't escape the function with any frames outstanding if the time to
3356  * render a frame was over 20ms.
3357  *
3358  * This should get us reasonable parallelism between CPU and GPU but also
3359  * relatively low latency when blocking on a particular request to finish.
3360  */
3361 static int
3362 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3363 {
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365         struct drm_i915_file_private *file_priv = file->driver_priv;
3366         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3367         struct drm_i915_gem_request *request;
3368         struct intel_ring_buffer *ring = NULL;
3369         u32 seqno = 0;
3370         int ret;
3371
3372         if (atomic_read(&dev_priv->mm.wedged))
3373                 return -EIO;
3374
3375         spin_lock(&file_priv->mm.lock);
3376         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3377                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3378                         break;
3379
3380                 ring = request->ring;
3381                 seqno = request->seqno;
3382         }
3383         spin_unlock(&file_priv->mm.lock);
3384
3385         if (seqno == 0)
3386                 return 0;
3387
3388         ret = 0;
3389         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3390                 /* And wait for the seqno passing without holding any locks and
3391                  * causing extra latency for others. This is safe as the irq
3392                  * generation is designed to be run atomically and so is
3393                  * lockless.
3394                  */
3395                 if (ring->irq_get(ring)) {
3396                         ret = wait_event_interruptible(ring->irq_queue,
3397                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3398                                                        || atomic_read(&dev_priv->mm.wedged));
3399                         ring->irq_put(ring);
3400
3401                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3402                                 ret = -EIO;
3403                 }
3404         }
3405
3406         if (ret == 0)
3407                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3408
3409         return ret;
3410 }
3411
3412 int
3413 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3414                     uint32_t alignment,
3415                     bool map_and_fenceable)
3416 {
3417         struct drm_device *dev = obj->base.dev;
3418         struct drm_i915_private *dev_priv = dev->dev_private;
3419         int ret;
3420
3421         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3422         WARN_ON(i915_verify_lists(dev));
3423
3424         if (obj->gtt_space != NULL) {
3425                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3426                     (map_and_fenceable && !obj->map_and_fenceable)) {
3427                         WARN(obj->pin_count,
3428                              "bo is already pinned with incorrect alignment:"
3429                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3430                              " obj->map_and_fenceable=%d\n",
3431                              obj->gtt_offset, alignment,
3432                              map_and_fenceable,
3433                              obj->map_and_fenceable);
3434                         ret = i915_gem_object_unbind(obj);
3435                         if (ret)
3436                                 return ret;
3437                 }
3438         }
3439
3440         if (obj->gtt_space == NULL) {
3441                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3442                                                   map_and_fenceable);
3443                 if (ret)
3444                         return ret;
3445         }
3446
3447         if (obj->pin_count++ == 0) {
3448                 if (!obj->active)
3449                         list_move_tail(&obj->mm_list,
3450                                        &dev_priv->mm.pinned_list);
3451         }
3452         obj->pin_mappable |= map_and_fenceable;
3453
3454         WARN_ON(i915_verify_lists(dev));
3455         return 0;
3456 }
3457
3458 void
3459 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3460 {
3461         struct drm_device *dev = obj->base.dev;
3462         drm_i915_private_t *dev_priv = dev->dev_private;
3463
3464         WARN_ON(i915_verify_lists(dev));
3465         BUG_ON(obj->pin_count == 0);
3466         BUG_ON(obj->gtt_space == NULL);
3467
3468         if (--obj->pin_count == 0) {
3469                 if (!obj->active)
3470                         list_move_tail(&obj->mm_list,
3471                                        &dev_priv->mm.inactive_list);
3472                 obj->pin_mappable = false;
3473         }
3474         WARN_ON(i915_verify_lists(dev));
3475 }
3476
3477 int
3478 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3479                    struct drm_file *file)
3480 {
3481         struct drm_i915_gem_pin *args = data;
3482         struct drm_i915_gem_object *obj;
3483         int ret;
3484
3485         ret = i915_mutex_lock_interruptible(dev);
3486         if (ret)
3487                 return ret;
3488
3489         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3490         if (&obj->base == NULL) {
3491                 ret = -ENOENT;
3492                 goto unlock;
3493         }
3494
3495         if (obj->madv != I915_MADV_WILLNEED) {
3496                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3497                 ret = -EINVAL;
3498                 goto out;
3499         }
3500
3501         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3502                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3503                           args->handle);
3504                 ret = -EINVAL;
3505                 goto out;
3506         }
3507
3508         obj->user_pin_count++;
3509         obj->pin_filp = file;
3510         if (obj->user_pin_count == 1) {
3511                 ret = i915_gem_object_pin(obj, args->alignment, true);
3512                 if (ret)
3513                         goto out;
3514         }
3515
3516         /* XXX - flush the CPU caches for pinned objects
3517          * as the X server doesn't manage domains yet
3518          */
3519         i915_gem_object_flush_cpu_write_domain(obj);
3520         args->offset = obj->gtt_offset;
3521 out:
3522         drm_gem_object_unreference(&obj->base);
3523 unlock:
3524         mutex_unlock(&dev->struct_mutex);
3525         return ret;
3526 }
3527
3528 int
3529 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3530                      struct drm_file *file)
3531 {
3532         struct drm_i915_gem_pin *args = data;
3533         struct drm_i915_gem_object *obj;
3534         int ret;
3535
3536         ret = i915_mutex_lock_interruptible(dev);
3537         if (ret)
3538                 return ret;
3539
3540         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3541         if (&obj->base == NULL) {
3542                 ret = -ENOENT;
3543                 goto unlock;
3544         }
3545
3546         if (obj->pin_filp != file) {
3547                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3548                           args->handle);
3549                 ret = -EINVAL;
3550                 goto out;
3551         }
3552         obj->user_pin_count--;
3553         if (obj->user_pin_count == 0) {
3554                 obj->pin_filp = NULL;
3555                 i915_gem_object_unpin(obj);
3556         }
3557
3558 out:
3559         drm_gem_object_unreference(&obj->base);
3560 unlock:
3561         mutex_unlock(&dev->struct_mutex);
3562         return ret;
3563 }
3564
3565 int
3566 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3567                     struct drm_file *file)
3568 {
3569         struct drm_i915_gem_busy *args = data;
3570         struct drm_i915_gem_object *obj;
3571         int ret;
3572
3573         ret = i915_mutex_lock_interruptible(dev);
3574         if (ret)
3575                 return ret;
3576
3577         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3578         if (&obj->base == NULL) {
3579                 ret = -ENOENT;
3580                 goto unlock;
3581         }
3582
3583         /* Count all active objects as busy, even if they are currently not used
3584          * by the gpu. Users of this interface expect objects to eventually
3585          * become non-busy without any further actions, therefore emit any
3586          * necessary flushes here.
3587          */
3588         args->busy = obj->active;
3589         if (args->busy) {
3590                 /* Unconditionally flush objects, even when the gpu still uses this
3591                  * object. Userspace calling this function indicates that it wants to
3592                  * use this buffer rather sooner than later, so issuing the required
3593                  * flush earlier is beneficial.
3594                  */
3595                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3596                         ret = i915_gem_flush_ring(obj->ring,
3597                                                   0, obj->base.write_domain);
3598                 } else if (obj->ring->outstanding_lazy_request ==
3599                            obj->last_rendering_seqno) {
3600                         struct drm_i915_gem_request *request;
3601
3602                         /* This ring is not being cleared by active usage,
3603                          * so emit a request to do so.
3604                          */
3605                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3606                         if (request)
3607                                 ret = i915_add_request(obj->ring, NULL,request);
3608                         else
3609                                 ret = -ENOMEM;
3610                 }
3611
3612                 /* Update the active list for the hardware's current position.
3613                  * Otherwise this only updates on a delayed timer or when irqs
3614                  * are actually unmasked, and our working set ends up being
3615                  * larger than required.
3616                  */
3617                 i915_gem_retire_requests_ring(obj->ring);
3618
3619                 args->busy = obj->active;
3620         }
3621
3622         drm_gem_object_unreference(&obj->base);
3623 unlock:
3624         mutex_unlock(&dev->struct_mutex);
3625         return ret;
3626 }
3627
3628 int
3629 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3630                         struct drm_file *file_priv)
3631 {
3632     return i915_gem_ring_throttle(dev, file_priv);
3633 }
3634
3635 int
3636 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3637                        struct drm_file *file_priv)
3638 {
3639         struct drm_i915_gem_madvise *args = data;
3640         struct drm_i915_gem_object *obj;
3641         int ret;
3642
3643         switch (args->madv) {
3644         case I915_MADV_DONTNEED:
3645         case I915_MADV_WILLNEED:
3646             break;
3647         default:
3648             return -EINVAL;
3649         }
3650
3651         ret = i915_mutex_lock_interruptible(dev);
3652         if (ret)
3653                 return ret;
3654
3655         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3656         if (&obj->base == NULL) {
3657                 ret = -ENOENT;
3658                 goto unlock;
3659         }
3660
3661         if (obj->pin_count) {
3662                 ret = -EINVAL;
3663                 goto out;
3664         }
3665
3666         if (obj->madv != __I915_MADV_PURGED)
3667                 obj->madv = args->madv;
3668
3669         /* if the object is no longer bound, discard its backing storage */
3670         if (i915_gem_object_is_purgeable(obj) &&
3671             obj->gtt_space == NULL)
3672                 i915_gem_object_truncate(obj);
3673
3674         args->retained = obj->madv != __I915_MADV_PURGED;
3675
3676 out:
3677         drm_gem_object_unreference(&obj->base);
3678 unlock:
3679         mutex_unlock(&dev->struct_mutex);
3680         return ret;
3681 }
3682
3683 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3684                                                   size_t size)
3685 {
3686         struct drm_i915_private *dev_priv = dev->dev_private;
3687         struct drm_i915_gem_object *obj;
3688
3689         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3690         if (obj == NULL)
3691                 return NULL;
3692
3693         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3694                 kfree(obj);
3695                 return NULL;
3696         }
3697
3698         i915_gem_info_add_obj(dev_priv, size);
3699
3700         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3701         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3702
3703         if (IS_GEN6(dev)) {
3704                 /* On Gen6, we can have the GPU use the LLC (the CPU
3705                  * cache) for about a 10% performance improvement
3706                  * compared to uncached.  Graphics requests other than
3707                  * display scanout are coherent with the CPU in
3708                  * accessing this cache.  This means in this mode we
3709                  * don't need to clflush on the CPU side, and on the
3710                  * GPU side we only need to flush internal caches to
3711                  * get data visible to the CPU.
3712                  *
3713                  * However, we maintain the display planes as UC, and so
3714                  * need to rebind when first used as such.
3715                  */
3716                 obj->cache_level = I915_CACHE_LLC;
3717         } else
3718                 obj->cache_level = I915_CACHE_NONE;
3719
3720         obj->base.driver_private = NULL;
3721         obj->fence_reg = I915_FENCE_REG_NONE;
3722         INIT_LIST_HEAD(&obj->mm_list);
3723         INIT_LIST_HEAD(&obj->gtt_list);
3724         INIT_LIST_HEAD(&obj->ring_list);
3725         INIT_LIST_HEAD(&obj->exec_list);
3726         INIT_LIST_HEAD(&obj->gpu_write_list);
3727         obj->madv = I915_MADV_WILLNEED;
3728         /* Avoid an unnecessary call to unbind on the first bind. */
3729         obj->map_and_fenceable = true;
3730
3731         return obj;
3732 }
3733
3734 int i915_gem_init_object(struct drm_gem_object *obj)
3735 {
3736         BUG();
3737
3738         return 0;
3739 }
3740
3741 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3742 {
3743         struct drm_device *dev = obj->base.dev;
3744         drm_i915_private_t *dev_priv = dev->dev_private;
3745         int ret;
3746
3747         ret = i915_gem_object_unbind(obj);
3748         if (ret == -ERESTARTSYS) {
3749                 list_move(&obj->mm_list,
3750                           &dev_priv->mm.deferred_free_list);
3751                 return;
3752         }
3753
3754         trace_i915_gem_object_destroy(obj);
3755
3756         if (obj->base.map_list.map)
3757                 i915_gem_free_mmap_offset(obj);
3758
3759         drm_gem_object_release(&obj->base);
3760         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3761
3762         kfree(obj->page_cpu_valid);
3763         kfree(obj->bit_17);
3764         kfree(obj);
3765 }
3766
3767 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3768 {
3769         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3770         struct drm_device *dev = obj->base.dev;
3771
3772         while (obj->pin_count > 0)
3773                 i915_gem_object_unpin(obj);
3774
3775         if (obj->phys_obj)
3776                 i915_gem_detach_phys_object(dev, obj);
3777
3778         i915_gem_free_object_tail(obj);
3779 }
3780
3781 int
3782 i915_gem_idle(struct drm_device *dev)
3783 {
3784         drm_i915_private_t *dev_priv = dev->dev_private;
3785         int ret;
3786
3787         mutex_lock(&dev->struct_mutex);
3788
3789         if (dev_priv->mm.suspended) {
3790                 mutex_unlock(&dev->struct_mutex);
3791                 return 0;
3792         }
3793
3794         ret = i915_gpu_idle(dev);
3795         if (ret) {
3796                 mutex_unlock(&dev->struct_mutex);
3797                 return ret;
3798         }
3799
3800         /* Under UMS, be paranoid and evict. */
3801         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3802                 ret = i915_gem_evict_inactive(dev, false);
3803                 if (ret) {
3804                         mutex_unlock(&dev->struct_mutex);
3805                         return ret;
3806                 }
3807         }
3808
3809         i915_gem_reset_fences(dev);
3810
3811         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3812          * We need to replace this with a semaphore, or something.
3813          * And not confound mm.suspended!
3814          */
3815         dev_priv->mm.suspended = 1;
3816         del_timer_sync(&dev_priv->hangcheck_timer);
3817
3818         i915_kernel_lost_context(dev);
3819         i915_gem_cleanup_ringbuffer(dev);
3820
3821         mutex_unlock(&dev->struct_mutex);
3822
3823         /* Cancel the retire work handler, which should be idle now. */
3824         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3825
3826         return 0;
3827 }
3828
3829 int
3830 i915_gem_init_ringbuffer(struct drm_device *dev)
3831 {
3832         drm_i915_private_t *dev_priv = dev->dev_private;
3833         int ret;
3834
3835         ret = intel_init_render_ring_buffer(dev);
3836         if (ret)
3837                 return ret;
3838
3839         if (HAS_BSD(dev)) {
3840                 ret = intel_init_bsd_ring_buffer(dev);
3841                 if (ret)
3842                         goto cleanup_render_ring;
3843         }
3844
3845         if (HAS_BLT(dev)) {
3846                 ret = intel_init_blt_ring_buffer(dev);
3847                 if (ret)
3848                         goto cleanup_bsd_ring;
3849         }
3850
3851         dev_priv->next_seqno = 1;
3852
3853         return 0;
3854
3855 cleanup_bsd_ring:
3856         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3857 cleanup_render_ring:
3858         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3859         return ret;
3860 }
3861
3862 void
3863 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3864 {
3865         drm_i915_private_t *dev_priv = dev->dev_private;
3866         int i;
3867
3868         for (i = 0; i < I915_NUM_RINGS; i++)
3869                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3870 }
3871
3872 int
3873 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3874                        struct drm_file *file_priv)
3875 {
3876         drm_i915_private_t *dev_priv = dev->dev_private;
3877         int ret, i;
3878
3879         if (drm_core_check_feature(dev, DRIVER_MODESET))
3880                 return 0;
3881
3882         if (atomic_read(&dev_priv->mm.wedged)) {
3883                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3884                 atomic_set(&dev_priv->mm.wedged, 0);
3885         }
3886
3887         mutex_lock(&dev->struct_mutex);
3888         dev_priv->mm.suspended = 0;
3889
3890         ret = i915_gem_init_ringbuffer(dev);
3891         if (ret != 0) {
3892                 mutex_unlock(&dev->struct_mutex);
3893                 return ret;
3894         }
3895
3896         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3897         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3898         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3899         for (i = 0; i < I915_NUM_RINGS; i++) {
3900                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3901                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3902         }
3903         mutex_unlock(&dev->struct_mutex);
3904
3905         ret = drm_irq_install(dev);
3906         if (ret)
3907                 goto cleanup_ringbuffer;
3908
3909         return 0;
3910
3911 cleanup_ringbuffer:
3912         mutex_lock(&dev->struct_mutex);
3913         i915_gem_cleanup_ringbuffer(dev);
3914         dev_priv->mm.suspended = 1;
3915         mutex_unlock(&dev->struct_mutex);
3916
3917         return ret;
3918 }
3919
3920 int
3921 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3922                        struct drm_file *file_priv)
3923 {
3924         if (drm_core_check_feature(dev, DRIVER_MODESET))
3925                 return 0;
3926
3927         drm_irq_uninstall(dev);
3928         return i915_gem_idle(dev);
3929 }
3930
3931 void
3932 i915_gem_lastclose(struct drm_device *dev)
3933 {
3934         int ret;
3935
3936         if (drm_core_check_feature(dev, DRIVER_MODESET))
3937                 return;
3938
3939         ret = i915_gem_idle(dev);
3940         if (ret)
3941                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3942 }
3943
3944 static void
3945 init_ring_lists(struct intel_ring_buffer *ring)
3946 {
3947         INIT_LIST_HEAD(&ring->active_list);
3948         INIT_LIST_HEAD(&ring->request_list);
3949         INIT_LIST_HEAD(&ring->gpu_write_list);
3950 }
3951
3952 void
3953 i915_gem_load(struct drm_device *dev)
3954 {
3955         int i;
3956         drm_i915_private_t *dev_priv = dev->dev_private;
3957
3958         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3959         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3960         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3961         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3962         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3963         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3964         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3965         for (i = 0; i < I915_NUM_RINGS; i++)
3966                 init_ring_lists(&dev_priv->ring[i]);
3967         for (i = 0; i < 16; i++)
3968                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3969         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3970                           i915_gem_retire_work_handler);
3971         init_completion(&dev_priv->error_completion);
3972
3973         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3974         if (IS_GEN3(dev)) {
3975                 u32 tmp = I915_READ(MI_ARB_STATE);
3976                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3977                         /* arb state is a masked write, so set bit + bit in mask */
3978                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3979                         I915_WRITE(MI_ARB_STATE, tmp);
3980                 }
3981         }
3982
3983         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3984
3985         /* Old X drivers will take 0-2 for front, back, depth buffers */
3986         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3987                 dev_priv->fence_reg_start = 3;
3988
3989         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3990                 dev_priv->num_fence_regs = 16;
3991         else
3992                 dev_priv->num_fence_regs = 8;
3993
3994         /* Initialize fence registers to zero */
3995         for (i = 0; i < dev_priv->num_fence_regs; i++) {
3996                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3997         }
3998
3999         i915_gem_detect_bit_6_swizzle(dev);
4000         init_waitqueue_head(&dev_priv->pending_flip_queue);
4001
4002         dev_priv->mm.interruptible = true;
4003
4004         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4005         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4006         register_shrinker(&dev_priv->mm.inactive_shrinker);
4007 }
4008
4009 /*
4010  * Create a physically contiguous memory object for this object
4011  * e.g. for cursor + overlay regs
4012  */
4013 static int i915_gem_init_phys_object(struct drm_device *dev,
4014                                      int id, int size, int align)
4015 {
4016         drm_i915_private_t *dev_priv = dev->dev_private;
4017         struct drm_i915_gem_phys_object *phys_obj;
4018         int ret;
4019
4020         if (dev_priv->mm.phys_objs[id - 1] || !size)
4021                 return 0;
4022
4023         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4024         if (!phys_obj)
4025                 return -ENOMEM;
4026
4027         phys_obj->id = id;
4028
4029         phys_obj->handle = drm_pci_alloc(dev, size, align);
4030         if (!phys_obj->handle) {
4031                 ret = -ENOMEM;
4032                 goto kfree_obj;
4033         }
4034 #ifdef CONFIG_X86
4035         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4036 #endif
4037
4038         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4039
4040         return 0;
4041 kfree_obj:
4042         kfree(phys_obj);
4043         return ret;
4044 }
4045
4046 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4047 {
4048         drm_i915_private_t *dev_priv = dev->dev_private;
4049         struct drm_i915_gem_phys_object *phys_obj;
4050
4051         if (!dev_priv->mm.phys_objs[id - 1])
4052                 return;
4053
4054         phys_obj = dev_priv->mm.phys_objs[id - 1];
4055         if (phys_obj->cur_obj) {
4056                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4057         }
4058
4059 #ifdef CONFIG_X86
4060         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4061 #endif
4062         drm_pci_free(dev, phys_obj->handle);
4063         kfree(phys_obj);
4064         dev_priv->mm.phys_objs[id - 1] = NULL;
4065 }
4066
4067 void i915_gem_free_all_phys_object(struct drm_device *dev)
4068 {
4069         int i;
4070
4071         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4072                 i915_gem_free_phys_object(dev, i);
4073 }
4074
4075 void i915_gem_detach_phys_object(struct drm_device *dev,
4076                                  struct drm_i915_gem_object *obj)
4077 {
4078         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4079         char *vaddr;
4080         int i;
4081         int page_count;
4082
4083         if (!obj->phys_obj)
4084                 return;
4085         vaddr = obj->phys_obj->handle->vaddr;
4086
4087         page_count = obj->base.size / PAGE_SIZE;
4088         for (i = 0; i < page_count; i++) {
4089                 struct page *page = read_cache_page_gfp(mapping, i,
4090                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
4091                 if (!IS_ERR(page)) {
4092                         char *dst = kmap_atomic(page);
4093                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4094                         kunmap_atomic(dst);
4095
4096                         drm_clflush_pages(&page, 1);
4097
4098                         set_page_dirty(page);
4099                         mark_page_accessed(page);
4100                         page_cache_release(page);
4101                 }
4102         }
4103         intel_gtt_chipset_flush();
4104
4105         obj->phys_obj->cur_obj = NULL;
4106         obj->phys_obj = NULL;
4107 }
4108
4109 int
4110 i915_gem_attach_phys_object(struct drm_device *dev,
4111                             struct drm_i915_gem_object *obj,
4112                             int id,
4113                             int align)
4114 {
4115         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4116         drm_i915_private_t *dev_priv = dev->dev_private;
4117         int ret = 0;
4118         int page_count;
4119         int i;
4120
4121         if (id > I915_MAX_PHYS_OBJECT)
4122                 return -EINVAL;
4123
4124         if (obj->phys_obj) {
4125                 if (obj->phys_obj->id == id)
4126                         return 0;
4127                 i915_gem_detach_phys_object(dev, obj);
4128         }
4129
4130         /* create a new object */
4131         if (!dev_priv->mm.phys_objs[id - 1]) {
4132                 ret = i915_gem_init_phys_object(dev, id,
4133                                                 obj->base.size, align);
4134                 if (ret) {
4135                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4136                                   id, obj->base.size);
4137                         return ret;
4138                 }
4139         }
4140
4141         /* bind to the object */
4142         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4143         obj->phys_obj->cur_obj = obj;
4144
4145         page_count = obj->base.size / PAGE_SIZE;
4146
4147         for (i = 0; i < page_count; i++) {
4148                 struct page *page;
4149                 char *dst, *src;
4150
4151                 page = read_cache_page_gfp(mapping, i,
4152                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
4153                 if (IS_ERR(page))
4154                         return PTR_ERR(page);
4155
4156                 src = kmap_atomic(page);
4157                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4158                 memcpy(dst, src, PAGE_SIZE);
4159                 kunmap_atomic(src);
4160
4161                 mark_page_accessed(page);
4162                 page_cache_release(page);
4163         }
4164
4165         return 0;
4166 }
4167
4168 static int
4169 i915_gem_phys_pwrite(struct drm_device *dev,
4170                      struct drm_i915_gem_object *obj,
4171                      struct drm_i915_gem_pwrite *args,
4172                      struct drm_file *file_priv)
4173 {
4174         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4175         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4176
4177         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4178                 unsigned long unwritten;
4179
4180                 /* The physical object once assigned is fixed for the lifetime
4181                  * of the obj, so we can safely drop the lock and continue
4182                  * to access vaddr.
4183                  */
4184                 mutex_unlock(&dev->struct_mutex);
4185                 unwritten = copy_from_user(vaddr, user_data, args->size);
4186                 mutex_lock(&dev->struct_mutex);
4187                 if (unwritten)
4188                         return -EFAULT;
4189         }
4190
4191         intel_gtt_chipset_flush();
4192         return 0;
4193 }
4194
4195 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4196 {
4197         struct drm_i915_file_private *file_priv = file->driver_priv;
4198
4199         /* Clean up our request list when the client is going away, so that
4200          * later retire_requests won't dereference our soon-to-be-gone
4201          * file_priv.
4202          */
4203         spin_lock(&file_priv->mm.lock);
4204         while (!list_empty(&file_priv->mm.request_list)) {
4205                 struct drm_i915_gem_request *request;
4206
4207                 request = list_first_entry(&file_priv->mm.request_list,
4208                                            struct drm_i915_gem_request,
4209                                            client_list);
4210                 list_del(&request->client_list);
4211                 request->file_priv = NULL;
4212         }
4213         spin_unlock(&file_priv->mm.lock);
4214 }
4215
4216 static int
4217 i915_gpu_is_active(struct drm_device *dev)
4218 {
4219         drm_i915_private_t *dev_priv = dev->dev_private;
4220         int lists_empty;
4221
4222         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4223                       list_empty(&dev_priv->mm.active_list);
4224
4225         return !lists_empty;
4226 }
4227
4228 static int
4229 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4230 {
4231         struct drm_i915_private *dev_priv =
4232                 container_of(shrinker,
4233                              struct drm_i915_private,
4234                              mm.inactive_shrinker);
4235         struct drm_device *dev = dev_priv->dev;
4236         struct drm_i915_gem_object *obj, *next;
4237         int nr_to_scan = sc->nr_to_scan;
4238         int cnt;
4239
4240         if (!mutex_trylock(&dev->struct_mutex))
4241                 return 0;
4242
4243         /* "fast-path" to count number of available objects */
4244         if (nr_to_scan == 0) {
4245                 cnt = 0;
4246                 list_for_each_entry(obj,
4247                                     &dev_priv->mm.inactive_list,
4248                                     mm_list)
4249                         cnt++;
4250                 mutex_unlock(&dev->struct_mutex);
4251                 return cnt / 100 * sysctl_vfs_cache_pressure;
4252         }
4253
4254 rescan:
4255         /* first scan for clean buffers */
4256         i915_gem_retire_requests(dev);
4257
4258         list_for_each_entry_safe(obj, next,
4259                                  &dev_priv->mm.inactive_list,
4260                                  mm_list) {
4261                 if (i915_gem_object_is_purgeable(obj)) {
4262                         if (i915_gem_object_unbind(obj) == 0 &&
4263                             --nr_to_scan == 0)
4264                                 break;
4265                 }
4266         }
4267
4268         /* second pass, evict/count anything still on the inactive list */
4269         cnt = 0;
4270         list_for_each_entry_safe(obj, next,
4271                                  &dev_priv->mm.inactive_list,
4272                                  mm_list) {
4273                 if (nr_to_scan &&
4274                     i915_gem_object_unbind(obj) == 0)
4275                         nr_to_scan--;
4276                 else
4277                         cnt++;
4278         }
4279
4280         if (nr_to_scan && i915_gpu_is_active(dev)) {
4281                 /*
4282                  * We are desperate for pages, so as a last resort, wait
4283                  * for the GPU to finish and discard whatever we can.
4284                  * This has a dramatic impact to reduce the number of
4285                  * OOM-killer events whilst running the GPU aggressively.
4286                  */
4287                 if (i915_gpu_idle(dev) == 0)
4288                         goto rescan;
4289         }
4290         mutex_unlock(&dev->struct_mutex);
4291         return cnt / 100 * sysctl_vfs_cache_pressure;
4292 }