2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/reservation.h>
38 #include <linux/shmem_fs.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/pci.h>
42 #include <linux/dma-buf.h>
44 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
45 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
46 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
48 static bool cpu_cache_is_coherent(struct drm_device *dev,
49 enum i915_cache_level level)
51 return HAS_LLC(dev) || level != I915_CACHE_NONE;
54 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
56 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
59 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
62 return obj->pin_display;
66 insert_mappable_node(struct i915_ggtt *ggtt,
67 struct drm_mm_node *node, u32 size)
69 memset(node, 0, sizeof(*node));
70 return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node,
72 0, ggtt->mappable_end,
73 DRM_MM_SEARCH_DEFAULT,
74 DRM_MM_CREATE_DEFAULT);
78 remove_mappable_node(struct drm_mm_node *node)
80 drm_mm_remove_node(node);
83 /* some bookkeeping */
84 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
87 spin_lock(&dev_priv->mm.object_stat_lock);
88 dev_priv->mm.object_count++;
89 dev_priv->mm.object_memory += size;
90 spin_unlock(&dev_priv->mm.object_stat_lock);
93 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count--;
98 dev_priv->mm.object_memory -= size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
103 i915_gem_wait_for_error(struct i915_gpu_error *error)
109 if (!i915_reset_in_progress(error))
113 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
114 * userspace. If it takes that long something really bad is going on and
115 * we should simply try to bail out and fail as gracefully as possible.
117 ret = wait_event_interruptible_timeout(error->reset_queue,
118 !i915_reset_in_progress(error),
121 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
123 } else if (ret < 0) {
130 int i915_mutex_lock_interruptible(struct drm_device *dev)
132 struct drm_i915_private *dev_priv = to_i915(dev);
135 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
139 ret = mutex_lock_interruptible(&dev->struct_mutex);
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = to_i915(dev);
151 struct i915_ggtt *ggtt = &dev_priv->ggtt;
152 struct drm_i915_gem_get_aperture *args = data;
153 struct i915_vma *vma;
157 mutex_lock(&dev->struct_mutex);
158 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
159 if (i915_vma_is_pinned(vma))
160 pinned += vma->node.size;
161 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
162 if (i915_vma_is_pinned(vma))
163 pinned += vma->node.size;
164 mutex_unlock(&dev->struct_mutex);
166 args->aper_size = ggtt->base.total;
167 args->aper_available_size = args->aper_size - pinned;
172 static struct sg_table *
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
175 struct address_space *mapping = obj->base.filp->f_mapping;
176 char *vaddr = obj->phys_handle->vaddr;
178 struct scatterlist *sg;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
182 return ERR_PTR(-EINVAL);
184 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
188 page = shmem_read_mapping_page(mapping, i);
190 return ERR_CAST(page);
192 src = kmap_atomic(page);
193 memcpy(vaddr, src, PAGE_SIZE);
194 drm_clflush_virt_range(vaddr, PAGE_SIZE);
201 i915_gem_chipset_flush(to_i915(obj->base.dev));
203 st = kmalloc(sizeof(*st), GFP_KERNEL);
205 return ERR_PTR(-ENOMEM);
207 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
209 return ERR_PTR(-ENOMEM);
214 sg->length = obj->base.size;
216 sg_dma_address(sg) = obj->phys_handle->busaddr;
217 sg_dma_len(sg) = obj->base.size;
223 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj)
225 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
227 if (obj->mm.madv == I915_MADV_DONTNEED)
228 obj->mm.dirty = false;
230 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
231 i915_gem_clflush_object(obj, false);
233 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
234 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
238 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
239 struct sg_table *pages)
241 __i915_gem_object_release_shmem(obj);
244 struct address_space *mapping = obj->base.filp->f_mapping;
245 char *vaddr = obj->phys_handle->vaddr;
248 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
252 page = shmem_read_mapping_page(mapping, i);
256 dst = kmap_atomic(page);
257 drm_clflush_virt_range(vaddr, PAGE_SIZE);
258 memcpy(dst, vaddr, PAGE_SIZE);
261 set_page_dirty(page);
262 if (obj->mm.madv == I915_MADV_WILLNEED)
263 mark_page_accessed(page);
267 obj->mm.dirty = false;
270 sg_free_table(pages);
275 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
277 drm_pci_free(obj->base.dev, obj->phys_handle);
278 i915_gem_object_unpin_pages(obj);
281 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
282 .get_pages = i915_gem_object_get_pages_phys,
283 .put_pages = i915_gem_object_put_pages_phys,
284 .release = i915_gem_object_release_phys,
287 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
289 struct i915_vma *vma;
290 LIST_HEAD(still_in_list);
293 lockdep_assert_held(&obj->base.dev->struct_mutex);
295 /* Closed vma are removed from the obj->vma_list - but they may
296 * still have an active binding on the object. To remove those we
297 * must wait for all rendering to complete to the object (as unbinding
298 * must anyway), and retire the requests.
300 ret = i915_gem_object_wait(obj,
301 I915_WAIT_INTERRUPTIBLE |
304 MAX_SCHEDULE_TIMEOUT,
309 i915_gem_retire_requests(to_i915(obj->base.dev));
311 while ((vma = list_first_entry_or_null(&obj->vma_list,
314 list_move_tail(&vma->obj_link, &still_in_list);
315 ret = i915_vma_unbind(vma);
319 list_splice(&still_in_list, &obj->vma_list);
325 i915_gem_object_wait_fence(struct dma_fence *fence,
328 struct intel_rps_client *rps)
330 struct drm_i915_gem_request *rq;
332 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
334 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
337 if (!dma_fence_is_i915(fence))
338 return dma_fence_wait_timeout(fence,
339 flags & I915_WAIT_INTERRUPTIBLE,
342 rq = to_request(fence);
343 if (i915_gem_request_completed(rq))
346 /* This client is about to stall waiting for the GPU. In many cases
347 * this is undesirable and limits the throughput of the system, as
348 * many clients cannot continue processing user input/output whilst
349 * blocked. RPS autotuning may take tens of milliseconds to respond
350 * to the GPU load and thus incurs additional latency for the client.
351 * We can circumvent that by promoting the GPU frequency to maximum
352 * before we wait. This makes the GPU throttle up much more quickly
353 * (good for benchmarks and user experience, e.g. window animations),
354 * but at a cost of spending more power processing the workload
355 * (bad for battery). Not all clients even want their results
356 * immediately and for them we should just let the GPU select its own
357 * frequency to maximise efficiency. To prevent a single client from
358 * forcing the clocks too high for the whole system, we only allow
359 * each client to waitboost once in a busy period.
362 if (INTEL_GEN(rq->i915) >= 6)
363 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
368 timeout = i915_wait_request(rq, flags, timeout);
371 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
372 i915_gem_request_retire_upto(rq);
374 if (rps && rq->fence.seqno == rq->timeline->last_submitted_seqno) {
375 /* The GPU is now idle and this client has stalled.
376 * Since no other client has submitted a request in the
377 * meantime, assume that this client is the only one
378 * supplying work to the GPU but is unable to keep that
379 * work supplied because it is waiting. Since the GPU is
380 * then never kept fully busy, RPS autoclocking will
381 * keep the clocks relatively low, causing further delays.
382 * Compensate by giving the synchronous client credit for
383 * a waitboost next time.
385 spin_lock(&rq->i915->rps.client_lock);
386 list_del_init(&rps->link);
387 spin_unlock(&rq->i915->rps.client_lock);
394 i915_gem_object_wait_reservation(struct reservation_object *resv,
397 struct intel_rps_client *rps)
399 struct dma_fence *excl;
401 if (flags & I915_WAIT_ALL) {
402 struct dma_fence **shared;
403 unsigned int count, i;
406 ret = reservation_object_get_fences_rcu(resv,
407 &excl, &count, &shared);
411 for (i = 0; i < count; i++) {
412 timeout = i915_gem_object_wait_fence(shared[i],
418 dma_fence_put(shared[i]);
421 for (; i < count; i++)
422 dma_fence_put(shared[i]);
425 excl = reservation_object_get_excl_rcu(resv);
428 if (excl && timeout > 0)
429 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
437 * Waits for rendering to the object to be completed
438 * @obj: i915 gem object
439 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
440 * @timeout: how long to wait
441 * @rps: client (user process) to charge for any waitboosting
444 i915_gem_object_wait(struct drm_i915_gem_object *obj,
447 struct intel_rps_client *rps)
450 #if IS_ENABLED(CONFIG_LOCKDEP)
451 GEM_BUG_ON(debug_locks &&
452 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
453 !!(flags & I915_WAIT_LOCKED));
455 GEM_BUG_ON(timeout < 0);
457 timeout = i915_gem_object_wait_reservation(obj->resv,
460 return timeout < 0 ? timeout : 0;
463 static struct intel_rps_client *to_rps_client(struct drm_file *file)
465 struct drm_i915_file_private *fpriv = file->driver_priv;
471 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
474 drm_dma_handle_t *phys;
477 if (obj->phys_handle) {
478 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
484 if (obj->mm.madv != I915_MADV_WILLNEED)
487 if (obj->base.filp == NULL)
490 ret = i915_gem_object_unbind(obj);
494 __i915_gem_object_put_pages(obj);
498 /* create a new object */
499 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
503 obj->phys_handle = phys;
504 obj->ops = &i915_gem_phys_ops;
506 return i915_gem_object_pin_pages(obj);
510 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
511 struct drm_i915_gem_pwrite *args,
512 struct drm_file *file)
514 struct drm_device *dev = obj->base.dev;
515 void *vaddr = obj->phys_handle->vaddr + args->offset;
516 char __user *user_data = u64_to_user_ptr(args->data_ptr);
519 /* We manually control the domain here and pretend that it
520 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
522 lockdep_assert_held(&obj->base.dev->struct_mutex);
523 ret = i915_gem_object_wait(obj,
524 I915_WAIT_INTERRUPTIBLE |
527 MAX_SCHEDULE_TIMEOUT,
528 to_rps_client(file));
532 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
533 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
534 unsigned long unwritten;
536 /* The physical object once assigned is fixed for the lifetime
537 * of the obj, so we can safely drop the lock and continue
540 mutex_unlock(&dev->struct_mutex);
541 unwritten = copy_from_user(vaddr, user_data, args->size);
542 mutex_lock(&dev->struct_mutex);
549 drm_clflush_virt_range(vaddr, args->size);
550 i915_gem_chipset_flush(to_i915(dev));
553 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
557 void *i915_gem_object_alloc(struct drm_device *dev)
559 struct drm_i915_private *dev_priv = to_i915(dev);
560 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
563 void i915_gem_object_free(struct drm_i915_gem_object *obj)
565 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
566 kmem_cache_free(dev_priv->objects, obj);
570 i915_gem_create(struct drm_file *file,
571 struct drm_device *dev,
575 struct drm_i915_gem_object *obj;
579 size = roundup(size, PAGE_SIZE);
583 /* Allocate the new object */
584 obj = i915_gem_object_create(dev, size);
588 ret = drm_gem_handle_create(file, &obj->base, &handle);
589 /* drop reference from allocate - handle holds it now */
590 i915_gem_object_put(obj);
599 i915_gem_dumb_create(struct drm_file *file,
600 struct drm_device *dev,
601 struct drm_mode_create_dumb *args)
603 /* have to work out size/pitch and return them */
604 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
605 args->size = args->pitch * args->height;
606 return i915_gem_create(file, dev,
607 args->size, &args->handle);
611 * Creates a new mm object and returns a handle to it.
612 * @dev: drm device pointer
613 * @data: ioctl data blob
614 * @file: drm file pointer
617 i915_gem_create_ioctl(struct drm_device *dev, void *data,
618 struct drm_file *file)
620 struct drm_i915_gem_create *args = data;
622 i915_gem_flush_free_objects(to_i915(dev));
624 return i915_gem_create(file, dev,
625 args->size, &args->handle);
629 __copy_to_user_swizzled(char __user *cpu_vaddr,
630 const char *gpu_vaddr, int gpu_offset,
633 int ret, cpu_offset = 0;
636 int cacheline_end = ALIGN(gpu_offset + 1, 64);
637 int this_length = min(cacheline_end - gpu_offset, length);
638 int swizzled_gpu_offset = gpu_offset ^ 64;
640 ret = __copy_to_user(cpu_vaddr + cpu_offset,
641 gpu_vaddr + swizzled_gpu_offset,
646 cpu_offset += this_length;
647 gpu_offset += this_length;
648 length -= this_length;
655 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
656 const char __user *cpu_vaddr,
659 int ret, cpu_offset = 0;
662 int cacheline_end = ALIGN(gpu_offset + 1, 64);
663 int this_length = min(cacheline_end - gpu_offset, length);
664 int swizzled_gpu_offset = gpu_offset ^ 64;
666 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
667 cpu_vaddr + cpu_offset,
672 cpu_offset += this_length;
673 gpu_offset += this_length;
674 length -= this_length;
681 * Pins the specified object's pages and synchronizes the object with
682 * GPU accesses. Sets needs_clflush to non-zero if the caller should
683 * flush the object from the CPU cache.
685 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
686 unsigned int *needs_clflush)
690 lockdep_assert_held(&obj->base.dev->struct_mutex);
693 if (!i915_gem_object_has_struct_page(obj))
696 ret = i915_gem_object_wait(obj,
697 I915_WAIT_INTERRUPTIBLE |
699 MAX_SCHEDULE_TIMEOUT,
704 ret = i915_gem_object_pin_pages(obj);
708 i915_gem_object_flush_gtt_write_domain(obj);
710 /* If we're not in the cpu read domain, set ourself into the gtt
711 * read domain and manually flush cachelines (if required). This
712 * optimizes for the case when the gpu will dirty the data
713 * anyway again before the next pread happens.
715 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
716 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
719 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
720 ret = i915_gem_object_set_to_cpu_domain(obj, false);
727 /* return with the pages pinned */
731 i915_gem_object_unpin_pages(obj);
735 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
736 unsigned int *needs_clflush)
740 lockdep_assert_held(&obj->base.dev->struct_mutex);
743 if (!i915_gem_object_has_struct_page(obj))
746 ret = i915_gem_object_wait(obj,
747 I915_WAIT_INTERRUPTIBLE |
750 MAX_SCHEDULE_TIMEOUT,
755 ret = i915_gem_object_pin_pages(obj);
759 i915_gem_object_flush_gtt_write_domain(obj);
761 /* If we're not in the cpu write domain, set ourself into the
762 * gtt write domain and manually flush cachelines (as required).
763 * This optimizes for the case when the gpu will use the data
764 * right away and we therefore have to clflush anyway.
766 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
767 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
769 /* Same trick applies to invalidate partially written cachelines read
772 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
773 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
776 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
777 ret = i915_gem_object_set_to_cpu_domain(obj, true);
784 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
785 obj->cache_dirty = true;
787 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
788 obj->mm.dirty = true;
789 /* return with the pages pinned */
793 i915_gem_object_unpin_pages(obj);
798 shmem_clflush_swizzled_range(char *addr, unsigned long length,
801 if (unlikely(swizzled)) {
802 unsigned long start = (unsigned long) addr;
803 unsigned long end = (unsigned long) addr + length;
805 /* For swizzling simply ensure that we always flush both
806 * channels. Lame, but simple and it works. Swizzled
807 * pwrite/pread is far from a hotpath - current userspace
808 * doesn't use it at all. */
809 start = round_down(start, 128);
810 end = round_up(end, 128);
812 drm_clflush_virt_range((void *)start, end - start);
814 drm_clflush_virt_range(addr, length);
819 /* Only difference to the fast-path function is that this can handle bit17
820 * and uses non-atomic copy and kmap functions. */
822 shmem_pread_slow(struct page *page, int offset, int length,
823 char __user *user_data,
824 bool page_do_bit17_swizzling, bool needs_clflush)
831 shmem_clflush_swizzled_range(vaddr + offset, length,
832 page_do_bit17_swizzling);
834 if (page_do_bit17_swizzling)
835 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
837 ret = __copy_to_user(user_data, vaddr + offset, length);
840 return ret ? - EFAULT : 0;
844 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
845 bool page_do_bit17_swizzling, bool needs_clflush)
850 if (!page_do_bit17_swizzling) {
851 char *vaddr = kmap_atomic(page);
854 drm_clflush_virt_range(vaddr + offset, length);
855 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
856 kunmap_atomic(vaddr);
861 return shmem_pread_slow(page, offset, length, user_data,
862 page_do_bit17_swizzling, needs_clflush);
866 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
867 struct drm_i915_gem_pread *args)
869 char __user *user_data;
871 unsigned int obj_do_bit17_swizzling;
872 unsigned int needs_clflush;
873 unsigned int idx, offset;
876 obj_do_bit17_swizzling = 0;
877 if (i915_gem_object_needs_bit17_swizzle(obj))
878 obj_do_bit17_swizzling = BIT(17);
880 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
884 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
885 mutex_unlock(&obj->base.dev->struct_mutex);
890 user_data = u64_to_user_ptr(args->data_ptr);
891 offset = offset_in_page(args->offset);
892 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
893 struct page *page = i915_gem_object_get_page(obj, idx);
897 if (offset + length > PAGE_SIZE)
898 length = PAGE_SIZE - offset;
900 ret = shmem_pread(page, offset, length, user_data,
901 page_to_phys(page) & obj_do_bit17_swizzling,
911 i915_gem_obj_finish_shmem_access(obj);
916 gtt_user_read(struct io_mapping *mapping,
917 loff_t base, int offset,
918 char __user *user_data, int length)
921 unsigned long unwritten;
923 /* We can use the cpu mem copy function because this is X86. */
924 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
925 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
926 io_mapping_unmap_atomic(vaddr);
928 vaddr = (void __force *)
929 io_mapping_map_wc(mapping, base, PAGE_SIZE);
930 unwritten = copy_to_user(user_data, vaddr + offset, length);
931 io_mapping_unmap(vaddr);
937 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
938 const struct drm_i915_gem_pread *args)
940 struct drm_i915_private *i915 = to_i915(obj->base.dev);
941 struct i915_ggtt *ggtt = &i915->ggtt;
942 struct drm_mm_node node;
943 struct i915_vma *vma;
944 void __user *user_data;
948 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
952 intel_runtime_pm_get(i915);
953 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
954 PIN_MAPPABLE | PIN_NONBLOCK);
956 node.start = i915_ggtt_offset(vma);
957 node.allocated = false;
958 ret = i915_vma_put_fence(vma);
965 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
968 GEM_BUG_ON(!node.allocated);
971 ret = i915_gem_object_set_to_gtt_domain(obj, false);
975 mutex_unlock(&i915->drm.struct_mutex);
977 user_data = u64_to_user_ptr(args->data_ptr);
979 offset = args->offset;
982 /* Operation in this page
984 * page_base = page offset within aperture
985 * page_offset = offset within page
986 * page_length = bytes to copy for this page
988 u32 page_base = node.start;
989 unsigned page_offset = offset_in_page(offset);
990 unsigned page_length = PAGE_SIZE - page_offset;
991 page_length = remain < page_length ? remain : page_length;
992 if (node.allocated) {
994 ggtt->base.insert_page(&ggtt->base,
995 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
996 node.start, I915_CACHE_NONE, 0);
999 page_base += offset & PAGE_MASK;
1002 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1003 user_data, page_length)) {
1008 remain -= page_length;
1009 user_data += page_length;
1010 offset += page_length;
1013 mutex_lock(&i915->drm.struct_mutex);
1015 if (node.allocated) {
1017 ggtt->base.clear_range(&ggtt->base,
1018 node.start, node.size);
1019 remove_mappable_node(&node);
1021 i915_vma_unpin(vma);
1024 intel_runtime_pm_put(i915);
1025 mutex_unlock(&i915->drm.struct_mutex);
1031 * Reads data from the object referenced by handle.
1032 * @dev: drm device pointer
1033 * @data: ioctl data blob
1034 * @file: drm file pointer
1036 * On error, the contents of *data are undefined.
1039 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1040 struct drm_file *file)
1042 struct drm_i915_gem_pread *args = data;
1043 struct drm_i915_gem_object *obj;
1046 if (args->size == 0)
1049 if (!access_ok(VERIFY_WRITE,
1050 u64_to_user_ptr(args->data_ptr),
1054 obj = i915_gem_object_lookup(file, args->handle);
1058 /* Bounds check source. */
1059 if (args->offset > obj->base.size ||
1060 args->size > obj->base.size - args->offset) {
1065 trace_i915_gem_object_pread(obj, args->offset, args->size);
1067 ret = i915_gem_object_wait(obj,
1068 I915_WAIT_INTERRUPTIBLE,
1069 MAX_SCHEDULE_TIMEOUT,
1070 to_rps_client(file));
1074 ret = i915_gem_object_pin_pages(obj);
1078 ret = i915_gem_shmem_pread(obj, args);
1079 if (ret == -EFAULT || ret == -ENODEV)
1080 ret = i915_gem_gtt_pread(obj, args);
1082 i915_gem_object_unpin_pages(obj);
1084 i915_gem_object_put(obj);
1088 /* This is the fast write path which cannot handle
1089 * page faults in the source data
1093 ggtt_write(struct io_mapping *mapping,
1094 loff_t base, int offset,
1095 char __user *user_data, int length)
1098 unsigned long unwritten;
1100 /* We can use the cpu mem copy function because this is X86. */
1101 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1102 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1104 io_mapping_unmap_atomic(vaddr);
1106 vaddr = (void __force *)
1107 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1108 unwritten = copy_from_user(vaddr + offset, user_data, length);
1109 io_mapping_unmap(vaddr);
1116 * This is the fast pwrite path, where we copy the data directly from the
1117 * user into the GTT, uncached.
1118 * @obj: i915 GEM object
1119 * @args: pwrite arguments structure
1122 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1123 const struct drm_i915_gem_pwrite *args)
1125 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1126 struct i915_ggtt *ggtt = &i915->ggtt;
1127 struct drm_mm_node node;
1128 struct i915_vma *vma;
1130 void __user *user_data;
1133 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1137 intel_runtime_pm_get(i915);
1138 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1139 PIN_MAPPABLE | PIN_NONBLOCK);
1141 node.start = i915_ggtt_offset(vma);
1142 node.allocated = false;
1143 ret = i915_vma_put_fence(vma);
1145 i915_vma_unpin(vma);
1150 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1153 GEM_BUG_ON(!node.allocated);
1156 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1160 mutex_unlock(&i915->drm.struct_mutex);
1162 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1164 user_data = u64_to_user_ptr(args->data_ptr);
1165 offset = args->offset;
1166 remain = args->size;
1168 /* Operation in this page
1170 * page_base = page offset within aperture
1171 * page_offset = offset within page
1172 * page_length = bytes to copy for this page
1174 u32 page_base = node.start;
1175 unsigned int page_offset = offset_in_page(offset);
1176 unsigned int page_length = PAGE_SIZE - page_offset;
1177 page_length = remain < page_length ? remain : page_length;
1178 if (node.allocated) {
1179 wmb(); /* flush the write before we modify the GGTT */
1180 ggtt->base.insert_page(&ggtt->base,
1181 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1182 node.start, I915_CACHE_NONE, 0);
1183 wmb(); /* flush modifications to the GGTT (insert_page) */
1185 page_base += offset & PAGE_MASK;
1187 /* If we get a fault while copying data, then (presumably) our
1188 * source page isn't available. Return the error and we'll
1189 * retry in the slow path.
1190 * If the object is non-shmem backed, we retry again with the
1191 * path that handles page fault.
1193 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1194 user_data, page_length)) {
1199 remain -= page_length;
1200 user_data += page_length;
1201 offset += page_length;
1203 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1205 mutex_lock(&i915->drm.struct_mutex);
1207 if (node.allocated) {
1209 ggtt->base.clear_range(&ggtt->base,
1210 node.start, node.size);
1211 remove_mappable_node(&node);
1213 i915_vma_unpin(vma);
1216 intel_runtime_pm_put(i915);
1217 mutex_unlock(&i915->drm.struct_mutex);
1222 shmem_pwrite_slow(struct page *page, int offset, int length,
1223 char __user *user_data,
1224 bool page_do_bit17_swizzling,
1225 bool needs_clflush_before,
1226 bool needs_clflush_after)
1232 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1233 shmem_clflush_swizzled_range(vaddr + offset, length,
1234 page_do_bit17_swizzling);
1235 if (page_do_bit17_swizzling)
1236 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1239 ret = __copy_from_user(vaddr + offset, user_data, length);
1240 if (needs_clflush_after)
1241 shmem_clflush_swizzled_range(vaddr + offset, length,
1242 page_do_bit17_swizzling);
1245 return ret ? -EFAULT : 0;
1248 /* Per-page copy function for the shmem pwrite fastpath.
1249 * Flushes invalid cachelines before writing to the target if
1250 * needs_clflush_before is set and flushes out any written cachelines after
1251 * writing if needs_clflush is set.
1254 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1255 bool page_do_bit17_swizzling,
1256 bool needs_clflush_before,
1257 bool needs_clflush_after)
1262 if (!page_do_bit17_swizzling) {
1263 char *vaddr = kmap_atomic(page);
1265 if (needs_clflush_before)
1266 drm_clflush_virt_range(vaddr + offset, len);
1267 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1268 if (needs_clflush_after)
1269 drm_clflush_virt_range(vaddr + offset, len);
1271 kunmap_atomic(vaddr);
1276 return shmem_pwrite_slow(page, offset, len, user_data,
1277 page_do_bit17_swizzling,
1278 needs_clflush_before,
1279 needs_clflush_after);
1283 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1284 const struct drm_i915_gem_pwrite *args)
1286 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1287 void __user *user_data;
1289 unsigned int obj_do_bit17_swizzling;
1290 unsigned int partial_cacheline_write;
1291 unsigned int needs_clflush;
1292 unsigned int offset, idx;
1295 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1299 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1300 mutex_unlock(&i915->drm.struct_mutex);
1304 obj_do_bit17_swizzling = 0;
1305 if (i915_gem_object_needs_bit17_swizzle(obj))
1306 obj_do_bit17_swizzling = BIT(17);
1308 /* If we don't overwrite a cacheline completely we need to be
1309 * careful to have up-to-date data by first clflushing. Don't
1310 * overcomplicate things and flush the entire patch.
1312 partial_cacheline_write = 0;
1313 if (needs_clflush & CLFLUSH_BEFORE)
1314 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1316 user_data = u64_to_user_ptr(args->data_ptr);
1317 remain = args->size;
1318 offset = offset_in_page(args->offset);
1319 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1320 struct page *page = i915_gem_object_get_page(obj, idx);
1324 if (offset + length > PAGE_SIZE)
1325 length = PAGE_SIZE - offset;
1327 ret = shmem_pwrite(page, offset, length, user_data,
1328 page_to_phys(page) & obj_do_bit17_swizzling,
1329 (offset | length) & partial_cacheline_write,
1330 needs_clflush & CLFLUSH_AFTER);
1335 user_data += length;
1339 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1340 i915_gem_obj_finish_shmem_access(obj);
1345 * Writes data to the object referenced by handle.
1347 * @data: ioctl data blob
1350 * On error, the contents of the buffer that were to be modified are undefined.
1353 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1354 struct drm_file *file)
1356 struct drm_i915_gem_pwrite *args = data;
1357 struct drm_i915_gem_object *obj;
1360 if (args->size == 0)
1363 if (!access_ok(VERIFY_READ,
1364 u64_to_user_ptr(args->data_ptr),
1368 obj = i915_gem_object_lookup(file, args->handle);
1372 /* Bounds check destination. */
1373 if (args->offset > obj->base.size ||
1374 args->size > obj->base.size - args->offset) {
1379 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1381 ret = i915_gem_object_wait(obj,
1382 I915_WAIT_INTERRUPTIBLE |
1384 MAX_SCHEDULE_TIMEOUT,
1385 to_rps_client(file));
1389 ret = i915_gem_object_pin_pages(obj);
1394 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1395 * it would end up going through the fenced access, and we'll get
1396 * different detiling behavior between reading and writing.
1397 * pread/pwrite currently are reading and writing from the CPU
1398 * perspective, requiring manual detiling by the client.
1400 if (!i915_gem_object_has_struct_page(obj) ||
1401 cpu_write_needs_clflush(obj))
1402 /* Note that the gtt paths might fail with non-page-backed user
1403 * pointers (e.g. gtt mappings when moving data between
1404 * textures). Fallback to the shmem path in that case.
1406 ret = i915_gem_gtt_pwrite_fast(obj, args);
1408 if (ret == -EFAULT || ret == -ENOSPC) {
1409 if (obj->phys_handle)
1410 ret = i915_gem_phys_pwrite(obj, args, file);
1412 ret = i915_gem_shmem_pwrite(obj, args);
1415 i915_gem_object_unpin_pages(obj);
1417 i915_gem_object_put(obj);
1421 static inline enum fb_op_origin
1422 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1424 return (domain == I915_GEM_DOMAIN_GTT ?
1425 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1428 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1430 struct drm_i915_private *i915;
1431 struct list_head *list;
1432 struct i915_vma *vma;
1434 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1435 if (!i915_vma_is_ggtt(vma))
1438 if (i915_vma_is_active(vma))
1441 if (!drm_mm_node_allocated(&vma->node))
1444 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1447 i915 = to_i915(obj->base.dev);
1448 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1449 list_move_tail(&obj->global_list, list);
1453 * Called when user space prepares to use an object with the CPU, either
1454 * through the mmap ioctl's mapping or a GTT mapping.
1456 * @data: ioctl data blob
1460 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1461 struct drm_file *file)
1463 struct drm_i915_gem_set_domain *args = data;
1464 struct drm_i915_gem_object *obj;
1465 uint32_t read_domains = args->read_domains;
1466 uint32_t write_domain = args->write_domain;
1469 /* Only handle setting domains to types used by the CPU. */
1470 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1473 /* Having something in the write domain implies it's in the read
1474 * domain, and only that read domain. Enforce that in the request.
1476 if (write_domain != 0 && read_domains != write_domain)
1479 obj = i915_gem_object_lookup(file, args->handle);
1483 /* Try to flush the object off the GPU without holding the lock.
1484 * We will repeat the flush holding the lock in the normal manner
1485 * to catch cases where we are gazumped.
1487 err = i915_gem_object_wait(obj,
1488 I915_WAIT_INTERRUPTIBLE |
1489 (write_domain ? I915_WAIT_ALL : 0),
1490 MAX_SCHEDULE_TIMEOUT,
1491 to_rps_client(file));
1495 /* Flush and acquire obj->pages so that we are coherent through
1496 * direct access in memory with previous cached writes through
1497 * shmemfs and that our cache domain tracking remains valid.
1498 * For example, if the obj->filp was moved to swap without us
1499 * being notified and releasing the pages, we would mistakenly
1500 * continue to assume that the obj remained out of the CPU cached
1503 err = i915_gem_object_pin_pages(obj);
1507 err = i915_mutex_lock_interruptible(dev);
1511 if (read_domains & I915_GEM_DOMAIN_GTT)
1512 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1514 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1516 /* And bump the LRU for this access */
1517 i915_gem_object_bump_inactive_ggtt(obj);
1519 mutex_unlock(&dev->struct_mutex);
1521 if (write_domain != 0)
1522 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1525 i915_gem_object_unpin_pages(obj);
1527 i915_gem_object_put(obj);
1532 * Called when user space has done writes to this buffer
1534 * @data: ioctl data blob
1538 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1539 struct drm_file *file)
1541 struct drm_i915_gem_sw_finish *args = data;
1542 struct drm_i915_gem_object *obj;
1545 obj = i915_gem_object_lookup(file, args->handle);
1549 /* Pinned buffers may be scanout, so flush the cache */
1550 if (READ_ONCE(obj->pin_display)) {
1551 err = i915_mutex_lock_interruptible(dev);
1553 i915_gem_object_flush_cpu_write_domain(obj);
1554 mutex_unlock(&dev->struct_mutex);
1558 i915_gem_object_put(obj);
1563 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1566 * @data: ioctl data blob
1569 * While the mapping holds a reference on the contents of the object, it doesn't
1570 * imply a ref on the object itself.
1574 * DRM driver writers who look a this function as an example for how to do GEM
1575 * mmap support, please don't implement mmap support like here. The modern way
1576 * to implement DRM mmap support is with an mmap offset ioctl (like
1577 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1578 * That way debug tooling like valgrind will understand what's going on, hiding
1579 * the mmap call in a driver private ioctl will break that. The i915 driver only
1580 * does cpu mmaps this way because we didn't know better.
1583 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1584 struct drm_file *file)
1586 struct drm_i915_gem_mmap *args = data;
1587 struct drm_i915_gem_object *obj;
1590 if (args->flags & ~(I915_MMAP_WC))
1593 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1596 obj = i915_gem_object_lookup(file, args->handle);
1600 /* prime objects have no backing filp to GEM mmap
1603 if (!obj->base.filp) {
1604 i915_gem_object_put(obj);
1608 addr = vm_mmap(obj->base.filp, 0, args->size,
1609 PROT_READ | PROT_WRITE, MAP_SHARED,
1611 if (args->flags & I915_MMAP_WC) {
1612 struct mm_struct *mm = current->mm;
1613 struct vm_area_struct *vma;
1615 if (down_write_killable(&mm->mmap_sem)) {
1616 i915_gem_object_put(obj);
1619 vma = find_vma(mm, addr);
1622 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1625 up_write(&mm->mmap_sem);
1627 /* This may race, but that's ok, it only gets set */
1628 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1630 i915_gem_object_put(obj);
1631 if (IS_ERR((void *)addr))
1634 args->addr_ptr = (uint64_t) addr;
1639 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1643 size = i915_gem_object_get_stride(obj);
1644 size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
1646 return size >> PAGE_SHIFT;
1650 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1652 * A history of the GTT mmap interface:
1654 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1655 * aligned and suitable for fencing, and still fit into the available
1656 * mappable space left by the pinned display objects. A classic problem
1657 * we called the page-fault-of-doom where we would ping-pong between
1658 * two objects that could not fit inside the GTT and so the memcpy
1659 * would page one object in at the expense of the other between every
1662 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1663 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1664 * object is too large for the available space (or simply too large
1665 * for the mappable aperture!), a view is created instead and faulted
1666 * into userspace. (This view is aligned and sized appropriately for
1671 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1672 * hangs on some architectures, corruption on others. An attempt to service
1673 * a GTT page fault from a snoopable object will generate a SIGBUS.
1675 * * the object must be able to fit into RAM (physical memory, though no
1676 * limited to the mappable aperture).
1681 * * a new GTT page fault will synchronize rendering from the GPU and flush
1682 * all data to system memory. Subsequent access will not be synchronized.
1684 * * all mappings are revoked on runtime device suspend.
1686 * * there are only 8, 16 or 32 fence registers to share between all users
1687 * (older machines require fence register for display and blitter access
1688 * as well). Contention of the fence registers will cause the previous users
1689 * to be unmapped and any new access will generate new page faults.
1691 * * running out of memory while servicing a fault may generate a SIGBUS,
1692 * rather than the expected SIGSEGV.
1694 int i915_gem_mmap_gtt_version(void)
1700 * i915_gem_fault - fault a page into the GTT
1701 * @area: CPU VMA in question
1704 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1705 * from userspace. The fault handler takes care of binding the object to
1706 * the GTT (if needed), allocating and programming a fence register (again,
1707 * only if needed based on whether the old reg is still valid or the object
1708 * is tiled) and inserting a new PTE into the faulting process.
1710 * Note that the faulting process may involve evicting existing objects
1711 * from the GTT and/or fence registers to make room. So performance may
1712 * suffer if the GTT working set is large or there are few fence registers
1715 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1716 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1718 int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1720 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1721 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1722 struct drm_device *dev = obj->base.dev;
1723 struct drm_i915_private *dev_priv = to_i915(dev);
1724 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1725 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1726 struct i915_vma *vma;
1727 pgoff_t page_offset;
1731 /* We don't use vmf->pgoff since that has the fake offset */
1732 page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >>
1735 trace_i915_gem_object_fault(obj, page_offset, true, write);
1737 /* Try to flush the object off the GPU first without holding the lock.
1738 * Upon acquiring the lock, we will perform our sanity checks and then
1739 * repeat the flush holding the lock in the normal manner to catch cases
1740 * where we are gazumped.
1742 ret = i915_gem_object_wait(obj,
1743 I915_WAIT_INTERRUPTIBLE,
1744 MAX_SCHEDULE_TIMEOUT,
1749 ret = i915_gem_object_pin_pages(obj);
1753 intel_runtime_pm_get(dev_priv);
1755 ret = i915_mutex_lock_interruptible(dev);
1759 /* Access to snoopable pages through the GTT is incoherent. */
1760 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1765 /* If the object is smaller than a couple of partial vma, it is
1766 * not worth only creating a single partial vma - we may as well
1767 * clear enough space for the full object.
1769 flags = PIN_MAPPABLE;
1770 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1771 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1773 /* Now pin it into the GTT as needed */
1774 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1776 struct i915_ggtt_view view;
1777 unsigned int chunk_size;
1779 /* Use a partial view if it is bigger than available space */
1780 chunk_size = MIN_CHUNK_PAGES;
1781 if (i915_gem_object_is_tiled(obj))
1782 chunk_size = max(chunk_size, tile_row_pages(obj));
1784 memset(&view, 0, sizeof(view));
1785 view.type = I915_GGTT_VIEW_PARTIAL;
1786 view.params.partial.offset = rounddown(page_offset, chunk_size);
1787 view.params.partial.size =
1788 min_t(unsigned int, chunk_size,
1789 vma_pages(area) - view.params.partial.offset);
1791 /* If the partial covers the entire object, just create a
1794 if (chunk_size >= obj->base.size >> PAGE_SHIFT)
1795 view.type = I915_GGTT_VIEW_NORMAL;
1797 /* Userspace is now writing through an untracked VMA, abandon
1798 * all hope that the hardware is able to track future writes.
1800 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1802 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1809 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1813 ret = i915_vma_get_fence(vma);
1817 /* Mark as being mmapped into userspace for later revocation */
1818 assert_rpm_wakelock_held(dev_priv);
1819 if (list_empty(&obj->userfault_link))
1820 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1822 /* Finally, remap it using the new GTT offset */
1823 ret = remap_io_mapping(area,
1824 area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
1825 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1826 min_t(u64, vma->size, area->vm_end - area->vm_start),
1830 __i915_vma_unpin(vma);
1832 mutex_unlock(&dev->struct_mutex);
1834 intel_runtime_pm_put(dev_priv);
1835 i915_gem_object_unpin_pages(obj);
1840 * We eat errors when the gpu is terminally wedged to avoid
1841 * userspace unduly crashing (gl has no provisions for mmaps to
1842 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1843 * and so needs to be reported.
1845 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1846 ret = VM_FAULT_SIGBUS;
1851 * EAGAIN means the gpu is hung and we'll wait for the error
1852 * handler to reset everything when re-faulting in
1853 * i915_mutex_lock_interruptible.
1860 * EBUSY is ok: this just means that another thread
1861 * already did the job.
1863 ret = VM_FAULT_NOPAGE;
1870 ret = VM_FAULT_SIGBUS;
1873 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1874 ret = VM_FAULT_SIGBUS;
1881 * i915_gem_release_mmap - remove physical page mappings
1882 * @obj: obj in question
1884 * Preserve the reservation of the mmapping with the DRM core code, but
1885 * relinquish ownership of the pages back to the system.
1887 * It is vital that we remove the page mapping if we have mapped a tiled
1888 * object through the GTT and then lose the fence register due to
1889 * resource pressure. Similarly if the object has been moved out of the
1890 * aperture, than pages mapped into userspace must be revoked. Removing the
1891 * mapping will then trigger a page fault on the next user access, allowing
1892 * fixup by i915_gem_fault().
1895 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1897 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1899 /* Serialisation between user GTT access and our code depends upon
1900 * revoking the CPU's PTE whilst the mutex is held. The next user
1901 * pagefault then has to wait until we release the mutex.
1903 * Note that RPM complicates somewhat by adding an additional
1904 * requirement that operations to the GGTT be made holding the RPM
1907 lockdep_assert_held(&i915->drm.struct_mutex);
1908 intel_runtime_pm_get(i915);
1910 if (list_empty(&obj->userfault_link))
1913 list_del_init(&obj->userfault_link);
1914 drm_vma_node_unmap(&obj->base.vma_node,
1915 obj->base.dev->anon_inode->i_mapping);
1917 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1918 * memory transactions from userspace before we return. The TLB
1919 * flushing implied above by changing the PTE above *should* be
1920 * sufficient, an extra barrier here just provides us with a bit
1921 * of paranoid documentation about our requirement to serialise
1922 * memory writes before touching registers / GSM.
1927 intel_runtime_pm_put(i915);
1930 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1932 struct drm_i915_gem_object *obj, *on;
1936 * Only called during RPM suspend. All users of the userfault_list
1937 * must be holding an RPM wakeref to ensure that this can not
1938 * run concurrently with themselves (and use the struct_mutex for
1939 * protection between themselves).
1942 list_for_each_entry_safe(obj, on,
1943 &dev_priv->mm.userfault_list, userfault_link) {
1944 list_del_init(&obj->userfault_link);
1945 drm_vma_node_unmap(&obj->base.vma_node,
1946 obj->base.dev->anon_inode->i_mapping);
1949 /* The fence will be lost when the device powers down. If any were
1950 * in use by hardware (i.e. they are pinned), we should not be powering
1951 * down! All other fences will be reacquired by the user upon waking.
1953 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1954 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1956 if (WARN_ON(reg->pin_count))
1962 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
1968 * i915_gem_get_ggtt_size - return required global GTT size for an object
1969 * @dev_priv: i915 device
1970 * @size: object size
1971 * @tiling_mode: tiling mode
1973 * Return the required global GTT size for an object, taking into account
1974 * potential fence register mapping.
1976 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
1977 u64 size, int tiling_mode)
1981 GEM_BUG_ON(size == 0);
1983 if (INTEL_GEN(dev_priv) >= 4 ||
1984 tiling_mode == I915_TILING_NONE)
1987 /* Previous chips need a power-of-two fence region when tiling */
1988 if (IS_GEN3(dev_priv))
1989 ggtt_size = 1024*1024;
1991 ggtt_size = 512*1024;
1993 while (ggtt_size < size)
2000 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2001 * @dev_priv: i915 device
2002 * @size: object size
2003 * @tiling_mode: tiling mode
2004 * @fenced: is fenced alignment required or not
2006 * Return the required global GTT alignment for an object, taking into account
2007 * potential fence register mapping.
2009 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
2010 int tiling_mode, bool fenced)
2012 GEM_BUG_ON(size == 0);
2015 * Minimum alignment is 4k (GTT page size), but might be greater
2016 * if a fence register is needed for the object.
2018 if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
2019 tiling_mode == I915_TILING_NONE)
2023 * Previous chips need to be aligned to the size of the smallest
2024 * fence register that can contain the object.
2026 return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
2029 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2031 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2034 err = drm_gem_create_mmap_offset(&obj->base);
2038 /* We can idle the GPU locklessly to flush stale objects, but in order
2039 * to claim that space for ourselves, we need to take the big
2040 * struct_mutex to free the requests+objects and allocate our slot.
2042 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2046 err = i915_mutex_lock_interruptible(&dev_priv->drm);
2048 i915_gem_retire_requests(dev_priv);
2049 err = drm_gem_create_mmap_offset(&obj->base);
2050 mutex_unlock(&dev_priv->drm.struct_mutex);
2056 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2058 drm_gem_free_mmap_offset(&obj->base);
2062 i915_gem_mmap_gtt(struct drm_file *file,
2063 struct drm_device *dev,
2067 struct drm_i915_gem_object *obj;
2070 obj = i915_gem_object_lookup(file, handle);
2074 ret = i915_gem_object_create_mmap_offset(obj);
2076 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2078 i915_gem_object_put(obj);
2083 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2085 * @data: GTT mapping ioctl data
2086 * @file: GEM object info
2088 * Simply returns the fake offset to userspace so it can mmap it.
2089 * The mmap call will end up in drm_gem_mmap(), which will set things
2090 * up so we can get faults in the handler above.
2092 * The fault handler will take care of binding the object into the GTT
2093 * (since it may have been evicted to make room for something), allocating
2094 * a fence register, and mapping the appropriate aperture address into
2098 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *file)
2101 struct drm_i915_gem_mmap_gtt *args = data;
2103 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2106 /* Immediately discard the backing storage */
2108 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2110 i915_gem_object_free_mmap_offset(obj);
2112 if (obj->base.filp == NULL)
2115 /* Our goal here is to return as much of the memory as
2116 * is possible back to the system as we are called from OOM.
2117 * To do this we must instruct the shmfs to drop all of its
2118 * backing pages, *now*.
2120 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2121 obj->mm.madv = __I915_MADV_PURGED;
2124 /* Try to discard unwanted pages */
2125 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2127 struct address_space *mapping;
2129 lockdep_assert_held(&obj->mm.lock);
2130 GEM_BUG_ON(obj->mm.pages);
2132 switch (obj->mm.madv) {
2133 case I915_MADV_DONTNEED:
2134 i915_gem_object_truncate(obj);
2135 case __I915_MADV_PURGED:
2139 if (obj->base.filp == NULL)
2142 mapping = obj->base.filp->f_mapping,
2143 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2147 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2148 struct sg_table *pages)
2150 struct sgt_iter sgt_iter;
2153 __i915_gem_object_release_shmem(obj);
2155 i915_gem_gtt_finish_pages(obj, pages);
2157 if (i915_gem_object_needs_bit17_swizzle(obj))
2158 i915_gem_object_save_bit_17_swizzle(obj, pages);
2160 for_each_sgt_page(page, sgt_iter, pages) {
2162 set_page_dirty(page);
2164 if (obj->mm.madv == I915_MADV_WILLNEED)
2165 mark_page_accessed(page);
2169 obj->mm.dirty = false;
2171 sg_free_table(pages);
2175 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2177 struct radix_tree_iter iter;
2180 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2181 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2184 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2186 struct sg_table *pages;
2188 if (i915_gem_object_has_pinned_pages(obj))
2191 GEM_BUG_ON(obj->bind_count);
2192 if (!READ_ONCE(obj->mm.pages))
2195 /* May be called by shrinker from within get_pages() (on another bo) */
2196 mutex_lock_nested(&obj->mm.lock, SINGLE_DEPTH_NESTING);
2197 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2200 /* ->put_pages might need to allocate memory for the bit17 swizzle
2201 * array, hence protect them from being reaped by removing them from gtt
2203 pages = fetch_and_zero(&obj->mm.pages);
2206 if (obj->mm.mapping) {
2209 ptr = ptr_mask_bits(obj->mm.mapping);
2210 if (is_vmalloc_addr(ptr))
2213 kunmap(kmap_to_page(ptr));
2215 obj->mm.mapping = NULL;
2218 __i915_gem_object_reset_page_iter(obj);
2220 obj->ops->put_pages(obj, pages);
2222 mutex_unlock(&obj->mm.lock);
2225 static unsigned int swiotlb_max_size(void)
2227 #if IS_ENABLED(CONFIG_SWIOTLB)
2228 return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE);
2234 static struct sg_table *
2235 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2237 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2239 struct address_space *mapping;
2240 struct sg_table *st;
2241 struct scatterlist *sg;
2242 struct sgt_iter sgt_iter;
2244 unsigned long last_pfn = 0; /* suppress gcc warning */
2245 unsigned int max_segment;
2249 /* Assert that the object is not currently in any GPU domain. As it
2250 * wasn't in the GTT, there shouldn't be any way it could have been in
2253 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2254 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2256 max_segment = swiotlb_max_size();
2258 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2260 st = kmalloc(sizeof(*st), GFP_KERNEL);
2262 return ERR_PTR(-ENOMEM);
2264 page_count = obj->base.size / PAGE_SIZE;
2265 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2267 return ERR_PTR(-ENOMEM);
2270 /* Get the list of pages out of our struct file. They'll be pinned
2271 * at this point until we release them.
2273 * Fail silently without starting the shrinker
2275 mapping = obj->base.filp->f_mapping;
2276 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2277 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2280 for (i = 0; i < page_count; i++) {
2281 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2283 i915_gem_shrink(dev_priv,
2286 I915_SHRINK_UNBOUND |
2287 I915_SHRINK_PURGEABLE);
2288 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2291 /* We've tried hard to allocate the memory by reaping
2292 * our own buffer, now let the real VM do its job and
2293 * go down in flames if truly OOM.
2295 page = shmem_read_mapping_page(mapping, i);
2297 ret = PTR_ERR(page);
2302 sg->length >= max_segment ||
2303 page_to_pfn(page) != last_pfn + 1) {
2307 sg_set_page(sg, page, PAGE_SIZE, 0);
2309 sg->length += PAGE_SIZE;
2311 last_pfn = page_to_pfn(page);
2313 /* Check that the i965g/gm workaround works. */
2314 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2316 if (sg) /* loop terminated early; short sg table */
2319 ret = i915_gem_gtt_prepare_pages(obj, st);
2323 if (i915_gem_object_needs_bit17_swizzle(obj))
2324 i915_gem_object_do_bit_17_swizzle(obj, st);
2326 if (i915_gem_object_is_tiled(obj) &&
2327 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2328 __i915_gem_object_pin_pages(obj);
2334 for_each_sgt_page(page, sgt_iter, st)
2339 /* shmemfs first checks if there is enough memory to allocate the page
2340 * and reports ENOSPC should there be insufficient, along with the usual
2341 * ENOMEM for a genuine allocation failure.
2343 * We use ENOSPC in our driver to mean that we have run out of aperture
2344 * space and so want to translate the error from shmemfs back to our
2345 * usual understanding of ENOMEM.
2350 return ERR_PTR(ret);
2353 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2354 struct sg_table *pages)
2356 lockdep_assert_held(&obj->mm.lock);
2358 obj->mm.get_page.sg_pos = pages->sgl;
2359 obj->mm.get_page.sg_idx = 0;
2361 obj->mm.pages = pages;
2364 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2366 struct sg_table *pages;
2368 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2369 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2373 pages = obj->ops->get_pages(obj);
2374 if (unlikely(IS_ERR(pages)))
2375 return PTR_ERR(pages);
2377 __i915_gem_object_set_pages(obj, pages);
2381 /* Ensure that the associated pages are gathered from the backing storage
2382 * and pinned into our object. i915_gem_object_pin_pages() may be called
2383 * multiple times before they are released by a single call to
2384 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2385 * either as a result of memory pressure (reaping pages under the shrinker)
2386 * or as the object is itself released.
2388 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2392 err = mutex_lock_interruptible(&obj->mm.lock);
2396 if (likely(obj->mm.pages)) {
2397 __i915_gem_object_pin_pages(obj);
2401 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2403 err = ____i915_gem_object_get_pages(obj);
2405 atomic_set_release(&obj->mm.pages_pin_count, 1);
2408 mutex_unlock(&obj->mm.lock);
2412 /* The 'mapping' part of i915_gem_object_pin_map() below */
2413 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2414 enum i915_map_type type)
2416 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2417 struct sg_table *sgt = obj->mm.pages;
2418 struct sgt_iter sgt_iter;
2420 struct page *stack_pages[32];
2421 struct page **pages = stack_pages;
2422 unsigned long i = 0;
2426 /* A single page can always be kmapped */
2427 if (n_pages == 1 && type == I915_MAP_WB)
2428 return kmap(sg_page(sgt->sgl));
2430 if (n_pages > ARRAY_SIZE(stack_pages)) {
2431 /* Too big for stack -- allocate temporary array instead */
2432 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2437 for_each_sgt_page(page, sgt_iter, sgt)
2440 /* Check that we have the expected number of pages */
2441 GEM_BUG_ON(i != n_pages);
2445 pgprot = PAGE_KERNEL;
2448 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2451 addr = vmap(pages, n_pages, 0, pgprot);
2453 if (pages != stack_pages)
2454 drm_free_large(pages);
2459 /* get, pin, and map the pages of the object into kernel space */
2460 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2461 enum i915_map_type type)
2463 enum i915_map_type has_type;
2468 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2470 ret = mutex_lock_interruptible(&obj->mm.lock);
2472 return ERR_PTR(ret);
2475 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2476 ret = ____i915_gem_object_get_pages(obj);
2480 GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count));
2481 atomic_set_release(&obj->mm.pages_pin_count, 1);
2484 GEM_BUG_ON(!obj->mm.pages);
2486 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2487 if (ptr && has_type != type) {
2493 if (is_vmalloc_addr(ptr))
2496 kunmap(kmap_to_page(ptr));
2498 ptr = obj->mm.mapping = NULL;
2502 ptr = i915_gem_object_map(obj, type);
2508 obj->mm.mapping = ptr_pack_bits(ptr, type);
2512 mutex_unlock(&obj->mm.lock);
2516 atomic_dec(&obj->mm.pages_pin_count);
2522 static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2524 unsigned long elapsed;
2526 if (ctx->hang_stats.banned)
2529 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2530 if (ctx->hang_stats.ban_period_seconds &&
2531 elapsed <= ctx->hang_stats.ban_period_seconds) {
2532 DRM_DEBUG("context hanging too fast, banning!\n");
2539 static void i915_set_reset_status(struct i915_gem_context *ctx,
2542 struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2545 hs->banned = i915_context_is_banned(ctx);
2547 hs->guilty_ts = get_seconds();
2549 hs->batch_pending++;
2553 struct drm_i915_gem_request *
2554 i915_gem_find_active_request(struct intel_engine_cs *engine)
2556 struct drm_i915_gem_request *request;
2558 /* We are called by the error capture and reset at a random
2559 * point in time. In particular, note that neither is crucially
2560 * ordered with an interrupt. After a hang, the GPU is dead and we
2561 * assume that no more writes can happen (we waited long enough for
2562 * all writes that were in transaction to be flushed) - adding an
2563 * extra delay for a recent interrupt is pointless. Hence, we do
2564 * not need an engine->irq_seqno_barrier() before the seqno reads.
2566 list_for_each_entry(request, &engine->timeline->requests, link) {
2567 if (__i915_gem_request_completed(request))
2576 static void reset_request(struct drm_i915_gem_request *request)
2578 void *vaddr = request->ring->vaddr;
2581 /* As this request likely depends on state from the lost
2582 * context, clear out all the user operations leaving the
2583 * breadcrumb at the end (so we get the fence notifications).
2585 head = request->head;
2586 if (request->postfix < head) {
2587 memset(vaddr + head, 0, request->ring->size - head);
2590 memset(vaddr + head, 0, request->postfix - head);
2593 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2595 struct drm_i915_gem_request *request;
2596 struct i915_gem_context *incomplete_ctx;
2597 struct intel_timeline *timeline;
2600 if (engine->irq_seqno_barrier)
2601 engine->irq_seqno_barrier(engine);
2603 request = i915_gem_find_active_request(engine);
2607 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2608 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
2611 i915_set_reset_status(request->ctx, ring_hung);
2615 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2616 engine->name, request->global_seqno);
2618 /* Setup the CS to resume from the breadcrumb of the hung request */
2619 engine->reset_hw(engine, request);
2621 /* Users of the default context do not rely on logical state
2622 * preserved between batches. They have to emit full state on
2623 * every batch and so it is safe to execute queued requests following
2626 * Other contexts preserve state, now corrupt. We want to skip all
2627 * queued requests that reference the corrupt context.
2629 incomplete_ctx = request->ctx;
2630 if (i915_gem_context_is_default(incomplete_ctx))
2633 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2634 if (request->ctx == incomplete_ctx)
2635 reset_request(request);
2637 timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2638 list_for_each_entry(request, &timeline->requests, link)
2639 reset_request(request);
2642 void i915_gem_reset(struct drm_i915_private *dev_priv)
2644 struct intel_engine_cs *engine;
2645 enum intel_engine_id id;
2647 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2649 i915_gem_retire_requests(dev_priv);
2651 for_each_engine(engine, dev_priv, id)
2652 i915_gem_reset_engine(engine);
2654 i915_gem_restore_fences(&dev_priv->drm);
2656 if (dev_priv->gt.awake) {
2657 intel_sanitize_gt_powersave(dev_priv);
2658 intel_enable_gt_powersave(dev_priv);
2659 if (INTEL_GEN(dev_priv) >= 6)
2660 gen6_rps_busy(dev_priv);
2664 static void nop_submit_request(struct drm_i915_gem_request *request)
2668 static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
2670 engine->submit_request = nop_submit_request;
2672 /* Mark all pending requests as complete so that any concurrent
2673 * (lockless) lookup doesn't try and wait upon the request as we
2676 intel_engine_init_global_seqno(engine,
2677 engine->timeline->last_submitted_seqno);
2680 * Clear the execlists queue up before freeing the requests, as those
2681 * are the ones that keep the context and ringbuffer backing objects
2685 if (i915.enable_execlists) {
2686 spin_lock(&engine->execlist_lock);
2687 INIT_LIST_HEAD(&engine->execlist_queue);
2688 i915_gem_request_put(engine->execlist_port[0].request);
2689 i915_gem_request_put(engine->execlist_port[1].request);
2690 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2691 spin_unlock(&engine->execlist_lock);
2695 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2697 struct intel_engine_cs *engine;
2698 enum intel_engine_id id;
2700 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2701 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2703 i915_gem_context_lost(dev_priv);
2704 for_each_engine(engine, dev_priv, id)
2705 i915_gem_cleanup_engine(engine);
2706 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2708 i915_gem_retire_requests(dev_priv);
2712 i915_gem_retire_work_handler(struct work_struct *work)
2714 struct drm_i915_private *dev_priv =
2715 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2716 struct drm_device *dev = &dev_priv->drm;
2718 /* Come back later if the device is busy... */
2719 if (mutex_trylock(&dev->struct_mutex)) {
2720 i915_gem_retire_requests(dev_priv);
2721 mutex_unlock(&dev->struct_mutex);
2724 /* Keep the retire handler running until we are finally idle.
2725 * We do not need to do this test under locking as in the worst-case
2726 * we queue the retire worker once too often.
2728 if (READ_ONCE(dev_priv->gt.awake)) {
2729 i915_queue_hangcheck(dev_priv);
2730 queue_delayed_work(dev_priv->wq,
2731 &dev_priv->gt.retire_work,
2732 round_jiffies_up_relative(HZ));
2737 i915_gem_idle_work_handler(struct work_struct *work)
2739 struct drm_i915_private *dev_priv =
2740 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2741 struct drm_device *dev = &dev_priv->drm;
2742 struct intel_engine_cs *engine;
2743 enum intel_engine_id id;
2744 bool rearm_hangcheck;
2746 if (!READ_ONCE(dev_priv->gt.awake))
2749 if (READ_ONCE(dev_priv->gt.active_requests))
2753 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2755 if (!mutex_trylock(&dev->struct_mutex)) {
2756 /* Currently busy, come back later */
2757 mod_delayed_work(dev_priv->wq,
2758 &dev_priv->gt.idle_work,
2759 msecs_to_jiffies(50));
2763 if (dev_priv->gt.active_requests)
2766 for_each_engine(engine, dev_priv, id)
2767 i915_gem_batch_pool_fini(&engine->batch_pool);
2769 GEM_BUG_ON(!dev_priv->gt.awake);
2770 dev_priv->gt.awake = false;
2771 rearm_hangcheck = false;
2773 if (INTEL_GEN(dev_priv) >= 6)
2774 gen6_rps_idle(dev_priv);
2775 intel_runtime_pm_put(dev_priv);
2777 mutex_unlock(&dev->struct_mutex);
2780 if (rearm_hangcheck) {
2781 GEM_BUG_ON(!dev_priv->gt.awake);
2782 i915_queue_hangcheck(dev_priv);
2786 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2788 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2789 struct drm_i915_file_private *fpriv = file->driver_priv;
2790 struct i915_vma *vma, *vn;
2792 mutex_lock(&obj->base.dev->struct_mutex);
2793 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
2794 if (vma->vm->file == fpriv)
2795 i915_vma_close(vma);
2797 if (i915_gem_object_is_active(obj) &&
2798 !i915_gem_object_has_active_reference(obj)) {
2799 i915_gem_object_set_active_reference(obj);
2800 i915_gem_object_get(obj);
2802 mutex_unlock(&obj->base.dev->struct_mutex);
2805 static unsigned long to_wait_timeout(s64 timeout_ns)
2808 return MAX_SCHEDULE_TIMEOUT;
2810 if (timeout_ns == 0)
2813 return nsecs_to_jiffies_timeout(timeout_ns);
2817 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2818 * @dev: drm device pointer
2819 * @data: ioctl data blob
2820 * @file: drm file pointer
2822 * Returns 0 if successful, else an error is returned with the remaining time in
2823 * the timeout parameter.
2824 * -ETIME: object is still busy after timeout
2825 * -ERESTARTSYS: signal interrupted the wait
2826 * -ENONENT: object doesn't exist
2827 * Also possible, but rare:
2828 * -EAGAIN: GPU wedged
2830 * -ENODEV: Internal IRQ fail
2831 * -E?: The add request failed
2833 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2834 * non-zero timeout parameter the wait ioctl will wait for the given number of
2835 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2836 * without holding struct_mutex the object may become re-busied before this
2837 * function completes. A similar but shorter * race condition exists in the busy
2841 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2843 struct drm_i915_gem_wait *args = data;
2844 struct drm_i915_gem_object *obj;
2848 if (args->flags != 0)
2851 obj = i915_gem_object_lookup(file, args->bo_handle);
2855 start = ktime_get();
2857 ret = i915_gem_object_wait(obj,
2858 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
2859 to_wait_timeout(args->timeout_ns),
2860 to_rps_client(file));
2862 if (args->timeout_ns > 0) {
2863 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
2864 if (args->timeout_ns < 0)
2865 args->timeout_ns = 0;
2868 i915_gem_object_put(obj);
2872 static void __i915_vma_iounmap(struct i915_vma *vma)
2874 GEM_BUG_ON(i915_vma_is_pinned(vma));
2876 if (vma->iomap == NULL)
2879 io_mapping_unmap(vma->iomap);
2883 int i915_vma_unbind(struct i915_vma *vma)
2885 struct drm_i915_gem_object *obj = vma->obj;
2886 unsigned long active;
2889 lockdep_assert_held(&obj->base.dev->struct_mutex);
2891 /* First wait upon any activity as retiring the request may
2892 * have side-effects such as unpinning or even unbinding this vma.
2894 active = i915_vma_get_active(vma);
2898 /* When a closed VMA is retired, it is unbound - eek.
2899 * In order to prevent it from being recursively closed,
2900 * take a pin on the vma so that the second unbind is
2903 * Even more scary is that the retire callback may free
2904 * the object (last active vma). To prevent the explosion
2905 * we defer the actual object free to a worker that can
2906 * only proceed once it acquires the struct_mutex (which
2907 * we currently hold, therefore it cannot free this object
2908 * before we are finished).
2910 __i915_vma_pin(vma);
2912 for_each_active(active, idx) {
2913 ret = i915_gem_active_retire(&vma->last_read[idx],
2914 &vma->vm->dev->struct_mutex);
2919 __i915_vma_unpin(vma);
2923 GEM_BUG_ON(i915_vma_is_active(vma));
2926 if (i915_vma_is_pinned(vma))
2929 if (!drm_mm_node_allocated(&vma->node))
2932 GEM_BUG_ON(obj->bind_count == 0);
2933 GEM_BUG_ON(!obj->mm.pages);
2935 if (i915_vma_is_map_and_fenceable(vma)) {
2936 /* release the fence reg _after_ flushing */
2937 ret = i915_vma_put_fence(vma);
2941 /* Force a pagefault for domain tracking on next user access */
2942 i915_gem_release_mmap(obj);
2944 __i915_vma_iounmap(vma);
2945 vma->flags &= ~I915_VMA_CAN_FENCE;
2948 if (likely(!vma->vm->closed)) {
2949 trace_i915_vma_unbind(vma);
2950 vma->vm->unbind_vma(vma);
2952 vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND);
2954 drm_mm_remove_node(&vma->node);
2955 list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
2957 if (vma->pages != obj->mm.pages) {
2958 GEM_BUG_ON(!vma->pages);
2959 sg_free_table(vma->pages);
2964 /* Since the unbound list is global, only move to that list if
2965 * no more VMAs exist. */
2966 if (--obj->bind_count == 0)
2967 list_move_tail(&obj->global_list,
2968 &to_i915(obj->base.dev)->mm.unbound_list);
2970 /* And finally now the object is completely decoupled from this vma,
2971 * we can drop its hold on the backing storage and allow it to be
2972 * reaped by the shrinker.
2974 i915_gem_object_unpin_pages(obj);
2977 if (unlikely(i915_vma_is_closed(vma)))
2978 i915_vma_destroy(vma);
2983 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
2987 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
2988 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
2996 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
2998 struct i915_gem_timeline *tl;
3001 list_for_each_entry(tl, &i915->gt.timelines, link) {
3002 ret = wait_for_timeline(tl, flags);
3010 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3011 unsigned long cache_level)
3013 struct drm_mm_node *gtt_space = &vma->node;
3014 struct drm_mm_node *other;
3017 * On some machines we have to be careful when putting differing types
3018 * of snoopable memory together to avoid the prefetcher crossing memory
3019 * domains and dying. During vm initialisation, we decide whether or not
3020 * these constraints apply and set the drm_mm.color_adjust
3023 if (vma->vm->mm.color_adjust == NULL)
3026 if (!drm_mm_node_allocated(gtt_space))
3029 if (list_empty(>t_space->node_list))
3032 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3033 if (other->allocated && !other->hole_follows && other->color != cache_level)
3036 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3037 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3044 * i915_vma_insert - finds a slot for the vma in its address space
3046 * @size: requested size in bytes (can be larger than the VMA)
3047 * @alignment: required alignment
3048 * @flags: mask of PIN_* flags to use
3050 * First we try to allocate some free space that meets the requirements for
3051 * the VMA. Failiing that, if the flags permit, it will evict an old VMA,
3052 * preferrably the oldest idle entry to make room for the new VMA.
3055 * 0 on success, negative error code otherwise.
3058 i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
3060 struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
3061 struct drm_i915_gem_object *obj = vma->obj;
3065 GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
3066 GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
3068 size = max(size, vma->size);
3069 if (flags & PIN_MAPPABLE)
3070 size = i915_gem_get_ggtt_size(dev_priv, size,
3071 i915_gem_object_get_tiling(obj));
3073 alignment = max(max(alignment, vma->display_alignment),
3074 i915_gem_get_ggtt_alignment(dev_priv, size,
3075 i915_gem_object_get_tiling(obj),
3076 flags & PIN_MAPPABLE));
3078 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3080 end = vma->vm->total;
3081 if (flags & PIN_MAPPABLE)
3082 end = min_t(u64, end, dev_priv->ggtt.mappable_end);
3083 if (flags & PIN_ZONE_4G)
3084 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3086 /* If binding the object/GGTT view requires more space than the entire
3087 * aperture has, reject it early before evicting everything in a vain
3088 * attempt to find space.
3091 DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n",
3092 size, obj->base.size,
3093 flags & PIN_MAPPABLE ? "mappable" : "total",
3098 ret = i915_gem_object_pin_pages(obj);
3102 if (flags & PIN_OFFSET_FIXED) {
3103 u64 offset = flags & PIN_OFFSET_MASK;
3104 if (offset & (alignment - 1) || offset > end - size) {
3109 vma->node.start = offset;
3110 vma->node.size = size;
3111 vma->node.color = obj->cache_level;
3112 ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node);
3114 ret = i915_gem_evict_for_vma(vma);
3116 ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node);
3121 u32 search_flag, alloc_flag;
3123 if (flags & PIN_HIGH) {
3124 search_flag = DRM_MM_SEARCH_BELOW;
3125 alloc_flag = DRM_MM_CREATE_TOP;
3127 search_flag = DRM_MM_SEARCH_DEFAULT;
3128 alloc_flag = DRM_MM_CREATE_DEFAULT;
3131 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3132 * so we know that we always have a minimum alignment of 4096.
3133 * The drm_mm range manager is optimised to return results
3134 * with zero alignment, so where possible use the optimal
3137 if (alignment <= 4096)
3141 ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm,
3149 ret = i915_gem_evict_something(vma->vm, size, alignment,
3159 GEM_BUG_ON(vma->node.start < start);
3160 GEM_BUG_ON(vma->node.start + vma->node.size > end);
3162 GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level));
3164 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3165 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3171 i915_gem_object_unpin_pages(obj);
3176 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3179 /* If we don't have a page list set up, then we're not pinned
3180 * to GPU, and we can ignore the cache flush because it'll happen
3181 * again at bind time.
3187 * Stolen memory is always coherent with the GPU as it is explicitly
3188 * marked as wc by the system, or the system is cache-coherent.
3190 if (obj->stolen || obj->phys_handle)
3193 /* If the GPU is snooping the contents of the CPU cache,
3194 * we do not need to manually clear the CPU cache lines. However,
3195 * the caches are only snooped when the render cache is
3196 * flushed/invalidated. As we always have to emit invalidations
3197 * and flushes when moving into and out of the RENDER domain, correct
3198 * snooping behaviour occurs naturally as the result of our domain
3201 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3202 obj->cache_dirty = true;
3206 trace_i915_gem_object_clflush(obj);
3207 drm_clflush_sg(obj->mm.pages);
3208 obj->cache_dirty = false;
3213 /** Flushes the GTT write domain for the object if it's dirty. */
3215 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3217 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3219 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3222 /* No actual flushing is required for the GTT write domain. Writes
3223 * to it "immediately" go to main memory as far as we know, so there's
3224 * no chipset flush. It also doesn't land in render cache.
3226 * However, we do have to enforce the order so that all writes through
3227 * the GTT land before any writes to the device, such as updates to
3230 * We also have to wait a bit for the writes to land from the GTT.
3231 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3232 * timing. This issue has only been observed when switching quickly
3233 * between GTT writes and CPU reads from inside the kernel on recent hw,
3234 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3235 * system agents we cannot reproduce this behaviour).
3238 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3239 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3241 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3243 obj->base.write_domain = 0;
3244 trace_i915_gem_object_change_domain(obj,
3245 obj->base.read_domains,
3246 I915_GEM_DOMAIN_GTT);
3249 /** Flushes the CPU write domain for the object if it's dirty. */
3251 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3253 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3256 if (i915_gem_clflush_object(obj, obj->pin_display))
3257 i915_gem_chipset_flush(to_i915(obj->base.dev));
3259 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3261 obj->base.write_domain = 0;
3262 trace_i915_gem_object_change_domain(obj,
3263 obj->base.read_domains,
3264 I915_GEM_DOMAIN_CPU);
3268 * Moves a single object to the GTT read, and possibly write domain.
3269 * @obj: object to act on
3270 * @write: ask for write access or read only
3272 * This function returns when the move is complete, including waiting on
3276 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3278 uint32_t old_write_domain, old_read_domains;
3281 lockdep_assert_held(&obj->base.dev->struct_mutex);
3283 ret = i915_gem_object_wait(obj,
3284 I915_WAIT_INTERRUPTIBLE |
3286 (write ? I915_WAIT_ALL : 0),
3287 MAX_SCHEDULE_TIMEOUT,
3292 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3295 /* Flush and acquire obj->pages so that we are coherent through
3296 * direct access in memory with previous cached writes through
3297 * shmemfs and that our cache domain tracking remains valid.
3298 * For example, if the obj->filp was moved to swap without us
3299 * being notified and releasing the pages, we would mistakenly
3300 * continue to assume that the obj remained out of the CPU cached
3303 ret = i915_gem_object_pin_pages(obj);
3307 i915_gem_object_flush_cpu_write_domain(obj);
3309 /* Serialise direct access to this object with the barriers for
3310 * coherent writes from the GPU, by effectively invalidating the
3311 * GTT domain upon first access.
3313 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3316 old_write_domain = obj->base.write_domain;
3317 old_read_domains = obj->base.read_domains;
3319 /* It should now be out of any other write domains, and we can update
3320 * the domain values for our changes.
3322 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3323 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3325 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3326 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3327 obj->mm.dirty = true;
3330 trace_i915_gem_object_change_domain(obj,
3334 i915_gem_object_unpin_pages(obj);
3339 * Changes the cache-level of an object across all VMA.
3340 * @obj: object to act on
3341 * @cache_level: new cache level to set for the object
3343 * After this function returns, the object will be in the new cache-level
3344 * across all GTT and the contents of the backing storage will be coherent,
3345 * with respect to the new cache-level. In order to keep the backing storage
3346 * coherent for all users, we only allow a single cache level to be set
3347 * globally on the object and prevent it from being changed whilst the
3348 * hardware is reading from the object. That is if the object is currently
3349 * on the scanout it will be set to uncached (or equivalent display
3350 * cache coherency) and all non-MOCS GPU access will also be uncached so
3351 * that all direct access to the scanout remains coherent.
3353 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3354 enum i915_cache_level cache_level)
3356 struct i915_vma *vma;
3359 lockdep_assert_held(&obj->base.dev->struct_mutex);
3361 if (obj->cache_level == cache_level)
3364 /* Inspect the list of currently bound VMA and unbind any that would
3365 * be invalid given the new cache-level. This is principally to
3366 * catch the issue of the CS prefetch crossing page boundaries and
3367 * reading an invalid PTE on older architectures.
3370 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3371 if (!drm_mm_node_allocated(&vma->node))
3374 if (i915_vma_is_pinned(vma)) {
3375 DRM_DEBUG("can not change the cache level of pinned objects\n");
3379 if (i915_gem_valid_gtt_space(vma, cache_level))
3382 ret = i915_vma_unbind(vma);
3386 /* As unbinding may affect other elements in the
3387 * obj->vma_list (due to side-effects from retiring
3388 * an active vma), play safe and restart the iterator.
3393 /* We can reuse the existing drm_mm nodes but need to change the
3394 * cache-level on the PTE. We could simply unbind them all and
3395 * rebind with the correct cache-level on next use. However since
3396 * we already have a valid slot, dma mapping, pages etc, we may as
3397 * rewrite the PTE in the belief that doing so tramples upon less
3398 * state and so involves less work.
3400 if (obj->bind_count) {
3401 /* Before we change the PTE, the GPU must not be accessing it.
3402 * If we wait upon the object, we know that all the bound
3403 * VMA are no longer active.
3405 ret = i915_gem_object_wait(obj,
3406 I915_WAIT_INTERRUPTIBLE |
3409 MAX_SCHEDULE_TIMEOUT,
3414 if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {
3415 /* Access to snoopable pages through the GTT is
3416 * incoherent and on some machines causes a hard
3417 * lockup. Relinquish the CPU mmaping to force
3418 * userspace to refault in the pages and we can
3419 * then double check if the GTT mapping is still
3420 * valid for that pointer access.
3422 i915_gem_release_mmap(obj);
3424 /* As we no longer need a fence for GTT access,
3425 * we can relinquish it now (and so prevent having
3426 * to steal a fence from someone else on the next
3427 * fence request). Note GPU activity would have
3428 * dropped the fence as all snoopable access is
3429 * supposed to be linear.
3431 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3432 ret = i915_vma_put_fence(vma);
3437 /* We either have incoherent backing store and
3438 * so no GTT access or the architecture is fully
3439 * coherent. In such cases, existing GTT mmaps
3440 * ignore the cache bit in the PTE and we can
3441 * rewrite it without confusing the GPU or having
3442 * to force userspace to fault back in its mmaps.
3446 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3447 if (!drm_mm_node_allocated(&vma->node))
3450 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3456 list_for_each_entry(vma, &obj->vma_list, obj_link)
3457 vma->node.color = cache_level;
3458 obj->cache_level = cache_level;
3461 /* Flush the dirty CPU caches to the backing storage so that the
3462 * object is now coherent at its new cache level (with respect
3463 * to the access domain).
3465 if (obj->cache_dirty && cpu_write_needs_clflush(obj)) {
3466 if (i915_gem_clflush_object(obj, true))
3467 i915_gem_chipset_flush(to_i915(obj->base.dev));
3473 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3474 struct drm_file *file)
3476 struct drm_i915_gem_caching *args = data;
3477 struct drm_i915_gem_object *obj;
3481 obj = i915_gem_object_lookup_rcu(file, args->handle);
3487 switch (obj->cache_level) {
3488 case I915_CACHE_LLC:
3489 case I915_CACHE_L3_LLC:
3490 args->caching = I915_CACHING_CACHED;
3494 args->caching = I915_CACHING_DISPLAY;
3498 args->caching = I915_CACHING_NONE;
3506 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3507 struct drm_file *file)
3509 struct drm_i915_private *i915 = to_i915(dev);
3510 struct drm_i915_gem_caching *args = data;
3511 struct drm_i915_gem_object *obj;
3512 enum i915_cache_level level;
3515 switch (args->caching) {
3516 case I915_CACHING_NONE:
3517 level = I915_CACHE_NONE;
3519 case I915_CACHING_CACHED:
3521 * Due to a HW issue on BXT A stepping, GPU stores via a
3522 * snooped mapping may leave stale data in a corresponding CPU
3523 * cacheline, whereas normally such cachelines would get
3526 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3529 level = I915_CACHE_LLC;
3531 case I915_CACHING_DISPLAY:
3532 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3538 ret = i915_mutex_lock_interruptible(dev);
3542 obj = i915_gem_object_lookup(file, args->handle);
3548 ret = i915_gem_object_set_cache_level(obj, level);
3549 i915_gem_object_put(obj);
3551 mutex_unlock(&dev->struct_mutex);
3556 * Prepare buffer for display plane (scanout, cursors, etc).
3557 * Can be called from an uninterruptible phase (modesetting) and allows
3558 * any flushes to be pipelined (for pageflips).
3561 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3563 const struct i915_ggtt_view *view)
3565 struct i915_vma *vma;
3566 u32 old_read_domains, old_write_domain;
3569 lockdep_assert_held(&obj->base.dev->struct_mutex);
3571 /* Mark the pin_display early so that we account for the
3572 * display coherency whilst setting up the cache domains.
3576 /* The display engine is not coherent with the LLC cache on gen6. As
3577 * a result, we make sure that the pinning that is about to occur is
3578 * done with uncached PTEs. This is lowest common denominator for all
3581 * However for gen6+, we could do better by using the GFDT bit instead
3582 * of uncaching, which would allow us to flush all the LLC-cached data
3583 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3585 ret = i915_gem_object_set_cache_level(obj,
3586 HAS_WT(to_i915(obj->base.dev)) ?
3587 I915_CACHE_WT : I915_CACHE_NONE);
3590 goto err_unpin_display;
3593 /* As the user may map the buffer once pinned in the display plane
3594 * (e.g. libkms for the bootup splash), we have to ensure that we
3595 * always use map_and_fenceable for all scanout buffers. However,
3596 * it may simply be too big to fit into mappable, in which case
3597 * put it anyway and hope that userspace can cope (but always first
3598 * try to preserve the existing ABI).
3600 vma = ERR_PTR(-ENOSPC);
3601 if (view->type == I915_GGTT_VIEW_NORMAL)
3602 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3603 PIN_MAPPABLE | PIN_NONBLOCK);
3605 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0);
3607 goto err_unpin_display;
3609 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3611 i915_gem_object_flush_cpu_write_domain(obj);
3613 old_write_domain = obj->base.write_domain;
3614 old_read_domains = obj->base.read_domains;
3616 /* It should now be out of any other write domains, and we can update
3617 * the domain values for our changes.
3619 obj->base.write_domain = 0;
3620 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3622 trace_i915_gem_object_change_domain(obj,
3634 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3636 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3638 if (WARN_ON(vma->obj->pin_display == 0))
3641 if (--vma->obj->pin_display == 0)
3642 vma->display_alignment = 0;
3644 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3645 if (!i915_vma_is_active(vma))
3646 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3648 i915_vma_unpin(vma);
3652 * Moves a single object to the CPU read, and possibly write domain.
3653 * @obj: object to act on
3654 * @write: requesting write or read-only access
3656 * This function returns when the move is complete, including waiting on
3660 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3662 uint32_t old_write_domain, old_read_domains;
3665 lockdep_assert_held(&obj->base.dev->struct_mutex);
3667 ret = i915_gem_object_wait(obj,
3668 I915_WAIT_INTERRUPTIBLE |
3670 (write ? I915_WAIT_ALL : 0),
3671 MAX_SCHEDULE_TIMEOUT,
3676 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3679 i915_gem_object_flush_gtt_write_domain(obj);
3681 old_write_domain = obj->base.write_domain;
3682 old_read_domains = obj->base.read_domains;
3684 /* Flush the CPU cache if it's still invalid. */
3685 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3686 i915_gem_clflush_object(obj, false);
3688 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3691 /* It should now be out of any other write domains, and we can update
3692 * the domain values for our changes.
3694 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3696 /* If we're writing through the CPU, then the GPU read domains will
3697 * need to be invalidated at next use.
3700 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3701 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3704 trace_i915_gem_object_change_domain(obj,
3711 /* Throttle our rendering by waiting until the ring has completed our requests
3712 * emitted over 20 msec ago.
3714 * Note that if we were to use the current jiffies each time around the loop,
3715 * we wouldn't escape the function with any frames outstanding if the time to
3716 * render a frame was over 20ms.
3718 * This should get us reasonable parallelism between CPU and GPU but also
3719 * relatively low latency when blocking on a particular request to finish.
3722 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3724 struct drm_i915_private *dev_priv = to_i915(dev);
3725 struct drm_i915_file_private *file_priv = file->driver_priv;
3726 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3727 struct drm_i915_gem_request *request, *target = NULL;
3730 /* ABI: return -EIO if already wedged */
3731 if (i915_terminally_wedged(&dev_priv->gpu_error))
3734 spin_lock(&file_priv->mm.lock);
3735 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3736 if (time_after_eq(request->emitted_jiffies, recent_enough))
3740 * Note that the request might not have been submitted yet.
3741 * In which case emitted_jiffies will be zero.
3743 if (!request->emitted_jiffies)
3749 i915_gem_request_get(target);
3750 spin_unlock(&file_priv->mm.lock);
3755 ret = i915_wait_request(target,
3756 I915_WAIT_INTERRUPTIBLE,
3757 MAX_SCHEDULE_TIMEOUT);
3758 i915_gem_request_put(target);
3760 return ret < 0 ? ret : 0;
3764 i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
3766 if (!drm_mm_node_allocated(&vma->node))
3769 if (vma->node.size < size)
3772 if (alignment && vma->node.start & (alignment - 1))
3775 if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
3778 if (flags & PIN_OFFSET_BIAS &&
3779 vma->node.start < (flags & PIN_OFFSET_MASK))
3782 if (flags & PIN_OFFSET_FIXED &&
3783 vma->node.start != (flags & PIN_OFFSET_MASK))
3789 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
3791 struct drm_i915_gem_object *obj = vma->obj;
3792 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3793 bool mappable, fenceable;
3794 u32 fence_size, fence_alignment;
3796 fence_size = i915_gem_get_ggtt_size(dev_priv,
3798 i915_gem_object_get_tiling(obj));
3799 fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
3801 i915_gem_object_get_tiling(obj),
3804 fenceable = (vma->node.size == fence_size &&
3805 (vma->node.start & (fence_alignment - 1)) == 0);
3807 mappable = (vma->node.start + fence_size <=
3808 dev_priv->ggtt.mappable_end);
3811 * Explicitly disable for rotated VMA since the display does not
3812 * need the fence and the VMA is not accessible to other users.
3814 if (mappable && fenceable &&
3815 vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED)
3816 vma->flags |= I915_VMA_CAN_FENCE;
3818 vma->flags &= ~I915_VMA_CAN_FENCE;
3821 int __i915_vma_do_pin(struct i915_vma *vma,
3822 u64 size, u64 alignment, u64 flags)
3824 unsigned int bound = vma->flags;
3827 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3828 GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0);
3829 GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma));
3831 if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) {
3836 if ((bound & I915_VMA_BIND_MASK) == 0) {
3837 ret = i915_vma_insert(vma, size, alignment, flags);
3842 ret = i915_vma_bind(vma, vma->obj->cache_level, flags);
3846 if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND)
3847 __i915_vma_set_map_and_fenceable(vma);
3849 GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags));
3853 __i915_vma_unpin(vma);
3858 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3859 const struct i915_ggtt_view *view,
3864 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3865 struct i915_address_space *vm = &dev_priv->ggtt.base;
3866 struct i915_vma *vma;
3869 lockdep_assert_held(&obj->base.dev->struct_mutex);
3871 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view);
3875 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3876 if (flags & PIN_NONBLOCK &&
3877 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3878 return ERR_PTR(-ENOSPC);
3880 if (flags & PIN_MAPPABLE) {
3883 fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
3884 i915_gem_object_get_tiling(obj));
3885 /* If the required space is larger than the available
3886 * aperture, we will not able to find a slot for the
3887 * object and unbinding the object now will be in
3888 * vain. Worse, doing so may cause us to ping-pong
3889 * the object in and out of the Global GTT and
3890 * waste a lot of cycles under the mutex.
3892 if (fence_size > dev_priv->ggtt.mappable_end)
3893 return ERR_PTR(-E2BIG);
3895 /* If NONBLOCK is set the caller is optimistically
3896 * trying to cache the full object within the mappable
3897 * aperture, and *must* have a fallback in place for
3898 * situations where we cannot bind the object. We
3899 * can be a little more lax here and use the fallback
3900 * more often to avoid costly migrations of ourselves
3901 * and other objects within the aperture.
3903 * Half-the-aperture is used as a simple heuristic.
3904 * More interesting would to do search for a free
3905 * block prior to making the commitment to unbind.
3906 * That caters for the self-harm case, and with a
3907 * little more heuristics (e.g. NOFAULT, NOEVICT)
3908 * we could try to minimise harm to others.
3910 if (flags & PIN_NONBLOCK &&
3911 fence_size > dev_priv->ggtt.mappable_end / 2)
3912 return ERR_PTR(-ENOSPC);
3915 WARN(i915_vma_is_pinned(vma),
3916 "bo is already pinned in ggtt with incorrect alignment:"
3917 " offset=%08x, req.alignment=%llx,"
3918 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3919 i915_ggtt_offset(vma), alignment,
3920 !!(flags & PIN_MAPPABLE),
3921 i915_vma_is_map_and_fenceable(vma));
3922 ret = i915_vma_unbind(vma);
3924 return ERR_PTR(ret);
3927 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3929 return ERR_PTR(ret);
3934 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3936 /* Note that we could alias engines in the execbuf API, but
3937 * that would be very unwise as it prevents userspace from
3938 * fine control over engine selection. Ahem.
3940 * This should be something like EXEC_MAX_ENGINE instead of
3943 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3944 return 0x10000 << id;
3947 static __always_inline unsigned int __busy_write_id(unsigned int id)
3949 /* The uABI guarantees an active writer is also amongst the read
3950 * engines. This would be true if we accessed the activity tracking
3951 * under the lock, but as we perform the lookup of the object and
3952 * its activity locklessly we can not guarantee that the last_write
3953 * being active implies that we have set the same engine flag from
3954 * last_read - hence we always set both read and write busy for
3957 return id | __busy_read_flag(id);
3960 static __always_inline unsigned int
3961 __busy_set_if_active(const struct dma_fence *fence,
3962 unsigned int (*flag)(unsigned int id))
3964 struct drm_i915_gem_request *rq;
3966 /* We have to check the current hw status of the fence as the uABI
3967 * guarantees forward progress. We could rely on the idle worker
3968 * to eventually flush us, but to minimise latency just ask the
3971 * Note we only report on the status of native fences.
3973 if (!dma_fence_is_i915(fence))
3976 /* opencode to_request() in order to avoid const warnings */
3977 rq = container_of(fence, struct drm_i915_gem_request, fence);
3978 if (i915_gem_request_completed(rq))
3981 return flag(rq->engine->exec_id);
3984 static __always_inline unsigned int
3985 busy_check_reader(const struct dma_fence *fence)
3987 return __busy_set_if_active(fence, __busy_read_flag);
3990 static __always_inline unsigned int
3991 busy_check_writer(const struct dma_fence *fence)
3996 return __busy_set_if_active(fence, __busy_write_id);
4000 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4001 struct drm_file *file)
4003 struct drm_i915_gem_busy *args = data;
4004 struct drm_i915_gem_object *obj;
4005 struct reservation_object_list *list;
4011 obj = i915_gem_object_lookup_rcu(file, args->handle);
4015 /* A discrepancy here is that we do not report the status of
4016 * non-i915 fences, i.e. even though we may report the object as idle,
4017 * a call to set-domain may still stall waiting for foreign rendering.
4018 * This also means that wait-ioctl may report an object as busy,
4019 * where busy-ioctl considers it idle.
4021 * We trade the ability to warn of foreign fences to report on which
4022 * i915 engines are active for the object.
4024 * Alternatively, we can trade that extra information on read/write
4027 * !reservation_object_test_signaled_rcu(obj->resv, true);
4028 * to report the overall busyness. This is what the wait-ioctl does.
4032 seq = raw_read_seqcount(&obj->resv->seq);
4034 /* Translate the exclusive fence to the READ *and* WRITE engine */
4035 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4037 /* Translate shared fences to READ set of engines */
4038 list = rcu_dereference(obj->resv->fence);
4040 unsigned int shared_count = list->shared_count, i;
4042 for (i = 0; i < shared_count; ++i) {
4043 struct dma_fence *fence =
4044 rcu_dereference(list->shared[i]);
4046 args->busy |= busy_check_reader(fence);
4050 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4060 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4061 struct drm_file *file_priv)
4063 return i915_gem_ring_throttle(dev, file_priv);
4067 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4068 struct drm_file *file_priv)
4070 struct drm_i915_private *dev_priv = to_i915(dev);
4071 struct drm_i915_gem_madvise *args = data;
4072 struct drm_i915_gem_object *obj;
4075 switch (args->madv) {
4076 case I915_MADV_DONTNEED:
4077 case I915_MADV_WILLNEED:
4083 obj = i915_gem_object_lookup(file_priv, args->handle);
4087 err = mutex_lock_interruptible(&obj->mm.lock);
4091 if (obj->mm.pages &&
4092 i915_gem_object_is_tiled(obj) &&
4093 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4094 if (obj->mm.madv == I915_MADV_WILLNEED)
4095 __i915_gem_object_unpin_pages(obj);
4096 if (args->madv == I915_MADV_WILLNEED)
4097 __i915_gem_object_pin_pages(obj);
4100 if (obj->mm.madv != __I915_MADV_PURGED)
4101 obj->mm.madv = args->madv;
4103 /* if the object is no longer attached, discard its backing storage */
4104 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4105 i915_gem_object_truncate(obj);
4107 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4108 mutex_unlock(&obj->mm.lock);
4111 i915_gem_object_put(obj);
4115 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4116 const struct drm_i915_gem_object_ops *ops)
4118 mutex_init(&obj->mm.lock);
4120 INIT_LIST_HEAD(&obj->global_list);
4121 INIT_LIST_HEAD(&obj->userfault_link);
4122 INIT_LIST_HEAD(&obj->obj_exec_link);
4123 INIT_LIST_HEAD(&obj->vma_list);
4124 INIT_LIST_HEAD(&obj->batch_pool_link);
4128 reservation_object_init(&obj->__builtin_resv);
4129 obj->resv = &obj->__builtin_resv;
4131 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4133 obj->mm.madv = I915_MADV_WILLNEED;
4134 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4135 mutex_init(&obj->mm.get_page.lock);
4137 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4140 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4141 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4142 .get_pages = i915_gem_object_get_pages_gtt,
4143 .put_pages = i915_gem_object_put_pages_gtt,
4146 /* Note we don't consider signbits :| */
4147 #define overflows_type(x, T) \
4148 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
4150 struct drm_i915_gem_object *
4151 i915_gem_object_create(struct drm_device *dev, u64 size)
4153 struct drm_i915_gem_object *obj;
4154 struct address_space *mapping;
4158 /* There is a prevalence of the assumption that we fit the object's
4159 * page count inside a 32bit _signed_ variable. Let's document this and
4160 * catch if we ever need to fix it. In the meantime, if you do spot
4161 * such a local variable, please consider fixing!
4163 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
4164 return ERR_PTR(-E2BIG);
4166 if (overflows_type(size, obj->base.size))
4167 return ERR_PTR(-E2BIG);
4169 obj = i915_gem_object_alloc(dev);
4171 return ERR_PTR(-ENOMEM);
4173 ret = drm_gem_object_init(dev, &obj->base, size);
4177 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4178 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4179 /* 965gm cannot relocate objects above 4GiB. */
4180 mask &= ~__GFP_HIGHMEM;
4181 mask |= __GFP_DMA32;
4184 mapping = obj->base.filp->f_mapping;
4185 mapping_set_gfp_mask(mapping, mask);
4187 i915_gem_object_init(obj, &i915_gem_object_ops);
4189 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4190 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4193 /* On some devices, we can have the GPU use the LLC (the CPU
4194 * cache) for about a 10% performance improvement
4195 * compared to uncached. Graphics requests other than
4196 * display scanout are coherent with the CPU in
4197 * accessing this cache. This means in this mode we
4198 * don't need to clflush on the CPU side, and on the
4199 * GPU side we only need to flush internal caches to
4200 * get data visible to the CPU.
4202 * However, we maintain the display planes as UC, and so
4203 * need to rebind when first used as such.
4205 obj->cache_level = I915_CACHE_LLC;
4207 obj->cache_level = I915_CACHE_NONE;
4209 trace_i915_gem_object_create(obj);
4214 i915_gem_object_free(obj);
4215 return ERR_PTR(ret);
4218 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4220 /* If we are the last user of the backing storage (be it shmemfs
4221 * pages or stolen etc), we know that the pages are going to be
4222 * immediately released. In this case, we can then skip copying
4223 * back the contents from the GPU.
4226 if (obj->mm.madv != I915_MADV_WILLNEED)
4229 if (obj->base.filp == NULL)
4232 /* At first glance, this looks racy, but then again so would be
4233 * userspace racing mmap against close. However, the first external
4234 * reference to the filp can only be obtained through the
4235 * i915_gem_mmap_ioctl() which safeguards us against the user
4236 * acquiring such a reference whilst we are in the middle of
4237 * freeing the object.
4239 return atomic_long_read(&obj->base.filp->f_count) == 1;
4242 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4243 struct llist_node *freed)
4245 struct drm_i915_gem_object *obj, *on;
4247 mutex_lock(&i915->drm.struct_mutex);
4248 intel_runtime_pm_get(i915);
4249 llist_for_each_entry(obj, freed, freed) {
4250 struct i915_vma *vma, *vn;
4252 trace_i915_gem_object_destroy(obj);
4254 GEM_BUG_ON(i915_gem_object_is_active(obj));
4255 list_for_each_entry_safe(vma, vn,
4256 &obj->vma_list, obj_link) {
4257 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4258 GEM_BUG_ON(i915_vma_is_active(vma));
4259 vma->flags &= ~I915_VMA_PIN_MASK;
4260 i915_vma_close(vma);
4263 list_del(&obj->global_list);
4265 intel_runtime_pm_put(i915);
4266 mutex_unlock(&i915->drm.struct_mutex);
4268 llist_for_each_entry_safe(obj, on, freed, freed) {
4269 GEM_BUG_ON(obj->bind_count);
4270 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4272 if (obj->ops->release)
4273 obj->ops->release(obj);
4275 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4276 atomic_set(&obj->mm.pages_pin_count, 0);
4277 __i915_gem_object_put_pages(obj);
4278 GEM_BUG_ON(obj->mm.pages);
4280 if (obj->base.import_attach)
4281 drm_prime_gem_destroy(&obj->base, NULL);
4283 reservation_object_fini(&obj->__builtin_resv);
4284 drm_gem_object_release(&obj->base);
4285 i915_gem_info_remove_obj(i915, obj->base.size);
4288 i915_gem_object_free(obj);
4292 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4294 struct llist_node *freed;
4296 freed = llist_del_all(&i915->mm.free_list);
4297 if (unlikely(freed))
4298 __i915_gem_free_objects(i915, freed);
4301 static void __i915_gem_free_work(struct work_struct *work)
4303 struct drm_i915_private *i915 =
4304 container_of(work, struct drm_i915_private, mm.free_work);
4305 struct llist_node *freed;
4307 /* All file-owned VMA should have been released by this point through
4308 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4309 * However, the object may also be bound into the global GTT (e.g.
4310 * older GPUs without per-process support, or for direct access through
4311 * the GTT either for the user or for scanout). Those VMA still need to
4315 while ((freed = llist_del_all(&i915->mm.free_list)))
4316 __i915_gem_free_objects(i915, freed);
4319 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4321 struct drm_i915_gem_object *obj =
4322 container_of(head, typeof(*obj), rcu);
4323 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4325 /* We can't simply use call_rcu() from i915_gem_free_object()
4326 * as we need to block whilst unbinding, and the call_rcu
4327 * task may be called from softirq context. So we take a
4328 * detour through a worker.
4330 if (llist_add(&obj->freed, &i915->mm.free_list))
4331 schedule_work(&i915->mm.free_work);
4334 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4336 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4338 if (discard_backing_storage(obj))
4339 obj->mm.madv = I915_MADV_DONTNEED;
4341 if (obj->mm.pages && obj->mm.madv == I915_MADV_WILLNEED &&
4342 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4343 i915_gem_object_is_tiled(obj))
4344 __i915_gem_object_unpin_pages(obj);
4346 /* Before we free the object, make sure any pure RCU-only
4347 * read-side critical sections are complete, e.g.
4348 * i915_gem_busy_ioctl(). For the corresponding synchronized
4349 * lookup see i915_gem_object_lookup_rcu().
4351 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4354 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4356 lockdep_assert_held(&obj->base.dev->struct_mutex);
4358 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4359 if (i915_gem_object_is_active(obj))
4360 i915_gem_object_set_active_reference(obj);
4362 i915_gem_object_put(obj);
4365 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4367 struct intel_engine_cs *engine;
4368 enum intel_engine_id id;
4370 for_each_engine(engine, dev_priv, id)
4371 GEM_BUG_ON(engine->last_context != dev_priv->kernel_context);
4374 int i915_gem_suspend(struct drm_device *dev)
4376 struct drm_i915_private *dev_priv = to_i915(dev);
4379 intel_suspend_gt_powersave(dev_priv);
4381 mutex_lock(&dev->struct_mutex);
4383 /* We have to flush all the executing contexts to main memory so
4384 * that they can saved in the hibernation image. To ensure the last
4385 * context image is coherent, we have to switch away from it. That
4386 * leaves the dev_priv->kernel_context still active when
4387 * we actually suspend, and its image in memory may not match the GPU
4388 * state. Fortunately, the kernel_context is disposable and we do
4389 * not rely on its state.
4391 ret = i915_gem_switch_to_kernel_context(dev_priv);
4395 ret = i915_gem_wait_for_idle(dev_priv,
4396 I915_WAIT_INTERRUPTIBLE |
4401 i915_gem_retire_requests(dev_priv);
4402 GEM_BUG_ON(dev_priv->gt.active_requests);
4404 assert_kernel_context_is_current(dev_priv);
4405 i915_gem_context_lost(dev_priv);
4406 mutex_unlock(&dev->struct_mutex);
4408 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4409 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4410 flush_delayed_work(&dev_priv->gt.idle_work);
4411 flush_work(&dev_priv->mm.free_work);
4413 /* Assert that we sucessfully flushed all the work and
4414 * reset the GPU back to its idle, low power state.
4416 WARN_ON(dev_priv->gt.awake);
4419 * Neither the BIOS, ourselves or any other kernel
4420 * expects the system to be in execlists mode on startup,
4421 * so we need to reset the GPU back to legacy mode. And the only
4422 * known way to disable logical contexts is through a GPU reset.
4424 * So in order to leave the system in a known default configuration,
4425 * always reset the GPU upon unload and suspend. Afterwards we then
4426 * clean up the GEM state tracking, flushing off the requests and
4427 * leaving the system in a known idle state.
4429 * Note that is of the upmost importance that the GPU is idle and
4430 * all stray writes are flushed *before* we dismantle the backing
4431 * storage for the pinned objects.
4433 * However, since we are uncertain that resetting the GPU on older
4434 * machines is a good idea, we don't - just in case it leaves the
4435 * machine in an unusable condition.
4437 if (HAS_HW_CONTEXTS(dev)) {
4438 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
4439 WARN_ON(reset && reset != -ENODEV);
4445 mutex_unlock(&dev->struct_mutex);
4449 void i915_gem_resume(struct drm_device *dev)
4451 struct drm_i915_private *dev_priv = to_i915(dev);
4453 mutex_lock(&dev->struct_mutex);
4454 i915_gem_restore_gtt_mappings(dev);
4456 /* As we didn't flush the kernel context before suspend, we cannot
4457 * guarantee that the context image is complete. So let's just reset
4458 * it and start again.
4460 dev_priv->gt.resume(dev_priv);
4462 mutex_unlock(&dev->struct_mutex);
4465 void i915_gem_init_swizzling(struct drm_device *dev)
4467 struct drm_i915_private *dev_priv = to_i915(dev);
4469 if (INTEL_INFO(dev)->gen < 5 ||
4470 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4473 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4474 DISP_TILE_SURFACE_SWIZZLING);
4476 if (IS_GEN5(dev_priv))
4479 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4480 if (IS_GEN6(dev_priv))
4481 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4482 else if (IS_GEN7(dev_priv))
4483 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4484 else if (IS_GEN8(dev_priv))
4485 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4490 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4492 I915_WRITE(RING_CTL(base), 0);
4493 I915_WRITE(RING_HEAD(base), 0);
4494 I915_WRITE(RING_TAIL(base), 0);
4495 I915_WRITE(RING_START(base), 0);
4498 static void init_unused_rings(struct drm_i915_private *dev_priv)
4500 if (IS_I830(dev_priv)) {
4501 init_unused_ring(dev_priv, PRB1_BASE);
4502 init_unused_ring(dev_priv, SRB0_BASE);
4503 init_unused_ring(dev_priv, SRB1_BASE);
4504 init_unused_ring(dev_priv, SRB2_BASE);
4505 init_unused_ring(dev_priv, SRB3_BASE);
4506 } else if (IS_GEN2(dev_priv)) {
4507 init_unused_ring(dev_priv, SRB0_BASE);
4508 init_unused_ring(dev_priv, SRB1_BASE);
4509 } else if (IS_GEN3(dev_priv)) {
4510 init_unused_ring(dev_priv, PRB1_BASE);
4511 init_unused_ring(dev_priv, PRB2_BASE);
4516 i915_gem_init_hw(struct drm_device *dev)
4518 struct drm_i915_private *dev_priv = to_i915(dev);
4519 struct intel_engine_cs *engine;
4520 enum intel_engine_id id;
4523 dev_priv->gt.last_init_time = ktime_get();
4525 /* Double layer security blanket, see i915_gem_init() */
4526 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4528 if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
4529 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4531 if (IS_HASWELL(dev_priv))
4532 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4533 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4535 if (HAS_PCH_NOP(dev_priv)) {
4536 if (IS_IVYBRIDGE(dev_priv)) {
4537 u32 temp = I915_READ(GEN7_MSG_CTL);
4538 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4539 I915_WRITE(GEN7_MSG_CTL, temp);
4540 } else if (INTEL_INFO(dev)->gen >= 7) {
4541 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4542 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4543 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4547 i915_gem_init_swizzling(dev);
4550 * At least 830 can leave some of the unused rings
4551 * "active" (ie. head != tail) after resume which
4552 * will prevent c3 entry. Makes sure all unused rings
4555 init_unused_rings(dev_priv);
4557 BUG_ON(!dev_priv->kernel_context);
4559 ret = i915_ppgtt_init_hw(dev);
4561 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4565 /* Need to do basic initialisation of all rings first: */
4566 for_each_engine(engine, dev_priv, id) {
4567 ret = engine->init_hw(engine);
4572 intel_mocs_init_l3cc_table(dev);
4574 /* We can't enable contexts until all firmware is loaded */
4575 ret = intel_guc_setup(dev);
4580 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4584 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4586 if (INTEL_INFO(dev_priv)->gen < 6)
4589 /* TODO: make semaphores and Execlists play nicely together */
4590 if (i915.enable_execlists)
4596 #ifdef CONFIG_INTEL_IOMMU
4597 /* Enable semaphores on SNB when IO remapping is off */
4598 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4605 int i915_gem_init(struct drm_device *dev)
4607 struct drm_i915_private *dev_priv = to_i915(dev);
4610 mutex_lock(&dev->struct_mutex);
4612 if (!i915.enable_execlists) {
4613 dev_priv->gt.resume = intel_legacy_submission_resume;
4614 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4616 dev_priv->gt.resume = intel_lr_context_resume;
4617 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4620 /* This is just a security blanket to placate dragons.
4621 * On some systems, we very sporadically observe that the first TLBs
4622 * used by the CS may be stale, despite us poking the TLB reset. If
4623 * we hold the forcewake during initialisation these problems
4624 * just magically go away.
4626 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4628 i915_gem_init_userptr(dev_priv);
4630 ret = i915_gem_init_ggtt(dev_priv);
4634 ret = i915_gem_context_init(dev);
4638 ret = intel_engines_init(dev);
4642 ret = i915_gem_init_hw(dev);
4644 /* Allow engine initialisation to fail by marking the GPU as
4645 * wedged. But we only want to do this where the GPU is angry,
4646 * for all other failure, such as an allocation failure, bail.
4648 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4649 i915_gem_set_wedged(dev_priv);
4654 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4655 mutex_unlock(&dev->struct_mutex);
4661 i915_gem_cleanup_engines(struct drm_device *dev)
4663 struct drm_i915_private *dev_priv = to_i915(dev);
4664 struct intel_engine_cs *engine;
4665 enum intel_engine_id id;
4667 for_each_engine(engine, dev_priv, id)
4668 dev_priv->gt.cleanup_engine(engine);
4672 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4674 struct drm_device *dev = &dev_priv->drm;
4677 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4678 !IS_CHERRYVIEW(dev_priv))
4679 dev_priv->num_fence_regs = 32;
4680 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4681 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4682 dev_priv->num_fence_regs = 16;
4684 dev_priv->num_fence_regs = 8;
4686 if (intel_vgpu_active(dev_priv))
4687 dev_priv->num_fence_regs =
4688 I915_READ(vgtif_reg(avail_rs.fence_num));
4690 /* Initialize fence registers to zero */
4691 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4692 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4694 fence->i915 = dev_priv;
4696 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4698 i915_gem_restore_fences(dev);
4700 i915_gem_detect_bit_6_swizzle(dev);
4704 i915_gem_load_init(struct drm_device *dev)
4706 struct drm_i915_private *dev_priv = to_i915(dev);
4710 kmem_cache_create("i915_gem_object",
4711 sizeof(struct drm_i915_gem_object), 0,
4714 if (!dev_priv->objects) {
4720 kmem_cache_create("i915_gem_vma",
4721 sizeof(struct i915_vma), 0,
4724 if (!dev_priv->vmas) {
4729 dev_priv->requests =
4730 kmem_cache_create("i915_gem_request",
4731 sizeof(struct drm_i915_gem_request), 0,
4732 SLAB_HWCACHE_ALIGN |
4733 SLAB_RECLAIM_ACCOUNT |
4734 SLAB_DESTROY_BY_RCU,
4736 if (!dev_priv->requests) {
4741 mutex_lock(&dev_priv->drm.struct_mutex);
4742 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4743 err = i915_gem_timeline_init(dev_priv,
4744 &dev_priv->gt.global_timeline,
4746 mutex_unlock(&dev_priv->drm.struct_mutex);
4750 INIT_LIST_HEAD(&dev_priv->context_list);
4751 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4752 init_llist_head(&dev_priv->mm.free_list);
4753 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4754 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4755 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4756 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4757 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4758 i915_gem_retire_work_handler);
4759 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4760 i915_gem_idle_work_handler);
4761 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4762 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4764 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4766 init_waitqueue_head(&dev_priv->pending_flip_queue);
4768 dev_priv->mm.interruptible = true;
4770 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4772 spin_lock_init(&dev_priv->fb_tracking.lock);
4777 kmem_cache_destroy(dev_priv->requests);
4779 kmem_cache_destroy(dev_priv->vmas);
4781 kmem_cache_destroy(dev_priv->objects);
4786 void i915_gem_load_cleanup(struct drm_device *dev)
4788 struct drm_i915_private *dev_priv = to_i915(dev);
4790 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4792 kmem_cache_destroy(dev_priv->requests);
4793 kmem_cache_destroy(dev_priv->vmas);
4794 kmem_cache_destroy(dev_priv->objects);
4796 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4800 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4802 intel_runtime_pm_get(dev_priv);
4804 mutex_lock(&dev_priv->drm.struct_mutex);
4805 i915_gem_shrink_all(dev_priv);
4806 mutex_unlock(&dev_priv->drm.struct_mutex);
4808 intel_runtime_pm_put(dev_priv);
4813 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4815 struct drm_i915_gem_object *obj;
4816 struct list_head *phases[] = {
4817 &dev_priv->mm.unbound_list,
4818 &dev_priv->mm.bound_list,
4822 /* Called just before we write the hibernation image.
4824 * We need to update the domain tracking to reflect that the CPU
4825 * will be accessing all the pages to create and restore from the
4826 * hibernation, and so upon restoration those pages will be in the
4829 * To make sure the hibernation image contains the latest state,
4830 * we update that state just before writing out the image.
4832 * To try and reduce the hibernation image, we manually shrink
4833 * the objects as well.
4836 mutex_lock(&dev_priv->drm.struct_mutex);
4837 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4839 for (p = phases; *p; p++) {
4840 list_for_each_entry(obj, *p, global_list) {
4841 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4842 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4845 mutex_unlock(&dev_priv->drm.struct_mutex);
4850 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4852 struct drm_i915_file_private *file_priv = file->driver_priv;
4853 struct drm_i915_gem_request *request;
4855 /* Clean up our request list when the client is going away, so that
4856 * later retire_requests won't dereference our soon-to-be-gone
4859 spin_lock(&file_priv->mm.lock);
4860 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4861 request->file_priv = NULL;
4862 spin_unlock(&file_priv->mm.lock);
4864 if (!list_empty(&file_priv->rps.link)) {
4865 spin_lock(&to_i915(dev)->rps.client_lock);
4866 list_del(&file_priv->rps.link);
4867 spin_unlock(&to_i915(dev)->rps.client_lock);
4871 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4873 struct drm_i915_file_private *file_priv;
4876 DRM_DEBUG_DRIVER("\n");
4878 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4882 file->driver_priv = file_priv;
4883 file_priv->dev_priv = to_i915(dev);
4884 file_priv->file = file;
4885 INIT_LIST_HEAD(&file_priv->rps.link);
4887 spin_lock_init(&file_priv->mm.lock);
4888 INIT_LIST_HEAD(&file_priv->mm.request_list);
4890 file_priv->bsd_engine = -1;
4892 ret = i915_gem_context_open(dev, file);
4900 * i915_gem_track_fb - update frontbuffer tracking
4901 * @old: current GEM buffer for the frontbuffer slots
4902 * @new: new GEM buffer for the frontbuffer slots
4903 * @frontbuffer_bits: bitmask of frontbuffer slots
4905 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4906 * from @old and setting them in @new. Both @old and @new can be NULL.
4908 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4909 struct drm_i915_gem_object *new,
4910 unsigned frontbuffer_bits)
4912 /* Control of individual bits within the mask are guarded by
4913 * the owning plane->mutex, i.e. we can never see concurrent
4914 * manipulation of individual bits. But since the bitfield as a whole
4915 * is updated using RMW, we need to use atomics in order to update
4918 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4919 sizeof(atomic_t) * BITS_PER_BYTE);
4922 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4923 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4927 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4928 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4932 /* Allocate a new GEM object and fill it with the supplied data */
4933 struct drm_i915_gem_object *
4934 i915_gem_object_create_from_data(struct drm_device *dev,
4935 const void *data, size_t size)
4937 struct drm_i915_gem_object *obj;
4938 struct sg_table *sg;
4942 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4946 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4950 ret = i915_gem_object_pin_pages(obj);
4955 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4956 obj->mm.dirty = true; /* Backing store is now out of date */
4957 i915_gem_object_unpin_pages(obj);
4959 if (WARN_ON(bytes != size)) {
4960 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4968 i915_gem_object_put(obj);
4969 return ERR_PTR(ret);
4972 struct scatterlist *
4973 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4975 unsigned int *offset)
4977 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4978 struct scatterlist *sg;
4979 unsigned int idx, count;
4982 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4983 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4985 /* As we iterate forward through the sg, we record each entry in a
4986 * radixtree for quick repeated (backwards) lookups. If we have seen
4987 * this index previously, we will have an entry for it.
4989 * Initial lookup is O(N), but this is amortized to O(1) for
4990 * sequential page access (where each new request is consecutive
4991 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4992 * i.e. O(1) with a large constant!
4994 if (n < READ_ONCE(iter->sg_idx))
4997 mutex_lock(&iter->lock);
4999 /* We prefer to reuse the last sg so that repeated lookup of this
5000 * (or the subsequent) sg are fast - comparing against the last
5001 * sg is faster than going through the radixtree.
5006 count = __sg_page_count(sg);
5008 while (idx + count <= n) {
5009 unsigned long exception, i;
5012 /* If we cannot allocate and insert this entry, or the
5013 * individual pages from this range, cancel updating the
5014 * sg_idx so that on this lookup we are forced to linearly
5015 * scan onwards, but on future lookups we will try the
5016 * insertion again (in which case we need to be careful of
5017 * the error return reporting that we have already inserted
5020 ret = radix_tree_insert(&iter->radix, idx, sg);
5021 if (ret && ret != -EEXIST)
5025 RADIX_TREE_EXCEPTIONAL_ENTRY |
5026 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5027 for (i = 1; i < count; i++) {
5028 ret = radix_tree_insert(&iter->radix, idx + i,
5030 if (ret && ret != -EEXIST)
5035 sg = ____sg_next(sg);
5036 count = __sg_page_count(sg);
5043 mutex_unlock(&iter->lock);
5045 if (unlikely(n < idx)) /* insertion completed by another thread */
5048 /* In case we failed to insert the entry into the radixtree, we need
5049 * to look beyond the current sg.
5051 while (idx + count <= n) {
5053 sg = ____sg_next(sg);
5054 count = __sg_page_count(sg);
5063 sg = radix_tree_lookup(&iter->radix, n);
5066 /* If this index is in the middle of multi-page sg entry,
5067 * the radixtree will contain an exceptional entry that points
5068 * to the start of that range. We will return the pointer to
5069 * the base page and the offset of this page within the
5073 if (unlikely(radix_tree_exception(sg))) {
5074 unsigned long base =
5075 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5077 sg = radix_tree_lookup(&iter->radix, base);
5089 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5091 struct scatterlist *sg;
5092 unsigned int offset;
5094 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5096 sg = i915_gem_object_get_sg(obj, n, &offset);
5097 return nth_page(sg_page(sg), offset);
5100 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5102 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5107 page = i915_gem_object_get_page(obj, n);
5109 set_page_dirty(page);
5115 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5118 struct scatterlist *sg;
5119 unsigned int offset;
5121 sg = i915_gem_object_get_sg(obj, n, &offset);
5122 return sg_dma_address(sg) + (offset << PAGE_SHIFT);