2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
45 bool map_and_fenceable);
46 static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
51 static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
57 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
61 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
64 i915_gem_release_mmap(obj);
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
69 obj->fence_dirty = false;
70 obj->fence_reg = I915_FENCE_REG_NONE;
73 /* some bookkeeping */
74 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
77 dev_priv->mm.object_count++;
78 dev_priv->mm.object_memory += size;
81 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
84 dev_priv->mm.object_count--;
85 dev_priv->mm.object_memory -= size;
89 i915_gem_wait_for_error(struct drm_device *dev)
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 struct completion *x = &dev_priv->error_completion;
96 if (!atomic_read(&dev_priv->mm.wedged))
99 ret = wait_for_completion_interruptible(x);
103 if (atomic_read(&dev_priv->mm.wedged)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
109 spin_lock_irqsave(&x->wait.lock, flags);
111 spin_unlock_irqrestore(&x->wait.lock, flags);
116 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 ret = i915_gem_wait_for_error(dev);
124 ret = mutex_lock_interruptible(&dev->struct_mutex);
128 WARN_ON(i915_verify_lists(dev));
133 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
139 i915_gem_init_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_gem_init *args = data;
144 if (drm_core_check_feature(dev, DRIVER_MODESET))
147 if (args->gtt_start >= args->gtt_end ||
148 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
151 /* GEM with user mode setting was never supported on ilk and later. */
152 if (INTEL_INFO(dev)->gen >= 5)
155 mutex_lock(&dev->struct_mutex);
156 i915_gem_init_global_gtt(dev, args->gtt_start,
157 args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
164 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
173 mutex_lock(&dev->struct_mutex);
174 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
176 pinned += obj->gtt_space->size;
177 mutex_unlock(&dev->struct_mutex);
179 args->aper_size = dev_priv->mm.gtt_total;
180 args->aper_available_size = args->aper_size - pinned;
186 i915_gem_create(struct drm_file *file,
187 struct drm_device *dev,
191 struct drm_i915_gem_object *obj;
195 size = roundup(size, PAGE_SIZE);
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
221 i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
232 int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
236 return drm_gem_handle_delete(file, handle);
240 * Creates a new mm object and returns a handle to it.
243 i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
246 struct drm_i915_gem_create *args = data;
248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
252 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
257 obj->tiling_mode != I915_TILING_NONE;
261 __copy_to_user_swizzled(char __user *cpu_vaddr,
262 const char *gpu_vaddr, int gpu_offset,
265 int ret, cpu_offset = 0;
268 int cacheline_end = ALIGN(gpu_offset + 1, 64);
269 int this_length = min(cacheline_end - gpu_offset, length);
270 int swizzled_gpu_offset = gpu_offset ^ 64;
272 ret = __copy_to_user(cpu_vaddr + cpu_offset,
273 gpu_vaddr + swizzled_gpu_offset,
278 cpu_offset += this_length;
279 gpu_offset += this_length;
280 length -= this_length;
287 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
288 const char __user *cpu_vaddr,
291 int ret, cpu_offset = 0;
294 int cacheline_end = ALIGN(gpu_offset + 1, 64);
295 int this_length = min(cacheline_end - gpu_offset, length);
296 int swizzled_gpu_offset = gpu_offset ^ 64;
298 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
299 cpu_vaddr + cpu_offset,
304 cpu_offset += this_length;
305 gpu_offset += this_length;
306 length -= this_length;
312 /* Per-page copy function for the shmem pread fastpath.
313 * Flushes invalid cachelines before reading the target if
314 * needs_clflush is set. */
316 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
317 char __user *user_data,
318 bool page_do_bit17_swizzling, bool needs_clflush)
323 if (unlikely(page_do_bit17_swizzling))
326 vaddr = kmap_atomic(page);
328 drm_clflush_virt_range(vaddr + shmem_page_offset,
330 ret = __copy_to_user_inatomic(user_data,
331 vaddr + shmem_page_offset,
333 kunmap_atomic(vaddr);
339 shmem_clflush_swizzled_range(char *addr, unsigned long length,
342 if (unlikely(swizzled)) {
343 unsigned long start = (unsigned long) addr;
344 unsigned long end = (unsigned long) addr + length;
346 /* For swizzling simply ensure that we always flush both
347 * channels. Lame, but simple and it works. Swizzled
348 * pwrite/pread is far from a hotpath - current userspace
349 * doesn't use it at all. */
350 start = round_down(start, 128);
351 end = round_up(end, 128);
353 drm_clflush_virt_range((void *)start, end - start);
355 drm_clflush_virt_range(addr, length);
360 /* Only difference to the fast-path function is that this can handle bit17
361 * and uses non-atomic copy and kmap functions. */
363 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
364 char __user *user_data,
365 bool page_do_bit17_swizzling, bool needs_clflush)
372 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
374 page_do_bit17_swizzling);
376 if (page_do_bit17_swizzling)
377 ret = __copy_to_user_swizzled(user_data,
378 vaddr, shmem_page_offset,
381 ret = __copy_to_user(user_data,
382 vaddr + shmem_page_offset,
390 i915_gem_shmem_pread(struct drm_device *dev,
391 struct drm_i915_gem_object *obj,
392 struct drm_i915_gem_pread *args,
393 struct drm_file *file)
395 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
396 char __user *user_data;
399 int shmem_page_offset, page_length, ret = 0;
400 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
401 int hit_slowpath = 0;
403 int needs_clflush = 0;
406 user_data = (char __user *) (uintptr_t) args->data_ptr;
409 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
412 /* If we're not in the cpu read domain, set ourself into the gtt
413 * read domain and manually flush cachelines (if required). This
414 * optimizes for the case when the gpu will dirty the data
415 * anyway again before the next pread happens. */
416 if (obj->cache_level == I915_CACHE_NONE)
418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
423 offset = args->offset;
428 /* Operation in this page
430 * shmem_page_offset = offset within page in shmem file
431 * page_length = bytes to copy for this page
433 shmem_page_offset = offset_in_page(offset);
434 page_length = remain;
435 if ((shmem_page_offset + page_length) > PAGE_SIZE)
436 page_length = PAGE_SIZE - shmem_page_offset;
439 page = obj->pages[offset >> PAGE_SHIFT];
442 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
450 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
451 (page_to_phys(page) & (1 << 17)) != 0;
453 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
454 user_data, page_do_bit17_swizzling,
460 page_cache_get(page);
461 mutex_unlock(&dev->struct_mutex);
464 ret = fault_in_multipages_writeable(user_data, remain);
465 /* Userspace is tricking us, but we've already clobbered
466 * its pages with the prefault and promised to write the
467 * data up to the first fault. Hence ignore any errors
468 * and just continue. */
473 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
474 user_data, page_do_bit17_swizzling,
477 mutex_lock(&dev->struct_mutex);
478 page_cache_release(page);
480 mark_page_accessed(page);
482 page_cache_release(page);
489 remain -= page_length;
490 user_data += page_length;
491 offset += page_length;
496 /* Fixup: Kill any reinstated backing storage pages */
497 if (obj->madv == __I915_MADV_PURGED)
498 i915_gem_object_truncate(obj);
505 * Reads data from the object referenced by handle.
507 * On error, the contents of *data are undefined.
510 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file)
513 struct drm_i915_gem_pread *args = data;
514 struct drm_i915_gem_object *obj;
520 if (!access_ok(VERIFY_WRITE,
521 (char __user *)(uintptr_t)args->data_ptr,
525 ret = i915_mutex_lock_interruptible(dev);
529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
530 if (&obj->base == NULL) {
535 /* Bounds check source. */
536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
542 /* prime objects have no backing filp to GEM pread/pwrite
545 if (!obj->base.filp) {
550 trace_i915_gem_object_pread(obj, args->offset, args->size);
552 ret = i915_gem_shmem_pread(dev, obj, args, file);
555 drm_gem_object_unreference(&obj->base);
557 mutex_unlock(&dev->struct_mutex);
561 /* This is the fast write path which cannot handle
562 * page faults in the source data
566 fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
571 void __iomem *vaddr_atomic;
573 unsigned long unwritten;
575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
580 io_mapping_unmap_atomic(vaddr_atomic);
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
589 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pwrite *args,
592 struct drm_file *file)
594 drm_i915_private_t *dev_priv = dev->dev_private;
596 loff_t offset, page_base;
597 char __user *user_data;
598 int page_offset, page_length, ret;
600 ret = i915_gem_object_pin(obj, 0, true);
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
608 ret = i915_gem_object_put_fence(obj);
612 user_data = (char __user *) (uintptr_t) args->data_ptr;
615 offset = obj->gtt_offset + args->offset;
618 /* Operation in this page
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
634 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
635 page_offset, user_data, page_length)) {
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
646 i915_gem_object_unpin(obj);
651 /* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
656 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
665 if (unlikely(page_do_bit17_swizzling))
668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
678 kunmap_atomic(vaddr);
683 /* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
686 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
699 page_do_bit17_swizzling);
700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
705 ret = __copy_from_user(vaddr + shmem_page_offset,
708 if (needs_clflush_after)
709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
711 page_do_bit17_swizzling);
718 i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
723 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
726 char __user *user_data;
727 int shmem_page_offset, page_length, ret = 0;
728 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
729 int hit_slowpath = 0;
730 int needs_clflush_after = 0;
731 int needs_clflush_before = 0;
734 user_data = (char __user *) (uintptr_t) args->data_ptr;
737 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
739 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
740 /* If we're not in the cpu write domain, set ourself into the gtt
741 * write domain and manually flush cachelines (if required). This
742 * optimizes for the case when the gpu will use the data
743 * right away and we therefore have to clflush anyway. */
744 if (obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_after = 1;
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
750 /* Same trick applies for invalidate partially written cachelines before
752 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
753 && obj->cache_level == I915_CACHE_NONE)
754 needs_clflush_before = 1;
756 offset = args->offset;
761 int partial_cacheline_write;
763 /* Operation in this page
765 * shmem_page_offset = offset within page in shmem file
766 * page_length = bytes to copy for this page
768 shmem_page_offset = offset_in_page(offset);
770 page_length = remain;
771 if ((shmem_page_offset + page_length) > PAGE_SIZE)
772 page_length = PAGE_SIZE - shmem_page_offset;
774 /* If we don't overwrite a cacheline completely we need to be
775 * careful to have up-to-date data by first clflushing. Don't
776 * overcomplicate things and flush the entire patch. */
777 partial_cacheline_write = needs_clflush_before &&
778 ((shmem_page_offset | page_length)
779 & (boot_cpu_data.x86_clflush_size - 1));
782 page = obj->pages[offset >> PAGE_SHIFT];
785 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
793 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
794 (page_to_phys(page) & (1 << 17)) != 0;
796 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
797 user_data, page_do_bit17_swizzling,
798 partial_cacheline_write,
799 needs_clflush_after);
804 page_cache_get(page);
805 mutex_unlock(&dev->struct_mutex);
807 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
808 user_data, page_do_bit17_swizzling,
809 partial_cacheline_write,
810 needs_clflush_after);
812 mutex_lock(&dev->struct_mutex);
813 page_cache_release(page);
815 set_page_dirty(page);
816 mark_page_accessed(page);
818 page_cache_release(page);
825 remain -= page_length;
826 user_data += page_length;
827 offset += page_length;
832 /* Fixup: Kill any reinstated backing storage pages */
833 if (obj->madv == __I915_MADV_PURGED)
834 i915_gem_object_truncate(obj);
835 /* and flush dirty cachelines in case the object isn't in the cpu write
837 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 i915_gem_clflush_object(obj);
839 intel_gtt_chipset_flush();
843 if (needs_clflush_after)
844 intel_gtt_chipset_flush();
850 * Writes data to the object referenced by handle.
852 * On error, the contents of the buffer that were to be modified are undefined.
855 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
865 if (!access_ok(VERIFY_READ,
866 (char __user *)(uintptr_t)args->data_ptr,
870 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
875 ret = i915_mutex_lock_interruptible(dev);
879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
880 if (&obj->base == NULL) {
885 /* Bounds check destination. */
886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
892 /* prime objects have no backing filp to GEM pread/pwrite
895 if (!obj->base.filp) {
900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
914 if (obj->gtt_space &&
915 obj->cache_level == I915_CACHE_NONE &&
916 obj->tiling_mode == I915_TILING_NONE &&
917 obj->map_and_fenceable &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
929 drm_gem_object_unreference(&obj->base);
931 mutex_unlock(&dev->struct_mutex);
936 * Called when user space prepares to use an object with the CPU, either
937 * through the mmap ioctl's mapping or a GTT mapping.
940 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *file)
943 struct drm_i915_gem_set_domain *args = data;
944 struct drm_i915_gem_object *obj;
945 uint32_t read_domains = args->read_domains;
946 uint32_t write_domain = args->write_domain;
949 /* Only handle setting domains to types used by the CPU. */
950 if (write_domain & I915_GEM_GPU_DOMAINS)
953 if (read_domains & I915_GEM_GPU_DOMAINS)
956 /* Having something in the write domain implies it's in the read
957 * domain, and only that read domain. Enforce that in the request.
959 if (write_domain != 0 && read_domains != write_domain)
962 ret = i915_mutex_lock_interruptible(dev);
966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
967 if (&obj->base == NULL) {
972 if (read_domains & I915_GEM_DOMAIN_GTT) {
973 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
975 /* Silently promote "you're not bound, there was nothing to do"
976 * to success, since the client was just asking us to
977 * make sure everything was done.
982 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
985 drm_gem_object_unreference(&obj->base);
987 mutex_unlock(&dev->struct_mutex);
992 * Called when user space has done writes to this buffer
995 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
998 struct drm_i915_gem_sw_finish *args = data;
999 struct drm_i915_gem_object *obj;
1002 ret = i915_mutex_lock_interruptible(dev);
1006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1007 if (&obj->base == NULL) {
1012 /* Pinned buffers may be scanout, so flush the cache */
1014 i915_gem_object_flush_cpu_write_domain(obj);
1016 drm_gem_object_unreference(&obj->base);
1018 mutex_unlock(&dev->struct_mutex);
1023 * Maps the contents of an object, returning the address it is mapped
1026 * While the mapping holds a reference on the contents of the object, it doesn't
1027 * imply a ref on the object itself.
1030 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1031 struct drm_file *file)
1033 struct drm_i915_gem_mmap *args = data;
1034 struct drm_gem_object *obj;
1037 obj = drm_gem_object_lookup(dev, file, args->handle);
1041 /* prime objects have no backing filp to GEM mmap
1045 drm_gem_object_unreference_unlocked(obj);
1049 addr = vm_mmap(obj->filp, 0, args->size,
1050 PROT_READ | PROT_WRITE, MAP_SHARED,
1052 drm_gem_object_unreference_unlocked(obj);
1053 if (IS_ERR((void *)addr))
1056 args->addr_ptr = (uint64_t) addr;
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1077 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1079 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1080 struct drm_device *dev = obj->base.dev;
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 pgoff_t page_offset;
1085 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1087 /* We don't use vmf->pgoff since that has the fake offset */
1088 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1091 ret = i915_mutex_lock_interruptible(dev);
1095 trace_i915_gem_object_fault(obj, page_offset, true, write);
1097 /* Now bind it into the GTT if needed */
1098 if (!obj->map_and_fenceable) {
1099 ret = i915_gem_object_unbind(obj);
1103 if (!obj->gtt_space) {
1104 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1108 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1113 if (!obj->has_global_gtt_mapping)
1114 i915_gem_gtt_bind_object(obj, obj->cache_level);
1116 ret = i915_gem_object_get_fence(obj);
1120 if (i915_gem_object_is_inactive(obj))
1121 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1123 obj->fault_mappable = true;
1125 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1128 /* Finally, remap it using the new GTT offset */
1129 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1131 mutex_unlock(&dev->struct_mutex);
1136 /* Give the error handler a chance to run and move the
1137 * objects off the GPU active list. Next time we service the
1138 * fault, we should be able to transition the page into the
1139 * GTT without touching the GPU (and so avoid further
1140 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1141 * with coherency, just lost writes.
1147 return VM_FAULT_NOPAGE;
1149 return VM_FAULT_OOM;
1151 return VM_FAULT_SIGBUS;
1156 * i915_gem_release_mmap - remove physical page mappings
1157 * @obj: obj in question
1159 * Preserve the reservation of the mmapping with the DRM core code, but
1160 * relinquish ownership of the pages back to the system.
1162 * It is vital that we remove the page mapping if we have mapped a tiled
1163 * object through the GTT and then lose the fence register due to
1164 * resource pressure. Similarly if the object has been moved out of the
1165 * aperture, than pages mapped into userspace must be revoked. Removing the
1166 * mapping will then trigger a page fault on the next user access, allowing
1167 * fixup by i915_gem_fault().
1170 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1172 if (!obj->fault_mappable)
1175 if (obj->base.dev->dev_mapping)
1176 unmap_mapping_range(obj->base.dev->dev_mapping,
1177 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1180 obj->fault_mappable = false;
1184 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1188 if (INTEL_INFO(dev)->gen >= 4 ||
1189 tiling_mode == I915_TILING_NONE)
1192 /* Previous chips need a power-of-two fence region when tiling */
1193 if (INTEL_INFO(dev)->gen == 3)
1194 gtt_size = 1024*1024;
1196 gtt_size = 512*1024;
1198 while (gtt_size < size)
1205 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1206 * @obj: object to check
1208 * Return the required GTT alignment for an object, taking into account
1209 * potential fence register mapping.
1212 i915_gem_get_gtt_alignment(struct drm_device *dev,
1217 * Minimum alignment is 4k (GTT page size), but might be greater
1218 * if a fence register is needed for the object.
1220 if (INTEL_INFO(dev)->gen >= 4 ||
1221 tiling_mode == I915_TILING_NONE)
1225 * Previous chips need to be aligned to the size of the smallest
1226 * fence register that can contain the object.
1228 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1232 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1235 * @size: size of the object
1236 * @tiling_mode: tiling mode of the object
1238 * Return the required GTT alignment for an object, only taking into account
1239 * unfenced tiled surface requirements.
1242 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1247 * Minimum alignment is 4k (GTT page size) for sane hw.
1249 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1250 tiling_mode == I915_TILING_NONE)
1253 /* Previous hardware however needs to be aligned to a power-of-two
1254 * tile height. The simplest method for determining this is to reuse
1255 * the power-of-tile object size.
1257 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1261 i915_gem_mmap_gtt(struct drm_file *file,
1262 struct drm_device *dev,
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 struct drm_i915_gem_object *obj;
1270 ret = i915_mutex_lock_interruptible(dev);
1274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1275 if (&obj->base == NULL) {
1280 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1285 if (obj->madv != I915_MADV_WILLNEED) {
1286 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1291 if (!obj->base.map_list.map) {
1292 ret = drm_gem_create_mmap_offset(&obj->base);
1297 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1300 drm_gem_object_unreference(&obj->base);
1302 mutex_unlock(&dev->struct_mutex);
1307 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1309 * @data: GTT mapping ioctl data
1310 * @file: GEM object info
1312 * Simply returns the fake offset to userspace so it can mmap it.
1313 * The mmap call will end up in drm_gem_mmap(), which will set things
1314 * up so we can get faults in the handler above.
1316 * The fault handler will take care of binding the object into the GTT
1317 * (since it may have been evicted to make room for something), allocating
1318 * a fence register, and mapping the appropriate aperture address into
1322 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *file)
1325 struct drm_i915_gem_mmap_gtt *args = data;
1327 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1331 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1335 struct address_space *mapping;
1336 struct inode *inode;
1339 if (obj->pages || obj->sg_table)
1342 /* Get the list of pages out of our struct file. They'll be pinned
1343 * at this point until we release them.
1345 page_count = obj->base.size / PAGE_SIZE;
1346 BUG_ON(obj->pages != NULL);
1347 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1348 if (obj->pages == NULL)
1351 inode = obj->base.filp->f_path.dentry->d_inode;
1352 mapping = inode->i_mapping;
1353 gfpmask |= mapping_gfp_mask(mapping);
1355 for (i = 0; i < page_count; i++) {
1356 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1360 obj->pages[i] = page;
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 i915_gem_object_do_bit_17_swizzle(obj);
1370 page_cache_release(obj->pages[i]);
1372 drm_free_large(obj->pages);
1374 return PTR_ERR(page);
1378 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1380 int page_count = obj->base.size / PAGE_SIZE;
1386 BUG_ON(obj->madv == __I915_MADV_PURGED);
1388 if (i915_gem_object_needs_bit17_swizzle(obj))
1389 i915_gem_object_save_bit_17_swizzle(obj);
1391 if (obj->madv == I915_MADV_DONTNEED)
1394 for (i = 0; i < page_count; i++) {
1396 set_page_dirty(obj->pages[i]);
1398 if (obj->madv == I915_MADV_WILLNEED)
1399 mark_page_accessed(obj->pages[i]);
1401 page_cache_release(obj->pages[i]);
1405 drm_free_large(obj->pages);
1410 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1411 struct intel_ring_buffer *ring,
1414 struct drm_device *dev = obj->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1417 BUG_ON(ring == NULL);
1420 /* Add a reference if we're newly entering the active list. */
1422 drm_gem_object_reference(&obj->base);
1426 /* Move from whatever list we were on to the tail of execution. */
1427 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1428 list_move_tail(&obj->ring_list, &ring->active_list);
1430 obj->last_rendering_seqno = seqno;
1432 if (obj->fenced_gpu_access) {
1433 obj->last_fenced_seqno = seqno;
1435 /* Bump MRU to take account of the delayed flush */
1436 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1437 struct drm_i915_fence_reg *reg;
1439 reg = &dev_priv->fence_regs[obj->fence_reg];
1440 list_move_tail(®->lru_list,
1441 &dev_priv->mm.fence_list);
1447 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1449 list_del_init(&obj->ring_list);
1450 obj->last_rendering_seqno = 0;
1451 obj->last_fenced_seqno = 0;
1455 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1457 struct drm_device *dev = obj->base.dev;
1458 drm_i915_private_t *dev_priv = dev->dev_private;
1460 BUG_ON(!obj->active);
1461 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1463 i915_gem_object_move_off_active(obj);
1467 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1469 struct drm_device *dev = obj->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1472 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1474 BUG_ON(!list_empty(&obj->gpu_write_list));
1475 BUG_ON(!obj->active);
1478 i915_gem_object_move_off_active(obj);
1479 obj->fenced_gpu_access = false;
1482 obj->pending_gpu_write = false;
1483 drm_gem_object_unreference(&obj->base);
1485 WARN_ON(i915_verify_lists(dev));
1488 /* Immediately discard the backing storage */
1490 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1492 struct inode *inode;
1494 /* Our goal here is to return as much of the memory as
1495 * is possible back to the system as we are called from OOM.
1496 * To do this we must instruct the shmfs to drop all of its
1497 * backing pages, *now*.
1499 inode = obj->base.filp->f_path.dentry->d_inode;
1500 shmem_truncate_range(inode, 0, (loff_t)-1);
1502 if (obj->base.map_list.map)
1503 drm_gem_free_mmap_offset(&obj->base);
1505 obj->madv = __I915_MADV_PURGED;
1509 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1511 return obj->madv == I915_MADV_DONTNEED;
1515 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1516 uint32_t flush_domains)
1518 struct drm_i915_gem_object *obj, *next;
1520 list_for_each_entry_safe(obj, next,
1521 &ring->gpu_write_list,
1523 if (obj->base.write_domain & flush_domains) {
1524 uint32_t old_write_domain = obj->base.write_domain;
1526 obj->base.write_domain = 0;
1527 list_del_init(&obj->gpu_write_list);
1528 i915_gem_object_move_to_active(obj, ring,
1529 i915_gem_next_request_seqno(ring));
1531 trace_i915_gem_object_change_domain(obj,
1532 obj->base.read_domains,
1539 i915_gem_get_seqno(struct drm_device *dev)
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 seqno = dev_priv->next_seqno;
1544 /* reserve 0 for non-seqno */
1545 if (++dev_priv->next_seqno == 0)
1546 dev_priv->next_seqno = 1;
1552 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1554 if (ring->outstanding_lazy_request == 0)
1555 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1557 return ring->outstanding_lazy_request;
1561 i915_add_request(struct intel_ring_buffer *ring,
1562 struct drm_file *file,
1563 struct drm_i915_gem_request *request)
1565 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1567 u32 request_ring_position;
1571 BUG_ON(request == NULL);
1572 seqno = i915_gem_next_request_seqno(ring);
1574 /* Record the position of the start of the request so that
1575 * should we detect the updated seqno part-way through the
1576 * GPU processing the request, we never over-estimate the
1577 * position of the head.
1579 request_ring_position = intel_ring_get_tail(ring);
1581 ret = ring->add_request(ring, &seqno);
1585 trace_i915_gem_request_add(ring, seqno);
1587 request->seqno = seqno;
1588 request->ring = ring;
1589 request->tail = request_ring_position;
1590 request->emitted_jiffies = jiffies;
1591 was_empty = list_empty(&ring->request_list);
1592 list_add_tail(&request->list, &ring->request_list);
1595 struct drm_i915_file_private *file_priv = file->driver_priv;
1597 spin_lock(&file_priv->mm.lock);
1598 request->file_priv = file_priv;
1599 list_add_tail(&request->client_list,
1600 &file_priv->mm.request_list);
1601 spin_unlock(&file_priv->mm.lock);
1604 ring->outstanding_lazy_request = 0;
1606 if (!dev_priv->mm.suspended) {
1607 if (i915_enable_hangcheck) {
1608 mod_timer(&dev_priv->hangcheck_timer,
1610 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1613 queue_delayed_work(dev_priv->wq,
1614 &dev_priv->mm.retire_work, HZ);
1620 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1622 struct drm_i915_file_private *file_priv = request->file_priv;
1627 spin_lock(&file_priv->mm.lock);
1628 if (request->file_priv) {
1629 list_del(&request->client_list);
1630 request->file_priv = NULL;
1632 spin_unlock(&file_priv->mm.lock);
1635 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1636 struct intel_ring_buffer *ring)
1638 while (!list_empty(&ring->request_list)) {
1639 struct drm_i915_gem_request *request;
1641 request = list_first_entry(&ring->request_list,
1642 struct drm_i915_gem_request,
1645 list_del(&request->list);
1646 i915_gem_request_remove_from_client(request);
1650 while (!list_empty(&ring->active_list)) {
1651 struct drm_i915_gem_object *obj;
1653 obj = list_first_entry(&ring->active_list,
1654 struct drm_i915_gem_object,
1657 obj->base.write_domain = 0;
1658 list_del_init(&obj->gpu_write_list);
1659 i915_gem_object_move_to_inactive(obj);
1663 static void i915_gem_reset_fences(struct drm_device *dev)
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1668 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1669 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1671 i915_gem_write_fence(dev, i, NULL);
1674 i915_gem_object_fence_lost(reg->obj);
1678 INIT_LIST_HEAD(®->lru_list);
1681 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1684 void i915_gem_reset(struct drm_device *dev)
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct drm_i915_gem_object *obj;
1688 struct intel_ring_buffer *ring;
1691 for_each_ring(ring, dev_priv, i)
1692 i915_gem_reset_ring_lists(dev_priv, ring);
1694 /* Remove anything from the flushing lists. The GPU cache is likely
1695 * to be lost on reset along with the data, so simply move the
1696 * lost bo to the inactive list.
1698 while (!list_empty(&dev_priv->mm.flushing_list)) {
1699 obj = list_first_entry(&dev_priv->mm.flushing_list,
1700 struct drm_i915_gem_object,
1703 obj->base.write_domain = 0;
1704 list_del_init(&obj->gpu_write_list);
1705 i915_gem_object_move_to_inactive(obj);
1708 /* Move everything out of the GPU domains to ensure we do any
1709 * necessary invalidation upon reuse.
1711 list_for_each_entry(obj,
1712 &dev_priv->mm.inactive_list,
1715 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1718 /* The fence registers are invalidated so clear them out */
1719 i915_gem_reset_fences(dev);
1723 * This function clears the request list as sequence numbers are passed.
1726 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1731 if (list_empty(&ring->request_list))
1734 WARN_ON(i915_verify_lists(ring->dev));
1736 seqno = ring->get_seqno(ring);
1738 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1739 if (seqno >= ring->sync_seqno[i])
1740 ring->sync_seqno[i] = 0;
1742 while (!list_empty(&ring->request_list)) {
1743 struct drm_i915_gem_request *request;
1745 request = list_first_entry(&ring->request_list,
1746 struct drm_i915_gem_request,
1749 if (!i915_seqno_passed(seqno, request->seqno))
1752 trace_i915_gem_request_retire(ring, request->seqno);
1753 /* We know the GPU must have read the request to have
1754 * sent us the seqno + interrupt, so use the position
1755 * of tail of the request to update the last known position
1758 ring->last_retired_head = request->tail;
1760 list_del(&request->list);
1761 i915_gem_request_remove_from_client(request);
1765 /* Move any buffers on the active list that are no longer referenced
1766 * by the ringbuffer to the flushing/inactive lists as appropriate.
1768 while (!list_empty(&ring->active_list)) {
1769 struct drm_i915_gem_object *obj;
1771 obj = list_first_entry(&ring->active_list,
1772 struct drm_i915_gem_object,
1775 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1778 if (obj->base.write_domain != 0)
1779 i915_gem_object_move_to_flushing(obj);
1781 i915_gem_object_move_to_inactive(obj);
1784 if (unlikely(ring->trace_irq_seqno &&
1785 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1786 ring->irq_put(ring);
1787 ring->trace_irq_seqno = 0;
1790 WARN_ON(i915_verify_lists(ring->dev));
1794 i915_gem_retire_requests(struct drm_device *dev)
1796 drm_i915_private_t *dev_priv = dev->dev_private;
1797 struct intel_ring_buffer *ring;
1800 for_each_ring(ring, dev_priv, i)
1801 i915_gem_retire_requests_ring(ring);
1805 i915_gem_retire_work_handler(struct work_struct *work)
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1809 struct intel_ring_buffer *ring;
1813 dev_priv = container_of(work, drm_i915_private_t,
1814 mm.retire_work.work);
1815 dev = dev_priv->dev;
1817 /* Come back later if the device is busy... */
1818 if (!mutex_trylock(&dev->struct_mutex)) {
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1823 i915_gem_retire_requests(dev);
1825 /* Send a periodic flush down the ring so we don't hold onto GEM
1826 * objects indefinitely.
1829 for_each_ring(ring, dev_priv, i) {
1830 if (!list_empty(&ring->gpu_write_list)) {
1831 struct drm_i915_gem_request *request;
1834 ret = i915_gem_flush_ring(ring,
1835 0, I915_GEM_GPU_DOMAINS);
1836 request = kzalloc(sizeof(*request), GFP_KERNEL);
1837 if (ret || request == NULL ||
1838 i915_add_request(ring, NULL, request))
1842 idle &= list_empty(&ring->request_list);
1845 if (!dev_priv->mm.suspended && !idle)
1846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1848 mutex_unlock(&dev->struct_mutex);
1852 i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1854 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1856 if (atomic_read(&dev_priv->mm.wedged)) {
1857 struct completion *x = &dev_priv->error_completion;
1858 bool recovery_complete;
1859 unsigned long flags;
1861 /* Give the error handler a chance to run. */
1862 spin_lock_irqsave(&x->wait.lock, flags);
1863 recovery_complete = x->done > 0;
1864 spin_unlock_irqrestore(&x->wait.lock, flags);
1866 return recovery_complete ? -EIO : -EAGAIN;
1873 * Compare seqno against outstanding lazy request. Emit a request if they are
1877 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1881 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1883 if (seqno == ring->outstanding_lazy_request) {
1884 struct drm_i915_gem_request *request;
1886 request = kzalloc(sizeof(*request), GFP_KERNEL);
1887 if (request == NULL)
1890 ret = i915_add_request(ring, NULL, request);
1896 BUG_ON(seqno != request->seqno);
1902 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1905 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1908 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1911 trace_i915_gem_request_wait_begin(ring, seqno);
1912 if (WARN_ON(!ring->irq_get(ring)))
1916 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1917 atomic_read(&dev_priv->mm.wedged))
1920 ret = wait_event_interruptible(ring->irq_queue,
1923 wait_event(ring->irq_queue, EXIT_COND);
1925 ring->irq_put(ring);
1926 trace_i915_gem_request_wait_end(ring, seqno);
1933 * Waits for a sequence number to be signaled, and cleans up the
1934 * request and object lists appropriately for that event.
1937 i915_wait_request(struct intel_ring_buffer *ring,
1940 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1945 ret = i915_gem_check_wedge(dev_priv);
1949 ret = i915_gem_check_olr(ring, seqno);
1953 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
1954 if (atomic_read(&dev_priv->mm.wedged))
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1965 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
1969 /* This function only exists to support waiting for existing rendering,
1970 * not for emitting required flushes.
1972 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
1974 /* If there is rendering queued on the buffer being evicted, wait for
1978 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
1981 i915_gem_retire_requests_ring(obj->ring);
1988 * i915_gem_object_sync - sync an object to a ring.
1990 * @obj: object which may be in use on another ring.
1991 * @to: ring we wish to use the object on. May be NULL.
1993 * This code is meant to abstract object synchronization with the GPU.
1994 * Calling with NULL implies synchronizing the object with the CPU
1995 * rather than a particular GPU ring.
1997 * Returns 0 if successful, else propagates up the lower layer error.
2000 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2001 struct intel_ring_buffer *to)
2003 struct intel_ring_buffer *from = obj->ring;
2007 if (from == NULL || to == from)
2010 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2011 return i915_gem_object_wait_rendering(obj);
2013 idx = intel_ring_sync_index(from, to);
2015 seqno = obj->last_rendering_seqno;
2016 if (seqno <= from->sync_seqno[idx])
2019 ret = i915_gem_check_olr(obj->ring, seqno);
2023 ret = to->sync_to(to, from, seqno);
2025 from->sync_seqno[idx] = seqno;
2030 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2032 u32 old_write_domain, old_read_domains;
2034 /* Act a barrier for all accesses through the GTT */
2037 /* Force a pagefault for domain tracking on next user access */
2038 i915_gem_release_mmap(obj);
2040 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2043 old_read_domains = obj->base.read_domains;
2044 old_write_domain = obj->base.write_domain;
2046 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2047 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2049 trace_i915_gem_object_change_domain(obj,
2055 * Unbinds an object from the GTT aperture.
2058 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2060 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2063 if (obj->gtt_space == NULL)
2066 if (obj->pin_count != 0) {
2067 DRM_ERROR("Attempting to unbind pinned buffer\n");
2071 ret = i915_gem_object_finish_gpu(obj);
2074 /* Continue on if we fail due to EIO, the GPU is hung so we
2075 * should be safe and we need to cleanup or else we might
2076 * cause memory corruption through use-after-free.
2079 i915_gem_object_finish_gtt(obj);
2081 /* Move the object to the CPU domain to ensure that
2082 * any possible CPU writes while it's not in the GTT
2083 * are flushed when we go to remap it.
2086 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2087 if (ret == -ERESTARTSYS)
2090 /* In the event of a disaster, abandon all caches and
2091 * hope for the best.
2093 i915_gem_clflush_object(obj);
2094 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2097 /* release the fence reg _after_ flushing */
2098 ret = i915_gem_object_put_fence(obj);
2102 trace_i915_gem_object_unbind(obj);
2104 if (obj->has_global_gtt_mapping)
2105 i915_gem_gtt_unbind_object(obj);
2106 if (obj->has_aliasing_ppgtt_mapping) {
2107 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2108 obj->has_aliasing_ppgtt_mapping = 0;
2110 i915_gem_gtt_finish_object(obj);
2112 i915_gem_object_put_pages_gtt(obj);
2114 list_del_init(&obj->gtt_list);
2115 list_del_init(&obj->mm_list);
2116 /* Avoid an unnecessary call to unbind on rebind. */
2117 obj->map_and_fenceable = true;
2119 drm_mm_put_block(obj->gtt_space);
2120 obj->gtt_space = NULL;
2121 obj->gtt_offset = 0;
2123 if (i915_gem_object_is_purgeable(obj))
2124 i915_gem_object_truncate(obj);
2130 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2131 uint32_t invalidate_domains,
2132 uint32_t flush_domains)
2136 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2139 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2141 ret = ring->flush(ring, invalidate_domains, flush_domains);
2145 if (flush_domains & I915_GEM_GPU_DOMAINS)
2146 i915_gem_process_flushing_list(ring, flush_domains);
2151 static int i915_ring_idle(struct intel_ring_buffer *ring)
2155 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2158 if (!list_empty(&ring->gpu_write_list)) {
2159 ret = i915_gem_flush_ring(ring,
2160 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2165 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2168 int i915_gpu_idle(struct drm_device *dev)
2170 drm_i915_private_t *dev_priv = dev->dev_private;
2171 struct intel_ring_buffer *ring;
2174 /* Flush everything onto the inactive list. */
2175 for_each_ring(ring, dev_priv, i) {
2176 ret = i915_ring_idle(ring);
2180 /* Is the device fubar? */
2181 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2188 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2189 struct drm_i915_gem_object *obj)
2191 drm_i915_private_t *dev_priv = dev->dev_private;
2195 u32 size = obj->gtt_space->size;
2197 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2199 val |= obj->gtt_offset & 0xfffff000;
2200 val |= (uint64_t)((obj->stride / 128) - 1) <<
2201 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2203 if (obj->tiling_mode == I915_TILING_Y)
2204 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2205 val |= I965_FENCE_REG_VALID;
2209 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2210 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2213 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2214 struct drm_i915_gem_object *obj)
2216 drm_i915_private_t *dev_priv = dev->dev_private;
2220 u32 size = obj->gtt_space->size;
2222 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2224 val |= obj->gtt_offset & 0xfffff000;
2225 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2226 if (obj->tiling_mode == I915_TILING_Y)
2227 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2228 val |= I965_FENCE_REG_VALID;
2232 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2233 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2236 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2237 struct drm_i915_gem_object *obj)
2239 drm_i915_private_t *dev_priv = dev->dev_private;
2243 u32 size = obj->gtt_space->size;
2247 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2248 (size & -size) != size ||
2249 (obj->gtt_offset & (size - 1)),
2250 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2251 obj->gtt_offset, obj->map_and_fenceable, size);
2253 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2258 /* Note: pitch better be a power of two tile widths */
2259 pitch_val = obj->stride / tile_width;
2260 pitch_val = ffs(pitch_val) - 1;
2262 val = obj->gtt_offset;
2263 if (obj->tiling_mode == I915_TILING_Y)
2264 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2265 val |= I915_FENCE_SIZE_BITS(size);
2266 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2267 val |= I830_FENCE_REG_VALID;
2272 reg = FENCE_REG_830_0 + reg * 4;
2274 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2276 I915_WRITE(reg, val);
2280 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2281 struct drm_i915_gem_object *obj)
2283 drm_i915_private_t *dev_priv = dev->dev_private;
2287 u32 size = obj->gtt_space->size;
2290 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2291 (size & -size) != size ||
2292 (obj->gtt_offset & (size - 1)),
2293 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2294 obj->gtt_offset, size);
2296 pitch_val = obj->stride / 128;
2297 pitch_val = ffs(pitch_val) - 1;
2299 val = obj->gtt_offset;
2300 if (obj->tiling_mode == I915_TILING_Y)
2301 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2302 val |= I830_FENCE_SIZE_BITS(size);
2303 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2304 val |= I830_FENCE_REG_VALID;
2308 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2309 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2312 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2313 struct drm_i915_gem_object *obj)
2315 switch (INTEL_INFO(dev)->gen) {
2317 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2319 case 4: i965_write_fence_reg(dev, reg, obj); break;
2320 case 3: i915_write_fence_reg(dev, reg, obj); break;
2321 case 2: i830_write_fence_reg(dev, reg, obj); break;
2326 static inline int fence_number(struct drm_i915_private *dev_priv,
2327 struct drm_i915_fence_reg *fence)
2329 return fence - dev_priv->fence_regs;
2332 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2333 struct drm_i915_fence_reg *fence,
2336 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2337 int reg = fence_number(dev_priv, fence);
2339 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2342 obj->fence_reg = reg;
2344 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2346 obj->fence_reg = I915_FENCE_REG_NONE;
2348 list_del_init(&fence->lru_list);
2353 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2357 if (obj->fenced_gpu_access) {
2358 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2359 ret = i915_gem_flush_ring(obj->ring,
2360 0, obj->base.write_domain);
2365 obj->fenced_gpu_access = false;
2368 if (obj->last_fenced_seqno) {
2369 ret = i915_wait_request(obj->ring, obj->last_fenced_seqno);
2373 obj->last_fenced_seqno = 0;
2376 /* Ensure that all CPU reads are completed before installing a fence
2377 * and all writes before removing the fence.
2379 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2386 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2388 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2391 ret = i915_gem_object_flush_fence(obj);
2395 if (obj->fence_reg == I915_FENCE_REG_NONE)
2398 i915_gem_object_update_fence(obj,
2399 &dev_priv->fence_regs[obj->fence_reg],
2401 i915_gem_object_fence_lost(obj);
2406 static struct drm_i915_fence_reg *
2407 i915_find_fence_reg(struct drm_device *dev)
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct drm_i915_fence_reg *reg, *avail;
2413 /* First try to find a free reg */
2415 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416 reg = &dev_priv->fence_regs[i];
2420 if (!reg->pin_count)
2427 /* None available, try to steal one or wait for a user to finish */
2428 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2439 * i915_gem_object_get_fence - set up fencing for an object
2440 * @obj: object to map through a fence reg
2442 * When mapping objects through the GTT, userspace wants to be able to write
2443 * to them without having to worry about swizzling if the object is tiled.
2444 * This function walks the fence regs looking for a free one for @obj,
2445 * stealing one if it can't find any.
2447 * It then sets up the reg based on the object's properties: address, pitch
2448 * and tiling format.
2450 * For an untiled surface, this removes any existing fence.
2453 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2455 struct drm_device *dev = obj->base.dev;
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 bool enable = obj->tiling_mode != I915_TILING_NONE;
2458 struct drm_i915_fence_reg *reg;
2461 /* Have we updated the tiling parameters upon the object and so
2462 * will need to serialise the write to the associated fence register?
2464 if (obj->fence_dirty) {
2465 ret = i915_gem_object_flush_fence(obj);
2470 /* Just update our place in the LRU if our fence is getting reused. */
2471 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2472 reg = &dev_priv->fence_regs[obj->fence_reg];
2473 if (!obj->fence_dirty) {
2474 list_move_tail(®->lru_list,
2475 &dev_priv->mm.fence_list);
2478 } else if (enable) {
2479 reg = i915_find_fence_reg(dev);
2484 struct drm_i915_gem_object *old = reg->obj;
2486 ret = i915_gem_object_flush_fence(old);
2490 i915_gem_object_fence_lost(old);
2495 i915_gem_object_update_fence(obj, reg, enable);
2496 obj->fence_dirty = false;
2502 * Finds free space in the GTT aperture and binds the object there.
2505 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2507 bool map_and_fenceable)
2509 struct drm_device *dev = obj->base.dev;
2510 drm_i915_private_t *dev_priv = dev->dev_private;
2511 struct drm_mm_node *free_space;
2512 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2513 u32 size, fence_size, fence_alignment, unfenced_alignment;
2514 bool mappable, fenceable;
2517 if (obj->madv != I915_MADV_WILLNEED) {
2518 DRM_ERROR("Attempting to bind a purgeable object\n");
2522 fence_size = i915_gem_get_gtt_size(dev,
2525 fence_alignment = i915_gem_get_gtt_alignment(dev,
2528 unfenced_alignment =
2529 i915_gem_get_unfenced_gtt_alignment(dev,
2534 alignment = map_and_fenceable ? fence_alignment :
2536 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2537 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2541 size = map_and_fenceable ? fence_size : obj->base.size;
2543 /* If the object is bigger than the entire aperture, reject it early
2544 * before evicting everything in a vain attempt to find space.
2546 if (obj->base.size >
2547 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2548 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2553 if (map_and_fenceable)
2555 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2557 dev_priv->mm.gtt_mappable_end,
2560 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2561 size, alignment, 0);
2563 if (free_space != NULL) {
2564 if (map_and_fenceable)
2566 drm_mm_get_block_range_generic(free_space,
2568 dev_priv->mm.gtt_mappable_end,
2572 drm_mm_get_block(free_space, size, alignment);
2574 if (obj->gtt_space == NULL) {
2575 /* If the gtt is empty and we're still having trouble
2576 * fitting our object in, we're out of memory.
2578 ret = i915_gem_evict_something(dev, size, alignment,
2586 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2588 drm_mm_put_block(obj->gtt_space);
2589 obj->gtt_space = NULL;
2591 if (ret == -ENOMEM) {
2592 /* first try to reclaim some memory by clearing the GTT */
2593 ret = i915_gem_evict_everything(dev, false);
2595 /* now try to shrink everyone else */
2610 ret = i915_gem_gtt_prepare_object(obj);
2612 i915_gem_object_put_pages_gtt(obj);
2613 drm_mm_put_block(obj->gtt_space);
2614 obj->gtt_space = NULL;
2616 if (i915_gem_evict_everything(dev, false))
2622 if (!dev_priv->mm.aliasing_ppgtt)
2623 i915_gem_gtt_bind_object(obj, obj->cache_level);
2625 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2626 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2628 /* Assert that the object is not currently in any GPU domain. As it
2629 * wasn't in the GTT, there shouldn't be any way it could have been in
2632 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2633 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2635 obj->gtt_offset = obj->gtt_space->start;
2638 obj->gtt_space->size == fence_size &&
2639 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2642 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2644 obj->map_and_fenceable = mappable && fenceable;
2646 trace_i915_gem_object_bind(obj, map_and_fenceable);
2651 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2653 /* If we don't have a page list set up, then we're not pinned
2654 * to GPU, and we can ignore the cache flush because it'll happen
2655 * again at bind time.
2657 if (obj->pages == NULL)
2660 /* If the GPU is snooping the contents of the CPU cache,
2661 * we do not need to manually clear the CPU cache lines. However,
2662 * the caches are only snooped when the render cache is
2663 * flushed/invalidated. As we always have to emit invalidations
2664 * and flushes when moving into and out of the RENDER domain, correct
2665 * snooping behaviour occurs naturally as the result of our domain
2668 if (obj->cache_level != I915_CACHE_NONE)
2671 trace_i915_gem_object_clflush(obj);
2673 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2676 /** Flushes any GPU write domain for the object if it's dirty. */
2678 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2680 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2683 /* Queue the GPU write cache flushing we need. */
2684 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2687 /** Flushes the GTT write domain for the object if it's dirty. */
2689 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2691 uint32_t old_write_domain;
2693 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2696 /* No actual flushing is required for the GTT write domain. Writes
2697 * to it immediately go to main memory as far as we know, so there's
2698 * no chipset flush. It also doesn't land in render cache.
2700 * However, we do have to enforce the order so that all writes through
2701 * the GTT land before any writes to the device, such as updates to
2706 old_write_domain = obj->base.write_domain;
2707 obj->base.write_domain = 0;
2709 trace_i915_gem_object_change_domain(obj,
2710 obj->base.read_domains,
2714 /** Flushes the CPU write domain for the object if it's dirty. */
2716 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2718 uint32_t old_write_domain;
2720 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2723 i915_gem_clflush_object(obj);
2724 intel_gtt_chipset_flush();
2725 old_write_domain = obj->base.write_domain;
2726 obj->base.write_domain = 0;
2728 trace_i915_gem_object_change_domain(obj,
2729 obj->base.read_domains,
2734 * Moves a single object to the GTT read, and possibly write domain.
2736 * This function returns when the move is complete, including waiting on
2740 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2742 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2743 uint32_t old_write_domain, old_read_domains;
2746 /* Not valid to be called on unbound objects. */
2747 if (obj->gtt_space == NULL)
2750 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2753 ret = i915_gem_object_flush_gpu_write_domain(obj);
2757 if (obj->pending_gpu_write || write) {
2758 ret = i915_gem_object_wait_rendering(obj);
2763 i915_gem_object_flush_cpu_write_domain(obj);
2765 old_write_domain = obj->base.write_domain;
2766 old_read_domains = obj->base.read_domains;
2768 /* It should now be out of any other write domains, and we can update
2769 * the domain values for our changes.
2771 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2772 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2774 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2775 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2779 trace_i915_gem_object_change_domain(obj,
2783 /* And bump the LRU for this access */
2784 if (i915_gem_object_is_inactive(obj))
2785 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2790 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2791 enum i915_cache_level cache_level)
2793 struct drm_device *dev = obj->base.dev;
2794 drm_i915_private_t *dev_priv = dev->dev_private;
2797 if (obj->cache_level == cache_level)
2800 if (obj->pin_count) {
2801 DRM_DEBUG("can not change the cache level of pinned objects\n");
2805 if (obj->gtt_space) {
2806 ret = i915_gem_object_finish_gpu(obj);
2810 i915_gem_object_finish_gtt(obj);
2812 /* Before SandyBridge, you could not use tiling or fence
2813 * registers with snooped memory, so relinquish any fences
2814 * currently pointing to our region in the aperture.
2816 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2817 ret = i915_gem_object_put_fence(obj);
2822 if (obj->has_global_gtt_mapping)
2823 i915_gem_gtt_bind_object(obj, cache_level);
2824 if (obj->has_aliasing_ppgtt_mapping)
2825 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2829 if (cache_level == I915_CACHE_NONE) {
2830 u32 old_read_domains, old_write_domain;
2832 /* If we're coming from LLC cached, then we haven't
2833 * actually been tracking whether the data is in the
2834 * CPU cache or not, since we only allow one bit set
2835 * in obj->write_domain and have been skipping the clflushes.
2836 * Just set it to the CPU cache for now.
2838 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2839 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2841 old_read_domains = obj->base.read_domains;
2842 old_write_domain = obj->base.write_domain;
2844 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2845 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2847 trace_i915_gem_object_change_domain(obj,
2852 obj->cache_level = cache_level;
2857 * Prepare buffer for display plane (scanout, cursors, etc).
2858 * Can be called from an uninterruptible phase (modesetting) and allows
2859 * any flushes to be pipelined (for pageflips).
2862 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2864 struct intel_ring_buffer *pipelined)
2866 u32 old_read_domains, old_write_domain;
2869 ret = i915_gem_object_flush_gpu_write_domain(obj);
2873 if (pipelined != obj->ring) {
2874 ret = i915_gem_object_sync(obj, pipelined);
2879 /* The display engine is not coherent with the LLC cache on gen6. As
2880 * a result, we make sure that the pinning that is about to occur is
2881 * done with uncached PTEs. This is lowest common denominator for all
2884 * However for gen6+, we could do better by using the GFDT bit instead
2885 * of uncaching, which would allow us to flush all the LLC-cached data
2886 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2888 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2892 /* As the user may map the buffer once pinned in the display plane
2893 * (e.g. libkms for the bootup splash), we have to ensure that we
2894 * always use map_and_fenceable for all scanout buffers.
2896 ret = i915_gem_object_pin(obj, alignment, true);
2900 i915_gem_object_flush_cpu_write_domain(obj);
2902 old_write_domain = obj->base.write_domain;
2903 old_read_domains = obj->base.read_domains;
2905 /* It should now be out of any other write domains, and we can update
2906 * the domain values for our changes.
2908 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2909 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2911 trace_i915_gem_object_change_domain(obj,
2919 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2923 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2926 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2927 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2932 ret = i915_gem_object_wait_rendering(obj);
2936 /* Ensure that we invalidate the GPU's caches and TLBs. */
2937 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2942 * Moves a single object to the CPU read, and possibly write domain.
2944 * This function returns when the move is complete, including waiting on
2948 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2950 uint32_t old_write_domain, old_read_domains;
2953 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2956 ret = i915_gem_object_flush_gpu_write_domain(obj);
2960 if (write || obj->pending_gpu_write) {
2961 ret = i915_gem_object_wait_rendering(obj);
2966 i915_gem_object_flush_gtt_write_domain(obj);
2968 old_write_domain = obj->base.write_domain;
2969 old_read_domains = obj->base.read_domains;
2971 /* Flush the CPU cache if it's still invalid. */
2972 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2973 i915_gem_clflush_object(obj);
2975 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2978 /* It should now be out of any other write domains, and we can update
2979 * the domain values for our changes.
2981 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2983 /* If we're writing through the CPU, then the GPU read domains will
2984 * need to be invalidated at next use.
2987 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2988 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2991 trace_i915_gem_object_change_domain(obj,
2998 /* Throttle our rendering by waiting until the ring has completed our requests
2999 * emitted over 20 msec ago.
3001 * Note that if we were to use the current jiffies each time around the loop,
3002 * we wouldn't escape the function with any frames outstanding if the time to
3003 * render a frame was over 20ms.
3005 * This should get us reasonable parallelism between CPU and GPU but also
3006 * relatively low latency when blocking on a particular request to finish.
3009 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct drm_i915_file_private *file_priv = file->driver_priv;
3013 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3014 struct drm_i915_gem_request *request;
3015 struct intel_ring_buffer *ring = NULL;
3019 if (atomic_read(&dev_priv->mm.wedged))
3022 spin_lock(&file_priv->mm.lock);
3023 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3024 if (time_after_eq(request->emitted_jiffies, recent_enough))
3027 ring = request->ring;
3028 seqno = request->seqno;
3030 spin_unlock(&file_priv->mm.lock);
3035 ret = __wait_seqno(ring, seqno, true);
3037 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3043 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3045 bool map_and_fenceable)
3049 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3051 if (obj->gtt_space != NULL) {
3052 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3053 (map_and_fenceable && !obj->map_and_fenceable)) {
3054 WARN(obj->pin_count,
3055 "bo is already pinned with incorrect alignment:"
3056 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3057 " obj->map_and_fenceable=%d\n",
3058 obj->gtt_offset, alignment,
3060 obj->map_and_fenceable);
3061 ret = i915_gem_object_unbind(obj);
3067 if (obj->gtt_space == NULL) {
3068 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3074 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3075 i915_gem_gtt_bind_object(obj, obj->cache_level);
3078 obj->pin_mappable |= map_and_fenceable;
3084 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3086 BUG_ON(obj->pin_count == 0);
3087 BUG_ON(obj->gtt_space == NULL);
3089 if (--obj->pin_count == 0)
3090 obj->pin_mappable = false;
3094 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3095 struct drm_file *file)
3097 struct drm_i915_gem_pin *args = data;
3098 struct drm_i915_gem_object *obj;
3101 ret = i915_mutex_lock_interruptible(dev);
3105 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3106 if (&obj->base == NULL) {
3111 if (obj->madv != I915_MADV_WILLNEED) {
3112 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3117 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3118 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3124 obj->user_pin_count++;
3125 obj->pin_filp = file;
3126 if (obj->user_pin_count == 1) {
3127 ret = i915_gem_object_pin(obj, args->alignment, true);
3132 /* XXX - flush the CPU caches for pinned objects
3133 * as the X server doesn't manage domains yet
3135 i915_gem_object_flush_cpu_write_domain(obj);
3136 args->offset = obj->gtt_offset;
3138 drm_gem_object_unreference(&obj->base);
3140 mutex_unlock(&dev->struct_mutex);
3145 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3146 struct drm_file *file)
3148 struct drm_i915_gem_pin *args = data;
3149 struct drm_i915_gem_object *obj;
3152 ret = i915_mutex_lock_interruptible(dev);
3156 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3157 if (&obj->base == NULL) {
3162 if (obj->pin_filp != file) {
3163 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3168 obj->user_pin_count--;
3169 if (obj->user_pin_count == 0) {
3170 obj->pin_filp = NULL;
3171 i915_gem_object_unpin(obj);
3175 drm_gem_object_unreference(&obj->base);
3177 mutex_unlock(&dev->struct_mutex);
3182 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3183 struct drm_file *file)
3185 struct drm_i915_gem_busy *args = data;
3186 struct drm_i915_gem_object *obj;
3189 ret = i915_mutex_lock_interruptible(dev);
3193 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3194 if (&obj->base == NULL) {
3199 /* Count all active objects as busy, even if they are currently not used
3200 * by the gpu. Users of this interface expect objects to eventually
3201 * become non-busy without any further actions, therefore emit any
3202 * necessary flushes here.
3204 args->busy = obj->active;
3206 /* Unconditionally flush objects, even when the gpu still uses this
3207 * object. Userspace calling this function indicates that it wants to
3208 * use this buffer rather sooner than later, so issuing the required
3209 * flush earlier is beneficial.
3211 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3212 ret = i915_gem_flush_ring(obj->ring,
3213 0, obj->base.write_domain);
3215 ret = i915_gem_check_olr(obj->ring,
3216 obj->last_rendering_seqno);
3219 /* Update the active list for the hardware's current position.
3220 * Otherwise this only updates on a delayed timer or when irqs
3221 * are actually unmasked, and our working set ends up being
3222 * larger than required.
3224 i915_gem_retire_requests_ring(obj->ring);
3226 args->busy = obj->active;
3229 drm_gem_object_unreference(&obj->base);
3231 mutex_unlock(&dev->struct_mutex);
3236 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3237 struct drm_file *file_priv)
3239 return i915_gem_ring_throttle(dev, file_priv);
3243 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3244 struct drm_file *file_priv)
3246 struct drm_i915_gem_madvise *args = data;
3247 struct drm_i915_gem_object *obj;
3250 switch (args->madv) {
3251 case I915_MADV_DONTNEED:
3252 case I915_MADV_WILLNEED:
3258 ret = i915_mutex_lock_interruptible(dev);
3262 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3263 if (&obj->base == NULL) {
3268 if (obj->pin_count) {
3273 if (obj->madv != __I915_MADV_PURGED)
3274 obj->madv = args->madv;
3276 /* if the object is no longer bound, discard its backing storage */
3277 if (i915_gem_object_is_purgeable(obj) &&
3278 obj->gtt_space == NULL)
3279 i915_gem_object_truncate(obj);
3281 args->retained = obj->madv != __I915_MADV_PURGED;
3284 drm_gem_object_unreference(&obj->base);
3286 mutex_unlock(&dev->struct_mutex);
3290 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294 struct drm_i915_gem_object *obj;
3295 struct address_space *mapping;
3297 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3301 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3306 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3307 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3309 i915_gem_info_add_obj(dev_priv, size);
3311 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3312 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3315 /* On some devices, we can have the GPU use the LLC (the CPU
3316 * cache) for about a 10% performance improvement
3317 * compared to uncached. Graphics requests other than
3318 * display scanout are coherent with the CPU in
3319 * accessing this cache. This means in this mode we
3320 * don't need to clflush on the CPU side, and on the
3321 * GPU side we only need to flush internal caches to
3322 * get data visible to the CPU.
3324 * However, we maintain the display planes as UC, and so
3325 * need to rebind when first used as such.
3327 obj->cache_level = I915_CACHE_LLC;
3329 obj->cache_level = I915_CACHE_NONE;
3331 obj->base.driver_private = NULL;
3332 obj->fence_reg = I915_FENCE_REG_NONE;
3333 INIT_LIST_HEAD(&obj->mm_list);
3334 INIT_LIST_HEAD(&obj->gtt_list);
3335 INIT_LIST_HEAD(&obj->ring_list);
3336 INIT_LIST_HEAD(&obj->exec_list);
3337 INIT_LIST_HEAD(&obj->gpu_write_list);
3338 obj->madv = I915_MADV_WILLNEED;
3339 /* Avoid an unnecessary call to unbind on the first bind. */
3340 obj->map_and_fenceable = true;
3345 int i915_gem_init_object(struct drm_gem_object *obj)
3352 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3354 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3355 struct drm_device *dev = obj->base.dev;
3356 drm_i915_private_t *dev_priv = dev->dev_private;
3358 trace_i915_gem_object_destroy(obj);
3360 if (gem_obj->import_attach)
3361 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3364 i915_gem_detach_phys_object(dev, obj);
3367 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3368 bool was_interruptible;
3370 was_interruptible = dev_priv->mm.interruptible;
3371 dev_priv->mm.interruptible = false;
3373 WARN_ON(i915_gem_object_unbind(obj));
3375 dev_priv->mm.interruptible = was_interruptible;
3378 if (obj->base.map_list.map)
3379 drm_gem_free_mmap_offset(&obj->base);
3381 drm_gem_object_release(&obj->base);
3382 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3389 i915_gem_idle(struct drm_device *dev)
3391 drm_i915_private_t *dev_priv = dev->dev_private;
3394 mutex_lock(&dev->struct_mutex);
3396 if (dev_priv->mm.suspended) {
3397 mutex_unlock(&dev->struct_mutex);
3401 ret = i915_gpu_idle(dev);
3403 mutex_unlock(&dev->struct_mutex);
3406 i915_gem_retire_requests(dev);
3408 /* Under UMS, be paranoid and evict. */
3409 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3410 i915_gem_evict_everything(dev, false);
3412 i915_gem_reset_fences(dev);
3414 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3415 * We need to replace this with a semaphore, or something.
3416 * And not confound mm.suspended!
3418 dev_priv->mm.suspended = 1;
3419 del_timer_sync(&dev_priv->hangcheck_timer);
3421 i915_kernel_lost_context(dev);
3422 i915_gem_cleanup_ringbuffer(dev);
3424 mutex_unlock(&dev->struct_mutex);
3426 /* Cancel the retire work handler, which should be idle now. */
3427 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3432 void i915_gem_init_swizzling(struct drm_device *dev)
3434 drm_i915_private_t *dev_priv = dev->dev_private;
3436 if (INTEL_INFO(dev)->gen < 5 ||
3437 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3440 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3441 DISP_TILE_SURFACE_SWIZZLING);
3446 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3448 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3450 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3453 void i915_gem_init_ppgtt(struct drm_device *dev)
3455 drm_i915_private_t *dev_priv = dev->dev_private;
3457 struct intel_ring_buffer *ring;
3458 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3459 uint32_t __iomem *pd_addr;
3463 if (!dev_priv->mm.aliasing_ppgtt)
3467 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3468 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3471 if (dev_priv->mm.gtt->needs_dmar)
3472 pt_addr = ppgtt->pt_dma_addr[i];
3474 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3476 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3477 pd_entry |= GEN6_PDE_VALID;
3479 writel(pd_entry, pd_addr + i);
3483 pd_offset = ppgtt->pd_offset;
3484 pd_offset /= 64; /* in cachelines, */
3487 if (INTEL_INFO(dev)->gen == 6) {
3488 uint32_t ecochk, gab_ctl, ecobits;
3490 ecobits = I915_READ(GAC_ECO_BITS);
3491 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3493 gab_ctl = I915_READ(GAB_CTL);
3494 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3496 ecochk = I915_READ(GAM_ECOCHK);
3497 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3498 ECOCHK_PPGTT_CACHE64B);
3499 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3500 } else if (INTEL_INFO(dev)->gen >= 7) {
3501 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3502 /* GFX_MODE is per-ring on gen7+ */
3505 for_each_ring(ring, dev_priv, i) {
3506 if (INTEL_INFO(dev)->gen >= 7)
3507 I915_WRITE(RING_MODE_GEN7(ring),
3508 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3510 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3511 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3516 i915_gem_init_hw(struct drm_device *dev)
3518 drm_i915_private_t *dev_priv = dev->dev_private;
3521 i915_gem_init_swizzling(dev);
3523 ret = intel_init_render_ring_buffer(dev);
3528 ret = intel_init_bsd_ring_buffer(dev);
3530 goto cleanup_render_ring;
3534 ret = intel_init_blt_ring_buffer(dev);
3536 goto cleanup_bsd_ring;
3539 dev_priv->next_seqno = 1;
3541 i915_gem_init_ppgtt(dev);
3546 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3547 cleanup_render_ring:
3548 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3553 intel_enable_ppgtt(struct drm_device *dev)
3555 if (i915_enable_ppgtt >= 0)
3556 return i915_enable_ppgtt;
3558 #ifdef CONFIG_INTEL_IOMMU
3559 /* Disable ppgtt on SNB if VT-d is on. */
3560 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3567 int i915_gem_init(struct drm_device *dev)
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 unsigned long gtt_size, mappable_size;
3573 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3574 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3576 mutex_lock(&dev->struct_mutex);
3577 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3578 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3579 * aperture accordingly when using aliasing ppgtt. */
3580 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3582 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3584 ret = i915_gem_init_aliasing_ppgtt(dev);
3586 mutex_unlock(&dev->struct_mutex);
3590 /* Let GEM Manage all of the aperture.
3592 * However, leave one page at the end still bound to the scratch
3593 * page. There are a number of places where the hardware
3594 * apparently prefetches past the end of the object, and we've
3595 * seen multiple hangs with the GPU head pointer stuck in a
3596 * batchbuffer bound at the last page of the aperture. One page
3597 * should be enough to keep any prefetching inside of the
3600 i915_gem_init_global_gtt(dev, 0, mappable_size,
3604 ret = i915_gem_init_hw(dev);
3605 mutex_unlock(&dev->struct_mutex);
3607 i915_gem_cleanup_aliasing_ppgtt(dev);
3611 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3612 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3613 dev_priv->dri1.allow_batchbuffer = 1;
3618 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3620 drm_i915_private_t *dev_priv = dev->dev_private;
3621 struct intel_ring_buffer *ring;
3624 for_each_ring(ring, dev_priv, i)
3625 intel_cleanup_ring_buffer(ring);
3629 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3630 struct drm_file *file_priv)
3632 drm_i915_private_t *dev_priv = dev->dev_private;
3635 if (drm_core_check_feature(dev, DRIVER_MODESET))
3638 if (atomic_read(&dev_priv->mm.wedged)) {
3639 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3640 atomic_set(&dev_priv->mm.wedged, 0);
3643 mutex_lock(&dev->struct_mutex);
3644 dev_priv->mm.suspended = 0;
3646 ret = i915_gem_init_hw(dev);
3648 mutex_unlock(&dev->struct_mutex);
3652 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3653 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3654 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3655 mutex_unlock(&dev->struct_mutex);
3657 ret = drm_irq_install(dev);
3659 goto cleanup_ringbuffer;
3664 mutex_lock(&dev->struct_mutex);
3665 i915_gem_cleanup_ringbuffer(dev);
3666 dev_priv->mm.suspended = 1;
3667 mutex_unlock(&dev->struct_mutex);
3673 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3674 struct drm_file *file_priv)
3676 if (drm_core_check_feature(dev, DRIVER_MODESET))
3679 drm_irq_uninstall(dev);
3680 return i915_gem_idle(dev);
3684 i915_gem_lastclose(struct drm_device *dev)
3688 if (drm_core_check_feature(dev, DRIVER_MODESET))
3691 ret = i915_gem_idle(dev);
3693 DRM_ERROR("failed to idle hardware: %d\n", ret);
3697 init_ring_lists(struct intel_ring_buffer *ring)
3699 INIT_LIST_HEAD(&ring->active_list);
3700 INIT_LIST_HEAD(&ring->request_list);
3701 INIT_LIST_HEAD(&ring->gpu_write_list);
3705 i915_gem_load(struct drm_device *dev)
3708 drm_i915_private_t *dev_priv = dev->dev_private;
3710 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3711 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3712 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3713 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3714 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3715 for (i = 0; i < I915_NUM_RINGS; i++)
3716 init_ring_lists(&dev_priv->ring[i]);
3717 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3718 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3719 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3720 i915_gem_retire_work_handler);
3721 init_completion(&dev_priv->error_completion);
3723 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3725 I915_WRITE(MI_ARB_STATE,
3726 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3729 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3731 /* Old X drivers will take 0-2 for front, back, depth buffers */
3732 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3733 dev_priv->fence_reg_start = 3;
3735 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3736 dev_priv->num_fence_regs = 16;
3738 dev_priv->num_fence_regs = 8;
3740 /* Initialize fence registers to zero */
3741 i915_gem_reset_fences(dev);
3743 i915_gem_detect_bit_6_swizzle(dev);
3744 init_waitqueue_head(&dev_priv->pending_flip_queue);
3746 dev_priv->mm.interruptible = true;
3748 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3749 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3750 register_shrinker(&dev_priv->mm.inactive_shrinker);
3754 * Create a physically contiguous memory object for this object
3755 * e.g. for cursor + overlay regs
3757 static int i915_gem_init_phys_object(struct drm_device *dev,
3758 int id, int size, int align)
3760 drm_i915_private_t *dev_priv = dev->dev_private;
3761 struct drm_i915_gem_phys_object *phys_obj;
3764 if (dev_priv->mm.phys_objs[id - 1] || !size)
3767 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3773 phys_obj->handle = drm_pci_alloc(dev, size, align);
3774 if (!phys_obj->handle) {
3779 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3782 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3790 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3792 drm_i915_private_t *dev_priv = dev->dev_private;
3793 struct drm_i915_gem_phys_object *phys_obj;
3795 if (!dev_priv->mm.phys_objs[id - 1])
3798 phys_obj = dev_priv->mm.phys_objs[id - 1];
3799 if (phys_obj->cur_obj) {
3800 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3804 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3806 drm_pci_free(dev, phys_obj->handle);
3808 dev_priv->mm.phys_objs[id - 1] = NULL;
3811 void i915_gem_free_all_phys_object(struct drm_device *dev)
3815 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3816 i915_gem_free_phys_object(dev, i);
3819 void i915_gem_detach_phys_object(struct drm_device *dev,
3820 struct drm_i915_gem_object *obj)
3822 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3829 vaddr = obj->phys_obj->handle->vaddr;
3831 page_count = obj->base.size / PAGE_SIZE;
3832 for (i = 0; i < page_count; i++) {
3833 struct page *page = shmem_read_mapping_page(mapping, i);
3834 if (!IS_ERR(page)) {
3835 char *dst = kmap_atomic(page);
3836 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3839 drm_clflush_pages(&page, 1);
3841 set_page_dirty(page);
3842 mark_page_accessed(page);
3843 page_cache_release(page);
3846 intel_gtt_chipset_flush();
3848 obj->phys_obj->cur_obj = NULL;
3849 obj->phys_obj = NULL;
3853 i915_gem_attach_phys_object(struct drm_device *dev,
3854 struct drm_i915_gem_object *obj,
3858 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3859 drm_i915_private_t *dev_priv = dev->dev_private;
3864 if (id > I915_MAX_PHYS_OBJECT)
3867 if (obj->phys_obj) {
3868 if (obj->phys_obj->id == id)
3870 i915_gem_detach_phys_object(dev, obj);
3873 /* create a new object */
3874 if (!dev_priv->mm.phys_objs[id - 1]) {
3875 ret = i915_gem_init_phys_object(dev, id,
3876 obj->base.size, align);
3878 DRM_ERROR("failed to init phys object %d size: %zu\n",
3879 id, obj->base.size);
3884 /* bind to the object */
3885 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3886 obj->phys_obj->cur_obj = obj;
3888 page_count = obj->base.size / PAGE_SIZE;
3890 for (i = 0; i < page_count; i++) {
3894 page = shmem_read_mapping_page(mapping, i);
3896 return PTR_ERR(page);
3898 src = kmap_atomic(page);
3899 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3900 memcpy(dst, src, PAGE_SIZE);
3903 mark_page_accessed(page);
3904 page_cache_release(page);
3911 i915_gem_phys_pwrite(struct drm_device *dev,
3912 struct drm_i915_gem_object *obj,
3913 struct drm_i915_gem_pwrite *args,
3914 struct drm_file *file_priv)
3916 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3917 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3919 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3920 unsigned long unwritten;
3922 /* The physical object once assigned is fixed for the lifetime
3923 * of the obj, so we can safely drop the lock and continue
3926 mutex_unlock(&dev->struct_mutex);
3927 unwritten = copy_from_user(vaddr, user_data, args->size);
3928 mutex_lock(&dev->struct_mutex);
3933 intel_gtt_chipset_flush();
3937 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3939 struct drm_i915_file_private *file_priv = file->driver_priv;
3941 /* Clean up our request list when the client is going away, so that
3942 * later retire_requests won't dereference our soon-to-be-gone
3945 spin_lock(&file_priv->mm.lock);
3946 while (!list_empty(&file_priv->mm.request_list)) {
3947 struct drm_i915_gem_request *request;
3949 request = list_first_entry(&file_priv->mm.request_list,
3950 struct drm_i915_gem_request,
3952 list_del(&request->client_list);
3953 request->file_priv = NULL;
3955 spin_unlock(&file_priv->mm.lock);
3959 i915_gpu_is_active(struct drm_device *dev)
3961 drm_i915_private_t *dev_priv = dev->dev_private;
3964 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3965 list_empty(&dev_priv->mm.active_list);
3967 return !lists_empty;
3971 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
3973 struct drm_i915_private *dev_priv =
3974 container_of(shrinker,
3975 struct drm_i915_private,
3976 mm.inactive_shrinker);
3977 struct drm_device *dev = dev_priv->dev;
3978 struct drm_i915_gem_object *obj, *next;
3979 int nr_to_scan = sc->nr_to_scan;
3982 if (!mutex_trylock(&dev->struct_mutex))
3985 /* "fast-path" to count number of available objects */
3986 if (nr_to_scan == 0) {
3988 list_for_each_entry(obj,
3989 &dev_priv->mm.inactive_list,
3992 mutex_unlock(&dev->struct_mutex);
3993 return cnt / 100 * sysctl_vfs_cache_pressure;
3997 /* first scan for clean buffers */
3998 i915_gem_retire_requests(dev);
4000 list_for_each_entry_safe(obj, next,
4001 &dev_priv->mm.inactive_list,
4003 if (i915_gem_object_is_purgeable(obj)) {
4004 if (i915_gem_object_unbind(obj) == 0 &&
4010 /* second pass, evict/count anything still on the inactive list */
4012 list_for_each_entry_safe(obj, next,
4013 &dev_priv->mm.inactive_list,
4016 i915_gem_object_unbind(obj) == 0)
4022 if (nr_to_scan && i915_gpu_is_active(dev)) {
4024 * We are desperate for pages, so as a last resort, wait
4025 * for the GPU to finish and discard whatever we can.
4026 * This has a dramatic impact to reduce the number of
4027 * OOM-killer events whilst running the GPU aggressively.
4029 if (i915_gpu_idle(dev) == 0)
4032 mutex_unlock(&dev->struct_mutex);
4033 return cnt / 100 * sysctl_vfs_cache_pressure;