2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "intel_drv.h"
33 #include <linux/swap.h>
34 #include <linux/pci.h>
36 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
56 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59 drm_i915_private_t *dev_priv = dev->dev_private;
62 (start & (PAGE_SIZE - 1)) != 0 ||
63 (end & (PAGE_SIZE - 1)) != 0) {
67 drm_mm_init(&dev_priv->mm.gtt_space, start,
70 dev->gtt_total = (uint32_t) (end - start);
76 i915_gem_init_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
79 struct drm_i915_gem_init *args = data;
82 mutex_lock(&dev->struct_mutex);
83 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
84 mutex_unlock(&dev->struct_mutex);
90 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
93 struct drm_i915_gem_get_aperture *args = data;
95 if (!(dev->driver->driver_features & DRIVER_GEM))
98 args->aper_size = dev->gtt_total;
99 args->aper_available_size = (args->aper_size -
100 atomic_read(&dev->pin_memory));
107 * Creates a new mm object and returns a handle to it.
110 i915_gem_create_ioctl(struct drm_device *dev, void *data,
111 struct drm_file *file_priv)
113 struct drm_i915_gem_create *args = data;
114 struct drm_gem_object *obj;
118 args->size = roundup(args->size, PAGE_SIZE);
120 /* Allocate the new object */
121 obj = drm_gem_object_alloc(dev, args->size);
125 ret = drm_gem_handle_create(file_priv, obj, &handle);
126 mutex_lock(&dev->struct_mutex);
127 drm_gem_object_handle_unreference(obj);
128 mutex_unlock(&dev->struct_mutex);
133 args->handle = handle;
139 fast_shmem_read(struct page **pages,
140 loff_t page_base, int page_offset,
147 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
151 kunmap_atomic(vaddr, KM_USER0);
159 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
161 drm_i915_private_t *dev_priv = obj->dev->dev_private;
162 struct drm_i915_gem_object *obj_priv = obj->driver_private;
164 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
165 obj_priv->tiling_mode != I915_TILING_NONE;
169 slow_shmem_copy(struct page *dst_page,
171 struct page *src_page,
175 char *dst_vaddr, *src_vaddr;
177 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
178 if (dst_vaddr == NULL)
181 src_vaddr = kmap_atomic(src_page, KM_USER1);
182 if (src_vaddr == NULL) {
183 kunmap_atomic(dst_vaddr, KM_USER0);
187 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
189 kunmap_atomic(src_vaddr, KM_USER1);
190 kunmap_atomic(dst_vaddr, KM_USER0);
196 slow_shmem_bit17_copy(struct page *gpu_page,
198 struct page *cpu_page,
203 char *gpu_vaddr, *cpu_vaddr;
205 /* Use the unswizzled path if this page isn't affected. */
206 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
208 return slow_shmem_copy(cpu_page, cpu_offset,
209 gpu_page, gpu_offset, length);
211 return slow_shmem_copy(gpu_page, gpu_offset,
212 cpu_page, cpu_offset, length);
215 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
216 if (gpu_vaddr == NULL)
219 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
220 if (cpu_vaddr == NULL) {
221 kunmap_atomic(gpu_vaddr, KM_USER0);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
247 kunmap_atomic(cpu_vaddr, KM_USER1);
248 kunmap_atomic(gpu_vaddr, KM_USER0);
254 * This is the fast shmem pread path, which attempts to copy_from_user directly
255 * from the backing pages of the object to the user's address space. On a
256 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
259 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
260 struct drm_i915_gem_pread *args,
261 struct drm_file *file_priv)
263 struct drm_i915_gem_object *obj_priv = obj->driver_private;
265 loff_t offset, page_base;
266 char __user *user_data;
267 int page_offset, page_length;
270 user_data = (char __user *) (uintptr_t) args->data_ptr;
273 mutex_lock(&dev->struct_mutex);
275 ret = i915_gem_object_get_pages(obj);
279 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
284 obj_priv = obj->driver_private;
285 offset = args->offset;
288 /* Operation in this page
290 * page_base = page offset within aperture
291 * page_offset = offset within page
292 * page_length = bytes to copy for this page
294 page_base = (offset & ~(PAGE_SIZE-1));
295 page_offset = offset & (PAGE_SIZE-1);
296 page_length = remain;
297 if ((page_offset + remain) > PAGE_SIZE)
298 page_length = PAGE_SIZE - page_offset;
300 ret = fast_shmem_read(obj_priv->pages,
301 page_base, page_offset,
302 user_data, page_length);
306 remain -= page_length;
307 user_data += page_length;
308 offset += page_length;
312 i915_gem_object_put_pages(obj);
314 mutex_unlock(&dev->struct_mutex);
320 * This is the fallback shmem pread path, which allocates temporary storage
321 * in kernel space to copy_to_user into outside of the struct_mutex, so we
322 * can copy out of the object's backing pages while holding the struct mutex
323 * and not take page faults.
326 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
327 struct drm_i915_gem_pread *args,
328 struct drm_file *file_priv)
330 struct drm_i915_gem_object *obj_priv = obj->driver_private;
331 struct mm_struct *mm = current->mm;
332 struct page **user_pages;
334 loff_t offset, pinned_pages, i;
335 loff_t first_data_page, last_data_page, num_pages;
336 int shmem_page_index, shmem_page_offset;
337 int data_page_index, data_page_offset;
340 uint64_t data_ptr = args->data_ptr;
341 int do_bit17_swizzling;
345 /* Pin the user pages containing the data. We can't fault while
346 * holding the struct mutex, yet we want to hold it while
347 * dereferencing the user data.
349 first_data_page = data_ptr / PAGE_SIZE;
350 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
351 num_pages = last_data_page - first_data_page + 1;
353 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
354 if (user_pages == NULL)
357 down_read(&mm->mmap_sem);
358 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
359 num_pages, 1, 0, user_pages, NULL);
360 up_read(&mm->mmap_sem);
361 if (pinned_pages < num_pages) {
363 goto fail_put_user_pages;
366 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
368 mutex_lock(&dev->struct_mutex);
370 ret = i915_gem_object_get_pages(obj);
374 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
379 obj_priv = obj->driver_private;
380 offset = args->offset;
383 /* Operation in this page
385 * shmem_page_index = page number within shmem file
386 * shmem_page_offset = offset within page in shmem file
387 * data_page_index = page number in get_user_pages return
388 * data_page_offset = offset with data_page_index page.
389 * page_length = bytes to copy for this page
391 shmem_page_index = offset / PAGE_SIZE;
392 shmem_page_offset = offset & ~PAGE_MASK;
393 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
394 data_page_offset = data_ptr & ~PAGE_MASK;
396 page_length = remain;
397 if ((shmem_page_offset + page_length) > PAGE_SIZE)
398 page_length = PAGE_SIZE - shmem_page_offset;
399 if ((data_page_offset + page_length) > PAGE_SIZE)
400 page_length = PAGE_SIZE - data_page_offset;
402 if (do_bit17_swizzling) {
403 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
405 user_pages[data_page_index],
410 ret = slow_shmem_copy(user_pages[data_page_index],
412 obj_priv->pages[shmem_page_index],
419 remain -= page_length;
420 data_ptr += page_length;
421 offset += page_length;
425 i915_gem_object_put_pages(obj);
427 mutex_unlock(&dev->struct_mutex);
429 for (i = 0; i < pinned_pages; i++) {
430 SetPageDirty(user_pages[i]);
431 page_cache_release(user_pages[i]);
433 drm_free_large(user_pages);
439 * Reads data from the object referenced by handle.
441 * On error, the contents of *data are undefined.
444 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
445 struct drm_file *file_priv)
447 struct drm_i915_gem_pread *args = data;
448 struct drm_gem_object *obj;
449 struct drm_i915_gem_object *obj_priv;
452 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
455 obj_priv = obj->driver_private;
457 /* Bounds check source.
459 * XXX: This could use review for overflow issues...
461 if (args->offset > obj->size || args->size > obj->size ||
462 args->offset + args->size > obj->size) {
463 drm_gem_object_unreference(obj);
467 if (i915_gem_object_needs_bit17_swizzle(obj)) {
468 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
470 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
472 ret = i915_gem_shmem_pread_slow(dev, obj, args,
476 drm_gem_object_unreference(obj);
481 /* This is the fast write path which cannot handle
482 * page faults in the source data
486 fast_user_write(struct io_mapping *mapping,
487 loff_t page_base, int page_offset,
488 char __user *user_data,
492 unsigned long unwritten;
494 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
495 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
497 io_mapping_unmap_atomic(vaddr_atomic);
503 /* Here's the write path which can sleep for
508 slow_kernel_write(struct io_mapping *mapping,
509 loff_t gtt_base, int gtt_offset,
510 struct page *user_page, int user_offset,
513 char *src_vaddr, *dst_vaddr;
514 unsigned long unwritten;
516 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
517 src_vaddr = kmap_atomic(user_page, KM_USER1);
518 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
519 src_vaddr + user_offset,
521 kunmap_atomic(src_vaddr, KM_USER1);
522 io_mapping_unmap_atomic(dst_vaddr);
529 fast_shmem_write(struct page **pages,
530 loff_t page_base, int page_offset,
535 unsigned long unwritten;
537 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
540 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
541 kunmap_atomic(vaddr, KM_USER0);
549 * This is the fast pwrite path, where we copy the data directly from the
550 * user into the GTT, uncached.
553 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
554 struct drm_i915_gem_pwrite *args,
555 struct drm_file *file_priv)
557 struct drm_i915_gem_object *obj_priv = obj->driver_private;
558 drm_i915_private_t *dev_priv = dev->dev_private;
560 loff_t offset, page_base;
561 char __user *user_data;
562 int page_offset, page_length;
565 user_data = (char __user *) (uintptr_t) args->data_ptr;
567 if (!access_ok(VERIFY_READ, user_data, remain))
571 mutex_lock(&dev->struct_mutex);
572 ret = i915_gem_object_pin(obj, 0);
574 mutex_unlock(&dev->struct_mutex);
577 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
581 obj_priv = obj->driver_private;
582 offset = obj_priv->gtt_offset + args->offset;
585 /* Operation in this page
587 * page_base = page offset within aperture
588 * page_offset = offset within page
589 * page_length = bytes to copy for this page
591 page_base = (offset & ~(PAGE_SIZE-1));
592 page_offset = offset & (PAGE_SIZE-1);
593 page_length = remain;
594 if ((page_offset + remain) > PAGE_SIZE)
595 page_length = PAGE_SIZE - page_offset;
597 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
598 page_offset, user_data, page_length);
600 /* If we get a fault while copying data, then (presumably) our
601 * source page isn't available. Return the error and we'll
602 * retry in the slow path.
607 remain -= page_length;
608 user_data += page_length;
609 offset += page_length;
613 i915_gem_object_unpin(obj);
614 mutex_unlock(&dev->struct_mutex);
620 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
621 * the memory and maps it using kmap_atomic for copying.
623 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
624 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
627 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
628 struct drm_i915_gem_pwrite *args,
629 struct drm_file *file_priv)
631 struct drm_i915_gem_object *obj_priv = obj->driver_private;
632 drm_i915_private_t *dev_priv = dev->dev_private;
634 loff_t gtt_page_base, offset;
635 loff_t first_data_page, last_data_page, num_pages;
636 loff_t pinned_pages, i;
637 struct page **user_pages;
638 struct mm_struct *mm = current->mm;
639 int gtt_page_offset, data_page_offset, data_page_index, page_length;
641 uint64_t data_ptr = args->data_ptr;
645 /* Pin the user pages containing the data. We can't fault while
646 * holding the struct mutex, and all of the pwrite implementations
647 * want to hold it while dereferencing the user data.
649 first_data_page = data_ptr / PAGE_SIZE;
650 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
651 num_pages = last_data_page - first_data_page + 1;
653 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
654 if (user_pages == NULL)
657 down_read(&mm->mmap_sem);
658 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
659 num_pages, 0, 0, user_pages, NULL);
660 up_read(&mm->mmap_sem);
661 if (pinned_pages < num_pages) {
663 goto out_unpin_pages;
666 mutex_lock(&dev->struct_mutex);
667 ret = i915_gem_object_pin(obj, 0);
671 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673 goto out_unpin_object;
675 obj_priv = obj->driver_private;
676 offset = obj_priv->gtt_offset + args->offset;
679 /* Operation in this page
681 * gtt_page_base = page offset within aperture
682 * gtt_page_offset = offset within page in aperture
683 * data_page_index = page number in get_user_pages return
684 * data_page_offset = offset with data_page_index page.
685 * page_length = bytes to copy for this page
687 gtt_page_base = offset & PAGE_MASK;
688 gtt_page_offset = offset & ~PAGE_MASK;
689 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
690 data_page_offset = data_ptr & ~PAGE_MASK;
692 page_length = remain;
693 if ((gtt_page_offset + page_length) > PAGE_SIZE)
694 page_length = PAGE_SIZE - gtt_page_offset;
695 if ((data_page_offset + page_length) > PAGE_SIZE)
696 page_length = PAGE_SIZE - data_page_offset;
698 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
699 gtt_page_base, gtt_page_offset,
700 user_pages[data_page_index],
704 /* If we get a fault while copying data, then (presumably) our
705 * source page isn't available. Return the error and we'll
706 * retry in the slow path.
709 goto out_unpin_object;
711 remain -= page_length;
712 offset += page_length;
713 data_ptr += page_length;
717 i915_gem_object_unpin(obj);
719 mutex_unlock(&dev->struct_mutex);
721 for (i = 0; i < pinned_pages; i++)
722 page_cache_release(user_pages[i]);
723 drm_free_large(user_pages);
729 * This is the fast shmem pwrite path, which attempts to directly
730 * copy_from_user into the kmapped pages backing the object.
733 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
734 struct drm_i915_gem_pwrite *args,
735 struct drm_file *file_priv)
737 struct drm_i915_gem_object *obj_priv = obj->driver_private;
739 loff_t offset, page_base;
740 char __user *user_data;
741 int page_offset, page_length;
744 user_data = (char __user *) (uintptr_t) args->data_ptr;
747 mutex_lock(&dev->struct_mutex);
749 ret = i915_gem_object_get_pages(obj);
753 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
757 obj_priv = obj->driver_private;
758 offset = args->offset;
762 /* Operation in this page
764 * page_base = page offset within aperture
765 * page_offset = offset within page
766 * page_length = bytes to copy for this page
768 page_base = (offset & ~(PAGE_SIZE-1));
769 page_offset = offset & (PAGE_SIZE-1);
770 page_length = remain;
771 if ((page_offset + remain) > PAGE_SIZE)
772 page_length = PAGE_SIZE - page_offset;
774 ret = fast_shmem_write(obj_priv->pages,
775 page_base, page_offset,
776 user_data, page_length);
780 remain -= page_length;
781 user_data += page_length;
782 offset += page_length;
786 i915_gem_object_put_pages(obj);
788 mutex_unlock(&dev->struct_mutex);
794 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
795 * the memory and maps it using kmap_atomic for copying.
797 * This avoids taking mmap_sem for faulting on the user's address while the
798 * struct_mutex is held.
801 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
802 struct drm_i915_gem_pwrite *args,
803 struct drm_file *file_priv)
805 struct drm_i915_gem_object *obj_priv = obj->driver_private;
806 struct mm_struct *mm = current->mm;
807 struct page **user_pages;
809 loff_t offset, pinned_pages, i;
810 loff_t first_data_page, last_data_page, num_pages;
811 int shmem_page_index, shmem_page_offset;
812 int data_page_index, data_page_offset;
815 uint64_t data_ptr = args->data_ptr;
816 int do_bit17_swizzling;
820 /* Pin the user pages containing the data. We can't fault while
821 * holding the struct mutex, and all of the pwrite implementations
822 * want to hold it while dereferencing the user data.
824 first_data_page = data_ptr / PAGE_SIZE;
825 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
826 num_pages = last_data_page - first_data_page + 1;
828 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
829 if (user_pages == NULL)
832 down_read(&mm->mmap_sem);
833 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
834 num_pages, 0, 0, user_pages, NULL);
835 up_read(&mm->mmap_sem);
836 if (pinned_pages < num_pages) {
838 goto fail_put_user_pages;
841 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
843 mutex_lock(&dev->struct_mutex);
845 ret = i915_gem_object_get_pages(obj);
849 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
853 obj_priv = obj->driver_private;
854 offset = args->offset;
858 /* Operation in this page
860 * shmem_page_index = page number within shmem file
861 * shmem_page_offset = offset within page in shmem file
862 * data_page_index = page number in get_user_pages return
863 * data_page_offset = offset with data_page_index page.
864 * page_length = bytes to copy for this page
866 shmem_page_index = offset / PAGE_SIZE;
867 shmem_page_offset = offset & ~PAGE_MASK;
868 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
869 data_page_offset = data_ptr & ~PAGE_MASK;
871 page_length = remain;
872 if ((shmem_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - shmem_page_offset;
874 if ((data_page_offset + page_length) > PAGE_SIZE)
875 page_length = PAGE_SIZE - data_page_offset;
877 if (do_bit17_swizzling) {
878 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
880 user_pages[data_page_index],
885 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
887 user_pages[data_page_index],
894 remain -= page_length;
895 data_ptr += page_length;
896 offset += page_length;
900 i915_gem_object_put_pages(obj);
902 mutex_unlock(&dev->struct_mutex);
904 for (i = 0; i < pinned_pages; i++)
905 page_cache_release(user_pages[i]);
906 drm_free_large(user_pages);
912 * Writes data to the object referenced by handle.
914 * On error, the contents of the buffer that were to be modified are undefined.
917 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
918 struct drm_file *file_priv)
920 struct drm_i915_gem_pwrite *args = data;
921 struct drm_gem_object *obj;
922 struct drm_i915_gem_object *obj_priv;
925 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
928 obj_priv = obj->driver_private;
930 /* Bounds check destination.
932 * XXX: This could use review for overflow issues...
934 if (args->offset > obj->size || args->size > obj->size ||
935 args->offset + args->size > obj->size) {
936 drm_gem_object_unreference(obj);
940 /* We can only do the GTT pwrite on untiled buffers, as otherwise
941 * it would end up going through the fenced access, and we'll get
942 * different detiling behavior between reading and writing.
943 * pread/pwrite currently are reading and writing from the CPU
944 * perspective, requiring manual detiling by the client.
946 if (obj_priv->phys_obj)
947 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
948 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
949 dev->gtt_total != 0) {
950 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
951 if (ret == -EFAULT) {
952 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
955 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
958 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
959 if (ret == -EFAULT) {
960 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
967 DRM_INFO("pwrite failed %d\n", ret);
970 drm_gem_object_unreference(obj);
976 * Called when user space prepares to use an object with the CPU, either
977 * through the mmap ioctl's mapping or a GTT mapping.
980 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv)
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_i915_gem_set_domain *args = data;
985 struct drm_gem_object *obj;
986 struct drm_i915_gem_object *obj_priv;
987 uint32_t read_domains = args->read_domains;
988 uint32_t write_domain = args->write_domain;
991 if (!(dev->driver->driver_features & DRIVER_GEM))
994 /* Only handle setting domains to types used by the CPU. */
995 if (write_domain & I915_GEM_GPU_DOMAINS)
998 if (read_domains & I915_GEM_GPU_DOMAINS)
1001 /* Having something in the write domain implies it's in the read
1002 * domain, and only that read domain. Enforce that in the request.
1004 if (write_domain != 0 && read_domains != write_domain)
1007 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1010 obj_priv = obj->driver_private;
1012 mutex_lock(&dev->struct_mutex);
1014 intel_mark_busy(dev, obj);
1017 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1018 obj, obj->size, read_domains, write_domain);
1020 if (read_domains & I915_GEM_DOMAIN_GTT) {
1021 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1023 /* Update the LRU on the fence for the CPU access that's
1026 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1027 list_move_tail(&obj_priv->fence_list,
1028 &dev_priv->mm.fence_list);
1031 /* Silently promote "you're not bound, there was nothing to do"
1032 * to success, since the client was just asking us to
1033 * make sure everything was done.
1038 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1041 drm_gem_object_unreference(obj);
1042 mutex_unlock(&dev->struct_mutex);
1047 * Called when user space has done writes to this buffer
1050 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv)
1053 struct drm_i915_gem_sw_finish *args = data;
1054 struct drm_gem_object *obj;
1055 struct drm_i915_gem_object *obj_priv;
1058 if (!(dev->driver->driver_features & DRIVER_GEM))
1061 mutex_lock(&dev->struct_mutex);
1062 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1064 mutex_unlock(&dev->struct_mutex);
1069 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1070 __func__, args->handle, obj, obj->size);
1072 obj_priv = obj->driver_private;
1074 /* Pinned buffers may be scanout, so flush the cache */
1075 if (obj_priv->pin_count)
1076 i915_gem_object_flush_cpu_write_domain(obj);
1078 drm_gem_object_unreference(obj);
1079 mutex_unlock(&dev->struct_mutex);
1084 * Maps the contents of an object, returning the address it is mapped
1087 * While the mapping holds a reference on the contents of the object, it doesn't
1088 * imply a ref on the object itself.
1091 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv)
1094 struct drm_i915_gem_mmap *args = data;
1095 struct drm_gem_object *obj;
1099 if (!(dev->driver->driver_features & DRIVER_GEM))
1102 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1106 offset = args->offset;
1108 down_write(¤t->mm->mmap_sem);
1109 addr = do_mmap(obj->filp, 0, args->size,
1110 PROT_READ | PROT_WRITE, MAP_SHARED,
1112 up_write(¤t->mm->mmap_sem);
1113 mutex_lock(&dev->struct_mutex);
1114 drm_gem_object_unreference(obj);
1115 mutex_unlock(&dev->struct_mutex);
1116 if (IS_ERR((void *)addr))
1119 args->addr_ptr = (uint64_t) addr;
1125 * i915_gem_fault - fault a page into the GTT
1126 * vma: VMA in question
1129 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1130 * from userspace. The fault handler takes care of binding the object to
1131 * the GTT (if needed), allocating and programming a fence register (again,
1132 * only if needed based on whether the old reg is still valid or the object
1133 * is tiled) and inserting a new PTE into the faulting process.
1135 * Note that the faulting process may involve evicting existing objects
1136 * from the GTT and/or fence registers to make room. So performance may
1137 * suffer if the GTT working set is large or there are few fence registers
1140 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1142 struct drm_gem_object *obj = vma->vm_private_data;
1143 struct drm_device *dev = obj->dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1146 pgoff_t page_offset;
1149 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1151 /* We don't use vmf->pgoff since that has the fake offset */
1152 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1155 /* Now bind it into the GTT if needed */
1156 mutex_lock(&dev->struct_mutex);
1157 if (!obj_priv->gtt_space) {
1158 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1160 mutex_unlock(&dev->struct_mutex);
1161 return VM_FAULT_SIGBUS;
1164 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1166 mutex_unlock(&dev->struct_mutex);
1167 return VM_FAULT_SIGBUS;
1170 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1173 /* Need a new fence register? */
1174 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1175 ret = i915_gem_object_get_fence_reg(obj);
1177 mutex_unlock(&dev->struct_mutex);
1178 return VM_FAULT_SIGBUS;
1182 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1185 /* Finally, remap it using the new GTT offset */
1186 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1188 mutex_unlock(&dev->struct_mutex);
1193 return VM_FAULT_OOM;
1196 return VM_FAULT_SIGBUS;
1198 return VM_FAULT_NOPAGE;
1203 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1204 * @obj: obj in question
1206 * GEM memory mapping works by handing back to userspace a fake mmap offset
1207 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1208 * up the object based on the offset and sets up the various memory mapping
1211 * This routine allocates and attaches a fake offset for @obj.
1214 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1216 struct drm_device *dev = obj->dev;
1217 struct drm_gem_mm *mm = dev->mm_private;
1218 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1219 struct drm_map_list *list;
1220 struct drm_local_map *map;
1223 /* Set the object up for mmap'ing */
1224 list = &obj->map_list;
1225 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1230 map->type = _DRM_GEM;
1231 map->size = obj->size;
1234 /* Get a DRM GEM mmap offset allocated... */
1235 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1236 obj->size / PAGE_SIZE, 0, 0);
1237 if (!list->file_offset_node) {
1238 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1243 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1244 obj->size / PAGE_SIZE, 0);
1245 if (!list->file_offset_node) {
1250 list->hash.key = list->file_offset_node->start;
1251 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1252 DRM_ERROR("failed to add to map hash\n");
1256 /* By now we should be all set, any drm_mmap request on the offset
1257 * below will get to our mmap & fault handler */
1258 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1263 drm_mm_put_block(list->file_offset_node);
1271 * i915_gem_release_mmap - remove physical page mappings
1272 * @obj: obj in question
1274 * Preserve the reservation of the mmaping with the DRM core code, but
1275 * relinquish ownership of the pages back to the system.
1277 * It is vital that we remove the page mapping if we have mapped a tiled
1278 * object through the GTT and then lose the fence register due to
1279 * resource pressure. Similarly if the object has been moved out of the
1280 * aperture, than pages mapped into userspace must be revoked. Removing the
1281 * mapping will then trigger a page fault on the next user access, allowing
1282 * fixup by i915_gem_fault().
1285 i915_gem_release_mmap(struct drm_gem_object *obj)
1287 struct drm_device *dev = obj->dev;
1288 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1290 if (dev->dev_mapping)
1291 unmap_mapping_range(dev->dev_mapping,
1292 obj_priv->mmap_offset, obj->size, 1);
1296 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1298 struct drm_device *dev = obj->dev;
1299 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1300 struct drm_gem_mm *mm = dev->mm_private;
1301 struct drm_map_list *list;
1303 list = &obj->map_list;
1304 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1306 if (list->file_offset_node) {
1307 drm_mm_put_block(list->file_offset_node);
1308 list->file_offset_node = NULL;
1316 obj_priv->mmap_offset = 0;
1320 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1321 * @obj: object to check
1323 * Return the required GTT alignment for an object, taking into account
1324 * potential fence register mapping if needed.
1327 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1329 struct drm_device *dev = obj->dev;
1330 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1334 * Minimum alignment is 4k (GTT page size), but might be greater
1335 * if a fence register is needed for the object.
1337 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1341 * Previous chips need to be aligned to the size of the smallest
1342 * fence register that can contain the object.
1349 for (i = start; i < obj->size; i <<= 1)
1356 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1358 * @data: GTT mapping ioctl data
1359 * @file_priv: GEM object info
1361 * Simply returns the fake offset to userspace so it can mmap it.
1362 * The mmap call will end up in drm_gem_mmap(), which will set things
1363 * up so we can get faults in the handler above.
1365 * The fault handler will take care of binding the object into the GTT
1366 * (since it may have been evicted to make room for something), allocating
1367 * a fence register, and mapping the appropriate aperture address into
1371 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1372 struct drm_file *file_priv)
1374 struct drm_i915_gem_mmap_gtt *args = data;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 struct drm_gem_object *obj;
1377 struct drm_i915_gem_object *obj_priv;
1380 if (!(dev->driver->driver_features & DRIVER_GEM))
1383 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1387 mutex_lock(&dev->struct_mutex);
1389 obj_priv = obj->driver_private;
1391 if (!obj_priv->mmap_offset) {
1392 ret = i915_gem_create_mmap_offset(obj);
1394 drm_gem_object_unreference(obj);
1395 mutex_unlock(&dev->struct_mutex);
1400 args->offset = obj_priv->mmap_offset;
1402 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1404 /* Make sure the alignment is correct for fence regs etc */
1405 if (obj_priv->agp_mem &&
1406 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1407 drm_gem_object_unreference(obj);
1408 mutex_unlock(&dev->struct_mutex);
1413 * Pull it into the GTT so that we have a page list (makes the
1414 * initial fault faster and any subsequent flushing possible).
1416 if (!obj_priv->agp_mem) {
1417 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1419 drm_gem_object_unreference(obj);
1420 mutex_unlock(&dev->struct_mutex);
1423 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1426 drm_gem_object_unreference(obj);
1427 mutex_unlock(&dev->struct_mutex);
1433 i915_gem_object_put_pages(struct drm_gem_object *obj)
1435 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1436 int page_count = obj->size / PAGE_SIZE;
1439 BUG_ON(obj_priv->pages_refcount == 0);
1441 if (--obj_priv->pages_refcount != 0)
1444 if (obj_priv->tiling_mode != I915_TILING_NONE)
1445 i915_gem_object_save_bit_17_swizzle(obj);
1447 for (i = 0; i < page_count; i++)
1448 if (obj_priv->pages[i] != NULL) {
1449 if (obj_priv->dirty)
1450 set_page_dirty(obj_priv->pages[i]);
1451 mark_page_accessed(obj_priv->pages[i]);
1452 page_cache_release(obj_priv->pages[i]);
1454 obj_priv->dirty = 0;
1456 drm_free_large(obj_priv->pages);
1457 obj_priv->pages = NULL;
1461 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1463 struct drm_device *dev = obj->dev;
1464 drm_i915_private_t *dev_priv = dev->dev_private;
1465 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1467 /* Add a reference if we're newly entering the active list. */
1468 if (!obj_priv->active) {
1469 drm_gem_object_reference(obj);
1470 obj_priv->active = 1;
1472 /* Move from whatever list we were on to the tail of execution. */
1473 spin_lock(&dev_priv->mm.active_list_lock);
1474 list_move_tail(&obj_priv->list,
1475 &dev_priv->mm.active_list);
1476 spin_unlock(&dev_priv->mm.active_list_lock);
1477 obj_priv->last_rendering_seqno = seqno;
1481 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1483 struct drm_device *dev = obj->dev;
1484 drm_i915_private_t *dev_priv = dev->dev_private;
1485 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1487 BUG_ON(!obj_priv->active);
1488 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1489 obj_priv->last_rendering_seqno = 0;
1493 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1495 struct drm_device *dev = obj->dev;
1496 drm_i915_private_t *dev_priv = dev->dev_private;
1497 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1499 i915_verify_inactive(dev, __FILE__, __LINE__);
1500 if (obj_priv->pin_count != 0)
1501 list_del_init(&obj_priv->list);
1503 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1505 obj_priv->last_rendering_seqno = 0;
1506 if (obj_priv->active) {
1507 obj_priv->active = 0;
1508 drm_gem_object_unreference(obj);
1510 i915_verify_inactive(dev, __FILE__, __LINE__);
1514 * Creates a new sequence number, emitting a write of it to the status page
1515 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1517 * Must be called with struct_lock held.
1519 * Returned sequence numbers are nonzero on success.
1522 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1523 uint32_t flush_domains)
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_file_private *i915_file_priv = NULL;
1527 struct drm_i915_gem_request *request;
1532 if (file_priv != NULL)
1533 i915_file_priv = file_priv->driver_priv;
1535 request = kzalloc(sizeof(*request), GFP_KERNEL);
1536 if (request == NULL)
1539 /* Grab the seqno we're going to make this request be, and bump the
1540 * next (skipping 0 so it can be the reserved no-seqno value).
1542 seqno = dev_priv->mm.next_gem_seqno;
1543 dev_priv->mm.next_gem_seqno++;
1544 if (dev_priv->mm.next_gem_seqno == 0)
1545 dev_priv->mm.next_gem_seqno++;
1548 OUT_RING(MI_STORE_DWORD_INDEX);
1549 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1552 OUT_RING(MI_USER_INTERRUPT);
1555 DRM_DEBUG("%d\n", seqno);
1557 request->seqno = seqno;
1558 request->emitted_jiffies = jiffies;
1559 was_empty = list_empty(&dev_priv->mm.request_list);
1560 list_add_tail(&request->list, &dev_priv->mm.request_list);
1561 if (i915_file_priv) {
1562 list_add_tail(&request->client_list,
1563 &i915_file_priv->mm.request_list);
1565 INIT_LIST_HEAD(&request->client_list);
1568 /* Associate any objects on the flushing list matching the write
1569 * domain we're flushing with our flush.
1571 if (flush_domains != 0) {
1572 struct drm_i915_gem_object *obj_priv, *next;
1574 list_for_each_entry_safe(obj_priv, next,
1575 &dev_priv->mm.flushing_list, list) {
1576 struct drm_gem_object *obj = obj_priv->obj;
1578 if ((obj->write_domain & flush_domains) ==
1579 obj->write_domain) {
1580 obj->write_domain = 0;
1581 i915_gem_object_move_to_active(obj, seqno);
1587 if (was_empty && !dev_priv->mm.suspended)
1588 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1593 * Command execution barrier
1595 * Ensures that all commands in the ring are finished
1596 * before signalling the CPU
1599 i915_retire_commands(struct drm_device *dev)
1601 drm_i915_private_t *dev_priv = dev->dev_private;
1602 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1603 uint32_t flush_domains = 0;
1606 /* The sampler always gets flushed on i965 (sigh) */
1608 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1611 OUT_RING(0); /* noop */
1613 return flush_domains;
1617 * Moves buffers associated only with the given active seqno from the active
1618 * to inactive list, potentially freeing them.
1621 i915_gem_retire_request(struct drm_device *dev,
1622 struct drm_i915_gem_request *request)
1624 drm_i915_private_t *dev_priv = dev->dev_private;
1626 /* Move any buffers on the active list that are no longer referenced
1627 * by the ringbuffer to the flushing/inactive lists as appropriate.
1629 spin_lock(&dev_priv->mm.active_list_lock);
1630 while (!list_empty(&dev_priv->mm.active_list)) {
1631 struct drm_gem_object *obj;
1632 struct drm_i915_gem_object *obj_priv;
1634 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1635 struct drm_i915_gem_object,
1637 obj = obj_priv->obj;
1639 /* If the seqno being retired doesn't match the oldest in the
1640 * list, then the oldest in the list must still be newer than
1643 if (obj_priv->last_rendering_seqno != request->seqno)
1647 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1648 __func__, request->seqno, obj);
1651 if (obj->write_domain != 0)
1652 i915_gem_object_move_to_flushing(obj);
1654 /* Take a reference on the object so it won't be
1655 * freed while the spinlock is held. The list
1656 * protection for this spinlock is safe when breaking
1657 * the lock like this since the next thing we do
1658 * is just get the head of the list again.
1660 drm_gem_object_reference(obj);
1661 i915_gem_object_move_to_inactive(obj);
1662 spin_unlock(&dev_priv->mm.active_list_lock);
1663 drm_gem_object_unreference(obj);
1664 spin_lock(&dev_priv->mm.active_list_lock);
1668 spin_unlock(&dev_priv->mm.active_list_lock);
1672 * Returns true if seq1 is later than seq2.
1675 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1677 return (int32_t)(seq1 - seq2) >= 0;
1681 i915_get_gem_seqno(struct drm_device *dev)
1683 drm_i915_private_t *dev_priv = dev->dev_private;
1685 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1689 * This function clears the request list as sequence numbers are passed.
1692 i915_gem_retire_requests(struct drm_device *dev)
1694 drm_i915_private_t *dev_priv = dev->dev_private;
1697 if (!dev_priv->hw_status_page)
1700 seqno = i915_get_gem_seqno(dev);
1702 while (!list_empty(&dev_priv->mm.request_list)) {
1703 struct drm_i915_gem_request *request;
1704 uint32_t retiring_seqno;
1706 request = list_first_entry(&dev_priv->mm.request_list,
1707 struct drm_i915_gem_request,
1709 retiring_seqno = request->seqno;
1711 if (i915_seqno_passed(seqno, retiring_seqno) ||
1712 dev_priv->mm.wedged) {
1713 i915_gem_retire_request(dev, request);
1715 list_del(&request->list);
1716 list_del(&request->client_list);
1724 i915_gem_retire_work_handler(struct work_struct *work)
1726 drm_i915_private_t *dev_priv;
1727 struct drm_device *dev;
1729 dev_priv = container_of(work, drm_i915_private_t,
1730 mm.retire_work.work);
1731 dev = dev_priv->dev;
1733 mutex_lock(&dev->struct_mutex);
1734 i915_gem_retire_requests(dev);
1735 if (!dev_priv->mm.suspended &&
1736 !list_empty(&dev_priv->mm.request_list))
1737 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1738 mutex_unlock(&dev->struct_mutex);
1742 * Waits for a sequence number to be signaled, and cleans up the
1743 * request and object lists appropriately for that event.
1746 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1748 drm_i915_private_t *dev_priv = dev->dev_private;
1754 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1756 ier = I915_READ(DEIER) | I915_READ(GTIER);
1758 ier = I915_READ(IER);
1760 DRM_ERROR("something (likely vbetool) disabled "
1761 "interrupts, re-enabling\n");
1762 i915_driver_irq_preinstall(dev);
1763 i915_driver_irq_postinstall(dev);
1766 dev_priv->mm.waiting_gem_seqno = seqno;
1767 i915_user_irq_get(dev);
1768 ret = wait_event_interruptible(dev_priv->irq_queue,
1769 i915_seqno_passed(i915_get_gem_seqno(dev),
1771 dev_priv->mm.wedged);
1772 i915_user_irq_put(dev);
1773 dev_priv->mm.waiting_gem_seqno = 0;
1775 if (dev_priv->mm.wedged)
1778 if (ret && ret != -ERESTARTSYS)
1779 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1780 __func__, ret, seqno, i915_get_gem_seqno(dev));
1782 /* Directly dispatch request retiring. While we have the work queue
1783 * to handle this, the waiter on a request often wants an associated
1784 * buffer to have made it to the inactive list, and we would need
1785 * a separate wait queue to handle that.
1788 i915_gem_retire_requests(dev);
1794 i915_gem_flush(struct drm_device *dev,
1795 uint32_t invalidate_domains,
1796 uint32_t flush_domains)
1798 drm_i915_private_t *dev_priv = dev->dev_private;
1803 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1804 invalidate_domains, flush_domains);
1807 if (flush_domains & I915_GEM_DOMAIN_CPU)
1808 drm_agp_chipset_flush(dev);
1810 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1812 * read/write caches:
1814 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1815 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1816 * also flushed at 2d versus 3d pipeline switches.
1820 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1821 * MI_READ_FLUSH is set, and is always flushed on 965.
1823 * I915_GEM_DOMAIN_COMMAND may not exist?
1825 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1826 * invalidated when MI_EXE_FLUSH is set.
1828 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1829 * invalidated with every MI_FLUSH.
1833 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1834 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1835 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1836 * are flushed at any MI_FLUSH.
1839 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1840 if ((invalidate_domains|flush_domains) &
1841 I915_GEM_DOMAIN_RENDER)
1842 cmd &= ~MI_NO_WRITE_FLUSH;
1843 if (!IS_I965G(dev)) {
1845 * On the 965, the sampler cache always gets flushed
1846 * and this bit is reserved.
1848 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1849 cmd |= MI_READ_FLUSH;
1851 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1852 cmd |= MI_EXE_FLUSH;
1855 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1859 OUT_RING(0); /* noop */
1865 * Ensures that all rendering to the object has completed and the object is
1866 * safe to unbind from the GTT or access from the CPU.
1869 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1871 struct drm_device *dev = obj->dev;
1872 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1875 /* This function only exists to support waiting for existing rendering,
1876 * not for emitting required flushes.
1878 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1880 /* If there is rendering queued on the buffer being evicted, wait for
1883 if (obj_priv->active) {
1885 DRM_INFO("%s: object %p wait for seqno %08x\n",
1886 __func__, obj, obj_priv->last_rendering_seqno);
1888 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1897 * Unbinds an object from the GTT aperture.
1900 i915_gem_object_unbind(struct drm_gem_object *obj)
1902 struct drm_device *dev = obj->dev;
1903 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1907 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1908 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1910 if (obj_priv->gtt_space == NULL)
1913 if (obj_priv->pin_count != 0) {
1914 DRM_ERROR("Attempting to unbind pinned buffer\n");
1918 /* Move the object to the CPU domain to ensure that
1919 * any possible CPU writes while it's not in the GTT
1920 * are flushed when we go to remap it. This will
1921 * also ensure that all pending GPU writes are finished
1924 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1926 if (ret != -ERESTARTSYS)
1927 DRM_ERROR("set_domain failed: %d\n", ret);
1931 if (obj_priv->agp_mem != NULL) {
1932 drm_unbind_agp(obj_priv->agp_mem);
1933 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1934 obj_priv->agp_mem = NULL;
1937 BUG_ON(obj_priv->active);
1939 /* blow away mappings if mapped through GTT */
1940 i915_gem_release_mmap(obj);
1942 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1943 i915_gem_clear_fence_reg(obj);
1945 i915_gem_object_put_pages(obj);
1947 if (obj_priv->gtt_space) {
1948 atomic_dec(&dev->gtt_count);
1949 atomic_sub(obj->size, &dev->gtt_memory);
1951 drm_mm_put_block(obj_priv->gtt_space);
1952 obj_priv->gtt_space = NULL;
1955 /* Remove ourselves from the LRU list if present. */
1956 if (!list_empty(&obj_priv->list))
1957 list_del_init(&obj_priv->list);
1963 i915_gem_evict_something(struct drm_device *dev)
1965 drm_i915_private_t *dev_priv = dev->dev_private;
1966 struct drm_gem_object *obj;
1967 struct drm_i915_gem_object *obj_priv;
1971 /* If there's an inactive buffer available now, grab it
1974 if (!list_empty(&dev_priv->mm.inactive_list)) {
1975 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1976 struct drm_i915_gem_object,
1978 obj = obj_priv->obj;
1979 BUG_ON(obj_priv->pin_count != 0);
1981 DRM_INFO("%s: evicting %p\n", __func__, obj);
1983 BUG_ON(obj_priv->active);
1985 /* Wait on the rendering and unbind the buffer. */
1986 ret = i915_gem_object_unbind(obj);
1990 /* If we didn't get anything, but the ring is still processing
1991 * things, wait for one of those things to finish and hopefully
1992 * leave us a buffer to evict.
1994 if (!list_empty(&dev_priv->mm.request_list)) {
1995 struct drm_i915_gem_request *request;
1997 request = list_first_entry(&dev_priv->mm.request_list,
1998 struct drm_i915_gem_request,
2001 ret = i915_wait_request(dev, request->seqno);
2005 /* if waiting caused an object to become inactive,
2006 * then loop around and wait for it. Otherwise, we
2007 * assume that waiting freed and unbound something,
2008 * so there should now be some space in the GTT
2010 if (!list_empty(&dev_priv->mm.inactive_list))
2015 /* If we didn't have anything on the request list but there
2016 * are buffers awaiting a flush, emit one and try again.
2017 * When we wait on it, those buffers waiting for that flush
2018 * will get moved to inactive.
2020 if (!list_empty(&dev_priv->mm.flushing_list)) {
2021 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2022 struct drm_i915_gem_object,
2024 obj = obj_priv->obj;
2029 i915_add_request(dev, NULL, obj->write_domain);
2035 DRM_ERROR("inactive empty %d request empty %d "
2036 "flushing empty %d\n",
2037 list_empty(&dev_priv->mm.inactive_list),
2038 list_empty(&dev_priv->mm.request_list),
2039 list_empty(&dev_priv->mm.flushing_list));
2040 /* If we didn't do any of the above, there's nothing to be done
2041 * and we just can't fit it in.
2049 i915_gem_evict_everything(struct drm_device *dev)
2054 ret = i915_gem_evict_something(dev);
2064 i915_gem_object_get_pages(struct drm_gem_object *obj)
2066 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2068 struct address_space *mapping;
2069 struct inode *inode;
2073 if (obj_priv->pages_refcount++ != 0)
2076 /* Get the list of pages out of our struct file. They'll be pinned
2077 * at this point until we release them.
2079 page_count = obj->size / PAGE_SIZE;
2080 BUG_ON(obj_priv->pages != NULL);
2081 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2082 if (obj_priv->pages == NULL) {
2083 DRM_ERROR("Faled to allocate page list\n");
2084 obj_priv->pages_refcount--;
2088 inode = obj->filp->f_path.dentry->d_inode;
2089 mapping = inode->i_mapping;
2090 for (i = 0; i < page_count; i++) {
2091 page = read_mapping_page(mapping, i, NULL);
2093 ret = PTR_ERR(page);
2094 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2095 i915_gem_object_put_pages(obj);
2098 obj_priv->pages[i] = page;
2101 if (obj_priv->tiling_mode != I915_TILING_NONE)
2102 i915_gem_object_do_bit_17_swizzle(obj);
2107 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2109 struct drm_gem_object *obj = reg->obj;
2110 struct drm_device *dev = obj->dev;
2111 drm_i915_private_t *dev_priv = dev->dev_private;
2112 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2113 int regnum = obj_priv->fence_reg;
2116 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2118 val |= obj_priv->gtt_offset & 0xfffff000;
2119 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2120 if (obj_priv->tiling_mode == I915_TILING_Y)
2121 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2122 val |= I965_FENCE_REG_VALID;
2124 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2127 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2129 struct drm_gem_object *obj = reg->obj;
2130 struct drm_device *dev = obj->dev;
2131 drm_i915_private_t *dev_priv = dev->dev_private;
2132 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2133 int regnum = obj_priv->fence_reg;
2135 uint32_t fence_reg, val;
2138 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2139 (obj_priv->gtt_offset & (obj->size - 1))) {
2140 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2141 __func__, obj_priv->gtt_offset, obj->size);
2145 if (obj_priv->tiling_mode == I915_TILING_Y &&
2146 HAS_128_BYTE_Y_TILING(dev))
2151 /* Note: pitch better be a power of two tile widths */
2152 pitch_val = obj_priv->stride / tile_width;
2153 pitch_val = ffs(pitch_val) - 1;
2155 val = obj_priv->gtt_offset;
2156 if (obj_priv->tiling_mode == I915_TILING_Y)
2157 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2158 val |= I915_FENCE_SIZE_BITS(obj->size);
2159 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2160 val |= I830_FENCE_REG_VALID;
2163 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2165 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2166 I915_WRITE(fence_reg, val);
2169 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2171 struct drm_gem_object *obj = reg->obj;
2172 struct drm_device *dev = obj->dev;
2173 drm_i915_private_t *dev_priv = dev->dev_private;
2174 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2175 int regnum = obj_priv->fence_reg;
2178 uint32_t fence_size_bits;
2180 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2181 (obj_priv->gtt_offset & (obj->size - 1))) {
2182 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2183 __func__, obj_priv->gtt_offset);
2187 pitch_val = obj_priv->stride / 128;
2188 pitch_val = ffs(pitch_val) - 1;
2189 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2191 val = obj_priv->gtt_offset;
2192 if (obj_priv->tiling_mode == I915_TILING_Y)
2193 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2194 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2195 WARN_ON(fence_size_bits & ~0x00000f00);
2196 val |= fence_size_bits;
2197 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2198 val |= I830_FENCE_REG_VALID;
2200 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2204 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2205 * @obj: object to map through a fence reg
2207 * When mapping objects through the GTT, userspace wants to be able to write
2208 * to them without having to worry about swizzling if the object is tiled.
2210 * This function walks the fence regs looking for a free one for @obj,
2211 * stealing one if it can't find any.
2213 * It then sets up the reg based on the object's properties: address, pitch
2214 * and tiling format.
2217 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2219 struct drm_device *dev = obj->dev;
2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2222 struct drm_i915_fence_reg *reg = NULL;
2223 struct drm_i915_gem_object *old_obj_priv = NULL;
2226 /* Just update our place in the LRU if our fence is getting used. */
2227 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2228 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2232 switch (obj_priv->tiling_mode) {
2233 case I915_TILING_NONE:
2234 WARN(1, "allocating a fence for non-tiled object?\n");
2237 if (!obj_priv->stride)
2239 WARN((obj_priv->stride & (512 - 1)),
2240 "object 0x%08x is X tiled but has non-512B pitch\n",
2241 obj_priv->gtt_offset);
2244 if (!obj_priv->stride)
2246 WARN((obj_priv->stride & (128 - 1)),
2247 "object 0x%08x is Y tiled but has non-128B pitch\n",
2248 obj_priv->gtt_offset);
2252 /* First try to find a free reg */
2254 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2255 reg = &dev_priv->fence_regs[i];
2259 old_obj_priv = reg->obj->driver_private;
2260 if (!old_obj_priv->pin_count)
2264 /* None available, try to steal one or wait for a user to finish */
2265 if (i == dev_priv->num_fence_regs) {
2266 struct drm_gem_object *old_obj = NULL;
2271 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2273 old_obj = old_obj_priv->obj;
2275 if (old_obj_priv->pin_count)
2278 /* Take a reference, as otherwise the wait_rendering
2279 * below may cause the object to get freed out from
2282 drm_gem_object_reference(old_obj);
2284 /* i915 uses fences for GPU access to tiled buffers */
2285 if (IS_I965G(dev) || !old_obj_priv->active)
2288 /* This brings the object to the head of the LRU if it
2289 * had been written to. The only way this should
2290 * result in us waiting longer than the expected
2291 * optimal amount of time is if there was a
2292 * fence-using buffer later that was read-only.
2294 i915_gem_object_flush_gpu_write_domain(old_obj);
2295 ret = i915_gem_object_wait_rendering(old_obj);
2297 drm_gem_object_unreference(old_obj);
2305 * Zap this virtual mapping so we can set up a fence again
2306 * for this object next time we need it.
2308 i915_gem_release_mmap(old_obj);
2310 i = old_obj_priv->fence_reg;
2311 reg = &dev_priv->fence_regs[i];
2313 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2314 list_del_init(&old_obj_priv->fence_list);
2316 drm_gem_object_unreference(old_obj);
2319 obj_priv->fence_reg = i;
2320 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2325 i965_write_fence_reg(reg);
2326 else if (IS_I9XX(dev))
2327 i915_write_fence_reg(reg);
2329 i830_write_fence_reg(reg);
2335 * i915_gem_clear_fence_reg - clear out fence register info
2336 * @obj: object to clear
2338 * Zeroes out the fence register itself and clears out the associated
2339 * data structures in dev_priv and obj_priv.
2342 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2344 struct drm_device *dev = obj->dev;
2345 drm_i915_private_t *dev_priv = dev->dev_private;
2346 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2349 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2353 if (obj_priv->fence_reg < 8)
2354 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2356 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2359 I915_WRITE(fence_reg, 0);
2362 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2363 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2364 list_del_init(&obj_priv->fence_list);
2368 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2369 * to the buffer to finish, and then resets the fence register.
2370 * @obj: tiled object holding a fence register.
2372 * Zeroes out the fence register itself and clears out the associated
2373 * data structures in dev_priv and obj_priv.
2376 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2378 struct drm_device *dev = obj->dev;
2379 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2381 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2384 /* On the i915, GPU access to tiled buffers is via a fence,
2385 * therefore we must wait for any outstanding access to complete
2386 * before clearing the fence.
2388 if (!IS_I965G(dev)) {
2391 i915_gem_object_flush_gpu_write_domain(obj);
2392 i915_gem_object_flush_gtt_write_domain(obj);
2393 ret = i915_gem_object_wait_rendering(obj);
2398 i915_gem_clear_fence_reg (obj);
2404 * Finds free space in the GTT aperture and binds the object there.
2407 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2409 struct drm_device *dev = obj->dev;
2410 drm_i915_private_t *dev_priv = dev->dev_private;
2411 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2412 struct drm_mm_node *free_space;
2413 int page_count, ret;
2415 if (dev_priv->mm.suspended)
2418 alignment = i915_gem_get_gtt_alignment(obj);
2419 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2420 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2425 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2426 obj->size, alignment, 0);
2427 if (free_space != NULL) {
2428 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2430 if (obj_priv->gtt_space != NULL) {
2431 obj_priv->gtt_space->private = obj;
2432 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2435 if (obj_priv->gtt_space == NULL) {
2438 /* If the gtt is empty and we're still having trouble
2439 * fitting our object in, we're out of memory.
2442 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2444 spin_lock(&dev_priv->mm.active_list_lock);
2445 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2446 list_empty(&dev_priv->mm.flushing_list) &&
2447 list_empty(&dev_priv->mm.active_list));
2448 spin_unlock(&dev_priv->mm.active_list_lock);
2450 DRM_ERROR("GTT full, but LRU list empty\n");
2454 ret = i915_gem_evict_something(dev);
2456 if (ret != -ERESTARTSYS)
2457 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2464 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2465 obj->size, obj_priv->gtt_offset);
2467 ret = i915_gem_object_get_pages(obj);
2469 drm_mm_put_block(obj_priv->gtt_space);
2470 obj_priv->gtt_space = NULL;
2474 page_count = obj->size / PAGE_SIZE;
2475 /* Create an AGP memory structure pointing at our pages, and bind it
2478 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2481 obj_priv->gtt_offset,
2482 obj_priv->agp_type);
2483 if (obj_priv->agp_mem == NULL) {
2484 i915_gem_object_put_pages(obj);
2485 drm_mm_put_block(obj_priv->gtt_space);
2486 obj_priv->gtt_space = NULL;
2489 atomic_inc(&dev->gtt_count);
2490 atomic_add(obj->size, &dev->gtt_memory);
2492 /* Assert that the object is not currently in any GPU domain. As it
2493 * wasn't in the GTT, there shouldn't be any way it could have been in
2496 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2497 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2503 i915_gem_clflush_object(struct drm_gem_object *obj)
2505 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2507 /* If we don't have a page list set up, then we're not pinned
2508 * to GPU, and we can ignore the cache flush because it'll happen
2509 * again at bind time.
2511 if (obj_priv->pages == NULL)
2514 /* XXX: The 865 in particular appears to be weird in how it handles
2515 * cache flushing. We haven't figured it out, but the
2516 * clflush+agp_chipset_flush doesn't appear to successfully get the
2517 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2519 if (IS_I865G(obj->dev)) {
2524 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2527 /** Flushes any GPU write domain for the object if it's dirty. */
2529 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2531 struct drm_device *dev = obj->dev;
2534 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2537 /* Queue the GPU write cache flushing we need. */
2538 i915_gem_flush(dev, 0, obj->write_domain);
2539 seqno = i915_add_request(dev, NULL, obj->write_domain);
2540 obj->write_domain = 0;
2541 i915_gem_object_move_to_active(obj, seqno);
2544 /** Flushes the GTT write domain for the object if it's dirty. */
2546 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2548 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2551 /* No actual flushing is required for the GTT write domain. Writes
2552 * to it immediately go to main memory as far as we know, so there's
2553 * no chipset flush. It also doesn't land in render cache.
2555 obj->write_domain = 0;
2558 /** Flushes the CPU write domain for the object if it's dirty. */
2560 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2562 struct drm_device *dev = obj->dev;
2564 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2567 i915_gem_clflush_object(obj);
2568 drm_agp_chipset_flush(dev);
2569 obj->write_domain = 0;
2573 * Moves a single object to the GTT read, and possibly write domain.
2575 * This function returns when the move is complete, including waiting on
2579 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2581 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2584 /* Not valid to be called on unbound objects. */
2585 if (obj_priv->gtt_space == NULL)
2588 i915_gem_object_flush_gpu_write_domain(obj);
2589 /* Wait on any GPU rendering and flushing to occur. */
2590 ret = i915_gem_object_wait_rendering(obj);
2594 /* If we're writing through the GTT domain, then CPU and GPU caches
2595 * will need to be invalidated at next use.
2598 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2600 i915_gem_object_flush_cpu_write_domain(obj);
2602 /* It should now be out of any other write domains, and we can update
2603 * the domain values for our changes.
2605 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2606 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2608 obj->write_domain = I915_GEM_DOMAIN_GTT;
2609 obj_priv->dirty = 1;
2616 * Moves a single object to the CPU read, and possibly write domain.
2618 * This function returns when the move is complete, including waiting on
2622 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2626 i915_gem_object_flush_gpu_write_domain(obj);
2627 /* Wait on any GPU rendering and flushing to occur. */
2628 ret = i915_gem_object_wait_rendering(obj);
2632 i915_gem_object_flush_gtt_write_domain(obj);
2634 /* If we have a partially-valid cache of the object in the CPU,
2635 * finish invalidating it and free the per-page flags.
2637 i915_gem_object_set_to_full_cpu_read_domain(obj);
2639 /* Flush the CPU cache if it's still invalid. */
2640 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2641 i915_gem_clflush_object(obj);
2643 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2646 /* It should now be out of any other write domains, and we can update
2647 * the domain values for our changes.
2649 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2651 /* If we're writing through the CPU, then the GPU read domains will
2652 * need to be invalidated at next use.
2655 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2656 obj->write_domain = I915_GEM_DOMAIN_CPU;
2663 * Set the next domain for the specified object. This
2664 * may not actually perform the necessary flushing/invaliding though,
2665 * as that may want to be batched with other set_domain operations
2667 * This is (we hope) the only really tricky part of gem. The goal
2668 * is fairly simple -- track which caches hold bits of the object
2669 * and make sure they remain coherent. A few concrete examples may
2670 * help to explain how it works. For shorthand, we use the notation
2671 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2672 * a pair of read and write domain masks.
2674 * Case 1: the batch buffer
2680 * 5. Unmapped from GTT
2683 * Let's take these a step at a time
2686 * Pages allocated from the kernel may still have
2687 * cache contents, so we set them to (CPU, CPU) always.
2688 * 2. Written by CPU (using pwrite)
2689 * The pwrite function calls set_domain (CPU, CPU) and
2690 * this function does nothing (as nothing changes)
2692 * This function asserts that the object is not
2693 * currently in any GPU-based read or write domains
2695 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2696 * As write_domain is zero, this function adds in the
2697 * current read domains (CPU+COMMAND, 0).
2698 * flush_domains is set to CPU.
2699 * invalidate_domains is set to COMMAND
2700 * clflush is run to get data out of the CPU caches
2701 * then i915_dev_set_domain calls i915_gem_flush to
2702 * emit an MI_FLUSH and drm_agp_chipset_flush
2703 * 5. Unmapped from GTT
2704 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2705 * flush_domains and invalidate_domains end up both zero
2706 * so no flushing/invalidating happens
2710 * Case 2: The shared render buffer
2714 * 3. Read/written by GPU
2715 * 4. set_domain to (CPU,CPU)
2716 * 5. Read/written by CPU
2717 * 6. Read/written by GPU
2720 * Same as last example, (CPU, CPU)
2722 * Nothing changes (assertions find that it is not in the GPU)
2723 * 3. Read/written by GPU
2724 * execbuffer calls set_domain (RENDER, RENDER)
2725 * flush_domains gets CPU
2726 * invalidate_domains gets GPU
2728 * MI_FLUSH and drm_agp_chipset_flush
2729 * 4. set_domain (CPU, CPU)
2730 * flush_domains gets GPU
2731 * invalidate_domains gets CPU
2732 * wait_rendering (obj) to make sure all drawing is complete.
2733 * This will include an MI_FLUSH to get the data from GPU
2735 * clflush (obj) to invalidate the CPU cache
2736 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2737 * 5. Read/written by CPU
2738 * cache lines are loaded and dirtied
2739 * 6. Read written by GPU
2740 * Same as last GPU access
2742 * Case 3: The constant buffer
2747 * 4. Updated (written) by CPU again
2756 * flush_domains = CPU
2757 * invalidate_domains = RENDER
2760 * drm_agp_chipset_flush
2761 * 4. Updated (written) by CPU again
2763 * flush_domains = 0 (no previous write domain)
2764 * invalidate_domains = 0 (no new read domains)
2767 * flush_domains = CPU
2768 * invalidate_domains = RENDER
2771 * drm_agp_chipset_flush
2774 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2776 struct drm_device *dev = obj->dev;
2777 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2778 uint32_t invalidate_domains = 0;
2779 uint32_t flush_domains = 0;
2781 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2782 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2784 intel_mark_busy(dev, obj);
2787 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2789 obj->read_domains, obj->pending_read_domains,
2790 obj->write_domain, obj->pending_write_domain);
2793 * If the object isn't moving to a new write domain,
2794 * let the object stay in multiple read domains
2796 if (obj->pending_write_domain == 0)
2797 obj->pending_read_domains |= obj->read_domains;
2799 obj_priv->dirty = 1;
2802 * Flush the current write domain if
2803 * the new read domains don't match. Invalidate
2804 * any read domains which differ from the old
2807 if (obj->write_domain &&
2808 obj->write_domain != obj->pending_read_domains) {
2809 flush_domains |= obj->write_domain;
2810 invalidate_domains |=
2811 obj->pending_read_domains & ~obj->write_domain;
2814 * Invalidate any read caches which may have
2815 * stale data. That is, any new read domains.
2817 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2818 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2820 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2821 __func__, flush_domains, invalidate_domains);
2823 i915_gem_clflush_object(obj);
2826 /* The actual obj->write_domain will be updated with
2827 * pending_write_domain after we emit the accumulated flush for all
2828 * of our domain changes in execbuffers (which clears objects'
2829 * write_domains). So if we have a current write domain that we
2830 * aren't changing, set pending_write_domain to that.
2832 if (flush_domains == 0 && obj->pending_write_domain == 0)
2833 obj->pending_write_domain = obj->write_domain;
2834 obj->read_domains = obj->pending_read_domains;
2836 dev->invalidate_domains |= invalidate_domains;
2837 dev->flush_domains |= flush_domains;
2839 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2841 obj->read_domains, obj->write_domain,
2842 dev->invalidate_domains, dev->flush_domains);
2847 * Moves the object from a partially CPU read to a full one.
2849 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2850 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2853 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2855 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2857 if (!obj_priv->page_cpu_valid)
2860 /* If we're partially in the CPU read domain, finish moving it in.
2862 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2865 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2866 if (obj_priv->page_cpu_valid[i])
2868 drm_clflush_pages(obj_priv->pages + i, 1);
2872 /* Free the page_cpu_valid mappings which are now stale, whether
2873 * or not we've got I915_GEM_DOMAIN_CPU.
2875 kfree(obj_priv->page_cpu_valid);
2876 obj_priv->page_cpu_valid = NULL;
2880 * Set the CPU read domain on a range of the object.
2882 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2883 * not entirely valid. The page_cpu_valid member of the object flags which
2884 * pages have been flushed, and will be respected by
2885 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2886 * of the whole object.
2888 * This function returns when the move is complete, including waiting on
2892 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2893 uint64_t offset, uint64_t size)
2895 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2898 if (offset == 0 && size == obj->size)
2899 return i915_gem_object_set_to_cpu_domain(obj, 0);
2901 i915_gem_object_flush_gpu_write_domain(obj);
2902 /* Wait on any GPU rendering and flushing to occur. */
2903 ret = i915_gem_object_wait_rendering(obj);
2906 i915_gem_object_flush_gtt_write_domain(obj);
2908 /* If we're already fully in the CPU read domain, we're done. */
2909 if (obj_priv->page_cpu_valid == NULL &&
2910 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2913 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2914 * newly adding I915_GEM_DOMAIN_CPU
2916 if (obj_priv->page_cpu_valid == NULL) {
2917 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
2919 if (obj_priv->page_cpu_valid == NULL)
2921 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2922 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2924 /* Flush the cache on any pages that are still invalid from the CPU's
2927 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2929 if (obj_priv->page_cpu_valid[i])
2932 drm_clflush_pages(obj_priv->pages + i, 1);
2934 obj_priv->page_cpu_valid[i] = 1;
2937 /* It should now be out of any other write domains, and we can update
2938 * the domain values for our changes.
2940 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2942 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2948 * Pin an object to the GTT and evaluate the relocations landing in it.
2951 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2952 struct drm_file *file_priv,
2953 struct drm_i915_gem_exec_object *entry,
2954 struct drm_i915_gem_relocation_entry *relocs)
2956 struct drm_device *dev = obj->dev;
2957 drm_i915_private_t *dev_priv = dev->dev_private;
2958 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2960 void __iomem *reloc_page;
2962 /* Choose the GTT offset for our buffer and put it there. */
2963 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2967 entry->offset = obj_priv->gtt_offset;
2969 /* Apply the relocations, using the GTT aperture to avoid cache
2970 * flushing requirements.
2972 for (i = 0; i < entry->relocation_count; i++) {
2973 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2974 struct drm_gem_object *target_obj;
2975 struct drm_i915_gem_object *target_obj_priv;
2976 uint32_t reloc_val, reloc_offset;
2977 uint32_t __iomem *reloc_entry;
2979 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2980 reloc->target_handle);
2981 if (target_obj == NULL) {
2982 i915_gem_object_unpin(obj);
2985 target_obj_priv = target_obj->driver_private;
2987 /* The target buffer should have appeared before us in the
2988 * exec_object list, so it should have a GTT space bound by now.
2990 if (target_obj_priv->gtt_space == NULL) {
2991 DRM_ERROR("No GTT space found for object %d\n",
2992 reloc->target_handle);
2993 drm_gem_object_unreference(target_obj);
2994 i915_gem_object_unpin(obj);
2998 if (reloc->offset > obj->size - 4) {
2999 DRM_ERROR("Relocation beyond object bounds: "
3000 "obj %p target %d offset %d size %d.\n",
3001 obj, reloc->target_handle,
3002 (int) reloc->offset, (int) obj->size);
3003 drm_gem_object_unreference(target_obj);
3004 i915_gem_object_unpin(obj);
3007 if (reloc->offset & 3) {
3008 DRM_ERROR("Relocation not 4-byte aligned: "
3009 "obj %p target %d offset %d.\n",
3010 obj, reloc->target_handle,
3011 (int) reloc->offset);
3012 drm_gem_object_unreference(target_obj);
3013 i915_gem_object_unpin(obj);
3017 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3018 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3019 DRM_ERROR("reloc with read/write CPU domains: "
3020 "obj %p target %d offset %d "
3021 "read %08x write %08x",
3022 obj, reloc->target_handle,
3023 (int) reloc->offset,
3024 reloc->read_domains,
3025 reloc->write_domain);
3026 drm_gem_object_unreference(target_obj);
3027 i915_gem_object_unpin(obj);
3031 if (reloc->write_domain && target_obj->pending_write_domain &&
3032 reloc->write_domain != target_obj->pending_write_domain) {
3033 DRM_ERROR("Write domain conflict: "
3034 "obj %p target %d offset %d "
3035 "new %08x old %08x\n",
3036 obj, reloc->target_handle,
3037 (int) reloc->offset,
3038 reloc->write_domain,
3039 target_obj->pending_write_domain);
3040 drm_gem_object_unreference(target_obj);
3041 i915_gem_object_unpin(obj);
3046 DRM_INFO("%s: obj %p offset %08x target %d "
3047 "read %08x write %08x gtt %08x "
3048 "presumed %08x delta %08x\n",
3051 (int) reloc->offset,
3052 (int) reloc->target_handle,
3053 (int) reloc->read_domains,
3054 (int) reloc->write_domain,
3055 (int) target_obj_priv->gtt_offset,
3056 (int) reloc->presumed_offset,
3060 target_obj->pending_read_domains |= reloc->read_domains;
3061 target_obj->pending_write_domain |= reloc->write_domain;
3063 /* If the relocation already has the right value in it, no
3064 * more work needs to be done.
3066 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3067 drm_gem_object_unreference(target_obj);
3071 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3073 drm_gem_object_unreference(target_obj);
3074 i915_gem_object_unpin(obj);
3078 /* Map the page containing the relocation we're going to
3081 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3082 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3085 reloc_entry = (uint32_t __iomem *)(reloc_page +
3086 (reloc_offset & (PAGE_SIZE - 1)));
3087 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3090 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3091 obj, (unsigned int) reloc->offset,
3092 readl(reloc_entry), reloc_val);
3094 writel(reloc_val, reloc_entry);
3095 io_mapping_unmap_atomic(reloc_page);
3097 /* The updated presumed offset for this entry will be
3098 * copied back out to the user.
3100 reloc->presumed_offset = target_obj_priv->gtt_offset;
3102 drm_gem_object_unreference(target_obj);
3107 i915_gem_dump_object(obj, 128, __func__, ~0);
3112 /** Dispatch a batchbuffer to the ring
3115 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3116 struct drm_i915_gem_execbuffer *exec,
3117 struct drm_clip_rect *cliprects,
3118 uint64_t exec_offset)
3120 drm_i915_private_t *dev_priv = dev->dev_private;
3121 int nbox = exec->num_cliprects;
3123 uint32_t exec_start, exec_len;
3126 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3127 exec_len = (uint32_t) exec->batch_len;
3129 count = nbox ? nbox : 1;
3131 for (i = 0; i < count; i++) {
3133 int ret = i915_emit_box(dev, cliprects, i,
3134 exec->DR1, exec->DR4);
3139 if (IS_I830(dev) || IS_845G(dev)) {
3141 OUT_RING(MI_BATCH_BUFFER);
3142 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3143 OUT_RING(exec_start + exec_len - 4);
3148 if (IS_I965G(dev)) {
3149 OUT_RING(MI_BATCH_BUFFER_START |
3151 MI_BATCH_NON_SECURE_I965);
3152 OUT_RING(exec_start);
3154 OUT_RING(MI_BATCH_BUFFER_START |
3156 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3162 /* XXX breadcrumb */
3166 /* Throttle our rendering by waiting until the ring has completed our requests
3167 * emitted over 20 msec ago.
3169 * Note that if we were to use the current jiffies each time around the loop,
3170 * we wouldn't escape the function with any frames outstanding if the time to
3171 * render a frame was over 20ms.
3173 * This should get us reasonable parallelism between CPU and GPU but also
3174 * relatively low latency when blocking on a particular request to finish.
3177 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3179 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3181 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3183 mutex_lock(&dev->struct_mutex);
3184 while (!list_empty(&i915_file_priv->mm.request_list)) {
3185 struct drm_i915_gem_request *request;
3187 request = list_first_entry(&i915_file_priv->mm.request_list,
3188 struct drm_i915_gem_request,
3191 if (time_after_eq(request->emitted_jiffies, recent_enough))
3194 ret = i915_wait_request(dev, request->seqno);
3198 mutex_unlock(&dev->struct_mutex);
3204 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3205 uint32_t buffer_count,
3206 struct drm_i915_gem_relocation_entry **relocs)
3208 uint32_t reloc_count = 0, reloc_index = 0, i;
3212 for (i = 0; i < buffer_count; i++) {
3213 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3215 reloc_count += exec_list[i].relocation_count;
3218 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3219 if (*relocs == NULL)
3222 for (i = 0; i < buffer_count; i++) {
3223 struct drm_i915_gem_relocation_entry __user *user_relocs;
3225 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3227 ret = copy_from_user(&(*relocs)[reloc_index],
3229 exec_list[i].relocation_count *
3232 drm_free_large(*relocs);
3237 reloc_index += exec_list[i].relocation_count;
3244 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3245 uint32_t buffer_count,
3246 struct drm_i915_gem_relocation_entry *relocs)
3248 uint32_t reloc_count = 0, i;
3251 for (i = 0; i < buffer_count; i++) {
3252 struct drm_i915_gem_relocation_entry __user *user_relocs;
3255 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3257 unwritten = copy_to_user(user_relocs,
3258 &relocs[reloc_count],
3259 exec_list[i].relocation_count *
3267 reloc_count += exec_list[i].relocation_count;
3271 drm_free_large(relocs);
3277 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3278 uint64_t exec_offset)
3280 uint32_t exec_start, exec_len;
3282 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3283 exec_len = (uint32_t) exec->batch_len;
3285 if ((exec_start | exec_len) & 0x7)
3295 i915_gem_execbuffer(struct drm_device *dev, void *data,
3296 struct drm_file *file_priv)
3298 drm_i915_private_t *dev_priv = dev->dev_private;
3299 struct drm_i915_gem_execbuffer *args = data;
3300 struct drm_i915_gem_exec_object *exec_list = NULL;
3301 struct drm_gem_object **object_list = NULL;
3302 struct drm_gem_object *batch_obj;
3303 struct drm_i915_gem_object *obj_priv;
3304 struct drm_clip_rect *cliprects = NULL;
3305 struct drm_i915_gem_relocation_entry *relocs;
3306 int ret, ret2, i, pinned = 0;
3307 uint64_t exec_offset;
3308 uint32_t seqno, flush_domains, reloc_index;
3312 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3313 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3316 if (args->buffer_count < 1) {
3317 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3320 /* Copy in the exec list from userland */
3321 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3322 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3323 if (exec_list == NULL || object_list == NULL) {
3324 DRM_ERROR("Failed to allocate exec or object list "
3326 args->buffer_count);
3330 ret = copy_from_user(exec_list,
3331 (struct drm_i915_relocation_entry __user *)
3332 (uintptr_t) args->buffers_ptr,
3333 sizeof(*exec_list) * args->buffer_count);
3335 DRM_ERROR("copy %d exec entries failed %d\n",
3336 args->buffer_count, ret);
3340 if (args->num_cliprects != 0) {
3341 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3343 if (cliprects == NULL)
3346 ret = copy_from_user(cliprects,
3347 (struct drm_clip_rect __user *)
3348 (uintptr_t) args->cliprects_ptr,
3349 sizeof(*cliprects) * args->num_cliprects);
3351 DRM_ERROR("copy %d cliprects failed: %d\n",
3352 args->num_cliprects, ret);
3357 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3362 mutex_lock(&dev->struct_mutex);
3364 i915_verify_inactive(dev, __FILE__, __LINE__);
3366 if (dev_priv->mm.wedged) {
3367 DRM_ERROR("Execbuf while wedged\n");
3368 mutex_unlock(&dev->struct_mutex);
3373 if (dev_priv->mm.suspended) {
3374 DRM_ERROR("Execbuf while VT-switched.\n");
3375 mutex_unlock(&dev->struct_mutex);
3380 /* Look up object handles */
3381 for (i = 0; i < args->buffer_count; i++) {
3382 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3383 exec_list[i].handle);
3384 if (object_list[i] == NULL) {
3385 DRM_ERROR("Invalid object handle %d at index %d\n",
3386 exec_list[i].handle, i);
3391 obj_priv = object_list[i]->driver_private;
3392 if (obj_priv->in_execbuffer) {
3393 DRM_ERROR("Object %p appears more than once in object list\n",
3398 obj_priv->in_execbuffer = true;
3401 /* Pin and relocate */
3402 for (pin_tries = 0; ; pin_tries++) {
3406 for (i = 0; i < args->buffer_count; i++) {
3407 object_list[i]->pending_read_domains = 0;
3408 object_list[i]->pending_write_domain = 0;
3409 ret = i915_gem_object_pin_and_relocate(object_list[i],
3412 &relocs[reloc_index]);
3416 reloc_index += exec_list[i].relocation_count;
3422 /* error other than GTT full, or we've already tried again */
3423 if (ret != -ENOSPC || pin_tries >= 1) {
3424 if (ret != -ERESTARTSYS)
3425 DRM_ERROR("Failed to pin buffers %d\n", ret);
3429 /* unpin all of our buffers */
3430 for (i = 0; i < pinned; i++)
3431 i915_gem_object_unpin(object_list[i]);
3434 /* evict everyone we can from the aperture */
3435 ret = i915_gem_evict_everything(dev);
3440 /* Set the pending read domains for the batch buffer to COMMAND */
3441 batch_obj = object_list[args->buffer_count-1];
3442 if (batch_obj->pending_write_domain) {
3443 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3447 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3449 /* Sanity check the batch buffer, prior to moving objects */
3450 exec_offset = exec_list[args->buffer_count - 1].offset;
3451 ret = i915_gem_check_execbuffer (args, exec_offset);
3453 DRM_ERROR("execbuf with invalid offset/length\n");
3457 i915_verify_inactive(dev, __FILE__, __LINE__);
3459 /* Zero the global flush/invalidate flags. These
3460 * will be modified as new domains are computed
3463 dev->invalidate_domains = 0;
3464 dev->flush_domains = 0;
3466 for (i = 0; i < args->buffer_count; i++) {
3467 struct drm_gem_object *obj = object_list[i];
3469 /* Compute new gpu domains and update invalidate/flush */
3470 i915_gem_object_set_to_gpu_domain(obj);
3473 i915_verify_inactive(dev, __FILE__, __LINE__);
3475 if (dev->invalidate_domains | dev->flush_domains) {
3477 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3479 dev->invalidate_domains,
3480 dev->flush_domains);
3483 dev->invalidate_domains,
3484 dev->flush_domains);
3485 if (dev->flush_domains)
3486 (void)i915_add_request(dev, file_priv,
3487 dev->flush_domains);
3490 for (i = 0; i < args->buffer_count; i++) {
3491 struct drm_gem_object *obj = object_list[i];
3493 obj->write_domain = obj->pending_write_domain;
3496 i915_verify_inactive(dev, __FILE__, __LINE__);
3499 for (i = 0; i < args->buffer_count; i++) {
3500 i915_gem_object_check_coherency(object_list[i],
3501 exec_list[i].handle);
3506 i915_gem_dump_object(batch_obj,
3512 /* Exec the batchbuffer */
3513 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3515 DRM_ERROR("dispatch failed %d\n", ret);
3520 * Ensure that the commands in the batch buffer are
3521 * finished before the interrupt fires
3523 flush_domains = i915_retire_commands(dev);
3525 i915_verify_inactive(dev, __FILE__, __LINE__);
3528 * Get a seqno representing the execution of the current buffer,
3529 * which we can wait on. We would like to mitigate these interrupts,
3530 * likely by only creating seqnos occasionally (so that we have
3531 * *some* interrupts representing completion of buffers that we can
3532 * wait on when trying to clear up gtt space).
3534 seqno = i915_add_request(dev, file_priv, flush_domains);
3536 for (i = 0; i < args->buffer_count; i++) {
3537 struct drm_gem_object *obj = object_list[i];
3539 i915_gem_object_move_to_active(obj, seqno);
3541 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3545 i915_dump_lru(dev, __func__);
3548 i915_verify_inactive(dev, __FILE__, __LINE__);
3551 for (i = 0; i < pinned; i++)
3552 i915_gem_object_unpin(object_list[i]);
3554 for (i = 0; i < args->buffer_count; i++) {
3555 if (object_list[i]) {
3556 obj_priv = object_list[i]->driver_private;
3557 obj_priv->in_execbuffer = false;
3559 drm_gem_object_unreference(object_list[i]);
3562 mutex_unlock(&dev->struct_mutex);
3565 /* Copy the new buffer offsets back to the user's exec list. */
3566 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3567 (uintptr_t) args->buffers_ptr,
3569 sizeof(*exec_list) * args->buffer_count);
3572 DRM_ERROR("failed to copy %d exec entries "
3573 "back to user (%d)\n",
3574 args->buffer_count, ret);
3578 /* Copy the updated relocations out regardless of current error
3579 * state. Failure to update the relocs would mean that the next
3580 * time userland calls execbuf, it would do so with presumed offset
3581 * state that didn't match the actual object state.
3583 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3586 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3593 drm_free_large(object_list);
3594 drm_free_large(exec_list);
3601 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3603 struct drm_device *dev = obj->dev;
3604 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3607 i915_verify_inactive(dev, __FILE__, __LINE__);
3608 if (obj_priv->gtt_space == NULL) {
3609 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3611 if (ret != -EBUSY && ret != -ERESTARTSYS)
3612 DRM_ERROR("Failure to bind: %d\n", ret);
3617 * Pre-965 chips need a fence register set up in order to
3618 * properly handle tiled surfaces.
3620 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3621 ret = i915_gem_object_get_fence_reg(obj);
3623 if (ret != -EBUSY && ret != -ERESTARTSYS)
3624 DRM_ERROR("Failure to install fence: %d\n",
3629 obj_priv->pin_count++;
3631 /* If the object is not active and not pending a flush,
3632 * remove it from the inactive list
3634 if (obj_priv->pin_count == 1) {
3635 atomic_inc(&dev->pin_count);
3636 atomic_add(obj->size, &dev->pin_memory);
3637 if (!obj_priv->active &&
3638 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3639 !list_empty(&obj_priv->list))
3640 list_del_init(&obj_priv->list);
3642 i915_verify_inactive(dev, __FILE__, __LINE__);
3648 i915_gem_object_unpin(struct drm_gem_object *obj)
3650 struct drm_device *dev = obj->dev;
3651 drm_i915_private_t *dev_priv = dev->dev_private;
3652 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3654 i915_verify_inactive(dev, __FILE__, __LINE__);
3655 obj_priv->pin_count--;
3656 BUG_ON(obj_priv->pin_count < 0);
3657 BUG_ON(obj_priv->gtt_space == NULL);
3659 /* If the object is no longer pinned, and is
3660 * neither active nor being flushed, then stick it on
3663 if (obj_priv->pin_count == 0) {
3664 if (!obj_priv->active &&
3665 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3666 list_move_tail(&obj_priv->list,
3667 &dev_priv->mm.inactive_list);
3668 atomic_dec(&dev->pin_count);
3669 atomic_sub(obj->size, &dev->pin_memory);
3671 i915_verify_inactive(dev, __FILE__, __LINE__);
3675 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3676 struct drm_file *file_priv)
3678 struct drm_i915_gem_pin *args = data;
3679 struct drm_gem_object *obj;
3680 struct drm_i915_gem_object *obj_priv;
3683 mutex_lock(&dev->struct_mutex);
3685 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3687 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3689 mutex_unlock(&dev->struct_mutex);
3692 obj_priv = obj->driver_private;
3694 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3695 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3697 drm_gem_object_unreference(obj);
3698 mutex_unlock(&dev->struct_mutex);
3702 obj_priv->user_pin_count++;
3703 obj_priv->pin_filp = file_priv;
3704 if (obj_priv->user_pin_count == 1) {
3705 ret = i915_gem_object_pin(obj, args->alignment);
3707 drm_gem_object_unreference(obj);
3708 mutex_unlock(&dev->struct_mutex);
3713 /* XXX - flush the CPU caches for pinned objects
3714 * as the X server doesn't manage domains yet
3716 i915_gem_object_flush_cpu_write_domain(obj);
3717 args->offset = obj_priv->gtt_offset;
3718 drm_gem_object_unreference(obj);
3719 mutex_unlock(&dev->struct_mutex);
3725 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3726 struct drm_file *file_priv)
3728 struct drm_i915_gem_pin *args = data;
3729 struct drm_gem_object *obj;
3730 struct drm_i915_gem_object *obj_priv;
3732 mutex_lock(&dev->struct_mutex);
3734 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3736 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3738 mutex_unlock(&dev->struct_mutex);
3742 obj_priv = obj->driver_private;
3743 if (obj_priv->pin_filp != file_priv) {
3744 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3746 drm_gem_object_unreference(obj);
3747 mutex_unlock(&dev->struct_mutex);
3750 obj_priv->user_pin_count--;
3751 if (obj_priv->user_pin_count == 0) {
3752 obj_priv->pin_filp = NULL;
3753 i915_gem_object_unpin(obj);
3756 drm_gem_object_unreference(obj);
3757 mutex_unlock(&dev->struct_mutex);
3762 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3763 struct drm_file *file_priv)
3765 struct drm_i915_gem_busy *args = data;
3766 struct drm_gem_object *obj;
3767 struct drm_i915_gem_object *obj_priv;
3769 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3771 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3776 mutex_lock(&dev->struct_mutex);
3777 /* Update the active list for the hardware's current position.
3778 * Otherwise this only updates on a delayed timer or when irqs are
3779 * actually unmasked, and our working set ends up being larger than
3782 i915_gem_retire_requests(dev);
3784 obj_priv = obj->driver_private;
3785 /* Don't count being on the flushing list against the object being
3786 * done. Otherwise, a buffer left on the flushing list but not getting
3787 * flushed (because nobody's flushing that domain) won't ever return
3788 * unbusy and get reused by libdrm's bo cache. The other expected
3789 * consumer of this interface, OpenGL's occlusion queries, also specs
3790 * that the objects get unbusy "eventually" without any interference.
3792 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3794 drm_gem_object_unreference(obj);
3795 mutex_unlock(&dev->struct_mutex);
3800 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3801 struct drm_file *file_priv)
3803 return i915_gem_ring_throttle(dev, file_priv);
3806 int i915_gem_init_object(struct drm_gem_object *obj)
3808 struct drm_i915_gem_object *obj_priv;
3810 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
3811 if (obj_priv == NULL)
3815 * We've just allocated pages from the kernel,
3816 * so they've just been written by the CPU with
3817 * zeros. They'll need to be clflushed before we
3818 * use them with the GPU.
3820 obj->write_domain = I915_GEM_DOMAIN_CPU;
3821 obj->read_domains = I915_GEM_DOMAIN_CPU;
3823 obj_priv->agp_type = AGP_USER_MEMORY;
3825 obj->driver_private = obj_priv;
3826 obj_priv->obj = obj;
3827 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3828 INIT_LIST_HEAD(&obj_priv->list);
3829 INIT_LIST_HEAD(&obj_priv->fence_list);
3834 void i915_gem_free_object(struct drm_gem_object *obj)
3836 struct drm_device *dev = obj->dev;
3837 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3839 while (obj_priv->pin_count > 0)
3840 i915_gem_object_unpin(obj);
3842 if (obj_priv->phys_obj)
3843 i915_gem_detach_phys_object(dev, obj);
3845 i915_gem_object_unbind(obj);
3847 i915_gem_free_mmap_offset(obj);
3849 kfree(obj_priv->page_cpu_valid);
3850 kfree(obj_priv->bit_17);
3851 kfree(obj->driver_private);
3854 /** Unbinds all objects that are on the given buffer list. */
3856 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3858 struct drm_gem_object *obj;
3859 struct drm_i915_gem_object *obj_priv;
3862 while (!list_empty(head)) {
3863 obj_priv = list_first_entry(head,
3864 struct drm_i915_gem_object,
3866 obj = obj_priv->obj;
3868 if (obj_priv->pin_count != 0) {
3869 DRM_ERROR("Pinned object in unbind list\n");
3870 mutex_unlock(&dev->struct_mutex);
3874 ret = i915_gem_object_unbind(obj);
3876 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3878 mutex_unlock(&dev->struct_mutex);
3888 i915_gem_idle(struct drm_device *dev)
3890 drm_i915_private_t *dev_priv = dev->dev_private;
3891 uint32_t seqno, cur_seqno, last_seqno;
3894 mutex_lock(&dev->struct_mutex);
3896 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3897 mutex_unlock(&dev->struct_mutex);
3901 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3902 * We need to replace this with a semaphore, or something.
3904 dev_priv->mm.suspended = 1;
3906 /* Cancel the retire work handler, wait for it to finish if running
3908 mutex_unlock(&dev->struct_mutex);
3909 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3910 mutex_lock(&dev->struct_mutex);
3912 i915_kernel_lost_context(dev);
3914 /* Flush the GPU along with all non-CPU write domains
3916 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3917 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3920 mutex_unlock(&dev->struct_mutex);
3924 dev_priv->mm.waiting_gem_seqno = seqno;
3928 cur_seqno = i915_get_gem_seqno(dev);
3929 if (i915_seqno_passed(cur_seqno, seqno))
3931 if (last_seqno == cur_seqno) {
3932 if (stuck++ > 100) {
3933 DRM_ERROR("hardware wedged\n");
3934 dev_priv->mm.wedged = 1;
3935 DRM_WAKEUP(&dev_priv->irq_queue);
3940 last_seqno = cur_seqno;
3942 dev_priv->mm.waiting_gem_seqno = 0;
3944 i915_gem_retire_requests(dev);
3946 spin_lock(&dev_priv->mm.active_list_lock);
3947 if (!dev_priv->mm.wedged) {
3948 /* Active and flushing should now be empty as we've
3949 * waited for a sequence higher than any pending execbuffer
3951 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3952 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3953 /* Request should now be empty as we've also waited
3954 * for the last request in the list
3956 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3959 /* Empty the active and flushing lists to inactive. If there's
3960 * anything left at this point, it means that we're wedged and
3961 * nothing good's going to happen by leaving them there. So strip
3962 * the GPU domains and just stuff them onto inactive.
3964 while (!list_empty(&dev_priv->mm.active_list)) {
3965 struct drm_i915_gem_object *obj_priv;
3967 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3968 struct drm_i915_gem_object,
3970 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3971 i915_gem_object_move_to_inactive(obj_priv->obj);
3973 spin_unlock(&dev_priv->mm.active_list_lock);
3975 while (!list_empty(&dev_priv->mm.flushing_list)) {
3976 struct drm_i915_gem_object *obj_priv;
3978 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3979 struct drm_i915_gem_object,
3981 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3982 i915_gem_object_move_to_inactive(obj_priv->obj);
3986 /* Move all inactive buffers out of the GTT. */
3987 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3988 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3990 mutex_unlock(&dev->struct_mutex);
3994 i915_gem_cleanup_ringbuffer(dev);
3995 mutex_unlock(&dev->struct_mutex);
4001 i915_gem_init_hws(struct drm_device *dev)
4003 drm_i915_private_t *dev_priv = dev->dev_private;
4004 struct drm_gem_object *obj;
4005 struct drm_i915_gem_object *obj_priv;
4008 /* If we need a physical address for the status page, it's already
4009 * initialized at driver load time.
4011 if (!I915_NEED_GFX_HWS(dev))
4014 obj = drm_gem_object_alloc(dev, 4096);
4016 DRM_ERROR("Failed to allocate status page\n");
4019 obj_priv = obj->driver_private;
4020 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4022 ret = i915_gem_object_pin(obj, 4096);
4024 drm_gem_object_unreference(obj);
4028 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4030 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4031 if (dev_priv->hw_status_page == NULL) {
4032 DRM_ERROR("Failed to map status page.\n");
4033 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4034 i915_gem_object_unpin(obj);
4035 drm_gem_object_unreference(obj);
4038 dev_priv->hws_obj = obj;
4039 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4040 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4041 I915_READ(HWS_PGA); /* posting read */
4042 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4048 i915_gem_cleanup_hws(struct drm_device *dev)
4050 drm_i915_private_t *dev_priv = dev->dev_private;
4051 struct drm_gem_object *obj;
4052 struct drm_i915_gem_object *obj_priv;
4054 if (dev_priv->hws_obj == NULL)
4057 obj = dev_priv->hws_obj;
4058 obj_priv = obj->driver_private;
4060 kunmap(obj_priv->pages[0]);
4061 i915_gem_object_unpin(obj);
4062 drm_gem_object_unreference(obj);
4063 dev_priv->hws_obj = NULL;
4065 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4066 dev_priv->hw_status_page = NULL;
4068 /* Write high address into HWS_PGA when disabling. */
4069 I915_WRITE(HWS_PGA, 0x1ffff000);
4073 i915_gem_init_ringbuffer(struct drm_device *dev)
4075 drm_i915_private_t *dev_priv = dev->dev_private;
4076 struct drm_gem_object *obj;
4077 struct drm_i915_gem_object *obj_priv;
4078 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4082 ret = i915_gem_init_hws(dev);
4086 obj = drm_gem_object_alloc(dev, 128 * 1024);
4088 DRM_ERROR("Failed to allocate ringbuffer\n");
4089 i915_gem_cleanup_hws(dev);
4092 obj_priv = obj->driver_private;
4094 ret = i915_gem_object_pin(obj, 4096);
4096 drm_gem_object_unreference(obj);
4097 i915_gem_cleanup_hws(dev);
4101 /* Set up the kernel mapping for the ring. */
4102 ring->Size = obj->size;
4104 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4105 ring->map.size = obj->size;
4107 ring->map.flags = 0;
4110 drm_core_ioremap_wc(&ring->map, dev);
4111 if (ring->map.handle == NULL) {
4112 DRM_ERROR("Failed to map ringbuffer.\n");
4113 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4114 i915_gem_object_unpin(obj);
4115 drm_gem_object_unreference(obj);
4116 i915_gem_cleanup_hws(dev);
4119 ring->ring_obj = obj;
4120 ring->virtual_start = ring->map.handle;
4122 /* Stop the ring if it's running. */
4123 I915_WRITE(PRB0_CTL, 0);
4124 I915_WRITE(PRB0_TAIL, 0);
4125 I915_WRITE(PRB0_HEAD, 0);
4127 /* Initialize the ring. */
4128 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4129 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4131 /* G45 ring initialization fails to reset head to zero */
4133 DRM_ERROR("Ring head not reset to zero "
4134 "ctl %08x head %08x tail %08x start %08x\n",
4135 I915_READ(PRB0_CTL),
4136 I915_READ(PRB0_HEAD),
4137 I915_READ(PRB0_TAIL),
4138 I915_READ(PRB0_START));
4139 I915_WRITE(PRB0_HEAD, 0);
4141 DRM_ERROR("Ring head forced to zero "
4142 "ctl %08x head %08x tail %08x start %08x\n",
4143 I915_READ(PRB0_CTL),
4144 I915_READ(PRB0_HEAD),
4145 I915_READ(PRB0_TAIL),
4146 I915_READ(PRB0_START));
4149 I915_WRITE(PRB0_CTL,
4150 ((obj->size - 4096) & RING_NR_PAGES) |
4154 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4156 /* If the head is still not zero, the ring is dead */
4158 DRM_ERROR("Ring initialization failed "
4159 "ctl %08x head %08x tail %08x start %08x\n",
4160 I915_READ(PRB0_CTL),
4161 I915_READ(PRB0_HEAD),
4162 I915_READ(PRB0_TAIL),
4163 I915_READ(PRB0_START));
4167 /* Update our cache of the ring state */
4168 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4169 i915_kernel_lost_context(dev);
4171 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4172 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4173 ring->space = ring->head - (ring->tail + 8);
4174 if (ring->space < 0)
4175 ring->space += ring->Size;
4182 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4184 drm_i915_private_t *dev_priv = dev->dev_private;
4186 if (dev_priv->ring.ring_obj == NULL)
4189 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4191 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4192 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4193 dev_priv->ring.ring_obj = NULL;
4194 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4196 i915_gem_cleanup_hws(dev);
4200 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4201 struct drm_file *file_priv)
4203 drm_i915_private_t *dev_priv = dev->dev_private;
4206 if (drm_core_check_feature(dev, DRIVER_MODESET))
4209 if (dev_priv->mm.wedged) {
4210 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4211 dev_priv->mm.wedged = 0;
4214 mutex_lock(&dev->struct_mutex);
4215 dev_priv->mm.suspended = 0;
4217 ret = i915_gem_init_ringbuffer(dev);
4219 mutex_unlock(&dev->struct_mutex);
4223 spin_lock(&dev_priv->mm.active_list_lock);
4224 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4225 spin_unlock(&dev_priv->mm.active_list_lock);
4227 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4228 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4229 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4230 mutex_unlock(&dev->struct_mutex);
4232 drm_irq_install(dev);
4238 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4239 struct drm_file *file_priv)
4241 if (drm_core_check_feature(dev, DRIVER_MODESET))
4244 drm_irq_uninstall(dev);
4245 return i915_gem_idle(dev);
4249 i915_gem_lastclose(struct drm_device *dev)
4253 if (drm_core_check_feature(dev, DRIVER_MODESET))
4256 ret = i915_gem_idle(dev);
4258 DRM_ERROR("failed to idle hardware: %d\n", ret);
4262 i915_gem_load(struct drm_device *dev)
4265 drm_i915_private_t *dev_priv = dev->dev_private;
4267 spin_lock_init(&dev_priv->mm.active_list_lock);
4268 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4269 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4270 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4271 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4272 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4273 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4274 i915_gem_retire_work_handler);
4275 dev_priv->mm.next_gem_seqno = 1;
4277 /* Old X drivers will take 0-2 for front, back, depth buffers */
4278 dev_priv->fence_reg_start = 3;
4280 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4281 dev_priv->num_fence_regs = 16;
4283 dev_priv->num_fence_regs = 8;
4285 /* Initialize fence registers to zero */
4286 if (IS_I965G(dev)) {
4287 for (i = 0; i < 16; i++)
4288 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4290 for (i = 0; i < 8; i++)
4291 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4292 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4293 for (i = 0; i < 8; i++)
4294 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4297 i915_gem_detect_bit_6_swizzle(dev);
4301 * Create a physically contiguous memory object for this object
4302 * e.g. for cursor + overlay regs
4304 int i915_gem_init_phys_object(struct drm_device *dev,
4307 drm_i915_private_t *dev_priv = dev->dev_private;
4308 struct drm_i915_gem_phys_object *phys_obj;
4311 if (dev_priv->mm.phys_objs[id - 1] || !size)
4314 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4320 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4321 if (!phys_obj->handle) {
4326 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4329 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4337 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4339 drm_i915_private_t *dev_priv = dev->dev_private;
4340 struct drm_i915_gem_phys_object *phys_obj;
4342 if (!dev_priv->mm.phys_objs[id - 1])
4345 phys_obj = dev_priv->mm.phys_objs[id - 1];
4346 if (phys_obj->cur_obj) {
4347 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4351 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4353 drm_pci_free(dev, phys_obj->handle);
4355 dev_priv->mm.phys_objs[id - 1] = NULL;
4358 void i915_gem_free_all_phys_object(struct drm_device *dev)
4362 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4363 i915_gem_free_phys_object(dev, i);
4366 void i915_gem_detach_phys_object(struct drm_device *dev,
4367 struct drm_gem_object *obj)
4369 struct drm_i915_gem_object *obj_priv;
4374 obj_priv = obj->driver_private;
4375 if (!obj_priv->phys_obj)
4378 ret = i915_gem_object_get_pages(obj);
4382 page_count = obj->size / PAGE_SIZE;
4384 for (i = 0; i < page_count; i++) {
4385 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4386 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4388 memcpy(dst, src, PAGE_SIZE);
4389 kunmap_atomic(dst, KM_USER0);
4391 drm_clflush_pages(obj_priv->pages, page_count);
4392 drm_agp_chipset_flush(dev);
4394 i915_gem_object_put_pages(obj);
4396 obj_priv->phys_obj->cur_obj = NULL;
4397 obj_priv->phys_obj = NULL;
4401 i915_gem_attach_phys_object(struct drm_device *dev,
4402 struct drm_gem_object *obj, int id)
4404 drm_i915_private_t *dev_priv = dev->dev_private;
4405 struct drm_i915_gem_object *obj_priv;
4410 if (id > I915_MAX_PHYS_OBJECT)
4413 obj_priv = obj->driver_private;
4415 if (obj_priv->phys_obj) {
4416 if (obj_priv->phys_obj->id == id)
4418 i915_gem_detach_phys_object(dev, obj);
4422 /* create a new object */
4423 if (!dev_priv->mm.phys_objs[id - 1]) {
4424 ret = i915_gem_init_phys_object(dev, id,
4427 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4432 /* bind to the object */
4433 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4434 obj_priv->phys_obj->cur_obj = obj;
4436 ret = i915_gem_object_get_pages(obj);
4438 DRM_ERROR("failed to get page list\n");
4442 page_count = obj->size / PAGE_SIZE;
4444 for (i = 0; i < page_count; i++) {
4445 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4446 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4448 memcpy(dst, src, PAGE_SIZE);
4449 kunmap_atomic(src, KM_USER0);
4452 i915_gem_object_put_pages(obj);
4460 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4461 struct drm_i915_gem_pwrite *args,
4462 struct drm_file *file_priv)
4464 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4467 char __user *user_data;
4469 user_data = (char __user *) (uintptr_t) args->data_ptr;
4470 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4472 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4473 ret = copy_from_user(obj_addr, user_data, args->size);
4477 drm_agp_chipset_flush(dev);
4481 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4483 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4485 /* Clean up our request list when the client is going away, so that
4486 * later retire_requests won't dereference our soon-to-be-gone
4489 mutex_lock(&dev->struct_mutex);
4490 while (!list_empty(&i915_file_priv->mm.request_list))
4491 list_del_init(i915_file_priv->mm.request_list.next);
4492 mutex_unlock(&dev->struct_mutex);