2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/pci.h>
43 #include <linux/dma-buf.h>
45 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
46 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
47 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
60 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
63 return obj->pin_display;
67 insert_mappable_node(struct i915_ggtt *ggtt,
68 struct drm_mm_node *node, u32 size)
70 memset(node, 0, sizeof(*node));
71 return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node,
73 0, ggtt->mappable_end,
74 DRM_MM_SEARCH_DEFAULT,
75 DRM_MM_CREATE_DEFAULT);
79 remove_mappable_node(struct drm_mm_node *node)
81 drm_mm_remove_node(node);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
88 spin_lock(&dev_priv->mm.object_stat_lock);
89 dev_priv->mm.object_count++;
90 dev_priv->mm.object_memory += size;
91 spin_unlock(&dev_priv->mm.object_stat_lock);
94 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
97 spin_lock(&dev_priv->mm.object_stat_lock);
98 dev_priv->mm.object_count--;
99 dev_priv->mm.object_memory -= size;
100 spin_unlock(&dev_priv->mm.object_stat_lock);
104 i915_gem_wait_for_error(struct i915_gpu_error *error)
110 if (!i915_reset_in_progress(error))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret = wait_event_interruptible_timeout(error->reset_queue,
119 !i915_reset_in_progress(error),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret < 0) {
131 int i915_mutex_lock_interruptible(struct drm_device *dev)
133 struct drm_i915_private *dev_priv = to_i915(dev);
136 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
140 ret = mutex_lock_interruptible(&dev->struct_mutex);
148 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file)
151 struct drm_i915_private *dev_priv = to_i915(dev);
152 struct i915_ggtt *ggtt = &dev_priv->ggtt;
153 struct drm_i915_gem_get_aperture *args = data;
154 struct i915_vma *vma;
158 mutex_lock(&dev->struct_mutex);
159 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
160 if (i915_vma_is_pinned(vma))
161 pinned += vma->node.size;
162 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
163 if (i915_vma_is_pinned(vma))
164 pinned += vma->node.size;
165 mutex_unlock(&dev->struct_mutex);
167 args->aper_size = ggtt->base.total;
168 args->aper_available_size = args->aper_size - pinned;
173 static struct sg_table *
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
176 struct address_space *mapping = obj->base.filp->f_mapping;
177 drm_dma_handle_t *phys;
179 struct scatterlist *sg;
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
184 return ERR_PTR(-EINVAL);
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
190 phys = drm_pci_alloc(obj->base.dev,
192 roundup_pow_of_two(obj->base.size));
194 return ERR_PTR(-ENOMEM);
197 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
201 page = shmem_read_mapping_page(mapping, i);
207 src = kmap_atomic(page);
208 memcpy(vaddr, src, PAGE_SIZE);
209 drm_clflush_virt_range(vaddr, PAGE_SIZE);
216 i915_gem_chipset_flush(to_i915(obj->base.dev));
218 st = kmalloc(sizeof(*st), GFP_KERNEL);
220 st = ERR_PTR(-ENOMEM);
224 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
226 st = ERR_PTR(-ENOMEM);
232 sg->length = obj->base.size;
234 sg_dma_address(sg) = phys->busaddr;
235 sg_dma_len(sg) = obj->base.size;
237 obj->phys_handle = phys;
241 drm_pci_free(obj->base.dev, phys);
246 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
247 struct sg_table *pages)
249 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251 if (obj->mm.madv == I915_MADV_DONTNEED)
252 obj->mm.dirty = false;
254 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
255 !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
256 drm_clflush_sg(pages);
258 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
259 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
264 struct sg_table *pages)
266 __i915_gem_object_release_shmem(obj, pages);
269 struct address_space *mapping = obj->base.filp->f_mapping;
270 char *vaddr = obj->phys_handle->vaddr;
273 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
277 page = shmem_read_mapping_page(mapping, i);
281 dst = kmap_atomic(page);
282 drm_clflush_virt_range(vaddr, PAGE_SIZE);
283 memcpy(dst, vaddr, PAGE_SIZE);
286 set_page_dirty(page);
287 if (obj->mm.madv == I915_MADV_WILLNEED)
288 mark_page_accessed(page);
292 obj->mm.dirty = false;
295 sg_free_table(pages);
298 drm_pci_free(obj->base.dev, obj->phys_handle);
302 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
304 i915_gem_object_unpin_pages(obj);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
308 .get_pages = i915_gem_object_get_pages_phys,
309 .put_pages = i915_gem_object_put_pages_phys,
310 .release = i915_gem_object_release_phys,
313 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
315 struct i915_vma *vma;
316 LIST_HEAD(still_in_list);
319 lockdep_assert_held(&obj->base.dev->struct_mutex);
321 /* Closed vma are removed from the obj->vma_list - but they may
322 * still have an active binding on the object. To remove those we
323 * must wait for all rendering to complete to the object (as unbinding
324 * must anyway), and retire the requests.
326 ret = i915_gem_object_wait(obj,
327 I915_WAIT_INTERRUPTIBLE |
330 MAX_SCHEDULE_TIMEOUT,
335 i915_gem_retire_requests(to_i915(obj->base.dev));
337 while ((vma = list_first_entry_or_null(&obj->vma_list,
340 list_move_tail(&vma->obj_link, &still_in_list);
341 ret = i915_vma_unbind(vma);
345 list_splice(&still_in_list, &obj->vma_list);
351 i915_gem_object_wait_fence(struct dma_fence *fence,
354 struct intel_rps_client *rps)
356 struct drm_i915_gem_request *rq;
358 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
360 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
363 if (!dma_fence_is_i915(fence))
364 return dma_fence_wait_timeout(fence,
365 flags & I915_WAIT_INTERRUPTIBLE,
368 rq = to_request(fence);
369 if (i915_gem_request_completed(rq))
372 /* This client is about to stall waiting for the GPU. In many cases
373 * this is undesirable and limits the throughput of the system, as
374 * many clients cannot continue processing user input/output whilst
375 * blocked. RPS autotuning may take tens of milliseconds to respond
376 * to the GPU load and thus incurs additional latency for the client.
377 * We can circumvent that by promoting the GPU frequency to maximum
378 * before we wait. This makes the GPU throttle up much more quickly
379 * (good for benchmarks and user experience, e.g. window animations),
380 * but at a cost of spending more power processing the workload
381 * (bad for battery). Not all clients even want their results
382 * immediately and for them we should just let the GPU select its own
383 * frequency to maximise efficiency. To prevent a single client from
384 * forcing the clocks too high for the whole system, we only allow
385 * each client to waitboost once in a busy period.
388 if (INTEL_GEN(rq->i915) >= 6)
389 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
394 timeout = i915_wait_request(rq, flags, timeout);
397 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
398 i915_gem_request_retire_upto(rq);
400 if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
401 /* The GPU is now idle and this client has stalled.
402 * Since no other client has submitted a request in the
403 * meantime, assume that this client is the only one
404 * supplying work to the GPU but is unable to keep that
405 * work supplied because it is waiting. Since the GPU is
406 * then never kept fully busy, RPS autoclocking will
407 * keep the clocks relatively low, causing further delays.
408 * Compensate by giving the synchronous client credit for
409 * a waitboost next time.
411 spin_lock(&rq->i915->rps.client_lock);
412 list_del_init(&rps->link);
413 spin_unlock(&rq->i915->rps.client_lock);
420 i915_gem_object_wait_reservation(struct reservation_object *resv,
423 struct intel_rps_client *rps)
425 struct dma_fence *excl;
427 if (flags & I915_WAIT_ALL) {
428 struct dma_fence **shared;
429 unsigned int count, i;
432 ret = reservation_object_get_fences_rcu(resv,
433 &excl, &count, &shared);
437 for (i = 0; i < count; i++) {
438 timeout = i915_gem_object_wait_fence(shared[i],
444 dma_fence_put(shared[i]);
447 for (; i < count; i++)
448 dma_fence_put(shared[i]);
451 excl = reservation_object_get_excl_rcu(resv);
454 if (excl && timeout > 0)
455 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
462 static void __fence_set_priority(struct dma_fence *fence, int prio)
464 struct drm_i915_gem_request *rq;
465 struct intel_engine_cs *engine;
467 if (!dma_fence_is_i915(fence))
470 rq = to_request(fence);
472 if (!engine->schedule)
475 engine->schedule(rq, prio);
478 static void fence_set_priority(struct dma_fence *fence, int prio)
480 /* Recurse once into a fence-array */
481 if (dma_fence_is_array(fence)) {
482 struct dma_fence_array *array = to_dma_fence_array(fence);
485 for (i = 0; i < array->num_fences; i++)
486 __fence_set_priority(array->fences[i], prio);
488 __fence_set_priority(fence, prio);
493 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
497 struct dma_fence *excl;
499 if (flags & I915_WAIT_ALL) {
500 struct dma_fence **shared;
501 unsigned int count, i;
504 ret = reservation_object_get_fences_rcu(obj->resv,
505 &excl, &count, &shared);
509 for (i = 0; i < count; i++) {
510 fence_set_priority(shared[i], prio);
511 dma_fence_put(shared[i]);
516 excl = reservation_object_get_excl_rcu(obj->resv);
520 fence_set_priority(excl, prio);
527 * Waits for rendering to the object to be completed
528 * @obj: i915 gem object
529 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
530 * @timeout: how long to wait
531 * @rps: client (user process) to charge for any waitboosting
534 i915_gem_object_wait(struct drm_i915_gem_object *obj,
537 struct intel_rps_client *rps)
540 #if IS_ENABLED(CONFIG_LOCKDEP)
541 GEM_BUG_ON(debug_locks &&
542 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
543 !!(flags & I915_WAIT_LOCKED));
545 GEM_BUG_ON(timeout < 0);
547 timeout = i915_gem_object_wait_reservation(obj->resv,
550 return timeout < 0 ? timeout : 0;
553 static struct intel_rps_client *to_rps_client(struct drm_file *file)
555 struct drm_i915_file_private *fpriv = file->driver_priv;
561 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
566 if (align > obj->base.size)
569 if (obj->ops == &i915_gem_phys_ops)
572 if (obj->mm.madv != I915_MADV_WILLNEED)
575 if (obj->base.filp == NULL)
578 ret = i915_gem_object_unbind(obj);
582 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
586 obj->ops = &i915_gem_phys_ops;
588 return i915_gem_object_pin_pages(obj);
592 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
593 struct drm_i915_gem_pwrite *args,
594 struct drm_file *file)
596 struct drm_device *dev = obj->base.dev;
597 void *vaddr = obj->phys_handle->vaddr + args->offset;
598 char __user *user_data = u64_to_user_ptr(args->data_ptr);
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
604 lockdep_assert_held(&obj->base.dev->struct_mutex);
605 ret = i915_gem_object_wait(obj,
606 I915_WAIT_INTERRUPTIBLE |
609 MAX_SCHEDULE_TIMEOUT,
610 to_rps_client(file));
614 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
615 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
616 unsigned long unwritten;
618 /* The physical object once assigned is fixed for the lifetime
619 * of the obj, so we can safely drop the lock and continue
622 mutex_unlock(&dev->struct_mutex);
623 unwritten = copy_from_user(vaddr, user_data, args->size);
624 mutex_lock(&dev->struct_mutex);
631 drm_clflush_virt_range(vaddr, args->size);
632 i915_gem_chipset_flush(to_i915(dev));
635 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
639 void *i915_gem_object_alloc(struct drm_device *dev)
641 struct drm_i915_private *dev_priv = to_i915(dev);
642 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
645 void i915_gem_object_free(struct drm_i915_gem_object *obj)
647 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
648 kmem_cache_free(dev_priv->objects, obj);
652 i915_gem_create(struct drm_file *file,
653 struct drm_device *dev,
657 struct drm_i915_gem_object *obj;
661 size = roundup(size, PAGE_SIZE);
665 /* Allocate the new object */
666 obj = i915_gem_object_create(dev, size);
670 ret = drm_gem_handle_create(file, &obj->base, &handle);
671 /* drop reference from allocate - handle holds it now */
672 i915_gem_object_put(obj);
681 i915_gem_dumb_create(struct drm_file *file,
682 struct drm_device *dev,
683 struct drm_mode_create_dumb *args)
685 /* have to work out size/pitch and return them */
686 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
687 args->size = args->pitch * args->height;
688 return i915_gem_create(file, dev,
689 args->size, &args->handle);
693 * Creates a new mm object and returns a handle to it.
694 * @dev: drm device pointer
695 * @data: ioctl data blob
696 * @file: drm file pointer
699 i915_gem_create_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *file)
702 struct drm_i915_gem_create *args = data;
704 i915_gem_flush_free_objects(to_i915(dev));
706 return i915_gem_create(file, dev,
707 args->size, &args->handle);
711 __copy_to_user_swizzled(char __user *cpu_vaddr,
712 const char *gpu_vaddr, int gpu_offset,
715 int ret, cpu_offset = 0;
718 int cacheline_end = ALIGN(gpu_offset + 1, 64);
719 int this_length = min(cacheline_end - gpu_offset, length);
720 int swizzled_gpu_offset = gpu_offset ^ 64;
722 ret = __copy_to_user(cpu_vaddr + cpu_offset,
723 gpu_vaddr + swizzled_gpu_offset,
728 cpu_offset += this_length;
729 gpu_offset += this_length;
730 length -= this_length;
737 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
738 const char __user *cpu_vaddr,
741 int ret, cpu_offset = 0;
744 int cacheline_end = ALIGN(gpu_offset + 1, 64);
745 int this_length = min(cacheline_end - gpu_offset, length);
746 int swizzled_gpu_offset = gpu_offset ^ 64;
748 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
749 cpu_vaddr + cpu_offset,
754 cpu_offset += this_length;
755 gpu_offset += this_length;
756 length -= this_length;
763 * Pins the specified object's pages and synchronizes the object with
764 * GPU accesses. Sets needs_clflush to non-zero if the caller should
765 * flush the object from the CPU cache.
767 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
768 unsigned int *needs_clflush)
772 lockdep_assert_held(&obj->base.dev->struct_mutex);
775 if (!i915_gem_object_has_struct_page(obj))
778 ret = i915_gem_object_wait(obj,
779 I915_WAIT_INTERRUPTIBLE |
781 MAX_SCHEDULE_TIMEOUT,
786 ret = i915_gem_object_pin_pages(obj);
790 i915_gem_object_flush_gtt_write_domain(obj);
792 /* If we're not in the cpu read domain, set ourself into the gtt
793 * read domain and manually flush cachelines (if required). This
794 * optimizes for the case when the gpu will dirty the data
795 * anyway again before the next pread happens.
797 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
798 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
801 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
802 ret = i915_gem_object_set_to_cpu_domain(obj, false);
809 /* return with the pages pinned */
813 i915_gem_object_unpin_pages(obj);
817 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
818 unsigned int *needs_clflush)
822 lockdep_assert_held(&obj->base.dev->struct_mutex);
825 if (!i915_gem_object_has_struct_page(obj))
828 ret = i915_gem_object_wait(obj,
829 I915_WAIT_INTERRUPTIBLE |
832 MAX_SCHEDULE_TIMEOUT,
837 ret = i915_gem_object_pin_pages(obj);
841 i915_gem_object_flush_gtt_write_domain(obj);
843 /* If we're not in the cpu write domain, set ourself into the
844 * gtt write domain and manually flush cachelines (as required).
845 * This optimizes for the case when the gpu will use the data
846 * right away and we therefore have to clflush anyway.
848 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
849 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
851 /* Same trick applies to invalidate partially written cachelines read
854 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
855 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
858 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
859 ret = i915_gem_object_set_to_cpu_domain(obj, true);
866 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
867 obj->cache_dirty = true;
869 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
870 obj->mm.dirty = true;
871 /* return with the pages pinned */
875 i915_gem_object_unpin_pages(obj);
880 shmem_clflush_swizzled_range(char *addr, unsigned long length,
883 if (unlikely(swizzled)) {
884 unsigned long start = (unsigned long) addr;
885 unsigned long end = (unsigned long) addr + length;
887 /* For swizzling simply ensure that we always flush both
888 * channels. Lame, but simple and it works. Swizzled
889 * pwrite/pread is far from a hotpath - current userspace
890 * doesn't use it at all. */
891 start = round_down(start, 128);
892 end = round_up(end, 128);
894 drm_clflush_virt_range((void *)start, end - start);
896 drm_clflush_virt_range(addr, length);
901 /* Only difference to the fast-path function is that this can handle bit17
902 * and uses non-atomic copy and kmap functions. */
904 shmem_pread_slow(struct page *page, int offset, int length,
905 char __user *user_data,
906 bool page_do_bit17_swizzling, bool needs_clflush)
913 shmem_clflush_swizzled_range(vaddr + offset, length,
914 page_do_bit17_swizzling);
916 if (page_do_bit17_swizzling)
917 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
919 ret = __copy_to_user(user_data, vaddr + offset, length);
922 return ret ? - EFAULT : 0;
926 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
927 bool page_do_bit17_swizzling, bool needs_clflush)
932 if (!page_do_bit17_swizzling) {
933 char *vaddr = kmap_atomic(page);
936 drm_clflush_virt_range(vaddr + offset, length);
937 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
938 kunmap_atomic(vaddr);
943 return shmem_pread_slow(page, offset, length, user_data,
944 page_do_bit17_swizzling, needs_clflush);
948 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
949 struct drm_i915_gem_pread *args)
951 char __user *user_data;
953 unsigned int obj_do_bit17_swizzling;
954 unsigned int needs_clflush;
955 unsigned int idx, offset;
958 obj_do_bit17_swizzling = 0;
959 if (i915_gem_object_needs_bit17_swizzle(obj))
960 obj_do_bit17_swizzling = BIT(17);
962 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
966 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
967 mutex_unlock(&obj->base.dev->struct_mutex);
972 user_data = u64_to_user_ptr(args->data_ptr);
973 offset = offset_in_page(args->offset);
974 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
975 struct page *page = i915_gem_object_get_page(obj, idx);
979 if (offset + length > PAGE_SIZE)
980 length = PAGE_SIZE - offset;
982 ret = shmem_pread(page, offset, length, user_data,
983 page_to_phys(page) & obj_do_bit17_swizzling,
993 i915_gem_obj_finish_shmem_access(obj);
998 gtt_user_read(struct io_mapping *mapping,
999 loff_t base, int offset,
1000 char __user *user_data, int length)
1003 unsigned long unwritten;
1005 /* We can use the cpu mem copy function because this is X86. */
1006 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1007 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1008 io_mapping_unmap_atomic(vaddr);
1010 vaddr = (void __force *)
1011 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1012 unwritten = copy_to_user(user_data, vaddr + offset, length);
1013 io_mapping_unmap(vaddr);
1019 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1020 const struct drm_i915_gem_pread *args)
1022 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1023 struct i915_ggtt *ggtt = &i915->ggtt;
1024 struct drm_mm_node node;
1025 struct i915_vma *vma;
1026 void __user *user_data;
1030 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1034 intel_runtime_pm_get(i915);
1035 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1036 PIN_MAPPABLE | PIN_NONBLOCK);
1038 node.start = i915_ggtt_offset(vma);
1039 node.allocated = false;
1040 ret = i915_vma_put_fence(vma);
1042 i915_vma_unpin(vma);
1047 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1050 GEM_BUG_ON(!node.allocated);
1053 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1057 mutex_unlock(&i915->drm.struct_mutex);
1059 user_data = u64_to_user_ptr(args->data_ptr);
1060 remain = args->size;
1061 offset = args->offset;
1063 while (remain > 0) {
1064 /* Operation in this page
1066 * page_base = page offset within aperture
1067 * page_offset = offset within page
1068 * page_length = bytes to copy for this page
1070 u32 page_base = node.start;
1071 unsigned page_offset = offset_in_page(offset);
1072 unsigned page_length = PAGE_SIZE - page_offset;
1073 page_length = remain < page_length ? remain : page_length;
1074 if (node.allocated) {
1076 ggtt->base.insert_page(&ggtt->base,
1077 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1078 node.start, I915_CACHE_NONE, 0);
1081 page_base += offset & PAGE_MASK;
1084 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1085 user_data, page_length)) {
1090 remain -= page_length;
1091 user_data += page_length;
1092 offset += page_length;
1095 mutex_lock(&i915->drm.struct_mutex);
1097 if (node.allocated) {
1099 ggtt->base.clear_range(&ggtt->base,
1100 node.start, node.size);
1101 remove_mappable_node(&node);
1103 i915_vma_unpin(vma);
1106 intel_runtime_pm_put(i915);
1107 mutex_unlock(&i915->drm.struct_mutex);
1113 * Reads data from the object referenced by handle.
1114 * @dev: drm device pointer
1115 * @data: ioctl data blob
1116 * @file: drm file pointer
1118 * On error, the contents of *data are undefined.
1121 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1122 struct drm_file *file)
1124 struct drm_i915_gem_pread *args = data;
1125 struct drm_i915_gem_object *obj;
1128 if (args->size == 0)
1131 if (!access_ok(VERIFY_WRITE,
1132 u64_to_user_ptr(args->data_ptr),
1136 obj = i915_gem_object_lookup(file, args->handle);
1140 /* Bounds check source. */
1141 if (args->offset > obj->base.size ||
1142 args->size > obj->base.size - args->offset) {
1147 trace_i915_gem_object_pread(obj, args->offset, args->size);
1149 ret = i915_gem_object_wait(obj,
1150 I915_WAIT_INTERRUPTIBLE,
1151 MAX_SCHEDULE_TIMEOUT,
1152 to_rps_client(file));
1156 ret = i915_gem_object_pin_pages(obj);
1160 ret = i915_gem_shmem_pread(obj, args);
1161 if (ret == -EFAULT || ret == -ENODEV)
1162 ret = i915_gem_gtt_pread(obj, args);
1164 i915_gem_object_unpin_pages(obj);
1166 i915_gem_object_put(obj);
1170 /* This is the fast write path which cannot handle
1171 * page faults in the source data
1175 ggtt_write(struct io_mapping *mapping,
1176 loff_t base, int offset,
1177 char __user *user_data, int length)
1180 unsigned long unwritten;
1182 /* We can use the cpu mem copy function because this is X86. */
1183 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1184 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1186 io_mapping_unmap_atomic(vaddr);
1188 vaddr = (void __force *)
1189 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1190 unwritten = copy_from_user(vaddr + offset, user_data, length);
1191 io_mapping_unmap(vaddr);
1198 * This is the fast pwrite path, where we copy the data directly from the
1199 * user into the GTT, uncached.
1200 * @obj: i915 GEM object
1201 * @args: pwrite arguments structure
1204 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1205 const struct drm_i915_gem_pwrite *args)
1207 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1208 struct i915_ggtt *ggtt = &i915->ggtt;
1209 struct drm_mm_node node;
1210 struct i915_vma *vma;
1212 void __user *user_data;
1215 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1219 intel_runtime_pm_get(i915);
1220 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1221 PIN_MAPPABLE | PIN_NONBLOCK);
1223 node.start = i915_ggtt_offset(vma);
1224 node.allocated = false;
1225 ret = i915_vma_put_fence(vma);
1227 i915_vma_unpin(vma);
1232 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1235 GEM_BUG_ON(!node.allocated);
1238 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1242 mutex_unlock(&i915->drm.struct_mutex);
1244 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1246 user_data = u64_to_user_ptr(args->data_ptr);
1247 offset = args->offset;
1248 remain = args->size;
1250 /* Operation in this page
1252 * page_base = page offset within aperture
1253 * page_offset = offset within page
1254 * page_length = bytes to copy for this page
1256 u32 page_base = node.start;
1257 unsigned int page_offset = offset_in_page(offset);
1258 unsigned int page_length = PAGE_SIZE - page_offset;
1259 page_length = remain < page_length ? remain : page_length;
1260 if (node.allocated) {
1261 wmb(); /* flush the write before we modify the GGTT */
1262 ggtt->base.insert_page(&ggtt->base,
1263 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1264 node.start, I915_CACHE_NONE, 0);
1265 wmb(); /* flush modifications to the GGTT (insert_page) */
1267 page_base += offset & PAGE_MASK;
1269 /* If we get a fault while copying data, then (presumably) our
1270 * source page isn't available. Return the error and we'll
1271 * retry in the slow path.
1272 * If the object is non-shmem backed, we retry again with the
1273 * path that handles page fault.
1275 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1276 user_data, page_length)) {
1281 remain -= page_length;
1282 user_data += page_length;
1283 offset += page_length;
1285 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1287 mutex_lock(&i915->drm.struct_mutex);
1289 if (node.allocated) {
1291 ggtt->base.clear_range(&ggtt->base,
1292 node.start, node.size);
1293 remove_mappable_node(&node);
1295 i915_vma_unpin(vma);
1298 intel_runtime_pm_put(i915);
1299 mutex_unlock(&i915->drm.struct_mutex);
1304 shmem_pwrite_slow(struct page *page, int offset, int length,
1305 char __user *user_data,
1306 bool page_do_bit17_swizzling,
1307 bool needs_clflush_before,
1308 bool needs_clflush_after)
1314 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1315 shmem_clflush_swizzled_range(vaddr + offset, length,
1316 page_do_bit17_swizzling);
1317 if (page_do_bit17_swizzling)
1318 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1321 ret = __copy_from_user(vaddr + offset, user_data, length);
1322 if (needs_clflush_after)
1323 shmem_clflush_swizzled_range(vaddr + offset, length,
1324 page_do_bit17_swizzling);
1327 return ret ? -EFAULT : 0;
1330 /* Per-page copy function for the shmem pwrite fastpath.
1331 * Flushes invalid cachelines before writing to the target if
1332 * needs_clflush_before is set and flushes out any written cachelines after
1333 * writing if needs_clflush is set.
1336 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1337 bool page_do_bit17_swizzling,
1338 bool needs_clflush_before,
1339 bool needs_clflush_after)
1344 if (!page_do_bit17_swizzling) {
1345 char *vaddr = kmap_atomic(page);
1347 if (needs_clflush_before)
1348 drm_clflush_virt_range(vaddr + offset, len);
1349 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1350 if (needs_clflush_after)
1351 drm_clflush_virt_range(vaddr + offset, len);
1353 kunmap_atomic(vaddr);
1358 return shmem_pwrite_slow(page, offset, len, user_data,
1359 page_do_bit17_swizzling,
1360 needs_clflush_before,
1361 needs_clflush_after);
1365 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1366 const struct drm_i915_gem_pwrite *args)
1368 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1369 void __user *user_data;
1371 unsigned int obj_do_bit17_swizzling;
1372 unsigned int partial_cacheline_write;
1373 unsigned int needs_clflush;
1374 unsigned int offset, idx;
1377 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1381 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1382 mutex_unlock(&i915->drm.struct_mutex);
1386 obj_do_bit17_swizzling = 0;
1387 if (i915_gem_object_needs_bit17_swizzle(obj))
1388 obj_do_bit17_swizzling = BIT(17);
1390 /* If we don't overwrite a cacheline completely we need to be
1391 * careful to have up-to-date data by first clflushing. Don't
1392 * overcomplicate things and flush the entire patch.
1394 partial_cacheline_write = 0;
1395 if (needs_clflush & CLFLUSH_BEFORE)
1396 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1398 user_data = u64_to_user_ptr(args->data_ptr);
1399 remain = args->size;
1400 offset = offset_in_page(args->offset);
1401 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1402 struct page *page = i915_gem_object_get_page(obj, idx);
1406 if (offset + length > PAGE_SIZE)
1407 length = PAGE_SIZE - offset;
1409 ret = shmem_pwrite(page, offset, length, user_data,
1410 page_to_phys(page) & obj_do_bit17_swizzling,
1411 (offset | length) & partial_cacheline_write,
1412 needs_clflush & CLFLUSH_AFTER);
1417 user_data += length;
1421 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1422 i915_gem_obj_finish_shmem_access(obj);
1427 * Writes data to the object referenced by handle.
1429 * @data: ioctl data blob
1432 * On error, the contents of the buffer that were to be modified are undefined.
1435 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1436 struct drm_file *file)
1438 struct drm_i915_gem_pwrite *args = data;
1439 struct drm_i915_gem_object *obj;
1442 if (args->size == 0)
1445 if (!access_ok(VERIFY_READ,
1446 u64_to_user_ptr(args->data_ptr),
1450 obj = i915_gem_object_lookup(file, args->handle);
1454 /* Bounds check destination. */
1455 if (args->offset > obj->base.size ||
1456 args->size > obj->base.size - args->offset) {
1461 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1463 ret = i915_gem_object_wait(obj,
1464 I915_WAIT_INTERRUPTIBLE |
1466 MAX_SCHEDULE_TIMEOUT,
1467 to_rps_client(file));
1471 ret = i915_gem_object_pin_pages(obj);
1476 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1477 * it would end up going through the fenced access, and we'll get
1478 * different detiling behavior between reading and writing.
1479 * pread/pwrite currently are reading and writing from the CPU
1480 * perspective, requiring manual detiling by the client.
1482 if (!i915_gem_object_has_struct_page(obj) ||
1483 cpu_write_needs_clflush(obj))
1484 /* Note that the gtt paths might fail with non-page-backed user
1485 * pointers (e.g. gtt mappings when moving data between
1486 * textures). Fallback to the shmem path in that case.
1488 ret = i915_gem_gtt_pwrite_fast(obj, args);
1490 if (ret == -EFAULT || ret == -ENOSPC) {
1491 if (obj->phys_handle)
1492 ret = i915_gem_phys_pwrite(obj, args, file);
1494 ret = i915_gem_shmem_pwrite(obj, args);
1497 i915_gem_object_unpin_pages(obj);
1499 i915_gem_object_put(obj);
1503 static inline enum fb_op_origin
1504 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1506 return (domain == I915_GEM_DOMAIN_GTT ?
1507 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1510 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1512 struct drm_i915_private *i915;
1513 struct list_head *list;
1514 struct i915_vma *vma;
1516 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1517 if (!i915_vma_is_ggtt(vma))
1520 if (i915_vma_is_active(vma))
1523 if (!drm_mm_node_allocated(&vma->node))
1526 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1529 i915 = to_i915(obj->base.dev);
1530 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1531 list_move_tail(&obj->global_link, list);
1535 * Called when user space prepares to use an object with the CPU, either
1536 * through the mmap ioctl's mapping or a GTT mapping.
1538 * @data: ioctl data blob
1542 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1543 struct drm_file *file)
1545 struct drm_i915_gem_set_domain *args = data;
1546 struct drm_i915_gem_object *obj;
1547 uint32_t read_domains = args->read_domains;
1548 uint32_t write_domain = args->write_domain;
1551 /* Only handle setting domains to types used by the CPU. */
1552 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1555 /* Having something in the write domain implies it's in the read
1556 * domain, and only that read domain. Enforce that in the request.
1558 if (write_domain != 0 && read_domains != write_domain)
1561 obj = i915_gem_object_lookup(file, args->handle);
1565 /* Try to flush the object off the GPU without holding the lock.
1566 * We will repeat the flush holding the lock in the normal manner
1567 * to catch cases where we are gazumped.
1569 err = i915_gem_object_wait(obj,
1570 I915_WAIT_INTERRUPTIBLE |
1571 (write_domain ? I915_WAIT_ALL : 0),
1572 MAX_SCHEDULE_TIMEOUT,
1573 to_rps_client(file));
1577 /* Flush and acquire obj->pages so that we are coherent through
1578 * direct access in memory with previous cached writes through
1579 * shmemfs and that our cache domain tracking remains valid.
1580 * For example, if the obj->filp was moved to swap without us
1581 * being notified and releasing the pages, we would mistakenly
1582 * continue to assume that the obj remained out of the CPU cached
1585 err = i915_gem_object_pin_pages(obj);
1589 err = i915_mutex_lock_interruptible(dev);
1593 if (read_domains & I915_GEM_DOMAIN_GTT)
1594 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1596 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1598 /* And bump the LRU for this access */
1599 i915_gem_object_bump_inactive_ggtt(obj);
1601 mutex_unlock(&dev->struct_mutex);
1603 if (write_domain != 0)
1604 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1607 i915_gem_object_unpin_pages(obj);
1609 i915_gem_object_put(obj);
1614 * Called when user space has done writes to this buffer
1616 * @data: ioctl data blob
1620 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file)
1623 struct drm_i915_gem_sw_finish *args = data;
1624 struct drm_i915_gem_object *obj;
1627 obj = i915_gem_object_lookup(file, args->handle);
1631 /* Pinned buffers may be scanout, so flush the cache */
1632 if (READ_ONCE(obj->pin_display)) {
1633 err = i915_mutex_lock_interruptible(dev);
1635 i915_gem_object_flush_cpu_write_domain(obj);
1636 mutex_unlock(&dev->struct_mutex);
1640 i915_gem_object_put(obj);
1645 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1648 * @data: ioctl data blob
1651 * While the mapping holds a reference on the contents of the object, it doesn't
1652 * imply a ref on the object itself.
1656 * DRM driver writers who look a this function as an example for how to do GEM
1657 * mmap support, please don't implement mmap support like here. The modern way
1658 * to implement DRM mmap support is with an mmap offset ioctl (like
1659 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1660 * That way debug tooling like valgrind will understand what's going on, hiding
1661 * the mmap call in a driver private ioctl will break that. The i915 driver only
1662 * does cpu mmaps this way because we didn't know better.
1665 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1666 struct drm_file *file)
1668 struct drm_i915_gem_mmap *args = data;
1669 struct drm_i915_gem_object *obj;
1672 if (args->flags & ~(I915_MMAP_WC))
1675 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1678 obj = i915_gem_object_lookup(file, args->handle);
1682 /* prime objects have no backing filp to GEM mmap
1685 if (!obj->base.filp) {
1686 i915_gem_object_put(obj);
1690 addr = vm_mmap(obj->base.filp, 0, args->size,
1691 PROT_READ | PROT_WRITE, MAP_SHARED,
1693 if (args->flags & I915_MMAP_WC) {
1694 struct mm_struct *mm = current->mm;
1695 struct vm_area_struct *vma;
1697 if (down_write_killable(&mm->mmap_sem)) {
1698 i915_gem_object_put(obj);
1701 vma = find_vma(mm, addr);
1704 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1707 up_write(&mm->mmap_sem);
1709 /* This may race, but that's ok, it only gets set */
1710 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1712 i915_gem_object_put(obj);
1713 if (IS_ERR((void *)addr))
1716 args->addr_ptr = (uint64_t) addr;
1721 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1725 size = i915_gem_object_get_stride(obj);
1726 size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
1728 return size >> PAGE_SHIFT;
1732 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1734 * A history of the GTT mmap interface:
1736 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1737 * aligned and suitable for fencing, and still fit into the available
1738 * mappable space left by the pinned display objects. A classic problem
1739 * we called the page-fault-of-doom where we would ping-pong between
1740 * two objects that could not fit inside the GTT and so the memcpy
1741 * would page one object in at the expense of the other between every
1744 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1745 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1746 * object is too large for the available space (or simply too large
1747 * for the mappable aperture!), a view is created instead and faulted
1748 * into userspace. (This view is aligned and sized appropriately for
1753 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1754 * hangs on some architectures, corruption on others. An attempt to service
1755 * a GTT page fault from a snoopable object will generate a SIGBUS.
1757 * * the object must be able to fit into RAM (physical memory, though no
1758 * limited to the mappable aperture).
1763 * * a new GTT page fault will synchronize rendering from the GPU and flush
1764 * all data to system memory. Subsequent access will not be synchronized.
1766 * * all mappings are revoked on runtime device suspend.
1768 * * there are only 8, 16 or 32 fence registers to share between all users
1769 * (older machines require fence register for display and blitter access
1770 * as well). Contention of the fence registers will cause the previous users
1771 * to be unmapped and any new access will generate new page faults.
1773 * * running out of memory while servicing a fault may generate a SIGBUS,
1774 * rather than the expected SIGSEGV.
1776 int i915_gem_mmap_gtt_version(void)
1782 * i915_gem_fault - fault a page into the GTT
1783 * @area: CPU VMA in question
1786 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1787 * from userspace. The fault handler takes care of binding the object to
1788 * the GTT (if needed), allocating and programming a fence register (again,
1789 * only if needed based on whether the old reg is still valid or the object
1790 * is tiled) and inserting a new PTE into the faulting process.
1792 * Note that the faulting process may involve evicting existing objects
1793 * from the GTT and/or fence registers to make room. So performance may
1794 * suffer if the GTT working set is large or there are few fence registers
1797 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1798 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1800 int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1802 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1803 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1804 struct drm_device *dev = obj->base.dev;
1805 struct drm_i915_private *dev_priv = to_i915(dev);
1806 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1807 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1808 struct i915_vma *vma;
1809 pgoff_t page_offset;
1813 /* We don't use vmf->pgoff since that has the fake offset */
1814 page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >>
1817 trace_i915_gem_object_fault(obj, page_offset, true, write);
1819 /* Try to flush the object off the GPU first without holding the lock.
1820 * Upon acquiring the lock, we will perform our sanity checks and then
1821 * repeat the flush holding the lock in the normal manner to catch cases
1822 * where we are gazumped.
1824 ret = i915_gem_object_wait(obj,
1825 I915_WAIT_INTERRUPTIBLE,
1826 MAX_SCHEDULE_TIMEOUT,
1831 ret = i915_gem_object_pin_pages(obj);
1835 intel_runtime_pm_get(dev_priv);
1837 ret = i915_mutex_lock_interruptible(dev);
1841 /* Access to snoopable pages through the GTT is incoherent. */
1842 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1847 /* If the object is smaller than a couple of partial vma, it is
1848 * not worth only creating a single partial vma - we may as well
1849 * clear enough space for the full object.
1851 flags = PIN_MAPPABLE;
1852 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1853 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1855 /* Now pin it into the GTT as needed */
1856 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1858 struct i915_ggtt_view view;
1859 unsigned int chunk_size;
1861 /* Use a partial view if it is bigger than available space */
1862 chunk_size = MIN_CHUNK_PAGES;
1863 if (i915_gem_object_is_tiled(obj))
1864 chunk_size = roundup(chunk_size, tile_row_pages(obj));
1866 memset(&view, 0, sizeof(view));
1867 view.type = I915_GGTT_VIEW_PARTIAL;
1868 view.params.partial.offset = rounddown(page_offset, chunk_size);
1869 view.params.partial.size =
1870 min_t(unsigned int, chunk_size,
1871 vma_pages(area) - view.params.partial.offset);
1873 /* If the partial covers the entire object, just create a
1876 if (chunk_size >= obj->base.size >> PAGE_SHIFT)
1877 view.type = I915_GGTT_VIEW_NORMAL;
1879 /* Userspace is now writing through an untracked VMA, abandon
1880 * all hope that the hardware is able to track future writes.
1882 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1884 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1891 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1895 ret = i915_vma_get_fence(vma);
1899 /* Mark as being mmapped into userspace for later revocation */
1900 assert_rpm_wakelock_held(dev_priv);
1901 if (list_empty(&obj->userfault_link))
1902 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1904 /* Finally, remap it using the new GTT offset */
1905 ret = remap_io_mapping(area,
1906 area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
1907 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1908 min_t(u64, vma->size, area->vm_end - area->vm_start),
1912 __i915_vma_unpin(vma);
1914 mutex_unlock(&dev->struct_mutex);
1916 intel_runtime_pm_put(dev_priv);
1917 i915_gem_object_unpin_pages(obj);
1922 * We eat errors when the gpu is terminally wedged to avoid
1923 * userspace unduly crashing (gl has no provisions for mmaps to
1924 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1925 * and so needs to be reported.
1927 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1928 ret = VM_FAULT_SIGBUS;
1933 * EAGAIN means the gpu is hung and we'll wait for the error
1934 * handler to reset everything when re-faulting in
1935 * i915_mutex_lock_interruptible.
1942 * EBUSY is ok: this just means that another thread
1943 * already did the job.
1945 ret = VM_FAULT_NOPAGE;
1952 ret = VM_FAULT_SIGBUS;
1955 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1956 ret = VM_FAULT_SIGBUS;
1963 * i915_gem_release_mmap - remove physical page mappings
1964 * @obj: obj in question
1966 * Preserve the reservation of the mmapping with the DRM core code, but
1967 * relinquish ownership of the pages back to the system.
1969 * It is vital that we remove the page mapping if we have mapped a tiled
1970 * object through the GTT and then lose the fence register due to
1971 * resource pressure. Similarly if the object has been moved out of the
1972 * aperture, than pages mapped into userspace must be revoked. Removing the
1973 * mapping will then trigger a page fault on the next user access, allowing
1974 * fixup by i915_gem_fault().
1977 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1979 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1981 /* Serialisation between user GTT access and our code depends upon
1982 * revoking the CPU's PTE whilst the mutex is held. The next user
1983 * pagefault then has to wait until we release the mutex.
1985 * Note that RPM complicates somewhat by adding an additional
1986 * requirement that operations to the GGTT be made holding the RPM
1989 lockdep_assert_held(&i915->drm.struct_mutex);
1990 intel_runtime_pm_get(i915);
1992 if (list_empty(&obj->userfault_link))
1995 list_del_init(&obj->userfault_link);
1996 drm_vma_node_unmap(&obj->base.vma_node,
1997 obj->base.dev->anon_inode->i_mapping);
1999 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2000 * memory transactions from userspace before we return. The TLB
2001 * flushing implied above by changing the PTE above *should* be
2002 * sufficient, an extra barrier here just provides us with a bit
2003 * of paranoid documentation about our requirement to serialise
2004 * memory writes before touching registers / GSM.
2009 intel_runtime_pm_put(i915);
2012 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2014 struct drm_i915_gem_object *obj, *on;
2018 * Only called during RPM suspend. All users of the userfault_list
2019 * must be holding an RPM wakeref to ensure that this can not
2020 * run concurrently with themselves (and use the struct_mutex for
2021 * protection between themselves).
2024 list_for_each_entry_safe(obj, on,
2025 &dev_priv->mm.userfault_list, userfault_link) {
2026 list_del_init(&obj->userfault_link);
2027 drm_vma_node_unmap(&obj->base.vma_node,
2028 obj->base.dev->anon_inode->i_mapping);
2031 /* The fence will be lost when the device powers down. If any were
2032 * in use by hardware (i.e. they are pinned), we should not be powering
2033 * down! All other fences will be reacquired by the user upon waking.
2035 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2036 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2038 if (WARN_ON(reg->pin_count))
2044 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2050 * i915_gem_get_ggtt_size - return required global GTT size for an object
2051 * @dev_priv: i915 device
2052 * @size: object size
2053 * @tiling_mode: tiling mode
2055 * Return the required global GTT size for an object, taking into account
2056 * potential fence register mapping.
2058 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
2059 u64 size, int tiling_mode)
2063 GEM_BUG_ON(size == 0);
2065 if (INTEL_GEN(dev_priv) >= 4 ||
2066 tiling_mode == I915_TILING_NONE)
2069 /* Previous chips need a power-of-two fence region when tiling */
2070 if (IS_GEN3(dev_priv))
2071 ggtt_size = 1024*1024;
2073 ggtt_size = 512*1024;
2075 while (ggtt_size < size)
2082 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2083 * @dev_priv: i915 device
2084 * @size: object size
2085 * @tiling_mode: tiling mode
2086 * @fenced: is fenced alignment required or not
2088 * Return the required global GTT alignment for an object, taking into account
2089 * potential fence register mapping.
2091 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
2092 int tiling_mode, bool fenced)
2094 GEM_BUG_ON(size == 0);
2097 * Minimum alignment is 4k (GTT page size), but might be greater
2098 * if a fence register is needed for the object.
2100 if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
2101 tiling_mode == I915_TILING_NONE)
2105 * Previous chips need to be aligned to the size of the smallest
2106 * fence register that can contain the object.
2108 return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
2111 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2113 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2116 err = drm_gem_create_mmap_offset(&obj->base);
2120 /* We can idle the GPU locklessly to flush stale objects, but in order
2121 * to claim that space for ourselves, we need to take the big
2122 * struct_mutex to free the requests+objects and allocate our slot.
2124 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2128 err = i915_mutex_lock_interruptible(&dev_priv->drm);
2130 i915_gem_retire_requests(dev_priv);
2131 err = drm_gem_create_mmap_offset(&obj->base);
2132 mutex_unlock(&dev_priv->drm.struct_mutex);
2138 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2140 drm_gem_free_mmap_offset(&obj->base);
2144 i915_gem_mmap_gtt(struct drm_file *file,
2145 struct drm_device *dev,
2149 struct drm_i915_gem_object *obj;
2152 obj = i915_gem_object_lookup(file, handle);
2156 ret = i915_gem_object_create_mmap_offset(obj);
2158 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2160 i915_gem_object_put(obj);
2165 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2167 * @data: GTT mapping ioctl data
2168 * @file: GEM object info
2170 * Simply returns the fake offset to userspace so it can mmap it.
2171 * The mmap call will end up in drm_gem_mmap(), which will set things
2172 * up so we can get faults in the handler above.
2174 * The fault handler will take care of binding the object into the GTT
2175 * (since it may have been evicted to make room for something), allocating
2176 * a fence register, and mapping the appropriate aperture address into
2180 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *file)
2183 struct drm_i915_gem_mmap_gtt *args = data;
2185 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2188 /* Immediately discard the backing storage */
2190 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2192 i915_gem_object_free_mmap_offset(obj);
2194 if (obj->base.filp == NULL)
2197 /* Our goal here is to return as much of the memory as
2198 * is possible back to the system as we are called from OOM.
2199 * To do this we must instruct the shmfs to drop all of its
2200 * backing pages, *now*.
2202 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2203 obj->mm.madv = __I915_MADV_PURGED;
2206 /* Try to discard unwanted pages */
2207 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2209 struct address_space *mapping;
2211 lockdep_assert_held(&obj->mm.lock);
2212 GEM_BUG_ON(obj->mm.pages);
2214 switch (obj->mm.madv) {
2215 case I915_MADV_DONTNEED:
2216 i915_gem_object_truncate(obj);
2217 case __I915_MADV_PURGED:
2221 if (obj->base.filp == NULL)
2224 mapping = obj->base.filp->f_mapping,
2225 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2229 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2230 struct sg_table *pages)
2232 struct sgt_iter sgt_iter;
2235 __i915_gem_object_release_shmem(obj, pages);
2237 i915_gem_gtt_finish_pages(obj, pages);
2239 if (i915_gem_object_needs_bit17_swizzle(obj))
2240 i915_gem_object_save_bit_17_swizzle(obj, pages);
2242 for_each_sgt_page(page, sgt_iter, pages) {
2244 set_page_dirty(page);
2246 if (obj->mm.madv == I915_MADV_WILLNEED)
2247 mark_page_accessed(page);
2251 obj->mm.dirty = false;
2253 sg_free_table(pages);
2257 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2259 struct radix_tree_iter iter;
2262 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2263 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2266 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2267 enum i915_mm_subclass subclass)
2269 struct sg_table *pages;
2271 if (i915_gem_object_has_pinned_pages(obj))
2274 GEM_BUG_ON(obj->bind_count);
2275 if (!READ_ONCE(obj->mm.pages))
2278 /* May be called by shrinker from within get_pages() (on another bo) */
2279 mutex_lock_nested(&obj->mm.lock, subclass);
2280 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2283 /* ->put_pages might need to allocate memory for the bit17 swizzle
2284 * array, hence protect them from being reaped by removing them from gtt
2286 pages = fetch_and_zero(&obj->mm.pages);
2289 if (obj->mm.mapping) {
2292 ptr = ptr_mask_bits(obj->mm.mapping);
2293 if (is_vmalloc_addr(ptr))
2296 kunmap(kmap_to_page(ptr));
2298 obj->mm.mapping = NULL;
2301 __i915_gem_object_reset_page_iter(obj);
2303 obj->ops->put_pages(obj, pages);
2305 mutex_unlock(&obj->mm.lock);
2308 static unsigned int swiotlb_max_size(void)
2310 #if IS_ENABLED(CONFIG_SWIOTLB)
2311 return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE);
2317 static void i915_sg_trim(struct sg_table *orig_st)
2319 struct sg_table new_st;
2320 struct scatterlist *sg, *new_sg;
2323 if (orig_st->nents == orig_st->orig_nents)
2326 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL))
2329 new_sg = new_st.sgl;
2330 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2331 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2332 /* called before being DMA mapped, no need to copy sg->dma_* */
2333 new_sg = sg_next(new_sg);
2336 sg_free_table(orig_st);
2341 static struct sg_table *
2342 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2344 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2345 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2347 struct address_space *mapping;
2348 struct sg_table *st;
2349 struct scatterlist *sg;
2350 struct sgt_iter sgt_iter;
2352 unsigned long last_pfn = 0; /* suppress gcc warning */
2353 unsigned int max_segment;
2357 /* Assert that the object is not currently in any GPU domain. As it
2358 * wasn't in the GTT, there shouldn't be any way it could have been in
2361 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2362 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2364 max_segment = swiotlb_max_size();
2366 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2368 st = kmalloc(sizeof(*st), GFP_KERNEL);
2370 return ERR_PTR(-ENOMEM);
2373 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2375 return ERR_PTR(-ENOMEM);
2378 /* Get the list of pages out of our struct file. They'll be pinned
2379 * at this point until we release them.
2381 * Fail silently without starting the shrinker
2383 mapping = obj->base.filp->f_mapping;
2384 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2385 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2388 for (i = 0; i < page_count; i++) {
2389 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2391 i915_gem_shrink(dev_priv,
2394 I915_SHRINK_UNBOUND |
2395 I915_SHRINK_PURGEABLE);
2396 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2399 /* We've tried hard to allocate the memory by reaping
2400 * our own buffer, now let the real VM do its job and
2401 * go down in flames if truly OOM.
2403 page = shmem_read_mapping_page(mapping, i);
2405 ret = PTR_ERR(page);
2410 sg->length >= max_segment ||
2411 page_to_pfn(page) != last_pfn + 1) {
2415 sg_set_page(sg, page, PAGE_SIZE, 0);
2417 sg->length += PAGE_SIZE;
2419 last_pfn = page_to_pfn(page);
2421 /* Check that the i965g/gm workaround works. */
2422 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2424 if (sg) /* loop terminated early; short sg table */
2427 /* Trim unused sg entries to avoid wasting memory. */
2430 ret = i915_gem_gtt_prepare_pages(obj, st);
2432 /* DMA remapping failed? One possible cause is that
2433 * it could not reserve enough large entries, asking
2434 * for PAGE_SIZE chunks instead may be helpful.
2436 if (max_segment > PAGE_SIZE) {
2437 for_each_sgt_page(page, sgt_iter, st)
2441 max_segment = PAGE_SIZE;
2444 dev_warn(&dev_priv->drm.pdev->dev,
2445 "Failed to DMA remap %lu pages\n",
2451 if (i915_gem_object_needs_bit17_swizzle(obj))
2452 i915_gem_object_do_bit_17_swizzle(obj, st);
2459 for_each_sgt_page(page, sgt_iter, st)
2464 /* shmemfs first checks if there is enough memory to allocate the page
2465 * and reports ENOSPC should there be insufficient, along with the usual
2466 * ENOMEM for a genuine allocation failure.
2468 * We use ENOSPC in our driver to mean that we have run out of aperture
2469 * space and so want to translate the error from shmemfs back to our
2470 * usual understanding of ENOMEM.
2475 return ERR_PTR(ret);
2478 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2479 struct sg_table *pages)
2481 lockdep_assert_held(&obj->mm.lock);
2483 obj->mm.get_page.sg_pos = pages->sgl;
2484 obj->mm.get_page.sg_idx = 0;
2486 obj->mm.pages = pages;
2488 if (i915_gem_object_is_tiled(obj) &&
2489 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2490 GEM_BUG_ON(obj->mm.quirked);
2491 __i915_gem_object_pin_pages(obj);
2492 obj->mm.quirked = true;
2496 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2498 struct sg_table *pages;
2500 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2502 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2503 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2507 pages = obj->ops->get_pages(obj);
2508 if (unlikely(IS_ERR(pages)))
2509 return PTR_ERR(pages);
2511 __i915_gem_object_set_pages(obj, pages);
2515 /* Ensure that the associated pages are gathered from the backing storage
2516 * and pinned into our object. i915_gem_object_pin_pages() may be called
2517 * multiple times before they are released by a single call to
2518 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2519 * either as a result of memory pressure (reaping pages under the shrinker)
2520 * or as the object is itself released.
2522 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2526 err = mutex_lock_interruptible(&obj->mm.lock);
2530 if (unlikely(!obj->mm.pages)) {
2531 err = ____i915_gem_object_get_pages(obj);
2535 smp_mb__before_atomic();
2537 atomic_inc(&obj->mm.pages_pin_count);
2540 mutex_unlock(&obj->mm.lock);
2544 /* The 'mapping' part of i915_gem_object_pin_map() below */
2545 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2546 enum i915_map_type type)
2548 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2549 struct sg_table *sgt = obj->mm.pages;
2550 struct sgt_iter sgt_iter;
2552 struct page *stack_pages[32];
2553 struct page **pages = stack_pages;
2554 unsigned long i = 0;
2558 /* A single page can always be kmapped */
2559 if (n_pages == 1 && type == I915_MAP_WB)
2560 return kmap(sg_page(sgt->sgl));
2562 if (n_pages > ARRAY_SIZE(stack_pages)) {
2563 /* Too big for stack -- allocate temporary array instead */
2564 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2569 for_each_sgt_page(page, sgt_iter, sgt)
2572 /* Check that we have the expected number of pages */
2573 GEM_BUG_ON(i != n_pages);
2577 pgprot = PAGE_KERNEL;
2580 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2583 addr = vmap(pages, n_pages, 0, pgprot);
2585 if (pages != stack_pages)
2586 drm_free_large(pages);
2591 /* get, pin, and map the pages of the object into kernel space */
2592 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2593 enum i915_map_type type)
2595 enum i915_map_type has_type;
2600 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2602 ret = mutex_lock_interruptible(&obj->mm.lock);
2604 return ERR_PTR(ret);
2607 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2608 if (unlikely(!obj->mm.pages)) {
2609 ret = ____i915_gem_object_get_pages(obj);
2613 smp_mb__before_atomic();
2615 atomic_inc(&obj->mm.pages_pin_count);
2618 GEM_BUG_ON(!obj->mm.pages);
2620 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2621 if (ptr && has_type != type) {
2627 if (is_vmalloc_addr(ptr))
2630 kunmap(kmap_to_page(ptr));
2632 ptr = obj->mm.mapping = NULL;
2636 ptr = i915_gem_object_map(obj, type);
2642 obj->mm.mapping = ptr_pack_bits(ptr, type);
2646 mutex_unlock(&obj->mm.lock);
2650 atomic_dec(&obj->mm.pages_pin_count);
2656 static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2658 unsigned long elapsed;
2660 if (ctx->hang_stats.banned)
2663 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2664 if (ctx->hang_stats.ban_period_seconds &&
2665 elapsed <= ctx->hang_stats.ban_period_seconds) {
2666 DRM_DEBUG("context hanging too fast, banning!\n");
2673 static void i915_set_reset_status(struct i915_gem_context *ctx,
2676 struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2679 hs->banned = i915_context_is_banned(ctx);
2681 hs->guilty_ts = get_seconds();
2683 hs->batch_pending++;
2687 struct drm_i915_gem_request *
2688 i915_gem_find_active_request(struct intel_engine_cs *engine)
2690 struct drm_i915_gem_request *request;
2692 /* We are called by the error capture and reset at a random
2693 * point in time. In particular, note that neither is crucially
2694 * ordered with an interrupt. After a hang, the GPU is dead and we
2695 * assume that no more writes can happen (we waited long enough for
2696 * all writes that were in transaction to be flushed) - adding an
2697 * extra delay for a recent interrupt is pointless. Hence, we do
2698 * not need an engine->irq_seqno_barrier() before the seqno reads.
2700 list_for_each_entry(request, &engine->timeline->requests, link) {
2701 if (__i915_gem_request_completed(request))
2710 static void reset_request(struct drm_i915_gem_request *request)
2712 void *vaddr = request->ring->vaddr;
2715 /* As this request likely depends on state from the lost
2716 * context, clear out all the user operations leaving the
2717 * breadcrumb at the end (so we get the fence notifications).
2719 head = request->head;
2720 if (request->postfix < head) {
2721 memset(vaddr + head, 0, request->ring->size - head);
2724 memset(vaddr + head, 0, request->postfix - head);
2727 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2729 struct drm_i915_gem_request *request;
2730 struct i915_gem_context *incomplete_ctx;
2731 struct intel_timeline *timeline;
2734 if (engine->irq_seqno_barrier)
2735 engine->irq_seqno_barrier(engine);
2737 request = i915_gem_find_active_request(engine);
2741 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2742 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
2745 i915_set_reset_status(request->ctx, ring_hung);
2749 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2750 engine->name, request->global_seqno);
2752 /* Setup the CS to resume from the breadcrumb of the hung request */
2753 engine->reset_hw(engine, request);
2755 /* Users of the default context do not rely on logical state
2756 * preserved between batches. They have to emit full state on
2757 * every batch and so it is safe to execute queued requests following
2760 * Other contexts preserve state, now corrupt. We want to skip all
2761 * queued requests that reference the corrupt context.
2763 incomplete_ctx = request->ctx;
2764 if (i915_gem_context_is_default(incomplete_ctx))
2767 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2768 if (request->ctx == incomplete_ctx)
2769 reset_request(request);
2771 timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2772 list_for_each_entry(request, &timeline->requests, link)
2773 reset_request(request);
2776 void i915_gem_reset(struct drm_i915_private *dev_priv)
2778 struct intel_engine_cs *engine;
2779 enum intel_engine_id id;
2781 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2783 i915_gem_retire_requests(dev_priv);
2785 for_each_engine(engine, dev_priv, id)
2786 i915_gem_reset_engine(engine);
2788 i915_gem_restore_fences(dev_priv);
2790 if (dev_priv->gt.awake) {
2791 intel_sanitize_gt_powersave(dev_priv);
2792 intel_enable_gt_powersave(dev_priv);
2793 if (INTEL_GEN(dev_priv) >= 6)
2794 gen6_rps_busy(dev_priv);
2798 static void nop_submit_request(struct drm_i915_gem_request *request)
2800 i915_gem_request_submit(request);
2801 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2804 static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
2806 engine->submit_request = nop_submit_request;
2808 /* Mark all pending requests as complete so that any concurrent
2809 * (lockless) lookup doesn't try and wait upon the request as we
2812 intel_engine_init_global_seqno(engine,
2813 intel_engine_last_submit(engine));
2816 * Clear the execlists queue up before freeing the requests, as those
2817 * are the ones that keep the context and ringbuffer backing objects
2821 if (i915.enable_execlists) {
2822 unsigned long flags;
2824 spin_lock_irqsave(&engine->timeline->lock, flags);
2826 i915_gem_request_put(engine->execlist_port[0].request);
2827 i915_gem_request_put(engine->execlist_port[1].request);
2828 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2829 engine->execlist_queue = RB_ROOT;
2830 engine->execlist_first = NULL;
2832 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2836 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2838 struct intel_engine_cs *engine;
2839 enum intel_engine_id id;
2841 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2842 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2844 i915_gem_context_lost(dev_priv);
2845 for_each_engine(engine, dev_priv, id)
2846 i915_gem_cleanup_engine(engine);
2847 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2849 i915_gem_retire_requests(dev_priv);
2853 i915_gem_retire_work_handler(struct work_struct *work)
2855 struct drm_i915_private *dev_priv =
2856 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2857 struct drm_device *dev = &dev_priv->drm;
2859 /* Come back later if the device is busy... */
2860 if (mutex_trylock(&dev->struct_mutex)) {
2861 i915_gem_retire_requests(dev_priv);
2862 mutex_unlock(&dev->struct_mutex);
2865 /* Keep the retire handler running until we are finally idle.
2866 * We do not need to do this test under locking as in the worst-case
2867 * we queue the retire worker once too often.
2869 if (READ_ONCE(dev_priv->gt.awake)) {
2870 i915_queue_hangcheck(dev_priv);
2871 queue_delayed_work(dev_priv->wq,
2872 &dev_priv->gt.retire_work,
2873 round_jiffies_up_relative(HZ));
2878 i915_gem_idle_work_handler(struct work_struct *work)
2880 struct drm_i915_private *dev_priv =
2881 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2882 struct drm_device *dev = &dev_priv->drm;
2883 struct intel_engine_cs *engine;
2884 enum intel_engine_id id;
2885 bool rearm_hangcheck;
2887 if (!READ_ONCE(dev_priv->gt.awake))
2891 * Wait for last execlists context complete, but bail out in case a
2892 * new request is submitted.
2894 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2895 intel_execlists_idle(dev_priv), 10);
2897 if (READ_ONCE(dev_priv->gt.active_requests))
2901 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2903 if (!mutex_trylock(&dev->struct_mutex)) {
2904 /* Currently busy, come back later */
2905 mod_delayed_work(dev_priv->wq,
2906 &dev_priv->gt.idle_work,
2907 msecs_to_jiffies(50));
2912 * New request retired after this work handler started, extend active
2913 * period until next instance of the work.
2915 if (work_pending(work))
2918 if (dev_priv->gt.active_requests)
2921 if (wait_for(intel_execlists_idle(dev_priv), 10))
2922 DRM_ERROR("Timeout waiting for engines to idle\n");
2924 for_each_engine(engine, dev_priv, id)
2925 i915_gem_batch_pool_fini(&engine->batch_pool);
2927 GEM_BUG_ON(!dev_priv->gt.awake);
2928 dev_priv->gt.awake = false;
2929 rearm_hangcheck = false;
2931 if (INTEL_GEN(dev_priv) >= 6)
2932 gen6_rps_idle(dev_priv);
2933 intel_runtime_pm_put(dev_priv);
2935 mutex_unlock(&dev->struct_mutex);
2938 if (rearm_hangcheck) {
2939 GEM_BUG_ON(!dev_priv->gt.awake);
2940 i915_queue_hangcheck(dev_priv);
2944 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2946 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2947 struct drm_i915_file_private *fpriv = file->driver_priv;
2948 struct i915_vma *vma, *vn;
2950 mutex_lock(&obj->base.dev->struct_mutex);
2951 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
2952 if (vma->vm->file == fpriv)
2953 i915_vma_close(vma);
2955 if (i915_gem_object_is_active(obj) &&
2956 !i915_gem_object_has_active_reference(obj)) {
2957 i915_gem_object_set_active_reference(obj);
2958 i915_gem_object_get(obj);
2960 mutex_unlock(&obj->base.dev->struct_mutex);
2963 static unsigned long to_wait_timeout(s64 timeout_ns)
2966 return MAX_SCHEDULE_TIMEOUT;
2968 if (timeout_ns == 0)
2971 return nsecs_to_jiffies_timeout(timeout_ns);
2975 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2976 * @dev: drm device pointer
2977 * @data: ioctl data blob
2978 * @file: drm file pointer
2980 * Returns 0 if successful, else an error is returned with the remaining time in
2981 * the timeout parameter.
2982 * -ETIME: object is still busy after timeout
2983 * -ERESTARTSYS: signal interrupted the wait
2984 * -ENONENT: object doesn't exist
2985 * Also possible, but rare:
2986 * -EAGAIN: GPU wedged
2988 * -ENODEV: Internal IRQ fail
2989 * -E?: The add request failed
2991 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2992 * non-zero timeout parameter the wait ioctl will wait for the given number of
2993 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2994 * without holding struct_mutex the object may become re-busied before this
2995 * function completes. A similar but shorter * race condition exists in the busy
2999 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3001 struct drm_i915_gem_wait *args = data;
3002 struct drm_i915_gem_object *obj;
3006 if (args->flags != 0)
3009 obj = i915_gem_object_lookup(file, args->bo_handle);
3013 start = ktime_get();
3015 ret = i915_gem_object_wait(obj,
3016 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3017 to_wait_timeout(args->timeout_ns),
3018 to_rps_client(file));
3020 if (args->timeout_ns > 0) {
3021 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3022 if (args->timeout_ns < 0)
3023 args->timeout_ns = 0;
3026 i915_gem_object_put(obj);
3030 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3034 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3035 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3043 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3047 if (flags & I915_WAIT_LOCKED) {
3048 struct i915_gem_timeline *tl;
3050 lockdep_assert_held(&i915->drm.struct_mutex);
3052 list_for_each_entry(tl, &i915->gt.timelines, link) {
3053 ret = wait_for_timeline(tl, flags);
3058 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3066 void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3069 /* If we don't have a page list set up, then we're not pinned
3070 * to GPU, and we can ignore the cache flush because it'll happen
3071 * again at bind time.
3077 * Stolen memory is always coherent with the GPU as it is explicitly
3078 * marked as wc by the system, or the system is cache-coherent.
3080 if (obj->stolen || obj->phys_handle)
3083 /* If the GPU is snooping the contents of the CPU cache,
3084 * we do not need to manually clear the CPU cache lines. However,
3085 * the caches are only snooped when the render cache is
3086 * flushed/invalidated. As we always have to emit invalidations
3087 * and flushes when moving into and out of the RENDER domain, correct
3088 * snooping behaviour occurs naturally as the result of our domain
3091 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3092 obj->cache_dirty = true;
3096 trace_i915_gem_object_clflush(obj);
3097 drm_clflush_sg(obj->mm.pages);
3098 obj->cache_dirty = false;
3101 /** Flushes the GTT write domain for the object if it's dirty. */
3103 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3105 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3107 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3110 /* No actual flushing is required for the GTT write domain. Writes
3111 * to it "immediately" go to main memory as far as we know, so there's
3112 * no chipset flush. It also doesn't land in render cache.
3114 * However, we do have to enforce the order so that all writes through
3115 * the GTT land before any writes to the device, such as updates to
3118 * We also have to wait a bit for the writes to land from the GTT.
3119 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3120 * timing. This issue has only been observed when switching quickly
3121 * between GTT writes and CPU reads from inside the kernel on recent hw,
3122 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3123 * system agents we cannot reproduce this behaviour).
3126 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3127 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3129 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3131 obj->base.write_domain = 0;
3132 trace_i915_gem_object_change_domain(obj,
3133 obj->base.read_domains,
3134 I915_GEM_DOMAIN_GTT);
3137 /** Flushes the CPU write domain for the object if it's dirty. */
3139 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3141 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3144 i915_gem_clflush_object(obj, obj->pin_display);
3145 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3147 obj->base.write_domain = 0;
3148 trace_i915_gem_object_change_domain(obj,
3149 obj->base.read_domains,
3150 I915_GEM_DOMAIN_CPU);
3154 * Moves a single object to the GTT read, and possibly write domain.
3155 * @obj: object to act on
3156 * @write: ask for write access or read only
3158 * This function returns when the move is complete, including waiting on
3162 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3164 uint32_t old_write_domain, old_read_domains;
3167 lockdep_assert_held(&obj->base.dev->struct_mutex);
3169 ret = i915_gem_object_wait(obj,
3170 I915_WAIT_INTERRUPTIBLE |
3172 (write ? I915_WAIT_ALL : 0),
3173 MAX_SCHEDULE_TIMEOUT,
3178 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3181 /* Flush and acquire obj->pages so that we are coherent through
3182 * direct access in memory with previous cached writes through
3183 * shmemfs and that our cache domain tracking remains valid.
3184 * For example, if the obj->filp was moved to swap without us
3185 * being notified and releasing the pages, we would mistakenly
3186 * continue to assume that the obj remained out of the CPU cached
3189 ret = i915_gem_object_pin_pages(obj);
3193 i915_gem_object_flush_cpu_write_domain(obj);
3195 /* Serialise direct access to this object with the barriers for
3196 * coherent writes from the GPU, by effectively invalidating the
3197 * GTT domain upon first access.
3199 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3202 old_write_domain = obj->base.write_domain;
3203 old_read_domains = obj->base.read_domains;
3205 /* It should now be out of any other write domains, and we can update
3206 * the domain values for our changes.
3208 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3209 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3211 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3212 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3213 obj->mm.dirty = true;
3216 trace_i915_gem_object_change_domain(obj,
3220 i915_gem_object_unpin_pages(obj);
3225 * Changes the cache-level of an object across all VMA.
3226 * @obj: object to act on
3227 * @cache_level: new cache level to set for the object
3229 * After this function returns, the object will be in the new cache-level
3230 * across all GTT and the contents of the backing storage will be coherent,
3231 * with respect to the new cache-level. In order to keep the backing storage
3232 * coherent for all users, we only allow a single cache level to be set
3233 * globally on the object and prevent it from being changed whilst the
3234 * hardware is reading from the object. That is if the object is currently
3235 * on the scanout it will be set to uncached (or equivalent display
3236 * cache coherency) and all non-MOCS GPU access will also be uncached so
3237 * that all direct access to the scanout remains coherent.
3239 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3240 enum i915_cache_level cache_level)
3242 struct i915_vma *vma;
3245 lockdep_assert_held(&obj->base.dev->struct_mutex);
3247 if (obj->cache_level == cache_level)
3250 /* Inspect the list of currently bound VMA and unbind any that would
3251 * be invalid given the new cache-level. This is principally to
3252 * catch the issue of the CS prefetch crossing page boundaries and
3253 * reading an invalid PTE on older architectures.
3256 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3257 if (!drm_mm_node_allocated(&vma->node))
3260 if (i915_vma_is_pinned(vma)) {
3261 DRM_DEBUG("can not change the cache level of pinned objects\n");
3265 if (i915_gem_valid_gtt_space(vma, cache_level))
3268 ret = i915_vma_unbind(vma);
3272 /* As unbinding may affect other elements in the
3273 * obj->vma_list (due to side-effects from retiring
3274 * an active vma), play safe and restart the iterator.
3279 /* We can reuse the existing drm_mm nodes but need to change the
3280 * cache-level on the PTE. We could simply unbind them all and
3281 * rebind with the correct cache-level on next use. However since
3282 * we already have a valid slot, dma mapping, pages etc, we may as
3283 * rewrite the PTE in the belief that doing so tramples upon less
3284 * state and so involves less work.
3286 if (obj->bind_count) {
3287 /* Before we change the PTE, the GPU must not be accessing it.
3288 * If we wait upon the object, we know that all the bound
3289 * VMA are no longer active.
3291 ret = i915_gem_object_wait(obj,
3292 I915_WAIT_INTERRUPTIBLE |
3295 MAX_SCHEDULE_TIMEOUT,
3300 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3301 cache_level != I915_CACHE_NONE) {
3302 /* Access to snoopable pages through the GTT is
3303 * incoherent and on some machines causes a hard
3304 * lockup. Relinquish the CPU mmaping to force
3305 * userspace to refault in the pages and we can
3306 * then double check if the GTT mapping is still
3307 * valid for that pointer access.
3309 i915_gem_release_mmap(obj);
3311 /* As we no longer need a fence for GTT access,
3312 * we can relinquish it now (and so prevent having
3313 * to steal a fence from someone else on the next
3314 * fence request). Note GPU activity would have
3315 * dropped the fence as all snoopable access is
3316 * supposed to be linear.
3318 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3319 ret = i915_vma_put_fence(vma);
3324 /* We either have incoherent backing store and
3325 * so no GTT access or the architecture is fully
3326 * coherent. In such cases, existing GTT mmaps
3327 * ignore the cache bit in the PTE and we can
3328 * rewrite it without confusing the GPU or having
3329 * to force userspace to fault back in its mmaps.
3333 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3334 if (!drm_mm_node_allocated(&vma->node))
3337 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3343 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3344 cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3345 obj->cache_dirty = true;
3347 list_for_each_entry(vma, &obj->vma_list, obj_link)
3348 vma->node.color = cache_level;
3349 obj->cache_level = cache_level;
3354 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3355 struct drm_file *file)
3357 struct drm_i915_gem_caching *args = data;
3358 struct drm_i915_gem_object *obj;
3362 obj = i915_gem_object_lookup_rcu(file, args->handle);
3368 switch (obj->cache_level) {
3369 case I915_CACHE_LLC:
3370 case I915_CACHE_L3_LLC:
3371 args->caching = I915_CACHING_CACHED;
3375 args->caching = I915_CACHING_DISPLAY;
3379 args->caching = I915_CACHING_NONE;
3387 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3388 struct drm_file *file)
3390 struct drm_i915_private *i915 = to_i915(dev);
3391 struct drm_i915_gem_caching *args = data;
3392 struct drm_i915_gem_object *obj;
3393 enum i915_cache_level level;
3396 switch (args->caching) {
3397 case I915_CACHING_NONE:
3398 level = I915_CACHE_NONE;
3400 case I915_CACHING_CACHED:
3402 * Due to a HW issue on BXT A stepping, GPU stores via a
3403 * snooped mapping may leave stale data in a corresponding CPU
3404 * cacheline, whereas normally such cachelines would get
3407 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3410 level = I915_CACHE_LLC;
3412 case I915_CACHING_DISPLAY:
3413 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3419 ret = i915_mutex_lock_interruptible(dev);
3423 obj = i915_gem_object_lookup(file, args->handle);
3429 ret = i915_gem_object_set_cache_level(obj, level);
3430 i915_gem_object_put(obj);
3432 mutex_unlock(&dev->struct_mutex);
3437 * Prepare buffer for display plane (scanout, cursors, etc).
3438 * Can be called from an uninterruptible phase (modesetting) and allows
3439 * any flushes to be pipelined (for pageflips).
3442 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3444 const struct i915_ggtt_view *view)
3446 struct i915_vma *vma;
3447 u32 old_read_domains, old_write_domain;
3450 lockdep_assert_held(&obj->base.dev->struct_mutex);
3452 /* Mark the pin_display early so that we account for the
3453 * display coherency whilst setting up the cache domains.
3457 /* The display engine is not coherent with the LLC cache on gen6. As
3458 * a result, we make sure that the pinning that is about to occur is
3459 * done with uncached PTEs. This is lowest common denominator for all
3462 * However for gen6+, we could do better by using the GFDT bit instead
3463 * of uncaching, which would allow us to flush all the LLC-cached data
3464 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3466 ret = i915_gem_object_set_cache_level(obj,
3467 HAS_WT(to_i915(obj->base.dev)) ?
3468 I915_CACHE_WT : I915_CACHE_NONE);
3471 goto err_unpin_display;
3474 /* As the user may map the buffer once pinned in the display plane
3475 * (e.g. libkms for the bootup splash), we have to ensure that we
3476 * always use map_and_fenceable for all scanout buffers. However,
3477 * it may simply be too big to fit into mappable, in which case
3478 * put it anyway and hope that userspace can cope (but always first
3479 * try to preserve the existing ABI).
3481 vma = ERR_PTR(-ENOSPC);
3482 if (view->type == I915_GGTT_VIEW_NORMAL)
3483 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3484 PIN_MAPPABLE | PIN_NONBLOCK);
3486 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3489 /* Valleyview is definitely limited to scanning out the first
3490 * 512MiB. Lets presume this behaviour was inherited from the
3491 * g4x display engine and that all earlier gen are similarly
3492 * limited. Testing suggests that it is a little more
3493 * complicated than this. For example, Cherryview appears quite
3494 * happy to scanout from anywhere within its global aperture.
3497 if (HAS_GMCH_DISPLAY(i915))
3498 flags = PIN_MAPPABLE;
3499 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3502 goto err_unpin_display;
3504 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3506 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3507 if (obj->cache_dirty) {
3508 i915_gem_clflush_object(obj, true);
3509 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
3512 old_write_domain = obj->base.write_domain;
3513 old_read_domains = obj->base.read_domains;
3515 /* It should now be out of any other write domains, and we can update
3516 * the domain values for our changes.
3518 obj->base.write_domain = 0;
3519 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3521 trace_i915_gem_object_change_domain(obj,
3533 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3535 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3537 if (WARN_ON(vma->obj->pin_display == 0))
3540 if (--vma->obj->pin_display == 0)
3541 vma->display_alignment = 0;
3543 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3544 if (!i915_vma_is_active(vma))
3545 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3547 i915_vma_unpin(vma);
3551 * Moves a single object to the CPU read, and possibly write domain.
3552 * @obj: object to act on
3553 * @write: requesting write or read-only access
3555 * This function returns when the move is complete, including waiting on
3559 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3561 uint32_t old_write_domain, old_read_domains;
3564 lockdep_assert_held(&obj->base.dev->struct_mutex);
3566 ret = i915_gem_object_wait(obj,
3567 I915_WAIT_INTERRUPTIBLE |
3569 (write ? I915_WAIT_ALL : 0),
3570 MAX_SCHEDULE_TIMEOUT,
3575 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3578 i915_gem_object_flush_gtt_write_domain(obj);
3580 old_write_domain = obj->base.write_domain;
3581 old_read_domains = obj->base.read_domains;
3583 /* Flush the CPU cache if it's still invalid. */
3584 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3585 i915_gem_clflush_object(obj, false);
3587 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3590 /* It should now be out of any other write domains, and we can update
3591 * the domain values for our changes.
3593 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3595 /* If we're writing through the CPU, then the GPU read domains will
3596 * need to be invalidated at next use.
3599 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3600 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3603 trace_i915_gem_object_change_domain(obj,
3610 /* Throttle our rendering by waiting until the ring has completed our requests
3611 * emitted over 20 msec ago.
3613 * Note that if we were to use the current jiffies each time around the loop,
3614 * we wouldn't escape the function with any frames outstanding if the time to
3615 * render a frame was over 20ms.
3617 * This should get us reasonable parallelism between CPU and GPU but also
3618 * relatively low latency when blocking on a particular request to finish.
3621 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3623 struct drm_i915_private *dev_priv = to_i915(dev);
3624 struct drm_i915_file_private *file_priv = file->driver_priv;
3625 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3626 struct drm_i915_gem_request *request, *target = NULL;
3629 /* ABI: return -EIO if already wedged */
3630 if (i915_terminally_wedged(&dev_priv->gpu_error))
3633 spin_lock(&file_priv->mm.lock);
3634 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3635 if (time_after_eq(request->emitted_jiffies, recent_enough))
3639 * Note that the request might not have been submitted yet.
3640 * In which case emitted_jiffies will be zero.
3642 if (!request->emitted_jiffies)
3648 i915_gem_request_get(target);
3649 spin_unlock(&file_priv->mm.lock);
3654 ret = i915_wait_request(target,
3655 I915_WAIT_INTERRUPTIBLE,
3656 MAX_SCHEDULE_TIMEOUT);
3657 i915_gem_request_put(target);
3659 return ret < 0 ? ret : 0;
3663 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3664 const struct i915_ggtt_view *view,
3669 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3670 struct i915_address_space *vm = &dev_priv->ggtt.base;
3671 struct i915_vma *vma;
3674 lockdep_assert_held(&obj->base.dev->struct_mutex);
3676 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view);
3680 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3681 if (flags & PIN_NONBLOCK &&
3682 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3683 return ERR_PTR(-ENOSPC);
3685 if (flags & PIN_MAPPABLE) {
3688 fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
3689 i915_gem_object_get_tiling(obj));
3690 /* If the required space is larger than the available
3691 * aperture, we will not able to find a slot for the
3692 * object and unbinding the object now will be in
3693 * vain. Worse, doing so may cause us to ping-pong
3694 * the object in and out of the Global GTT and
3695 * waste a lot of cycles under the mutex.
3697 if (fence_size > dev_priv->ggtt.mappable_end)
3698 return ERR_PTR(-E2BIG);
3700 /* If NONBLOCK is set the caller is optimistically
3701 * trying to cache the full object within the mappable
3702 * aperture, and *must* have a fallback in place for
3703 * situations where we cannot bind the object. We
3704 * can be a little more lax here and use the fallback
3705 * more often to avoid costly migrations of ourselves
3706 * and other objects within the aperture.
3708 * Half-the-aperture is used as a simple heuristic.
3709 * More interesting would to do search for a free
3710 * block prior to making the commitment to unbind.
3711 * That caters for the self-harm case, and with a
3712 * little more heuristics (e.g. NOFAULT, NOEVICT)
3713 * we could try to minimise harm to others.
3715 if (flags & PIN_NONBLOCK &&
3716 fence_size > dev_priv->ggtt.mappable_end / 2)
3717 return ERR_PTR(-ENOSPC);
3720 WARN(i915_vma_is_pinned(vma),
3721 "bo is already pinned in ggtt with incorrect alignment:"
3722 " offset=%08x, req.alignment=%llx,"
3723 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3724 i915_ggtt_offset(vma), alignment,
3725 !!(flags & PIN_MAPPABLE),
3726 i915_vma_is_map_and_fenceable(vma));
3727 ret = i915_vma_unbind(vma);
3729 return ERR_PTR(ret);
3732 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3734 return ERR_PTR(ret);
3739 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3741 /* Note that we could alias engines in the execbuf API, but
3742 * that would be very unwise as it prevents userspace from
3743 * fine control over engine selection. Ahem.
3745 * This should be something like EXEC_MAX_ENGINE instead of
3748 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3749 return 0x10000 << id;
3752 static __always_inline unsigned int __busy_write_id(unsigned int id)
3754 /* The uABI guarantees an active writer is also amongst the read
3755 * engines. This would be true if we accessed the activity tracking
3756 * under the lock, but as we perform the lookup of the object and
3757 * its activity locklessly we can not guarantee that the last_write
3758 * being active implies that we have set the same engine flag from
3759 * last_read - hence we always set both read and write busy for
3762 return id | __busy_read_flag(id);
3765 static __always_inline unsigned int
3766 __busy_set_if_active(const struct dma_fence *fence,
3767 unsigned int (*flag)(unsigned int id))
3769 struct drm_i915_gem_request *rq;
3771 /* We have to check the current hw status of the fence as the uABI
3772 * guarantees forward progress. We could rely on the idle worker
3773 * to eventually flush us, but to minimise latency just ask the
3776 * Note we only report on the status of native fences.
3778 if (!dma_fence_is_i915(fence))
3781 /* opencode to_request() in order to avoid const warnings */
3782 rq = container_of(fence, struct drm_i915_gem_request, fence);
3783 if (i915_gem_request_completed(rq))
3786 return flag(rq->engine->exec_id);
3789 static __always_inline unsigned int
3790 busy_check_reader(const struct dma_fence *fence)
3792 return __busy_set_if_active(fence, __busy_read_flag);
3795 static __always_inline unsigned int
3796 busy_check_writer(const struct dma_fence *fence)
3801 return __busy_set_if_active(fence, __busy_write_id);
3805 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3806 struct drm_file *file)
3808 struct drm_i915_gem_busy *args = data;
3809 struct drm_i915_gem_object *obj;
3810 struct reservation_object_list *list;
3816 obj = i915_gem_object_lookup_rcu(file, args->handle);
3820 /* A discrepancy here is that we do not report the status of
3821 * non-i915 fences, i.e. even though we may report the object as idle,
3822 * a call to set-domain may still stall waiting for foreign rendering.
3823 * This also means that wait-ioctl may report an object as busy,
3824 * where busy-ioctl considers it idle.
3826 * We trade the ability to warn of foreign fences to report on which
3827 * i915 engines are active for the object.
3829 * Alternatively, we can trade that extra information on read/write
3832 * !reservation_object_test_signaled_rcu(obj->resv, true);
3833 * to report the overall busyness. This is what the wait-ioctl does.
3837 seq = raw_read_seqcount(&obj->resv->seq);
3839 /* Translate the exclusive fence to the READ *and* WRITE engine */
3840 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3842 /* Translate shared fences to READ set of engines */
3843 list = rcu_dereference(obj->resv->fence);
3845 unsigned int shared_count = list->shared_count, i;
3847 for (i = 0; i < shared_count; ++i) {
3848 struct dma_fence *fence =
3849 rcu_dereference(list->shared[i]);
3851 args->busy |= busy_check_reader(fence);
3855 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3865 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3866 struct drm_file *file_priv)
3868 return i915_gem_ring_throttle(dev, file_priv);
3872 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3873 struct drm_file *file_priv)
3875 struct drm_i915_private *dev_priv = to_i915(dev);
3876 struct drm_i915_gem_madvise *args = data;
3877 struct drm_i915_gem_object *obj;
3880 switch (args->madv) {
3881 case I915_MADV_DONTNEED:
3882 case I915_MADV_WILLNEED:
3888 obj = i915_gem_object_lookup(file_priv, args->handle);
3892 err = mutex_lock_interruptible(&obj->mm.lock);
3896 if (obj->mm.pages &&
3897 i915_gem_object_is_tiled(obj) &&
3898 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3899 if (obj->mm.madv == I915_MADV_WILLNEED) {
3900 GEM_BUG_ON(!obj->mm.quirked);
3901 __i915_gem_object_unpin_pages(obj);
3902 obj->mm.quirked = false;
3904 if (args->madv == I915_MADV_WILLNEED) {
3905 GEM_BUG_ON(obj->mm.quirked);
3906 __i915_gem_object_pin_pages(obj);
3907 obj->mm.quirked = true;
3911 if (obj->mm.madv != __I915_MADV_PURGED)
3912 obj->mm.madv = args->madv;
3914 /* if the object is no longer attached, discard its backing storage */
3915 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3916 i915_gem_object_truncate(obj);
3918 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3919 mutex_unlock(&obj->mm.lock);
3922 i915_gem_object_put(obj);
3927 frontbuffer_retire(struct i915_gem_active *active,
3928 struct drm_i915_gem_request *request)
3930 struct drm_i915_gem_object *obj =
3931 container_of(active, typeof(*obj), frontbuffer_write);
3933 intel_fb_obj_flush(obj, true, ORIGIN_CS);
3936 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3937 const struct drm_i915_gem_object_ops *ops)
3939 mutex_init(&obj->mm.lock);
3941 INIT_LIST_HEAD(&obj->global_link);
3942 INIT_LIST_HEAD(&obj->userfault_link);
3943 INIT_LIST_HEAD(&obj->obj_exec_link);
3944 INIT_LIST_HEAD(&obj->vma_list);
3945 INIT_LIST_HEAD(&obj->batch_pool_link);
3949 reservation_object_init(&obj->__builtin_resv);
3950 obj->resv = &obj->__builtin_resv;
3952 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
3953 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
3955 obj->mm.madv = I915_MADV_WILLNEED;
3956 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
3957 mutex_init(&obj->mm.get_page.lock);
3959 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3962 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3963 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
3964 I915_GEM_OBJECT_IS_SHRINKABLE,
3965 .get_pages = i915_gem_object_get_pages_gtt,
3966 .put_pages = i915_gem_object_put_pages_gtt,
3969 /* Note we don't consider signbits :| */
3970 #define overflows_type(x, T) \
3971 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3973 struct drm_i915_gem_object *
3974 i915_gem_object_create(struct drm_device *dev, u64 size)
3976 struct drm_i915_private *dev_priv = to_i915(dev);
3977 struct drm_i915_gem_object *obj;
3978 struct address_space *mapping;
3982 /* There is a prevalence of the assumption that we fit the object's
3983 * page count inside a 32bit _signed_ variable. Let's document this and
3984 * catch if we ever need to fix it. In the meantime, if you do spot
3985 * such a local variable, please consider fixing!
3987 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
3988 return ERR_PTR(-E2BIG);
3990 if (overflows_type(size, obj->base.size))
3991 return ERR_PTR(-E2BIG);
3993 obj = i915_gem_object_alloc(dev);
3995 return ERR_PTR(-ENOMEM);
3997 ret = drm_gem_object_init(dev, &obj->base, size);
4001 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4002 if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
4003 /* 965gm cannot relocate objects above 4GiB. */
4004 mask &= ~__GFP_HIGHMEM;
4005 mask |= __GFP_DMA32;
4008 mapping = obj->base.filp->f_mapping;
4009 mapping_set_gfp_mask(mapping, mask);
4011 i915_gem_object_init(obj, &i915_gem_object_ops);
4013 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4014 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4016 if (HAS_LLC(dev_priv)) {
4017 /* On some devices, we can have the GPU use the LLC (the CPU
4018 * cache) for about a 10% performance improvement
4019 * compared to uncached. Graphics requests other than
4020 * display scanout are coherent with the CPU in
4021 * accessing this cache. This means in this mode we
4022 * don't need to clflush on the CPU side, and on the
4023 * GPU side we only need to flush internal caches to
4024 * get data visible to the CPU.
4026 * However, we maintain the display planes as UC, and so
4027 * need to rebind when first used as such.
4029 obj->cache_level = I915_CACHE_LLC;
4031 obj->cache_level = I915_CACHE_NONE;
4033 trace_i915_gem_object_create(obj);
4038 i915_gem_object_free(obj);
4039 return ERR_PTR(ret);
4042 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4044 /* If we are the last user of the backing storage (be it shmemfs
4045 * pages or stolen etc), we know that the pages are going to be
4046 * immediately released. In this case, we can then skip copying
4047 * back the contents from the GPU.
4050 if (obj->mm.madv != I915_MADV_WILLNEED)
4053 if (obj->base.filp == NULL)
4056 /* At first glance, this looks racy, but then again so would be
4057 * userspace racing mmap against close. However, the first external
4058 * reference to the filp can only be obtained through the
4059 * i915_gem_mmap_ioctl() which safeguards us against the user
4060 * acquiring such a reference whilst we are in the middle of
4061 * freeing the object.
4063 return atomic_long_read(&obj->base.filp->f_count) == 1;
4066 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4067 struct llist_node *freed)
4069 struct drm_i915_gem_object *obj, *on;
4071 mutex_lock(&i915->drm.struct_mutex);
4072 intel_runtime_pm_get(i915);
4073 llist_for_each_entry(obj, freed, freed) {
4074 struct i915_vma *vma, *vn;
4076 trace_i915_gem_object_destroy(obj);
4078 GEM_BUG_ON(i915_gem_object_is_active(obj));
4079 list_for_each_entry_safe(vma, vn,
4080 &obj->vma_list, obj_link) {
4081 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4082 GEM_BUG_ON(i915_vma_is_active(vma));
4083 vma->flags &= ~I915_VMA_PIN_MASK;
4084 i915_vma_close(vma);
4086 GEM_BUG_ON(!list_empty(&obj->vma_list));
4087 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4089 list_del(&obj->global_link);
4091 intel_runtime_pm_put(i915);
4092 mutex_unlock(&i915->drm.struct_mutex);
4094 llist_for_each_entry_safe(obj, on, freed, freed) {
4095 GEM_BUG_ON(obj->bind_count);
4096 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4098 if (obj->ops->release)
4099 obj->ops->release(obj);
4101 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4102 atomic_set(&obj->mm.pages_pin_count, 0);
4103 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4104 GEM_BUG_ON(obj->mm.pages);
4106 if (obj->base.import_attach)
4107 drm_prime_gem_destroy(&obj->base, NULL);
4109 reservation_object_fini(&obj->__builtin_resv);
4110 drm_gem_object_release(&obj->base);
4111 i915_gem_info_remove_obj(i915, obj->base.size);
4114 i915_gem_object_free(obj);
4118 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4120 struct llist_node *freed;
4122 freed = llist_del_all(&i915->mm.free_list);
4123 if (unlikely(freed))
4124 __i915_gem_free_objects(i915, freed);
4127 static void __i915_gem_free_work(struct work_struct *work)
4129 struct drm_i915_private *i915 =
4130 container_of(work, struct drm_i915_private, mm.free_work);
4131 struct llist_node *freed;
4133 /* All file-owned VMA should have been released by this point through
4134 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4135 * However, the object may also be bound into the global GTT (e.g.
4136 * older GPUs without per-process support, or for direct access through
4137 * the GTT either for the user or for scanout). Those VMA still need to
4141 while ((freed = llist_del_all(&i915->mm.free_list)))
4142 __i915_gem_free_objects(i915, freed);
4145 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4147 struct drm_i915_gem_object *obj =
4148 container_of(head, typeof(*obj), rcu);
4149 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4151 /* We can't simply use call_rcu() from i915_gem_free_object()
4152 * as we need to block whilst unbinding, and the call_rcu
4153 * task may be called from softirq context. So we take a
4154 * detour through a worker.
4156 if (llist_add(&obj->freed, &i915->mm.free_list))
4157 schedule_work(&i915->mm.free_work);
4160 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4162 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4164 if (obj->mm.quirked)
4165 __i915_gem_object_unpin_pages(obj);
4167 if (discard_backing_storage(obj))
4168 obj->mm.madv = I915_MADV_DONTNEED;
4170 /* Before we free the object, make sure any pure RCU-only
4171 * read-side critical sections are complete, e.g.
4172 * i915_gem_busy_ioctl(). For the corresponding synchronized
4173 * lookup see i915_gem_object_lookup_rcu().
4175 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4178 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4180 lockdep_assert_held(&obj->base.dev->struct_mutex);
4182 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4183 if (i915_gem_object_is_active(obj))
4184 i915_gem_object_set_active_reference(obj);
4186 i915_gem_object_put(obj);
4189 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4191 struct intel_engine_cs *engine;
4192 enum intel_engine_id id;
4194 for_each_engine(engine, dev_priv, id)
4195 GEM_BUG_ON(engine->last_context != dev_priv->kernel_context);
4198 int i915_gem_suspend(struct drm_device *dev)
4200 struct drm_i915_private *dev_priv = to_i915(dev);
4203 intel_suspend_gt_powersave(dev_priv);
4205 mutex_lock(&dev->struct_mutex);
4207 /* We have to flush all the executing contexts to main memory so
4208 * that they can saved in the hibernation image. To ensure the last
4209 * context image is coherent, we have to switch away from it. That
4210 * leaves the dev_priv->kernel_context still active when
4211 * we actually suspend, and its image in memory may not match the GPU
4212 * state. Fortunately, the kernel_context is disposable and we do
4213 * not rely on its state.
4215 ret = i915_gem_switch_to_kernel_context(dev_priv);
4219 ret = i915_gem_wait_for_idle(dev_priv,
4220 I915_WAIT_INTERRUPTIBLE |
4225 i915_gem_retire_requests(dev_priv);
4226 GEM_BUG_ON(dev_priv->gt.active_requests);
4228 assert_kernel_context_is_current(dev_priv);
4229 i915_gem_context_lost(dev_priv);
4230 mutex_unlock(&dev->struct_mutex);
4232 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4233 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4234 flush_delayed_work(&dev_priv->gt.idle_work);
4235 flush_work(&dev_priv->mm.free_work);
4237 /* Assert that we sucessfully flushed all the work and
4238 * reset the GPU back to its idle, low power state.
4240 WARN_ON(dev_priv->gt.awake);
4241 WARN_ON(!intel_execlists_idle(dev_priv));
4244 * Neither the BIOS, ourselves or any other kernel
4245 * expects the system to be in execlists mode on startup,
4246 * so we need to reset the GPU back to legacy mode. And the only
4247 * known way to disable logical contexts is through a GPU reset.
4249 * So in order to leave the system in a known default configuration,
4250 * always reset the GPU upon unload and suspend. Afterwards we then
4251 * clean up the GEM state tracking, flushing off the requests and
4252 * leaving the system in a known idle state.
4254 * Note that is of the upmost importance that the GPU is idle and
4255 * all stray writes are flushed *before* we dismantle the backing
4256 * storage for the pinned objects.
4258 * However, since we are uncertain that resetting the GPU on older
4259 * machines is a good idea, we don't - just in case it leaves the
4260 * machine in an unusable condition.
4262 if (HAS_HW_CONTEXTS(dev_priv)) {
4263 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
4264 WARN_ON(reset && reset != -ENODEV);
4270 mutex_unlock(&dev->struct_mutex);
4274 void i915_gem_resume(struct drm_device *dev)
4276 struct drm_i915_private *dev_priv = to_i915(dev);
4278 WARN_ON(dev_priv->gt.awake);
4280 mutex_lock(&dev->struct_mutex);
4281 i915_gem_restore_gtt_mappings(dev_priv);
4283 /* As we didn't flush the kernel context before suspend, we cannot
4284 * guarantee that the context image is complete. So let's just reset
4285 * it and start again.
4287 dev_priv->gt.resume(dev_priv);
4289 mutex_unlock(&dev->struct_mutex);
4292 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4294 if (INTEL_GEN(dev_priv) < 5 ||
4295 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4298 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4299 DISP_TILE_SURFACE_SWIZZLING);
4301 if (IS_GEN5(dev_priv))
4304 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4305 if (IS_GEN6(dev_priv))
4306 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4307 else if (IS_GEN7(dev_priv))
4308 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4309 else if (IS_GEN8(dev_priv))
4310 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4315 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4317 I915_WRITE(RING_CTL(base), 0);
4318 I915_WRITE(RING_HEAD(base), 0);
4319 I915_WRITE(RING_TAIL(base), 0);
4320 I915_WRITE(RING_START(base), 0);
4323 static void init_unused_rings(struct drm_i915_private *dev_priv)
4325 if (IS_I830(dev_priv)) {
4326 init_unused_ring(dev_priv, PRB1_BASE);
4327 init_unused_ring(dev_priv, SRB0_BASE);
4328 init_unused_ring(dev_priv, SRB1_BASE);
4329 init_unused_ring(dev_priv, SRB2_BASE);
4330 init_unused_ring(dev_priv, SRB3_BASE);
4331 } else if (IS_GEN2(dev_priv)) {
4332 init_unused_ring(dev_priv, SRB0_BASE);
4333 init_unused_ring(dev_priv, SRB1_BASE);
4334 } else if (IS_GEN3(dev_priv)) {
4335 init_unused_ring(dev_priv, PRB1_BASE);
4336 init_unused_ring(dev_priv, PRB2_BASE);
4341 i915_gem_init_hw(struct drm_device *dev)
4343 struct drm_i915_private *dev_priv = to_i915(dev);
4344 struct intel_engine_cs *engine;
4345 enum intel_engine_id id;
4348 dev_priv->gt.last_init_time = ktime_get();
4350 /* Double layer security blanket, see i915_gem_init() */
4351 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4353 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4354 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4356 if (IS_HASWELL(dev_priv))
4357 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4358 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4360 if (HAS_PCH_NOP(dev_priv)) {
4361 if (IS_IVYBRIDGE(dev_priv)) {
4362 u32 temp = I915_READ(GEN7_MSG_CTL);
4363 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4364 I915_WRITE(GEN7_MSG_CTL, temp);
4365 } else if (INTEL_GEN(dev_priv) >= 7) {
4366 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4367 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4368 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4372 i915_gem_init_swizzling(dev_priv);
4375 * At least 830 can leave some of the unused rings
4376 * "active" (ie. head != tail) after resume which
4377 * will prevent c3 entry. Makes sure all unused rings
4380 init_unused_rings(dev_priv);
4382 BUG_ON(!dev_priv->kernel_context);
4384 ret = i915_ppgtt_init_hw(dev_priv);
4386 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4390 /* Need to do basic initialisation of all rings first: */
4391 for_each_engine(engine, dev_priv, id) {
4392 ret = engine->init_hw(engine);
4397 intel_mocs_init_l3cc_table(dev);
4399 /* We can't enable contexts until all firmware is loaded */
4400 ret = intel_guc_setup(dev);
4405 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4409 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4411 if (INTEL_INFO(dev_priv)->gen < 6)
4414 /* TODO: make semaphores and Execlists play nicely together */
4415 if (i915.enable_execlists)
4421 #ifdef CONFIG_INTEL_IOMMU
4422 /* Enable semaphores on SNB when IO remapping is off */
4423 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4430 int i915_gem_init(struct drm_device *dev)
4432 struct drm_i915_private *dev_priv = to_i915(dev);
4435 mutex_lock(&dev->struct_mutex);
4437 if (!i915.enable_execlists) {
4438 dev_priv->gt.resume = intel_legacy_submission_resume;
4439 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4441 dev_priv->gt.resume = intel_lr_context_resume;
4442 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4445 /* This is just a security blanket to placate dragons.
4446 * On some systems, we very sporadically observe that the first TLBs
4447 * used by the CS may be stale, despite us poking the TLB reset. If
4448 * we hold the forcewake during initialisation these problems
4449 * just magically go away.
4451 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4453 i915_gem_init_userptr(dev_priv);
4455 ret = i915_gem_init_ggtt(dev_priv);
4459 ret = i915_gem_context_init(dev);
4463 ret = intel_engines_init(dev);
4467 ret = i915_gem_init_hw(dev);
4469 /* Allow engine initialisation to fail by marking the GPU as
4470 * wedged. But we only want to do this where the GPU is angry,
4471 * for all other failure, such as an allocation failure, bail.
4473 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4474 i915_gem_set_wedged(dev_priv);
4479 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4480 mutex_unlock(&dev->struct_mutex);
4486 i915_gem_cleanup_engines(struct drm_device *dev)
4488 struct drm_i915_private *dev_priv = to_i915(dev);
4489 struct intel_engine_cs *engine;
4490 enum intel_engine_id id;
4492 for_each_engine(engine, dev_priv, id)
4493 dev_priv->gt.cleanup_engine(engine);
4497 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4501 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4502 !IS_CHERRYVIEW(dev_priv))
4503 dev_priv->num_fence_regs = 32;
4504 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4505 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4506 dev_priv->num_fence_regs = 16;
4508 dev_priv->num_fence_regs = 8;
4510 if (intel_vgpu_active(dev_priv))
4511 dev_priv->num_fence_regs =
4512 I915_READ(vgtif_reg(avail_rs.fence_num));
4514 /* Initialize fence registers to zero */
4515 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4516 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4518 fence->i915 = dev_priv;
4520 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4522 i915_gem_restore_fences(dev_priv);
4524 i915_gem_detect_bit_6_swizzle(dev_priv);
4528 i915_gem_load_init(struct drm_device *dev)
4530 struct drm_i915_private *dev_priv = to_i915(dev);
4533 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4534 if (!dev_priv->objects)
4537 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4538 if (!dev_priv->vmas)
4541 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4542 SLAB_HWCACHE_ALIGN |
4543 SLAB_RECLAIM_ACCOUNT |
4544 SLAB_DESTROY_BY_RCU);
4545 if (!dev_priv->requests)
4548 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4549 SLAB_HWCACHE_ALIGN |
4550 SLAB_RECLAIM_ACCOUNT);
4551 if (!dev_priv->dependencies)
4554 mutex_lock(&dev_priv->drm.struct_mutex);
4555 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4556 err = i915_gem_timeline_init__global(dev_priv);
4557 mutex_unlock(&dev_priv->drm.struct_mutex);
4559 goto err_dependencies;
4561 INIT_LIST_HEAD(&dev_priv->context_list);
4562 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4563 init_llist_head(&dev_priv->mm.free_list);
4564 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4565 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4566 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4567 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4568 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4569 i915_gem_retire_work_handler);
4570 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4571 i915_gem_idle_work_handler);
4572 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4573 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4575 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4577 init_waitqueue_head(&dev_priv->pending_flip_queue);
4579 dev_priv->mm.interruptible = true;
4581 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4583 spin_lock_init(&dev_priv->fb_tracking.lock);
4588 kmem_cache_destroy(dev_priv->dependencies);
4590 kmem_cache_destroy(dev_priv->requests);
4592 kmem_cache_destroy(dev_priv->vmas);
4594 kmem_cache_destroy(dev_priv->objects);
4599 void i915_gem_load_cleanup(struct drm_device *dev)
4601 struct drm_i915_private *dev_priv = to_i915(dev);
4603 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4605 mutex_lock(&dev_priv->drm.struct_mutex);
4606 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4607 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4608 mutex_unlock(&dev_priv->drm.struct_mutex);
4610 kmem_cache_destroy(dev_priv->dependencies);
4611 kmem_cache_destroy(dev_priv->requests);
4612 kmem_cache_destroy(dev_priv->vmas);
4613 kmem_cache_destroy(dev_priv->objects);
4615 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4619 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4621 intel_runtime_pm_get(dev_priv);
4623 mutex_lock(&dev_priv->drm.struct_mutex);
4624 i915_gem_shrink_all(dev_priv);
4625 mutex_unlock(&dev_priv->drm.struct_mutex);
4627 intel_runtime_pm_put(dev_priv);
4632 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4634 struct drm_i915_gem_object *obj;
4635 struct list_head *phases[] = {
4636 &dev_priv->mm.unbound_list,
4637 &dev_priv->mm.bound_list,
4641 /* Called just before we write the hibernation image.
4643 * We need to update the domain tracking to reflect that the CPU
4644 * will be accessing all the pages to create and restore from the
4645 * hibernation, and so upon restoration those pages will be in the
4648 * To make sure the hibernation image contains the latest state,
4649 * we update that state just before writing out the image.
4651 * To try and reduce the hibernation image, we manually shrink
4652 * the objects as well.
4655 mutex_lock(&dev_priv->drm.struct_mutex);
4656 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4658 for (p = phases; *p; p++) {
4659 list_for_each_entry(obj, *p, global_link) {
4660 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4661 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4664 mutex_unlock(&dev_priv->drm.struct_mutex);
4669 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4671 struct drm_i915_file_private *file_priv = file->driver_priv;
4672 struct drm_i915_gem_request *request;
4674 /* Clean up our request list when the client is going away, so that
4675 * later retire_requests won't dereference our soon-to-be-gone
4678 spin_lock(&file_priv->mm.lock);
4679 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4680 request->file_priv = NULL;
4681 spin_unlock(&file_priv->mm.lock);
4683 if (!list_empty(&file_priv->rps.link)) {
4684 spin_lock(&to_i915(dev)->rps.client_lock);
4685 list_del(&file_priv->rps.link);
4686 spin_unlock(&to_i915(dev)->rps.client_lock);
4690 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4692 struct drm_i915_file_private *file_priv;
4697 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4701 file->driver_priv = file_priv;
4702 file_priv->dev_priv = to_i915(dev);
4703 file_priv->file = file;
4704 INIT_LIST_HEAD(&file_priv->rps.link);
4706 spin_lock_init(&file_priv->mm.lock);
4707 INIT_LIST_HEAD(&file_priv->mm.request_list);
4709 file_priv->bsd_engine = -1;
4711 ret = i915_gem_context_open(dev, file);
4719 * i915_gem_track_fb - update frontbuffer tracking
4720 * @old: current GEM buffer for the frontbuffer slots
4721 * @new: new GEM buffer for the frontbuffer slots
4722 * @frontbuffer_bits: bitmask of frontbuffer slots
4724 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4725 * from @old and setting them in @new. Both @old and @new can be NULL.
4727 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4728 struct drm_i915_gem_object *new,
4729 unsigned frontbuffer_bits)
4731 /* Control of individual bits within the mask are guarded by
4732 * the owning plane->mutex, i.e. we can never see concurrent
4733 * manipulation of individual bits. But since the bitfield as a whole
4734 * is updated using RMW, we need to use atomics in order to update
4737 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4738 sizeof(atomic_t) * BITS_PER_BYTE);
4741 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4742 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4746 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4747 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4751 /* Allocate a new GEM object and fill it with the supplied data */
4752 struct drm_i915_gem_object *
4753 i915_gem_object_create_from_data(struct drm_device *dev,
4754 const void *data, size_t size)
4756 struct drm_i915_gem_object *obj;
4757 struct sg_table *sg;
4761 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4765 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4769 ret = i915_gem_object_pin_pages(obj);
4774 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4775 obj->mm.dirty = true; /* Backing store is now out of date */
4776 i915_gem_object_unpin_pages(obj);
4778 if (WARN_ON(bytes != size)) {
4779 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4787 i915_gem_object_put(obj);
4788 return ERR_PTR(ret);
4791 struct scatterlist *
4792 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4794 unsigned int *offset)
4796 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4797 struct scatterlist *sg;
4798 unsigned int idx, count;
4801 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4802 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4804 /* As we iterate forward through the sg, we record each entry in a
4805 * radixtree for quick repeated (backwards) lookups. If we have seen
4806 * this index previously, we will have an entry for it.
4808 * Initial lookup is O(N), but this is amortized to O(1) for
4809 * sequential page access (where each new request is consecutive
4810 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4811 * i.e. O(1) with a large constant!
4813 if (n < READ_ONCE(iter->sg_idx))
4816 mutex_lock(&iter->lock);
4818 /* We prefer to reuse the last sg so that repeated lookup of this
4819 * (or the subsequent) sg are fast - comparing against the last
4820 * sg is faster than going through the radixtree.
4825 count = __sg_page_count(sg);
4827 while (idx + count <= n) {
4828 unsigned long exception, i;
4831 /* If we cannot allocate and insert this entry, or the
4832 * individual pages from this range, cancel updating the
4833 * sg_idx so that on this lookup we are forced to linearly
4834 * scan onwards, but on future lookups we will try the
4835 * insertion again (in which case we need to be careful of
4836 * the error return reporting that we have already inserted
4839 ret = radix_tree_insert(&iter->radix, idx, sg);
4840 if (ret && ret != -EEXIST)
4844 RADIX_TREE_EXCEPTIONAL_ENTRY |
4845 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4846 for (i = 1; i < count; i++) {
4847 ret = radix_tree_insert(&iter->radix, idx + i,
4849 if (ret && ret != -EEXIST)
4854 sg = ____sg_next(sg);
4855 count = __sg_page_count(sg);
4862 mutex_unlock(&iter->lock);
4864 if (unlikely(n < idx)) /* insertion completed by another thread */
4867 /* In case we failed to insert the entry into the radixtree, we need
4868 * to look beyond the current sg.
4870 while (idx + count <= n) {
4872 sg = ____sg_next(sg);
4873 count = __sg_page_count(sg);
4882 sg = radix_tree_lookup(&iter->radix, n);
4885 /* If this index is in the middle of multi-page sg entry,
4886 * the radixtree will contain an exceptional entry that points
4887 * to the start of that range. We will return the pointer to
4888 * the base page and the offset of this page within the
4892 if (unlikely(radix_tree_exception(sg))) {
4893 unsigned long base =
4894 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4896 sg = radix_tree_lookup(&iter->radix, base);
4908 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4910 struct scatterlist *sg;
4911 unsigned int offset;
4913 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4915 sg = i915_gem_object_get_sg(obj, n, &offset);
4916 return nth_page(sg_page(sg), offset);
4919 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4921 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
4926 page = i915_gem_object_get_page(obj, n);
4928 set_page_dirty(page);
4934 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
4937 struct scatterlist *sg;
4938 unsigned int offset;
4940 sg = i915_gem_object_get_sg(obj, n, &offset);
4941 return sg_dma_address(sg) + (offset << PAGE_SHIFT);