2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
47 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
49 bool map_and_fenceable);
50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
51 struct drm_i915_fence_reg *reg);
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
67 dev_priv->mm.object_count++;
68 dev_priv->mm.object_memory += size;
71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
74 dev_priv->mm.object_count--;
75 dev_priv->mm.object_memory -= size;
79 i915_gem_check_is_wedged(struct drm_device *dev)
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 struct completion *x = &dev_priv->error_completion;
86 if (!atomic_read(&dev_priv->mm.wedged))
89 ret = wait_for_completion_interruptible(x);
93 /* Success, we reset the GPU! */
94 if (!atomic_read(&dev_priv->mm.wedged))
97 /* GPU is hung, bump the completion count to account for
98 * the token we just consumed so that we never hit zero and
99 * end up waiting upon a subsequent completion event that
102 spin_lock_irqsave(&x->wait.lock, flags);
104 spin_unlock_irqrestore(&x->wait.lock, flags);
108 int i915_mutex_lock_interruptible(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
113 ret = i915_gem_check_is_wedged(dev);
117 ret = mutex_lock_interruptible(&dev->struct_mutex);
121 if (atomic_read(&dev_priv->mm.wedged)) {
122 mutex_unlock(&dev->struct_mutex);
126 WARN_ON(i915_verify_lists(dev));
131 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
133 return obj->gtt_space && !obj->active && obj->pin_count == 0;
136 void i915_gem_do_init(struct drm_device *dev,
138 unsigned long mappable_end,
141 drm_i915_private_t *dev_priv = dev->dev_private;
143 drm_mm_init(&dev_priv->mm.gtt_space, start,
146 dev_priv->mm.gtt_total = end - start;
147 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
148 dev_priv->mm.gtt_mappable_end = mappable_end;
152 i915_gem_init_ioctl(struct drm_device *dev, void *data,
153 struct drm_file *file)
155 struct drm_i915_gem_init *args = data;
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 mutex_lock(&dev->struct_mutex);
162 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
177 if (!(dev->driver->driver_features & DRIVER_GEM))
181 mutex_lock(&dev->struct_mutex);
182 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
183 pinned += obj->gtt_space->size;
184 mutex_unlock(&dev->struct_mutex);
186 args->aper_size = dev_priv->mm.gtt_total;
187 args->aper_available_size = args->aper_size -pinned;
193 * Creates a new mm object and returns a handle to it.
196 i915_gem_create_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_gem_create *args = data;
200 struct drm_i915_gem_object *obj;
204 args->size = roundup(args->size, PAGE_SIZE);
206 /* Allocate the new object */
207 obj = i915_gem_alloc_object(dev, args->size);
211 ret = drm_gem_handle_create(file, &obj->base, &handle);
213 drm_gem_object_release(&obj->base);
214 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
219 /* drop reference from allocate - handle holds it now */
220 drm_gem_object_unreference(&obj->base);
221 trace_i915_gem_object_create(obj);
223 args->handle = handle;
227 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
229 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
231 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
232 obj->tiling_mode != I915_TILING_NONE;
236 slow_shmem_copy(struct page *dst_page,
238 struct page *src_page,
242 char *dst_vaddr, *src_vaddr;
244 dst_vaddr = kmap(dst_page);
245 src_vaddr = kmap(src_page);
247 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
254 slow_shmem_bit17_copy(struct page *gpu_page,
256 struct page *cpu_page,
261 char *gpu_vaddr, *cpu_vaddr;
263 /* Use the unswizzled path if this page isn't affected. */
264 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
266 return slow_shmem_copy(cpu_page, cpu_offset,
267 gpu_page, gpu_offset, length);
269 return slow_shmem_copy(gpu_page, gpu_offset,
270 cpu_page, cpu_offset, length);
273 gpu_vaddr = kmap(gpu_page);
274 cpu_vaddr = kmap(cpu_page);
276 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
277 * XORing with the other bits (A9 for Y, A9 and A10 for X)
280 int cacheline_end = ALIGN(gpu_offset + 1, 64);
281 int this_length = min(cacheline_end - gpu_offset, length);
282 int swizzled_gpu_offset = gpu_offset ^ 64;
285 memcpy(cpu_vaddr + cpu_offset,
286 gpu_vaddr + swizzled_gpu_offset,
289 memcpy(gpu_vaddr + swizzled_gpu_offset,
290 cpu_vaddr + cpu_offset,
293 cpu_offset += this_length;
294 gpu_offset += this_length;
295 length -= this_length;
303 * This is the fast shmem pread path, which attempts to copy_from_user directly
304 * from the backing pages of the object to the user's address space. On a
305 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
308 i915_gem_shmem_pread_fast(struct drm_device *dev,
309 struct drm_i915_gem_object *obj,
310 struct drm_i915_gem_pread *args,
311 struct drm_file *file)
313 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
316 char __user *user_data;
317 int page_offset, page_length;
319 user_data = (char __user *) (uintptr_t) args->data_ptr;
322 offset = args->offset;
329 /* Operation in this page
331 * page_offset = offset within page
332 * page_length = bytes to copy for this page
334 page_offset = offset & (PAGE_SIZE-1);
335 page_length = remain;
336 if ((page_offset + remain) > PAGE_SIZE)
337 page_length = PAGE_SIZE - page_offset;
339 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
340 GFP_HIGHUSER | __GFP_RECLAIMABLE);
342 return PTR_ERR(page);
344 vaddr = kmap_atomic(page);
345 ret = __copy_to_user_inatomic(user_data,
348 kunmap_atomic(vaddr);
350 mark_page_accessed(page);
351 page_cache_release(page);
355 remain -= page_length;
356 user_data += page_length;
357 offset += page_length;
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev,
371 struct drm_i915_gem_object *obj,
372 struct drm_i915_gem_pread *args,
373 struct drm_file *file)
375 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
376 struct mm_struct *mm = current->mm;
377 struct page **user_pages;
379 loff_t offset, pinned_pages, i;
380 loff_t first_data_page, last_data_page, num_pages;
381 int shmem_page_offset;
382 int data_page_index, data_page_offset;
385 uint64_t data_ptr = args->data_ptr;
386 int do_bit17_swizzling;
390 /* Pin the user pages containing the data. We can't fault while
391 * holding the struct mutex, yet we want to hold it while
392 * dereferencing the user data.
394 first_data_page = data_ptr / PAGE_SIZE;
395 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
396 num_pages = last_data_page - first_data_page + 1;
398 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
399 if (user_pages == NULL)
402 mutex_unlock(&dev->struct_mutex);
403 down_read(&mm->mmap_sem);
404 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
405 num_pages, 1, 0, user_pages, NULL);
406 up_read(&mm->mmap_sem);
407 mutex_lock(&dev->struct_mutex);
408 if (pinned_pages < num_pages) {
413 ret = i915_gem_object_set_cpu_read_domain_range(obj,
419 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
421 offset = args->offset;
426 /* Operation in this page
428 * shmem_page_offset = offset within page in shmem file
429 * data_page_index = page number in get_user_pages return
430 * data_page_offset = offset with data_page_index page.
431 * page_length = bytes to copy for this page
433 shmem_page_offset = offset & ~PAGE_MASK;
434 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
435 data_page_offset = data_ptr & ~PAGE_MASK;
437 page_length = remain;
438 if ((shmem_page_offset + page_length) > PAGE_SIZE)
439 page_length = PAGE_SIZE - shmem_page_offset;
440 if ((data_page_offset + page_length) > PAGE_SIZE)
441 page_length = PAGE_SIZE - data_page_offset;
443 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
444 GFP_HIGHUSER | __GFP_RECLAIMABLE);
446 return PTR_ERR(page);
448 if (do_bit17_swizzling) {
449 slow_shmem_bit17_copy(page,
451 user_pages[data_page_index],
456 slow_shmem_copy(user_pages[data_page_index],
463 mark_page_accessed(page);
464 page_cache_release(page);
466 remain -= page_length;
467 data_ptr += page_length;
468 offset += page_length;
472 for (i = 0; i < pinned_pages; i++) {
473 SetPageDirty(user_pages[i]);
474 mark_page_accessed(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_i915_gem_object *obj;
498 if (!access_ok(VERIFY_WRITE,
499 (char __user *)(uintptr_t)args->data_ptr,
503 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
508 ret = i915_mutex_lock_interruptible(dev);
512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
518 /* Bounds check source. */
519 if (args->offset > obj->base.size ||
520 args->size > obj->base.size - args->offset) {
525 ret = i915_gem_object_set_cpu_read_domain_range(obj,
532 if (!i915_gem_object_needs_bit17_swizzle(obj))
533 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
535 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
538 drm_gem_object_unreference(&obj->base);
540 mutex_unlock(&dev->struct_mutex);
544 /* This is the fast write path which cannot handle
545 * page faults in the source data
549 fast_user_write(struct io_mapping *mapping,
550 loff_t page_base, int page_offset,
551 char __user *user_data,
555 unsigned long unwritten;
557 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
558 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
560 io_mapping_unmap_atomic(vaddr_atomic);
564 /* Here's the write path which can sleep for
569 slow_kernel_write(struct io_mapping *mapping,
570 loff_t gtt_base, int gtt_offset,
571 struct page *user_page, int user_offset,
574 char __iomem *dst_vaddr;
577 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
578 src_vaddr = kmap(user_page);
580 memcpy_toio(dst_vaddr + gtt_offset,
581 src_vaddr + user_offset,
585 io_mapping_unmap(dst_vaddr);
589 * This is the fast pwrite path, where we copy the data directly from the
590 * user into the GTT, uncached.
593 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
594 struct drm_i915_gem_object *obj,
595 struct drm_i915_gem_pwrite *args,
596 struct drm_file *file)
598 drm_i915_private_t *dev_priv = dev->dev_private;
600 loff_t offset, page_base;
601 char __user *user_data;
602 int page_offset, page_length;
604 user_data = (char __user *) (uintptr_t) args->data_ptr;
607 offset = obj->gtt_offset + args->offset;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
622 /* If we get a fault while copying data, then (presumably) our
623 * source page isn't available. Return the error and we'll
624 * retry in the slow path.
626 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
627 page_offset, user_data, page_length))
631 remain -= page_length;
632 user_data += page_length;
633 offset += page_length;
640 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
641 * the memory and maps it using kmap_atomic for copying.
643 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
644 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
647 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
648 struct drm_i915_gem_object *obj,
649 struct drm_i915_gem_pwrite *args,
650 struct drm_file *file)
652 drm_i915_private_t *dev_priv = dev->dev_private;
654 loff_t gtt_page_base, offset;
655 loff_t first_data_page, last_data_page, num_pages;
656 loff_t pinned_pages, i;
657 struct page **user_pages;
658 struct mm_struct *mm = current->mm;
659 int gtt_page_offset, data_page_offset, data_page_index, page_length;
661 uint64_t data_ptr = args->data_ptr;
665 /* Pin the user pages containing the data. We can't fault while
666 * holding the struct mutex, and all of the pwrite implementations
667 * want to hold it while dereferencing the user data.
669 first_data_page = data_ptr / PAGE_SIZE;
670 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
671 num_pages = last_data_page - first_data_page + 1;
673 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
674 if (user_pages == NULL)
677 mutex_unlock(&dev->struct_mutex);
678 down_read(&mm->mmap_sem);
679 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
680 num_pages, 0, 0, user_pages, NULL);
681 up_read(&mm->mmap_sem);
682 mutex_lock(&dev->struct_mutex);
683 if (pinned_pages < num_pages) {
685 goto out_unpin_pages;
688 ret = i915_gem_object_set_to_gtt_domain(obj, true);
690 goto out_unpin_pages;
692 ret = i915_gem_object_put_fence(obj);
694 goto out_unpin_pages;
696 offset = obj->gtt_offset + args->offset;
699 /* Operation in this page
701 * gtt_page_base = page offset within aperture
702 * gtt_page_offset = offset within page in aperture
703 * data_page_index = page number in get_user_pages return
704 * data_page_offset = offset with data_page_index page.
705 * page_length = bytes to copy for this page
707 gtt_page_base = offset & PAGE_MASK;
708 gtt_page_offset = offset & ~PAGE_MASK;
709 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
710 data_page_offset = data_ptr & ~PAGE_MASK;
712 page_length = remain;
713 if ((gtt_page_offset + page_length) > PAGE_SIZE)
714 page_length = PAGE_SIZE - gtt_page_offset;
715 if ((data_page_offset + page_length) > PAGE_SIZE)
716 page_length = PAGE_SIZE - data_page_offset;
718 slow_kernel_write(dev_priv->mm.gtt_mapping,
719 gtt_page_base, gtt_page_offset,
720 user_pages[data_page_index],
724 remain -= page_length;
725 offset += page_length;
726 data_ptr += page_length;
730 for (i = 0; i < pinned_pages; i++)
731 page_cache_release(user_pages[i]);
732 drm_free_large(user_pages);
738 * This is the fast shmem pwrite path, which attempts to directly
739 * copy_from_user into the kmapped pages backing the object.
742 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
743 struct drm_i915_gem_object *obj,
744 struct drm_i915_gem_pwrite *args,
745 struct drm_file *file)
747 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
750 char __user *user_data;
751 int page_offset, page_length;
753 user_data = (char __user *) (uintptr_t) args->data_ptr;
756 offset = args->offset;
764 /* Operation in this page
766 * page_offset = offset within page
767 * page_length = bytes to copy for this page
769 page_offset = offset & (PAGE_SIZE-1);
770 page_length = remain;
771 if ((page_offset + remain) > PAGE_SIZE)
772 page_length = PAGE_SIZE - page_offset;
774 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
775 GFP_HIGHUSER | __GFP_RECLAIMABLE);
777 return PTR_ERR(page);
779 vaddr = kmap_atomic(page, KM_USER0);
780 ret = __copy_from_user_inatomic(vaddr + page_offset,
783 kunmap_atomic(vaddr, KM_USER0);
785 set_page_dirty(page);
786 mark_page_accessed(page);
787 page_cache_release(page);
789 /* If we get a fault while copying data, then (presumably) our
790 * source page isn't available. Return the error and we'll
791 * retry in the slow path.
796 remain -= page_length;
797 user_data += page_length;
798 offset += page_length;
805 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
806 * the memory and maps it using kmap_atomic for copying.
808 * This avoids taking mmap_sem for faulting on the user's address while the
809 * struct_mutex is held.
812 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
813 struct drm_i915_gem_object *obj,
814 struct drm_i915_gem_pwrite *args,
815 struct drm_file *file)
817 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
818 struct mm_struct *mm = current->mm;
819 struct page **user_pages;
821 loff_t offset, pinned_pages, i;
822 loff_t first_data_page, last_data_page, num_pages;
823 int shmem_page_offset;
824 int data_page_index, data_page_offset;
827 uint64_t data_ptr = args->data_ptr;
828 int do_bit17_swizzling;
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
836 first_data_page = data_ptr / PAGE_SIZE;
837 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
838 num_pages = last_data_page - first_data_page + 1;
840 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
841 if (user_pages == NULL)
844 mutex_unlock(&dev->struct_mutex);
845 down_read(&mm->mmap_sem);
846 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
847 num_pages, 0, 0, user_pages, NULL);
848 up_read(&mm->mmap_sem);
849 mutex_lock(&dev->struct_mutex);
850 if (pinned_pages < num_pages) {
855 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
859 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
861 offset = args->offset;
867 /* Operation in this page
869 * shmem_page_offset = offset within page in shmem file
870 * data_page_index = page number in get_user_pages return
871 * data_page_offset = offset with data_page_index page.
872 * page_length = bytes to copy for this page
874 shmem_page_offset = offset & ~PAGE_MASK;
875 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
876 data_page_offset = data_ptr & ~PAGE_MASK;
878 page_length = remain;
879 if ((shmem_page_offset + page_length) > PAGE_SIZE)
880 page_length = PAGE_SIZE - shmem_page_offset;
881 if ((data_page_offset + page_length) > PAGE_SIZE)
882 page_length = PAGE_SIZE - data_page_offset;
884 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
885 GFP_HIGHUSER | __GFP_RECLAIMABLE);
891 if (do_bit17_swizzling) {
892 slow_shmem_bit17_copy(page,
894 user_pages[data_page_index],
899 slow_shmem_copy(page,
901 user_pages[data_page_index],
906 set_page_dirty(page);
907 mark_page_accessed(page);
908 page_cache_release(page);
910 remain -= page_length;
911 data_ptr += page_length;
912 offset += page_length;
916 for (i = 0; i < pinned_pages; i++)
917 page_cache_release(user_pages[i]);
918 drm_free_large(user_pages);
924 * Writes data to the object referenced by handle.
926 * On error, the contents of the buffer that were to be modified are undefined.
929 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
930 struct drm_file *file)
932 struct drm_i915_gem_pwrite *args = data;
933 struct drm_i915_gem_object *obj;
939 if (!access_ok(VERIFY_READ,
940 (char __user *)(uintptr_t)args->data_ptr,
944 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
949 ret = i915_mutex_lock_interruptible(dev);
953 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
959 /* Bounds check destination. */
960 if (args->offset > obj->base.size ||
961 args->size > obj->base.size - args->offset) {
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
973 ret = i915_gem_phys_pwrite(dev, obj, args, file);
974 else if (obj->gtt_space &&
975 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
976 ret = i915_gem_object_pin(obj, 0, true);
980 ret = i915_gem_object_set_to_gtt_domain(obj, true);
984 ret = i915_gem_object_put_fence(obj);
988 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
990 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
993 i915_gem_object_unpin(obj);
995 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1000 if (!i915_gem_object_needs_bit17_swizzle(obj))
1001 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1003 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1007 drm_gem_object_unreference(&obj->base);
1009 mutex_unlock(&dev->struct_mutex);
1014 * Called when user space prepares to use an object with the CPU, either
1015 * through the mmap ioctl's mapping or a GTT mapping.
1018 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1019 struct drm_file *file)
1021 struct drm_i915_gem_set_domain *args = data;
1022 struct drm_i915_gem_object *obj;
1023 uint32_t read_domains = args->read_domains;
1024 uint32_t write_domain = args->write_domain;
1027 if (!(dev->driver->driver_features & DRIVER_GEM))
1030 /* Only handle setting domains to types used by the CPU. */
1031 if (write_domain & I915_GEM_GPU_DOMAINS)
1034 if (read_domains & I915_GEM_GPU_DOMAINS)
1037 /* Having something in the write domain implies it's in the read
1038 * domain, and only that read domain. Enforce that in the request.
1040 if (write_domain != 0 && read_domains != write_domain)
1043 ret = i915_mutex_lock_interruptible(dev);
1047 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1053 if (read_domains & I915_GEM_DOMAIN_GTT) {
1054 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1056 /* Silently promote "you're not bound, there was nothing to do"
1057 * to success, since the client was just asking us to
1058 * make sure everything was done.
1063 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1066 drm_gem_object_unreference(&obj->base);
1068 mutex_unlock(&dev->struct_mutex);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file)
1079 struct drm_i915_gem_sw_finish *args = data;
1080 struct drm_i915_gem_object *obj;
1083 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 ret = i915_mutex_lock_interruptible(dev);
1090 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1096 /* Pinned buffers may be scanout, so flush the cache */
1098 i915_gem_object_flush_cpu_write_domain(obj);
1100 drm_gem_object_unreference(&obj->base);
1102 mutex_unlock(&dev->struct_mutex);
1107 * Maps the contents of an object, returning the address it is mapped
1110 * While the mapping holds a reference on the contents of the object, it doesn't
1111 * imply a ref on the object itself.
1114 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file)
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 struct drm_i915_gem_mmap *args = data;
1119 struct drm_gem_object *obj;
1123 if (!(dev->driver->driver_features & DRIVER_GEM))
1126 obj = drm_gem_object_lookup(dev, file, args->handle);
1130 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1131 drm_gem_object_unreference_unlocked(obj);
1135 offset = args->offset;
1137 down_write(¤t->mm->mmap_sem);
1138 addr = do_mmap(obj->filp, 0, args->size,
1139 PROT_READ | PROT_WRITE, MAP_SHARED,
1141 up_write(¤t->mm->mmap_sem);
1142 drm_gem_object_unreference_unlocked(obj);
1143 if (IS_ERR((void *)addr))
1146 args->addr_ptr = (uint64_t) addr;
1152 * i915_gem_fault - fault a page into the GTT
1153 * vma: VMA in question
1156 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1157 * from userspace. The fault handler takes care of binding the object to
1158 * the GTT (if needed), allocating and programming a fence register (again,
1159 * only if needed based on whether the old reg is still valid or the object
1160 * is tiled) and inserting a new PTE into the faulting process.
1162 * Note that the faulting process may involve evicting existing objects
1163 * from the GTT and/or fence registers to make room. So performance may
1164 * suffer if the GTT working set is large or there are few fence registers
1167 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1170 struct drm_device *dev = obj->base.dev;
1171 drm_i915_private_t *dev_priv = dev->dev_private;
1172 pgoff_t page_offset;
1175 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1177 /* We don't use vmf->pgoff since that has the fake offset */
1178 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181 /* Now bind it into the GTT if needed */
1182 mutex_lock(&dev->struct_mutex);
1184 if (!obj->map_and_fenceable) {
1185 ret = i915_gem_object_unbind(obj);
1189 if (!obj->gtt_space) {
1190 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1195 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1199 if (obj->tiling_mode == I915_TILING_NONE)
1200 ret = i915_gem_object_put_fence(obj);
1202 ret = i915_gem_object_get_fence(obj, NULL, true);
1206 if (i915_gem_object_is_inactive(obj))
1207 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1209 obj->fault_mappable = true;
1211 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1214 /* Finally, remap it using the new GTT offset */
1215 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1217 mutex_unlock(&dev->struct_mutex);
1224 return VM_FAULT_NOPAGE;
1226 return VM_FAULT_OOM;
1228 return VM_FAULT_SIGBUS;
1233 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1234 * @obj: obj in question
1236 * GEM memory mapping works by handing back to userspace a fake mmap offset
1237 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1238 * up the object based on the offset and sets up the various memory mapping
1241 * This routine allocates and attaches a fake offset for @obj.
1244 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1246 struct drm_device *dev = obj->base.dev;
1247 struct drm_gem_mm *mm = dev->mm_private;
1248 struct drm_map_list *list;
1249 struct drm_local_map *map;
1252 /* Set the object up for mmap'ing */
1253 list = &obj->base.map_list;
1254 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1259 map->type = _DRM_GEM;
1260 map->size = obj->base.size;
1263 /* Get a DRM GEM mmap offset allocated... */
1264 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1265 obj->base.size / PAGE_SIZE,
1267 if (!list->file_offset_node) {
1268 DRM_ERROR("failed to allocate offset for bo %d\n",
1274 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1275 obj->base.size / PAGE_SIZE,
1277 if (!list->file_offset_node) {
1282 list->hash.key = list->file_offset_node->start;
1283 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1285 DRM_ERROR("failed to add to map hash\n");
1292 drm_mm_put_block(list->file_offset_node);
1301 * i915_gem_release_mmap - remove physical page mappings
1302 * @obj: obj in question
1304 * Preserve the reservation of the mmapping with the DRM core code, but
1305 * relinquish ownership of the pages back to the system.
1307 * It is vital that we remove the page mapping if we have mapped a tiled
1308 * object through the GTT and then lose the fence register due to
1309 * resource pressure. Similarly if the object has been moved out of the
1310 * aperture, than pages mapped into userspace must be revoked. Removing the
1311 * mapping will then trigger a page fault on the next user access, allowing
1312 * fixup by i915_gem_fault().
1315 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1317 if (!obj->fault_mappable)
1320 unmap_mapping_range(obj->base.dev->dev_mapping,
1321 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1324 obj->fault_mappable = false;
1328 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1330 struct drm_device *dev = obj->base.dev;
1331 struct drm_gem_mm *mm = dev->mm_private;
1332 struct drm_map_list *list = &obj->base.map_list;
1334 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1335 drm_mm_put_block(list->file_offset_node);
1341 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1343 struct drm_device *dev = obj->base.dev;
1346 if (INTEL_INFO(dev)->gen >= 4 ||
1347 obj->tiling_mode == I915_TILING_NONE)
1348 return obj->base.size;
1350 /* Previous chips need a power-of-two fence region when tiling */
1351 if (INTEL_INFO(dev)->gen == 3)
1356 while (size < obj->base.size)
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping.
1370 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1372 struct drm_device *dev = obj->base.dev;
1375 * Minimum alignment is 4k (GTT page size), but might be greater
1376 * if a fence register is needed for the object.
1378 if (INTEL_INFO(dev)->gen >= 4 ||
1379 obj->tiling_mode == I915_TILING_NONE)
1383 * Previous chips need to be aligned to the size of the smallest
1384 * fence register that can contain the object.
1386 return i915_gem_get_gtt_size(obj);
1390 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1392 * @obj: object to check
1394 * Return the required GTT alignment for an object, only taking into account
1395 * unfenced tiled surface requirements.
1398 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1400 struct drm_device *dev = obj->base.dev;
1404 * Minimum alignment is 4k (GTT page size) for sane hw.
1406 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1407 obj->tiling_mode == I915_TILING_NONE)
1411 * Older chips need unfenced tiled buffers to be aligned to the left
1412 * edge of an even tile row (where tile rows are counted as if the bo is
1413 * placed in a fenced gtt region).
1416 (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1421 return tile_height * obj->stride * 2;
1425 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1427 * @data: GTT mapping ioctl data
1428 * @file: GEM object info
1430 * Simply returns the fake offset to userspace so it can mmap it.
1431 * The mmap call will end up in drm_gem_mmap(), which will set things
1432 * up so we can get faults in the handler above.
1434 * The fault handler will take care of binding the object into the GTT
1435 * (since it may have been evicted to make room for something), allocating
1436 * a fence register, and mapping the appropriate aperture address into
1440 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1441 struct drm_file *file)
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 struct drm_i915_gem_mmap_gtt *args = data;
1445 struct drm_i915_gem_object *obj;
1448 if (!(dev->driver->driver_features & DRIVER_GEM))
1451 ret = i915_mutex_lock_interruptible(dev);
1455 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1461 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1466 if (obj->madv != I915_MADV_WILLNEED) {
1467 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1472 if (!obj->base.map_list.map) {
1473 ret = i915_gem_create_mmap_offset(obj);
1478 args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1481 drm_gem_object_unreference(&obj->base);
1483 mutex_unlock(&dev->struct_mutex);
1488 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1492 struct address_space *mapping;
1493 struct inode *inode;
1496 /* Get the list of pages out of our struct file. They'll be pinned
1497 * at this point until we release them.
1499 page_count = obj->base.size / PAGE_SIZE;
1500 BUG_ON(obj->pages != NULL);
1501 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1502 if (obj->pages == NULL)
1505 inode = obj->base.filp->f_path.dentry->d_inode;
1506 mapping = inode->i_mapping;
1507 for (i = 0; i < page_count; i++) {
1508 page = read_cache_page_gfp(mapping, i,
1516 obj->pages[i] = page;
1519 if (obj->tiling_mode != I915_TILING_NONE)
1520 i915_gem_object_do_bit_17_swizzle(obj);
1526 page_cache_release(obj->pages[i]);
1528 drm_free_large(obj->pages);
1530 return PTR_ERR(page);
1534 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1536 int page_count = obj->base.size / PAGE_SIZE;
1539 BUG_ON(obj->madv == __I915_MADV_PURGED);
1541 if (obj->tiling_mode != I915_TILING_NONE)
1542 i915_gem_object_save_bit_17_swizzle(obj);
1544 if (obj->madv == I915_MADV_DONTNEED)
1547 for (i = 0; i < page_count; i++) {
1549 set_page_dirty(obj->pages[i]);
1551 if (obj->madv == I915_MADV_WILLNEED)
1552 mark_page_accessed(obj->pages[i]);
1554 page_cache_release(obj->pages[i]);
1558 drm_free_large(obj->pages);
1563 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1564 struct intel_ring_buffer *ring,
1567 struct drm_device *dev = obj->base.dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1570 BUG_ON(ring == NULL);
1573 /* Add a reference if we're newly entering the active list. */
1575 drm_gem_object_reference(&obj->base);
1579 /* Move from whatever list we were on to the tail of execution. */
1580 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1581 list_move_tail(&obj->ring_list, &ring->active_list);
1583 obj->last_rendering_seqno = seqno;
1584 if (obj->fenced_gpu_access) {
1585 struct drm_i915_fence_reg *reg;
1587 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1589 obj->last_fenced_seqno = seqno;
1590 obj->last_fenced_ring = ring;
1592 reg = &dev_priv->fence_regs[obj->fence_reg];
1593 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1598 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1600 list_del_init(&obj->ring_list);
1601 obj->last_rendering_seqno = 0;
1605 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1607 struct drm_device *dev = obj->base.dev;
1608 drm_i915_private_t *dev_priv = dev->dev_private;
1610 BUG_ON(!obj->active);
1611 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1613 i915_gem_object_move_off_active(obj);
1617 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1619 struct drm_device *dev = obj->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1622 if (obj->pin_count != 0)
1623 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1625 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1627 BUG_ON(!list_empty(&obj->gpu_write_list));
1628 BUG_ON(!obj->active);
1631 i915_gem_object_move_off_active(obj);
1632 obj->fenced_gpu_access = false;
1635 obj->pending_gpu_write = false;
1636 drm_gem_object_unreference(&obj->base);
1638 WARN_ON(i915_verify_lists(dev));
1641 /* Immediately discard the backing storage */
1643 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1645 struct inode *inode;
1647 /* Our goal here is to return as much of the memory as
1648 * is possible back to the system as we are called from OOM.
1649 * To do this we must instruct the shmfs to drop all of its
1650 * backing pages, *now*. Here we mirror the actions taken
1651 * when by shmem_delete_inode() to release the backing store.
1653 inode = obj->base.filp->f_path.dentry->d_inode;
1654 truncate_inode_pages(inode->i_mapping, 0);
1655 if (inode->i_op->truncate_range)
1656 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1658 obj->madv = __I915_MADV_PURGED;
1662 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1664 return obj->madv == I915_MADV_DONTNEED;
1668 i915_gem_process_flushing_list(struct drm_device *dev,
1669 uint32_t flush_domains,
1670 struct intel_ring_buffer *ring)
1672 struct drm_i915_gem_object *obj, *next;
1674 list_for_each_entry_safe(obj, next,
1675 &ring->gpu_write_list,
1677 if (obj->base.write_domain & flush_domains) {
1678 uint32_t old_write_domain = obj->base.write_domain;
1680 obj->base.write_domain = 0;
1681 list_del_init(&obj->gpu_write_list);
1682 i915_gem_object_move_to_active(obj, ring,
1683 i915_gem_next_request_seqno(dev, ring));
1685 trace_i915_gem_object_change_domain(obj,
1686 obj->base.read_domains,
1693 i915_add_request(struct drm_device *dev,
1694 struct drm_file *file,
1695 struct drm_i915_gem_request *request,
1696 struct intel_ring_buffer *ring)
1698 drm_i915_private_t *dev_priv = dev->dev_private;
1699 struct drm_i915_file_private *file_priv = NULL;
1704 BUG_ON(request == NULL);
1707 file_priv = file->driver_priv;
1709 ret = ring->add_request(ring, &seqno);
1713 ring->outstanding_lazy_request = false;
1715 request->seqno = seqno;
1716 request->ring = ring;
1717 request->emitted_jiffies = jiffies;
1718 was_empty = list_empty(&ring->request_list);
1719 list_add_tail(&request->list, &ring->request_list);
1722 spin_lock(&file_priv->mm.lock);
1723 request->file_priv = file_priv;
1724 list_add_tail(&request->client_list,
1725 &file_priv->mm.request_list);
1726 spin_unlock(&file_priv->mm.lock);
1729 if (!dev_priv->mm.suspended) {
1730 mod_timer(&dev_priv->hangcheck_timer,
1731 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1733 queue_delayed_work(dev_priv->wq,
1734 &dev_priv->mm.retire_work, HZ);
1740 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1742 struct drm_i915_file_private *file_priv = request->file_priv;
1747 spin_lock(&file_priv->mm.lock);
1748 list_del(&request->client_list);
1749 request->file_priv = NULL;
1750 spin_unlock(&file_priv->mm.lock);
1753 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1754 struct intel_ring_buffer *ring)
1756 while (!list_empty(&ring->request_list)) {
1757 struct drm_i915_gem_request *request;
1759 request = list_first_entry(&ring->request_list,
1760 struct drm_i915_gem_request,
1763 list_del(&request->list);
1764 i915_gem_request_remove_from_client(request);
1768 while (!list_empty(&ring->active_list)) {
1769 struct drm_i915_gem_object *obj;
1771 obj = list_first_entry(&ring->active_list,
1772 struct drm_i915_gem_object,
1775 obj->base.write_domain = 0;
1776 list_del_init(&obj->gpu_write_list);
1777 i915_gem_object_move_to_inactive(obj);
1781 static void i915_gem_reset_fences(struct drm_device *dev)
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1786 for (i = 0; i < 16; i++) {
1787 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1788 struct drm_i915_gem_object *obj = reg->obj;
1793 if (obj->tiling_mode)
1794 i915_gem_release_mmap(obj);
1796 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1797 reg->obj->fenced_gpu_access = false;
1798 reg->obj->last_fenced_seqno = 0;
1799 reg->obj->last_fenced_ring = NULL;
1800 i915_gem_clear_fence_reg(dev, reg);
1804 void i915_gem_reset(struct drm_device *dev)
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct drm_i915_gem_object *obj;
1810 for (i = 0; i < I915_NUM_RINGS; i++)
1811 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1813 /* Remove anything from the flushing lists. The GPU cache is likely
1814 * to be lost on reset along with the data, so simply move the
1815 * lost bo to the inactive list.
1817 while (!list_empty(&dev_priv->mm.flushing_list)) {
1818 obj= list_first_entry(&dev_priv->mm.flushing_list,
1819 struct drm_i915_gem_object,
1822 obj->base.write_domain = 0;
1823 list_del_init(&obj->gpu_write_list);
1824 i915_gem_object_move_to_inactive(obj);
1827 /* Move everything out of the GPU domains to ensure we do any
1828 * necessary invalidation upon reuse.
1830 list_for_each_entry(obj,
1831 &dev_priv->mm.inactive_list,
1834 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1837 /* The fence registers are invalidated so clear them out */
1838 i915_gem_reset_fences(dev);
1842 * This function clears the request list as sequence numbers are passed.
1845 i915_gem_retire_requests_ring(struct drm_device *dev,
1846 struct intel_ring_buffer *ring)
1848 drm_i915_private_t *dev_priv = dev->dev_private;
1852 if (!ring->status_page.page_addr ||
1853 list_empty(&ring->request_list))
1856 WARN_ON(i915_verify_lists(dev));
1858 seqno = ring->get_seqno(ring);
1860 for (i = 0; i < I915_NUM_RINGS; i++)
1861 if (seqno >= ring->sync_seqno[i])
1862 ring->sync_seqno[i] = 0;
1864 while (!list_empty(&ring->request_list)) {
1865 struct drm_i915_gem_request *request;
1867 request = list_first_entry(&ring->request_list,
1868 struct drm_i915_gem_request,
1871 if (!i915_seqno_passed(seqno, request->seqno))
1874 trace_i915_gem_request_retire(dev, request->seqno);
1876 list_del(&request->list);
1877 i915_gem_request_remove_from_client(request);
1881 /* Move any buffers on the active list that are no longer referenced
1882 * by the ringbuffer to the flushing/inactive lists as appropriate.
1884 while (!list_empty(&ring->active_list)) {
1885 struct drm_i915_gem_object *obj;
1887 obj= list_first_entry(&ring->active_list,
1888 struct drm_i915_gem_object,
1891 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1894 if (obj->base.write_domain != 0)
1895 i915_gem_object_move_to_flushing(obj);
1897 i915_gem_object_move_to_inactive(obj);
1900 if (unlikely (dev_priv->trace_irq_seqno &&
1901 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1902 ring->irq_put(ring);
1903 dev_priv->trace_irq_seqno = 0;
1906 WARN_ON(i915_verify_lists(dev));
1910 i915_gem_retire_requests(struct drm_device *dev)
1912 drm_i915_private_t *dev_priv = dev->dev_private;
1915 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1916 struct drm_i915_gem_object *obj, *next;
1918 /* We must be careful that during unbind() we do not
1919 * accidentally infinitely recurse into retire requests.
1921 * retire -> free -> unbind -> wait -> retire_ring
1923 list_for_each_entry_safe(obj, next,
1924 &dev_priv->mm.deferred_free_list,
1926 i915_gem_free_object_tail(obj);
1929 for (i = 0; i < I915_NUM_RINGS; i++)
1930 i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]);
1934 i915_gem_retire_work_handler(struct work_struct *work)
1936 drm_i915_private_t *dev_priv;
1937 struct drm_device *dev;
1939 dev_priv = container_of(work, drm_i915_private_t,
1940 mm.retire_work.work);
1941 dev = dev_priv->dev;
1943 /* Come back later if the device is busy... */
1944 if (!mutex_trylock(&dev->struct_mutex)) {
1945 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1949 i915_gem_retire_requests(dev);
1951 if (!dev_priv->mm.suspended &&
1952 (!list_empty(&dev_priv->ring[RCS].request_list) ||
1953 !list_empty(&dev_priv->ring[VCS].request_list) ||
1954 !list_empty(&dev_priv->ring[BCS].request_list)))
1955 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1956 mutex_unlock(&dev->struct_mutex);
1960 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1961 bool interruptible, struct intel_ring_buffer *ring)
1963 drm_i915_private_t *dev_priv = dev->dev_private;
1969 if (atomic_read(&dev_priv->mm.wedged))
1972 if (seqno == ring->outstanding_lazy_request) {
1973 struct drm_i915_gem_request *request;
1975 request = kzalloc(sizeof(*request), GFP_KERNEL);
1976 if (request == NULL)
1979 ret = i915_add_request(dev, NULL, request, ring);
1985 seqno = request->seqno;
1988 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1989 if (HAS_PCH_SPLIT(dev))
1990 ier = I915_READ(DEIER) | I915_READ(GTIER);
1992 ier = I915_READ(IER);
1994 DRM_ERROR("something (likely vbetool) disabled "
1995 "interrupts, re-enabling\n");
1996 i915_driver_irq_preinstall(dev);
1997 i915_driver_irq_postinstall(dev);
2000 trace_i915_gem_request_wait_begin(dev, seqno);
2002 ring->waiting_seqno = seqno;
2003 if (ring->irq_get(ring)) {
2005 ret = wait_event_interruptible(ring->irq_queue,
2006 i915_seqno_passed(ring->get_seqno(ring), seqno)
2007 || atomic_read(&dev_priv->mm.wedged));
2009 wait_event(ring->irq_queue,
2010 i915_seqno_passed(ring->get_seqno(ring), seqno)
2011 || atomic_read(&dev_priv->mm.wedged));
2013 ring->irq_put(ring);
2014 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2016 atomic_read(&dev_priv->mm.wedged), 3000))
2018 ring->waiting_seqno = 0;
2020 trace_i915_gem_request_wait_end(dev, seqno);
2022 if (atomic_read(&dev_priv->mm.wedged))
2025 if (ret && ret != -ERESTARTSYS)
2026 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2027 __func__, ret, seqno, ring->get_seqno(ring),
2028 dev_priv->next_seqno);
2030 /* Directly dispatch request retiring. While we have the work queue
2031 * to handle this, the waiter on a request often wants an associated
2032 * buffer to have made it to the inactive list, and we would need
2033 * a separate wait queue to handle that.
2036 i915_gem_retire_requests_ring(dev, ring);
2042 * Waits for a sequence number to be signaled, and cleans up the
2043 * request and object lists appropriately for that event.
2046 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2047 struct intel_ring_buffer *ring)
2049 return i915_do_wait_request(dev, seqno, 1, ring);
2053 * Ensures that all rendering to the object has completed and the object is
2054 * safe to unbind from the GTT or access from the CPU.
2057 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2060 struct drm_device *dev = obj->base.dev;
2063 /* This function only exists to support waiting for existing rendering,
2064 * not for emitting required flushes.
2066 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2068 /* If there is rendering queued on the buffer being evicted, wait for
2072 ret = i915_do_wait_request(dev,
2073 obj->last_rendering_seqno,
2084 * Unbinds an object from the GTT aperture.
2087 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2091 if (obj->gtt_space == NULL)
2094 if (obj->pin_count != 0) {
2095 DRM_ERROR("Attempting to unbind pinned buffer\n");
2099 /* blow away mappings if mapped through GTT */
2100 i915_gem_release_mmap(obj);
2102 /* Move the object to the CPU domain to ensure that
2103 * any possible CPU writes while it's not in the GTT
2104 * are flushed when we go to remap it. This will
2105 * also ensure that all pending GPU writes are finished
2108 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2109 if (ret == -ERESTARTSYS)
2111 /* Continue on if we fail due to EIO, the GPU is hung so we
2112 * should be safe and we need to cleanup or else we might
2113 * cause memory corruption through use-after-free.
2116 i915_gem_clflush_object(obj);
2117 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2120 /* release the fence reg _after_ flushing */
2121 ret = i915_gem_object_put_fence(obj);
2122 if (ret == -ERESTARTSYS)
2125 i915_gem_gtt_unbind_object(obj);
2126 i915_gem_object_put_pages_gtt(obj);
2128 list_del_init(&obj->gtt_list);
2129 list_del_init(&obj->mm_list);
2130 /* Avoid an unnecessary call to unbind on rebind. */
2131 obj->map_and_fenceable = true;
2133 drm_mm_put_block(obj->gtt_space);
2134 obj->gtt_space = NULL;
2135 obj->gtt_offset = 0;
2137 if (i915_gem_object_is_purgeable(obj))
2138 i915_gem_object_truncate(obj);
2140 trace_i915_gem_object_unbind(obj);
2146 i915_gem_flush_ring(struct drm_device *dev,
2147 struct intel_ring_buffer *ring,
2148 uint32_t invalidate_domains,
2149 uint32_t flush_domains)
2151 ring->flush(ring, invalidate_domains, flush_domains);
2152 i915_gem_process_flushing_list(dev, flush_domains, ring);
2155 static int i915_ring_idle(struct drm_device *dev,
2156 struct intel_ring_buffer *ring)
2158 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2161 if (!list_empty(&ring->gpu_write_list))
2162 i915_gem_flush_ring(dev, ring,
2163 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2164 return i915_wait_request(dev,
2165 i915_gem_next_request_seqno(dev, ring),
2170 i915_gpu_idle(struct drm_device *dev)
2172 drm_i915_private_t *dev_priv = dev->dev_private;
2176 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2177 list_empty(&dev_priv->mm.active_list));
2181 /* Flush everything onto the inactive list. */
2182 for (i = 0; i < I915_NUM_RINGS; i++) {
2183 ret = i915_ring_idle(dev, &dev_priv->ring[i]);
2191 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2192 struct intel_ring_buffer *pipelined)
2194 struct drm_device *dev = obj->base.dev;
2195 drm_i915_private_t *dev_priv = dev->dev_private;
2196 u32 size = obj->gtt_space->size;
2197 int regnum = obj->fence_reg;
2200 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2202 val |= obj->gtt_offset & 0xfffff000;
2203 val |= (uint64_t)((obj->stride / 128) - 1) <<
2204 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2206 if (obj->tiling_mode == I915_TILING_Y)
2207 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2208 val |= I965_FENCE_REG_VALID;
2211 int ret = intel_ring_begin(pipelined, 6);
2215 intel_ring_emit(pipelined, MI_NOOP);
2216 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2217 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2218 intel_ring_emit(pipelined, (u32)val);
2219 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2220 intel_ring_emit(pipelined, (u32)(val >> 32));
2221 intel_ring_advance(pipelined);
2223 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2228 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2229 struct intel_ring_buffer *pipelined)
2231 struct drm_device *dev = obj->base.dev;
2232 drm_i915_private_t *dev_priv = dev->dev_private;
2233 u32 size = obj->gtt_space->size;
2234 int regnum = obj->fence_reg;
2237 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2239 val |= obj->gtt_offset & 0xfffff000;
2240 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2241 if (obj->tiling_mode == I915_TILING_Y)
2242 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2243 val |= I965_FENCE_REG_VALID;
2246 int ret = intel_ring_begin(pipelined, 6);
2250 intel_ring_emit(pipelined, MI_NOOP);
2251 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2252 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2253 intel_ring_emit(pipelined, (u32)val);
2254 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2255 intel_ring_emit(pipelined, (u32)(val >> 32));
2256 intel_ring_advance(pipelined);
2258 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2263 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2264 struct intel_ring_buffer *pipelined)
2266 struct drm_device *dev = obj->base.dev;
2267 drm_i915_private_t *dev_priv = dev->dev_private;
2268 u32 size = obj->gtt_space->size;
2269 u32 fence_reg, val, pitch_val;
2272 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2273 (size & -size) != size ||
2274 (obj->gtt_offset & (size - 1)),
2275 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2276 obj->gtt_offset, obj->map_and_fenceable, size))
2279 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2284 /* Note: pitch better be a power of two tile widths */
2285 pitch_val = obj->stride / tile_width;
2286 pitch_val = ffs(pitch_val) - 1;
2288 val = obj->gtt_offset;
2289 if (obj->tiling_mode == I915_TILING_Y)
2290 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2291 val |= I915_FENCE_SIZE_BITS(size);
2292 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2293 val |= I830_FENCE_REG_VALID;
2295 fence_reg = obj->fence_reg;
2297 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2299 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2302 int ret = intel_ring_begin(pipelined, 4);
2306 intel_ring_emit(pipelined, MI_NOOP);
2307 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2308 intel_ring_emit(pipelined, fence_reg);
2309 intel_ring_emit(pipelined, val);
2310 intel_ring_advance(pipelined);
2312 I915_WRITE(fence_reg, val);
2317 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2318 struct intel_ring_buffer *pipelined)
2320 struct drm_device *dev = obj->base.dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
2322 u32 size = obj->gtt_space->size;
2323 int regnum = obj->fence_reg;
2327 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2328 (size & -size) != size ||
2329 (obj->gtt_offset & (size - 1)),
2330 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2331 obj->gtt_offset, size))
2334 pitch_val = obj->stride / 128;
2335 pitch_val = ffs(pitch_val) - 1;
2337 val = obj->gtt_offset;
2338 if (obj->tiling_mode == I915_TILING_Y)
2339 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2340 val |= I830_FENCE_SIZE_BITS(size);
2341 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2342 val |= I830_FENCE_REG_VALID;
2345 int ret = intel_ring_begin(pipelined, 4);
2349 intel_ring_emit(pipelined, MI_NOOP);
2350 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2351 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2352 intel_ring_emit(pipelined, val);
2353 intel_ring_advance(pipelined);
2355 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2360 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2362 return i915_seqno_passed(ring->get_seqno(ring), seqno);
2366 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2367 struct intel_ring_buffer *pipelined,
2372 if (obj->fenced_gpu_access) {
2373 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2374 i915_gem_flush_ring(obj->base.dev,
2375 obj->last_fenced_ring,
2376 0, obj->base.write_domain);
2378 obj->fenced_gpu_access = false;
2381 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2382 if (!ring_passed_seqno(obj->last_fenced_ring,
2383 obj->last_fenced_seqno)) {
2384 ret = i915_do_wait_request(obj->base.dev,
2385 obj->last_fenced_seqno,
2387 obj->last_fenced_ring);
2392 obj->last_fenced_seqno = 0;
2393 obj->last_fenced_ring = NULL;
2400 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2404 if (obj->tiling_mode)
2405 i915_gem_release_mmap(obj);
2407 ret = i915_gem_object_flush_fence(obj, NULL, true);
2411 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2412 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2413 i915_gem_clear_fence_reg(obj->base.dev,
2414 &dev_priv->fence_regs[obj->fence_reg]);
2416 obj->fence_reg = I915_FENCE_REG_NONE;
2422 static struct drm_i915_fence_reg *
2423 i915_find_fence_reg(struct drm_device *dev,
2424 struct intel_ring_buffer *pipelined)
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct drm_i915_fence_reg *reg, *first, *avail;
2430 /* First try to find a free reg */
2432 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2433 reg = &dev_priv->fence_regs[i];
2437 if (!reg->obj->pin_count)
2444 /* None available, try to steal one or wait for a user to finish */
2445 avail = first = NULL;
2446 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2447 if (reg->obj->pin_count)
2454 !reg->obj->last_fenced_ring ||
2455 reg->obj->last_fenced_ring == pipelined) {
2468 * i915_gem_object_get_fence - set up a fence reg for an object
2469 * @obj: object to map through a fence reg
2470 * @pipelined: ring on which to queue the change, or NULL for CPU access
2471 * @interruptible: must we wait uninterruptibly for the register to retire?
2473 * When mapping objects through the GTT, userspace wants to be able to write
2474 * to them without having to worry about swizzling if the object is tiled.
2476 * This function walks the fence regs looking for a free one for @obj,
2477 * stealing one if it can't find any.
2479 * It then sets up the reg based on the object's properties: address, pitch
2480 * and tiling format.
2483 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2484 struct intel_ring_buffer *pipelined,
2487 struct drm_device *dev = obj->base.dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct drm_i915_fence_reg *reg;
2492 /* XXX disable pipelining. There are bugs. Shocking. */
2495 /* Just update our place in the LRU if our fence is getting reused. */
2496 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2497 reg = &dev_priv->fence_regs[obj->fence_reg];
2498 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2500 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2504 if (reg->setup_seqno) {
2505 if (!ring_passed_seqno(obj->last_fenced_ring,
2506 reg->setup_seqno)) {
2507 ret = i915_do_wait_request(obj->base.dev,
2510 obj->last_fenced_ring);
2515 reg->setup_seqno = 0;
2517 } else if (obj->last_fenced_ring &&
2518 obj->last_fenced_ring != pipelined) {
2519 ret = i915_gem_object_flush_fence(obj,
2524 } else if (obj->tiling_changed) {
2525 if (obj->fenced_gpu_access) {
2526 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2527 i915_gem_flush_ring(obj->base.dev, obj->ring,
2528 0, obj->base.write_domain);
2530 obj->fenced_gpu_access = false;
2534 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2536 BUG_ON(!pipelined && reg->setup_seqno);
2538 if (obj->tiling_changed) {
2541 i915_gem_next_request_seqno(dev, pipelined);
2542 obj->last_fenced_seqno = reg->setup_seqno;
2543 obj->last_fenced_ring = pipelined;
2551 reg = i915_find_fence_reg(dev, pipelined);
2555 ret = i915_gem_object_flush_fence(obj, pipelined, interruptible);
2560 struct drm_i915_gem_object *old = reg->obj;
2562 drm_gem_object_reference(&old->base);
2564 if (old->tiling_mode)
2565 i915_gem_release_mmap(old);
2567 ret = i915_gem_object_flush_fence(old,
2571 drm_gem_object_unreference(&old->base);
2575 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2578 old->fence_reg = I915_FENCE_REG_NONE;
2579 old->last_fenced_ring = pipelined;
2580 old->last_fenced_seqno =
2581 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2583 drm_gem_object_unreference(&old->base);
2584 } else if (obj->last_fenced_seqno == 0)
2588 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2589 obj->fence_reg = reg - dev_priv->fence_regs;
2590 obj->last_fenced_ring = pipelined;
2593 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2594 obj->last_fenced_seqno = reg->setup_seqno;
2597 obj->tiling_changed = false;
2598 switch (INTEL_INFO(dev)->gen) {
2600 ret = sandybridge_write_fence_reg(obj, pipelined);
2604 ret = i965_write_fence_reg(obj, pipelined);
2607 ret = i915_write_fence_reg(obj, pipelined);
2610 ret = i830_write_fence_reg(obj, pipelined);
2618 * i915_gem_clear_fence_reg - clear out fence register info
2619 * @obj: object to clear
2621 * Zeroes out the fence register itself and clears out the associated
2622 * data structures in dev_priv and obj.
2625 i915_gem_clear_fence_reg(struct drm_device *dev,
2626 struct drm_i915_fence_reg *reg)
2628 drm_i915_private_t *dev_priv = dev->dev_private;
2629 uint32_t fence_reg = reg - dev_priv->fence_regs;
2631 switch (INTEL_INFO(dev)->gen) {
2633 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2637 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2641 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2644 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2646 I915_WRITE(fence_reg, 0);
2650 list_del_init(®->lru_list);
2652 reg->setup_seqno = 0;
2656 * Finds free space in the GTT aperture and binds the object there.
2659 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2661 bool map_and_fenceable)
2663 struct drm_device *dev = obj->base.dev;
2664 drm_i915_private_t *dev_priv = dev->dev_private;
2665 struct drm_mm_node *free_space;
2666 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2667 u32 size, fence_size, fence_alignment, unfenced_alignment;
2668 bool mappable, fenceable;
2671 if (obj->madv != I915_MADV_WILLNEED) {
2672 DRM_ERROR("Attempting to bind a purgeable object\n");
2676 fence_size = i915_gem_get_gtt_size(obj);
2677 fence_alignment = i915_gem_get_gtt_alignment(obj);
2678 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2681 alignment = map_and_fenceable ? fence_alignment :
2683 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2684 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2688 size = map_and_fenceable ? fence_size : obj->base.size;
2690 /* If the object is bigger than the entire aperture, reject it early
2691 * before evicting everything in a vain attempt to find space.
2693 if (obj->base.size >
2694 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2695 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2700 if (map_and_fenceable)
2702 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2704 dev_priv->mm.gtt_mappable_end,
2707 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2708 size, alignment, 0);
2710 if (free_space != NULL) {
2711 if (map_and_fenceable)
2713 drm_mm_get_block_range_generic(free_space,
2715 dev_priv->mm.gtt_mappable_end,
2719 drm_mm_get_block(free_space, size, alignment);
2721 if (obj->gtt_space == NULL) {
2722 /* If the gtt is empty and we're still having trouble
2723 * fitting our object in, we're out of memory.
2725 ret = i915_gem_evict_something(dev, size, alignment,
2733 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2735 drm_mm_put_block(obj->gtt_space);
2736 obj->gtt_space = NULL;
2738 if (ret == -ENOMEM) {
2739 /* first try to clear up some space from the GTT */
2740 ret = i915_gem_evict_something(dev, size,
2744 /* now try to shrink everyone else */
2759 ret = i915_gem_gtt_bind_object(obj);
2761 i915_gem_object_put_pages_gtt(obj);
2762 drm_mm_put_block(obj->gtt_space);
2763 obj->gtt_space = NULL;
2765 ret = i915_gem_evict_something(dev, size,
2766 alignment, map_and_fenceable);
2773 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2774 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2776 /* Assert that the object is not currently in any GPU domain. As it
2777 * wasn't in the GTT, there shouldn't be any way it could have been in
2780 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2781 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2783 obj->gtt_offset = obj->gtt_space->start;
2786 obj->gtt_space->size == fence_size &&
2787 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2790 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2792 obj->map_and_fenceable = mappable && fenceable;
2794 trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable);
2799 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2801 /* If we don't have a page list set up, then we're not pinned
2802 * to GPU, and we can ignore the cache flush because it'll happen
2803 * again at bind time.
2805 if (obj->pages == NULL)
2808 trace_i915_gem_object_clflush(obj);
2810 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2813 /** Flushes any GPU write domain for the object if it's dirty. */
2815 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2817 struct drm_device *dev = obj->base.dev;
2819 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2822 /* Queue the GPU write cache flushing we need. */
2823 i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
2824 BUG_ON(obj->base.write_domain);
2827 /** Flushes the GTT write domain for the object if it's dirty. */
2829 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2831 uint32_t old_write_domain;
2833 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2836 /* No actual flushing is required for the GTT write domain. Writes
2837 * to it immediately go to main memory as far as we know, so there's
2838 * no chipset flush. It also doesn't land in render cache.
2840 i915_gem_release_mmap(obj);
2842 old_write_domain = obj->base.write_domain;
2843 obj->base.write_domain = 0;
2845 trace_i915_gem_object_change_domain(obj,
2846 obj->base.read_domains,
2850 /** Flushes the CPU write domain for the object if it's dirty. */
2852 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2854 uint32_t old_write_domain;
2856 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2859 i915_gem_clflush_object(obj);
2860 intel_gtt_chipset_flush();
2861 old_write_domain = obj->base.write_domain;
2862 obj->base.write_domain = 0;
2864 trace_i915_gem_object_change_domain(obj,
2865 obj->base.read_domains,
2870 * Moves a single object to the GTT read, and possibly write domain.
2872 * This function returns when the move is complete, including waiting on
2876 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2878 uint32_t old_write_domain, old_read_domains;
2881 /* Not valid to be called on unbound objects. */
2882 if (obj->gtt_space == NULL)
2885 i915_gem_object_flush_gpu_write_domain(obj);
2886 if (obj->pending_gpu_write || write) {
2887 ret = i915_gem_object_wait_rendering(obj, true);
2892 i915_gem_object_flush_cpu_write_domain(obj);
2894 old_write_domain = obj->base.write_domain;
2895 old_read_domains = obj->base.read_domains;
2897 /* It should now be out of any other write domains, and we can update
2898 * the domain values for our changes.
2900 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2901 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2903 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2904 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2908 trace_i915_gem_object_change_domain(obj,
2916 * Prepare buffer for display plane. Use uninterruptible for possible flush
2917 * wait, as in modesetting process we're not supposed to be interrupted.
2920 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
2921 struct intel_ring_buffer *pipelined)
2923 uint32_t old_read_domains;
2926 /* Not valid to be called on unbound objects. */
2927 if (obj->gtt_space == NULL)
2930 i915_gem_object_flush_gpu_write_domain(obj);
2932 /* Currently, we are always called from an non-interruptible context. */
2933 if (pipelined != obj->ring) {
2934 ret = i915_gem_object_wait_rendering(obj, false);
2939 i915_gem_object_flush_cpu_write_domain(obj);
2941 old_read_domains = obj->base.read_domains;
2942 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2944 trace_i915_gem_object_change_domain(obj,
2946 obj->base.write_domain);
2952 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
2958 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2959 i915_gem_flush_ring(obj->base.dev, obj->ring,
2960 0, obj->base.write_domain);
2962 return i915_gem_object_wait_rendering(obj, interruptible);
2966 * Moves a single object to the CPU read, and possibly write domain.
2968 * This function returns when the move is complete, including waiting on
2972 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2974 uint32_t old_write_domain, old_read_domains;
2977 i915_gem_object_flush_gpu_write_domain(obj);
2978 ret = i915_gem_object_wait_rendering(obj, true);
2982 i915_gem_object_flush_gtt_write_domain(obj);
2984 /* If we have a partially-valid cache of the object in the CPU,
2985 * finish invalidating it and free the per-page flags.
2987 i915_gem_object_set_to_full_cpu_read_domain(obj);
2989 old_write_domain = obj->base.write_domain;
2990 old_read_domains = obj->base.read_domains;
2992 /* Flush the CPU cache if it's still invalid. */
2993 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2994 i915_gem_clflush_object(obj);
2996 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2999 /* It should now be out of any other write domains, and we can update
3000 * the domain values for our changes.
3002 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3004 /* If we're writing through the CPU, then the GPU read domains will
3005 * need to be invalidated at next use.
3008 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3009 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3012 trace_i915_gem_object_change_domain(obj,
3020 * Moves the object from a partially CPU read to a full one.
3022 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3023 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3026 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3028 if (!obj->page_cpu_valid)
3031 /* If we're partially in the CPU read domain, finish moving it in.
3033 if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3036 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3037 if (obj->page_cpu_valid[i])
3039 drm_clflush_pages(obj->pages + i, 1);
3043 /* Free the page_cpu_valid mappings which are now stale, whether
3044 * or not we've got I915_GEM_DOMAIN_CPU.
3046 kfree(obj->page_cpu_valid);
3047 obj->page_cpu_valid = NULL;
3051 * Set the CPU read domain on a range of the object.
3053 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3054 * not entirely valid. The page_cpu_valid member of the object flags which
3055 * pages have been flushed, and will be respected by
3056 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3057 * of the whole object.
3059 * This function returns when the move is complete, including waiting on
3063 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3064 uint64_t offset, uint64_t size)
3066 uint32_t old_read_domains;
3069 if (offset == 0 && size == obj->base.size)
3070 return i915_gem_object_set_to_cpu_domain(obj, 0);
3072 i915_gem_object_flush_gpu_write_domain(obj);
3073 ret = i915_gem_object_wait_rendering(obj, true);
3077 i915_gem_object_flush_gtt_write_domain(obj);
3079 /* If we're already fully in the CPU read domain, we're done. */
3080 if (obj->page_cpu_valid == NULL &&
3081 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3084 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3085 * newly adding I915_GEM_DOMAIN_CPU
3087 if (obj->page_cpu_valid == NULL) {
3088 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3090 if (obj->page_cpu_valid == NULL)
3092 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3093 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3095 /* Flush the cache on any pages that are still invalid from the CPU's
3098 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3100 if (obj->page_cpu_valid[i])
3103 drm_clflush_pages(obj->pages + i, 1);
3105 obj->page_cpu_valid[i] = 1;
3108 /* It should now be out of any other write domains, and we can update
3109 * the domain values for our changes.
3111 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3113 old_read_domains = obj->base.read_domains;
3114 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3116 trace_i915_gem_object_change_domain(obj,
3118 obj->base.write_domain);
3123 /* Throttle our rendering by waiting until the ring has completed our requests
3124 * emitted over 20 msec ago.
3126 * Note that if we were to use the current jiffies each time around the loop,
3127 * we wouldn't escape the function with any frames outstanding if the time to
3128 * render a frame was over 20ms.
3130 * This should get us reasonable parallelism between CPU and GPU but also
3131 * relatively low latency when blocking on a particular request to finish.
3134 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3136 struct drm_i915_private *dev_priv = dev->dev_private;
3137 struct drm_i915_file_private *file_priv = file->driver_priv;
3138 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3139 struct drm_i915_gem_request *request;
3140 struct intel_ring_buffer *ring = NULL;
3144 spin_lock(&file_priv->mm.lock);
3145 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3146 if (time_after_eq(request->emitted_jiffies, recent_enough))
3149 ring = request->ring;
3150 seqno = request->seqno;
3152 spin_unlock(&file_priv->mm.lock);
3158 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3159 /* And wait for the seqno passing without holding any locks and
3160 * causing extra latency for others. This is safe as the irq
3161 * generation is designed to be run atomically and so is
3164 if (ring->irq_get(ring)) {
3165 ret = wait_event_interruptible(ring->irq_queue,
3166 i915_seqno_passed(ring->get_seqno(ring), seqno)
3167 || atomic_read(&dev_priv->mm.wedged));
3168 ring->irq_put(ring);
3170 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3176 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3182 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3184 bool map_and_fenceable)
3186 struct drm_device *dev = obj->base.dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3190 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3191 WARN_ON(i915_verify_lists(dev));
3193 if (obj->gtt_space != NULL) {
3194 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3195 (map_and_fenceable && !obj->map_and_fenceable)) {
3196 WARN(obj->pin_count,
3197 "bo is already pinned with incorrect alignment:"
3198 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3199 " obj->map_and_fenceable=%d\n",
3200 obj->gtt_offset, alignment,
3202 obj->map_and_fenceable);
3203 ret = i915_gem_object_unbind(obj);
3209 if (obj->gtt_space == NULL) {
3210 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3216 if (obj->pin_count++ == 0) {
3218 list_move_tail(&obj->mm_list,
3219 &dev_priv->mm.pinned_list);
3221 obj->pin_mappable |= map_and_fenceable;
3223 WARN_ON(i915_verify_lists(dev));
3228 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3230 struct drm_device *dev = obj->base.dev;
3231 drm_i915_private_t *dev_priv = dev->dev_private;
3233 WARN_ON(i915_verify_lists(dev));
3234 BUG_ON(obj->pin_count == 0);
3235 BUG_ON(obj->gtt_space == NULL);
3237 if (--obj->pin_count == 0) {
3239 list_move_tail(&obj->mm_list,
3240 &dev_priv->mm.inactive_list);
3241 obj->pin_mappable = false;
3243 WARN_ON(i915_verify_lists(dev));
3247 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file)
3250 struct drm_i915_gem_pin *args = data;
3251 struct drm_i915_gem_object *obj;
3254 ret = i915_mutex_lock_interruptible(dev);
3258 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3264 if (obj->madv != I915_MADV_WILLNEED) {
3265 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3270 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3271 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3277 obj->user_pin_count++;
3278 obj->pin_filp = file;
3279 if (obj->user_pin_count == 1) {
3280 ret = i915_gem_object_pin(obj, args->alignment, true);
3285 /* XXX - flush the CPU caches for pinned objects
3286 * as the X server doesn't manage domains yet
3288 i915_gem_object_flush_cpu_write_domain(obj);
3289 args->offset = obj->gtt_offset;
3291 drm_gem_object_unreference(&obj->base);
3293 mutex_unlock(&dev->struct_mutex);
3298 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3299 struct drm_file *file)
3301 struct drm_i915_gem_pin *args = data;
3302 struct drm_i915_gem_object *obj;
3305 ret = i915_mutex_lock_interruptible(dev);
3309 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3315 if (obj->pin_filp != file) {
3316 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3321 obj->user_pin_count--;
3322 if (obj->user_pin_count == 0) {
3323 obj->pin_filp = NULL;
3324 i915_gem_object_unpin(obj);
3328 drm_gem_object_unreference(&obj->base);
3330 mutex_unlock(&dev->struct_mutex);
3335 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3336 struct drm_file *file)
3338 struct drm_i915_gem_busy *args = data;
3339 struct drm_i915_gem_object *obj;
3342 ret = i915_mutex_lock_interruptible(dev);
3346 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3352 /* Count all active objects as busy, even if they are currently not used
3353 * by the gpu. Users of this interface expect objects to eventually
3354 * become non-busy without any further actions, therefore emit any
3355 * necessary flushes here.
3357 args->busy = obj->active;
3359 /* Unconditionally flush objects, even when the gpu still uses this
3360 * object. Userspace calling this function indicates that it wants to
3361 * use this buffer rather sooner than later, so issuing the required
3362 * flush earlier is beneficial.
3364 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3365 i915_gem_flush_ring(dev, obj->ring,
3366 0, obj->base.write_domain);
3367 } else if (obj->ring->outstanding_lazy_request ==
3368 obj->last_rendering_seqno) {
3369 struct drm_i915_gem_request *request;
3371 /* This ring is not being cleared by active usage,
3372 * so emit a request to do so.
3374 request = kzalloc(sizeof(*request), GFP_KERNEL);
3376 ret = i915_add_request(dev,
3383 /* Update the active list for the hardware's current position.
3384 * Otherwise this only updates on a delayed timer or when irqs
3385 * are actually unmasked, and our working set ends up being
3386 * larger than required.
3388 i915_gem_retire_requests_ring(dev, obj->ring);
3390 args->busy = obj->active;
3393 drm_gem_object_unreference(&obj->base);
3395 mutex_unlock(&dev->struct_mutex);
3400 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3401 struct drm_file *file_priv)
3403 return i915_gem_ring_throttle(dev, file_priv);
3407 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3408 struct drm_file *file_priv)
3410 struct drm_i915_gem_madvise *args = data;
3411 struct drm_i915_gem_object *obj;
3414 switch (args->madv) {
3415 case I915_MADV_DONTNEED:
3416 case I915_MADV_WILLNEED:
3422 ret = i915_mutex_lock_interruptible(dev);
3426 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3432 if (obj->pin_count) {
3437 if (obj->madv != __I915_MADV_PURGED)
3438 obj->madv = args->madv;
3440 /* if the object is no longer bound, discard its backing storage */
3441 if (i915_gem_object_is_purgeable(obj) &&
3442 obj->gtt_space == NULL)
3443 i915_gem_object_truncate(obj);
3445 args->retained = obj->madv != __I915_MADV_PURGED;
3448 drm_gem_object_unreference(&obj->base);
3450 mutex_unlock(&dev->struct_mutex);
3454 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3457 struct drm_i915_private *dev_priv = dev->dev_private;
3458 struct drm_i915_gem_object *obj;
3460 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3464 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3469 i915_gem_info_add_obj(dev_priv, size);
3471 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3472 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3474 obj->agp_type = AGP_USER_MEMORY;
3475 obj->base.driver_private = NULL;
3476 obj->fence_reg = I915_FENCE_REG_NONE;
3477 INIT_LIST_HEAD(&obj->mm_list);
3478 INIT_LIST_HEAD(&obj->gtt_list);
3479 INIT_LIST_HEAD(&obj->ring_list);
3480 INIT_LIST_HEAD(&obj->exec_list);
3481 INIT_LIST_HEAD(&obj->gpu_write_list);
3482 obj->madv = I915_MADV_WILLNEED;
3483 /* Avoid an unnecessary call to unbind on the first bind. */
3484 obj->map_and_fenceable = true;
3489 int i915_gem_init_object(struct drm_gem_object *obj)
3496 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3498 struct drm_device *dev = obj->base.dev;
3499 drm_i915_private_t *dev_priv = dev->dev_private;
3502 ret = i915_gem_object_unbind(obj);
3503 if (ret == -ERESTARTSYS) {
3504 list_move(&obj->mm_list,
3505 &dev_priv->mm.deferred_free_list);
3509 if (obj->base.map_list.map)
3510 i915_gem_free_mmap_offset(obj);
3512 drm_gem_object_release(&obj->base);
3513 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3515 kfree(obj->page_cpu_valid);
3520 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3522 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3523 struct drm_device *dev = obj->base.dev;
3525 trace_i915_gem_object_destroy(obj);
3527 while (obj->pin_count > 0)
3528 i915_gem_object_unpin(obj);
3531 i915_gem_detach_phys_object(dev, obj);
3533 i915_gem_free_object_tail(obj);
3537 i915_gem_idle(struct drm_device *dev)
3539 drm_i915_private_t *dev_priv = dev->dev_private;
3542 mutex_lock(&dev->struct_mutex);
3544 if (dev_priv->mm.suspended) {
3545 mutex_unlock(&dev->struct_mutex);
3549 ret = i915_gpu_idle(dev);
3551 mutex_unlock(&dev->struct_mutex);
3555 /* Under UMS, be paranoid and evict. */
3556 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3557 ret = i915_gem_evict_inactive(dev, false);
3559 mutex_unlock(&dev->struct_mutex);
3564 i915_gem_reset_fences(dev);
3566 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3567 * We need to replace this with a semaphore, or something.
3568 * And not confound mm.suspended!
3570 dev_priv->mm.suspended = 1;
3571 del_timer_sync(&dev_priv->hangcheck_timer);
3573 i915_kernel_lost_context(dev);
3574 i915_gem_cleanup_ringbuffer(dev);
3576 mutex_unlock(&dev->struct_mutex);
3578 /* Cancel the retire work handler, which should be idle now. */
3579 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3585 i915_gem_init_ringbuffer(struct drm_device *dev)
3587 drm_i915_private_t *dev_priv = dev->dev_private;
3590 ret = intel_init_render_ring_buffer(dev);
3595 ret = intel_init_bsd_ring_buffer(dev);
3597 goto cleanup_render_ring;
3601 ret = intel_init_blt_ring_buffer(dev);
3603 goto cleanup_bsd_ring;
3606 dev_priv->next_seqno = 1;
3611 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3612 cleanup_render_ring:
3613 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3618 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3620 drm_i915_private_t *dev_priv = dev->dev_private;
3623 for (i = 0; i < I915_NUM_RINGS; i++)
3624 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3628 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3629 struct drm_file *file_priv)
3631 drm_i915_private_t *dev_priv = dev->dev_private;
3634 if (drm_core_check_feature(dev, DRIVER_MODESET))
3637 if (atomic_read(&dev_priv->mm.wedged)) {
3638 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3639 atomic_set(&dev_priv->mm.wedged, 0);
3642 mutex_lock(&dev->struct_mutex);
3643 dev_priv->mm.suspended = 0;
3645 ret = i915_gem_init_ringbuffer(dev);
3647 mutex_unlock(&dev->struct_mutex);
3651 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3652 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3653 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3654 for (i = 0; i < I915_NUM_RINGS; i++) {
3655 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3656 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3658 mutex_unlock(&dev->struct_mutex);
3660 ret = drm_irq_install(dev);
3662 goto cleanup_ringbuffer;
3667 mutex_lock(&dev->struct_mutex);
3668 i915_gem_cleanup_ringbuffer(dev);
3669 dev_priv->mm.suspended = 1;
3670 mutex_unlock(&dev->struct_mutex);
3676 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3677 struct drm_file *file_priv)
3679 if (drm_core_check_feature(dev, DRIVER_MODESET))
3682 drm_irq_uninstall(dev);
3683 return i915_gem_idle(dev);
3687 i915_gem_lastclose(struct drm_device *dev)
3691 if (drm_core_check_feature(dev, DRIVER_MODESET))
3694 ret = i915_gem_idle(dev);
3696 DRM_ERROR("failed to idle hardware: %d\n", ret);
3700 init_ring_lists(struct intel_ring_buffer *ring)
3702 INIT_LIST_HEAD(&ring->active_list);
3703 INIT_LIST_HEAD(&ring->request_list);
3704 INIT_LIST_HEAD(&ring->gpu_write_list);
3708 i915_gem_load(struct drm_device *dev)
3711 drm_i915_private_t *dev_priv = dev->dev_private;
3713 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3714 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3715 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3716 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3717 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3718 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3719 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3720 for (i = 0; i < I915_NUM_RINGS; i++)
3721 init_ring_lists(&dev_priv->ring[i]);
3722 for (i = 0; i < 16; i++)
3723 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3724 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3725 i915_gem_retire_work_handler);
3726 init_completion(&dev_priv->error_completion);
3728 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3730 u32 tmp = I915_READ(MI_ARB_STATE);
3731 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3732 /* arb state is a masked write, so set bit + bit in mask */
3733 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3734 I915_WRITE(MI_ARB_STATE, tmp);
3738 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3740 /* Old X drivers will take 0-2 for front, back, depth buffers */
3741 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3742 dev_priv->fence_reg_start = 3;
3744 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3745 dev_priv->num_fence_regs = 16;
3747 dev_priv->num_fence_regs = 8;
3749 /* Initialize fence registers to zero */
3750 switch (INTEL_INFO(dev)->gen) {
3752 for (i = 0; i < 16; i++)
3753 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3757 for (i = 0; i < 16; i++)
3758 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3761 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3762 for (i = 0; i < 8; i++)
3763 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3765 for (i = 0; i < 8; i++)
3766 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3769 i915_gem_detect_bit_6_swizzle(dev);
3770 init_waitqueue_head(&dev_priv->pending_flip_queue);
3772 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3773 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3774 register_shrinker(&dev_priv->mm.inactive_shrinker);
3778 * Create a physically contiguous memory object for this object
3779 * e.g. for cursor + overlay regs
3781 static int i915_gem_init_phys_object(struct drm_device *dev,
3782 int id, int size, int align)
3784 drm_i915_private_t *dev_priv = dev->dev_private;
3785 struct drm_i915_gem_phys_object *phys_obj;
3788 if (dev_priv->mm.phys_objs[id - 1] || !size)
3791 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3797 phys_obj->handle = drm_pci_alloc(dev, size, align);
3798 if (!phys_obj->handle) {
3803 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3806 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3814 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3816 drm_i915_private_t *dev_priv = dev->dev_private;
3817 struct drm_i915_gem_phys_object *phys_obj;
3819 if (!dev_priv->mm.phys_objs[id - 1])
3822 phys_obj = dev_priv->mm.phys_objs[id - 1];
3823 if (phys_obj->cur_obj) {
3824 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3828 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3830 drm_pci_free(dev, phys_obj->handle);
3832 dev_priv->mm.phys_objs[id - 1] = NULL;
3835 void i915_gem_free_all_phys_object(struct drm_device *dev)
3839 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3840 i915_gem_free_phys_object(dev, i);
3843 void i915_gem_detach_phys_object(struct drm_device *dev,
3844 struct drm_i915_gem_object *obj)
3846 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3853 vaddr = obj->phys_obj->handle->vaddr;
3855 page_count = obj->base.size / PAGE_SIZE;
3856 for (i = 0; i < page_count; i++) {
3857 struct page *page = read_cache_page_gfp(mapping, i,
3858 GFP_HIGHUSER | __GFP_RECLAIMABLE);
3859 if (!IS_ERR(page)) {
3860 char *dst = kmap_atomic(page);
3861 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3864 drm_clflush_pages(&page, 1);
3866 set_page_dirty(page);
3867 mark_page_accessed(page);
3868 page_cache_release(page);
3871 intel_gtt_chipset_flush();
3873 obj->phys_obj->cur_obj = NULL;
3874 obj->phys_obj = NULL;
3878 i915_gem_attach_phys_object(struct drm_device *dev,
3879 struct drm_i915_gem_object *obj,
3883 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3884 drm_i915_private_t *dev_priv = dev->dev_private;
3889 if (id > I915_MAX_PHYS_OBJECT)
3892 if (obj->phys_obj) {
3893 if (obj->phys_obj->id == id)
3895 i915_gem_detach_phys_object(dev, obj);
3898 /* create a new object */
3899 if (!dev_priv->mm.phys_objs[id - 1]) {
3900 ret = i915_gem_init_phys_object(dev, id,
3901 obj->base.size, align);
3903 DRM_ERROR("failed to init phys object %d size: %zu\n",
3904 id, obj->base.size);
3909 /* bind to the object */
3910 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3911 obj->phys_obj->cur_obj = obj;
3913 page_count = obj->base.size / PAGE_SIZE;
3915 for (i = 0; i < page_count; i++) {
3919 page = read_cache_page_gfp(mapping, i,
3920 GFP_HIGHUSER | __GFP_RECLAIMABLE);
3922 return PTR_ERR(page);
3924 src = kmap_atomic(page);
3925 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3926 memcpy(dst, src, PAGE_SIZE);
3929 mark_page_accessed(page);
3930 page_cache_release(page);
3937 i915_gem_phys_pwrite(struct drm_device *dev,
3938 struct drm_i915_gem_object *obj,
3939 struct drm_i915_gem_pwrite *args,
3940 struct drm_file *file_priv)
3942 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3943 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3945 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3946 unsigned long unwritten;
3948 /* The physical object once assigned is fixed for the lifetime
3949 * of the obj, so we can safely drop the lock and continue
3952 mutex_unlock(&dev->struct_mutex);
3953 unwritten = copy_from_user(vaddr, user_data, args->size);
3954 mutex_lock(&dev->struct_mutex);
3959 intel_gtt_chipset_flush();
3963 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3965 struct drm_i915_file_private *file_priv = file->driver_priv;
3967 /* Clean up our request list when the client is going away, so that
3968 * later retire_requests won't dereference our soon-to-be-gone
3971 spin_lock(&file_priv->mm.lock);
3972 while (!list_empty(&file_priv->mm.request_list)) {
3973 struct drm_i915_gem_request *request;
3975 request = list_first_entry(&file_priv->mm.request_list,
3976 struct drm_i915_gem_request,
3978 list_del(&request->client_list);
3979 request->file_priv = NULL;
3981 spin_unlock(&file_priv->mm.lock);
3985 i915_gpu_is_active(struct drm_device *dev)
3987 drm_i915_private_t *dev_priv = dev->dev_private;
3990 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3991 list_empty(&dev_priv->mm.active_list);
3993 return !lists_empty;
3997 i915_gem_inactive_shrink(struct shrinker *shrinker,
4001 struct drm_i915_private *dev_priv =
4002 container_of(shrinker,
4003 struct drm_i915_private,
4004 mm.inactive_shrinker);
4005 struct drm_device *dev = dev_priv->dev;
4006 struct drm_i915_gem_object *obj, *next;
4009 if (!mutex_trylock(&dev->struct_mutex))
4012 /* "fast-path" to count number of available objects */
4013 if (nr_to_scan == 0) {
4015 list_for_each_entry(obj,
4016 &dev_priv->mm.inactive_list,
4019 mutex_unlock(&dev->struct_mutex);
4020 return cnt / 100 * sysctl_vfs_cache_pressure;
4024 /* first scan for clean buffers */
4025 i915_gem_retire_requests(dev);
4027 list_for_each_entry_safe(obj, next,
4028 &dev_priv->mm.inactive_list,
4030 if (i915_gem_object_is_purgeable(obj)) {
4031 if (i915_gem_object_unbind(obj) == 0 &&
4037 /* second pass, evict/count anything still on the inactive list */
4039 list_for_each_entry_safe(obj, next,
4040 &dev_priv->mm.inactive_list,
4043 i915_gem_object_unbind(obj) == 0)
4049 if (nr_to_scan && i915_gpu_is_active(dev)) {
4051 * We are desperate for pages, so as a last resort, wait
4052 * for the GPU to finish and discard whatever we can.
4053 * This has a dramatic impact to reduce the number of
4054 * OOM-killer events whilst running the GPU aggressively.
4056 if (i915_gpu_idle(dev) == 0)
4059 mutex_unlock(&dev->struct_mutex);
4060 return cnt / 100 * sysctl_vfs_cache_pressure;