drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/shmem_fs.h>
  35 #include <linux/slab.h>
  36 #include <linux/swap.h>
  37 #include <linux/pci.h>
  38
  39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  42 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  43                                                           bool write);
  44 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  45                                                                   uint64_t offset,
  46                                                                   uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  48 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  49                                                     unsigned alignment,
  50                                                     bool map_and_fenceable);
  51 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  52                                      struct drm_i915_fence_reg *reg);
  53 static int i915_gem_phys_pwrite(struct drm_device *dev,
  54                                 struct drm_i915_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file);
  57 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  58
  59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  60                                     struct shrink_control *sc);
  61
  62 /* some bookkeeping */
  63 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  64                                   size_t size)
  65 {
  66         dev_priv->mm.object_count++;
  67         dev_priv->mm.object_memory += size;
  68 }
  69
  70 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  71                                      size_t size)
  72 {
  73         dev_priv->mm.object_count--;
  74         dev_priv->mm.object_memory -= size;
  75 }
  76
  77 static int
  78 i915_gem_wait_for_error(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct completion *x = &dev_priv->error_completion;
  82         unsigned long flags;
  83         int ret;
  84
  85         if (!atomic_read(&dev_priv->mm.wedged))
  86                 return 0;
  87
  88         ret = wait_for_completion_interruptible(x);
  89         if (ret)
  90                 return ret;
  91
  92         if (atomic_read(&dev_priv->mm.wedged)) {
  93                 /* GPU is hung, bump the completion count to account for
  94                  * the token we just consumed so that we never hit zero and
  95                  * end up waiting upon a subsequent completion event that
  96                  * will never happen.
  97                  */
  98                 spin_lock_irqsave(&x->wait.lock, flags);
  99                 x->done++;
 100                 spin_unlock_irqrestore(&x->wait.lock, flags);
 101         }
 102         return 0;
 103 }
 104
 105 int i915_mutex_lock_interruptible(struct drm_device *dev)
 106 {
 107         int ret;
 108
 109         ret = i915_gem_wait_for_error(dev);
 110         if (ret)
 111                 return ret;
 112
 113         ret = mutex_lock_interruptible(&dev->struct_mutex);
 114         if (ret)
 115                 return ret;
 116
 117         WARN_ON(i915_verify_lists(dev));
 118         return 0;
 119 }
 120
 121 static inline bool
 122 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 123 {
 124         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 125 }
 126
 127 void i915_gem_do_init(struct drm_device *dev,
 128                       unsigned long start,
 129                       unsigned long mappable_end,
 130                       unsigned long end)
 131 {
 132         drm_i915_private_t *dev_priv = dev->dev_private;
 133
 134         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 135
 136         dev_priv->mm.gtt_start = start;
 137         dev_priv->mm.gtt_mappable_end = mappable_end;
 138         dev_priv->mm.gtt_end = end;
 139         dev_priv->mm.gtt_total = end - start;
 140         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 141
 142         /* Take over this portion of the GTT */
 143         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 144 }
 145
 146 int
 147 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 148                     struct drm_file *file)
 149 {
 150         struct drm_i915_gem_init *args = data;
 151
 152         if (args->gtt_start >= args->gtt_end ||
 153             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 154                 return -EINVAL;
 155
 156         mutex_lock(&dev->struct_mutex);
 157         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 158         mutex_unlock(&dev->struct_mutex);
 159
 160         return 0;
 161 }
 162
 163 int
 164 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 165                             struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_get_aperture *args = data;
 169         struct drm_i915_gem_object *obj;
 170         size_t pinned;
 171
 172         if (!(dev->driver->driver_features & DRIVER_GEM))
 173                 return -ENODEV;
 174
 175         pinned = 0;
 176         mutex_lock(&dev->struct_mutex);
 177         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 178                 pinned += obj->gtt_space->size;
 179         mutex_unlock(&dev->struct_mutex);
 180
 181         args->aper_size = dev_priv->mm.gtt_total;
 182         args->aper_available_size = args->aper_size -pinned;
 183
 184         return 0;
 185 }
 186
 187 static int
 188 i915_gem_create(struct drm_file *file,
 189                 struct drm_device *dev,
 190                 uint64_t size,
 191                 uint32_t *handle_p)
 192 {
 193         struct drm_i915_gem_object *obj;
 194         int ret;
 195         u32 handle;
 196
 197         size = roundup(size, PAGE_SIZE);
 198
 199         /* Allocate the new object */
 200         obj = i915_gem_alloc_object(dev, size);
 201         if (obj == NULL)
 202                 return -ENOMEM;
 203
 204         ret = drm_gem_handle_create(file, &obj->base, &handle);
 205         if (ret) {
 206                 drm_gem_object_release(&obj->base);
 207                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 208                 kfree(obj);
 209                 return ret;
 210         }
 211
 212         /* drop reference from allocate - handle holds it now */
 213         drm_gem_object_unreference(&obj->base);
 214         trace_i915_gem_object_create(obj);
 215
 216         *handle_p = handle;
 217         return 0;
 218 }
 219
 220 int
 221 i915_gem_dumb_create(struct drm_file *file,
 222                      struct drm_device *dev,
 223                      struct drm_mode_create_dumb *args)
 224 {
 225         /* have to work out size/pitch and return them */
 226         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 227         args->size = args->pitch * args->height;
 228         return i915_gem_create(file, dev,
 229                                args->size, &args->handle);
 230 }
 231
 232 int i915_gem_dumb_destroy(struct drm_file *file,
 233                           struct drm_device *dev,
 234                           uint32_t handle)
 235 {
 236         return drm_gem_handle_delete(file, handle);
 237 }
 238
 239 /**
 240  * Creates a new mm object and returns a handle to it.
 241  */
 242 int
 243 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 244                       struct drm_file *file)
 245 {
 246         struct drm_i915_gem_create *args = data;
 247         return i915_gem_create(file, dev,
 248                                args->size, &args->handle);
 249 }
 250
 251 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 252 {
 253         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 254
 255         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 256                 obj->tiling_mode != I915_TILING_NONE;
 257 }
 258
 259 static inline void
 260 slow_shmem_copy(struct page *dst_page,
 261                 int dst_offset,
 262                 struct page *src_page,
 263                 int src_offset,
 264                 int length)
 265 {
 266         char *dst_vaddr, *src_vaddr;
 267
 268         dst_vaddr = kmap(dst_page);
 269         src_vaddr = kmap(src_page);
 270
 271         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 272
 273         kunmap(src_page);
 274         kunmap(dst_page);
 275 }
 276
 277 static inline void
 278 slow_shmem_bit17_copy(struct page *gpu_page,
 279                       int gpu_offset,
 280                       struct page *cpu_page,
 281                       int cpu_offset,
 282                       int length,
 283                       int is_read)
 284 {
 285         char *gpu_vaddr, *cpu_vaddr;
 286
 287         /* Use the unswizzled path if this page isn't affected. */
 288         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 289                 if (is_read)
 290                         return slow_shmem_copy(cpu_page, cpu_offset,
 291                                                gpu_page, gpu_offset, length);
 292                 else
 293                         return slow_shmem_copy(gpu_page, gpu_offset,
 294                                                cpu_page, cpu_offset, length);
 295         }
 296
 297         gpu_vaddr = kmap(gpu_page);
 298         cpu_vaddr = kmap(cpu_page);
 299
 300         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 301          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 302          */
 303         while (length > 0) {
 304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 305                 int this_length = min(cacheline_end - gpu_offset, length);
 306                 int swizzled_gpu_offset = gpu_offset ^ 64;
 307
 308                 if (is_read) {
 309                         memcpy(cpu_vaddr + cpu_offset,
 310                                gpu_vaddr + swizzled_gpu_offset,
 311                                this_length);
 312                 } else {
 313                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 314                                cpu_vaddr + cpu_offset,
 315                                this_length);
 316                 }
 317                 cpu_offset += this_length;
 318                 gpu_offset += this_length;
 319                 length -= this_length;
 320         }
 321
 322         kunmap(cpu_page);
 323         kunmap(gpu_page);
 324 }
 325
 326 /**
 327  * This is the fast shmem pread path, which attempts to copy_from_user directly
 328  * from the backing pages of the object to the user's address space.  On a
 329  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 330  */
 331 static int
 332 i915_gem_shmem_pread_fast(struct drm_device *dev,
 333                           struct drm_i915_gem_object *obj,
 334                           struct drm_i915_gem_pread *args,
 335                           struct drm_file *file)
 336 {
 337         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 338         ssize_t remain;
 339         loff_t offset;
 340         char __user *user_data;
 341         int page_offset, page_length;
 342
 343         user_data = (char __user *) (uintptr_t) args->data_ptr;
 344         remain = args->size;
 345
 346         offset = args->offset;
 347
 348         while (remain > 0) {
 349                 struct page *page;
 350                 char *vaddr;
 351                 int ret;
 352
 353                 /* Operation in this page
 354                  *
 355                  * page_offset = offset within page
 356                  * page_length = bytes to copy for this page
 357                  */
 358                 page_offset = offset_in_page(offset);
 359                 page_length = remain;
 360                 if ((page_offset + remain) > PAGE_SIZE)
 361                         page_length = PAGE_SIZE - page_offset;
 362
 363                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 364                 if (IS_ERR(page))
 365                         return PTR_ERR(page);
 366
 367                 vaddr = kmap_atomic(page);
 368                 ret = __copy_to_user_inatomic(user_data,
 369                                               vaddr + page_offset,
 370                                               page_length);
 371                 kunmap_atomic(vaddr);
 372
 373                 mark_page_accessed(page);
 374                 page_cache_release(page);
 375                 if (ret)
 376                         return -EFAULT;
 377
 378                 remain -= page_length;
 379                 user_data += page_length;
 380                 offset += page_length;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * This is the fallback shmem pread path, which allocates temporary storage
 388  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 389  * can copy out of the object's backing pages while holding the struct mutex
 390  * and not take page faults.
 391  */
 392 static int
 393 i915_gem_shmem_pread_slow(struct drm_device *dev,
 394                           struct drm_i915_gem_object *obj,
 395                           struct drm_i915_gem_pread *args,
 396                           struct drm_file *file)
 397 {
 398         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 399         struct mm_struct *mm = current->mm;
 400         struct page **user_pages;
 401         ssize_t remain;
 402         loff_t offset, pinned_pages, i;
 403         loff_t first_data_page, last_data_page, num_pages;
 404         int shmem_page_offset;
 405         int data_page_index, data_page_offset;
 406         int page_length;
 407         int ret;
 408         uint64_t data_ptr = args->data_ptr;
 409         int do_bit17_swizzling;
 410
 411         remain = args->size;
 412
 413         /* Pin the user pages containing the data.  We can't fault while
 414          * holding the struct mutex, yet we want to hold it while
 415          * dereferencing the user data.
 416          */
 417         first_data_page = data_ptr / PAGE_SIZE;
 418         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 419         num_pages = last_data_page - first_data_page + 1;
 420
 421         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 422         if (user_pages == NULL)
 423                 return -ENOMEM;
 424
 425         mutex_unlock(&dev->struct_mutex);
 426         down_read(&mm->mmap_sem);
 427         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 428                                       num_pages, 1, 0, user_pages, NULL);
 429         up_read(&mm->mmap_sem);
 430         mutex_lock(&dev->struct_mutex);
 431         if (pinned_pages < num_pages) {
 432                 ret = -EFAULT;
 433                 goto out;
 434         }
 435
 436         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 437                                                         args->offset,
 438                                                         args->size);
 439         if (ret)
 440                 goto out;
 441
 442         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 443
 444         offset = args->offset;
 445
 446         while (remain > 0) {
 447                 struct page *page;
 448
 449                 /* Operation in this page
 450                  *
 451                  * shmem_page_offset = offset within page in shmem file
 452                  * data_page_index = page number in get_user_pages return
 453                  * data_page_offset = offset with data_page_index page.
 454                  * page_length = bytes to copy for this page
 455                  */
 456                 shmem_page_offset = offset_in_page(offset);
 457                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 458                 data_page_offset = offset_in_page(data_ptr);
 459
 460                 page_length = remain;
 461                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 462                         page_length = PAGE_SIZE - shmem_page_offset;
 463                 if ((data_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - data_page_offset;
 465
 466                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 467                 if (IS_ERR(page)) {
 468                         ret = PTR_ERR(page);
 469                         goto out;
 470                 }
 471
 472                 if (do_bit17_swizzling) {
 473                         slow_shmem_bit17_copy(page,
 474                                               shmem_page_offset,
 475                                               user_pages[data_page_index],
 476                                               data_page_offset,
 477                                               page_length,
 478                                               1);
 479                 } else {
 480                         slow_shmem_copy(user_pages[data_page_index],
 481                                         data_page_offset,
 482                                         page,
 483                                         shmem_page_offset,
 484                                         page_length);
 485                 }
 486
 487                 mark_page_accessed(page);
 488                 page_cache_release(page);
 489
 490                 remain -= page_length;
 491                 data_ptr += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         for (i = 0; i < pinned_pages; i++) {
 497                 SetPageDirty(user_pages[i]);
 498                 mark_page_accessed(user_pages[i]);
 499                 page_cache_release(user_pages[i]);
 500         }
 501         drm_free_large(user_pages);
 502
 503         return ret;
 504 }
 505
 506 /**
 507  * Reads data from the object referenced by handle.
 508  *
 509  * On error, the contents of *data are undefined.
 510  */
 511 int
 512 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 513                      struct drm_file *file)
 514 {
 515         struct drm_i915_gem_pread *args = data;
 516         struct drm_i915_gem_object *obj;
 517         int ret = 0;
 518
 519         if (args->size == 0)
 520                 return 0;
 521
 522         if (!access_ok(VERIFY_WRITE,
 523                        (char __user *)(uintptr_t)args->data_ptr,
 524                        args->size))
 525                 return -EFAULT;
 526
 527         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 528                                        args->size);
 529         if (ret)
 530                 return -EFAULT;
 531
 532         ret = i915_mutex_lock_interruptible(dev);
 533         if (ret)
 534                 return ret;
 535
 536         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 537         if (&obj->base == NULL) {
 538                 ret = -ENOENT;
 539                 goto unlock;
 540         }
 541
 542         /* Bounds check source.  */
 543         if (args->offset > obj->base.size ||
 544             args->size > obj->base.size - args->offset) {
 545                 ret = -EINVAL;
 546                 goto out;
 547         }
 548
 549         trace_i915_gem_object_pread(obj, args->offset, args->size);
 550
 551         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 552                                                         args->offset,
 553                                                         args->size);
 554         if (ret)
 555                 goto out;
 556
 557         ret = -EFAULT;
 558         if (!i915_gem_object_needs_bit17_swizzle(obj))
 559                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 560         if (ret == -EFAULT)
 561                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 562
 563 out:
 564         drm_gem_object_unreference(&obj->base);
 565 unlock:
 566         mutex_unlock(&dev->struct_mutex);
 567         return ret;
 568 }
 569
 570 /* This is the fast write path which cannot handle
 571  * page faults in the source data
 572  */
 573
 574 static inline int
 575 fast_user_write(struct io_mapping *mapping,
 576                 loff_t page_base, int page_offset,
 577                 char __user *user_data,
 578                 int length)
 579 {
 580         char *vaddr_atomic;
 581         unsigned long unwritten;
 582
 583         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 584         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 585                                                       user_data, length);
 586         io_mapping_unmap_atomic(vaddr_atomic);
 587         return unwritten;
 588 }
 589
 590 /* Here's the write path which can sleep for
 591  * page faults
 592  */
 593
 594 static inline void
 595 slow_kernel_write(struct io_mapping *mapping,
 596                   loff_t gtt_base, int gtt_offset,
 597                   struct page *user_page, int user_offset,
 598                   int length)
 599 {
 600         char __iomem *dst_vaddr;
 601         char *src_vaddr;
 602
 603         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 604         src_vaddr = kmap(user_page);
 605
 606         memcpy_toio(dst_vaddr + gtt_offset,
 607                     src_vaddr + user_offset,
 608                     length);
 609
 610         kunmap(user_page);
 611         io_mapping_unmap(dst_vaddr);
 612 }
 613
 614 /**
 615  * This is the fast pwrite path, where we copy the data directly from the
 616  * user into the GTT, uncached.
 617  */
 618 static int
 619 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 620                          struct drm_i915_gem_object *obj,
 621                          struct drm_i915_gem_pwrite *args,
 622                          struct drm_file *file)
 623 {
 624         drm_i915_private_t *dev_priv = dev->dev_private;
 625         ssize_t remain;
 626         loff_t offset, page_base;
 627         char __user *user_data;
 628         int page_offset, page_length;
 629
 630         user_data = (char __user *) (uintptr_t) args->data_ptr;
 631         remain = args->size;
 632
 633         offset = obj->gtt_offset + args->offset;
 634
 635         while (remain > 0) {
 636                 /* Operation in this page
 637                  *
 638                  * page_base = page offset within aperture
 639                  * page_offset = offset within page
 640                  * page_length = bytes to copy for this page
 641                  */
 642                 page_base = offset & PAGE_MASK;
 643                 page_offset = offset_in_page(offset);
 644                 page_length = remain;
 645                 if ((page_offset + remain) > PAGE_SIZE)
 646                         page_length = PAGE_SIZE - page_offset;
 647
 648                 /* If we get a fault while copying data, then (presumably) our
 649                  * source page isn't available.  Return the error and we'll
 650                  * retry in the slow path.
 651                  */
 652                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 653                                     page_offset, user_data, page_length))
 654                         return -EFAULT;
 655
 656                 remain -= page_length;
 657                 user_data += page_length;
 658                 offset += page_length;
 659         }
 660
 661         return 0;
 662 }
 663
 664 /**
 665  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 666  * the memory and maps it using kmap_atomic for copying.
 667  *
 668  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 669  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 670  */
 671 static int
 672 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 673                          struct drm_i915_gem_object *obj,
 674                          struct drm_i915_gem_pwrite *args,
 675                          struct drm_file *file)
 676 {
 677         drm_i915_private_t *dev_priv = dev->dev_private;
 678         ssize_t remain;
 679         loff_t gtt_page_base, offset;
 680         loff_t first_data_page, last_data_page, num_pages;
 681         loff_t pinned_pages, i;
 682         struct page **user_pages;
 683         struct mm_struct *mm = current->mm;
 684         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 685         int ret;
 686         uint64_t data_ptr = args->data_ptr;
 687
 688         remain = args->size;
 689
 690         /* Pin the user pages containing the data.  We can't fault while
 691          * holding the struct mutex, and all of the pwrite implementations
 692          * want to hold it while dereferencing the user data.
 693          */
 694         first_data_page = data_ptr / PAGE_SIZE;
 695         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 696         num_pages = last_data_page - first_data_page + 1;
 697
 698         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 699         if (user_pages == NULL)
 700                 return -ENOMEM;
 701
 702         mutex_unlock(&dev->struct_mutex);
 703         down_read(&mm->mmap_sem);
 704         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 705                                       num_pages, 0, 0, user_pages, NULL);
 706         up_read(&mm->mmap_sem);
 707         mutex_lock(&dev->struct_mutex);
 708         if (pinned_pages < num_pages) {
 709                 ret = -EFAULT;
 710                 goto out_unpin_pages;
 711         }
 712
 713         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 714         if (ret)
 715                 goto out_unpin_pages;
 716
 717         ret = i915_gem_object_put_fence(obj);
 718         if (ret)
 719                 goto out_unpin_pages;
 720
 721         offset = obj->gtt_offset + args->offset;
 722
 723         while (remain > 0) {
 724                 /* Operation in this page
 725                  *
 726                  * gtt_page_base = page offset within aperture
 727                  * gtt_page_offset = offset within page in aperture
 728                  * data_page_index = page number in get_user_pages return
 729                  * data_page_offset = offset with data_page_index page.
 730                  * page_length = bytes to copy for this page
 731                  */
 732                 gtt_page_base = offset & PAGE_MASK;
 733                 gtt_page_offset = offset_in_page(offset);
 734                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 735                 data_page_offset = offset_in_page(data_ptr);
 736
 737                 page_length = remain;
 738                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 739                         page_length = PAGE_SIZE - gtt_page_offset;
 740                 if ((data_page_offset + page_length) > PAGE_SIZE)
 741                         page_length = PAGE_SIZE - data_page_offset;
 742
 743                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 744                                   gtt_page_base, gtt_page_offset,
 745                                   user_pages[data_page_index],
 746                                   data_page_offset,
 747                                   page_length);
 748
 749                 remain -= page_length;
 750                 offset += page_length;
 751                 data_ptr += page_length;
 752         }
 753
 754 out_unpin_pages:
 755         for (i = 0; i < pinned_pages; i++)
 756                 page_cache_release(user_pages[i]);
 757         drm_free_large(user_pages);
 758
 759         return ret;
 760 }
 761
 762 /**
 763  * This is the fast shmem pwrite path, which attempts to directly
 764  * copy_from_user into the kmapped pages backing the object.
 765  */
 766 static int
 767 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 768                            struct drm_i915_gem_object *obj,
 769                            struct drm_i915_gem_pwrite *args,
 770                            struct drm_file *file)
 771 {
 772         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 773         ssize_t remain;
 774         loff_t offset;
 775         char __user *user_data;
 776         int page_offset, page_length;
 777
 778         user_data = (char __user *) (uintptr_t) args->data_ptr;
 779         remain = args->size;
 780
 781         offset = args->offset;
 782         obj->dirty = 1;
 783
 784         while (remain > 0) {
 785                 struct page *page;
 786                 char *vaddr;
 787                 int ret;
 788
 789                 /* Operation in this page
 790                  *
 791                  * page_offset = offset within page
 792                  * page_length = bytes to copy for this page
 793                  */
 794                 page_offset = offset_in_page(offset);
 795                 page_length = remain;
 796                 if ((page_offset + remain) > PAGE_SIZE)
 797                         page_length = PAGE_SIZE - page_offset;
 798
 799                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 800                 if (IS_ERR(page))
 801                         return PTR_ERR(page);
 802
 803                 vaddr = kmap_atomic(page, KM_USER0);
 804                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 805                                                 user_data,
 806                                                 page_length);
 807                 kunmap_atomic(vaddr, KM_USER0);
 808
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811                 page_cache_release(page);
 812
 813                 /* If we get a fault while copying data, then (presumably) our
 814                  * source page isn't available.  Return the error and we'll
 815                  * retry in the slow path.
 816                  */
 817                 if (ret)
 818                         return -EFAULT;
 819
 820                 remain -= page_length;
 821                 user_data += page_length;
 822                 offset += page_length;
 823         }
 824
 825         return 0;
 826 }
 827
 828 /**
 829  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 830  * the memory and maps it using kmap_atomic for copying.
 831  *
 832  * This avoids taking mmap_sem for faulting on the user's address while the
 833  * struct_mutex is held.
 834  */
 835 static int
 836 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 837                            struct drm_i915_gem_object *obj,
 838                            struct drm_i915_gem_pwrite *args,
 839                            struct drm_file *file)
 840 {
 841         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 842         struct mm_struct *mm = current->mm;
 843         struct page **user_pages;
 844         ssize_t remain;
 845         loff_t offset, pinned_pages, i;
 846         loff_t first_data_page, last_data_page, num_pages;
 847         int shmem_page_offset;
 848         int data_page_index,  data_page_offset;
 849         int page_length;
 850         int ret;
 851         uint64_t data_ptr = args->data_ptr;
 852         int do_bit17_swizzling;
 853
 854         remain = args->size;
 855
 856         /* Pin the user pages containing the data.  We can't fault while
 857          * holding the struct mutex, and all of the pwrite implementations
 858          * want to hold it while dereferencing the user data.
 859          */
 860         first_data_page = data_ptr / PAGE_SIZE;
 861         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 862         num_pages = last_data_page - first_data_page + 1;
 863
 864         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 865         if (user_pages == NULL)
 866                 return -ENOMEM;
 867
 868         mutex_unlock(&dev->struct_mutex);
 869         down_read(&mm->mmap_sem);
 870         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 871                                       num_pages, 0, 0, user_pages, NULL);
 872         up_read(&mm->mmap_sem);
 873         mutex_lock(&dev->struct_mutex);
 874         if (pinned_pages < num_pages) {
 875                 ret = -EFAULT;
 876                 goto out;
 877         }
 878
 879         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 880         if (ret)
 881                 goto out;
 882
 883         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         offset = args->offset;
 886         obj->dirty = 1;
 887
 888         while (remain > 0) {
 889                 struct page *page;
 890
 891                 /* Operation in this page
 892                  *
 893                  * shmem_page_offset = offset within page in shmem file
 894                  * data_page_index = page number in get_user_pages return
 895                  * data_page_offset = offset with data_page_index page.
 896                  * page_length = bytes to copy for this page
 897                  */
 898                 shmem_page_offset = offset_in_page(offset);
 899                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 900                 data_page_offset = offset_in_page(data_ptr);
 901
 902                 page_length = remain;
 903                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 904                         page_length = PAGE_SIZE - shmem_page_offset;
 905                 if ((data_page_offset + page_length) > PAGE_SIZE)
 906                         page_length = PAGE_SIZE - data_page_offset;
 907
 908                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 909                 if (IS_ERR(page)) {
 910                         ret = PTR_ERR(page);
 911                         goto out;
 912                 }
 913
 914                 if (do_bit17_swizzling) {
 915                         slow_shmem_bit17_copy(page,
 916                                               shmem_page_offset,
 917                                               user_pages[data_page_index],
 918                                               data_page_offset,
 919                                               page_length,
 920                                               0);
 921                 } else {
 922                         slow_shmem_copy(page,
 923                                         shmem_page_offset,
 924                                         user_pages[data_page_index],
 925                                         data_page_offset,
 926                                         page_length);
 927                 }
 928
 929                 set_page_dirty(page);
 930                 mark_page_accessed(page);
 931                 page_cache_release(page);
 932
 933                 remain -= page_length;
 934                 data_ptr += page_length;
 935                 offset += page_length;
 936         }
 937
 938 out:
 939         for (i = 0; i < pinned_pages; i++)
 940                 page_cache_release(user_pages[i]);
 941         drm_free_large(user_pages);
 942
 943         return ret;
 944 }
 945
 946 /**
 947  * Writes data to the object referenced by handle.
 948  *
 949  * On error, the contents of the buffer that were to be modified are undefined.
 950  */
 951 int
 952 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 953                       struct drm_file *file)
 954 {
 955         struct drm_i915_gem_pwrite *args = data;
 956         struct drm_i915_gem_object *obj;
 957         int ret;
 958
 959         if (args->size == 0)
 960                 return 0;
 961
 962         if (!access_ok(VERIFY_READ,
 963                        (char __user *)(uintptr_t)args->data_ptr,
 964                        args->size))
 965                 return -EFAULT;
 966
 967         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 968                                       args->size);
 969         if (ret)
 970                 return -EFAULT;
 971
 972         ret = i915_mutex_lock_interruptible(dev);
 973         if (ret)
 974                 return ret;
 975
 976         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 977         if (&obj->base == NULL) {
 978                 ret = -ENOENT;
 979                 goto unlock;
 980         }
 981
 982         /* Bounds check destination. */
 983         if (args->offset > obj->base.size ||
 984             args->size > obj->base.size - args->offset) {
 985                 ret = -EINVAL;
 986                 goto out;
 987         }
 988
 989         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 990
 991         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 992          * it would end up going through the fenced access, and we'll get
 993          * different detiling behavior between reading and writing.
 994          * pread/pwrite currently are reading and writing from the CPU
 995          * perspective, requiring manual detiling by the client.
 996          */
 997         if (obj->phys_obj)
 998                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 999         else if (obj->gtt_space &&
1000                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1001                 ret = i915_gem_object_pin(obj, 0, true);
1002                 if (ret)
1003                         goto out;
1004
1005                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1006                 if (ret)
1007                         goto out_unpin;
1008
1009                 ret = i915_gem_object_put_fence(obj);
1010                 if (ret)
1011                         goto out_unpin;
1012
1013                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1014                 if (ret == -EFAULT)
1015                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1016
1017 out_unpin:
1018                 i915_gem_object_unpin(obj);
1019         } else {
1020                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1021                 if (ret)
1022                         goto out;
1023
1024                 ret = -EFAULT;
1025                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1027                 if (ret == -EFAULT)
1028                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1029         }
1030
1031 out:
1032         drm_gem_object_unreference(&obj->base);
1033 unlock:
1034         mutex_unlock(&dev->struct_mutex);
1035         return ret;
1036 }
1037
1038 /**
1039  * Called when user space prepares to use an object with the CPU, either
1040  * through the mmap ioctl's mapping or a GTT mapping.
1041  */
1042 int
1043 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1044                           struct drm_file *file)
1045 {
1046         struct drm_i915_gem_set_domain *args = data;
1047         struct drm_i915_gem_object *obj;
1048         uint32_t read_domains = args->read_domains;
1049         uint32_t write_domain = args->write_domain;
1050         int ret;
1051
1052         if (!(dev->driver->driver_features & DRIVER_GEM))
1053                 return -ENODEV;
1054
1055         /* Only handle setting domains to types used by the CPU. */
1056         if (write_domain & I915_GEM_GPU_DOMAINS)
1057                 return -EINVAL;
1058
1059         if (read_domains & I915_GEM_GPU_DOMAINS)
1060                 return -EINVAL;
1061
1062         /* Having something in the write domain implies it's in the read
1063          * domain, and only that read domain.  Enforce that in the request.
1064          */
1065         if (write_domain != 0 && read_domains != write_domain)
1066                 return -EINVAL;
1067
1068         ret = i915_mutex_lock_interruptible(dev);
1069         if (ret)
1070                 return ret;
1071
1072         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1073         if (&obj->base == NULL) {
1074                 ret = -ENOENT;
1075                 goto unlock;
1076         }
1077
1078         if (read_domains & I915_GEM_DOMAIN_GTT) {
1079                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1080
1081                 /* Silently promote "you're not bound, there was nothing to do"
1082                  * to success, since the client was just asking us to
1083                  * make sure everything was done.
1084                  */
1085                 if (ret == -EINVAL)
1086                         ret = 0;
1087         } else {
1088                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1089         }
1090
1091         drm_gem_object_unreference(&obj->base);
1092 unlock:
1093         mutex_unlock(&dev->struct_mutex);
1094         return ret;
1095 }
1096
1097 /**
1098  * Called when user space has done writes to this buffer
1099  */
1100 int
1101 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1102                          struct drm_file *file)
1103 {
1104         struct drm_i915_gem_sw_finish *args = data;
1105         struct drm_i915_gem_object *obj;
1106         int ret = 0;
1107
1108         if (!(dev->driver->driver_features & DRIVER_GEM))
1109                 return -ENODEV;
1110
1111         ret = i915_mutex_lock_interruptible(dev);
1112         if (ret)
1113                 return ret;
1114
1115         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1116         if (&obj->base == NULL) {
1117                 ret = -ENOENT;
1118                 goto unlock;
1119         }
1120
1121         /* Pinned buffers may be scanout, so flush the cache */
1122         if (obj->pin_count)
1123                 i915_gem_object_flush_cpu_write_domain(obj);
1124
1125         drm_gem_object_unreference(&obj->base);
1126 unlock:
1127         mutex_unlock(&dev->struct_mutex);
1128         return ret;
1129 }
1130
1131 /**
1132  * Maps the contents of an object, returning the address it is mapped
1133  * into.
1134  *
1135  * While the mapping holds a reference on the contents of the object, it doesn't
1136  * imply a ref on the object itself.
1137  */
1138 int
1139 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1140                     struct drm_file *file)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         struct drm_i915_gem_mmap *args = data;
1144         struct drm_gem_object *obj;
1145         unsigned long addr;
1146
1147         if (!(dev->driver->driver_features & DRIVER_GEM))
1148                 return -ENODEV;
1149
1150         obj = drm_gem_object_lookup(dev, file, args->handle);
1151         if (obj == NULL)
1152                 return -ENOENT;
1153
1154         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155                 drm_gem_object_unreference_unlocked(obj);
1156                 return -E2BIG;
1157         }
1158
1159         down_write(&current->mm->mmap_sem);
1160         addr = do_mmap(obj->filp, 0, args->size,
1161                        PROT_READ | PROT_WRITE, MAP_SHARED,
1162                        args->offset);
1163         up_write(&current->mm->mmap_sem);
1164         drm_gem_object_unreference_unlocked(obj);
1165         if (IS_ERR((void *)addr))
1166                 return addr;
1167
1168         args->addr_ptr = (uint64_t) addr;
1169
1170         return 0;
1171 }
1172
1173 /**
1174  * i915_gem_fault - fault a page into the GTT
1175  * vma: VMA in question
1176  * vmf: fault info
1177  *
1178  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179  * from userspace.  The fault handler takes care of binding the object to
1180  * the GTT (if needed), allocating and programming a fence register (again,
1181  * only if needed based on whether the old reg is still valid or the object
1182  * is tiled) and inserting a new PTE into the faulting process.
1183  *
1184  * Note that the faulting process may involve evicting existing objects
1185  * from the GTT and/or fence registers to make room.  So performance may
1186  * suffer if the GTT working set is large or there are few fence registers
1187  * left.
1188  */
1189 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1190 {
1191         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192         struct drm_device *dev = obj->base.dev;
1193         drm_i915_private_t *dev_priv = dev->dev_private;
1194         pgoff_t page_offset;
1195         unsigned long pfn;
1196         int ret = 0;
1197         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1198
1199         /* We don't use vmf->pgoff since that has the fake offset */
1200         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1201                 PAGE_SHIFT;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 goto out;
1206
1207         trace_i915_gem_object_fault(obj, page_offset, true, write);
1208
1209         /* Now bind it into the GTT if needed */
1210         if (!obj->map_and_fenceable) {
1211                 ret = i915_gem_object_unbind(obj);
1212                 if (ret)
1213                         goto unlock;
1214         }
1215         if (!obj->gtt_space) {
1216                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1217                 if (ret)
1218                         goto unlock;
1219
1220                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1221                 if (ret)
1222                         goto unlock;
1223         }
1224
1225         if (obj->tiling_mode == I915_TILING_NONE)
1226                 ret = i915_gem_object_put_fence(obj);
1227         else
1228                 ret = i915_gem_object_get_fence(obj, NULL);
1229         if (ret)
1230                 goto unlock;
1231
1232         if (i915_gem_object_is_inactive(obj))
1233                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1234
1235         obj->fault_mappable = true;
1236
1237         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1238                 page_offset;
1239
1240         /* Finally, remap it using the new GTT offset */
1241         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1242 unlock:
1243         mutex_unlock(&dev->struct_mutex);
1244 out:
1245         switch (ret) {
1246         case -EIO:
1247         case -EAGAIN:
1248                 /* Give the error handler a chance to run and move the
1249                  * objects off the GPU active list. Next time we service the
1250                  * fault, we should be able to transition the page into the
1251                  * GTT without touching the GPU (and so avoid further
1252                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253                  * with coherency, just lost writes.
1254                  */
1255                 set_need_resched();
1256         case 0:
1257         case -ERESTARTSYS:
1258         case -EINTR:
1259                 return VM_FAULT_NOPAGE;
1260         case -ENOMEM:
1261                 return VM_FAULT_OOM;
1262         default:
1263                 return VM_FAULT_SIGBUS;
1264         }
1265 }
1266
1267 /**
1268  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1269  * @obj: obj in question
1270  *
1271  * GEM memory mapping works by handing back to userspace a fake mmap offset
1272  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1273  * up the object based on the offset and sets up the various memory mapping
1274  * structures.
1275  *
1276  * This routine allocates and attaches a fake offset for @obj.
1277  */
1278 static int
1279 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1280 {
1281         struct drm_device *dev = obj->base.dev;
1282         struct drm_gem_mm *mm = dev->mm_private;
1283         struct drm_map_list *list;
1284         struct drm_local_map *map;
1285         int ret = 0;
1286
1287         /* Set the object up for mmap'ing */
1288         list = &obj->base.map_list;
1289         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1290         if (!list->map)
1291                 return -ENOMEM;
1292
1293         map = list->map;
1294         map->type = _DRM_GEM;
1295         map->size = obj->base.size;
1296         map->handle = obj;
1297
1298         /* Get a DRM GEM mmap offset allocated... */
1299         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1300                                                     obj->base.size / PAGE_SIZE,
1301                                                     0, 0);
1302         if (!list->file_offset_node) {
1303                 DRM_ERROR("failed to allocate offset for bo %d\n",
1304                           obj->base.name);
1305                 ret = -ENOSPC;
1306                 goto out_free_list;
1307         }
1308
1309         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1310                                                   obj->base.size / PAGE_SIZE,
1311                                                   0);
1312         if (!list->file_offset_node) {
1313                 ret = -ENOMEM;
1314                 goto out_free_list;
1315         }
1316
1317         list->hash.key = list->file_offset_node->start;
1318         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1319         if (ret) {
1320                 DRM_ERROR("failed to add to map hash\n");
1321                 goto out_free_mm;
1322         }
1323
1324         return 0;
1325
1326 out_free_mm:
1327         drm_mm_put_block(list->file_offset_node);
1328 out_free_list:
1329         kfree(list->map);
1330         list->map = NULL;
1331
1332         return ret;
1333 }
1334
1335 /**
1336  * i915_gem_release_mmap - remove physical page mappings
1337  * @obj: obj in question
1338  *
1339  * Preserve the reservation of the mmapping with the DRM core code, but
1340  * relinquish ownership of the pages back to the system.
1341  *
1342  * It is vital that we remove the page mapping if we have mapped a tiled
1343  * object through the GTT and then lose the fence register due to
1344  * resource pressure. Similarly if the object has been moved out of the
1345  * aperture, than pages mapped into userspace must be revoked. Removing the
1346  * mapping will then trigger a page fault on the next user access, allowing
1347  * fixup by i915_gem_fault().
1348  */
1349 void
1350 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1351 {
1352         if (!obj->fault_mappable)
1353                 return;
1354
1355         if (obj->base.dev->dev_mapping)
1356                 unmap_mapping_range(obj->base.dev->dev_mapping,
1357                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1358                                     obj->base.size, 1);
1359
1360         obj->fault_mappable = false;
1361 }
1362
1363 static void
1364 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1365 {
1366         struct drm_device *dev = obj->base.dev;
1367         struct drm_gem_mm *mm = dev->mm_private;
1368         struct drm_map_list *list = &obj->base.map_list;
1369
1370         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1371         drm_mm_put_block(list->file_offset_node);
1372         kfree(list->map);
1373         list->map = NULL;
1374 }
1375
1376 static uint32_t
1377 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1378 {
1379         struct drm_device *dev = obj->base.dev;
1380         uint32_t size;
1381
1382         if (INTEL_INFO(dev)->gen >= 4 ||
1383             obj->tiling_mode == I915_TILING_NONE)
1384                 return obj->base.size;
1385
1386         /* Previous chips need a power-of-two fence region when tiling */
1387         if (INTEL_INFO(dev)->gen == 3)
1388                 size = 1024*1024;
1389         else
1390                 size = 512*1024;
1391
1392         while (size < obj->base.size)
1393                 size <<= 1;
1394
1395         return size;
1396 }
1397
1398 /**
1399  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1400  * @obj: object to check
1401  *
1402  * Return the required GTT alignment for an object, taking into account
1403  * potential fence register mapping.
1404  */
1405 static uint32_t
1406 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1407 {
1408         struct drm_device *dev = obj->base.dev;
1409
1410         /*
1411          * Minimum alignment is 4k (GTT page size), but might be greater
1412          * if a fence register is needed for the object.
1413          */
1414         if (INTEL_INFO(dev)->gen >= 4 ||
1415             obj->tiling_mode == I915_TILING_NONE)
1416                 return 4096;
1417
1418         /*
1419          * Previous chips need to be aligned to the size of the smallest
1420          * fence register that can contain the object.
1421          */
1422         return i915_gem_get_gtt_size(obj);
1423 }
1424
1425 /**
1426  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1427  *                                       unfenced object
1428  * @obj: object to check
1429  *
1430  * Return the required GTT alignment for an object, only taking into account
1431  * unfenced tiled surface requirements.
1432  */
1433 uint32_t
1434 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1435 {
1436         struct drm_device *dev = obj->base.dev;
1437         int tile_height;
1438
1439         /*
1440          * Minimum alignment is 4k (GTT page size) for sane hw.
1441          */
1442         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1443             obj->tiling_mode == I915_TILING_NONE)
1444                 return 4096;
1445
1446         /*
1447          * Older chips need unfenced tiled buffers to be aligned to the left
1448          * edge of an even tile row (where tile rows are counted as if the bo is
1449          * placed in a fenced gtt region).
1450          */
1451         if (IS_GEN2(dev))
1452                 tile_height = 16;
1453         else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1454                 tile_height = 32;
1455         else
1456                 tile_height = 8;
1457
1458         return tile_height * obj->stride * 2;
1459 }
1460
1461 int
1462 i915_gem_mmap_gtt(struct drm_file *file,
1463                   struct drm_device *dev,
1464                   uint32_t handle,
1465                   uint64_t *offset)
1466 {
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         struct drm_i915_gem_object *obj;
1469         int ret;
1470
1471         if (!(dev->driver->driver_features & DRIVER_GEM))
1472                 return -ENODEV;
1473
1474         ret = i915_mutex_lock_interruptible(dev);
1475         if (ret)
1476                 return ret;
1477
1478         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1479         if (&obj->base == NULL) {
1480                 ret = -ENOENT;
1481                 goto unlock;
1482         }
1483
1484         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1485                 ret = -E2BIG;
1486                 goto unlock;
1487         }
1488
1489         if (obj->madv != I915_MADV_WILLNEED) {
1490                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1491                 ret = -EINVAL;
1492                 goto out;
1493         }
1494
1495         if (!obj->base.map_list.map) {
1496                 ret = i915_gem_create_mmap_offset(obj);
1497                 if (ret)
1498                         goto out;
1499         }
1500
1501         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1502
1503 out:
1504         drm_gem_object_unreference(&obj->base);
1505 unlock:
1506         mutex_unlock(&dev->struct_mutex);
1507         return ret;
1508 }
1509
1510 /**
1511  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1512  * @dev: DRM device
1513  * @data: GTT mapping ioctl data
1514  * @file: GEM object info
1515  *
1516  * Simply returns the fake offset to userspace so it can mmap it.
1517  * The mmap call will end up in drm_gem_mmap(), which will set things
1518  * up so we can get faults in the handler above.
1519  *
1520  * The fault handler will take care of binding the object into the GTT
1521  * (since it may have been evicted to make room for something), allocating
1522  * a fence register, and mapping the appropriate aperture address into
1523  * userspace.
1524  */
1525 int
1526 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1527                         struct drm_file *file)
1528 {
1529         struct drm_i915_gem_mmap_gtt *args = data;
1530
1531         if (!(dev->driver->driver_features & DRIVER_GEM))
1532                 return -ENODEV;
1533
1534         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1535 }
1536
1537
1538 static int
1539 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1540                               gfp_t gfpmask)
1541 {
1542         int page_count, i;
1543         struct address_space *mapping;
1544         struct inode *inode;
1545         struct page *page;
1546
1547         /* Get the list of pages out of our struct file.  They'll be pinned
1548          * at this point until we release them.
1549          */
1550         page_count = obj->base.size / PAGE_SIZE;
1551         BUG_ON(obj->pages != NULL);
1552         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1553         if (obj->pages == NULL)
1554                 return -ENOMEM;
1555
1556         inode = obj->base.filp->f_path.dentry->d_inode;
1557         mapping = inode->i_mapping;
1558         gfpmask |= mapping_gfp_mask(mapping);
1559
1560         for (i = 0; i < page_count; i++) {
1561                 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1562                 if (IS_ERR(page))
1563                         goto err_pages;
1564
1565                 obj->pages[i] = page;
1566         }
1567
1568         if (obj->tiling_mode != I915_TILING_NONE)
1569                 i915_gem_object_do_bit_17_swizzle(obj);
1570
1571         return 0;
1572
1573 err_pages:
1574         while (i--)
1575                 page_cache_release(obj->pages[i]);
1576
1577         drm_free_large(obj->pages);
1578         obj->pages = NULL;
1579         return PTR_ERR(page);
1580 }
1581
1582 static void
1583 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1584 {
1585         int page_count = obj->base.size / PAGE_SIZE;
1586         int i;
1587
1588         BUG_ON(obj->madv == __I915_MADV_PURGED);
1589
1590         if (obj->tiling_mode != I915_TILING_NONE)
1591                 i915_gem_object_save_bit_17_swizzle(obj);
1592
1593         if (obj->madv == I915_MADV_DONTNEED)
1594                 obj->dirty = 0;
1595
1596         for (i = 0; i < page_count; i++) {
1597                 if (obj->dirty)
1598                         set_page_dirty(obj->pages[i]);
1599
1600                 if (obj->madv == I915_MADV_WILLNEED)
1601                         mark_page_accessed(obj->pages[i]);
1602
1603                 page_cache_release(obj->pages[i]);
1604         }
1605         obj->dirty = 0;
1606
1607         drm_free_large(obj->pages);
1608         obj->pages = NULL;
1609 }
1610
1611 void
1612 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1613                                struct intel_ring_buffer *ring,
1614                                u32 seqno)
1615 {
1616         struct drm_device *dev = obj->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619         BUG_ON(ring == NULL);
1620         obj->ring = ring;
1621
1622         /* Add a reference if we're newly entering the active list. */
1623         if (!obj->active) {
1624                 drm_gem_object_reference(&obj->base);
1625                 obj->active = 1;
1626         }
1627
1628         /* Move from whatever list we were on to the tail of execution. */
1629         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1630         list_move_tail(&obj->ring_list, &ring->active_list);
1631
1632         obj->last_rendering_seqno = seqno;
1633         if (obj->fenced_gpu_access) {
1634                 struct drm_i915_fence_reg *reg;
1635
1636                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1637
1638                 obj->last_fenced_seqno = seqno;
1639                 obj->last_fenced_ring = ring;
1640
1641                 reg = &dev_priv->fence_regs[obj->fence_reg];
1642                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1643         }
1644 }
1645
1646 static void
1647 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1648 {
1649         list_del_init(&obj->ring_list);
1650         obj->last_rendering_seqno = 0;
1651 }
1652
1653 static void
1654 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1655 {
1656         struct drm_device *dev = obj->base.dev;
1657         drm_i915_private_t *dev_priv = dev->dev_private;
1658
1659         BUG_ON(!obj->active);
1660         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1661
1662         i915_gem_object_move_off_active(obj);
1663 }
1664
1665 static void
1666 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1667 {
1668         struct drm_device *dev = obj->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670
1671         if (obj->pin_count != 0)
1672                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1673         else
1674                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1675
1676         BUG_ON(!list_empty(&obj->gpu_write_list));
1677         BUG_ON(!obj->active);
1678         obj->ring = NULL;
1679
1680         i915_gem_object_move_off_active(obj);
1681         obj->fenced_gpu_access = false;
1682
1683         obj->active = 0;
1684         obj->pending_gpu_write = false;
1685         drm_gem_object_unreference(&obj->base);
1686
1687         WARN_ON(i915_verify_lists(dev));
1688 }
1689
1690 /* Immediately discard the backing storage */
1691 static void
1692 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1693 {
1694         struct inode *inode;
1695
1696         /* Our goal here is to return as much of the memory as
1697          * is possible back to the system as we are called from OOM.
1698          * To do this we must instruct the shmfs to drop all of its
1699          * backing pages, *now*.
1700          */
1701         inode = obj->base.filp->f_path.dentry->d_inode;
1702         shmem_truncate_range(inode, 0, (loff_t)-1);
1703
1704         obj->madv = __I915_MADV_PURGED;
1705 }
1706
1707 static inline int
1708 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1709 {
1710         return obj->madv == I915_MADV_DONTNEED;
1711 }
1712
1713 static void
1714 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1715                                uint32_t flush_domains)
1716 {
1717         struct drm_i915_gem_object *obj, *next;
1718
1719         list_for_each_entry_safe(obj, next,
1720                                  &ring->gpu_write_list,
1721                                  gpu_write_list) {
1722                 if (obj->base.write_domain & flush_domains) {
1723                         uint32_t old_write_domain = obj->base.write_domain;
1724
1725                         obj->base.write_domain = 0;
1726                         list_del_init(&obj->gpu_write_list);
1727                         i915_gem_object_move_to_active(obj, ring,
1728                                                        i915_gem_next_request_seqno(ring));
1729
1730                         trace_i915_gem_object_change_domain(obj,
1731                                                             obj->base.read_domains,
1732                                                             old_write_domain);
1733                 }
1734         }
1735 }
1736
1737 int
1738 i915_add_request(struct intel_ring_buffer *ring,
1739                  struct drm_file *file,
1740                  struct drm_i915_gem_request *request)
1741 {
1742         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1743         uint32_t seqno;
1744         int was_empty;
1745         int ret;
1746
1747         BUG_ON(request == NULL);
1748
1749         ret = ring->add_request(ring, &seqno);
1750         if (ret)
1751             return ret;
1752
1753         trace_i915_gem_request_add(ring, seqno);
1754
1755         request->seqno = seqno;
1756         request->ring = ring;
1757         request->emitted_jiffies = jiffies;
1758         was_empty = list_empty(&ring->request_list);
1759         list_add_tail(&request->list, &ring->request_list);
1760
1761         if (file) {
1762                 struct drm_i915_file_private *file_priv = file->driver_priv;
1763
1764                 spin_lock(&file_priv->mm.lock);
1765                 request->file_priv = file_priv;
1766                 list_add_tail(&request->client_list,
1767                               &file_priv->mm.request_list);
1768                 spin_unlock(&file_priv->mm.lock);
1769         }
1770
1771         ring->outstanding_lazy_request = false;
1772
1773         if (!dev_priv->mm.suspended) {
1774                 if (i915_enable_hangcheck) {
1775                         mod_timer(&dev_priv->hangcheck_timer,
1776                                   jiffies +
1777                                   msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1778                 }
1779                 if (was_empty)
1780                         queue_delayed_work(dev_priv->wq,
1781                                            &dev_priv->mm.retire_work, HZ);
1782         }
1783         return 0;
1784 }
1785
1786 static inline void
1787 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1788 {
1789         struct drm_i915_file_private *file_priv = request->file_priv;
1790
1791         if (!file_priv)
1792                 return;
1793
1794         spin_lock(&file_priv->mm.lock);
1795         if (request->file_priv) {
1796                 list_del(&request->client_list);
1797                 request->file_priv = NULL;
1798         }
1799         spin_unlock(&file_priv->mm.lock);
1800 }
1801
1802 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1803                                       struct intel_ring_buffer *ring)
1804 {
1805         while (!list_empty(&ring->request_list)) {
1806                 struct drm_i915_gem_request *request;
1807
1808                 request = list_first_entry(&ring->request_list,
1809                                            struct drm_i915_gem_request,
1810                                            list);
1811
1812                 list_del(&request->list);
1813                 i915_gem_request_remove_from_client(request);
1814                 kfree(request);
1815         }
1816
1817         while (!list_empty(&ring->active_list)) {
1818                 struct drm_i915_gem_object *obj;
1819
1820                 obj = list_first_entry(&ring->active_list,
1821                                        struct drm_i915_gem_object,
1822                                        ring_list);
1823
1824                 obj->base.write_domain = 0;
1825                 list_del_init(&obj->gpu_write_list);
1826                 i915_gem_object_move_to_inactive(obj);
1827         }
1828 }
1829
1830 static void i915_gem_reset_fences(struct drm_device *dev)
1831 {
1832         struct drm_i915_private *dev_priv = dev->dev_private;
1833         int i;
1834
1835         for (i = 0; i < 16; i++) {
1836                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1837                 struct drm_i915_gem_object *obj = reg->obj;
1838
1839                 if (!obj)
1840                         continue;
1841
1842                 if (obj->tiling_mode)
1843                         i915_gem_release_mmap(obj);
1844
1845                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1846                 reg->obj->fenced_gpu_access = false;
1847                 reg->obj->last_fenced_seqno = 0;
1848                 reg->obj->last_fenced_ring = NULL;
1849                 i915_gem_clear_fence_reg(dev, reg);
1850         }
1851 }
1852
1853 void i915_gem_reset(struct drm_device *dev)
1854 {
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct drm_i915_gem_object *obj;
1857         int i;
1858
1859         for (i = 0; i < I915_NUM_RINGS; i++)
1860                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1861
1862         /* Remove anything from the flushing lists. The GPU cache is likely
1863          * to be lost on reset along with the data, so simply move the
1864          * lost bo to the inactive list.
1865          */
1866         while (!list_empty(&dev_priv->mm.flushing_list)) {
1867                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1868                                       struct drm_i915_gem_object,
1869                                       mm_list);
1870
1871                 obj->base.write_domain = 0;
1872                 list_del_init(&obj->gpu_write_list);
1873                 i915_gem_object_move_to_inactive(obj);
1874         }
1875
1876         /* Move everything out of the GPU domains to ensure we do any
1877          * necessary invalidation upon reuse.
1878          */
1879         list_for_each_entry(obj,
1880                             &dev_priv->mm.inactive_list,
1881                             mm_list)
1882         {
1883                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1884         }
1885
1886         /* The fence registers are invalidated so clear them out */
1887         i915_gem_reset_fences(dev);
1888 }
1889
1890 /**
1891  * This function clears the request list as sequence numbers are passed.
1892  */
1893 static void
1894 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1895 {
1896         uint32_t seqno;
1897         int i;
1898
1899         if (list_empty(&ring->request_list))
1900                 return;
1901
1902         WARN_ON(i915_verify_lists(ring->dev));
1903
1904         seqno = ring->get_seqno(ring);
1905
1906         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1907                 if (seqno >= ring->sync_seqno[i])
1908                         ring->sync_seqno[i] = 0;
1909
1910         while (!list_empty(&ring->request_list)) {
1911                 struct drm_i915_gem_request *request;
1912
1913                 request = list_first_entry(&ring->request_list,
1914                                            struct drm_i915_gem_request,
1915                                            list);
1916
1917                 if (!i915_seqno_passed(seqno, request->seqno))
1918                         break;
1919
1920                 trace_i915_gem_request_retire(ring, request->seqno);
1921
1922                 list_del(&request->list);
1923                 i915_gem_request_remove_from_client(request);
1924                 kfree(request);
1925         }
1926
1927         /* Move any buffers on the active list that are no longer referenced
1928          * by the ringbuffer to the flushing/inactive lists as appropriate.
1929          */
1930         while (!list_empty(&ring->active_list)) {
1931                 struct drm_i915_gem_object *obj;
1932
1933                 obj= list_first_entry(&ring->active_list,
1934                                       struct drm_i915_gem_object,
1935                                       ring_list);
1936
1937                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1938                         break;
1939
1940                 if (obj->base.write_domain != 0)
1941                         i915_gem_object_move_to_flushing(obj);
1942                 else
1943                         i915_gem_object_move_to_inactive(obj);
1944         }
1945
1946         if (unlikely(ring->trace_irq_seqno &&
1947                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1948                 ring->irq_put(ring);
1949                 ring->trace_irq_seqno = 0;
1950         }
1951
1952         WARN_ON(i915_verify_lists(ring->dev));
1953 }
1954
1955 void
1956 i915_gem_retire_requests(struct drm_device *dev)
1957 {
1958         drm_i915_private_t *dev_priv = dev->dev_private;
1959         int i;
1960
1961         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1962             struct drm_i915_gem_object *obj, *next;
1963
1964             /* We must be careful that during unbind() we do not
1965              * accidentally infinitely recurse into retire requests.
1966              * Currently:
1967              *   retire -> free -> unbind -> wait -> retire_ring
1968              */
1969             list_for_each_entry_safe(obj, next,
1970                                      &dev_priv->mm.deferred_free_list,
1971                                      mm_list)
1972                     i915_gem_free_object_tail(obj);
1973         }
1974
1975         for (i = 0; i < I915_NUM_RINGS; i++)
1976                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1977 }
1978
1979 static void
1980 i915_gem_retire_work_handler(struct work_struct *work)
1981 {
1982         drm_i915_private_t *dev_priv;
1983         struct drm_device *dev;
1984         bool idle;
1985         int i;
1986
1987         dev_priv = container_of(work, drm_i915_private_t,
1988                                 mm.retire_work.work);
1989         dev = dev_priv->dev;
1990
1991         /* Come back later if the device is busy... */
1992         if (!mutex_trylock(&dev->struct_mutex)) {
1993                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1994                 return;
1995         }
1996
1997         i915_gem_retire_requests(dev);
1998
1999         /* Send a periodic flush down the ring so we don't hold onto GEM
2000          * objects indefinitely.
2001          */
2002         idle = true;
2003         for (i = 0; i < I915_NUM_RINGS; i++) {
2004                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2005
2006                 if (!list_empty(&ring->gpu_write_list)) {
2007                         struct drm_i915_gem_request *request;
2008                         int ret;
2009
2010                         ret = i915_gem_flush_ring(ring,
2011                                                   0, I915_GEM_GPU_DOMAINS);
2012                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2013                         if (ret || request == NULL ||
2014                             i915_add_request(ring, NULL, request))
2015                             kfree(request);
2016                 }
2017
2018                 idle &= list_empty(&ring->request_list);
2019         }
2020
2021         if (!dev_priv->mm.suspended && !idle)
2022                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2023
2024         mutex_unlock(&dev->struct_mutex);
2025 }
2026
2027 /**
2028  * Waits for a sequence number to be signaled, and cleans up the
2029  * request and object lists appropriately for that event.
2030  */
2031 int
2032 i915_wait_request(struct intel_ring_buffer *ring,
2033                   uint32_t seqno)
2034 {
2035         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2036         u32 ier;
2037         int ret = 0;
2038
2039         BUG_ON(seqno == 0);
2040
2041         if (atomic_read(&dev_priv->mm.wedged)) {
2042                 struct completion *x = &dev_priv->error_completion;
2043                 bool recovery_complete;
2044                 unsigned long flags;
2045
2046                 /* Give the error handler a chance to run. */
2047                 spin_lock_irqsave(&x->wait.lock, flags);
2048                 recovery_complete = x->done > 0;
2049                 spin_unlock_irqrestore(&x->wait.lock, flags);
2050
2051                 return recovery_complete ? -EIO : -EAGAIN;
2052         }
2053
2054         if (seqno == ring->outstanding_lazy_request) {
2055                 struct drm_i915_gem_request *request;
2056
2057                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2058                 if (request == NULL)
2059                         return -ENOMEM;
2060
2061                 ret = i915_add_request(ring, NULL, request);
2062                 if (ret) {
2063                         kfree(request);
2064                         return ret;
2065                 }
2066
2067                 seqno = request->seqno;
2068         }
2069
2070         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2071                 if (HAS_PCH_SPLIT(ring->dev))
2072                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2073                 else
2074                         ier = I915_READ(IER);
2075                 if (!ier) {
2076                         DRM_ERROR("something (likely vbetool) disabled "
2077                                   "interrupts, re-enabling\n");
2078                         ring->dev->driver->irq_preinstall(ring->dev);
2079                         ring->dev->driver->irq_postinstall(ring->dev);
2080                 }
2081
2082                 trace_i915_gem_request_wait_begin(ring, seqno);
2083
2084                 ring->waiting_seqno = seqno;
2085                 if (ring->irq_get(ring)) {
2086                         if (dev_priv->mm.interruptible)
2087                                 ret = wait_event_interruptible(ring->irq_queue,
2088                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2089                                                                || atomic_read(&dev_priv->mm.wedged));
2090                         else
2091                                 wait_event(ring->irq_queue,
2092                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2093                                            || atomic_read(&dev_priv->mm.wedged));
2094
2095                         ring->irq_put(ring);
2096                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2097                                                       seqno) ||
2098                                     atomic_read(&dev_priv->mm.wedged), 3000))
2099                         ret = -EBUSY;
2100                 ring->waiting_seqno = 0;
2101
2102                 trace_i915_gem_request_wait_end(ring, seqno);
2103         }
2104         if (atomic_read(&dev_priv->mm.wedged))
2105                 ret = -EAGAIN;
2106
2107         if (ret && ret != -ERESTARTSYS)
2108                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2109                           __func__, ret, seqno, ring->get_seqno(ring),
2110                           dev_priv->next_seqno);
2111
2112         /* Directly dispatch request retiring.  While we have the work queue
2113          * to handle this, the waiter on a request often wants an associated
2114          * buffer to have made it to the inactive list, and we would need
2115          * a separate wait queue to handle that.
2116          */
2117         if (ret == 0)
2118                 i915_gem_retire_requests_ring(ring);
2119
2120         return ret;
2121 }
2122
2123 /**
2124  * Ensures that all rendering to the object has completed and the object is
2125  * safe to unbind from the GTT or access from the CPU.
2126  */
2127 int
2128 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2129 {
2130         int ret;
2131
2132         /* This function only exists to support waiting for existing rendering,
2133          * not for emitting required flushes.
2134          */
2135         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2136
2137         /* If there is rendering queued on the buffer being evicted, wait for
2138          * it.
2139          */
2140         if (obj->active) {
2141                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2142                 if (ret)
2143                         return ret;
2144         }
2145
2146         return 0;
2147 }
2148
2149 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2150 {
2151         u32 old_write_domain, old_read_domains;
2152
2153         /* Act a barrier for all accesses through the GTT */
2154         mb();
2155
2156         /* Force a pagefault for domain tracking on next user access */
2157         i915_gem_release_mmap(obj);
2158
2159         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2160                 return;
2161
2162         old_read_domains = obj->base.read_domains;
2163         old_write_domain = obj->base.write_domain;
2164
2165         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2166         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2167
2168         trace_i915_gem_object_change_domain(obj,
2169                                             old_read_domains,
2170                                             old_write_domain);
2171 }
2172
2173 /**
2174  * Unbinds an object from the GTT aperture.
2175  */
2176 int
2177 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2178 {
2179         int ret = 0;
2180
2181         if (obj->gtt_space == NULL)
2182                 return 0;
2183
2184         if (obj->pin_count != 0) {
2185                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2186                 return -EINVAL;
2187         }
2188
2189         ret = i915_gem_object_finish_gpu(obj);
2190         if (ret == -ERESTARTSYS)
2191                 return ret;
2192         /* Continue on if we fail due to EIO, the GPU is hung so we
2193          * should be safe and we need to cleanup or else we might
2194          * cause memory corruption through use-after-free.
2195          */
2196
2197         i915_gem_object_finish_gtt(obj);
2198
2199         /* Move the object to the CPU domain to ensure that
2200          * any possible CPU writes while it's not in the GTT
2201          * are flushed when we go to remap it.
2202          */
2203         if (ret == 0)
2204                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2205         if (ret == -ERESTARTSYS)
2206                 return ret;
2207         if (ret) {
2208                 /* In the event of a disaster, abandon all caches and
2209                  * hope for the best.
2210                  */
2211                 i915_gem_clflush_object(obj);
2212                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2213         }
2214
2215         /* release the fence reg _after_ flushing */
2216         ret = i915_gem_object_put_fence(obj);
2217         if (ret == -ERESTARTSYS)
2218                 return ret;
2219
2220         trace_i915_gem_object_unbind(obj);
2221
2222         i915_gem_gtt_unbind_object(obj);
2223         i915_gem_object_put_pages_gtt(obj);
2224
2225         list_del_init(&obj->gtt_list);
2226         list_del_init(&obj->mm_list);
2227         /* Avoid an unnecessary call to unbind on rebind. */
2228         obj->map_and_fenceable = true;
2229
2230         drm_mm_put_block(obj->gtt_space);
2231         obj->gtt_space = NULL;
2232         obj->gtt_offset = 0;
2233
2234         if (i915_gem_object_is_purgeable(obj))
2235                 i915_gem_object_truncate(obj);
2236
2237         return ret;
2238 }
2239
2240 int
2241 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2242                     uint32_t invalidate_domains,
2243                     uint32_t flush_domains)
2244 {
2245         int ret;
2246
2247         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2248                 return 0;
2249
2250         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2251
2252         ret = ring->flush(ring, invalidate_domains, flush_domains);
2253         if (ret)
2254                 return ret;
2255
2256         if (flush_domains & I915_GEM_GPU_DOMAINS)
2257                 i915_gem_process_flushing_list(ring, flush_domains);
2258
2259         return 0;
2260 }
2261
2262 static int i915_ring_idle(struct intel_ring_buffer *ring)
2263 {
2264         int ret;
2265
2266         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2267                 return 0;
2268
2269         if (!list_empty(&ring->gpu_write_list)) {
2270                 ret = i915_gem_flush_ring(ring,
2271                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2272                 if (ret)
2273                         return ret;
2274         }
2275
2276         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2277 }
2278
2279 int
2280 i915_gpu_idle(struct drm_device *dev)
2281 {
2282         drm_i915_private_t *dev_priv = dev->dev_private;
2283         bool lists_empty;
2284         int ret, i;
2285
2286         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2287                        list_empty(&dev_priv->mm.active_list));
2288         if (lists_empty)
2289                 return 0;
2290
2291         /* Flush everything onto the inactive list. */
2292         for (i = 0; i < I915_NUM_RINGS; i++) {
2293                 ret = i915_ring_idle(&dev_priv->ring[i]);
2294                 if (ret)
2295                         return ret;
2296         }
2297
2298         return 0;
2299 }
2300
2301 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2302                                        struct intel_ring_buffer *pipelined)
2303 {
2304         struct drm_device *dev = obj->base.dev;
2305         drm_i915_private_t *dev_priv = dev->dev_private;
2306         u32 size = obj->gtt_space->size;
2307         int regnum = obj->fence_reg;
2308         uint64_t val;
2309
2310         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2311                          0xfffff000) << 32;
2312         val |= obj->gtt_offset & 0xfffff000;
2313         val |= (uint64_t)((obj->stride / 128) - 1) <<
2314                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2315
2316         if (obj->tiling_mode == I915_TILING_Y)
2317                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2318         val |= I965_FENCE_REG_VALID;
2319
2320         if (pipelined) {
2321                 int ret = intel_ring_begin(pipelined, 6);
2322                 if (ret)
2323                         return ret;
2324
2325                 intel_ring_emit(pipelined, MI_NOOP);
2326                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2327                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2328                 intel_ring_emit(pipelined, (u32)val);
2329                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2330                 intel_ring_emit(pipelined, (u32)(val >> 32));
2331                 intel_ring_advance(pipelined);
2332         } else
2333                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2334
2335         return 0;
2336 }
2337
2338 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2339                                 struct intel_ring_buffer *pipelined)
2340 {
2341         struct drm_device *dev = obj->base.dev;
2342         drm_i915_private_t *dev_priv = dev->dev_private;
2343         u32 size = obj->gtt_space->size;
2344         int regnum = obj->fence_reg;
2345         uint64_t val;
2346
2347         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2348                     0xfffff000) << 32;
2349         val |= obj->gtt_offset & 0xfffff000;
2350         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2351         if (obj->tiling_mode == I915_TILING_Y)
2352                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2353         val |= I965_FENCE_REG_VALID;
2354
2355         if (pipelined) {
2356                 int ret = intel_ring_begin(pipelined, 6);
2357                 if (ret)
2358                         return ret;
2359
2360                 intel_ring_emit(pipelined, MI_NOOP);
2361                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2362                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2363                 intel_ring_emit(pipelined, (u32)val);
2364                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2365                 intel_ring_emit(pipelined, (u32)(val >> 32));
2366                 intel_ring_advance(pipelined);
2367         } else
2368                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2369
2370         return 0;
2371 }
2372
2373 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2374                                 struct intel_ring_buffer *pipelined)
2375 {
2376         struct drm_device *dev = obj->base.dev;
2377         drm_i915_private_t *dev_priv = dev->dev_private;
2378         u32 size = obj->gtt_space->size;
2379         u32 fence_reg, val, pitch_val;
2380         int tile_width;
2381
2382         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2383                  (size & -size) != size ||
2384                  (obj->gtt_offset & (size - 1)),
2385                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2386                  obj->gtt_offset, obj->map_and_fenceable, size))
2387                 return -EINVAL;
2388
2389         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2390                 tile_width = 128;
2391         else
2392                 tile_width = 512;
2393
2394         /* Note: pitch better be a power of two tile widths */
2395         pitch_val = obj->stride / tile_width;
2396         pitch_val = ffs(pitch_val) - 1;
2397
2398         val = obj->gtt_offset;
2399         if (obj->tiling_mode == I915_TILING_Y)
2400                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2401         val |= I915_FENCE_SIZE_BITS(size);
2402         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2403         val |= I830_FENCE_REG_VALID;
2404
2405         fence_reg = obj->fence_reg;
2406         if (fence_reg < 8)
2407                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2408         else
2409                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2410
2411         if (pipelined) {
2412                 int ret = intel_ring_begin(pipelined, 4);
2413                 if (ret)
2414                         return ret;
2415
2416                 intel_ring_emit(pipelined, MI_NOOP);
2417                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2418                 intel_ring_emit(pipelined, fence_reg);
2419                 intel_ring_emit(pipelined, val);
2420                 intel_ring_advance(pipelined);
2421         } else
2422                 I915_WRITE(fence_reg, val);
2423
2424         return 0;
2425 }
2426
2427 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2428                                 struct intel_ring_buffer *pipelined)
2429 {
2430         struct drm_device *dev = obj->base.dev;
2431         drm_i915_private_t *dev_priv = dev->dev_private;
2432         u32 size = obj->gtt_space->size;
2433         int regnum = obj->fence_reg;
2434         uint32_t val;
2435         uint32_t pitch_val;
2436
2437         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2438                  (size & -size) != size ||
2439                  (obj->gtt_offset & (size - 1)),
2440                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2441                  obj->gtt_offset, size))
2442                 return -EINVAL;
2443
2444         pitch_val = obj->stride / 128;
2445         pitch_val = ffs(pitch_val) - 1;
2446
2447         val = obj->gtt_offset;
2448         if (obj->tiling_mode == I915_TILING_Y)
2449                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2450         val |= I830_FENCE_SIZE_BITS(size);
2451         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2452         val |= I830_FENCE_REG_VALID;
2453
2454         if (pipelined) {
2455                 int ret = intel_ring_begin(pipelined, 4);
2456                 if (ret)
2457                         return ret;
2458
2459                 intel_ring_emit(pipelined, MI_NOOP);
2460                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2461                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2462                 intel_ring_emit(pipelined, val);
2463                 intel_ring_advance(pipelined);
2464         } else
2465                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2466
2467         return 0;
2468 }
2469
2470 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2471 {
2472         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2473 }
2474
2475 static int
2476 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2477                             struct intel_ring_buffer *pipelined)
2478 {
2479         int ret;
2480
2481         if (obj->fenced_gpu_access) {
2482                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2483                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2484                                                   0, obj->base.write_domain);
2485                         if (ret)
2486                                 return ret;
2487                 }
2488
2489                 obj->fenced_gpu_access = false;
2490         }
2491
2492         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2493                 if (!ring_passed_seqno(obj->last_fenced_ring,
2494                                        obj->last_fenced_seqno)) {
2495                         ret = i915_wait_request(obj->last_fenced_ring,
2496                                                 obj->last_fenced_seqno);
2497                         if (ret)
2498                                 return ret;
2499                 }
2500
2501                 obj->last_fenced_seqno = 0;
2502                 obj->last_fenced_ring = NULL;
2503         }
2504
2505         /* Ensure that all CPU reads are completed before installing a fence
2506          * and all writes before removing the fence.
2507          */
2508         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2509                 mb();
2510
2511         return 0;
2512 }
2513
2514 int
2515 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2516 {
2517         int ret;
2518
2519         if (obj->tiling_mode)
2520                 i915_gem_release_mmap(obj);
2521
2522         ret = i915_gem_object_flush_fence(obj, NULL);
2523         if (ret)
2524                 return ret;
2525
2526         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2527                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2528                 i915_gem_clear_fence_reg(obj->base.dev,
2529                                          &dev_priv->fence_regs[obj->fence_reg]);
2530
2531                 obj->fence_reg = I915_FENCE_REG_NONE;
2532         }
2533
2534         return 0;
2535 }
2536
2537 static struct drm_i915_fence_reg *
2538 i915_find_fence_reg(struct drm_device *dev,
2539                     struct intel_ring_buffer *pipelined)
2540 {
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         struct drm_i915_fence_reg *reg, *first, *avail;
2543         int i;
2544
2545         /* First try to find a free reg */
2546         avail = NULL;
2547         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2548                 reg = &dev_priv->fence_regs[i];
2549                 if (!reg->obj)
2550                         return reg;
2551
2552                 if (!reg->obj->pin_count)
2553                         avail = reg;
2554         }
2555
2556         if (avail == NULL)
2557                 return NULL;
2558
2559         /* None available, try to steal one or wait for a user to finish */
2560         avail = first = NULL;
2561         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2562                 if (reg->obj->pin_count)
2563                         continue;
2564
2565                 if (first == NULL)
2566                         first = reg;
2567
2568                 if (!pipelined ||
2569                     !reg->obj->last_fenced_ring ||
2570                     reg->obj->last_fenced_ring == pipelined) {
2571                         avail = reg;
2572                         break;
2573                 }
2574         }
2575
2576         if (avail == NULL)
2577                 avail = first;
2578
2579         return avail;
2580 }
2581
2582 /**
2583  * i915_gem_object_get_fence - set up a fence reg for an object
2584  * @obj: object to map through a fence reg
2585  * @pipelined: ring on which to queue the change, or NULL for CPU access
2586  * @interruptible: must we wait uninterruptibly for the register to retire?
2587  *
2588  * When mapping objects through the GTT, userspace wants to be able to write
2589  * to them without having to worry about swizzling if the object is tiled.
2590  *
2591  * This function walks the fence regs looking for a free one for @obj,
2592  * stealing one if it can't find any.
2593  *
2594  * It then sets up the reg based on the object's properties: address, pitch
2595  * and tiling format.
2596  */
2597 int
2598 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2599                           struct intel_ring_buffer *pipelined)
2600 {
2601         struct drm_device *dev = obj->base.dev;
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         struct drm_i915_fence_reg *reg;
2604         int ret;
2605
2606         /* XXX disable pipelining. There are bugs. Shocking. */
2607         pipelined = NULL;
2608
2609         /* Just update our place in the LRU if our fence is getting reused. */
2610         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2611                 reg = &dev_priv->fence_regs[obj->fence_reg];
2612                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2613
2614                 if (obj->tiling_changed) {
2615                         ret = i915_gem_object_flush_fence(obj, pipelined);
2616                         if (ret)
2617                                 return ret;
2618
2619                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2620                                 pipelined = NULL;
2621
2622                         if (pipelined) {
2623                                 reg->setup_seqno =
2624                                         i915_gem_next_request_seqno(pipelined);
2625                                 obj->last_fenced_seqno = reg->setup_seqno;
2626                                 obj->last_fenced_ring = pipelined;
2627                         }
2628
2629                         goto update;
2630                 }
2631
2632                 if (!pipelined) {
2633                         if (reg->setup_seqno) {
2634                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2635                                                        reg->setup_seqno)) {
2636                                         ret = i915_wait_request(obj->last_fenced_ring,
2637                                                                 reg->setup_seqno);
2638                                         if (ret)
2639                                                 return ret;
2640                                 }
2641
2642                                 reg->setup_seqno = 0;
2643                         }
2644                 } else if (obj->last_fenced_ring &&
2645                            obj->last_fenced_ring != pipelined) {
2646                         ret = i915_gem_object_flush_fence(obj, pipelined);
2647                         if (ret)
2648                                 return ret;
2649                 }
2650
2651                 return 0;
2652         }
2653
2654         reg = i915_find_fence_reg(dev, pipelined);
2655         if (reg == NULL)
2656                 return -ENOSPC;
2657
2658         ret = i915_gem_object_flush_fence(obj, pipelined);
2659         if (ret)
2660                 return ret;
2661
2662         if (reg->obj) {
2663                 struct drm_i915_gem_object *old = reg->obj;
2664
2665                 drm_gem_object_reference(&old->base);
2666
2667                 if (old->tiling_mode)
2668                         i915_gem_release_mmap(old);
2669
2670                 ret = i915_gem_object_flush_fence(old, pipelined);
2671                 if (ret) {
2672                         drm_gem_object_unreference(&old->base);
2673                         return ret;
2674                 }
2675
2676                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2677                         pipelined = NULL;
2678
2679                 old->fence_reg = I915_FENCE_REG_NONE;
2680                 old->last_fenced_ring = pipelined;
2681                 old->last_fenced_seqno =
2682                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2683
2684                 drm_gem_object_unreference(&old->base);
2685         } else if (obj->last_fenced_seqno == 0)
2686                 pipelined = NULL;
2687
2688         reg->obj = obj;
2689         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2690         obj->fence_reg = reg - dev_priv->fence_regs;
2691         obj->last_fenced_ring = pipelined;
2692
2693         reg->setup_seqno =
2694                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2695         obj->last_fenced_seqno = reg->setup_seqno;
2696
2697 update:
2698         obj->tiling_changed = false;
2699         switch (INTEL_INFO(dev)->gen) {
2700         case 7:
2701         case 6:
2702                 ret = sandybridge_write_fence_reg(obj, pipelined);
2703                 break;
2704         case 5:
2705         case 4:
2706                 ret = i965_write_fence_reg(obj, pipelined);
2707                 break;
2708         case 3:
2709                 ret = i915_write_fence_reg(obj, pipelined);
2710                 break;
2711         case 2:
2712                 ret = i830_write_fence_reg(obj, pipelined);
2713                 break;
2714         }
2715
2716         return ret;
2717 }
2718
2719 /**
2720  * i915_gem_clear_fence_reg - clear out fence register info
2721  * @obj: object to clear
2722  *
2723  * Zeroes out the fence register itself and clears out the associated
2724  * data structures in dev_priv and obj.
2725  */
2726 static void
2727 i915_gem_clear_fence_reg(struct drm_device *dev,
2728                          struct drm_i915_fence_reg *reg)
2729 {
2730         drm_i915_private_t *dev_priv = dev->dev_private;
2731         uint32_t fence_reg = reg - dev_priv->fence_regs;
2732
2733         switch (INTEL_INFO(dev)->gen) {
2734         case 7:
2735         case 6:
2736                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2737                 break;
2738         case 5:
2739         case 4:
2740                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2741                 break;
2742         case 3:
2743                 if (fence_reg >= 8)
2744                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2745                 else
2746         case 2:
2747                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2748
2749                 I915_WRITE(fence_reg, 0);
2750                 break;
2751         }
2752
2753         list_del_init(&reg->lru_list);
2754         reg->obj = NULL;
2755         reg->setup_seqno = 0;
2756 }
2757
2758 /**
2759  * Finds free space in the GTT aperture and binds the object there.
2760  */
2761 static int
2762 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2763                             unsigned alignment,
2764                             bool map_and_fenceable)
2765 {
2766         struct drm_device *dev = obj->base.dev;
2767         drm_i915_private_t *dev_priv = dev->dev_private;
2768         struct drm_mm_node *free_space;
2769         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2770         u32 size, fence_size, fence_alignment, unfenced_alignment;
2771         bool mappable, fenceable;
2772         int ret;
2773
2774         if (obj->madv != I915_MADV_WILLNEED) {
2775                 DRM_ERROR("Attempting to bind a purgeable object\n");
2776                 return -EINVAL;
2777         }
2778
2779         fence_size = i915_gem_get_gtt_size(obj);
2780         fence_alignment = i915_gem_get_gtt_alignment(obj);
2781         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2782
2783         if (alignment == 0)
2784                 alignment = map_and_fenceable ? fence_alignment :
2785                                                 unfenced_alignment;
2786         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2787                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2788                 return -EINVAL;
2789         }
2790
2791         size = map_and_fenceable ? fence_size : obj->base.size;
2792
2793         /* If the object is bigger than the entire aperture, reject it early
2794          * before evicting everything in a vain attempt to find space.
2795          */
2796         if (obj->base.size >
2797             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2798                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2799                 return -E2BIG;
2800         }
2801
2802  search_free:
2803         if (map_and_fenceable)
2804                 free_space =
2805                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2806                                                     size, alignment, 0,
2807                                                     dev_priv->mm.gtt_mappable_end,
2808                                                     0);
2809         else
2810                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2811                                                 size, alignment, 0);
2812
2813         if (free_space != NULL) {
2814                 if (map_and_fenceable)
2815                         obj->gtt_space =
2816                                 drm_mm_get_block_range_generic(free_space,
2817                                                                size, alignment, 0,
2818                                                                dev_priv->mm.gtt_mappable_end,
2819                                                                0);
2820                 else
2821                         obj->gtt_space =
2822                                 drm_mm_get_block(free_space, size, alignment);
2823         }
2824         if (obj->gtt_space == NULL) {
2825                 /* If the gtt is empty and we're still having trouble
2826                  * fitting our object in, we're out of memory.
2827                  */
2828                 ret = i915_gem_evict_something(dev, size, alignment,
2829                                                map_and_fenceable);
2830                 if (ret)
2831                         return ret;
2832
2833                 goto search_free;
2834         }
2835
2836         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2837         if (ret) {
2838                 drm_mm_put_block(obj->gtt_space);
2839                 obj->gtt_space = NULL;
2840
2841                 if (ret == -ENOMEM) {
2842                         /* first try to reclaim some memory by clearing the GTT */
2843                         ret = i915_gem_evict_everything(dev, false);
2844                         if (ret) {
2845                                 /* now try to shrink everyone else */
2846                                 if (gfpmask) {
2847                                         gfpmask = 0;
2848                                         goto search_free;
2849                                 }
2850
2851                                 return -ENOMEM;
2852                         }
2853
2854                         goto search_free;
2855                 }
2856
2857                 return ret;
2858         }
2859
2860         ret = i915_gem_gtt_bind_object(obj);
2861         if (ret) {
2862                 i915_gem_object_put_pages_gtt(obj);
2863                 drm_mm_put_block(obj->gtt_space);
2864                 obj->gtt_space = NULL;
2865
2866                 if (i915_gem_evict_everything(dev, false))
2867                         return ret;
2868
2869                 goto search_free;
2870         }
2871
2872         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2873         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2874
2875         /* Assert that the object is not currently in any GPU domain. As it
2876          * wasn't in the GTT, there shouldn't be any way it could have been in
2877          * a GPU cache
2878          */
2879         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2880         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2881
2882         obj->gtt_offset = obj->gtt_space->start;
2883
2884         fenceable =
2885                 obj->gtt_space->size == fence_size &&
2886                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2887
2888         mappable =
2889                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2890
2891         obj->map_and_fenceable = mappable && fenceable;
2892
2893         trace_i915_gem_object_bind(obj, map_and_fenceable);
2894         return 0;
2895 }
2896
2897 void
2898 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2899 {
2900         /* If we don't have a page list set up, then we're not pinned
2901          * to GPU, and we can ignore the cache flush because it'll happen
2902          * again at bind time.
2903          */
2904         if (obj->pages == NULL)
2905                 return;
2906
2907         /* If the GPU is snooping the contents of the CPU cache,
2908          * we do not need to manually clear the CPU cache lines.  However,
2909          * the caches are only snooped when the render cache is
2910          * flushed/invalidated.  As we always have to emit invalidations
2911          * and flushes when moving into and out of the RENDER domain, correct
2912          * snooping behaviour occurs naturally as the result of our domain
2913          * tracking.
2914          */
2915         if (obj->cache_level != I915_CACHE_NONE)
2916                 return;
2917
2918         trace_i915_gem_object_clflush(obj);
2919
2920         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2921 }
2922
2923 /** Flushes any GPU write domain for the object if it's dirty. */
2924 static int
2925 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2926 {
2927         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2928                 return 0;
2929
2930         /* Queue the GPU write cache flushing we need. */
2931         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2932 }
2933
2934 /** Flushes the GTT write domain for the object if it's dirty. */
2935 static void
2936 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2937 {
2938         uint32_t old_write_domain;
2939
2940         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2941                 return;
2942
2943         /* No actual flushing is required for the GTT write domain.  Writes
2944          * to it immediately go to main memory as far as we know, so there's
2945          * no chipset flush.  It also doesn't land in render cache.
2946          *
2947          * However, we do have to enforce the order so that all writes through
2948          * the GTT land before any writes to the device, such as updates to
2949          * the GATT itself.
2950          */
2951         wmb();
2952
2953         old_write_domain = obj->base.write_domain;
2954         obj->base.write_domain = 0;
2955
2956         trace_i915_gem_object_change_domain(obj,
2957                                             obj->base.read_domains,
2958                                             old_write_domain);
2959 }
2960
2961 /** Flushes the CPU write domain for the object if it's dirty. */
2962 static void
2963 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2964 {
2965         uint32_t old_write_domain;
2966
2967         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2968                 return;
2969
2970         i915_gem_clflush_object(obj);
2971         intel_gtt_chipset_flush();
2972         old_write_domain = obj->base.write_domain;
2973         obj->base.write_domain = 0;
2974
2975         trace_i915_gem_object_change_domain(obj,
2976                                             obj->base.read_domains,
2977                                             old_write_domain);
2978 }
2979
2980 /**
2981  * Moves a single object to the GTT read, and possibly write domain.
2982  *
2983  * This function returns when the move is complete, including waiting on
2984  * flushes to occur.
2985  */
2986 int
2987 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2988 {
2989         uint32_t old_write_domain, old_read_domains;
2990         int ret;
2991
2992         /* Not valid to be called on unbound objects. */
2993         if (obj->gtt_space == NULL)
2994                 return -EINVAL;
2995
2996         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2997                 return 0;
2998
2999         ret = i915_gem_object_flush_gpu_write_domain(obj);
3000         if (ret)
3001                 return ret;
3002
3003         if (obj->pending_gpu_write || write) {
3004                 ret = i915_gem_object_wait_rendering(obj);
3005                 if (ret)
3006                         return ret;
3007         }
3008
3009         i915_gem_object_flush_cpu_write_domain(obj);
3010
3011         old_write_domain = obj->base.write_domain;
3012         old_read_domains = obj->base.read_domains;
3013
3014         /* It should now be out of any other write domains, and we can update
3015          * the domain values for our changes.
3016          */
3017         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3018         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3019         if (write) {
3020                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3021                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3022                 obj->dirty = 1;
3023         }
3024
3025         trace_i915_gem_object_change_domain(obj,
3026                                             old_read_domains,
3027                                             old_write_domain);
3028
3029         return 0;
3030 }
3031
3032 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3033                                     enum i915_cache_level cache_level)
3034 {
3035         int ret;
3036
3037         if (obj->cache_level == cache_level)
3038                 return 0;
3039
3040         if (obj->pin_count) {
3041                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3042                 return -EBUSY;
3043         }
3044
3045         if (obj->gtt_space) {
3046                 ret = i915_gem_object_finish_gpu(obj);
3047                 if (ret)
3048                         return ret;
3049
3050                 i915_gem_object_finish_gtt(obj);
3051
3052                 /* Before SandyBridge, you could not use tiling or fence
3053                  * registers with snooped memory, so relinquish any fences
3054                  * currently pointing to our region in the aperture.
3055                  */
3056                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3057                         ret = i915_gem_object_put_fence(obj);
3058                         if (ret)
3059                                 return ret;
3060                 }
3061
3062                 i915_gem_gtt_rebind_object(obj, cache_level);
3063         }
3064
3065         if (cache_level == I915_CACHE_NONE) {
3066                 u32 old_read_domains, old_write_domain;
3067
3068                 /* If we're coming from LLC cached, then we haven't
3069                  * actually been tracking whether the data is in the
3070                  * CPU cache or not, since we only allow one bit set
3071                  * in obj->write_domain and have been skipping the clflushes.
3072                  * Just set it to the CPU cache for now.
3073                  */
3074                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3075                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3076
3077                 old_read_domains = obj->base.read_domains;
3078                 old_write_domain = obj->base.write_domain;
3079
3080                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3081                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3082
3083                 trace_i915_gem_object_change_domain(obj,
3084                                                     old_read_domains,
3085                                                     old_write_domain);
3086         }
3087
3088         obj->cache_level = cache_level;
3089         return 0;
3090 }
3091
3092 /*
3093  * Prepare buffer for display plane (scanout, cursors, etc).
3094  * Can be called from an uninterruptible phase (modesetting) and allows
3095  * any flushes to be pipelined (for pageflips).
3096  *
3097  * For the display plane, we want to be in the GTT but out of any write
3098  * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3099  * ability to pipeline the waits, pinning and any additional subtleties
3100  * that may differentiate the display plane from ordinary buffers.
3101  */
3102 int
3103 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3104                                      u32 alignment,
3105                                      struct intel_ring_buffer *pipelined)
3106 {
3107         u32 old_read_domains, old_write_domain;
3108         int ret;
3109
3110         ret = i915_gem_object_flush_gpu_write_domain(obj);
3111         if (ret)
3112                 return ret;
3113
3114         if (pipelined != obj->ring) {
3115                 ret = i915_gem_object_wait_rendering(obj);
3116                 if (ret)
3117                         return ret;
3118         }
3119
3120         /* The display engine is not coherent with the LLC cache on gen6.  As
3121          * a result, we make sure that the pinning that is about to occur is
3122          * done with uncached PTEs. This is lowest common denominator for all
3123          * chipsets.
3124          *
3125          * However for gen6+, we could do better by using the GFDT bit instead
3126          * of uncaching, which would allow us to flush all the LLC-cached data
3127          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3128          */
3129         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3130         if (ret)
3131                 return ret;
3132
3133         /* As the user may map the buffer once pinned in the display plane
3134          * (e.g. libkms for the bootup splash), we have to ensure that we
3135          * always use map_and_fenceable for all scanout buffers.
3136          */
3137         ret = i915_gem_object_pin(obj, alignment, true);
3138         if (ret)
3139                 return ret;
3140
3141         i915_gem_object_flush_cpu_write_domain(obj);
3142
3143         old_write_domain = obj->base.write_domain;
3144         old_read_domains = obj->base.read_domains;
3145
3146         /* It should now be out of any other write domains, and we can update
3147          * the domain values for our changes.
3148          */
3149         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3150         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3151
3152         trace_i915_gem_object_change_domain(obj,
3153                                             old_read_domains,
3154                                             old_write_domain);
3155
3156         return 0;
3157 }
3158
3159 int
3160 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3161 {
3162         int ret;
3163
3164         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3165                 return 0;
3166
3167         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3168                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3169                 if (ret)
3170                         return ret;
3171         }
3172
3173         /* Ensure that we invalidate the GPU's caches and TLBs. */
3174         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3175
3176         return i915_gem_object_wait_rendering(obj);
3177 }
3178
3179 /**
3180  * Moves a single object to the CPU read, and possibly write domain.
3181  *
3182  * This function returns when the move is complete, including waiting on
3183  * flushes to occur.
3184  */
3185 static int
3186 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3187 {
3188         uint32_t old_write_domain, old_read_domains;
3189         int ret;
3190
3191         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3192                 return 0;
3193
3194         ret = i915_gem_object_flush_gpu_write_domain(obj);
3195         if (ret)
3196                 return ret;
3197
3198         ret = i915_gem_object_wait_rendering(obj);
3199         if (ret)
3200                 return ret;
3201
3202         i915_gem_object_flush_gtt_write_domain(obj);
3203
3204         /* If we have a partially-valid cache of the object in the CPU,
3205          * finish invalidating it and free the per-page flags.
3206          */
3207         i915_gem_object_set_to_full_cpu_read_domain(obj);
3208
3209         old_write_domain = obj->base.write_domain;
3210         old_read_domains = obj->base.read_domains;
3211
3212         /* Flush the CPU cache if it's still invalid. */
3213         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3214                 i915_gem_clflush_object(obj);
3215
3216                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3217         }
3218
3219         /* It should now be out of any other write domains, and we can update
3220          * the domain values for our changes.
3221          */
3222         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3223
3224         /* If we're writing through the CPU, then the GPU read domains will
3225          * need to be invalidated at next use.
3226          */
3227         if (write) {
3228                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3229                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3230         }
3231
3232         trace_i915_gem_object_change_domain(obj,
3233                                             old_read_domains,
3234                                             old_write_domain);
3235
3236         return 0;
3237 }
3238
3239 /**
3240  * Moves the object from a partially CPU read to a full one.
3241  *
3242  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3243  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3244  */
3245 static void
3246 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3247 {
3248         if (!obj->page_cpu_valid)
3249                 return;
3250
3251         /* If we're partially in the CPU read domain, finish moving it in.
3252          */
3253         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3254                 int i;
3255
3256                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3257                         if (obj->page_cpu_valid[i])
3258                                 continue;
3259                         drm_clflush_pages(obj->pages + i, 1);
3260                 }
3261         }
3262
3263         /* Free the page_cpu_valid mappings which are now stale, whether
3264          * or not we've got I915_GEM_DOMAIN_CPU.
3265          */
3266         kfree(obj->page_cpu_valid);
3267         obj->page_cpu_valid = NULL;
3268 }
3269
3270 /**
3271  * Set the CPU read domain on a range of the object.
3272  *
3273  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3274  * not entirely valid.  The page_cpu_valid member of the object flags which
3275  * pages have been flushed, and will be respected by
3276  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3277  * of the whole object.
3278  *
3279  * This function returns when the move is complete, including waiting on
3280  * flushes to occur.
3281  */
3282 static int
3283 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3284                                           uint64_t offset, uint64_t size)
3285 {
3286         uint32_t old_read_domains;
3287         int i, ret;
3288
3289         if (offset == 0 && size == obj->base.size)
3290                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3291
3292         ret = i915_gem_object_flush_gpu_write_domain(obj);
3293         if (ret)
3294                 return ret;
3295
3296         ret = i915_gem_object_wait_rendering(obj);
3297         if (ret)
3298                 return ret;
3299
3300         i915_gem_object_flush_gtt_write_domain(obj);
3301
3302         /* If we're already fully in the CPU read domain, we're done. */
3303         if (obj->page_cpu_valid == NULL &&
3304             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3305                 return 0;
3306
3307         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3308          * newly adding I915_GEM_DOMAIN_CPU
3309          */
3310         if (obj->page_cpu_valid == NULL) {
3311                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3312                                               GFP_KERNEL);
3313                 if (obj->page_cpu_valid == NULL)
3314                         return -ENOMEM;
3315         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3316                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3317
3318         /* Flush the cache on any pages that are still invalid from the CPU's
3319          * perspective.
3320          */
3321         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3322              i++) {
3323                 if (obj->page_cpu_valid[i])
3324                         continue;
3325
3326                 drm_clflush_pages(obj->pages + i, 1);
3327
3328                 obj->page_cpu_valid[i] = 1;
3329         }
3330
3331         /* It should now be out of any other write domains, and we can update
3332          * the domain values for our changes.
3333          */
3334         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3335
3336         old_read_domains = obj->base.read_domains;
3337         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3338
3339         trace_i915_gem_object_change_domain(obj,
3340                                             old_read_domains,
3341                                             obj->base.write_domain);
3342
3343         return 0;
3344 }
3345
3346 /* Throttle our rendering by waiting until the ring has completed our requests
3347  * emitted over 20 msec ago.
3348  *
3349  * Note that if we were to use the current jiffies each time around the loop,
3350  * we wouldn't escape the function with any frames outstanding if the time to
3351  * render a frame was over 20ms.
3352  *
3353  * This should get us reasonable parallelism between CPU and GPU but also
3354  * relatively low latency when blocking on a particular request to finish.
3355  */
3356 static int
3357 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3358 {
3359         struct drm_i915_private *dev_priv = dev->dev_private;
3360         struct drm_i915_file_private *file_priv = file->driver_priv;
3361         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3362         struct drm_i915_gem_request *request;
3363         struct intel_ring_buffer *ring = NULL;
3364         u32 seqno = 0;
3365         int ret;
3366
3367         if (atomic_read(&dev_priv->mm.wedged))
3368                 return -EIO;
3369
3370         spin_lock(&file_priv->mm.lock);
3371         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3372                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3373                         break;
3374
3375                 ring = request->ring;
3376                 seqno = request->seqno;
3377         }
3378         spin_unlock(&file_priv->mm.lock);
3379
3380         if (seqno == 0)
3381                 return 0;
3382
3383         ret = 0;
3384         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3385                 /* And wait for the seqno passing without holding any locks and
3386                  * causing extra latency for others. This is safe as the irq
3387                  * generation is designed to be run atomically and so is
3388                  * lockless.
3389                  */
3390                 if (ring->irq_get(ring)) {
3391                         ret = wait_event_interruptible(ring->irq_queue,
3392                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3393                                                        || atomic_read(&dev_priv->mm.wedged));
3394                         ring->irq_put(ring);
3395
3396                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3397                                 ret = -EIO;
3398                 }
3399         }
3400
3401         if (ret == 0)
3402                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3403
3404         return ret;
3405 }
3406
3407 int
3408 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3409                     uint32_t alignment,
3410                     bool map_and_fenceable)
3411 {
3412         struct drm_device *dev = obj->base.dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         int ret;
3415
3416         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3417         WARN_ON(i915_verify_lists(dev));
3418
3419         if (obj->gtt_space != NULL) {
3420                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3421                     (map_and_fenceable && !obj->map_and_fenceable)) {
3422                         WARN(obj->pin_count,
3423                              "bo is already pinned with incorrect alignment:"
3424                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3425                              " obj->map_and_fenceable=%d\n",
3426                              obj->gtt_offset, alignment,
3427                              map_and_fenceable,
3428                              obj->map_and_fenceable);
3429                         ret = i915_gem_object_unbind(obj);
3430                         if (ret)
3431                                 return ret;
3432                 }
3433         }
3434
3435         if (obj->gtt_space == NULL) {
3436                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3437                                                   map_and_fenceable);
3438                 if (ret)
3439                         return ret;
3440         }
3441
3442         if (obj->pin_count++ == 0) {
3443                 if (!obj->active)
3444                         list_move_tail(&obj->mm_list,
3445                                        &dev_priv->mm.pinned_list);
3446         }
3447         obj->pin_mappable |= map_and_fenceable;
3448
3449         WARN_ON(i915_verify_lists(dev));
3450         return 0;
3451 }
3452
3453 void
3454 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3455 {
3456         struct drm_device *dev = obj->base.dev;
3457         drm_i915_private_t *dev_priv = dev->dev_private;
3458
3459         WARN_ON(i915_verify_lists(dev));
3460         BUG_ON(obj->pin_count == 0);
3461         BUG_ON(obj->gtt_space == NULL);
3462
3463         if (--obj->pin_count == 0) {
3464                 if (!obj->active)
3465                         list_move_tail(&obj->mm_list,
3466                                        &dev_priv->mm.inactive_list);
3467                 obj->pin_mappable = false;
3468         }
3469         WARN_ON(i915_verify_lists(dev));
3470 }
3471
3472 int
3473 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3474                    struct drm_file *file)
3475 {
3476         struct drm_i915_gem_pin *args = data;
3477         struct drm_i915_gem_object *obj;
3478         int ret;
3479
3480         ret = i915_mutex_lock_interruptible(dev);
3481         if (ret)
3482                 return ret;
3483
3484         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3485         if (&obj->base == NULL) {
3486                 ret = -ENOENT;
3487                 goto unlock;
3488         }
3489
3490         if (obj->madv != I915_MADV_WILLNEED) {
3491                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3492                 ret = -EINVAL;
3493                 goto out;
3494         }
3495
3496         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3497                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3498                           args->handle);
3499                 ret = -EINVAL;
3500                 goto out;
3501         }
3502
3503         obj->user_pin_count++;
3504         obj->pin_filp = file;
3505         if (obj->user_pin_count == 1) {
3506                 ret = i915_gem_object_pin(obj, args->alignment, true);
3507                 if (ret)
3508                         goto out;
3509         }
3510
3511         /* XXX - flush the CPU caches for pinned objects
3512          * as the X server doesn't manage domains yet
3513          */
3514         i915_gem_object_flush_cpu_write_domain(obj);
3515         args->offset = obj->gtt_offset;
3516 out:
3517         drm_gem_object_unreference(&obj->base);
3518 unlock:
3519         mutex_unlock(&dev->struct_mutex);
3520         return ret;
3521 }
3522
3523 int
3524 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3525                      struct drm_file *file)
3526 {
3527         struct drm_i915_gem_pin *args = data;
3528         struct drm_i915_gem_object *obj;
3529         int ret;
3530
3531         ret = i915_mutex_lock_interruptible(dev);
3532         if (ret)
3533                 return ret;
3534
3535         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3536         if (&obj->base == NULL) {
3537                 ret = -ENOENT;
3538                 goto unlock;
3539         }
3540
3541         if (obj->pin_filp != file) {
3542                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3543                           args->handle);
3544                 ret = -EINVAL;
3545                 goto out;
3546         }
3547         obj->user_pin_count--;
3548         if (obj->user_pin_count == 0) {
3549                 obj->pin_filp = NULL;
3550                 i915_gem_object_unpin(obj);
3551         }
3552
3553 out:
3554         drm_gem_object_unreference(&obj->base);
3555 unlock:
3556         mutex_unlock(&dev->struct_mutex);
3557         return ret;
3558 }
3559
3560 int
3561 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3562                     struct drm_file *file)
3563 {
3564         struct drm_i915_gem_busy *args = data;
3565         struct drm_i915_gem_object *obj;
3566         int ret;
3567
3568         ret = i915_mutex_lock_interruptible(dev);
3569         if (ret)
3570                 return ret;
3571
3572         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3573         if (&obj->base == NULL) {
3574                 ret = -ENOENT;
3575                 goto unlock;
3576         }
3577
3578         /* Count all active objects as busy, even if they are currently not used
3579          * by the gpu. Users of this interface expect objects to eventually
3580          * become non-busy without any further actions, therefore emit any
3581          * necessary flushes here.
3582          */
3583         args->busy = obj->active;
3584         if (args->busy) {
3585                 /* Unconditionally flush objects, even when the gpu still uses this
3586                  * object. Userspace calling this function indicates that it wants to
3587                  * use this buffer rather sooner than later, so issuing the required
3588                  * flush earlier is beneficial.
3589                  */
3590                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3591                         ret = i915_gem_flush_ring(obj->ring,
3592                                                   0, obj->base.write_domain);
3593                 } else if (obj->ring->outstanding_lazy_request ==
3594                            obj->last_rendering_seqno) {
3595                         struct drm_i915_gem_request *request;
3596
3597                         /* This ring is not being cleared by active usage,
3598                          * so emit a request to do so.
3599                          */
3600                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3601                         if (request)
3602                                 ret = i915_add_request(obj->ring, NULL,request);
3603                         else
3604                                 ret = -ENOMEM;
3605                 }
3606
3607                 /* Update the active list for the hardware's current position.
3608                  * Otherwise this only updates on a delayed timer or when irqs
3609                  * are actually unmasked, and our working set ends up being
3610                  * larger than required.
3611                  */
3612                 i915_gem_retire_requests_ring(obj->ring);
3613
3614                 args->busy = obj->active;
3615         }
3616
3617         drm_gem_object_unreference(&obj->base);
3618 unlock:
3619         mutex_unlock(&dev->struct_mutex);
3620         return ret;
3621 }
3622
3623 int
3624 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3625                         struct drm_file *file_priv)
3626 {
3627     return i915_gem_ring_throttle(dev, file_priv);
3628 }
3629
3630 int
3631 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3632                        struct drm_file *file_priv)
3633 {
3634         struct drm_i915_gem_madvise *args = data;
3635         struct drm_i915_gem_object *obj;
3636         int ret;
3637
3638         switch (args->madv) {
3639         case I915_MADV_DONTNEED:
3640         case I915_MADV_WILLNEED:
3641             break;
3642         default:
3643             return -EINVAL;
3644         }
3645
3646         ret = i915_mutex_lock_interruptible(dev);
3647         if (ret)
3648                 return ret;
3649
3650         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3651         if (&obj->base == NULL) {
3652                 ret = -ENOENT;
3653                 goto unlock;
3654         }
3655
3656         if (obj->pin_count) {
3657                 ret = -EINVAL;
3658                 goto out;
3659         }
3660
3661         if (obj->madv != __I915_MADV_PURGED)
3662                 obj->madv = args->madv;
3663
3664         /* if the object is no longer bound, discard its backing storage */
3665         if (i915_gem_object_is_purgeable(obj) &&
3666             obj->gtt_space == NULL)
3667                 i915_gem_object_truncate(obj);
3668
3669         args->retained = obj->madv != __I915_MADV_PURGED;
3670
3671 out:
3672         drm_gem_object_unreference(&obj->base);
3673 unlock:
3674         mutex_unlock(&dev->struct_mutex);
3675         return ret;
3676 }
3677
3678 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3679                                                   size_t size)
3680 {
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682         struct drm_i915_gem_object *obj;
3683         struct address_space *mapping;
3684
3685         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3686         if (obj == NULL)
3687                 return NULL;
3688
3689         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3690                 kfree(obj);
3691                 return NULL;
3692         }
3693
3694         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3695         mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3696
3697         i915_gem_info_add_obj(dev_priv, size);
3698
3699         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3700         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3701
3702         if (IS_GEN6(dev)) {
3703                 /* On Gen6, we can have the GPU use the LLC (the CPU
3704                  * cache) for about a 10% performance improvement
3705                  * compared to uncached.  Graphics requests other than
3706                  * display scanout are coherent with the CPU in
3707                  * accessing this cache.  This means in this mode we
3708                  * don't need to clflush on the CPU side, and on the
3709                  * GPU side we only need to flush internal caches to
3710                  * get data visible to the CPU.
3711                  *
3712                  * However, we maintain the display planes as UC, and so
3713                  * need to rebind when first used as such.
3714                  */
3715                 obj->cache_level = I915_CACHE_LLC;
3716         } else
3717                 obj->cache_level = I915_CACHE_NONE;
3718
3719         obj->base.driver_private = NULL;
3720         obj->fence_reg = I915_FENCE_REG_NONE;
3721         INIT_LIST_HEAD(&obj->mm_list);
3722         INIT_LIST_HEAD(&obj->gtt_list);
3723         INIT_LIST_HEAD(&obj->ring_list);
3724         INIT_LIST_HEAD(&obj->exec_list);
3725         INIT_LIST_HEAD(&obj->gpu_write_list);
3726         obj->madv = I915_MADV_WILLNEED;
3727         /* Avoid an unnecessary call to unbind on the first bind. */
3728         obj->map_and_fenceable = true;
3729
3730         return obj;
3731 }
3732
3733 int i915_gem_init_object(struct drm_gem_object *obj)
3734 {
3735         BUG();
3736
3737         return 0;
3738 }
3739
3740 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3741 {
3742         struct drm_device *dev = obj->base.dev;
3743         drm_i915_private_t *dev_priv = dev->dev_private;
3744         int ret;
3745
3746         ret = i915_gem_object_unbind(obj);
3747         if (ret == -ERESTARTSYS) {
3748                 list_move(&obj->mm_list,
3749                           &dev_priv->mm.deferred_free_list);
3750                 return;
3751         }
3752
3753         trace_i915_gem_object_destroy(obj);
3754
3755         if (obj->base.map_list.map)
3756                 i915_gem_free_mmap_offset(obj);
3757
3758         drm_gem_object_release(&obj->base);
3759         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3760
3761         kfree(obj->page_cpu_valid);
3762         kfree(obj->bit_17);
3763         kfree(obj);
3764 }
3765
3766 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3767 {
3768         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3769         struct drm_device *dev = obj->base.dev;
3770
3771         while (obj->pin_count > 0)
3772                 i915_gem_object_unpin(obj);
3773
3774         if (obj->phys_obj)
3775                 i915_gem_detach_phys_object(dev, obj);
3776
3777         i915_gem_free_object_tail(obj);
3778 }
3779
3780 int
3781 i915_gem_idle(struct drm_device *dev)
3782 {
3783         drm_i915_private_t *dev_priv = dev->dev_private;
3784         int ret;
3785
3786         mutex_lock(&dev->struct_mutex);
3787
3788         if (dev_priv->mm.suspended) {
3789                 mutex_unlock(&dev->struct_mutex);
3790                 return 0;
3791         }
3792
3793         ret = i915_gpu_idle(dev);
3794         if (ret) {
3795                 mutex_unlock(&dev->struct_mutex);
3796                 return ret;
3797         }
3798
3799         /* Under UMS, be paranoid and evict. */
3800         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3801                 ret = i915_gem_evict_inactive(dev, false);
3802                 if (ret) {
3803                         mutex_unlock(&dev->struct_mutex);
3804                         return ret;
3805                 }
3806         }
3807
3808         i915_gem_reset_fences(dev);
3809
3810         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3811          * We need to replace this with a semaphore, or something.
3812          * And not confound mm.suspended!
3813          */
3814         dev_priv->mm.suspended = 1;
3815         del_timer_sync(&dev_priv->hangcheck_timer);
3816
3817         i915_kernel_lost_context(dev);
3818         i915_gem_cleanup_ringbuffer(dev);
3819
3820         mutex_unlock(&dev->struct_mutex);
3821
3822         /* Cancel the retire work handler, which should be idle now. */
3823         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3824
3825         return 0;
3826 }
3827
3828 int
3829 i915_gem_init_ringbuffer(struct drm_device *dev)
3830 {
3831         drm_i915_private_t *dev_priv = dev->dev_private;
3832         int ret;
3833
3834         ret = intel_init_render_ring_buffer(dev);
3835         if (ret)
3836                 return ret;
3837
3838         if (HAS_BSD(dev)) {
3839                 ret = intel_init_bsd_ring_buffer(dev);
3840                 if (ret)
3841                         goto cleanup_render_ring;
3842         }
3843
3844         if (HAS_BLT(dev)) {
3845                 ret = intel_init_blt_ring_buffer(dev);
3846                 if (ret)
3847                         goto cleanup_bsd_ring;
3848         }
3849
3850         dev_priv->next_seqno = 1;
3851
3852         return 0;
3853
3854 cleanup_bsd_ring:
3855         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3856 cleanup_render_ring:
3857         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3858         return ret;
3859 }
3860
3861 void
3862 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3863 {
3864         drm_i915_private_t *dev_priv = dev->dev_private;
3865         int i;
3866
3867         for (i = 0; i < I915_NUM_RINGS; i++)
3868                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3869 }
3870
3871 int
3872 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3873                        struct drm_file *file_priv)
3874 {
3875         drm_i915_private_t *dev_priv = dev->dev_private;
3876         int ret, i;
3877
3878         if (drm_core_check_feature(dev, DRIVER_MODESET))
3879                 return 0;
3880
3881         if (atomic_read(&dev_priv->mm.wedged)) {
3882                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3883                 atomic_set(&dev_priv->mm.wedged, 0);
3884         }
3885
3886         mutex_lock(&dev->struct_mutex);
3887         dev_priv->mm.suspended = 0;
3888
3889         ret = i915_gem_init_ringbuffer(dev);
3890         if (ret != 0) {
3891                 mutex_unlock(&dev->struct_mutex);
3892                 return ret;
3893         }
3894
3895         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3896         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3897         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3898         for (i = 0; i < I915_NUM_RINGS; i++) {
3899                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3900                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3901         }
3902         mutex_unlock(&dev->struct_mutex);
3903
3904         ret = drm_irq_install(dev);
3905         if (ret)
3906                 goto cleanup_ringbuffer;
3907
3908         return 0;
3909
3910 cleanup_ringbuffer:
3911         mutex_lock(&dev->struct_mutex);
3912         i915_gem_cleanup_ringbuffer(dev);
3913         dev_priv->mm.suspended = 1;
3914         mutex_unlock(&dev->struct_mutex);
3915
3916         return ret;
3917 }
3918
3919 int
3920 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3921                        struct drm_file *file_priv)
3922 {
3923         if (drm_core_check_feature(dev, DRIVER_MODESET))
3924                 return 0;
3925
3926         drm_irq_uninstall(dev);
3927         return i915_gem_idle(dev);
3928 }
3929
3930 void
3931 i915_gem_lastclose(struct drm_device *dev)
3932 {
3933         int ret;
3934
3935         if (drm_core_check_feature(dev, DRIVER_MODESET))
3936                 return;
3937
3938         ret = i915_gem_idle(dev);
3939         if (ret)
3940                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3941 }
3942
3943 static void
3944 init_ring_lists(struct intel_ring_buffer *ring)
3945 {
3946         INIT_LIST_HEAD(&ring->active_list);
3947         INIT_LIST_HEAD(&ring->request_list);
3948         INIT_LIST_HEAD(&ring->gpu_write_list);
3949 }
3950
3951 void
3952 i915_gem_load(struct drm_device *dev)
3953 {
3954         int i;
3955         drm_i915_private_t *dev_priv = dev->dev_private;
3956
3957         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3958         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3959         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3960         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3961         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3962         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3963         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3964         for (i = 0; i < I915_NUM_RINGS; i++)
3965                 init_ring_lists(&dev_priv->ring[i]);
3966         for (i = 0; i < 16; i++)
3967                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3968         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3969                           i915_gem_retire_work_handler);
3970         init_completion(&dev_priv->error_completion);
3971
3972         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3973         if (IS_GEN3(dev)) {
3974                 u32 tmp = I915_READ(MI_ARB_STATE);
3975                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3976                         /* arb state is a masked write, so set bit + bit in mask */
3977                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3978                         I915_WRITE(MI_ARB_STATE, tmp);
3979                 }
3980         }
3981
3982         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3983
3984         /* Old X drivers will take 0-2 for front, back, depth buffers */
3985         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3986                 dev_priv->fence_reg_start = 3;
3987
3988         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3989                 dev_priv->num_fence_regs = 16;
3990         else
3991                 dev_priv->num_fence_regs = 8;
3992
3993         /* Initialize fence registers to zero */
3994         for (i = 0; i < dev_priv->num_fence_regs; i++) {
3995                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3996         }
3997
3998         i915_gem_detect_bit_6_swizzle(dev);
3999         init_waitqueue_head(&dev_priv->pending_flip_queue);
4000
4001         dev_priv->mm.interruptible = true;
4002
4003         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4004         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4005         register_shrinker(&dev_priv->mm.inactive_shrinker);
4006 }
4007
4008 /*
4009  * Create a physically contiguous memory object for this object
4010  * e.g. for cursor + overlay regs
4011  */
4012 static int i915_gem_init_phys_object(struct drm_device *dev,
4013                                      int id, int size, int align)
4014 {
4015         drm_i915_private_t *dev_priv = dev->dev_private;
4016         struct drm_i915_gem_phys_object *phys_obj;
4017         int ret;
4018
4019         if (dev_priv->mm.phys_objs[id - 1] || !size)
4020                 return 0;
4021
4022         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4023         if (!phys_obj)
4024                 return -ENOMEM;
4025
4026         phys_obj->id = id;
4027
4028         phys_obj->handle = drm_pci_alloc(dev, size, align);
4029         if (!phys_obj->handle) {
4030                 ret = -ENOMEM;
4031                 goto kfree_obj;
4032         }
4033 #ifdef CONFIG_X86
4034         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4035 #endif
4036
4037         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4038
4039         return 0;
4040 kfree_obj:
4041         kfree(phys_obj);
4042         return ret;
4043 }
4044
4045 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4046 {
4047         drm_i915_private_t *dev_priv = dev->dev_private;
4048         struct drm_i915_gem_phys_object *phys_obj;
4049
4050         if (!dev_priv->mm.phys_objs[id - 1])
4051                 return;
4052
4053         phys_obj = dev_priv->mm.phys_objs[id - 1];
4054         if (phys_obj->cur_obj) {
4055                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4056         }
4057
4058 #ifdef CONFIG_X86
4059         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4060 #endif
4061         drm_pci_free(dev, phys_obj->handle);
4062         kfree(phys_obj);
4063         dev_priv->mm.phys_objs[id - 1] = NULL;
4064 }
4065
4066 void i915_gem_free_all_phys_object(struct drm_device *dev)
4067 {
4068         int i;
4069
4070         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4071                 i915_gem_free_phys_object(dev, i);
4072 }
4073
4074 void i915_gem_detach_phys_object(struct drm_device *dev,
4075                                  struct drm_i915_gem_object *obj)
4076 {
4077         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4078         char *vaddr;
4079         int i;
4080         int page_count;
4081
4082         if (!obj->phys_obj)
4083                 return;
4084         vaddr = obj->phys_obj->handle->vaddr;
4085
4086         page_count = obj->base.size / PAGE_SIZE;
4087         for (i = 0; i < page_count; i++) {
4088                 struct page *page = shmem_read_mapping_page(mapping, i);
4089                 if (!IS_ERR(page)) {
4090                         char *dst = kmap_atomic(page);
4091                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4092                         kunmap_atomic(dst);
4093
4094                         drm_clflush_pages(&page, 1);
4095
4096                         set_page_dirty(page);
4097                         mark_page_accessed(page);
4098                         page_cache_release(page);
4099                 }
4100         }
4101         intel_gtt_chipset_flush();
4102
4103         obj->phys_obj->cur_obj = NULL;
4104         obj->phys_obj = NULL;
4105 }
4106
4107 int
4108 i915_gem_attach_phys_object(struct drm_device *dev,
4109                             struct drm_i915_gem_object *obj,
4110                             int id,
4111                             int align)
4112 {
4113         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4114         drm_i915_private_t *dev_priv = dev->dev_private;
4115         int ret = 0;
4116         int page_count;
4117         int i;
4118
4119         if (id > I915_MAX_PHYS_OBJECT)
4120                 return -EINVAL;
4121
4122         if (obj->phys_obj) {
4123                 if (obj->phys_obj->id == id)
4124                         return 0;
4125                 i915_gem_detach_phys_object(dev, obj);
4126         }
4127
4128         /* create a new object */
4129         if (!dev_priv->mm.phys_objs[id - 1]) {
4130                 ret = i915_gem_init_phys_object(dev, id,
4131                                                 obj->base.size, align);
4132                 if (ret) {
4133                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4134                                   id, obj->base.size);
4135                         return ret;
4136                 }
4137         }
4138
4139         /* bind to the object */
4140         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4141         obj->phys_obj->cur_obj = obj;
4142
4143         page_count = obj->base.size / PAGE_SIZE;
4144
4145         for (i = 0; i < page_count; i++) {
4146                 struct page *page;
4147                 char *dst, *src;
4148
4149                 page = shmem_read_mapping_page(mapping, i);
4150                 if (IS_ERR(page))
4151                         return PTR_ERR(page);
4152
4153                 src = kmap_atomic(page);
4154                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4155                 memcpy(dst, src, PAGE_SIZE);
4156                 kunmap_atomic(src);
4157
4158                 mark_page_accessed(page);
4159                 page_cache_release(page);
4160         }
4161
4162         return 0;
4163 }
4164
4165 static int
4166 i915_gem_phys_pwrite(struct drm_device *dev,
4167                      struct drm_i915_gem_object *obj,
4168                      struct drm_i915_gem_pwrite *args,
4169                      struct drm_file *file_priv)
4170 {
4171         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4172         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4173
4174         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4175                 unsigned long unwritten;
4176
4177                 /* The physical object once assigned is fixed for the lifetime
4178                  * of the obj, so we can safely drop the lock and continue
4179                  * to access vaddr.
4180                  */
4181                 mutex_unlock(&dev->struct_mutex);
4182                 unwritten = copy_from_user(vaddr, user_data, args->size);
4183                 mutex_lock(&dev->struct_mutex);
4184                 if (unwritten)
4185                         return -EFAULT;
4186         }
4187
4188         intel_gtt_chipset_flush();
4189         return 0;
4190 }
4191
4192 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4193 {
4194         struct drm_i915_file_private *file_priv = file->driver_priv;
4195
4196         /* Clean up our request list when the client is going away, so that
4197          * later retire_requests won't dereference our soon-to-be-gone
4198          * file_priv.
4199          */
4200         spin_lock(&file_priv->mm.lock);
4201         while (!list_empty(&file_priv->mm.request_list)) {
4202                 struct drm_i915_gem_request *request;
4203
4204                 request = list_first_entry(&file_priv->mm.request_list,
4205                                            struct drm_i915_gem_request,
4206                                            client_list);
4207                 list_del(&request->client_list);
4208                 request->file_priv = NULL;
4209         }
4210         spin_unlock(&file_priv->mm.lock);
4211 }
4212
4213 static int
4214 i915_gpu_is_active(struct drm_device *dev)
4215 {
4216         drm_i915_private_t *dev_priv = dev->dev_private;
4217         int lists_empty;
4218
4219         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4220                       list_empty(&dev_priv->mm.active_list);
4221
4222         return !lists_empty;
4223 }
4224
4225 static int
4226 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4227 {
4228         struct drm_i915_private *dev_priv =
4229                 container_of(shrinker,
4230                              struct drm_i915_private,
4231                              mm.inactive_shrinker);
4232         struct drm_device *dev = dev_priv->dev;
4233         struct drm_i915_gem_object *obj, *next;
4234         int nr_to_scan = sc->nr_to_scan;
4235         int cnt;
4236
4237         if (!mutex_trylock(&dev->struct_mutex))
4238                 return 0;
4239
4240         /* "fast-path" to count number of available objects */
4241         if (nr_to_scan == 0) {
4242                 cnt = 0;
4243                 list_for_each_entry(obj,
4244                                     &dev_priv->mm.inactive_list,
4245                                     mm_list)
4246                         cnt++;
4247                 mutex_unlock(&dev->struct_mutex);
4248                 return cnt / 100 * sysctl_vfs_cache_pressure;
4249         }
4250
4251 rescan:
4252         /* first scan for clean buffers */
4253         i915_gem_retire_requests(dev);
4254
4255         list_for_each_entry_safe(obj, next,
4256                                  &dev_priv->mm.inactive_list,
4257                                  mm_list) {
4258                 if (i915_gem_object_is_purgeable(obj)) {
4259                         if (i915_gem_object_unbind(obj) == 0 &&
4260                             --nr_to_scan == 0)
4261                                 break;
4262                 }
4263         }
4264
4265         /* second pass, evict/count anything still on the inactive list */
4266         cnt = 0;
4267         list_for_each_entry_safe(obj, next,
4268                                  &dev_priv->mm.inactive_list,
4269                                  mm_list) {
4270                 if (nr_to_scan &&
4271                     i915_gem_object_unbind(obj) == 0)
4272                         nr_to_scan--;
4273                 else
4274                         cnt++;
4275         }
4276
4277         if (nr_to_scan && i915_gpu_is_active(dev)) {
4278                 /*
4279                  * We are desperate for pages, so as a last resort, wait
4280                  * for the GPU to finish and discard whatever we can.
4281                  * This has a dramatic impact to reduce the number of
4282                  * OOM-killer events whilst running the GPU aggressively.
4283                  */
4284                 if (i915_gpu_idle(dev) == 0)
4285                         goto rescan;
4286         }
4287         mutex_unlock(&dev->struct_mutex);
4288         return cnt / 100 * sysctl_vfs_cache_pressure;
4289 }