2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1206 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1208 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1213 /* Need a new fence register? */
1214 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1215 ret = i915_gem_object_get_fence_reg(obj);
1220 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1223 /* Finally, remap it using the new GTT offset */
1224 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1226 mutex_unlock(&dev->struct_mutex);
1231 return VM_FAULT_NOPAGE;
1234 return VM_FAULT_OOM;
1236 return VM_FAULT_SIGBUS;
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1249 * This routine allocates and attaches a fake offset for @obj.
1252 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1254 struct drm_device *dev = obj->dev;
1255 struct drm_gem_mm *mm = dev->mm_private;
1256 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1257 struct drm_map_list *list;
1258 struct drm_local_map *map;
1261 /* Set the object up for mmap'ing */
1262 list = &obj->map_list;
1263 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1268 map->type = _DRM_GEM;
1269 map->size = obj->size;
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1274 obj->size / PAGE_SIZE, 0, 0);
1275 if (!list->file_offset_node) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1281 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1282 obj->size / PAGE_SIZE, 0);
1283 if (!list->file_offset_node) {
1288 list->hash.key = list->file_offset_node->start;
1289 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1290 DRM_ERROR("failed to add to map hash\n");
1295 /* By now we should be all set, any drm_mmap request on the offset
1296 * below will get to our mmap & fault handler */
1297 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1302 drm_mm_put_block(list->file_offset_node);
1310 * i915_gem_release_mmap - remove physical page mappings
1311 * @obj: obj in question
1313 * Preserve the reservation of the mmapping with the DRM core code, but
1314 * relinquish ownership of the pages back to the system.
1316 * It is vital that we remove the page mapping if we have mapped a tiled
1317 * object through the GTT and then lose the fence register due to
1318 * resource pressure. Similarly if the object has been moved out of the
1319 * aperture, than pages mapped into userspace must be revoked. Removing the
1320 * mapping will then trigger a page fault on the next user access, allowing
1321 * fixup by i915_gem_fault().
1324 i915_gem_release_mmap(struct drm_gem_object *obj)
1326 struct drm_device *dev = obj->dev;
1327 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1329 if (dev->dev_mapping)
1330 unmap_mapping_range(dev->dev_mapping,
1331 obj_priv->mmap_offset, obj->size, 1);
1335 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1337 struct drm_device *dev = obj->dev;
1338 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1339 struct drm_gem_mm *mm = dev->mm_private;
1340 struct drm_map_list *list;
1342 list = &obj->map_list;
1343 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1345 if (list->file_offset_node) {
1346 drm_mm_put_block(list->file_offset_node);
1347 list->file_offset_node = NULL;
1355 obj_priv->mmap_offset = 0;
1359 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1360 * @obj: object to check
1362 * Return the required GTT alignment for an object, taking into account
1363 * potential fence register mapping if needed.
1366 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1368 struct drm_device *dev = obj->dev;
1369 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1373 * Minimum alignment is 4k (GTT page size), but might be greater
1374 * if a fence register is needed for the object.
1376 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1380 * Previous chips need to be aligned to the size of the smallest
1381 * fence register that can contain the object.
1388 for (i = start; i < obj->size; i <<= 1)
1395 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1397 * @data: GTT mapping ioctl data
1398 * @file_priv: GEM object info
1400 * Simply returns the fake offset to userspace so it can mmap it.
1401 * The mmap call will end up in drm_gem_mmap(), which will set things
1402 * up so we can get faults in the handler above.
1404 * The fault handler will take care of binding the object into the GTT
1405 * (since it may have been evicted to make room for something), allocating
1406 * a fence register, and mapping the appropriate aperture address into
1410 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1411 struct drm_file *file_priv)
1413 struct drm_i915_gem_mmap_gtt *args = data;
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415 struct drm_gem_object *obj;
1416 struct drm_i915_gem_object *obj_priv;
1419 if (!(dev->driver->driver_features & DRIVER_GEM))
1422 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1426 mutex_lock(&dev->struct_mutex);
1428 obj_priv = obj->driver_private;
1430 if (obj_priv->madv != I915_MADV_WILLNEED) {
1431 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1432 drm_gem_object_unreference(obj);
1433 mutex_unlock(&dev->struct_mutex);
1438 if (!obj_priv->mmap_offset) {
1439 ret = i915_gem_create_mmap_offset(obj);
1441 drm_gem_object_unreference(obj);
1442 mutex_unlock(&dev->struct_mutex);
1447 args->offset = obj_priv->mmap_offset;
1450 * Pull it into the GTT so that we have a page list (makes the
1451 * initial fault faster and any subsequent flushing possible).
1453 if (!obj_priv->agp_mem) {
1454 ret = i915_gem_object_bind_to_gtt(obj, 0);
1456 drm_gem_object_unreference(obj);
1457 mutex_unlock(&dev->struct_mutex);
1460 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1463 drm_gem_object_unreference(obj);
1464 mutex_unlock(&dev->struct_mutex);
1470 i915_gem_object_put_pages(struct drm_gem_object *obj)
1472 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1473 int page_count = obj->size / PAGE_SIZE;
1476 BUG_ON(obj_priv->pages_refcount == 0);
1477 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1479 if (--obj_priv->pages_refcount != 0)
1482 if (obj_priv->tiling_mode != I915_TILING_NONE)
1483 i915_gem_object_save_bit_17_swizzle(obj);
1485 if (obj_priv->madv == I915_MADV_DONTNEED)
1486 obj_priv->dirty = 0;
1488 for (i = 0; i < page_count; i++) {
1489 if (obj_priv->pages[i] == NULL)
1492 if (obj_priv->dirty)
1493 set_page_dirty(obj_priv->pages[i]);
1495 if (obj_priv->madv == I915_MADV_WILLNEED)
1496 mark_page_accessed(obj_priv->pages[i]);
1498 page_cache_release(obj_priv->pages[i]);
1500 obj_priv->dirty = 0;
1502 drm_free_large(obj_priv->pages);
1503 obj_priv->pages = NULL;
1507 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1509 struct drm_device *dev = obj->dev;
1510 drm_i915_private_t *dev_priv = dev->dev_private;
1511 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1513 /* Add a reference if we're newly entering the active list. */
1514 if (!obj_priv->active) {
1515 drm_gem_object_reference(obj);
1516 obj_priv->active = 1;
1518 /* Move from whatever list we were on to the tail of execution. */
1519 spin_lock(&dev_priv->mm.active_list_lock);
1520 list_move_tail(&obj_priv->list,
1521 &dev_priv->mm.active_list);
1522 spin_unlock(&dev_priv->mm.active_list_lock);
1523 obj_priv->last_rendering_seqno = seqno;
1527 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1529 struct drm_device *dev = obj->dev;
1530 drm_i915_private_t *dev_priv = dev->dev_private;
1531 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1533 BUG_ON(!obj_priv->active);
1534 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1535 obj_priv->last_rendering_seqno = 0;
1538 /* Immediately discard the backing storage */
1540 i915_gem_object_truncate(struct drm_gem_object *obj)
1542 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1543 struct inode *inode;
1545 inode = obj->filp->f_path.dentry->d_inode;
1546 if (inode->i_op->truncate)
1547 inode->i_op->truncate (inode);
1549 obj_priv->madv = __I915_MADV_PURGED;
1553 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1555 return obj_priv->madv == I915_MADV_DONTNEED;
1559 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1561 struct drm_device *dev = obj->dev;
1562 drm_i915_private_t *dev_priv = dev->dev_private;
1563 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1565 i915_verify_inactive(dev, __FILE__, __LINE__);
1566 if (obj_priv->pin_count != 0)
1567 list_del_init(&obj_priv->list);
1569 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1571 obj_priv->last_rendering_seqno = 0;
1572 if (obj_priv->active) {
1573 obj_priv->active = 0;
1574 drm_gem_object_unreference(obj);
1576 i915_verify_inactive(dev, __FILE__, __LINE__);
1580 * Creates a new sequence number, emitting a write of it to the status page
1581 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1583 * Must be called with struct_lock held.
1585 * Returned sequence numbers are nonzero on success.
1588 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1589 uint32_t flush_domains)
1591 drm_i915_private_t *dev_priv = dev->dev_private;
1592 struct drm_i915_file_private *i915_file_priv = NULL;
1593 struct drm_i915_gem_request *request;
1598 if (file_priv != NULL)
1599 i915_file_priv = file_priv->driver_priv;
1601 request = kzalloc(sizeof(*request), GFP_KERNEL);
1602 if (request == NULL)
1605 /* Grab the seqno we're going to make this request be, and bump the
1606 * next (skipping 0 so it can be the reserved no-seqno value).
1608 seqno = dev_priv->mm.next_gem_seqno;
1609 dev_priv->mm.next_gem_seqno++;
1610 if (dev_priv->mm.next_gem_seqno == 0)
1611 dev_priv->mm.next_gem_seqno++;
1614 OUT_RING(MI_STORE_DWORD_INDEX);
1615 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1618 OUT_RING(MI_USER_INTERRUPT);
1621 DRM_DEBUG_DRIVER("%d\n", seqno);
1623 request->seqno = seqno;
1624 request->emitted_jiffies = jiffies;
1625 was_empty = list_empty(&dev_priv->mm.request_list);
1626 list_add_tail(&request->list, &dev_priv->mm.request_list);
1627 if (i915_file_priv) {
1628 list_add_tail(&request->client_list,
1629 &i915_file_priv->mm.request_list);
1631 INIT_LIST_HEAD(&request->client_list);
1634 /* Associate any objects on the flushing list matching the write
1635 * domain we're flushing with our flush.
1637 if (flush_domains != 0) {
1638 struct drm_i915_gem_object *obj_priv, *next;
1640 list_for_each_entry_safe(obj_priv, next,
1641 &dev_priv->mm.flushing_list, list) {
1642 struct drm_gem_object *obj = obj_priv->obj;
1644 if ((obj->write_domain & flush_domains) ==
1645 obj->write_domain) {
1646 uint32_t old_write_domain = obj->write_domain;
1648 obj->write_domain = 0;
1649 i915_gem_object_move_to_active(obj, seqno);
1651 trace_i915_gem_object_change_domain(obj,
1659 if (!dev_priv->mm.suspended) {
1660 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1662 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1668 * Command execution barrier
1670 * Ensures that all commands in the ring are finished
1671 * before signalling the CPU
1674 i915_retire_commands(struct drm_device *dev)
1676 drm_i915_private_t *dev_priv = dev->dev_private;
1677 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1678 uint32_t flush_domains = 0;
1681 /* The sampler always gets flushed on i965 (sigh) */
1683 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1686 OUT_RING(0); /* noop */
1688 return flush_domains;
1692 * Moves buffers associated only with the given active seqno from the active
1693 * to inactive list, potentially freeing them.
1696 i915_gem_retire_request(struct drm_device *dev,
1697 struct drm_i915_gem_request *request)
1699 drm_i915_private_t *dev_priv = dev->dev_private;
1701 trace_i915_gem_request_retire(dev, request->seqno);
1703 /* Move any buffers on the active list that are no longer referenced
1704 * by the ringbuffer to the flushing/inactive lists as appropriate.
1706 spin_lock(&dev_priv->mm.active_list_lock);
1707 while (!list_empty(&dev_priv->mm.active_list)) {
1708 struct drm_gem_object *obj;
1709 struct drm_i915_gem_object *obj_priv;
1711 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1712 struct drm_i915_gem_object,
1714 obj = obj_priv->obj;
1716 /* If the seqno being retired doesn't match the oldest in the
1717 * list, then the oldest in the list must still be newer than
1720 if (obj_priv->last_rendering_seqno != request->seqno)
1724 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1725 __func__, request->seqno, obj);
1728 if (obj->write_domain != 0)
1729 i915_gem_object_move_to_flushing(obj);
1731 /* Take a reference on the object so it won't be
1732 * freed while the spinlock is held. The list
1733 * protection for this spinlock is safe when breaking
1734 * the lock like this since the next thing we do
1735 * is just get the head of the list again.
1737 drm_gem_object_reference(obj);
1738 i915_gem_object_move_to_inactive(obj);
1739 spin_unlock(&dev_priv->mm.active_list_lock);
1740 drm_gem_object_unreference(obj);
1741 spin_lock(&dev_priv->mm.active_list_lock);
1745 spin_unlock(&dev_priv->mm.active_list_lock);
1749 * Returns true if seq1 is later than seq2.
1752 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1754 return (int32_t)(seq1 - seq2) >= 0;
1758 i915_get_gem_seqno(struct drm_device *dev)
1760 drm_i915_private_t *dev_priv = dev->dev_private;
1762 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1766 * This function clears the request list as sequence numbers are passed.
1769 i915_gem_retire_requests(struct drm_device *dev)
1771 drm_i915_private_t *dev_priv = dev->dev_private;
1774 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1777 seqno = i915_get_gem_seqno(dev);
1779 while (!list_empty(&dev_priv->mm.request_list)) {
1780 struct drm_i915_gem_request *request;
1781 uint32_t retiring_seqno;
1783 request = list_first_entry(&dev_priv->mm.request_list,
1784 struct drm_i915_gem_request,
1786 retiring_seqno = request->seqno;
1788 if (i915_seqno_passed(seqno, retiring_seqno) ||
1789 atomic_read(&dev_priv->mm.wedged)) {
1790 i915_gem_retire_request(dev, request);
1792 list_del(&request->list);
1793 list_del(&request->client_list);
1799 if (unlikely (dev_priv->trace_irq_seqno &&
1800 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1801 i915_user_irq_put(dev);
1802 dev_priv->trace_irq_seqno = 0;
1807 i915_gem_retire_work_handler(struct work_struct *work)
1809 drm_i915_private_t *dev_priv;
1810 struct drm_device *dev;
1812 dev_priv = container_of(work, drm_i915_private_t,
1813 mm.retire_work.work);
1814 dev = dev_priv->dev;
1816 mutex_lock(&dev->struct_mutex);
1817 i915_gem_retire_requests(dev);
1818 if (!dev_priv->mm.suspended &&
1819 !list_empty(&dev_priv->mm.request_list))
1820 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1821 mutex_unlock(&dev->struct_mutex);
1825 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1827 drm_i915_private_t *dev_priv = dev->dev_private;
1833 if (atomic_read(&dev_priv->mm.wedged))
1836 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1837 if (IS_IRONLAKE(dev))
1838 ier = I915_READ(DEIER) | I915_READ(GTIER);
1840 ier = I915_READ(IER);
1842 DRM_ERROR("something (likely vbetool) disabled "
1843 "interrupts, re-enabling\n");
1844 i915_driver_irq_preinstall(dev);
1845 i915_driver_irq_postinstall(dev);
1848 trace_i915_gem_request_wait_begin(dev, seqno);
1850 dev_priv->mm.waiting_gem_seqno = seqno;
1851 i915_user_irq_get(dev);
1853 ret = wait_event_interruptible(dev_priv->irq_queue,
1854 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1855 atomic_read(&dev_priv->mm.wedged));
1857 wait_event(dev_priv->irq_queue,
1858 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1859 atomic_read(&dev_priv->mm.wedged));
1861 i915_user_irq_put(dev);
1862 dev_priv->mm.waiting_gem_seqno = 0;
1864 trace_i915_gem_request_wait_end(dev, seqno);
1866 if (atomic_read(&dev_priv->mm.wedged))
1869 if (ret && ret != -ERESTARTSYS)
1870 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871 __func__, ret, seqno, i915_get_gem_seqno(dev));
1873 /* Directly dispatch request retiring. While we have the work queue
1874 * to handle this, the waiter on a request often wants an associated
1875 * buffer to have made it to the inactive list, and we would need
1876 * a separate wait queue to handle that.
1879 i915_gem_retire_requests(dev);
1885 * Waits for a sequence number to be signaled, and cleans up the
1886 * request and object lists appropriately for that event.
1889 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1891 return i915_do_wait_request(dev, seqno, 1);
1895 i915_gem_flush(struct drm_device *dev,
1896 uint32_t invalidate_domains,
1897 uint32_t flush_domains)
1899 drm_i915_private_t *dev_priv = dev->dev_private;
1904 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1905 invalidate_domains, flush_domains);
1907 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1908 invalidate_domains, flush_domains);
1910 if (flush_domains & I915_GEM_DOMAIN_CPU)
1911 drm_agp_chipset_flush(dev);
1913 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1915 * read/write caches:
1917 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1918 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1919 * also flushed at 2d versus 3d pipeline switches.
1923 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1924 * MI_READ_FLUSH is set, and is always flushed on 965.
1926 * I915_GEM_DOMAIN_COMMAND may not exist?
1928 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1929 * invalidated when MI_EXE_FLUSH is set.
1931 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1932 * invalidated with every MI_FLUSH.
1936 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1937 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1938 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1939 * are flushed at any MI_FLUSH.
1942 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1943 if ((invalidate_domains|flush_domains) &
1944 I915_GEM_DOMAIN_RENDER)
1945 cmd &= ~MI_NO_WRITE_FLUSH;
1946 if (!IS_I965G(dev)) {
1948 * On the 965, the sampler cache always gets flushed
1949 * and this bit is reserved.
1951 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1952 cmd |= MI_READ_FLUSH;
1954 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1955 cmd |= MI_EXE_FLUSH;
1958 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1968 * Ensures that all rendering to the object has completed and the object is
1969 * safe to unbind from the GTT or access from the CPU.
1972 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1974 struct drm_device *dev = obj->dev;
1975 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1978 /* This function only exists to support waiting for existing rendering,
1979 * not for emitting required flushes.
1981 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1983 /* If there is rendering queued on the buffer being evicted, wait for
1986 if (obj_priv->active) {
1988 DRM_INFO("%s: object %p wait for seqno %08x\n",
1989 __func__, obj, obj_priv->last_rendering_seqno);
1991 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
2000 * Unbinds an object from the GTT aperture.
2003 i915_gem_object_unbind(struct drm_gem_object *obj)
2005 struct drm_device *dev = obj->dev;
2006 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2010 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2011 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2013 if (obj_priv->gtt_space == NULL)
2016 if (obj_priv->pin_count != 0) {
2017 DRM_ERROR("Attempting to unbind pinned buffer\n");
2021 /* blow away mappings if mapped through GTT */
2022 i915_gem_release_mmap(obj);
2024 /* Move the object to the CPU domain to ensure that
2025 * any possible CPU writes while it's not in the GTT
2026 * are flushed when we go to remap it. This will
2027 * also ensure that all pending GPU writes are finished
2030 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2032 if (ret != -ERESTARTSYS)
2033 DRM_ERROR("set_domain failed: %d\n", ret);
2037 BUG_ON(obj_priv->active);
2039 /* release the fence reg _after_ flushing */
2040 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2041 i915_gem_clear_fence_reg(obj);
2043 if (obj_priv->agp_mem != NULL) {
2044 drm_unbind_agp(obj_priv->agp_mem);
2045 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2046 obj_priv->agp_mem = NULL;
2049 i915_gem_object_put_pages(obj);
2050 BUG_ON(obj_priv->pages_refcount);
2052 if (obj_priv->gtt_space) {
2053 atomic_dec(&dev->gtt_count);
2054 atomic_sub(obj->size, &dev->gtt_memory);
2056 drm_mm_put_block(obj_priv->gtt_space);
2057 obj_priv->gtt_space = NULL;
2060 /* Remove ourselves from the LRU list if present. */
2061 if (!list_empty(&obj_priv->list))
2062 list_del_init(&obj_priv->list);
2064 if (i915_gem_object_is_purgeable(obj_priv))
2065 i915_gem_object_truncate(obj);
2067 trace_i915_gem_object_unbind(obj);
2072 static struct drm_gem_object *
2073 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2075 drm_i915_private_t *dev_priv = dev->dev_private;
2076 struct drm_i915_gem_object *obj_priv;
2077 struct drm_gem_object *best = NULL;
2078 struct drm_gem_object *first = NULL;
2080 /* Try to find the smallest clean object */
2081 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2082 struct drm_gem_object *obj = obj_priv->obj;
2083 if (obj->size >= min_size) {
2084 if ((!obj_priv->dirty ||
2085 i915_gem_object_is_purgeable(obj_priv)) &&
2086 (!best || obj->size < best->size)) {
2088 if (best->size == min_size)
2096 return best ? best : first;
2100 i915_gem_evict_everything(struct drm_device *dev)
2102 drm_i915_private_t *dev_priv = dev->dev_private;
2107 spin_lock(&dev_priv->mm.active_list_lock);
2108 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2109 list_empty(&dev_priv->mm.flushing_list) &&
2110 list_empty(&dev_priv->mm.active_list));
2111 spin_unlock(&dev_priv->mm.active_list_lock);
2116 /* Flush everything (on to the inactive lists) and evict */
2117 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2118 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2122 ret = i915_wait_request(dev, seqno);
2126 ret = i915_gem_evict_from_inactive_list(dev);
2130 spin_lock(&dev_priv->mm.active_list_lock);
2131 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2132 list_empty(&dev_priv->mm.flushing_list) &&
2133 list_empty(&dev_priv->mm.active_list));
2134 spin_unlock(&dev_priv->mm.active_list_lock);
2135 BUG_ON(!lists_empty);
2141 i915_gem_evict_something(struct drm_device *dev, int min_size)
2143 drm_i915_private_t *dev_priv = dev->dev_private;
2144 struct drm_gem_object *obj;
2148 i915_gem_retire_requests(dev);
2150 /* If there's an inactive buffer available now, grab it
2153 obj = i915_gem_find_inactive_object(dev, min_size);
2155 struct drm_i915_gem_object *obj_priv;
2158 DRM_INFO("%s: evicting %p\n", __func__, obj);
2160 obj_priv = obj->driver_private;
2161 BUG_ON(obj_priv->pin_count != 0);
2162 BUG_ON(obj_priv->active);
2164 /* Wait on the rendering and unbind the buffer. */
2165 return i915_gem_object_unbind(obj);
2168 /* If we didn't get anything, but the ring is still processing
2169 * things, wait for the next to finish and hopefully leave us
2170 * a buffer to evict.
2172 if (!list_empty(&dev_priv->mm.request_list)) {
2173 struct drm_i915_gem_request *request;
2175 request = list_first_entry(&dev_priv->mm.request_list,
2176 struct drm_i915_gem_request,
2179 ret = i915_wait_request(dev, request->seqno);
2186 /* If we didn't have anything on the request list but there
2187 * are buffers awaiting a flush, emit one and try again.
2188 * When we wait on it, those buffers waiting for that flush
2189 * will get moved to inactive.
2191 if (!list_empty(&dev_priv->mm.flushing_list)) {
2192 struct drm_i915_gem_object *obj_priv;
2194 /* Find an object that we can immediately reuse */
2195 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2196 obj = obj_priv->obj;
2197 if (obj->size >= min_size)
2209 seqno = i915_add_request(dev, NULL, obj->write_domain);
2213 ret = i915_wait_request(dev, seqno);
2221 /* If we didn't do any of the above, there's no single buffer
2222 * large enough to swap out for the new one, so just evict
2223 * everything and start again. (This should be rare.)
2225 if (!list_empty (&dev_priv->mm.inactive_list))
2226 return i915_gem_evict_from_inactive_list(dev);
2228 return i915_gem_evict_everything(dev);
2233 i915_gem_object_get_pages(struct drm_gem_object *obj)
2235 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2237 struct address_space *mapping;
2238 struct inode *inode;
2242 if (obj_priv->pages_refcount++ != 0)
2245 /* Get the list of pages out of our struct file. They'll be pinned
2246 * at this point until we release them.
2248 page_count = obj->size / PAGE_SIZE;
2249 BUG_ON(obj_priv->pages != NULL);
2250 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2251 if (obj_priv->pages == NULL) {
2252 obj_priv->pages_refcount--;
2256 inode = obj->filp->f_path.dentry->d_inode;
2257 mapping = inode->i_mapping;
2258 for (i = 0; i < page_count; i++) {
2259 page = read_mapping_page(mapping, i, NULL);
2261 ret = PTR_ERR(page);
2262 i915_gem_object_put_pages(obj);
2265 obj_priv->pages[i] = page;
2268 if (obj_priv->tiling_mode != I915_TILING_NONE)
2269 i915_gem_object_do_bit_17_swizzle(obj);
2274 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2276 struct drm_gem_object *obj = reg->obj;
2277 struct drm_device *dev = obj->dev;
2278 drm_i915_private_t *dev_priv = dev->dev_private;
2279 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2280 int regnum = obj_priv->fence_reg;
2283 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2285 val |= obj_priv->gtt_offset & 0xfffff000;
2286 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2287 if (obj_priv->tiling_mode == I915_TILING_Y)
2288 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2289 val |= I965_FENCE_REG_VALID;
2291 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2294 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2296 struct drm_gem_object *obj = reg->obj;
2297 struct drm_device *dev = obj->dev;
2298 drm_i915_private_t *dev_priv = dev->dev_private;
2299 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2300 int regnum = obj_priv->fence_reg;
2302 uint32_t fence_reg, val;
2305 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2306 (obj_priv->gtt_offset & (obj->size - 1))) {
2307 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2308 __func__, obj_priv->gtt_offset, obj->size);
2312 if (obj_priv->tiling_mode == I915_TILING_Y &&
2313 HAS_128_BYTE_Y_TILING(dev))
2318 /* Note: pitch better be a power of two tile widths */
2319 pitch_val = obj_priv->stride / tile_width;
2320 pitch_val = ffs(pitch_val) - 1;
2322 val = obj_priv->gtt_offset;
2323 if (obj_priv->tiling_mode == I915_TILING_Y)
2324 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2325 val |= I915_FENCE_SIZE_BITS(obj->size);
2326 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2327 val |= I830_FENCE_REG_VALID;
2330 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2332 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2333 I915_WRITE(fence_reg, val);
2336 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2338 struct drm_gem_object *obj = reg->obj;
2339 struct drm_device *dev = obj->dev;
2340 drm_i915_private_t *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2342 int regnum = obj_priv->fence_reg;
2345 uint32_t fence_size_bits;
2347 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2348 (obj_priv->gtt_offset & (obj->size - 1))) {
2349 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2350 __func__, obj_priv->gtt_offset);
2354 pitch_val = obj_priv->stride / 128;
2355 pitch_val = ffs(pitch_val) - 1;
2356 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2358 val = obj_priv->gtt_offset;
2359 if (obj_priv->tiling_mode == I915_TILING_Y)
2360 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2361 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2362 WARN_ON(fence_size_bits & ~0x00000f00);
2363 val |= fence_size_bits;
2364 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2365 val |= I830_FENCE_REG_VALID;
2367 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2371 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2372 * @obj: object to map through a fence reg
2374 * When mapping objects through the GTT, userspace wants to be able to write
2375 * to them without having to worry about swizzling if the object is tiled.
2377 * This function walks the fence regs looking for a free one for @obj,
2378 * stealing one if it can't find any.
2380 * It then sets up the reg based on the object's properties: address, pitch
2381 * and tiling format.
2384 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2386 struct drm_device *dev = obj->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2389 struct drm_i915_fence_reg *reg = NULL;
2390 struct drm_i915_gem_object *old_obj_priv = NULL;
2393 /* Just update our place in the LRU if our fence is getting used. */
2394 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2395 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2399 switch (obj_priv->tiling_mode) {
2400 case I915_TILING_NONE:
2401 WARN(1, "allocating a fence for non-tiled object?\n");
2404 if (!obj_priv->stride)
2406 WARN((obj_priv->stride & (512 - 1)),
2407 "object 0x%08x is X tiled but has non-512B pitch\n",
2408 obj_priv->gtt_offset);
2411 if (!obj_priv->stride)
2413 WARN((obj_priv->stride & (128 - 1)),
2414 "object 0x%08x is Y tiled but has non-128B pitch\n",
2415 obj_priv->gtt_offset);
2419 /* First try to find a free reg */
2421 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2422 reg = &dev_priv->fence_regs[i];
2426 old_obj_priv = reg->obj->driver_private;
2427 if (!old_obj_priv->pin_count)
2431 /* None available, try to steal one or wait for a user to finish */
2432 if (i == dev_priv->num_fence_regs) {
2433 struct drm_gem_object *old_obj = NULL;
2438 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2440 old_obj = old_obj_priv->obj;
2442 if (old_obj_priv->pin_count)
2445 /* Take a reference, as otherwise the wait_rendering
2446 * below may cause the object to get freed out from
2449 drm_gem_object_reference(old_obj);
2451 /* i915 uses fences for GPU access to tiled buffers */
2452 if (IS_I965G(dev) || !old_obj_priv->active)
2455 /* This brings the object to the head of the LRU if it
2456 * had been written to. The only way this should
2457 * result in us waiting longer than the expected
2458 * optimal amount of time is if there was a
2459 * fence-using buffer later that was read-only.
2461 i915_gem_object_flush_gpu_write_domain(old_obj);
2462 ret = i915_gem_object_wait_rendering(old_obj);
2464 drm_gem_object_unreference(old_obj);
2472 * Zap this virtual mapping so we can set up a fence again
2473 * for this object next time we need it.
2475 i915_gem_release_mmap(old_obj);
2477 i = old_obj_priv->fence_reg;
2478 reg = &dev_priv->fence_regs[i];
2480 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2481 list_del_init(&old_obj_priv->fence_list);
2483 drm_gem_object_unreference(old_obj);
2486 obj_priv->fence_reg = i;
2487 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2492 i965_write_fence_reg(reg);
2493 else if (IS_I9XX(dev))
2494 i915_write_fence_reg(reg);
2496 i830_write_fence_reg(reg);
2498 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2504 * i915_gem_clear_fence_reg - clear out fence register info
2505 * @obj: object to clear
2507 * Zeroes out the fence register itself and clears out the associated
2508 * data structures in dev_priv and obj_priv.
2511 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2513 struct drm_device *dev = obj->dev;
2514 drm_i915_private_t *dev_priv = dev->dev_private;
2515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2518 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2522 if (obj_priv->fence_reg < 8)
2523 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2525 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2528 I915_WRITE(fence_reg, 0);
2531 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2532 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2533 list_del_init(&obj_priv->fence_list);
2537 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2538 * to the buffer to finish, and then resets the fence register.
2539 * @obj: tiled object holding a fence register.
2541 * Zeroes out the fence register itself and clears out the associated
2542 * data structures in dev_priv and obj_priv.
2545 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2547 struct drm_device *dev = obj->dev;
2548 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2550 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2553 /* On the i915, GPU access to tiled buffers is via a fence,
2554 * therefore we must wait for any outstanding access to complete
2555 * before clearing the fence.
2557 if (!IS_I965G(dev)) {
2560 i915_gem_object_flush_gpu_write_domain(obj);
2561 i915_gem_object_flush_gtt_write_domain(obj);
2562 ret = i915_gem_object_wait_rendering(obj);
2567 i915_gem_clear_fence_reg (obj);
2573 * Finds free space in the GTT aperture and binds the object there.
2576 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2578 struct drm_device *dev = obj->dev;
2579 drm_i915_private_t *dev_priv = dev->dev_private;
2580 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2581 struct drm_mm_node *free_space;
2582 bool retry_alloc = false;
2585 if (obj_priv->madv != I915_MADV_WILLNEED) {
2586 DRM_ERROR("Attempting to bind a purgeable object\n");
2591 alignment = i915_gem_get_gtt_alignment(obj);
2592 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2593 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2598 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2599 obj->size, alignment, 0);
2600 if (free_space != NULL) {
2601 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2603 if (obj_priv->gtt_space != NULL) {
2604 obj_priv->gtt_space->private = obj;
2605 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2608 if (obj_priv->gtt_space == NULL) {
2609 /* If the gtt is empty and we're still having trouble
2610 * fitting our object in, we're out of memory.
2613 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2615 ret = i915_gem_evict_something(dev, obj->size);
2623 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2624 obj->size, obj_priv->gtt_offset);
2627 i915_gem_object_set_page_gfp_mask (obj,
2628 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2630 ret = i915_gem_object_get_pages(obj);
2632 i915_gem_object_set_page_gfp_mask (obj,
2633 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2636 drm_mm_put_block(obj_priv->gtt_space);
2637 obj_priv->gtt_space = NULL;
2639 if (ret == -ENOMEM) {
2640 /* first try to clear up some space from the GTT */
2641 ret = i915_gem_evict_something(dev, obj->size);
2643 /* now try to shrink everyone else */
2644 if (! retry_alloc) {
2658 /* Create an AGP memory structure pointing at our pages, and bind it
2661 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2663 obj->size >> PAGE_SHIFT,
2664 obj_priv->gtt_offset,
2665 obj_priv->agp_type);
2666 if (obj_priv->agp_mem == NULL) {
2667 i915_gem_object_put_pages(obj);
2668 drm_mm_put_block(obj_priv->gtt_space);
2669 obj_priv->gtt_space = NULL;
2671 ret = i915_gem_evict_something(dev, obj->size);
2677 atomic_inc(&dev->gtt_count);
2678 atomic_add(obj->size, &dev->gtt_memory);
2680 /* Assert that the object is not currently in any GPU domain. As it
2681 * wasn't in the GTT, there shouldn't be any way it could have been in
2684 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2685 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2687 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2693 i915_gem_clflush_object(struct drm_gem_object *obj)
2695 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2697 /* If we don't have a page list set up, then we're not pinned
2698 * to GPU, and we can ignore the cache flush because it'll happen
2699 * again at bind time.
2701 if (obj_priv->pages == NULL)
2704 trace_i915_gem_object_clflush(obj);
2706 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2709 /** Flushes any GPU write domain for the object if it's dirty. */
2711 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2713 struct drm_device *dev = obj->dev;
2715 uint32_t old_write_domain;
2717 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2720 /* Queue the GPU write cache flushing we need. */
2721 old_write_domain = obj->write_domain;
2722 i915_gem_flush(dev, 0, obj->write_domain);
2723 seqno = i915_add_request(dev, NULL, obj->write_domain);
2724 obj->write_domain = 0;
2725 i915_gem_object_move_to_active(obj, seqno);
2727 trace_i915_gem_object_change_domain(obj,
2732 /** Flushes the GTT write domain for the object if it's dirty. */
2734 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2736 uint32_t old_write_domain;
2738 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2741 /* No actual flushing is required for the GTT write domain. Writes
2742 * to it immediately go to main memory as far as we know, so there's
2743 * no chipset flush. It also doesn't land in render cache.
2745 old_write_domain = obj->write_domain;
2746 obj->write_domain = 0;
2748 trace_i915_gem_object_change_domain(obj,
2753 /** Flushes the CPU write domain for the object if it's dirty. */
2755 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2757 struct drm_device *dev = obj->dev;
2758 uint32_t old_write_domain;
2760 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2763 i915_gem_clflush_object(obj);
2764 drm_agp_chipset_flush(dev);
2765 old_write_domain = obj->write_domain;
2766 obj->write_domain = 0;
2768 trace_i915_gem_object_change_domain(obj,
2774 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2776 switch (obj->write_domain) {
2777 case I915_GEM_DOMAIN_GTT:
2778 i915_gem_object_flush_gtt_write_domain(obj);
2780 case I915_GEM_DOMAIN_CPU:
2781 i915_gem_object_flush_cpu_write_domain(obj);
2784 i915_gem_object_flush_gpu_write_domain(obj);
2790 * Moves a single object to the GTT read, and possibly write domain.
2792 * This function returns when the move is complete, including waiting on
2796 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2798 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2799 uint32_t old_write_domain, old_read_domains;
2802 /* Not valid to be called on unbound objects. */
2803 if (obj_priv->gtt_space == NULL)
2806 i915_gem_object_flush_gpu_write_domain(obj);
2807 /* Wait on any GPU rendering and flushing to occur. */
2808 ret = i915_gem_object_wait_rendering(obj);
2812 old_write_domain = obj->write_domain;
2813 old_read_domains = obj->read_domains;
2815 /* If we're writing through the GTT domain, then CPU and GPU caches
2816 * will need to be invalidated at next use.
2819 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2821 i915_gem_object_flush_cpu_write_domain(obj);
2823 /* It should now be out of any other write domains, and we can update
2824 * the domain values for our changes.
2826 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2827 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2829 obj->write_domain = I915_GEM_DOMAIN_GTT;
2830 obj_priv->dirty = 1;
2833 trace_i915_gem_object_change_domain(obj,
2841 * Prepare buffer for display plane. Use uninterruptible for possible flush
2842 * wait, as in modesetting process we're not supposed to be interrupted.
2845 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2847 struct drm_device *dev = obj->dev;
2848 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2849 uint32_t old_write_domain, old_read_domains;
2852 /* Not valid to be called on unbound objects. */
2853 if (obj_priv->gtt_space == NULL)
2856 i915_gem_object_flush_gpu_write_domain(obj);
2858 /* Wait on any GPU rendering and flushing to occur. */
2859 if (obj_priv->active) {
2861 DRM_INFO("%s: object %p wait for seqno %08x\n",
2862 __func__, obj, obj_priv->last_rendering_seqno);
2864 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2869 old_write_domain = obj->write_domain;
2870 old_read_domains = obj->read_domains;
2872 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2874 i915_gem_object_flush_cpu_write_domain(obj);
2876 /* It should now be out of any other write domains, and we can update
2877 * the domain values for our changes.
2879 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2880 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2881 obj->write_domain = I915_GEM_DOMAIN_GTT;
2882 obj_priv->dirty = 1;
2884 trace_i915_gem_object_change_domain(obj,
2892 * Moves a single object to the CPU read, and possibly write domain.
2894 * This function returns when the move is complete, including waiting on
2898 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2900 uint32_t old_write_domain, old_read_domains;
2903 i915_gem_object_flush_gpu_write_domain(obj);
2904 /* Wait on any GPU rendering and flushing to occur. */
2905 ret = i915_gem_object_wait_rendering(obj);
2909 i915_gem_object_flush_gtt_write_domain(obj);
2911 /* If we have a partially-valid cache of the object in the CPU,
2912 * finish invalidating it and free the per-page flags.
2914 i915_gem_object_set_to_full_cpu_read_domain(obj);
2916 old_write_domain = obj->write_domain;
2917 old_read_domains = obj->read_domains;
2919 /* Flush the CPU cache if it's still invalid. */
2920 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2921 i915_gem_clflush_object(obj);
2923 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2926 /* It should now be out of any other write domains, and we can update
2927 * the domain values for our changes.
2929 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2931 /* If we're writing through the CPU, then the GPU read domains will
2932 * need to be invalidated at next use.
2935 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2936 obj->write_domain = I915_GEM_DOMAIN_CPU;
2939 trace_i915_gem_object_change_domain(obj,
2947 * Set the next domain for the specified object. This
2948 * may not actually perform the necessary flushing/invaliding though,
2949 * as that may want to be batched with other set_domain operations
2951 * This is (we hope) the only really tricky part of gem. The goal
2952 * is fairly simple -- track which caches hold bits of the object
2953 * and make sure they remain coherent. A few concrete examples may
2954 * help to explain how it works. For shorthand, we use the notation
2955 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2956 * a pair of read and write domain masks.
2958 * Case 1: the batch buffer
2964 * 5. Unmapped from GTT
2967 * Let's take these a step at a time
2970 * Pages allocated from the kernel may still have
2971 * cache contents, so we set them to (CPU, CPU) always.
2972 * 2. Written by CPU (using pwrite)
2973 * The pwrite function calls set_domain (CPU, CPU) and
2974 * this function does nothing (as nothing changes)
2976 * This function asserts that the object is not
2977 * currently in any GPU-based read or write domains
2979 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2980 * As write_domain is zero, this function adds in the
2981 * current read domains (CPU+COMMAND, 0).
2982 * flush_domains is set to CPU.
2983 * invalidate_domains is set to COMMAND
2984 * clflush is run to get data out of the CPU caches
2985 * then i915_dev_set_domain calls i915_gem_flush to
2986 * emit an MI_FLUSH and drm_agp_chipset_flush
2987 * 5. Unmapped from GTT
2988 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2989 * flush_domains and invalidate_domains end up both zero
2990 * so no flushing/invalidating happens
2994 * Case 2: The shared render buffer
2998 * 3. Read/written by GPU
2999 * 4. set_domain to (CPU,CPU)
3000 * 5. Read/written by CPU
3001 * 6. Read/written by GPU
3004 * Same as last example, (CPU, CPU)
3006 * Nothing changes (assertions find that it is not in the GPU)
3007 * 3. Read/written by GPU
3008 * execbuffer calls set_domain (RENDER, RENDER)
3009 * flush_domains gets CPU
3010 * invalidate_domains gets GPU
3012 * MI_FLUSH and drm_agp_chipset_flush
3013 * 4. set_domain (CPU, CPU)
3014 * flush_domains gets GPU
3015 * invalidate_domains gets CPU
3016 * wait_rendering (obj) to make sure all drawing is complete.
3017 * This will include an MI_FLUSH to get the data from GPU
3019 * clflush (obj) to invalidate the CPU cache
3020 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3021 * 5. Read/written by CPU
3022 * cache lines are loaded and dirtied
3023 * 6. Read written by GPU
3024 * Same as last GPU access
3026 * Case 3: The constant buffer
3031 * 4. Updated (written) by CPU again
3040 * flush_domains = CPU
3041 * invalidate_domains = RENDER
3044 * drm_agp_chipset_flush
3045 * 4. Updated (written) by CPU again
3047 * flush_domains = 0 (no previous write domain)
3048 * invalidate_domains = 0 (no new read domains)
3051 * flush_domains = CPU
3052 * invalidate_domains = RENDER
3055 * drm_agp_chipset_flush
3058 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3060 struct drm_device *dev = obj->dev;
3061 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3062 uint32_t invalidate_domains = 0;
3063 uint32_t flush_domains = 0;
3064 uint32_t old_read_domains;
3066 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3067 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3069 intel_mark_busy(dev, obj);
3072 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3074 obj->read_domains, obj->pending_read_domains,
3075 obj->write_domain, obj->pending_write_domain);
3078 * If the object isn't moving to a new write domain,
3079 * let the object stay in multiple read domains
3081 if (obj->pending_write_domain == 0)
3082 obj->pending_read_domains |= obj->read_domains;
3084 obj_priv->dirty = 1;
3087 * Flush the current write domain if
3088 * the new read domains don't match. Invalidate
3089 * any read domains which differ from the old
3092 if (obj->write_domain &&
3093 obj->write_domain != obj->pending_read_domains) {
3094 flush_domains |= obj->write_domain;
3095 invalidate_domains |=
3096 obj->pending_read_domains & ~obj->write_domain;
3099 * Invalidate any read caches which may have
3100 * stale data. That is, any new read domains.
3102 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3103 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3105 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3106 __func__, flush_domains, invalidate_domains);
3108 i915_gem_clflush_object(obj);
3111 old_read_domains = obj->read_domains;
3113 /* The actual obj->write_domain will be updated with
3114 * pending_write_domain after we emit the accumulated flush for all
3115 * of our domain changes in execbuffers (which clears objects'
3116 * write_domains). So if we have a current write domain that we
3117 * aren't changing, set pending_write_domain to that.
3119 if (flush_domains == 0 && obj->pending_write_domain == 0)
3120 obj->pending_write_domain = obj->write_domain;
3121 obj->read_domains = obj->pending_read_domains;
3123 dev->invalidate_domains |= invalidate_domains;
3124 dev->flush_domains |= flush_domains;
3126 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3128 obj->read_domains, obj->write_domain,
3129 dev->invalidate_domains, dev->flush_domains);
3132 trace_i915_gem_object_change_domain(obj,
3138 * Moves the object from a partially CPU read to a full one.
3140 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3141 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3144 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3146 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3148 if (!obj_priv->page_cpu_valid)
3151 /* If we're partially in the CPU read domain, finish moving it in.
3153 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3156 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3157 if (obj_priv->page_cpu_valid[i])
3159 drm_clflush_pages(obj_priv->pages + i, 1);
3163 /* Free the page_cpu_valid mappings which are now stale, whether
3164 * or not we've got I915_GEM_DOMAIN_CPU.
3166 kfree(obj_priv->page_cpu_valid);
3167 obj_priv->page_cpu_valid = NULL;
3171 * Set the CPU read domain on a range of the object.
3173 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3174 * not entirely valid. The page_cpu_valid member of the object flags which
3175 * pages have been flushed, and will be respected by
3176 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3177 * of the whole object.
3179 * This function returns when the move is complete, including waiting on
3183 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3184 uint64_t offset, uint64_t size)
3186 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3187 uint32_t old_read_domains;
3190 if (offset == 0 && size == obj->size)
3191 return i915_gem_object_set_to_cpu_domain(obj, 0);
3193 i915_gem_object_flush_gpu_write_domain(obj);
3194 /* Wait on any GPU rendering and flushing to occur. */
3195 ret = i915_gem_object_wait_rendering(obj);
3198 i915_gem_object_flush_gtt_write_domain(obj);
3200 /* If we're already fully in the CPU read domain, we're done. */
3201 if (obj_priv->page_cpu_valid == NULL &&
3202 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3205 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3206 * newly adding I915_GEM_DOMAIN_CPU
3208 if (obj_priv->page_cpu_valid == NULL) {
3209 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3211 if (obj_priv->page_cpu_valid == NULL)
3213 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3214 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3216 /* Flush the cache on any pages that are still invalid from the CPU's
3219 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3221 if (obj_priv->page_cpu_valid[i])
3224 drm_clflush_pages(obj_priv->pages + i, 1);
3226 obj_priv->page_cpu_valid[i] = 1;
3229 /* It should now be out of any other write domains, and we can update
3230 * the domain values for our changes.
3232 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3234 old_read_domains = obj->read_domains;
3235 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3237 trace_i915_gem_object_change_domain(obj,
3245 * Pin an object to the GTT and evaluate the relocations landing in it.
3248 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3249 struct drm_file *file_priv,
3250 struct drm_i915_gem_exec_object2 *entry,
3251 struct drm_i915_gem_relocation_entry *relocs)
3253 struct drm_device *dev = obj->dev;
3254 drm_i915_private_t *dev_priv = dev->dev_private;
3255 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3257 void __iomem *reloc_page;
3260 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3261 obj_priv->tiling_mode != I915_TILING_NONE;
3263 /* Check fence reg constraints and rebind if necessary */
3264 if (need_fence && !i915_obj_fenceable(dev, obj))
3265 i915_gem_object_unbind(obj);
3267 /* Choose the GTT offset for our buffer and put it there. */
3268 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3273 * Pre-965 chips need a fence register set up in order to
3274 * properly handle blits to/from tiled surfaces.
3277 ret = i915_gem_object_get_fence_reg(obj);
3279 if (ret != -EBUSY && ret != -ERESTARTSYS)
3280 DRM_ERROR("Failure to install fence: %d\n",
3282 i915_gem_object_unpin(obj);
3287 entry->offset = obj_priv->gtt_offset;
3289 /* Apply the relocations, using the GTT aperture to avoid cache
3290 * flushing requirements.
3292 for (i = 0; i < entry->relocation_count; i++) {
3293 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3294 struct drm_gem_object *target_obj;
3295 struct drm_i915_gem_object *target_obj_priv;
3296 uint32_t reloc_val, reloc_offset;
3297 uint32_t __iomem *reloc_entry;
3299 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3300 reloc->target_handle);
3301 if (target_obj == NULL) {
3302 i915_gem_object_unpin(obj);
3305 target_obj_priv = target_obj->driver_private;
3308 DRM_INFO("%s: obj %p offset %08x target %d "
3309 "read %08x write %08x gtt %08x "
3310 "presumed %08x delta %08x\n",
3313 (int) reloc->offset,
3314 (int) reloc->target_handle,
3315 (int) reloc->read_domains,
3316 (int) reloc->write_domain,
3317 (int) target_obj_priv->gtt_offset,
3318 (int) reloc->presumed_offset,
3322 /* The target buffer should have appeared before us in the
3323 * exec_object list, so it should have a GTT space bound by now.
3325 if (target_obj_priv->gtt_space == NULL) {
3326 DRM_ERROR("No GTT space found for object %d\n",
3327 reloc->target_handle);
3328 drm_gem_object_unreference(target_obj);
3329 i915_gem_object_unpin(obj);
3333 /* Validate that the target is in a valid r/w GPU domain */
3334 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3335 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3336 DRM_ERROR("reloc with read/write CPU domains: "
3337 "obj %p target %d offset %d "
3338 "read %08x write %08x",
3339 obj, reloc->target_handle,
3340 (int) reloc->offset,
3341 reloc->read_domains,
3342 reloc->write_domain);
3343 drm_gem_object_unreference(target_obj);
3344 i915_gem_object_unpin(obj);
3347 if (reloc->write_domain && target_obj->pending_write_domain &&
3348 reloc->write_domain != target_obj->pending_write_domain) {
3349 DRM_ERROR("Write domain conflict: "
3350 "obj %p target %d offset %d "
3351 "new %08x old %08x\n",
3352 obj, reloc->target_handle,
3353 (int) reloc->offset,
3354 reloc->write_domain,
3355 target_obj->pending_write_domain);
3356 drm_gem_object_unreference(target_obj);
3357 i915_gem_object_unpin(obj);
3361 target_obj->pending_read_domains |= reloc->read_domains;
3362 target_obj->pending_write_domain |= reloc->write_domain;
3364 /* If the relocation already has the right value in it, no
3365 * more work needs to be done.
3367 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3368 drm_gem_object_unreference(target_obj);
3372 /* Check that the relocation address is valid... */
3373 if (reloc->offset > obj->size - 4) {
3374 DRM_ERROR("Relocation beyond object bounds: "
3375 "obj %p target %d offset %d size %d.\n",
3376 obj, reloc->target_handle,
3377 (int) reloc->offset, (int) obj->size);
3378 drm_gem_object_unreference(target_obj);
3379 i915_gem_object_unpin(obj);
3382 if (reloc->offset & 3) {
3383 DRM_ERROR("Relocation not 4-byte aligned: "
3384 "obj %p target %d offset %d.\n",
3385 obj, reloc->target_handle,
3386 (int) reloc->offset);
3387 drm_gem_object_unreference(target_obj);
3388 i915_gem_object_unpin(obj);
3392 /* and points to somewhere within the target object. */
3393 if (reloc->delta >= target_obj->size) {
3394 DRM_ERROR("Relocation beyond target object bounds: "
3395 "obj %p target %d delta %d size %d.\n",
3396 obj, reloc->target_handle,
3397 (int) reloc->delta, (int) target_obj->size);
3398 drm_gem_object_unreference(target_obj);
3399 i915_gem_object_unpin(obj);
3403 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3405 drm_gem_object_unreference(target_obj);
3406 i915_gem_object_unpin(obj);
3410 /* Map the page containing the relocation we're going to
3413 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3414 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3417 reloc_entry = (uint32_t __iomem *)(reloc_page +
3418 (reloc_offset & (PAGE_SIZE - 1)));
3419 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3422 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3423 obj, (unsigned int) reloc->offset,
3424 readl(reloc_entry), reloc_val);
3426 writel(reloc_val, reloc_entry);
3427 io_mapping_unmap_atomic(reloc_page);
3429 /* The updated presumed offset for this entry will be
3430 * copied back out to the user.
3432 reloc->presumed_offset = target_obj_priv->gtt_offset;
3434 drm_gem_object_unreference(target_obj);
3439 i915_gem_dump_object(obj, 128, __func__, ~0);
3444 /** Dispatch a batchbuffer to the ring
3447 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3448 struct drm_i915_gem_execbuffer2 *exec,
3449 struct drm_clip_rect *cliprects,
3450 uint64_t exec_offset)
3452 drm_i915_private_t *dev_priv = dev->dev_private;
3453 int nbox = exec->num_cliprects;
3455 uint32_t exec_start, exec_len;
3458 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3459 exec_len = (uint32_t) exec->batch_len;
3461 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3463 count = nbox ? nbox : 1;
3465 for (i = 0; i < count; i++) {
3467 int ret = i915_emit_box(dev, cliprects, i,
3468 exec->DR1, exec->DR4);
3473 if (IS_I830(dev) || IS_845G(dev)) {
3475 OUT_RING(MI_BATCH_BUFFER);
3476 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3477 OUT_RING(exec_start + exec_len - 4);
3482 if (IS_I965G(dev)) {
3483 OUT_RING(MI_BATCH_BUFFER_START |
3485 MI_BATCH_NON_SECURE_I965);
3486 OUT_RING(exec_start);
3488 OUT_RING(MI_BATCH_BUFFER_START |
3490 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3496 /* XXX breadcrumb */
3500 /* Throttle our rendering by waiting until the ring has completed our requests
3501 * emitted over 20 msec ago.
3503 * Note that if we were to use the current jiffies each time around the loop,
3504 * we wouldn't escape the function with any frames outstanding if the time to
3505 * render a frame was over 20ms.
3507 * This should get us reasonable parallelism between CPU and GPU but also
3508 * relatively low latency when blocking on a particular request to finish.
3511 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3513 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3515 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3517 mutex_lock(&dev->struct_mutex);
3518 while (!list_empty(&i915_file_priv->mm.request_list)) {
3519 struct drm_i915_gem_request *request;
3521 request = list_first_entry(&i915_file_priv->mm.request_list,
3522 struct drm_i915_gem_request,
3525 if (time_after_eq(request->emitted_jiffies, recent_enough))
3528 ret = i915_wait_request(dev, request->seqno);
3532 mutex_unlock(&dev->struct_mutex);
3538 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3539 uint32_t buffer_count,
3540 struct drm_i915_gem_relocation_entry **relocs)
3542 uint32_t reloc_count = 0, reloc_index = 0, i;
3546 for (i = 0; i < buffer_count; i++) {
3547 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3549 reloc_count += exec_list[i].relocation_count;
3552 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3553 if (*relocs == NULL) {
3554 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3558 for (i = 0; i < buffer_count; i++) {
3559 struct drm_i915_gem_relocation_entry __user *user_relocs;
3561 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3563 ret = copy_from_user(&(*relocs)[reloc_index],
3565 exec_list[i].relocation_count *
3568 drm_free_large(*relocs);
3573 reloc_index += exec_list[i].relocation_count;
3580 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3581 uint32_t buffer_count,
3582 struct drm_i915_gem_relocation_entry *relocs)
3584 uint32_t reloc_count = 0, i;
3587 for (i = 0; i < buffer_count; i++) {
3588 struct drm_i915_gem_relocation_entry __user *user_relocs;
3591 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3593 unwritten = copy_to_user(user_relocs,
3594 &relocs[reloc_count],
3595 exec_list[i].relocation_count *
3603 reloc_count += exec_list[i].relocation_count;
3607 drm_free_large(relocs);
3613 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3614 uint64_t exec_offset)
3616 uint32_t exec_start, exec_len;
3618 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3619 exec_len = (uint32_t) exec->batch_len;
3621 if ((exec_start | exec_len) & 0x7)
3631 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3632 struct drm_gem_object **object_list,
3635 drm_i915_private_t *dev_priv = dev->dev_private;
3636 struct drm_i915_gem_object *obj_priv;
3641 prepare_to_wait(&dev_priv->pending_flip_queue,
3642 &wait, TASK_INTERRUPTIBLE);
3643 for (i = 0; i < count; i++) {
3644 obj_priv = object_list[i]->driver_private;
3645 if (atomic_read(&obj_priv->pending_flip) > 0)
3651 if (!signal_pending(current)) {
3652 mutex_unlock(&dev->struct_mutex);
3654 mutex_lock(&dev->struct_mutex);
3660 finish_wait(&dev_priv->pending_flip_queue, &wait);
3666 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3667 struct drm_file *file_priv,
3668 struct drm_i915_gem_execbuffer2 *args,
3669 struct drm_i915_gem_exec_object2 *exec_list)
3671 drm_i915_private_t *dev_priv = dev->dev_private;
3672 struct drm_gem_object **object_list = NULL;
3673 struct drm_gem_object *batch_obj;
3674 struct drm_i915_gem_object *obj_priv;
3675 struct drm_clip_rect *cliprects = NULL;
3676 struct drm_i915_gem_relocation_entry *relocs;
3677 int ret = 0, ret2, i, pinned = 0;
3678 uint64_t exec_offset;
3679 uint32_t seqno, flush_domains, reloc_index;
3680 int pin_tries, flips;
3683 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3684 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3687 if (args->buffer_count < 1) {
3688 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3691 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3692 if (object_list == NULL) {
3693 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3694 args->buffer_count);
3699 if (args->num_cliprects != 0) {
3700 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3702 if (cliprects == NULL)
3705 ret = copy_from_user(cliprects,
3706 (struct drm_clip_rect __user *)
3707 (uintptr_t) args->cliprects_ptr,
3708 sizeof(*cliprects) * args->num_cliprects);
3710 DRM_ERROR("copy %d cliprects failed: %d\n",
3711 args->num_cliprects, ret);
3716 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3721 mutex_lock(&dev->struct_mutex);
3723 i915_verify_inactive(dev, __FILE__, __LINE__);
3725 if (atomic_read(&dev_priv->mm.wedged)) {
3726 mutex_unlock(&dev->struct_mutex);
3731 if (dev_priv->mm.suspended) {
3732 mutex_unlock(&dev->struct_mutex);
3737 /* Look up object handles */
3739 for (i = 0; i < args->buffer_count; i++) {
3740 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3741 exec_list[i].handle);
3742 if (object_list[i] == NULL) {
3743 DRM_ERROR("Invalid object handle %d at index %d\n",
3744 exec_list[i].handle, i);
3749 obj_priv = object_list[i]->driver_private;
3750 if (obj_priv->in_execbuffer) {
3751 DRM_ERROR("Object %p appears more than once in object list\n",
3756 obj_priv->in_execbuffer = true;
3757 flips += atomic_read(&obj_priv->pending_flip);
3761 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3762 args->buffer_count);
3767 /* Pin and relocate */
3768 for (pin_tries = 0; ; pin_tries++) {
3772 for (i = 0; i < args->buffer_count; i++) {
3773 object_list[i]->pending_read_domains = 0;
3774 object_list[i]->pending_write_domain = 0;
3775 ret = i915_gem_object_pin_and_relocate(object_list[i],
3778 &relocs[reloc_index]);
3782 reloc_index += exec_list[i].relocation_count;
3788 /* error other than GTT full, or we've already tried again */
3789 if (ret != -ENOSPC || pin_tries >= 1) {
3790 if (ret != -ERESTARTSYS) {
3791 unsigned long long total_size = 0;
3792 for (i = 0; i < args->buffer_count; i++)
3793 total_size += object_list[i]->size;
3794 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3795 pinned+1, args->buffer_count,
3797 DRM_ERROR("%d objects [%d pinned], "
3798 "%d object bytes [%d pinned], "
3799 "%d/%d gtt bytes\n",
3800 atomic_read(&dev->object_count),
3801 atomic_read(&dev->pin_count),
3802 atomic_read(&dev->object_memory),
3803 atomic_read(&dev->pin_memory),
3804 atomic_read(&dev->gtt_memory),
3810 /* unpin all of our buffers */
3811 for (i = 0; i < pinned; i++)
3812 i915_gem_object_unpin(object_list[i]);
3815 /* evict everyone we can from the aperture */
3816 ret = i915_gem_evict_everything(dev);
3817 if (ret && ret != -ENOSPC)
3821 /* Set the pending read domains for the batch buffer to COMMAND */
3822 batch_obj = object_list[args->buffer_count-1];
3823 if (batch_obj->pending_write_domain) {
3824 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3828 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3830 /* Sanity check the batch buffer, prior to moving objects */
3831 exec_offset = exec_list[args->buffer_count - 1].offset;
3832 ret = i915_gem_check_execbuffer (args, exec_offset);
3834 DRM_ERROR("execbuf with invalid offset/length\n");
3838 i915_verify_inactive(dev, __FILE__, __LINE__);
3840 /* Zero the global flush/invalidate flags. These
3841 * will be modified as new domains are computed
3844 dev->invalidate_domains = 0;
3845 dev->flush_domains = 0;
3847 for (i = 0; i < args->buffer_count; i++) {
3848 struct drm_gem_object *obj = object_list[i];
3850 /* Compute new gpu domains and update invalidate/flush */
3851 i915_gem_object_set_to_gpu_domain(obj);
3854 i915_verify_inactive(dev, __FILE__, __LINE__);
3856 if (dev->invalidate_domains | dev->flush_domains) {
3858 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3860 dev->invalidate_domains,
3861 dev->flush_domains);
3864 dev->invalidate_domains,
3865 dev->flush_domains);
3866 if (dev->flush_domains)
3867 (void)i915_add_request(dev, file_priv,
3868 dev->flush_domains);
3871 for (i = 0; i < args->buffer_count; i++) {
3872 struct drm_gem_object *obj = object_list[i];
3873 uint32_t old_write_domain = obj->write_domain;
3875 obj->write_domain = obj->pending_write_domain;
3876 trace_i915_gem_object_change_domain(obj,
3881 i915_verify_inactive(dev, __FILE__, __LINE__);
3884 for (i = 0; i < args->buffer_count; i++) {
3885 i915_gem_object_check_coherency(object_list[i],
3886 exec_list[i].handle);
3891 i915_gem_dump_object(batch_obj,
3897 /* Exec the batchbuffer */
3898 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3900 DRM_ERROR("dispatch failed %d\n", ret);
3905 * Ensure that the commands in the batch buffer are
3906 * finished before the interrupt fires
3908 flush_domains = i915_retire_commands(dev);
3910 i915_verify_inactive(dev, __FILE__, __LINE__);
3913 * Get a seqno representing the execution of the current buffer,
3914 * which we can wait on. We would like to mitigate these interrupts,
3915 * likely by only creating seqnos occasionally (so that we have
3916 * *some* interrupts representing completion of buffers that we can
3917 * wait on when trying to clear up gtt space).
3919 seqno = i915_add_request(dev, file_priv, flush_domains);
3921 for (i = 0; i < args->buffer_count; i++) {
3922 struct drm_gem_object *obj = object_list[i];
3924 i915_gem_object_move_to_active(obj, seqno);
3926 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3930 i915_dump_lru(dev, __func__);
3933 i915_verify_inactive(dev, __FILE__, __LINE__);
3936 for (i = 0; i < pinned; i++)
3937 i915_gem_object_unpin(object_list[i]);
3939 for (i = 0; i < args->buffer_count; i++) {
3940 if (object_list[i]) {
3941 obj_priv = object_list[i]->driver_private;
3942 obj_priv->in_execbuffer = false;
3944 drm_gem_object_unreference(object_list[i]);
3947 mutex_unlock(&dev->struct_mutex);
3949 /* Copy the updated relocations out regardless of current error
3950 * state. Failure to update the relocs would mean that the next
3951 * time userland calls execbuf, it would do so with presumed offset
3952 * state that didn't match the actual object state.
3954 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3957 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3964 drm_free_large(object_list);
3971 * Legacy execbuffer just creates an exec2 list from the original exec object
3972 * list array and passes it to the real function.
3975 i915_gem_execbuffer(struct drm_device *dev, void *data,
3976 struct drm_file *file_priv)
3978 struct drm_i915_gem_execbuffer *args = data;
3979 struct drm_i915_gem_execbuffer2 exec2;
3980 struct drm_i915_gem_exec_object *exec_list = NULL;
3981 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3985 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3986 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3989 if (args->buffer_count < 1) {
3990 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3994 /* Copy in the exec list from userland */
3995 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3996 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3997 if (exec_list == NULL || exec2_list == NULL) {
3998 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3999 args->buffer_count);
4000 drm_free_large(exec_list);
4001 drm_free_large(exec2_list);
4004 ret = copy_from_user(exec_list,
4005 (struct drm_i915_relocation_entry __user *)
4006 (uintptr_t) args->buffers_ptr,
4007 sizeof(*exec_list) * args->buffer_count);
4009 DRM_ERROR("copy %d exec entries failed %d\n",
4010 args->buffer_count, ret);
4011 drm_free_large(exec_list);
4012 drm_free_large(exec2_list);
4016 for (i = 0; i < args->buffer_count; i++) {
4017 exec2_list[i].handle = exec_list[i].handle;
4018 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4019 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4020 exec2_list[i].alignment = exec_list[i].alignment;
4021 exec2_list[i].offset = exec_list[i].offset;
4023 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4025 exec2_list[i].flags = 0;
4028 exec2.buffers_ptr = args->buffers_ptr;
4029 exec2.buffer_count = args->buffer_count;
4030 exec2.batch_start_offset = args->batch_start_offset;
4031 exec2.batch_len = args->batch_len;
4032 exec2.DR1 = args->DR1;
4033 exec2.DR4 = args->DR4;
4034 exec2.num_cliprects = args->num_cliprects;
4035 exec2.cliprects_ptr = args->cliprects_ptr;
4038 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4040 /* Copy the new buffer offsets back to the user's exec list. */
4041 for (i = 0; i < args->buffer_count; i++)
4042 exec_list[i].offset = exec2_list[i].offset;
4043 /* ... and back out to userspace */
4044 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4045 (uintptr_t) args->buffers_ptr,
4047 sizeof(*exec_list) * args->buffer_count);
4050 DRM_ERROR("failed to copy %d exec entries "
4051 "back to user (%d)\n",
4052 args->buffer_count, ret);
4056 drm_free_large(exec_list);
4057 drm_free_large(exec2_list);
4062 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4063 struct drm_file *file_priv)
4065 struct drm_i915_gem_execbuffer2 *args = data;
4066 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4070 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4071 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4074 if (args->buffer_count < 1) {
4075 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4079 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4080 if (exec2_list == NULL) {
4081 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4082 args->buffer_count);
4085 ret = copy_from_user(exec2_list,
4086 (struct drm_i915_relocation_entry __user *)
4087 (uintptr_t) args->buffers_ptr,
4088 sizeof(*exec2_list) * args->buffer_count);
4090 DRM_ERROR("copy %d exec entries failed %d\n",
4091 args->buffer_count, ret);
4092 drm_free_large(exec2_list);
4096 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4098 /* Copy the new buffer offsets back to the user's exec list. */
4099 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4100 (uintptr_t) args->buffers_ptr,
4102 sizeof(*exec2_list) * args->buffer_count);
4105 DRM_ERROR("failed to copy %d exec entries "
4106 "back to user (%d)\n",
4107 args->buffer_count, ret);
4111 drm_free_large(exec2_list);
4116 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4118 struct drm_device *dev = obj->dev;
4119 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4122 i915_verify_inactive(dev, __FILE__, __LINE__);
4123 if (obj_priv->gtt_space == NULL) {
4124 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4129 obj_priv->pin_count++;
4131 /* If the object is not active and not pending a flush,
4132 * remove it from the inactive list
4134 if (obj_priv->pin_count == 1) {
4135 atomic_inc(&dev->pin_count);
4136 atomic_add(obj->size, &dev->pin_memory);
4137 if (!obj_priv->active &&
4138 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4139 !list_empty(&obj_priv->list))
4140 list_del_init(&obj_priv->list);
4142 i915_verify_inactive(dev, __FILE__, __LINE__);
4148 i915_gem_object_unpin(struct drm_gem_object *obj)
4150 struct drm_device *dev = obj->dev;
4151 drm_i915_private_t *dev_priv = dev->dev_private;
4152 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4154 i915_verify_inactive(dev, __FILE__, __LINE__);
4155 obj_priv->pin_count--;
4156 BUG_ON(obj_priv->pin_count < 0);
4157 BUG_ON(obj_priv->gtt_space == NULL);
4159 /* If the object is no longer pinned, and is
4160 * neither active nor being flushed, then stick it on
4163 if (obj_priv->pin_count == 0) {
4164 if (!obj_priv->active &&
4165 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4166 list_move_tail(&obj_priv->list,
4167 &dev_priv->mm.inactive_list);
4168 atomic_dec(&dev->pin_count);
4169 atomic_sub(obj->size, &dev->pin_memory);
4171 i915_verify_inactive(dev, __FILE__, __LINE__);
4175 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4176 struct drm_file *file_priv)
4178 struct drm_i915_gem_pin *args = data;
4179 struct drm_gem_object *obj;
4180 struct drm_i915_gem_object *obj_priv;
4183 mutex_lock(&dev->struct_mutex);
4185 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4187 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4189 mutex_unlock(&dev->struct_mutex);
4192 obj_priv = obj->driver_private;
4194 if (obj_priv->madv != I915_MADV_WILLNEED) {
4195 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4196 drm_gem_object_unreference(obj);
4197 mutex_unlock(&dev->struct_mutex);
4201 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4202 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4204 drm_gem_object_unreference(obj);
4205 mutex_unlock(&dev->struct_mutex);
4209 obj_priv->user_pin_count++;
4210 obj_priv->pin_filp = file_priv;
4211 if (obj_priv->user_pin_count == 1) {
4212 ret = i915_gem_object_pin(obj, args->alignment);
4214 drm_gem_object_unreference(obj);
4215 mutex_unlock(&dev->struct_mutex);
4220 /* XXX - flush the CPU caches for pinned objects
4221 * as the X server doesn't manage domains yet
4223 i915_gem_object_flush_cpu_write_domain(obj);
4224 args->offset = obj_priv->gtt_offset;
4225 drm_gem_object_unreference(obj);
4226 mutex_unlock(&dev->struct_mutex);
4232 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4233 struct drm_file *file_priv)
4235 struct drm_i915_gem_pin *args = data;
4236 struct drm_gem_object *obj;
4237 struct drm_i915_gem_object *obj_priv;
4239 mutex_lock(&dev->struct_mutex);
4241 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4243 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4245 mutex_unlock(&dev->struct_mutex);
4249 obj_priv = obj->driver_private;
4250 if (obj_priv->pin_filp != file_priv) {
4251 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4253 drm_gem_object_unreference(obj);
4254 mutex_unlock(&dev->struct_mutex);
4257 obj_priv->user_pin_count--;
4258 if (obj_priv->user_pin_count == 0) {
4259 obj_priv->pin_filp = NULL;
4260 i915_gem_object_unpin(obj);
4263 drm_gem_object_unreference(obj);
4264 mutex_unlock(&dev->struct_mutex);
4269 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4270 struct drm_file *file_priv)
4272 struct drm_i915_gem_busy *args = data;
4273 struct drm_gem_object *obj;
4274 struct drm_i915_gem_object *obj_priv;
4276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4278 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4283 mutex_lock(&dev->struct_mutex);
4284 /* Update the active list for the hardware's current position.
4285 * Otherwise this only updates on a delayed timer or when irqs are
4286 * actually unmasked, and our working set ends up being larger than
4289 i915_gem_retire_requests(dev);
4291 obj_priv = obj->driver_private;
4292 /* Don't count being on the flushing list against the object being
4293 * done. Otherwise, a buffer left on the flushing list but not getting
4294 * flushed (because nobody's flushing that domain) won't ever return
4295 * unbusy and get reused by libdrm's bo cache. The other expected
4296 * consumer of this interface, OpenGL's occlusion queries, also specs
4297 * that the objects get unbusy "eventually" without any interference.
4299 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4301 drm_gem_object_unreference(obj);
4302 mutex_unlock(&dev->struct_mutex);
4307 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4308 struct drm_file *file_priv)
4310 return i915_gem_ring_throttle(dev, file_priv);
4314 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4315 struct drm_file *file_priv)
4317 struct drm_i915_gem_madvise *args = data;
4318 struct drm_gem_object *obj;
4319 struct drm_i915_gem_object *obj_priv;
4321 switch (args->madv) {
4322 case I915_MADV_DONTNEED:
4323 case I915_MADV_WILLNEED:
4329 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4331 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4336 mutex_lock(&dev->struct_mutex);
4337 obj_priv = obj->driver_private;
4339 if (obj_priv->pin_count) {
4340 drm_gem_object_unreference(obj);
4341 mutex_unlock(&dev->struct_mutex);
4343 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4347 if (obj_priv->madv != __I915_MADV_PURGED)
4348 obj_priv->madv = args->madv;
4350 /* if the object is no longer bound, discard its backing storage */
4351 if (i915_gem_object_is_purgeable(obj_priv) &&
4352 obj_priv->gtt_space == NULL)
4353 i915_gem_object_truncate(obj);
4355 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4357 drm_gem_object_unreference(obj);
4358 mutex_unlock(&dev->struct_mutex);
4363 int i915_gem_init_object(struct drm_gem_object *obj)
4365 struct drm_i915_gem_object *obj_priv;
4367 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4368 if (obj_priv == NULL)
4372 * We've just allocated pages from the kernel,
4373 * so they've just been written by the CPU with
4374 * zeros. They'll need to be clflushed before we
4375 * use them with the GPU.
4377 obj->write_domain = I915_GEM_DOMAIN_CPU;
4378 obj->read_domains = I915_GEM_DOMAIN_CPU;
4380 obj_priv->agp_type = AGP_USER_MEMORY;
4382 obj->driver_private = obj_priv;
4383 obj_priv->obj = obj;
4384 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4385 INIT_LIST_HEAD(&obj_priv->list);
4386 INIT_LIST_HEAD(&obj_priv->fence_list);
4387 obj_priv->madv = I915_MADV_WILLNEED;
4389 trace_i915_gem_object_create(obj);
4394 void i915_gem_free_object(struct drm_gem_object *obj)
4396 struct drm_device *dev = obj->dev;
4397 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4399 trace_i915_gem_object_destroy(obj);
4401 while (obj_priv->pin_count > 0)
4402 i915_gem_object_unpin(obj);
4404 if (obj_priv->phys_obj)
4405 i915_gem_detach_phys_object(dev, obj);
4407 i915_gem_object_unbind(obj);
4409 if (obj_priv->mmap_offset)
4410 i915_gem_free_mmap_offset(obj);
4412 kfree(obj_priv->page_cpu_valid);
4413 kfree(obj_priv->bit_17);
4414 kfree(obj->driver_private);
4417 /** Unbinds all inactive objects. */
4419 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4421 drm_i915_private_t *dev_priv = dev->dev_private;
4423 while (!list_empty(&dev_priv->mm.inactive_list)) {
4424 struct drm_gem_object *obj;
4427 obj = list_first_entry(&dev_priv->mm.inactive_list,
4428 struct drm_i915_gem_object,
4431 ret = i915_gem_object_unbind(obj);
4433 DRM_ERROR("Error unbinding object: %d\n", ret);
4442 i915_gem_idle(struct drm_device *dev)
4444 drm_i915_private_t *dev_priv = dev->dev_private;
4445 uint32_t seqno, cur_seqno, last_seqno;
4448 mutex_lock(&dev->struct_mutex);
4450 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4451 mutex_unlock(&dev->struct_mutex);
4455 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4456 * We need to replace this with a semaphore, or something.
4458 dev_priv->mm.suspended = 1;
4459 del_timer(&dev_priv->hangcheck_timer);
4461 /* Cancel the retire work handler, wait for it to finish if running
4463 mutex_unlock(&dev->struct_mutex);
4464 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4465 mutex_lock(&dev->struct_mutex);
4467 i915_kernel_lost_context(dev);
4469 /* Flush the GPU along with all non-CPU write domains
4471 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4472 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4475 mutex_unlock(&dev->struct_mutex);
4479 dev_priv->mm.waiting_gem_seqno = seqno;
4483 cur_seqno = i915_get_gem_seqno(dev);
4484 if (i915_seqno_passed(cur_seqno, seqno))
4486 if (last_seqno == cur_seqno) {
4487 if (stuck++ > 100) {
4488 DRM_ERROR("hardware wedged\n");
4489 atomic_set(&dev_priv->mm.wedged, 1);
4490 DRM_WAKEUP(&dev_priv->irq_queue);
4495 last_seqno = cur_seqno;
4497 dev_priv->mm.waiting_gem_seqno = 0;
4499 i915_gem_retire_requests(dev);
4501 spin_lock(&dev_priv->mm.active_list_lock);
4502 if (!atomic_read(&dev_priv->mm.wedged)) {
4503 /* Active and flushing should now be empty as we've
4504 * waited for a sequence higher than any pending execbuffer
4506 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4507 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4508 /* Request should now be empty as we've also waited
4509 * for the last request in the list
4511 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4514 /* Empty the active and flushing lists to inactive. If there's
4515 * anything left at this point, it means that we're wedged and
4516 * nothing good's going to happen by leaving them there. So strip
4517 * the GPU domains and just stuff them onto inactive.
4519 while (!list_empty(&dev_priv->mm.active_list)) {
4520 struct drm_gem_object *obj;
4521 uint32_t old_write_domain;
4523 obj = list_first_entry(&dev_priv->mm.active_list,
4524 struct drm_i915_gem_object,
4526 old_write_domain = obj->write_domain;
4527 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4528 i915_gem_object_move_to_inactive(obj);
4530 trace_i915_gem_object_change_domain(obj,
4534 spin_unlock(&dev_priv->mm.active_list_lock);
4536 while (!list_empty(&dev_priv->mm.flushing_list)) {
4537 struct drm_gem_object *obj;
4538 uint32_t old_write_domain;
4540 obj = list_first_entry(&dev_priv->mm.flushing_list,
4541 struct drm_i915_gem_object,
4543 old_write_domain = obj->write_domain;
4544 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4545 i915_gem_object_move_to_inactive(obj);
4547 trace_i915_gem_object_change_domain(obj,
4553 /* Move all inactive buffers out of the GTT. */
4554 ret = i915_gem_evict_from_inactive_list(dev);
4555 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4557 mutex_unlock(&dev->struct_mutex);
4561 i915_gem_cleanup_ringbuffer(dev);
4562 mutex_unlock(&dev->struct_mutex);
4568 i915_gem_init_hws(struct drm_device *dev)
4570 drm_i915_private_t *dev_priv = dev->dev_private;
4571 struct drm_gem_object *obj;
4572 struct drm_i915_gem_object *obj_priv;
4575 /* If we need a physical address for the status page, it's already
4576 * initialized at driver load time.
4578 if (!I915_NEED_GFX_HWS(dev))
4581 obj = drm_gem_object_alloc(dev, 4096);
4583 DRM_ERROR("Failed to allocate status page\n");
4586 obj_priv = obj->driver_private;
4587 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4589 ret = i915_gem_object_pin(obj, 4096);
4591 drm_gem_object_unreference(obj);
4595 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4597 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4598 if (dev_priv->hw_status_page == NULL) {
4599 DRM_ERROR("Failed to map status page.\n");
4600 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4601 i915_gem_object_unpin(obj);
4602 drm_gem_object_unreference(obj);
4605 dev_priv->hws_obj = obj;
4606 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4607 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4608 I915_READ(HWS_PGA); /* posting read */
4609 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4615 i915_gem_cleanup_hws(struct drm_device *dev)
4617 drm_i915_private_t *dev_priv = dev->dev_private;
4618 struct drm_gem_object *obj;
4619 struct drm_i915_gem_object *obj_priv;
4621 if (dev_priv->hws_obj == NULL)
4624 obj = dev_priv->hws_obj;
4625 obj_priv = obj->driver_private;
4627 kunmap(obj_priv->pages[0]);
4628 i915_gem_object_unpin(obj);
4629 drm_gem_object_unreference(obj);
4630 dev_priv->hws_obj = NULL;
4632 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4633 dev_priv->hw_status_page = NULL;
4635 /* Write high address into HWS_PGA when disabling. */
4636 I915_WRITE(HWS_PGA, 0x1ffff000);
4640 i915_gem_init_ringbuffer(struct drm_device *dev)
4642 drm_i915_private_t *dev_priv = dev->dev_private;
4643 struct drm_gem_object *obj;
4644 struct drm_i915_gem_object *obj_priv;
4645 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4649 ret = i915_gem_init_hws(dev);
4653 obj = drm_gem_object_alloc(dev, 128 * 1024);
4655 DRM_ERROR("Failed to allocate ringbuffer\n");
4656 i915_gem_cleanup_hws(dev);
4659 obj_priv = obj->driver_private;
4661 ret = i915_gem_object_pin(obj, 4096);
4663 drm_gem_object_unreference(obj);
4664 i915_gem_cleanup_hws(dev);
4668 /* Set up the kernel mapping for the ring. */
4669 ring->Size = obj->size;
4671 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4672 ring->map.size = obj->size;
4674 ring->map.flags = 0;
4677 drm_core_ioremap_wc(&ring->map, dev);
4678 if (ring->map.handle == NULL) {
4679 DRM_ERROR("Failed to map ringbuffer.\n");
4680 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4681 i915_gem_object_unpin(obj);
4682 drm_gem_object_unreference(obj);
4683 i915_gem_cleanup_hws(dev);
4686 ring->ring_obj = obj;
4687 ring->virtual_start = ring->map.handle;
4689 /* Stop the ring if it's running. */
4690 I915_WRITE(PRB0_CTL, 0);
4691 I915_WRITE(PRB0_TAIL, 0);
4692 I915_WRITE(PRB0_HEAD, 0);
4694 /* Initialize the ring. */
4695 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4696 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4698 /* G45 ring initialization fails to reset head to zero */
4700 DRM_ERROR("Ring head not reset to zero "
4701 "ctl %08x head %08x tail %08x start %08x\n",
4702 I915_READ(PRB0_CTL),
4703 I915_READ(PRB0_HEAD),
4704 I915_READ(PRB0_TAIL),
4705 I915_READ(PRB0_START));
4706 I915_WRITE(PRB0_HEAD, 0);
4708 DRM_ERROR("Ring head forced to zero "
4709 "ctl %08x head %08x tail %08x start %08x\n",
4710 I915_READ(PRB0_CTL),
4711 I915_READ(PRB0_HEAD),
4712 I915_READ(PRB0_TAIL),
4713 I915_READ(PRB0_START));
4716 I915_WRITE(PRB0_CTL,
4717 ((obj->size - 4096) & RING_NR_PAGES) |
4721 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4723 /* If the head is still not zero, the ring is dead */
4725 DRM_ERROR("Ring initialization failed "
4726 "ctl %08x head %08x tail %08x start %08x\n",
4727 I915_READ(PRB0_CTL),
4728 I915_READ(PRB0_HEAD),
4729 I915_READ(PRB0_TAIL),
4730 I915_READ(PRB0_START));
4734 /* Update our cache of the ring state */
4735 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4736 i915_kernel_lost_context(dev);
4738 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4739 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4740 ring->space = ring->head - (ring->tail + 8);
4741 if (ring->space < 0)
4742 ring->space += ring->Size;
4749 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4751 drm_i915_private_t *dev_priv = dev->dev_private;
4753 if (dev_priv->ring.ring_obj == NULL)
4756 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4758 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4759 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4760 dev_priv->ring.ring_obj = NULL;
4761 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4763 i915_gem_cleanup_hws(dev);
4767 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4768 struct drm_file *file_priv)
4770 drm_i915_private_t *dev_priv = dev->dev_private;
4773 if (drm_core_check_feature(dev, DRIVER_MODESET))
4776 if (atomic_read(&dev_priv->mm.wedged)) {
4777 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4778 atomic_set(&dev_priv->mm.wedged, 0);
4781 mutex_lock(&dev->struct_mutex);
4782 dev_priv->mm.suspended = 0;
4784 ret = i915_gem_init_ringbuffer(dev);
4786 mutex_unlock(&dev->struct_mutex);
4790 spin_lock(&dev_priv->mm.active_list_lock);
4791 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4792 spin_unlock(&dev_priv->mm.active_list_lock);
4794 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4795 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4796 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4797 mutex_unlock(&dev->struct_mutex);
4799 drm_irq_install(dev);
4805 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4806 struct drm_file *file_priv)
4808 if (drm_core_check_feature(dev, DRIVER_MODESET))
4811 drm_irq_uninstall(dev);
4812 return i915_gem_idle(dev);
4816 i915_gem_lastclose(struct drm_device *dev)
4820 if (drm_core_check_feature(dev, DRIVER_MODESET))
4823 ret = i915_gem_idle(dev);
4825 DRM_ERROR("failed to idle hardware: %d\n", ret);
4829 i915_gem_load(struct drm_device *dev)
4832 drm_i915_private_t *dev_priv = dev->dev_private;
4834 spin_lock_init(&dev_priv->mm.active_list_lock);
4835 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4836 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4837 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4838 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4839 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4840 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4841 i915_gem_retire_work_handler);
4842 dev_priv->mm.next_gem_seqno = 1;
4844 spin_lock(&shrink_list_lock);
4845 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4846 spin_unlock(&shrink_list_lock);
4848 /* Old X drivers will take 0-2 for front, back, depth buffers */
4849 dev_priv->fence_reg_start = 3;
4851 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4852 dev_priv->num_fence_regs = 16;
4854 dev_priv->num_fence_regs = 8;
4856 /* Initialize fence registers to zero */
4857 if (IS_I965G(dev)) {
4858 for (i = 0; i < 16; i++)
4859 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4861 for (i = 0; i < 8; i++)
4862 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4863 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4864 for (i = 0; i < 8; i++)
4865 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4867 i915_gem_detect_bit_6_swizzle(dev);
4868 init_waitqueue_head(&dev_priv->pending_flip_queue);
4872 * Create a physically contiguous memory object for this object
4873 * e.g. for cursor + overlay regs
4875 int i915_gem_init_phys_object(struct drm_device *dev,
4878 drm_i915_private_t *dev_priv = dev->dev_private;
4879 struct drm_i915_gem_phys_object *phys_obj;
4882 if (dev_priv->mm.phys_objs[id - 1] || !size)
4885 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4891 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4892 if (!phys_obj->handle) {
4897 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4900 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4908 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4910 drm_i915_private_t *dev_priv = dev->dev_private;
4911 struct drm_i915_gem_phys_object *phys_obj;
4913 if (!dev_priv->mm.phys_objs[id - 1])
4916 phys_obj = dev_priv->mm.phys_objs[id - 1];
4917 if (phys_obj->cur_obj) {
4918 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4922 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4924 drm_pci_free(dev, phys_obj->handle);
4926 dev_priv->mm.phys_objs[id - 1] = NULL;
4929 void i915_gem_free_all_phys_object(struct drm_device *dev)
4933 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4934 i915_gem_free_phys_object(dev, i);
4937 void i915_gem_detach_phys_object(struct drm_device *dev,
4938 struct drm_gem_object *obj)
4940 struct drm_i915_gem_object *obj_priv;
4945 obj_priv = obj->driver_private;
4946 if (!obj_priv->phys_obj)
4949 ret = i915_gem_object_get_pages(obj);
4953 page_count = obj->size / PAGE_SIZE;
4955 for (i = 0; i < page_count; i++) {
4956 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4957 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4959 memcpy(dst, src, PAGE_SIZE);
4960 kunmap_atomic(dst, KM_USER0);
4962 drm_clflush_pages(obj_priv->pages, page_count);
4963 drm_agp_chipset_flush(dev);
4965 i915_gem_object_put_pages(obj);
4967 obj_priv->phys_obj->cur_obj = NULL;
4968 obj_priv->phys_obj = NULL;
4972 i915_gem_attach_phys_object(struct drm_device *dev,
4973 struct drm_gem_object *obj, int id)
4975 drm_i915_private_t *dev_priv = dev->dev_private;
4976 struct drm_i915_gem_object *obj_priv;
4981 if (id > I915_MAX_PHYS_OBJECT)
4984 obj_priv = obj->driver_private;
4986 if (obj_priv->phys_obj) {
4987 if (obj_priv->phys_obj->id == id)
4989 i915_gem_detach_phys_object(dev, obj);
4993 /* create a new object */
4994 if (!dev_priv->mm.phys_objs[id - 1]) {
4995 ret = i915_gem_init_phys_object(dev, id,
4998 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
5003 /* bind to the object */
5004 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5005 obj_priv->phys_obj->cur_obj = obj;
5007 ret = i915_gem_object_get_pages(obj);
5009 DRM_ERROR("failed to get page list\n");
5013 page_count = obj->size / PAGE_SIZE;
5015 for (i = 0; i < page_count; i++) {
5016 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5017 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5019 memcpy(dst, src, PAGE_SIZE);
5020 kunmap_atomic(src, KM_USER0);
5023 i915_gem_object_put_pages(obj);
5031 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5032 struct drm_i915_gem_pwrite *args,
5033 struct drm_file *file_priv)
5035 struct drm_i915_gem_object *obj_priv = obj->driver_private;
5038 char __user *user_data;
5040 user_data = (char __user *) (uintptr_t) args->data_ptr;
5041 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5043 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5044 ret = copy_from_user(obj_addr, user_data, args->size);
5048 drm_agp_chipset_flush(dev);
5052 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5054 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5056 /* Clean up our request list when the client is going away, so that
5057 * later retire_requests won't dereference our soon-to-be-gone
5060 mutex_lock(&dev->struct_mutex);
5061 while (!list_empty(&i915_file_priv->mm.request_list))
5062 list_del_init(i915_file_priv->mm.request_list.next);
5063 mutex_unlock(&dev->struct_mutex);
5067 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5069 drm_i915_private_t *dev_priv, *next_dev;
5070 struct drm_i915_gem_object *obj_priv, *next_obj;
5072 int would_deadlock = 1;
5074 /* "fast-path" to count number of available objects */
5075 if (nr_to_scan == 0) {
5076 spin_lock(&shrink_list_lock);
5077 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5078 struct drm_device *dev = dev_priv->dev;
5080 if (mutex_trylock(&dev->struct_mutex)) {
5081 list_for_each_entry(obj_priv,
5082 &dev_priv->mm.inactive_list,
5085 mutex_unlock(&dev->struct_mutex);
5088 spin_unlock(&shrink_list_lock);
5090 return (cnt / 100) * sysctl_vfs_cache_pressure;
5093 spin_lock(&shrink_list_lock);
5095 /* first scan for clean buffers */
5096 list_for_each_entry_safe(dev_priv, next_dev,
5097 &shrink_list, mm.shrink_list) {
5098 struct drm_device *dev = dev_priv->dev;
5100 if (! mutex_trylock(&dev->struct_mutex))
5103 spin_unlock(&shrink_list_lock);
5105 i915_gem_retire_requests(dev);
5107 list_for_each_entry_safe(obj_priv, next_obj,
5108 &dev_priv->mm.inactive_list,
5110 if (i915_gem_object_is_purgeable(obj_priv)) {
5111 i915_gem_object_unbind(obj_priv->obj);
5112 if (--nr_to_scan <= 0)
5117 spin_lock(&shrink_list_lock);
5118 mutex_unlock(&dev->struct_mutex);
5122 if (nr_to_scan <= 0)
5126 /* second pass, evict/count anything still on the inactive list */
5127 list_for_each_entry_safe(dev_priv, next_dev,
5128 &shrink_list, mm.shrink_list) {
5129 struct drm_device *dev = dev_priv->dev;
5131 if (! mutex_trylock(&dev->struct_mutex))
5134 spin_unlock(&shrink_list_lock);
5136 list_for_each_entry_safe(obj_priv, next_obj,
5137 &dev_priv->mm.inactive_list,
5139 if (nr_to_scan > 0) {
5140 i915_gem_object_unbind(obj_priv->obj);
5146 spin_lock(&shrink_list_lock);
5147 mutex_unlock(&dev->struct_mutex);
5152 spin_unlock(&shrink_list_lock);
5157 return (cnt / 100) * sysctl_vfs_cache_pressure;
5162 static struct shrinker shrinker = {
5163 .shrink = i915_gem_shrink,
5164 .seeks = DEFAULT_SEEKS,
5168 i915_gem_shrinker_init(void)
5170 register_shrinker(&shrinker);
5174 i915_gem_shrinker_exit(void)
5176 unregister_shrinker(&shrinker);