2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1206 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1208 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1213 /* Need a new fence register? */
1214 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1215 ret = i915_gem_object_get_fence_reg(obj);
1220 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1223 /* Finally, remap it using the new GTT offset */
1224 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1226 mutex_unlock(&dev->struct_mutex);
1231 return VM_FAULT_NOPAGE;
1234 return VM_FAULT_OOM;
1236 return VM_FAULT_SIGBUS;
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1249 * This routine allocates and attaches a fake offset for @obj.
1252 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1254 struct drm_device *dev = obj->dev;
1255 struct drm_gem_mm *mm = dev->mm_private;
1256 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1257 struct drm_map_list *list;
1258 struct drm_local_map *map;
1261 /* Set the object up for mmap'ing */
1262 list = &obj->map_list;
1263 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1268 map->type = _DRM_GEM;
1269 map->size = obj->size;
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1274 obj->size / PAGE_SIZE, 0, 0);
1275 if (!list->file_offset_node) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1281 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1282 obj->size / PAGE_SIZE, 0);
1283 if (!list->file_offset_node) {
1288 list->hash.key = list->file_offset_node->start;
1289 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1290 DRM_ERROR("failed to add to map hash\n");
1294 /* By now we should be all set, any drm_mmap request on the offset
1295 * below will get to our mmap & fault handler */
1296 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1301 drm_mm_put_block(list->file_offset_node);
1309 * i915_gem_release_mmap - remove physical page mappings
1310 * @obj: obj in question
1312 * Preserve the reservation of the mmaping with the DRM core code, but
1313 * relinquish ownership of the pages back to the system.
1315 * It is vital that we remove the page mapping if we have mapped a tiled
1316 * object through the GTT and then lose the fence register due to
1317 * resource pressure. Similarly if the object has been moved out of the
1318 * aperture, than pages mapped into userspace must be revoked. Removing the
1319 * mapping will then trigger a page fault on the next user access, allowing
1320 * fixup by i915_gem_fault().
1323 i915_gem_release_mmap(struct drm_gem_object *obj)
1325 struct drm_device *dev = obj->dev;
1326 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1328 if (dev->dev_mapping)
1329 unmap_mapping_range(dev->dev_mapping,
1330 obj_priv->mmap_offset, obj->size, 1);
1334 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1336 struct drm_device *dev = obj->dev;
1337 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1338 struct drm_gem_mm *mm = dev->mm_private;
1339 struct drm_map_list *list;
1341 list = &obj->map_list;
1342 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1344 if (list->file_offset_node) {
1345 drm_mm_put_block(list->file_offset_node);
1346 list->file_offset_node = NULL;
1354 obj_priv->mmap_offset = 0;
1358 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1359 * @obj: object to check
1361 * Return the required GTT alignment for an object, taking into account
1362 * potential fence register mapping if needed.
1365 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1367 struct drm_device *dev = obj->dev;
1368 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1372 * Minimum alignment is 4k (GTT page size), but might be greater
1373 * if a fence register is needed for the object.
1375 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1379 * Previous chips need to be aligned to the size of the smallest
1380 * fence register that can contain the object.
1387 for (i = start; i < obj->size; i <<= 1)
1394 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1396 * @data: GTT mapping ioctl data
1397 * @file_priv: GEM object info
1399 * Simply returns the fake offset to userspace so it can mmap it.
1400 * The mmap call will end up in drm_gem_mmap(), which will set things
1401 * up so we can get faults in the handler above.
1403 * The fault handler will take care of binding the object into the GTT
1404 * (since it may have been evicted to make room for something), allocating
1405 * a fence register, and mapping the appropriate aperture address into
1409 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv)
1412 struct drm_i915_gem_mmap_gtt *args = data;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct drm_gem_object *obj;
1415 struct drm_i915_gem_object *obj_priv;
1418 if (!(dev->driver->driver_features & DRIVER_GEM))
1421 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1425 mutex_lock(&dev->struct_mutex);
1427 obj_priv = obj->driver_private;
1429 if (obj_priv->madv != I915_MADV_WILLNEED) {
1430 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1431 drm_gem_object_unreference(obj);
1432 mutex_unlock(&dev->struct_mutex);
1437 if (!obj_priv->mmap_offset) {
1438 ret = i915_gem_create_mmap_offset(obj);
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
1446 args->offset = obj_priv->mmap_offset;
1449 * Pull it into the GTT so that we have a page list (makes the
1450 * initial fault faster and any subsequent flushing possible).
1452 if (!obj_priv->agp_mem) {
1453 ret = i915_gem_object_bind_to_gtt(obj, 0);
1455 drm_gem_object_unreference(obj);
1456 mutex_unlock(&dev->struct_mutex);
1459 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1462 drm_gem_object_unreference(obj);
1463 mutex_unlock(&dev->struct_mutex);
1469 i915_gem_object_put_pages(struct drm_gem_object *obj)
1471 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1472 int page_count = obj->size / PAGE_SIZE;
1475 BUG_ON(obj_priv->pages_refcount == 0);
1476 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1478 if (--obj_priv->pages_refcount != 0)
1481 if (obj_priv->tiling_mode != I915_TILING_NONE)
1482 i915_gem_object_save_bit_17_swizzle(obj);
1484 if (obj_priv->madv == I915_MADV_DONTNEED)
1485 obj_priv->dirty = 0;
1487 for (i = 0; i < page_count; i++) {
1488 if (obj_priv->pages[i] == NULL)
1491 if (obj_priv->dirty)
1492 set_page_dirty(obj_priv->pages[i]);
1494 if (obj_priv->madv == I915_MADV_WILLNEED)
1495 mark_page_accessed(obj_priv->pages[i]);
1497 page_cache_release(obj_priv->pages[i]);
1499 obj_priv->dirty = 0;
1501 drm_free_large(obj_priv->pages);
1502 obj_priv->pages = NULL;
1506 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1508 struct drm_device *dev = obj->dev;
1509 drm_i915_private_t *dev_priv = dev->dev_private;
1510 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1512 /* Add a reference if we're newly entering the active list. */
1513 if (!obj_priv->active) {
1514 drm_gem_object_reference(obj);
1515 obj_priv->active = 1;
1517 /* Move from whatever list we were on to the tail of execution. */
1518 spin_lock(&dev_priv->mm.active_list_lock);
1519 list_move_tail(&obj_priv->list,
1520 &dev_priv->mm.active_list);
1521 spin_unlock(&dev_priv->mm.active_list_lock);
1522 obj_priv->last_rendering_seqno = seqno;
1526 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1528 struct drm_device *dev = obj->dev;
1529 drm_i915_private_t *dev_priv = dev->dev_private;
1530 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1532 BUG_ON(!obj_priv->active);
1533 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1534 obj_priv->last_rendering_seqno = 0;
1537 /* Immediately discard the backing storage */
1539 i915_gem_object_truncate(struct drm_gem_object *obj)
1541 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1542 struct inode *inode;
1544 inode = obj->filp->f_path.dentry->d_inode;
1545 if (inode->i_op->truncate)
1546 inode->i_op->truncate (inode);
1548 obj_priv->madv = __I915_MADV_PURGED;
1552 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1554 return obj_priv->madv == I915_MADV_DONTNEED;
1558 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1560 struct drm_device *dev = obj->dev;
1561 drm_i915_private_t *dev_priv = dev->dev_private;
1562 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1564 i915_verify_inactive(dev, __FILE__, __LINE__);
1565 if (obj_priv->pin_count != 0)
1566 list_del_init(&obj_priv->list);
1568 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1570 obj_priv->last_rendering_seqno = 0;
1571 if (obj_priv->active) {
1572 obj_priv->active = 0;
1573 drm_gem_object_unreference(obj);
1575 i915_verify_inactive(dev, __FILE__, __LINE__);
1579 * Creates a new sequence number, emitting a write of it to the status page
1580 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1582 * Must be called with struct_lock held.
1584 * Returned sequence numbers are nonzero on success.
1587 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1588 uint32_t flush_domains)
1590 drm_i915_private_t *dev_priv = dev->dev_private;
1591 struct drm_i915_file_private *i915_file_priv = NULL;
1592 struct drm_i915_gem_request *request;
1597 if (file_priv != NULL)
1598 i915_file_priv = file_priv->driver_priv;
1600 request = kzalloc(sizeof(*request), GFP_KERNEL);
1601 if (request == NULL)
1604 /* Grab the seqno we're going to make this request be, and bump the
1605 * next (skipping 0 so it can be the reserved no-seqno value).
1607 seqno = dev_priv->mm.next_gem_seqno;
1608 dev_priv->mm.next_gem_seqno++;
1609 if (dev_priv->mm.next_gem_seqno == 0)
1610 dev_priv->mm.next_gem_seqno++;
1613 OUT_RING(MI_STORE_DWORD_INDEX);
1614 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1617 OUT_RING(MI_USER_INTERRUPT);
1620 DRM_DEBUG("%d\n", seqno);
1622 request->seqno = seqno;
1623 request->emitted_jiffies = jiffies;
1624 was_empty = list_empty(&dev_priv->mm.request_list);
1625 list_add_tail(&request->list, &dev_priv->mm.request_list);
1626 if (i915_file_priv) {
1627 list_add_tail(&request->client_list,
1628 &i915_file_priv->mm.request_list);
1630 INIT_LIST_HEAD(&request->client_list);
1633 /* Associate any objects on the flushing list matching the write
1634 * domain we're flushing with our flush.
1636 if (flush_domains != 0) {
1637 struct drm_i915_gem_object *obj_priv, *next;
1639 list_for_each_entry_safe(obj_priv, next,
1640 &dev_priv->mm.flushing_list, list) {
1641 struct drm_gem_object *obj = obj_priv->obj;
1643 if ((obj->write_domain & flush_domains) ==
1644 obj->write_domain) {
1645 uint32_t old_write_domain = obj->write_domain;
1647 obj->write_domain = 0;
1648 i915_gem_object_move_to_active(obj, seqno);
1650 trace_i915_gem_object_change_domain(obj,
1658 if (!dev_priv->mm.suspended) {
1659 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1661 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1667 * Command execution barrier
1669 * Ensures that all commands in the ring are finished
1670 * before signalling the CPU
1673 i915_retire_commands(struct drm_device *dev)
1675 drm_i915_private_t *dev_priv = dev->dev_private;
1676 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1677 uint32_t flush_domains = 0;
1680 /* The sampler always gets flushed on i965 (sigh) */
1682 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1685 OUT_RING(0); /* noop */
1687 return flush_domains;
1691 * Moves buffers associated only with the given active seqno from the active
1692 * to inactive list, potentially freeing them.
1695 i915_gem_retire_request(struct drm_device *dev,
1696 struct drm_i915_gem_request *request)
1698 drm_i915_private_t *dev_priv = dev->dev_private;
1700 trace_i915_gem_request_retire(dev, request->seqno);
1702 /* Move any buffers on the active list that are no longer referenced
1703 * by the ringbuffer to the flushing/inactive lists as appropriate.
1705 spin_lock(&dev_priv->mm.active_list_lock);
1706 while (!list_empty(&dev_priv->mm.active_list)) {
1707 struct drm_gem_object *obj;
1708 struct drm_i915_gem_object *obj_priv;
1710 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1711 struct drm_i915_gem_object,
1713 obj = obj_priv->obj;
1715 /* If the seqno being retired doesn't match the oldest in the
1716 * list, then the oldest in the list must still be newer than
1719 if (obj_priv->last_rendering_seqno != request->seqno)
1723 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1724 __func__, request->seqno, obj);
1727 if (obj->write_domain != 0)
1728 i915_gem_object_move_to_flushing(obj);
1730 /* Take a reference on the object so it won't be
1731 * freed while the spinlock is held. The list
1732 * protection for this spinlock is safe when breaking
1733 * the lock like this since the next thing we do
1734 * is just get the head of the list again.
1736 drm_gem_object_reference(obj);
1737 i915_gem_object_move_to_inactive(obj);
1738 spin_unlock(&dev_priv->mm.active_list_lock);
1739 drm_gem_object_unreference(obj);
1740 spin_lock(&dev_priv->mm.active_list_lock);
1744 spin_unlock(&dev_priv->mm.active_list_lock);
1748 * Returns true if seq1 is later than seq2.
1751 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1753 return (int32_t)(seq1 - seq2) >= 0;
1757 i915_get_gem_seqno(struct drm_device *dev)
1759 drm_i915_private_t *dev_priv = dev->dev_private;
1761 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1765 * This function clears the request list as sequence numbers are passed.
1768 i915_gem_retire_requests(struct drm_device *dev)
1770 drm_i915_private_t *dev_priv = dev->dev_private;
1773 if (!dev_priv->hw_status_page)
1776 seqno = i915_get_gem_seqno(dev);
1778 while (!list_empty(&dev_priv->mm.request_list)) {
1779 struct drm_i915_gem_request *request;
1780 uint32_t retiring_seqno;
1782 request = list_first_entry(&dev_priv->mm.request_list,
1783 struct drm_i915_gem_request,
1785 retiring_seqno = request->seqno;
1787 if (i915_seqno_passed(seqno, retiring_seqno) ||
1788 atomic_read(&dev_priv->mm.wedged)) {
1789 i915_gem_retire_request(dev, request);
1791 list_del(&request->list);
1792 list_del(&request->client_list);
1800 i915_gem_retire_work_handler(struct work_struct *work)
1802 drm_i915_private_t *dev_priv;
1803 struct drm_device *dev;
1805 dev_priv = container_of(work, drm_i915_private_t,
1806 mm.retire_work.work);
1807 dev = dev_priv->dev;
1809 mutex_lock(&dev->struct_mutex);
1810 i915_gem_retire_requests(dev);
1811 if (!dev_priv->mm.suspended &&
1812 !list_empty(&dev_priv->mm.request_list))
1813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1814 mutex_unlock(&dev->struct_mutex);
1818 * Waits for a sequence number to be signaled, and cleans up the
1819 * request and object lists appropriately for that event.
1822 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1824 drm_i915_private_t *dev_priv = dev->dev_private;
1830 if (atomic_read(&dev_priv->mm.wedged))
1833 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1835 ier = I915_READ(DEIER) | I915_READ(GTIER);
1837 ier = I915_READ(IER);
1839 DRM_ERROR("something (likely vbetool) disabled "
1840 "interrupts, re-enabling\n");
1841 i915_driver_irq_preinstall(dev);
1842 i915_driver_irq_postinstall(dev);
1845 trace_i915_gem_request_wait_begin(dev, seqno);
1847 dev_priv->mm.waiting_gem_seqno = seqno;
1848 i915_user_irq_get(dev);
1849 ret = wait_event_interruptible(dev_priv->irq_queue,
1850 i915_seqno_passed(i915_get_gem_seqno(dev),
1852 atomic_read(&dev_priv->mm.wedged));
1853 i915_user_irq_put(dev);
1854 dev_priv->mm.waiting_gem_seqno = 0;
1856 trace_i915_gem_request_wait_end(dev, seqno);
1858 if (atomic_read(&dev_priv->mm.wedged))
1861 if (ret && ret != -ERESTARTSYS)
1862 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1863 __func__, ret, seqno, i915_get_gem_seqno(dev));
1865 /* Directly dispatch request retiring. While we have the work queue
1866 * to handle this, the waiter on a request often wants an associated
1867 * buffer to have made it to the inactive list, and we would need
1868 * a separate wait queue to handle that.
1871 i915_gem_retire_requests(dev);
1877 i915_gem_flush(struct drm_device *dev,
1878 uint32_t invalidate_domains,
1879 uint32_t flush_domains)
1881 drm_i915_private_t *dev_priv = dev->dev_private;
1886 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1887 invalidate_domains, flush_domains);
1889 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1890 invalidate_domains, flush_domains);
1892 if (flush_domains & I915_GEM_DOMAIN_CPU)
1893 drm_agp_chipset_flush(dev);
1895 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1897 * read/write caches:
1899 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1900 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1901 * also flushed at 2d versus 3d pipeline switches.
1905 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1906 * MI_READ_FLUSH is set, and is always flushed on 965.
1908 * I915_GEM_DOMAIN_COMMAND may not exist?
1910 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1911 * invalidated when MI_EXE_FLUSH is set.
1913 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1914 * invalidated with every MI_FLUSH.
1918 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1919 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1920 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1921 * are flushed at any MI_FLUSH.
1924 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1925 if ((invalidate_domains|flush_domains) &
1926 I915_GEM_DOMAIN_RENDER)
1927 cmd &= ~MI_NO_WRITE_FLUSH;
1928 if (!IS_I965G(dev)) {
1930 * On the 965, the sampler cache always gets flushed
1931 * and this bit is reserved.
1933 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1934 cmd |= MI_READ_FLUSH;
1936 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1937 cmd |= MI_EXE_FLUSH;
1940 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1944 OUT_RING(0); /* noop */
1950 * Ensures that all rendering to the object has completed and the object is
1951 * safe to unbind from the GTT or access from the CPU.
1954 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1956 struct drm_device *dev = obj->dev;
1957 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1960 /* This function only exists to support waiting for existing rendering,
1961 * not for emitting required flushes.
1963 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1965 /* If there is rendering queued on the buffer being evicted, wait for
1968 if (obj_priv->active) {
1970 DRM_INFO("%s: object %p wait for seqno %08x\n",
1971 __func__, obj, obj_priv->last_rendering_seqno);
1973 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1982 * Unbinds an object from the GTT aperture.
1985 i915_gem_object_unbind(struct drm_gem_object *obj)
1987 struct drm_device *dev = obj->dev;
1988 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1992 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1993 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1995 if (obj_priv->gtt_space == NULL)
1998 if (obj_priv->pin_count != 0) {
1999 DRM_ERROR("Attempting to unbind pinned buffer\n");
2003 /* blow away mappings if mapped through GTT */
2004 i915_gem_release_mmap(obj);
2006 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2007 i915_gem_clear_fence_reg(obj);
2009 /* Move the object to the CPU domain to ensure that
2010 * any possible CPU writes while it's not in the GTT
2011 * are flushed when we go to remap it. This will
2012 * also ensure that all pending GPU writes are finished
2015 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2017 if (ret != -ERESTARTSYS)
2018 DRM_ERROR("set_domain failed: %d\n", ret);
2022 BUG_ON(obj_priv->active);
2024 if (obj_priv->agp_mem != NULL) {
2025 drm_unbind_agp(obj_priv->agp_mem);
2026 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2027 obj_priv->agp_mem = NULL;
2030 i915_gem_object_put_pages(obj);
2031 BUG_ON(obj_priv->pages_refcount);
2033 if (obj_priv->gtt_space) {
2034 atomic_dec(&dev->gtt_count);
2035 atomic_sub(obj->size, &dev->gtt_memory);
2037 drm_mm_put_block(obj_priv->gtt_space);
2038 obj_priv->gtt_space = NULL;
2041 /* Remove ourselves from the LRU list if present. */
2042 if (!list_empty(&obj_priv->list))
2043 list_del_init(&obj_priv->list);
2045 if (i915_gem_object_is_purgeable(obj_priv))
2046 i915_gem_object_truncate(obj);
2048 trace_i915_gem_object_unbind(obj);
2053 static struct drm_gem_object *
2054 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2056 drm_i915_private_t *dev_priv = dev->dev_private;
2057 struct drm_i915_gem_object *obj_priv;
2058 struct drm_gem_object *best = NULL;
2059 struct drm_gem_object *first = NULL;
2061 /* Try to find the smallest clean object */
2062 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2063 struct drm_gem_object *obj = obj_priv->obj;
2064 if (obj->size >= min_size) {
2065 if ((!obj_priv->dirty ||
2066 i915_gem_object_is_purgeable(obj_priv)) &&
2067 (!best || obj->size < best->size)) {
2069 if (best->size == min_size)
2077 return best ? best : first;
2081 i915_gem_evict_everything(struct drm_device *dev)
2083 drm_i915_private_t *dev_priv = dev->dev_private;
2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
2091 list_empty(&dev_priv->mm.active_list));
2092 spin_unlock(&dev_priv->mm.active_list_lock);
2097 /* Flush everything (on to the inactive lists) and evict */
2098 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2099 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2103 ret = i915_wait_request(dev, seqno);
2107 ret = i915_gem_evict_from_inactive_list(dev);
2111 spin_lock(&dev_priv->mm.active_list_lock);
2112 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2113 list_empty(&dev_priv->mm.flushing_list) &&
2114 list_empty(&dev_priv->mm.active_list));
2115 spin_unlock(&dev_priv->mm.active_list_lock);
2116 BUG_ON(!lists_empty);
2122 i915_gem_evict_something(struct drm_device *dev, int min_size)
2124 drm_i915_private_t *dev_priv = dev->dev_private;
2125 struct drm_gem_object *obj;
2129 i915_gem_retire_requests(dev);
2131 /* If there's an inactive buffer available now, grab it
2134 obj = i915_gem_find_inactive_object(dev, min_size);
2136 struct drm_i915_gem_object *obj_priv;
2139 DRM_INFO("%s: evicting %p\n", __func__, obj);
2141 obj_priv = obj->driver_private;
2142 BUG_ON(obj_priv->pin_count != 0);
2143 BUG_ON(obj_priv->active);
2145 /* Wait on the rendering and unbind the buffer. */
2146 return i915_gem_object_unbind(obj);
2149 /* If we didn't get anything, but the ring is still processing
2150 * things, wait for the next to finish and hopefully leave us
2151 * a buffer to evict.
2153 if (!list_empty(&dev_priv->mm.request_list)) {
2154 struct drm_i915_gem_request *request;
2156 request = list_first_entry(&dev_priv->mm.request_list,
2157 struct drm_i915_gem_request,
2160 ret = i915_wait_request(dev, request->seqno);
2167 /* If we didn't have anything on the request list but there
2168 * are buffers awaiting a flush, emit one and try again.
2169 * When we wait on it, those buffers waiting for that flush
2170 * will get moved to inactive.
2172 if (!list_empty(&dev_priv->mm.flushing_list)) {
2173 struct drm_i915_gem_object *obj_priv;
2175 /* Find an object that we can immediately reuse */
2176 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2177 obj = obj_priv->obj;
2178 if (obj->size >= min_size)
2190 seqno = i915_add_request(dev, NULL, obj->write_domain);
2194 ret = i915_wait_request(dev, seqno);
2202 /* If we didn't do any of the above, there's no single buffer
2203 * large enough to swap out for the new one, so just evict
2204 * everything and start again. (This should be rare.)
2206 if (!list_empty (&dev_priv->mm.inactive_list))
2207 return i915_gem_evict_from_inactive_list(dev);
2209 return i915_gem_evict_everything(dev);
2214 i915_gem_object_get_pages(struct drm_gem_object *obj)
2216 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2218 struct address_space *mapping;
2219 struct inode *inode;
2223 if (obj_priv->pages_refcount++ != 0)
2226 /* Get the list of pages out of our struct file. They'll be pinned
2227 * at this point until we release them.
2229 page_count = obj->size / PAGE_SIZE;
2230 BUG_ON(obj_priv->pages != NULL);
2231 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2232 if (obj_priv->pages == NULL) {
2233 obj_priv->pages_refcount--;
2237 inode = obj->filp->f_path.dentry->d_inode;
2238 mapping = inode->i_mapping;
2239 for (i = 0; i < page_count; i++) {
2240 page = read_mapping_page(mapping, i, NULL);
2242 ret = PTR_ERR(page);
2243 i915_gem_object_put_pages(obj);
2246 obj_priv->pages[i] = page;
2249 if (obj_priv->tiling_mode != I915_TILING_NONE)
2250 i915_gem_object_do_bit_17_swizzle(obj);
2255 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2257 struct drm_gem_object *obj = reg->obj;
2258 struct drm_device *dev = obj->dev;
2259 drm_i915_private_t *dev_priv = dev->dev_private;
2260 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2261 int regnum = obj_priv->fence_reg;
2264 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2266 val |= obj_priv->gtt_offset & 0xfffff000;
2267 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2268 if (obj_priv->tiling_mode == I915_TILING_Y)
2269 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2270 val |= I965_FENCE_REG_VALID;
2272 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2275 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2277 struct drm_gem_object *obj = reg->obj;
2278 struct drm_device *dev = obj->dev;
2279 drm_i915_private_t *dev_priv = dev->dev_private;
2280 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2281 int regnum = obj_priv->fence_reg;
2283 uint32_t fence_reg, val;
2286 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2287 (obj_priv->gtt_offset & (obj->size - 1))) {
2288 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2289 __func__, obj_priv->gtt_offset, obj->size);
2293 if (obj_priv->tiling_mode == I915_TILING_Y &&
2294 HAS_128_BYTE_Y_TILING(dev))
2299 /* Note: pitch better be a power of two tile widths */
2300 pitch_val = obj_priv->stride / tile_width;
2301 pitch_val = ffs(pitch_val) - 1;
2303 val = obj_priv->gtt_offset;
2304 if (obj_priv->tiling_mode == I915_TILING_Y)
2305 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2306 val |= I915_FENCE_SIZE_BITS(obj->size);
2307 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2308 val |= I830_FENCE_REG_VALID;
2311 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2313 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2314 I915_WRITE(fence_reg, val);
2317 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2319 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
2322 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2323 int regnum = obj_priv->fence_reg;
2326 uint32_t fence_size_bits;
2328 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2329 (obj_priv->gtt_offset & (obj->size - 1))) {
2330 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2331 __func__, obj_priv->gtt_offset);
2335 pitch_val = obj_priv->stride / 128;
2336 pitch_val = ffs(pitch_val) - 1;
2337 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2339 val = obj_priv->gtt_offset;
2340 if (obj_priv->tiling_mode == I915_TILING_Y)
2341 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2342 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2343 WARN_ON(fence_size_bits & ~0x00000f00);
2344 val |= fence_size_bits;
2345 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2346 val |= I830_FENCE_REG_VALID;
2348 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2352 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2353 * @obj: object to map through a fence reg
2355 * When mapping objects through the GTT, userspace wants to be able to write
2356 * to them without having to worry about swizzling if the object is tiled.
2358 * This function walks the fence regs looking for a free one for @obj,
2359 * stealing one if it can't find any.
2361 * It then sets up the reg based on the object's properties: address, pitch
2362 * and tiling format.
2365 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2367 struct drm_device *dev = obj->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2370 struct drm_i915_fence_reg *reg = NULL;
2371 struct drm_i915_gem_object *old_obj_priv = NULL;
2374 /* Just update our place in the LRU if our fence is getting used. */
2375 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2376 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2380 switch (obj_priv->tiling_mode) {
2381 case I915_TILING_NONE:
2382 WARN(1, "allocating a fence for non-tiled object?\n");
2385 if (!obj_priv->stride)
2387 WARN((obj_priv->stride & (512 - 1)),
2388 "object 0x%08x is X tiled but has non-512B pitch\n",
2389 obj_priv->gtt_offset);
2392 if (!obj_priv->stride)
2394 WARN((obj_priv->stride & (128 - 1)),
2395 "object 0x%08x is Y tiled but has non-128B pitch\n",
2396 obj_priv->gtt_offset);
2400 /* First try to find a free reg */
2402 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2403 reg = &dev_priv->fence_regs[i];
2407 old_obj_priv = reg->obj->driver_private;
2408 if (!old_obj_priv->pin_count)
2412 /* None available, try to steal one or wait for a user to finish */
2413 if (i == dev_priv->num_fence_regs) {
2414 struct drm_gem_object *old_obj = NULL;
2419 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2421 old_obj = old_obj_priv->obj;
2423 if (old_obj_priv->pin_count)
2426 /* Take a reference, as otherwise the wait_rendering
2427 * below may cause the object to get freed out from
2430 drm_gem_object_reference(old_obj);
2432 /* i915 uses fences for GPU access to tiled buffers */
2433 if (IS_I965G(dev) || !old_obj_priv->active)
2436 /* This brings the object to the head of the LRU if it
2437 * had been written to. The only way this should
2438 * result in us waiting longer than the expected
2439 * optimal amount of time is if there was a
2440 * fence-using buffer later that was read-only.
2442 i915_gem_object_flush_gpu_write_domain(old_obj);
2443 ret = i915_gem_object_wait_rendering(old_obj);
2445 drm_gem_object_unreference(old_obj);
2453 * Zap this virtual mapping so we can set up a fence again
2454 * for this object next time we need it.
2456 i915_gem_release_mmap(old_obj);
2458 i = old_obj_priv->fence_reg;
2459 reg = &dev_priv->fence_regs[i];
2461 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2462 list_del_init(&old_obj_priv->fence_list);
2464 drm_gem_object_unreference(old_obj);
2467 obj_priv->fence_reg = i;
2468 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2473 i965_write_fence_reg(reg);
2474 else if (IS_I9XX(dev))
2475 i915_write_fence_reg(reg);
2477 i830_write_fence_reg(reg);
2479 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2485 * i915_gem_clear_fence_reg - clear out fence register info
2486 * @obj: object to clear
2488 * Zeroes out the fence register itself and clears out the associated
2489 * data structures in dev_priv and obj_priv.
2492 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2494 struct drm_device *dev = obj->dev;
2495 drm_i915_private_t *dev_priv = dev->dev_private;
2496 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2499 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2503 if (obj_priv->fence_reg < 8)
2504 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2506 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2509 I915_WRITE(fence_reg, 0);
2512 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2513 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2514 list_del_init(&obj_priv->fence_list);
2518 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2519 * to the buffer to finish, and then resets the fence register.
2520 * @obj: tiled object holding a fence register.
2522 * Zeroes out the fence register itself and clears out the associated
2523 * data structures in dev_priv and obj_priv.
2526 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2528 struct drm_device *dev = obj->dev;
2529 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2531 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2534 /* On the i915, GPU access to tiled buffers is via a fence,
2535 * therefore we must wait for any outstanding access to complete
2536 * before clearing the fence.
2538 if (!IS_I965G(dev)) {
2541 i915_gem_object_flush_gpu_write_domain(obj);
2542 i915_gem_object_flush_gtt_write_domain(obj);
2543 ret = i915_gem_object_wait_rendering(obj);
2548 i915_gem_clear_fence_reg (obj);
2554 * Finds free space in the GTT aperture and binds the object there.
2557 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2559 struct drm_device *dev = obj->dev;
2560 drm_i915_private_t *dev_priv = dev->dev_private;
2561 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2562 struct drm_mm_node *free_space;
2563 bool retry_alloc = false;
2566 if (dev_priv->mm.suspended)
2569 if (obj_priv->madv != I915_MADV_WILLNEED) {
2570 DRM_ERROR("Attempting to bind a purgeable object\n");
2575 alignment = i915_gem_get_gtt_alignment(obj);
2576 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2577 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2582 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2583 obj->size, alignment, 0);
2584 if (free_space != NULL) {
2585 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2587 if (obj_priv->gtt_space != NULL) {
2588 obj_priv->gtt_space->private = obj;
2589 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2592 if (obj_priv->gtt_space == NULL) {
2593 /* If the gtt is empty and we're still having trouble
2594 * fitting our object in, we're out of memory.
2597 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2599 ret = i915_gem_evict_something(dev, obj->size);
2607 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2608 obj->size, obj_priv->gtt_offset);
2611 i915_gem_object_set_page_gfp_mask (obj,
2612 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2614 ret = i915_gem_object_get_pages(obj);
2616 i915_gem_object_set_page_gfp_mask (obj,
2617 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2620 drm_mm_put_block(obj_priv->gtt_space);
2621 obj_priv->gtt_space = NULL;
2623 if (ret == -ENOMEM) {
2624 /* first try to clear up some space from the GTT */
2625 ret = i915_gem_evict_something(dev, obj->size);
2627 /* now try to shrink everyone else */
2628 if (! retry_alloc) {
2642 /* Create an AGP memory structure pointing at our pages, and bind it
2645 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2647 obj->size >> PAGE_SHIFT,
2648 obj_priv->gtt_offset,
2649 obj_priv->agp_type);
2650 if (obj_priv->agp_mem == NULL) {
2651 i915_gem_object_put_pages(obj);
2652 drm_mm_put_block(obj_priv->gtt_space);
2653 obj_priv->gtt_space = NULL;
2655 ret = i915_gem_evict_something(dev, obj->size);
2661 atomic_inc(&dev->gtt_count);
2662 atomic_add(obj->size, &dev->gtt_memory);
2664 /* Assert that the object is not currently in any GPU domain. As it
2665 * wasn't in the GTT, there shouldn't be any way it could have been in
2668 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2669 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2671 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2677 i915_gem_clflush_object(struct drm_gem_object *obj)
2679 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2681 /* If we don't have a page list set up, then we're not pinned
2682 * to GPU, and we can ignore the cache flush because it'll happen
2683 * again at bind time.
2685 if (obj_priv->pages == NULL)
2688 trace_i915_gem_object_clflush(obj);
2690 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2693 /** Flushes any GPU write domain for the object if it's dirty. */
2695 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2697 struct drm_device *dev = obj->dev;
2699 uint32_t old_write_domain;
2701 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2704 /* Queue the GPU write cache flushing we need. */
2705 old_write_domain = obj->write_domain;
2706 i915_gem_flush(dev, 0, obj->write_domain);
2707 seqno = i915_add_request(dev, NULL, obj->write_domain);
2708 obj->write_domain = 0;
2709 i915_gem_object_move_to_active(obj, seqno);
2711 trace_i915_gem_object_change_domain(obj,
2716 /** Flushes the GTT write domain for the object if it's dirty. */
2718 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2720 uint32_t old_write_domain;
2722 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2725 /* No actual flushing is required for the GTT write domain. Writes
2726 * to it immediately go to main memory as far as we know, so there's
2727 * no chipset flush. It also doesn't land in render cache.
2729 old_write_domain = obj->write_domain;
2730 obj->write_domain = 0;
2732 trace_i915_gem_object_change_domain(obj,
2737 /** Flushes the CPU write domain for the object if it's dirty. */
2739 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2741 struct drm_device *dev = obj->dev;
2742 uint32_t old_write_domain;
2744 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2747 i915_gem_clflush_object(obj);
2748 drm_agp_chipset_flush(dev);
2749 old_write_domain = obj->write_domain;
2750 obj->write_domain = 0;
2752 trace_i915_gem_object_change_domain(obj,
2758 * Moves a single object to the GTT read, and possibly write domain.
2760 * This function returns when the move is complete, including waiting on
2764 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2766 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2767 uint32_t old_write_domain, old_read_domains;
2770 /* Not valid to be called on unbound objects. */
2771 if (obj_priv->gtt_space == NULL)
2774 i915_gem_object_flush_gpu_write_domain(obj);
2775 /* Wait on any GPU rendering and flushing to occur. */
2776 ret = i915_gem_object_wait_rendering(obj);
2780 old_write_domain = obj->write_domain;
2781 old_read_domains = obj->read_domains;
2783 /* If we're writing through the GTT domain, then CPU and GPU caches
2784 * will need to be invalidated at next use.
2787 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2789 i915_gem_object_flush_cpu_write_domain(obj);
2791 /* It should now be out of any other write domains, and we can update
2792 * the domain values for our changes.
2794 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2795 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2797 obj->write_domain = I915_GEM_DOMAIN_GTT;
2798 obj_priv->dirty = 1;
2801 trace_i915_gem_object_change_domain(obj,
2809 * Moves a single object to the CPU read, and possibly write domain.
2811 * This function returns when the move is complete, including waiting on
2815 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2817 uint32_t old_write_domain, old_read_domains;
2820 i915_gem_object_flush_gpu_write_domain(obj);
2821 /* Wait on any GPU rendering and flushing to occur. */
2822 ret = i915_gem_object_wait_rendering(obj);
2826 i915_gem_object_flush_gtt_write_domain(obj);
2828 /* If we have a partially-valid cache of the object in the CPU,
2829 * finish invalidating it and free the per-page flags.
2831 i915_gem_object_set_to_full_cpu_read_domain(obj);
2833 old_write_domain = obj->write_domain;
2834 old_read_domains = obj->read_domains;
2836 /* Flush the CPU cache if it's still invalid. */
2837 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2838 i915_gem_clflush_object(obj);
2840 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2843 /* It should now be out of any other write domains, and we can update
2844 * the domain values for our changes.
2846 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2848 /* If we're writing through the CPU, then the GPU read domains will
2849 * need to be invalidated at next use.
2852 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2853 obj->write_domain = I915_GEM_DOMAIN_CPU;
2856 trace_i915_gem_object_change_domain(obj,
2864 * Set the next domain for the specified object. This
2865 * may not actually perform the necessary flushing/invaliding though,
2866 * as that may want to be batched with other set_domain operations
2868 * This is (we hope) the only really tricky part of gem. The goal
2869 * is fairly simple -- track which caches hold bits of the object
2870 * and make sure they remain coherent. A few concrete examples may
2871 * help to explain how it works. For shorthand, we use the notation
2872 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2873 * a pair of read and write domain masks.
2875 * Case 1: the batch buffer
2881 * 5. Unmapped from GTT
2884 * Let's take these a step at a time
2887 * Pages allocated from the kernel may still have
2888 * cache contents, so we set them to (CPU, CPU) always.
2889 * 2. Written by CPU (using pwrite)
2890 * The pwrite function calls set_domain (CPU, CPU) and
2891 * this function does nothing (as nothing changes)
2893 * This function asserts that the object is not
2894 * currently in any GPU-based read or write domains
2896 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2897 * As write_domain is zero, this function adds in the
2898 * current read domains (CPU+COMMAND, 0).
2899 * flush_domains is set to CPU.
2900 * invalidate_domains is set to COMMAND
2901 * clflush is run to get data out of the CPU caches
2902 * then i915_dev_set_domain calls i915_gem_flush to
2903 * emit an MI_FLUSH and drm_agp_chipset_flush
2904 * 5. Unmapped from GTT
2905 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2906 * flush_domains and invalidate_domains end up both zero
2907 * so no flushing/invalidating happens
2911 * Case 2: The shared render buffer
2915 * 3. Read/written by GPU
2916 * 4. set_domain to (CPU,CPU)
2917 * 5. Read/written by CPU
2918 * 6. Read/written by GPU
2921 * Same as last example, (CPU, CPU)
2923 * Nothing changes (assertions find that it is not in the GPU)
2924 * 3. Read/written by GPU
2925 * execbuffer calls set_domain (RENDER, RENDER)
2926 * flush_domains gets CPU
2927 * invalidate_domains gets GPU
2929 * MI_FLUSH and drm_agp_chipset_flush
2930 * 4. set_domain (CPU, CPU)
2931 * flush_domains gets GPU
2932 * invalidate_domains gets CPU
2933 * wait_rendering (obj) to make sure all drawing is complete.
2934 * This will include an MI_FLUSH to get the data from GPU
2936 * clflush (obj) to invalidate the CPU cache
2937 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2938 * 5. Read/written by CPU
2939 * cache lines are loaded and dirtied
2940 * 6. Read written by GPU
2941 * Same as last GPU access
2943 * Case 3: The constant buffer
2948 * 4. Updated (written) by CPU again
2957 * flush_domains = CPU
2958 * invalidate_domains = RENDER
2961 * drm_agp_chipset_flush
2962 * 4. Updated (written) by CPU again
2964 * flush_domains = 0 (no previous write domain)
2965 * invalidate_domains = 0 (no new read domains)
2968 * flush_domains = CPU
2969 * invalidate_domains = RENDER
2972 * drm_agp_chipset_flush
2975 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2977 struct drm_device *dev = obj->dev;
2978 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2979 uint32_t invalidate_domains = 0;
2980 uint32_t flush_domains = 0;
2981 uint32_t old_read_domains;
2983 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2984 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2986 intel_mark_busy(dev, obj);
2989 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2991 obj->read_domains, obj->pending_read_domains,
2992 obj->write_domain, obj->pending_write_domain);
2995 * If the object isn't moving to a new write domain,
2996 * let the object stay in multiple read domains
2998 if (obj->pending_write_domain == 0)
2999 obj->pending_read_domains |= obj->read_domains;
3001 obj_priv->dirty = 1;
3004 * Flush the current write domain if
3005 * the new read domains don't match. Invalidate
3006 * any read domains which differ from the old
3009 if (obj->write_domain &&
3010 obj->write_domain != obj->pending_read_domains) {
3011 flush_domains |= obj->write_domain;
3012 invalidate_domains |=
3013 obj->pending_read_domains & ~obj->write_domain;
3016 * Invalidate any read caches which may have
3017 * stale data. That is, any new read domains.
3019 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3020 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3022 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3023 __func__, flush_domains, invalidate_domains);
3025 i915_gem_clflush_object(obj);
3028 old_read_domains = obj->read_domains;
3030 /* The actual obj->write_domain will be updated with
3031 * pending_write_domain after we emit the accumulated flush for all
3032 * of our domain changes in execbuffers (which clears objects'
3033 * write_domains). So if we have a current write domain that we
3034 * aren't changing, set pending_write_domain to that.
3036 if (flush_domains == 0 && obj->pending_write_domain == 0)
3037 obj->pending_write_domain = obj->write_domain;
3038 obj->read_domains = obj->pending_read_domains;
3040 dev->invalidate_domains |= invalidate_domains;
3041 dev->flush_domains |= flush_domains;
3043 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3045 obj->read_domains, obj->write_domain,
3046 dev->invalidate_domains, dev->flush_domains);
3049 trace_i915_gem_object_change_domain(obj,
3055 * Moves the object from a partially CPU read to a full one.
3057 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3058 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3061 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3063 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3065 if (!obj_priv->page_cpu_valid)
3068 /* If we're partially in the CPU read domain, finish moving it in.
3070 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3073 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3074 if (obj_priv->page_cpu_valid[i])
3076 drm_clflush_pages(obj_priv->pages + i, 1);
3080 /* Free the page_cpu_valid mappings which are now stale, whether
3081 * or not we've got I915_GEM_DOMAIN_CPU.
3083 kfree(obj_priv->page_cpu_valid);
3084 obj_priv->page_cpu_valid = NULL;
3088 * Set the CPU read domain on a range of the object.
3090 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3091 * not entirely valid. The page_cpu_valid member of the object flags which
3092 * pages have been flushed, and will be respected by
3093 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3094 * of the whole object.
3096 * This function returns when the move is complete, including waiting on
3100 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3101 uint64_t offset, uint64_t size)
3103 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3104 uint32_t old_read_domains;
3107 if (offset == 0 && size == obj->size)
3108 return i915_gem_object_set_to_cpu_domain(obj, 0);
3110 i915_gem_object_flush_gpu_write_domain(obj);
3111 /* Wait on any GPU rendering and flushing to occur. */
3112 ret = i915_gem_object_wait_rendering(obj);
3115 i915_gem_object_flush_gtt_write_domain(obj);
3117 /* If we're already fully in the CPU read domain, we're done. */
3118 if (obj_priv->page_cpu_valid == NULL &&
3119 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3122 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3123 * newly adding I915_GEM_DOMAIN_CPU
3125 if (obj_priv->page_cpu_valid == NULL) {
3126 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3128 if (obj_priv->page_cpu_valid == NULL)
3130 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3131 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3133 /* Flush the cache on any pages that are still invalid from the CPU's
3136 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3138 if (obj_priv->page_cpu_valid[i])
3141 drm_clflush_pages(obj_priv->pages + i, 1);
3143 obj_priv->page_cpu_valid[i] = 1;
3146 /* It should now be out of any other write domains, and we can update
3147 * the domain values for our changes.
3149 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3151 old_read_domains = obj->read_domains;
3152 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3154 trace_i915_gem_object_change_domain(obj,
3162 * Pin an object to the GTT and evaluate the relocations landing in it.
3165 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3166 struct drm_file *file_priv,
3167 struct drm_i915_gem_exec_object *entry,
3168 struct drm_i915_gem_relocation_entry *relocs)
3170 struct drm_device *dev = obj->dev;
3171 drm_i915_private_t *dev_priv = dev->dev_private;
3172 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3174 void __iomem *reloc_page;
3176 /* Choose the GTT offset for our buffer and put it there. */
3177 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3181 entry->offset = obj_priv->gtt_offset;
3183 /* Apply the relocations, using the GTT aperture to avoid cache
3184 * flushing requirements.
3186 for (i = 0; i < entry->relocation_count; i++) {
3187 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3188 struct drm_gem_object *target_obj;
3189 struct drm_i915_gem_object *target_obj_priv;
3190 uint32_t reloc_val, reloc_offset;
3191 uint32_t __iomem *reloc_entry;
3193 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3194 reloc->target_handle);
3195 if (target_obj == NULL) {
3196 i915_gem_object_unpin(obj);
3199 target_obj_priv = target_obj->driver_private;
3202 DRM_INFO("%s: obj %p offset %08x target %d "
3203 "read %08x write %08x gtt %08x "
3204 "presumed %08x delta %08x\n",
3207 (int) reloc->offset,
3208 (int) reloc->target_handle,
3209 (int) reloc->read_domains,
3210 (int) reloc->write_domain,
3211 (int) target_obj_priv->gtt_offset,
3212 (int) reloc->presumed_offset,
3216 /* The target buffer should have appeared before us in the
3217 * exec_object list, so it should have a GTT space bound by now.
3219 if (target_obj_priv->gtt_space == NULL) {
3220 DRM_ERROR("No GTT space found for object %d\n",
3221 reloc->target_handle);
3222 drm_gem_object_unreference(target_obj);
3223 i915_gem_object_unpin(obj);
3227 /* Validate that the target is in a valid r/w GPU domain */
3228 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3229 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3230 DRM_ERROR("reloc with read/write CPU domains: "
3231 "obj %p target %d offset %d "
3232 "read %08x write %08x",
3233 obj, reloc->target_handle,
3234 (int) reloc->offset,
3235 reloc->read_domains,
3236 reloc->write_domain);
3237 drm_gem_object_unreference(target_obj);
3238 i915_gem_object_unpin(obj);
3241 if (reloc->write_domain && target_obj->pending_write_domain &&
3242 reloc->write_domain != target_obj->pending_write_domain) {
3243 DRM_ERROR("Write domain conflict: "
3244 "obj %p target %d offset %d "
3245 "new %08x old %08x\n",
3246 obj, reloc->target_handle,
3247 (int) reloc->offset,
3248 reloc->write_domain,
3249 target_obj->pending_write_domain);
3250 drm_gem_object_unreference(target_obj);
3251 i915_gem_object_unpin(obj);
3255 target_obj->pending_read_domains |= reloc->read_domains;
3256 target_obj->pending_write_domain |= reloc->write_domain;
3258 /* If the relocation already has the right value in it, no
3259 * more work needs to be done.
3261 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3262 drm_gem_object_unreference(target_obj);
3266 /* Check that the relocation address is valid... */
3267 if (reloc->offset > obj->size - 4) {
3268 DRM_ERROR("Relocation beyond object bounds: "
3269 "obj %p target %d offset %d size %d.\n",
3270 obj, reloc->target_handle,
3271 (int) reloc->offset, (int) obj->size);
3272 drm_gem_object_unreference(target_obj);
3273 i915_gem_object_unpin(obj);
3276 if (reloc->offset & 3) {
3277 DRM_ERROR("Relocation not 4-byte aligned: "
3278 "obj %p target %d offset %d.\n",
3279 obj, reloc->target_handle,
3280 (int) reloc->offset);
3281 drm_gem_object_unreference(target_obj);
3282 i915_gem_object_unpin(obj);
3286 /* and points to somewhere within the target object. */
3287 if (reloc->delta >= target_obj->size) {
3288 DRM_ERROR("Relocation beyond target object bounds: "
3289 "obj %p target %d delta %d size %d.\n",
3290 obj, reloc->target_handle,
3291 (int) reloc->delta, (int) target_obj->size);
3292 drm_gem_object_unreference(target_obj);
3293 i915_gem_object_unpin(obj);
3297 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3299 drm_gem_object_unreference(target_obj);
3300 i915_gem_object_unpin(obj);
3304 /* Map the page containing the relocation we're going to
3307 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3308 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3311 reloc_entry = (uint32_t __iomem *)(reloc_page +
3312 (reloc_offset & (PAGE_SIZE - 1)));
3313 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3316 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3317 obj, (unsigned int) reloc->offset,
3318 readl(reloc_entry), reloc_val);
3320 writel(reloc_val, reloc_entry);
3321 io_mapping_unmap_atomic(reloc_page);
3323 /* The updated presumed offset for this entry will be
3324 * copied back out to the user.
3326 reloc->presumed_offset = target_obj_priv->gtt_offset;
3328 drm_gem_object_unreference(target_obj);
3333 i915_gem_dump_object(obj, 128, __func__, ~0);
3338 /** Dispatch a batchbuffer to the ring
3341 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3342 struct drm_i915_gem_execbuffer *exec,
3343 struct drm_clip_rect *cliprects,
3344 uint64_t exec_offset)
3346 drm_i915_private_t *dev_priv = dev->dev_private;
3347 int nbox = exec->num_cliprects;
3349 uint32_t exec_start, exec_len;
3352 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3353 exec_len = (uint32_t) exec->batch_len;
3355 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3357 count = nbox ? nbox : 1;
3359 for (i = 0; i < count; i++) {
3361 int ret = i915_emit_box(dev, cliprects, i,
3362 exec->DR1, exec->DR4);
3367 if (IS_I830(dev) || IS_845G(dev)) {
3369 OUT_RING(MI_BATCH_BUFFER);
3370 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3371 OUT_RING(exec_start + exec_len - 4);
3376 if (IS_I965G(dev)) {
3377 OUT_RING(MI_BATCH_BUFFER_START |
3379 MI_BATCH_NON_SECURE_I965);
3380 OUT_RING(exec_start);
3382 OUT_RING(MI_BATCH_BUFFER_START |
3384 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3390 /* XXX breadcrumb */
3394 /* Throttle our rendering by waiting until the ring has completed our requests
3395 * emitted over 20 msec ago.
3397 * Note that if we were to use the current jiffies each time around the loop,
3398 * we wouldn't escape the function with any frames outstanding if the time to
3399 * render a frame was over 20ms.
3401 * This should get us reasonable parallelism between CPU and GPU but also
3402 * relatively low latency when blocking on a particular request to finish.
3405 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3407 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3409 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3411 mutex_lock(&dev->struct_mutex);
3412 while (!list_empty(&i915_file_priv->mm.request_list)) {
3413 struct drm_i915_gem_request *request;
3415 request = list_first_entry(&i915_file_priv->mm.request_list,
3416 struct drm_i915_gem_request,
3419 if (time_after_eq(request->emitted_jiffies, recent_enough))
3422 ret = i915_wait_request(dev, request->seqno);
3426 mutex_unlock(&dev->struct_mutex);
3432 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3433 uint32_t buffer_count,
3434 struct drm_i915_gem_relocation_entry **relocs)
3436 uint32_t reloc_count = 0, reloc_index = 0, i;
3440 for (i = 0; i < buffer_count; i++) {
3441 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3443 reloc_count += exec_list[i].relocation_count;
3446 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3447 if (*relocs == NULL)
3450 for (i = 0; i < buffer_count; i++) {
3451 struct drm_i915_gem_relocation_entry __user *user_relocs;
3453 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3455 ret = copy_from_user(&(*relocs)[reloc_index],
3457 exec_list[i].relocation_count *
3460 drm_free_large(*relocs);
3465 reloc_index += exec_list[i].relocation_count;
3472 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3473 uint32_t buffer_count,
3474 struct drm_i915_gem_relocation_entry *relocs)
3476 uint32_t reloc_count = 0, i;
3479 for (i = 0; i < buffer_count; i++) {
3480 struct drm_i915_gem_relocation_entry __user *user_relocs;
3483 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3485 unwritten = copy_to_user(user_relocs,
3486 &relocs[reloc_count],
3487 exec_list[i].relocation_count *
3495 reloc_count += exec_list[i].relocation_count;
3499 drm_free_large(relocs);
3505 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3506 uint64_t exec_offset)
3508 uint32_t exec_start, exec_len;
3510 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3511 exec_len = (uint32_t) exec->batch_len;
3513 if ((exec_start | exec_len) & 0x7)
3523 i915_gem_execbuffer(struct drm_device *dev, void *data,
3524 struct drm_file *file_priv)
3526 drm_i915_private_t *dev_priv = dev->dev_private;
3527 struct drm_i915_gem_execbuffer *args = data;
3528 struct drm_i915_gem_exec_object *exec_list = NULL;
3529 struct drm_gem_object **object_list = NULL;
3530 struct drm_gem_object *batch_obj;
3531 struct drm_i915_gem_object *obj_priv;
3532 struct drm_clip_rect *cliprects = NULL;
3533 struct drm_i915_gem_relocation_entry *relocs;
3534 int ret, ret2, i, pinned = 0;
3535 uint64_t exec_offset;
3536 uint32_t seqno, flush_domains, reloc_index;
3540 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3541 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3544 if (args->buffer_count < 1) {
3545 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3548 /* Copy in the exec list from userland */
3549 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3550 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3551 if (exec_list == NULL || object_list == NULL) {
3552 DRM_ERROR("Failed to allocate exec or object list "
3554 args->buffer_count);
3558 ret = copy_from_user(exec_list,
3559 (struct drm_i915_relocation_entry __user *)
3560 (uintptr_t) args->buffers_ptr,
3561 sizeof(*exec_list) * args->buffer_count);
3563 DRM_ERROR("copy %d exec entries failed %d\n",
3564 args->buffer_count, ret);
3568 if (args->num_cliprects != 0) {
3569 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3571 if (cliprects == NULL)
3574 ret = copy_from_user(cliprects,
3575 (struct drm_clip_rect __user *)
3576 (uintptr_t) args->cliprects_ptr,
3577 sizeof(*cliprects) * args->num_cliprects);
3579 DRM_ERROR("copy %d cliprects failed: %d\n",
3580 args->num_cliprects, ret);
3585 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3590 mutex_lock(&dev->struct_mutex);
3592 i915_verify_inactive(dev, __FILE__, __LINE__);
3594 if (atomic_read(&dev_priv->mm.wedged)) {
3595 DRM_ERROR("Execbuf while wedged\n");
3596 mutex_unlock(&dev->struct_mutex);
3601 if (dev_priv->mm.suspended) {
3602 DRM_ERROR("Execbuf while VT-switched.\n");
3603 mutex_unlock(&dev->struct_mutex);
3608 /* Look up object handles */
3609 for (i = 0; i < args->buffer_count; i++) {
3610 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3611 exec_list[i].handle);
3612 if (object_list[i] == NULL) {
3613 DRM_ERROR("Invalid object handle %d at index %d\n",
3614 exec_list[i].handle, i);
3619 obj_priv = object_list[i]->driver_private;
3620 if (obj_priv->in_execbuffer) {
3621 DRM_ERROR("Object %p appears more than once in object list\n",
3626 obj_priv->in_execbuffer = true;
3629 /* Pin and relocate */
3630 for (pin_tries = 0; ; pin_tries++) {
3634 for (i = 0; i < args->buffer_count; i++) {
3635 object_list[i]->pending_read_domains = 0;
3636 object_list[i]->pending_write_domain = 0;
3637 ret = i915_gem_object_pin_and_relocate(object_list[i],
3640 &relocs[reloc_index]);
3644 reloc_index += exec_list[i].relocation_count;
3650 /* error other than GTT full, or we've already tried again */
3651 if (ret != -ENOSPC || pin_tries >= 1) {
3652 if (ret != -ERESTARTSYS) {
3653 unsigned long long total_size = 0;
3654 for (i = 0; i < args->buffer_count; i++)
3655 total_size += object_list[i]->size;
3656 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3657 pinned+1, args->buffer_count,
3659 DRM_ERROR("%d objects [%d pinned], "
3660 "%d object bytes [%d pinned], "
3661 "%d/%d gtt bytes\n",
3662 atomic_read(&dev->object_count),
3663 atomic_read(&dev->pin_count),
3664 atomic_read(&dev->object_memory),
3665 atomic_read(&dev->pin_memory),
3666 atomic_read(&dev->gtt_memory),
3672 /* unpin all of our buffers */
3673 for (i = 0; i < pinned; i++)
3674 i915_gem_object_unpin(object_list[i]);
3677 /* evict everyone we can from the aperture */
3678 ret = i915_gem_evict_everything(dev);
3679 if (ret && ret != -ENOSPC)
3683 /* Set the pending read domains for the batch buffer to COMMAND */
3684 batch_obj = object_list[args->buffer_count-1];
3685 if (batch_obj->pending_write_domain) {
3686 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3690 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3692 /* Sanity check the batch buffer, prior to moving objects */
3693 exec_offset = exec_list[args->buffer_count - 1].offset;
3694 ret = i915_gem_check_execbuffer (args, exec_offset);
3696 DRM_ERROR("execbuf with invalid offset/length\n");
3700 i915_verify_inactive(dev, __FILE__, __LINE__);
3702 /* Zero the global flush/invalidate flags. These
3703 * will be modified as new domains are computed
3706 dev->invalidate_domains = 0;
3707 dev->flush_domains = 0;
3709 for (i = 0; i < args->buffer_count; i++) {
3710 struct drm_gem_object *obj = object_list[i];
3712 /* Compute new gpu domains and update invalidate/flush */
3713 i915_gem_object_set_to_gpu_domain(obj);
3716 i915_verify_inactive(dev, __FILE__, __LINE__);
3718 if (dev->invalidate_domains | dev->flush_domains) {
3720 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3722 dev->invalidate_domains,
3723 dev->flush_domains);
3726 dev->invalidate_domains,
3727 dev->flush_domains);
3728 if (dev->flush_domains)
3729 (void)i915_add_request(dev, file_priv,
3730 dev->flush_domains);
3733 for (i = 0; i < args->buffer_count; i++) {
3734 struct drm_gem_object *obj = object_list[i];
3735 uint32_t old_write_domain = obj->write_domain;
3737 obj->write_domain = obj->pending_write_domain;
3738 trace_i915_gem_object_change_domain(obj,
3743 i915_verify_inactive(dev, __FILE__, __LINE__);
3746 for (i = 0; i < args->buffer_count; i++) {
3747 i915_gem_object_check_coherency(object_list[i],
3748 exec_list[i].handle);
3753 i915_gem_dump_object(batch_obj,
3759 /* Exec the batchbuffer */
3760 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3762 DRM_ERROR("dispatch failed %d\n", ret);
3767 * Ensure that the commands in the batch buffer are
3768 * finished before the interrupt fires
3770 flush_domains = i915_retire_commands(dev);
3772 i915_verify_inactive(dev, __FILE__, __LINE__);
3775 * Get a seqno representing the execution of the current buffer,
3776 * which we can wait on. We would like to mitigate these interrupts,
3777 * likely by only creating seqnos occasionally (so that we have
3778 * *some* interrupts representing completion of buffers that we can
3779 * wait on when trying to clear up gtt space).
3781 seqno = i915_add_request(dev, file_priv, flush_domains);
3783 for (i = 0; i < args->buffer_count; i++) {
3784 struct drm_gem_object *obj = object_list[i];
3786 i915_gem_object_move_to_active(obj, seqno);
3788 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3792 i915_dump_lru(dev, __func__);
3795 i915_verify_inactive(dev, __FILE__, __LINE__);
3798 for (i = 0; i < pinned; i++)
3799 i915_gem_object_unpin(object_list[i]);
3801 for (i = 0; i < args->buffer_count; i++) {
3802 if (object_list[i]) {
3803 obj_priv = object_list[i]->driver_private;
3804 obj_priv->in_execbuffer = false;
3806 drm_gem_object_unreference(object_list[i]);
3809 mutex_unlock(&dev->struct_mutex);
3812 /* Copy the new buffer offsets back to the user's exec list. */
3813 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3814 (uintptr_t) args->buffers_ptr,
3816 sizeof(*exec_list) * args->buffer_count);
3819 DRM_ERROR("failed to copy %d exec entries "
3820 "back to user (%d)\n",
3821 args->buffer_count, ret);
3825 /* Copy the updated relocations out regardless of current error
3826 * state. Failure to update the relocs would mean that the next
3827 * time userland calls execbuf, it would do so with presumed offset
3828 * state that didn't match the actual object state.
3830 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3833 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3840 drm_free_large(object_list);
3841 drm_free_large(exec_list);
3848 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3850 struct drm_device *dev = obj->dev;
3851 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3854 i915_verify_inactive(dev, __FILE__, __LINE__);
3855 if (obj_priv->gtt_space == NULL) {
3856 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3861 * Pre-965 chips need a fence register set up in order to
3862 * properly handle tiled surfaces.
3864 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3865 ret = i915_gem_object_get_fence_reg(obj);
3867 if (ret != -EBUSY && ret != -ERESTARTSYS)
3868 DRM_ERROR("Failure to install fence: %d\n",
3873 obj_priv->pin_count++;
3875 /* If the object is not active and not pending a flush,
3876 * remove it from the inactive list
3878 if (obj_priv->pin_count == 1) {
3879 atomic_inc(&dev->pin_count);
3880 atomic_add(obj->size, &dev->pin_memory);
3881 if (!obj_priv->active &&
3882 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3883 !list_empty(&obj_priv->list))
3884 list_del_init(&obj_priv->list);
3886 i915_verify_inactive(dev, __FILE__, __LINE__);
3892 i915_gem_object_unpin(struct drm_gem_object *obj)
3894 struct drm_device *dev = obj->dev;
3895 drm_i915_private_t *dev_priv = dev->dev_private;
3896 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3898 i915_verify_inactive(dev, __FILE__, __LINE__);
3899 obj_priv->pin_count--;
3900 BUG_ON(obj_priv->pin_count < 0);
3901 BUG_ON(obj_priv->gtt_space == NULL);
3903 /* If the object is no longer pinned, and is
3904 * neither active nor being flushed, then stick it on
3907 if (obj_priv->pin_count == 0) {
3908 if (!obj_priv->active &&
3909 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3910 list_move_tail(&obj_priv->list,
3911 &dev_priv->mm.inactive_list);
3912 atomic_dec(&dev->pin_count);
3913 atomic_sub(obj->size, &dev->pin_memory);
3915 i915_verify_inactive(dev, __FILE__, __LINE__);
3919 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3920 struct drm_file *file_priv)
3922 struct drm_i915_gem_pin *args = data;
3923 struct drm_gem_object *obj;
3924 struct drm_i915_gem_object *obj_priv;
3927 mutex_lock(&dev->struct_mutex);
3929 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3931 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3933 mutex_unlock(&dev->struct_mutex);
3936 obj_priv = obj->driver_private;
3938 if (obj_priv->madv != I915_MADV_WILLNEED) {
3939 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3940 drm_gem_object_unreference(obj);
3941 mutex_unlock(&dev->struct_mutex);
3945 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3946 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3948 drm_gem_object_unreference(obj);
3949 mutex_unlock(&dev->struct_mutex);
3953 obj_priv->user_pin_count++;
3954 obj_priv->pin_filp = file_priv;
3955 if (obj_priv->user_pin_count == 1) {
3956 ret = i915_gem_object_pin(obj, args->alignment);
3958 drm_gem_object_unreference(obj);
3959 mutex_unlock(&dev->struct_mutex);
3964 /* XXX - flush the CPU caches for pinned objects
3965 * as the X server doesn't manage domains yet
3967 i915_gem_object_flush_cpu_write_domain(obj);
3968 args->offset = obj_priv->gtt_offset;
3969 drm_gem_object_unreference(obj);
3970 mutex_unlock(&dev->struct_mutex);
3976 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3977 struct drm_file *file_priv)
3979 struct drm_i915_gem_pin *args = data;
3980 struct drm_gem_object *obj;
3981 struct drm_i915_gem_object *obj_priv;
3983 mutex_lock(&dev->struct_mutex);
3985 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3987 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3989 mutex_unlock(&dev->struct_mutex);
3993 obj_priv = obj->driver_private;
3994 if (obj_priv->pin_filp != file_priv) {
3995 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3997 drm_gem_object_unreference(obj);
3998 mutex_unlock(&dev->struct_mutex);
4001 obj_priv->user_pin_count--;
4002 if (obj_priv->user_pin_count == 0) {
4003 obj_priv->pin_filp = NULL;
4004 i915_gem_object_unpin(obj);
4007 drm_gem_object_unreference(obj);
4008 mutex_unlock(&dev->struct_mutex);
4013 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4014 struct drm_file *file_priv)
4016 struct drm_i915_gem_busy *args = data;
4017 struct drm_gem_object *obj;
4018 struct drm_i915_gem_object *obj_priv;
4020 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4022 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4027 mutex_lock(&dev->struct_mutex);
4028 /* Update the active list for the hardware's current position.
4029 * Otherwise this only updates on a delayed timer or when irqs are
4030 * actually unmasked, and our working set ends up being larger than
4033 i915_gem_retire_requests(dev);
4035 obj_priv = obj->driver_private;
4036 /* Don't count being on the flushing list against the object being
4037 * done. Otherwise, a buffer left on the flushing list but not getting
4038 * flushed (because nobody's flushing that domain) won't ever return
4039 * unbusy and get reused by libdrm's bo cache. The other expected
4040 * consumer of this interface, OpenGL's occlusion queries, also specs
4041 * that the objects get unbusy "eventually" without any interference.
4043 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4045 drm_gem_object_unreference(obj);
4046 mutex_unlock(&dev->struct_mutex);
4051 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4052 struct drm_file *file_priv)
4054 return i915_gem_ring_throttle(dev, file_priv);
4058 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4059 struct drm_file *file_priv)
4061 struct drm_i915_gem_madvise *args = data;
4062 struct drm_gem_object *obj;
4063 struct drm_i915_gem_object *obj_priv;
4065 switch (args->madv) {
4066 case I915_MADV_DONTNEED:
4067 case I915_MADV_WILLNEED:
4073 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4075 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4080 mutex_lock(&dev->struct_mutex);
4081 obj_priv = obj->driver_private;
4083 if (obj_priv->pin_count) {
4084 drm_gem_object_unreference(obj);
4085 mutex_unlock(&dev->struct_mutex);
4087 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4091 if (obj_priv->madv != __I915_MADV_PURGED)
4092 obj_priv->madv = args->madv;
4094 /* if the object is no longer bound, discard its backing storage */
4095 if (i915_gem_object_is_purgeable(obj_priv) &&
4096 obj_priv->gtt_space == NULL)
4097 i915_gem_object_truncate(obj);
4099 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4101 drm_gem_object_unreference(obj);
4102 mutex_unlock(&dev->struct_mutex);
4107 int i915_gem_init_object(struct drm_gem_object *obj)
4109 struct drm_i915_gem_object *obj_priv;
4111 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4112 if (obj_priv == NULL)
4116 * We've just allocated pages from the kernel,
4117 * so they've just been written by the CPU with
4118 * zeros. They'll need to be clflushed before we
4119 * use them with the GPU.
4121 obj->write_domain = I915_GEM_DOMAIN_CPU;
4122 obj->read_domains = I915_GEM_DOMAIN_CPU;
4124 obj_priv->agp_type = AGP_USER_MEMORY;
4126 obj->driver_private = obj_priv;
4127 obj_priv->obj = obj;
4128 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4129 INIT_LIST_HEAD(&obj_priv->list);
4130 INIT_LIST_HEAD(&obj_priv->fence_list);
4131 obj_priv->madv = I915_MADV_WILLNEED;
4133 trace_i915_gem_object_create(obj);
4138 void i915_gem_free_object(struct drm_gem_object *obj)
4140 struct drm_device *dev = obj->dev;
4141 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4143 trace_i915_gem_object_destroy(obj);
4145 while (obj_priv->pin_count > 0)
4146 i915_gem_object_unpin(obj);
4148 if (obj_priv->phys_obj)
4149 i915_gem_detach_phys_object(dev, obj);
4151 i915_gem_object_unbind(obj);
4153 if (obj_priv->mmap_offset)
4154 i915_gem_free_mmap_offset(obj);
4156 kfree(obj_priv->page_cpu_valid);
4157 kfree(obj_priv->bit_17);
4158 kfree(obj->driver_private);
4161 /** Unbinds all inactive objects. */
4163 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4165 drm_i915_private_t *dev_priv = dev->dev_private;
4167 while (!list_empty(&dev_priv->mm.inactive_list)) {
4168 struct drm_gem_object *obj;
4171 obj = list_first_entry(&dev_priv->mm.inactive_list,
4172 struct drm_i915_gem_object,
4175 ret = i915_gem_object_unbind(obj);
4177 DRM_ERROR("Error unbinding object: %d\n", ret);
4186 i915_gem_idle(struct drm_device *dev)
4188 drm_i915_private_t *dev_priv = dev->dev_private;
4189 uint32_t seqno, cur_seqno, last_seqno;
4192 mutex_lock(&dev->struct_mutex);
4194 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4195 mutex_unlock(&dev->struct_mutex);
4199 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4200 * We need to replace this with a semaphore, or something.
4202 dev_priv->mm.suspended = 1;
4203 del_timer(&dev_priv->hangcheck_timer);
4205 /* Cancel the retire work handler, wait for it to finish if running
4207 mutex_unlock(&dev->struct_mutex);
4208 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4209 mutex_lock(&dev->struct_mutex);
4211 i915_kernel_lost_context(dev);
4213 /* Flush the GPU along with all non-CPU write domains
4215 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4216 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4219 mutex_unlock(&dev->struct_mutex);
4223 dev_priv->mm.waiting_gem_seqno = seqno;
4227 cur_seqno = i915_get_gem_seqno(dev);
4228 if (i915_seqno_passed(cur_seqno, seqno))
4230 if (last_seqno == cur_seqno) {
4231 if (stuck++ > 100) {
4232 DRM_ERROR("hardware wedged\n");
4233 atomic_set(&dev_priv->mm.wedged, 1);
4234 DRM_WAKEUP(&dev_priv->irq_queue);
4239 last_seqno = cur_seqno;
4241 dev_priv->mm.waiting_gem_seqno = 0;
4243 i915_gem_retire_requests(dev);
4245 spin_lock(&dev_priv->mm.active_list_lock);
4246 if (!atomic_read(&dev_priv->mm.wedged)) {
4247 /* Active and flushing should now be empty as we've
4248 * waited for a sequence higher than any pending execbuffer
4250 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4251 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4252 /* Request should now be empty as we've also waited
4253 * for the last request in the list
4255 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4258 /* Empty the active and flushing lists to inactive. If there's
4259 * anything left at this point, it means that we're wedged and
4260 * nothing good's going to happen by leaving them there. So strip
4261 * the GPU domains and just stuff them onto inactive.
4263 while (!list_empty(&dev_priv->mm.active_list)) {
4264 struct drm_gem_object *obj;
4265 uint32_t old_write_domain;
4267 obj = list_first_entry(&dev_priv->mm.active_list,
4268 struct drm_i915_gem_object,
4270 old_write_domain = obj->write_domain;
4271 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4272 i915_gem_object_move_to_inactive(obj);
4274 trace_i915_gem_object_change_domain(obj,
4278 spin_unlock(&dev_priv->mm.active_list_lock);
4280 while (!list_empty(&dev_priv->mm.flushing_list)) {
4281 struct drm_gem_object *obj;
4282 uint32_t old_write_domain;
4284 obj = list_first_entry(&dev_priv->mm.flushing_list,
4285 struct drm_i915_gem_object,
4287 old_write_domain = obj->write_domain;
4288 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4289 i915_gem_object_move_to_inactive(obj);
4291 trace_i915_gem_object_change_domain(obj,
4297 /* Move all inactive buffers out of the GTT. */
4298 ret = i915_gem_evict_from_inactive_list(dev);
4299 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4301 mutex_unlock(&dev->struct_mutex);
4305 i915_gem_cleanup_ringbuffer(dev);
4306 mutex_unlock(&dev->struct_mutex);
4312 i915_gem_init_hws(struct drm_device *dev)
4314 drm_i915_private_t *dev_priv = dev->dev_private;
4315 struct drm_gem_object *obj;
4316 struct drm_i915_gem_object *obj_priv;
4319 /* If we need a physical address for the status page, it's already
4320 * initialized at driver load time.
4322 if (!I915_NEED_GFX_HWS(dev))
4325 obj = drm_gem_object_alloc(dev, 4096);
4327 DRM_ERROR("Failed to allocate status page\n");
4330 obj_priv = obj->driver_private;
4331 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4333 ret = i915_gem_object_pin(obj, 4096);
4335 drm_gem_object_unreference(obj);
4339 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4341 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4342 if (dev_priv->hw_status_page == NULL) {
4343 DRM_ERROR("Failed to map status page.\n");
4344 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4345 i915_gem_object_unpin(obj);
4346 drm_gem_object_unreference(obj);
4349 dev_priv->hws_obj = obj;
4350 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4351 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4352 I915_READ(HWS_PGA); /* posting read */
4353 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4359 i915_gem_cleanup_hws(struct drm_device *dev)
4361 drm_i915_private_t *dev_priv = dev->dev_private;
4362 struct drm_gem_object *obj;
4363 struct drm_i915_gem_object *obj_priv;
4365 if (dev_priv->hws_obj == NULL)
4368 obj = dev_priv->hws_obj;
4369 obj_priv = obj->driver_private;
4371 kunmap(obj_priv->pages[0]);
4372 i915_gem_object_unpin(obj);
4373 drm_gem_object_unreference(obj);
4374 dev_priv->hws_obj = NULL;
4376 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4377 dev_priv->hw_status_page = NULL;
4379 /* Write high address into HWS_PGA when disabling. */
4380 I915_WRITE(HWS_PGA, 0x1ffff000);
4384 i915_gem_init_ringbuffer(struct drm_device *dev)
4386 drm_i915_private_t *dev_priv = dev->dev_private;
4387 struct drm_gem_object *obj;
4388 struct drm_i915_gem_object *obj_priv;
4389 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4393 ret = i915_gem_init_hws(dev);
4397 obj = drm_gem_object_alloc(dev, 128 * 1024);
4399 DRM_ERROR("Failed to allocate ringbuffer\n");
4400 i915_gem_cleanup_hws(dev);
4403 obj_priv = obj->driver_private;
4405 ret = i915_gem_object_pin(obj, 4096);
4407 drm_gem_object_unreference(obj);
4408 i915_gem_cleanup_hws(dev);
4412 /* Set up the kernel mapping for the ring. */
4413 ring->Size = obj->size;
4415 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4416 ring->map.size = obj->size;
4418 ring->map.flags = 0;
4421 drm_core_ioremap_wc(&ring->map, dev);
4422 if (ring->map.handle == NULL) {
4423 DRM_ERROR("Failed to map ringbuffer.\n");
4424 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4425 i915_gem_object_unpin(obj);
4426 drm_gem_object_unreference(obj);
4427 i915_gem_cleanup_hws(dev);
4430 ring->ring_obj = obj;
4431 ring->virtual_start = ring->map.handle;
4433 /* Stop the ring if it's running. */
4434 I915_WRITE(PRB0_CTL, 0);
4435 I915_WRITE(PRB0_TAIL, 0);
4436 I915_WRITE(PRB0_HEAD, 0);
4438 /* Initialize the ring. */
4439 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4440 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4442 /* G45 ring initialization fails to reset head to zero */
4444 DRM_ERROR("Ring head not reset to zero "
4445 "ctl %08x head %08x tail %08x start %08x\n",
4446 I915_READ(PRB0_CTL),
4447 I915_READ(PRB0_HEAD),
4448 I915_READ(PRB0_TAIL),
4449 I915_READ(PRB0_START));
4450 I915_WRITE(PRB0_HEAD, 0);
4452 DRM_ERROR("Ring head forced to zero "
4453 "ctl %08x head %08x tail %08x start %08x\n",
4454 I915_READ(PRB0_CTL),
4455 I915_READ(PRB0_HEAD),
4456 I915_READ(PRB0_TAIL),
4457 I915_READ(PRB0_START));
4460 I915_WRITE(PRB0_CTL,
4461 ((obj->size - 4096) & RING_NR_PAGES) |
4465 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4467 /* If the head is still not zero, the ring is dead */
4469 DRM_ERROR("Ring initialization failed "
4470 "ctl %08x head %08x tail %08x start %08x\n",
4471 I915_READ(PRB0_CTL),
4472 I915_READ(PRB0_HEAD),
4473 I915_READ(PRB0_TAIL),
4474 I915_READ(PRB0_START));
4478 /* Update our cache of the ring state */
4479 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4480 i915_kernel_lost_context(dev);
4482 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4483 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4484 ring->space = ring->head - (ring->tail + 8);
4485 if (ring->space < 0)
4486 ring->space += ring->Size;
4493 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4495 drm_i915_private_t *dev_priv = dev->dev_private;
4497 if (dev_priv->ring.ring_obj == NULL)
4500 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4502 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4503 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4504 dev_priv->ring.ring_obj = NULL;
4505 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4507 i915_gem_cleanup_hws(dev);
4511 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4512 struct drm_file *file_priv)
4514 drm_i915_private_t *dev_priv = dev->dev_private;
4517 if (drm_core_check_feature(dev, DRIVER_MODESET))
4520 if (atomic_read(&dev_priv->mm.wedged)) {
4521 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4522 atomic_set(&dev_priv->mm.wedged, 0);
4525 mutex_lock(&dev->struct_mutex);
4526 dev_priv->mm.suspended = 0;
4528 ret = i915_gem_init_ringbuffer(dev);
4530 mutex_unlock(&dev->struct_mutex);
4534 spin_lock(&dev_priv->mm.active_list_lock);
4535 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4536 spin_unlock(&dev_priv->mm.active_list_lock);
4538 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4539 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4540 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4541 mutex_unlock(&dev->struct_mutex);
4543 drm_irq_install(dev);
4549 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4550 struct drm_file *file_priv)
4552 if (drm_core_check_feature(dev, DRIVER_MODESET))
4555 drm_irq_uninstall(dev);
4556 return i915_gem_idle(dev);
4560 i915_gem_lastclose(struct drm_device *dev)
4564 if (drm_core_check_feature(dev, DRIVER_MODESET))
4567 ret = i915_gem_idle(dev);
4569 DRM_ERROR("failed to idle hardware: %d\n", ret);
4573 i915_gem_load(struct drm_device *dev)
4576 drm_i915_private_t *dev_priv = dev->dev_private;
4578 spin_lock_init(&dev_priv->mm.active_list_lock);
4579 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4580 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4581 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4583 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4584 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4585 i915_gem_retire_work_handler);
4586 dev_priv->mm.next_gem_seqno = 1;
4588 spin_lock(&shrink_list_lock);
4589 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4590 spin_unlock(&shrink_list_lock);
4592 /* Old X drivers will take 0-2 for front, back, depth buffers */
4593 dev_priv->fence_reg_start = 3;
4595 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4596 dev_priv->num_fence_regs = 16;
4598 dev_priv->num_fence_regs = 8;
4600 /* Initialize fence registers to zero */
4601 if (IS_I965G(dev)) {
4602 for (i = 0; i < 16; i++)
4603 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4605 for (i = 0; i < 8; i++)
4606 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4607 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4608 for (i = 0; i < 8; i++)
4609 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4612 i915_gem_detect_bit_6_swizzle(dev);
4616 * Create a physically contiguous memory object for this object
4617 * e.g. for cursor + overlay regs
4619 int i915_gem_init_phys_object(struct drm_device *dev,
4622 drm_i915_private_t *dev_priv = dev->dev_private;
4623 struct drm_i915_gem_phys_object *phys_obj;
4626 if (dev_priv->mm.phys_objs[id - 1] || !size)
4629 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4635 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4636 if (!phys_obj->handle) {
4641 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4644 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4652 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4654 drm_i915_private_t *dev_priv = dev->dev_private;
4655 struct drm_i915_gem_phys_object *phys_obj;
4657 if (!dev_priv->mm.phys_objs[id - 1])
4660 phys_obj = dev_priv->mm.phys_objs[id - 1];
4661 if (phys_obj->cur_obj) {
4662 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4666 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4668 drm_pci_free(dev, phys_obj->handle);
4670 dev_priv->mm.phys_objs[id - 1] = NULL;
4673 void i915_gem_free_all_phys_object(struct drm_device *dev)
4677 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4678 i915_gem_free_phys_object(dev, i);
4681 void i915_gem_detach_phys_object(struct drm_device *dev,
4682 struct drm_gem_object *obj)
4684 struct drm_i915_gem_object *obj_priv;
4689 obj_priv = obj->driver_private;
4690 if (!obj_priv->phys_obj)
4693 ret = i915_gem_object_get_pages(obj);
4697 page_count = obj->size / PAGE_SIZE;
4699 for (i = 0; i < page_count; i++) {
4700 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4701 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4703 memcpy(dst, src, PAGE_SIZE);
4704 kunmap_atomic(dst, KM_USER0);
4706 drm_clflush_pages(obj_priv->pages, page_count);
4707 drm_agp_chipset_flush(dev);
4709 i915_gem_object_put_pages(obj);
4711 obj_priv->phys_obj->cur_obj = NULL;
4712 obj_priv->phys_obj = NULL;
4716 i915_gem_attach_phys_object(struct drm_device *dev,
4717 struct drm_gem_object *obj, int id)
4719 drm_i915_private_t *dev_priv = dev->dev_private;
4720 struct drm_i915_gem_object *obj_priv;
4725 if (id > I915_MAX_PHYS_OBJECT)
4728 obj_priv = obj->driver_private;
4730 if (obj_priv->phys_obj) {
4731 if (obj_priv->phys_obj->id == id)
4733 i915_gem_detach_phys_object(dev, obj);
4737 /* create a new object */
4738 if (!dev_priv->mm.phys_objs[id - 1]) {
4739 ret = i915_gem_init_phys_object(dev, id,
4742 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4747 /* bind to the object */
4748 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4749 obj_priv->phys_obj->cur_obj = obj;
4751 ret = i915_gem_object_get_pages(obj);
4753 DRM_ERROR("failed to get page list\n");
4757 page_count = obj->size / PAGE_SIZE;
4759 for (i = 0; i < page_count; i++) {
4760 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4761 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4763 memcpy(dst, src, PAGE_SIZE);
4764 kunmap_atomic(src, KM_USER0);
4767 i915_gem_object_put_pages(obj);
4775 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4776 struct drm_i915_gem_pwrite *args,
4777 struct drm_file *file_priv)
4779 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4782 char __user *user_data;
4784 user_data = (char __user *) (uintptr_t) args->data_ptr;
4785 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4787 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4788 ret = copy_from_user(obj_addr, user_data, args->size);
4792 drm_agp_chipset_flush(dev);
4796 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4798 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4800 /* Clean up our request list when the client is going away, so that
4801 * later retire_requests won't dereference our soon-to-be-gone
4804 mutex_lock(&dev->struct_mutex);
4805 while (!list_empty(&i915_file_priv->mm.request_list))
4806 list_del_init(i915_file_priv->mm.request_list.next);
4807 mutex_unlock(&dev->struct_mutex);
4811 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4813 drm_i915_private_t *dev_priv, *next_dev;
4814 struct drm_i915_gem_object *obj_priv, *next_obj;
4816 int would_deadlock = 1;
4818 /* "fast-path" to count number of available objects */
4819 if (nr_to_scan == 0) {
4820 spin_lock(&shrink_list_lock);
4821 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4822 struct drm_device *dev = dev_priv->dev;
4824 if (mutex_trylock(&dev->struct_mutex)) {
4825 list_for_each_entry(obj_priv,
4826 &dev_priv->mm.inactive_list,
4829 mutex_unlock(&dev->struct_mutex);
4832 spin_unlock(&shrink_list_lock);
4834 return (cnt / 100) * sysctl_vfs_cache_pressure;
4837 spin_lock(&shrink_list_lock);
4839 /* first scan for clean buffers */
4840 list_for_each_entry_safe(dev_priv, next_dev,
4841 &shrink_list, mm.shrink_list) {
4842 struct drm_device *dev = dev_priv->dev;
4844 if (! mutex_trylock(&dev->struct_mutex))
4847 spin_unlock(&shrink_list_lock);
4849 i915_gem_retire_requests(dev);
4851 list_for_each_entry_safe(obj_priv, next_obj,
4852 &dev_priv->mm.inactive_list,
4854 if (i915_gem_object_is_purgeable(obj_priv)) {
4855 i915_gem_object_unbind(obj_priv->obj);
4856 if (--nr_to_scan <= 0)
4861 spin_lock(&shrink_list_lock);
4862 mutex_unlock(&dev->struct_mutex);
4866 if (nr_to_scan <= 0)
4870 /* second pass, evict/count anything still on the inactive list */
4871 list_for_each_entry_safe(dev_priv, next_dev,
4872 &shrink_list, mm.shrink_list) {
4873 struct drm_device *dev = dev_priv->dev;
4875 if (! mutex_trylock(&dev->struct_mutex))
4878 spin_unlock(&shrink_list_lock);
4880 list_for_each_entry_safe(obj_priv, next_obj,
4881 &dev_priv->mm.inactive_list,
4883 if (nr_to_scan > 0) {
4884 i915_gem_object_unbind(obj_priv->obj);
4890 spin_lock(&shrink_list_lock);
4891 mutex_unlock(&dev->struct_mutex);
4896 spin_unlock(&shrink_list_lock);
4901 return (cnt / 100) * sysctl_vfs_cache_pressure;
4906 static struct shrinker shrinker = {
4907 .shrink = i915_gem_shrink,
4908 .seeks = DEFAULT_SEEKS,
4912 i915_gem_shrinker_init(void)
4914 register_shrinker(&shrinker);
4918 i915_gem_shrinker_exit(void)
4920 unregister_shrinker(&shrinker);