2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915_prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915_prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
974 static void fake_irq(unsigned long data)
976 wake_up_process((struct task_struct *)data);
979 static bool missed_irq(struct drm_i915_private *dev_priv,
980 struct intel_ring_buffer *ring)
982 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
986 * __wait_seqno - wait until execution of seqno has finished
987 * @ring: the ring expected to report seqno
989 * @reset_counter: reset sequence associated with the given seqno
990 * @interruptible: do an interruptible wait (normally yes)
991 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
993 * Note: It is of utmost importance that the passed in seqno and reset_counter
994 * values have been read by the caller in an smp safe manner. Where read-side
995 * locks are involved, it is sufficient to read the reset_counter before
996 * unlocking the lock that protects the seqno. For lockless tricks, the
997 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1000 * Returns 0 if the seqno was found within the alloted time. Else returns the
1001 * errno with remaining time filled in timeout argument.
1003 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1004 unsigned reset_counter,
1005 bool interruptible, struct timespec *timeout)
1007 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1008 struct timespec before, now;
1010 long timeout_jiffies;
1013 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1015 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1018 timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1;
1020 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) &&
1021 WARN_ON(!ring->irq_get(ring)))
1024 /* Record current time in case interrupted by signal, or wedged */
1025 trace_i915_gem_request_wait_begin(ring, seqno);
1026 getrawmonotonic(&before);
1028 struct timer_list timer;
1029 unsigned long expire;
1031 prepare_to_wait(&ring->irq_queue, &wait,
1032 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1034 /* We need to check whether any gpu reset happened in between
1035 * the caller grabbing the seqno and now ... */
1036 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1037 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1038 * is truely gone. */
1039 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1045 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1050 if (interruptible && signal_pending(current)) {
1055 if (timeout_jiffies <= 0) {
1060 timer.function = NULL;
1061 if (timeout || missed_irq(dev_priv, ring)) {
1062 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1063 expire = jiffies + (missed_irq(dev_priv, ring) ? 1: timeout_jiffies);
1064 mod_timer(&timer, expire);
1070 timeout_jiffies = expire - jiffies;
1072 if (timer.function) {
1073 del_singleshot_timer_sync(&timer);
1074 destroy_timer_on_stack(&timer);
1077 getrawmonotonic(&now);
1078 trace_i915_gem_request_wait_end(ring, seqno);
1080 ring->irq_put(ring);
1082 finish_wait(&ring->irq_queue, &wait);
1085 struct timespec sleep_time = timespec_sub(now, before);
1086 *timeout = timespec_sub(*timeout, sleep_time);
1087 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1088 set_normalized_timespec(timeout, 0, 0);
1095 * Waits for a sequence number to be signaled, and cleans up the
1096 * request and object lists appropriately for that event.
1099 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1101 struct drm_device *dev = ring->dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 bool interruptible = dev_priv->mm.interruptible;
1106 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1109 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1113 ret = i915_gem_check_olr(ring, seqno);
1117 return __wait_seqno(ring, seqno,
1118 atomic_read(&dev_priv->gpu_error.reset_counter),
1119 interruptible, NULL);
1123 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1124 struct intel_ring_buffer *ring)
1126 i915_gem_retire_requests_ring(ring);
1128 /* Manually manage the write flush as we may have not yet
1129 * retired the buffer.
1131 * Note that the last_write_seqno is always the earlier of
1132 * the two (read/write) seqno, so if we haved successfully waited,
1133 * we know we have passed the last write.
1135 obj->last_write_seqno = 0;
1136 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1142 * Ensures that all rendering to the object has completed and the object is
1143 * safe to unbind from the GTT or access from the CPU.
1145 static __must_check int
1146 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1149 struct intel_ring_buffer *ring = obj->ring;
1153 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1157 ret = i915_wait_seqno(ring, seqno);
1161 return i915_gem_object_wait_rendering__tail(obj, ring);
1164 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1165 * as the object state may change during this call.
1167 static __must_check int
1168 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1171 struct drm_device *dev = obj->base.dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct intel_ring_buffer *ring = obj->ring;
1174 unsigned reset_counter;
1178 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1179 BUG_ON(!dev_priv->mm.interruptible);
1181 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1185 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1189 ret = i915_gem_check_olr(ring, seqno);
1193 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1194 mutex_unlock(&dev->struct_mutex);
1195 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1196 mutex_lock(&dev->struct_mutex);
1200 return i915_gem_object_wait_rendering__tail(obj, ring);
1204 * Called when user space prepares to use an object with the CPU, either
1205 * through the mmap ioctl's mapping or a GTT mapping.
1208 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1209 struct drm_file *file)
1211 struct drm_i915_gem_set_domain *args = data;
1212 struct drm_i915_gem_object *obj;
1213 uint32_t read_domains = args->read_domains;
1214 uint32_t write_domain = args->write_domain;
1217 /* Only handle setting domains to types used by the CPU. */
1218 if (write_domain & I915_GEM_GPU_DOMAINS)
1221 if (read_domains & I915_GEM_GPU_DOMAINS)
1224 /* Having something in the write domain implies it's in the read
1225 * domain, and only that read domain. Enforce that in the request.
1227 if (write_domain != 0 && read_domains != write_domain)
1230 ret = i915_mutex_lock_interruptible(dev);
1234 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1235 if (&obj->base == NULL) {
1240 /* Try to flush the object off the GPU without holding the lock.
1241 * We will repeat the flush holding the lock in the normal manner
1242 * to catch cases where we are gazumped.
1244 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1248 if (read_domains & I915_GEM_DOMAIN_GTT) {
1249 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1251 /* Silently promote "you're not bound, there was nothing to do"
1252 * to success, since the client was just asking us to
1253 * make sure everything was done.
1258 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1262 drm_gem_object_unreference(&obj->base);
1264 mutex_unlock(&dev->struct_mutex);
1269 * Called when user space has done writes to this buffer
1272 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1273 struct drm_file *file)
1275 struct drm_i915_gem_sw_finish *args = data;
1276 struct drm_i915_gem_object *obj;
1279 ret = i915_mutex_lock_interruptible(dev);
1283 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1284 if (&obj->base == NULL) {
1289 /* Pinned buffers may be scanout, so flush the cache */
1290 if (obj->pin_display)
1291 i915_gem_object_flush_cpu_write_domain(obj, true);
1293 drm_gem_object_unreference(&obj->base);
1295 mutex_unlock(&dev->struct_mutex);
1300 * Maps the contents of an object, returning the address it is mapped
1303 * While the mapping holds a reference on the contents of the object, it doesn't
1304 * imply a ref on the object itself.
1307 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1308 struct drm_file *file)
1310 struct drm_i915_gem_mmap *args = data;
1311 struct drm_gem_object *obj;
1314 obj = drm_gem_object_lookup(dev, file, args->handle);
1318 /* prime objects have no backing filp to GEM mmap
1322 drm_gem_object_unreference_unlocked(obj);
1326 addr = vm_mmap(obj->filp, 0, args->size,
1327 PROT_READ | PROT_WRITE, MAP_SHARED,
1329 drm_gem_object_unreference_unlocked(obj);
1330 if (IS_ERR((void *)addr))
1333 args->addr_ptr = (uint64_t) addr;
1339 * i915_gem_fault - fault a page into the GTT
1340 * vma: VMA in question
1343 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1344 * from userspace. The fault handler takes care of binding the object to
1345 * the GTT (if needed), allocating and programming a fence register (again,
1346 * only if needed based on whether the old reg is still valid or the object
1347 * is tiled) and inserting a new PTE into the faulting process.
1349 * Note that the faulting process may involve evicting existing objects
1350 * from the GTT and/or fence registers to make room. So performance may
1351 * suffer if the GTT working set is large or there are few fence registers
1354 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1356 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1357 struct drm_device *dev = obj->base.dev;
1358 drm_i915_private_t *dev_priv = dev->dev_private;
1359 pgoff_t page_offset;
1362 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1364 /* We don't use vmf->pgoff since that has the fake offset */
1365 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1368 ret = i915_mutex_lock_interruptible(dev);
1372 trace_i915_gem_object_fault(obj, page_offset, true, write);
1374 /* Access to snoopable pages through the GTT is incoherent. */
1375 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1380 /* Now bind it into the GTT if needed */
1381 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1385 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1389 ret = i915_gem_object_get_fence(obj);
1393 obj->fault_mappable = true;
1395 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1399 /* Finally, remap it using the new GTT offset */
1400 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1402 i915_gem_object_unpin(obj);
1404 mutex_unlock(&dev->struct_mutex);
1408 /* If this -EIO is due to a gpu hang, give the reset code a
1409 * chance to clean up the mess. Otherwise return the proper
1411 if (i915_terminally_wedged(&dev_priv->gpu_error))
1412 return VM_FAULT_SIGBUS;
1415 * EAGAIN means the gpu is hung and we'll wait for the error
1416 * handler to reset everything when re-faulting in
1417 * i915_mutex_lock_interruptible.
1424 * EBUSY is ok: this just means that another thread
1425 * already did the job.
1427 return VM_FAULT_NOPAGE;
1429 return VM_FAULT_OOM;
1431 return VM_FAULT_SIGBUS;
1433 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1434 return VM_FAULT_SIGBUS;
1439 * i915_gem_release_mmap - remove physical page mappings
1440 * @obj: obj in question
1442 * Preserve the reservation of the mmapping with the DRM core code, but
1443 * relinquish ownership of the pages back to the system.
1445 * It is vital that we remove the page mapping if we have mapped a tiled
1446 * object through the GTT and then lose the fence register due to
1447 * resource pressure. Similarly if the object has been moved out of the
1448 * aperture, than pages mapped into userspace must be revoked. Removing the
1449 * mapping will then trigger a page fault on the next user access, allowing
1450 * fixup by i915_gem_fault().
1453 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1455 if (!obj->fault_mappable)
1458 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1459 obj->fault_mappable = false;
1463 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1467 if (INTEL_INFO(dev)->gen >= 4 ||
1468 tiling_mode == I915_TILING_NONE)
1471 /* Previous chips need a power-of-two fence region when tiling */
1472 if (INTEL_INFO(dev)->gen == 3)
1473 gtt_size = 1024*1024;
1475 gtt_size = 512*1024;
1477 while (gtt_size < size)
1484 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1485 * @obj: object to check
1487 * Return the required GTT alignment for an object, taking into account
1488 * potential fence register mapping.
1491 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1492 int tiling_mode, bool fenced)
1495 * Minimum alignment is 4k (GTT page size), but might be greater
1496 * if a fence register is needed for the object.
1498 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1499 tiling_mode == I915_TILING_NONE)
1503 * Previous chips need to be aligned to the size of the smallest
1504 * fence register that can contain the object.
1506 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1509 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1511 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1514 if (drm_vma_node_has_offset(&obj->base.vma_node))
1517 dev_priv->mm.shrinker_no_lock_stealing = true;
1519 ret = drm_gem_create_mmap_offset(&obj->base);
1523 /* Badly fragmented mmap space? The only way we can recover
1524 * space is by destroying unwanted objects. We can't randomly release
1525 * mmap_offsets as userspace expects them to be persistent for the
1526 * lifetime of the objects. The closest we can is to release the
1527 * offsets on purgeable objects by truncating it and marking it purged,
1528 * which prevents userspace from ever using that object again.
1530 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1531 ret = drm_gem_create_mmap_offset(&obj->base);
1535 i915_gem_shrink_all(dev_priv);
1536 ret = drm_gem_create_mmap_offset(&obj->base);
1538 dev_priv->mm.shrinker_no_lock_stealing = false;
1543 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1545 drm_gem_free_mmap_offset(&obj->base);
1549 i915_gem_mmap_gtt(struct drm_file *file,
1550 struct drm_device *dev,
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_i915_gem_object *obj;
1558 ret = i915_mutex_lock_interruptible(dev);
1562 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1563 if (&obj->base == NULL) {
1568 if (obj->base.size > dev_priv->gtt.mappable_end) {
1573 if (obj->madv != I915_MADV_WILLNEED) {
1574 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1579 ret = i915_gem_object_create_mmap_offset(obj);
1583 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1586 drm_gem_object_unreference(&obj->base);
1588 mutex_unlock(&dev->struct_mutex);
1593 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1595 * @data: GTT mapping ioctl data
1596 * @file: GEM object info
1598 * Simply returns the fake offset to userspace so it can mmap it.
1599 * The mmap call will end up in drm_gem_mmap(), which will set things
1600 * up so we can get faults in the handler above.
1602 * The fault handler will take care of binding the object into the GTT
1603 * (since it may have been evicted to make room for something), allocating
1604 * a fence register, and mapping the appropriate aperture address into
1608 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1609 struct drm_file *file)
1611 struct drm_i915_gem_mmap_gtt *args = data;
1613 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1616 /* Immediately discard the backing storage */
1618 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1620 struct inode *inode;
1622 i915_gem_object_free_mmap_offset(obj);
1624 if (obj->base.filp == NULL)
1627 /* Our goal here is to return as much of the memory as
1628 * is possible back to the system as we are called from OOM.
1629 * To do this we must instruct the shmfs to drop all of its
1630 * backing pages, *now*.
1632 inode = file_inode(obj->base.filp);
1633 shmem_truncate_range(inode, 0, (loff_t)-1);
1635 obj->madv = __I915_MADV_PURGED;
1639 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1641 return obj->madv == I915_MADV_DONTNEED;
1645 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1647 struct sg_page_iter sg_iter;
1650 BUG_ON(obj->madv == __I915_MADV_PURGED);
1652 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1654 /* In the event of a disaster, abandon all caches and
1655 * hope for the best.
1657 WARN_ON(ret != -EIO);
1658 i915_gem_clflush_object(obj, true);
1659 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1662 if (i915_gem_object_needs_bit17_swizzle(obj))
1663 i915_gem_object_save_bit_17_swizzle(obj);
1665 if (obj->madv == I915_MADV_DONTNEED)
1668 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1669 struct page *page = sg_page_iter_page(&sg_iter);
1672 set_page_dirty(page);
1674 if (obj->madv == I915_MADV_WILLNEED)
1675 mark_page_accessed(page);
1677 page_cache_release(page);
1681 sg_free_table(obj->pages);
1686 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1688 const struct drm_i915_gem_object_ops *ops = obj->ops;
1690 if (obj->pages == NULL)
1693 if (obj->pages_pin_count)
1696 BUG_ON(i915_gem_obj_bound_any(obj));
1698 /* ->put_pages might need to allocate memory for the bit17 swizzle
1699 * array, hence protect them from being reaped by removing them from gtt
1701 list_del(&obj->global_list);
1703 ops->put_pages(obj);
1706 if (i915_gem_object_is_purgeable(obj))
1707 i915_gem_object_truncate(obj);
1713 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1714 bool purgeable_only)
1716 struct list_head still_bound_list;
1717 struct drm_i915_gem_object *obj, *next;
1720 list_for_each_entry_safe(obj, next,
1721 &dev_priv->mm.unbound_list,
1723 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1724 i915_gem_object_put_pages(obj) == 0) {
1725 count += obj->base.size >> PAGE_SHIFT;
1726 if (count >= target)
1732 * As we may completely rewrite the bound list whilst unbinding
1733 * (due to retiring requests) we have to strictly process only
1734 * one element of the list at the time, and recheck the list
1735 * on every iteration.
1737 INIT_LIST_HEAD(&still_bound_list);
1738 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1739 struct i915_vma *vma, *v;
1741 obj = list_first_entry(&dev_priv->mm.bound_list,
1742 typeof(*obj), global_list);
1743 list_move_tail(&obj->global_list, &still_bound_list);
1745 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1749 * Hold a reference whilst we unbind this object, as we may
1750 * end up waiting for and retiring requests. This might
1751 * release the final reference (held by the active list)
1752 * and result in the object being freed from under us.
1753 * in this object being freed.
1755 * Note 1: Shrinking the bound list is special since only active
1756 * (and hence bound objects) can contain such limbo objects, so
1757 * we don't need special tricks for shrinking the unbound list.
1758 * The only other place where we have to be careful with active
1759 * objects suddenly disappearing due to retiring requests is the
1762 * Note 2: Even though the bound list doesn't hold a reference
1763 * to the object we can safely grab one here: The final object
1764 * unreferencing and the bound_list are both protected by the
1765 * dev->struct_mutex and so we won't ever be able to observe an
1766 * object on the bound_list with a reference count equals 0.
1768 drm_gem_object_reference(&obj->base);
1770 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1771 if (i915_vma_unbind(vma))
1774 if (i915_gem_object_put_pages(obj) == 0)
1775 count += obj->base.size >> PAGE_SHIFT;
1777 drm_gem_object_unreference(&obj->base);
1779 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1785 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1787 return __i915_gem_shrink(dev_priv, target, true);
1791 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1793 struct drm_i915_gem_object *obj, *next;
1796 i915_gem_evict_everything(dev_priv->dev);
1798 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1800 if (obj->pages_pin_count == 0)
1801 freed += obj->base.size >> PAGE_SHIFT;
1802 i915_gem_object_put_pages(obj);
1808 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1810 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1812 struct address_space *mapping;
1813 struct sg_table *st;
1814 struct scatterlist *sg;
1815 struct sg_page_iter sg_iter;
1817 unsigned long last_pfn = 0; /* suppress gcc warning */
1820 /* Assert that the object is not currently in any GPU domain. As it
1821 * wasn't in the GTT, there shouldn't be any way it could have been in
1824 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1825 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1827 st = kmalloc(sizeof(*st), GFP_KERNEL);
1831 page_count = obj->base.size / PAGE_SIZE;
1832 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1837 /* Get the list of pages out of our struct file. They'll be pinned
1838 * at this point until we release them.
1840 * Fail silently without starting the shrinker
1842 mapping = file_inode(obj->base.filp)->i_mapping;
1843 gfp = mapping_gfp_mask(mapping);
1844 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1845 gfp &= ~(__GFP_IO | __GFP_WAIT);
1848 for (i = 0; i < page_count; i++) {
1849 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1851 i915_gem_purge(dev_priv, page_count);
1852 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1855 /* We've tried hard to allocate the memory by reaping
1856 * our own buffer, now let the real VM do its job and
1857 * go down in flames if truly OOM.
1859 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1860 gfp |= __GFP_IO | __GFP_WAIT;
1862 i915_gem_shrink_all(dev_priv);
1863 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1867 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1868 gfp &= ~(__GFP_IO | __GFP_WAIT);
1870 #ifdef CONFIG_SWIOTLB
1871 if (swiotlb_nr_tbl()) {
1873 sg_set_page(sg, page, PAGE_SIZE, 0);
1878 if (!i || page_to_pfn(page) != last_pfn + 1) {
1882 sg_set_page(sg, page, PAGE_SIZE, 0);
1884 sg->length += PAGE_SIZE;
1886 last_pfn = page_to_pfn(page);
1888 #ifdef CONFIG_SWIOTLB
1889 if (!swiotlb_nr_tbl())
1894 if (i915_gem_object_needs_bit17_swizzle(obj))
1895 i915_gem_object_do_bit_17_swizzle(obj);
1901 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1902 page_cache_release(sg_page_iter_page(&sg_iter));
1905 return PTR_ERR(page);
1908 /* Ensure that the associated pages are gathered from the backing storage
1909 * and pinned into our object. i915_gem_object_get_pages() may be called
1910 * multiple times before they are released by a single call to
1911 * i915_gem_object_put_pages() - once the pages are no longer referenced
1912 * either as a result of memory pressure (reaping pages under the shrinker)
1913 * or as the object is itself released.
1916 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1918 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1919 const struct drm_i915_gem_object_ops *ops = obj->ops;
1925 if (obj->madv != I915_MADV_WILLNEED) {
1926 DRM_ERROR("Attempting to obtain a purgeable object\n");
1930 BUG_ON(obj->pages_pin_count);
1932 ret = ops->get_pages(obj);
1936 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1941 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1942 struct intel_ring_buffer *ring)
1944 struct drm_device *dev = obj->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 u32 seqno = intel_ring_get_seqno(ring);
1948 BUG_ON(ring == NULL);
1949 if (obj->ring != ring && obj->last_write_seqno) {
1950 /* Keep the seqno relative to the current ring */
1951 obj->last_write_seqno = seqno;
1955 /* Add a reference if we're newly entering the active list. */
1957 drm_gem_object_reference(&obj->base);
1961 list_move_tail(&obj->ring_list, &ring->active_list);
1963 obj->last_read_seqno = seqno;
1965 if (obj->fenced_gpu_access) {
1966 obj->last_fenced_seqno = seqno;
1968 /* Bump MRU to take account of the delayed flush */
1969 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1970 struct drm_i915_fence_reg *reg;
1972 reg = &dev_priv->fence_regs[obj->fence_reg];
1973 list_move_tail(®->lru_list,
1974 &dev_priv->mm.fence_list);
1979 void i915_vma_move_to_active(struct i915_vma *vma,
1980 struct intel_ring_buffer *ring)
1982 list_move_tail(&vma->mm_list, &vma->vm->active_list);
1983 return i915_gem_object_move_to_active(vma->obj, ring);
1987 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1989 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1990 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1991 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1993 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1994 BUG_ON(!obj->active);
1996 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1998 list_del_init(&obj->ring_list);
2001 obj->last_read_seqno = 0;
2002 obj->last_write_seqno = 0;
2003 obj->base.write_domain = 0;
2005 obj->last_fenced_seqno = 0;
2006 obj->fenced_gpu_access = false;
2009 drm_gem_object_unreference(&obj->base);
2011 WARN_ON(i915_verify_lists(dev));
2015 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018 struct intel_ring_buffer *ring;
2021 /* Carefully retire all requests without writing to the rings */
2022 for_each_ring(ring, dev_priv, i) {
2023 ret = intel_ring_idle(ring);
2027 i915_gem_retire_requests(dev);
2029 /* Finally reset hw state */
2030 for_each_ring(ring, dev_priv, i) {
2031 intel_ring_init_seqno(ring, seqno);
2033 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2034 ring->sync_seqno[j] = 0;
2040 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2048 /* HWS page needs to be set less than what we
2049 * will inject to ring
2051 ret = i915_gem_init_seqno(dev, seqno - 1);
2055 /* Carefully set the last_seqno value so that wrap
2056 * detection still works
2058 dev_priv->next_seqno = seqno;
2059 dev_priv->last_seqno = seqno - 1;
2060 if (dev_priv->last_seqno == 0)
2061 dev_priv->last_seqno--;
2067 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2071 /* reserve 0 for non-seqno */
2072 if (dev_priv->next_seqno == 0) {
2073 int ret = i915_gem_init_seqno(dev, 0);
2077 dev_priv->next_seqno = 1;
2080 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2084 int __i915_add_request(struct intel_ring_buffer *ring,
2085 struct drm_file *file,
2086 struct drm_i915_gem_object *obj,
2089 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2090 struct drm_i915_gem_request *request;
2091 u32 request_ring_position, request_start;
2095 request_start = intel_ring_get_tail(ring);
2097 * Emit any outstanding flushes - execbuf can fail to emit the flush
2098 * after having emitted the batchbuffer command. Hence we need to fix
2099 * things up similar to emitting the lazy request. The difference here
2100 * is that the flush _must_ happen before the next request, no matter
2103 ret = intel_ring_flush_all_caches(ring);
2107 request = ring->preallocated_lazy_request;
2108 if (WARN_ON(request == NULL))
2111 /* Record the position of the start of the request so that
2112 * should we detect the updated seqno part-way through the
2113 * GPU processing the request, we never over-estimate the
2114 * position of the head.
2116 request_ring_position = intel_ring_get_tail(ring);
2118 ret = ring->add_request(ring);
2122 request->seqno = intel_ring_get_seqno(ring);
2123 request->ring = ring;
2124 request->head = request_start;
2125 request->tail = request_ring_position;
2127 /* Whilst this request exists, batch_obj will be on the
2128 * active_list, and so will hold the active reference. Only when this
2129 * request is retired will the the batch_obj be moved onto the
2130 * inactive_list and lose its active reference. Hence we do not need
2131 * to explicitly hold another reference here.
2133 request->batch_obj = obj;
2135 /* Hold a reference to the current context so that we can inspect
2136 * it later in case a hangcheck error event fires.
2138 request->ctx = ring->last_context;
2140 i915_gem_context_reference(request->ctx);
2142 request->emitted_jiffies = jiffies;
2143 was_empty = list_empty(&ring->request_list);
2144 list_add_tail(&request->list, &ring->request_list);
2145 request->file_priv = NULL;
2148 struct drm_i915_file_private *file_priv = file->driver_priv;
2150 spin_lock(&file_priv->mm.lock);
2151 request->file_priv = file_priv;
2152 list_add_tail(&request->client_list,
2153 &file_priv->mm.request_list);
2154 spin_unlock(&file_priv->mm.lock);
2157 trace_i915_gem_request_add(ring, request->seqno);
2158 ring->outstanding_lazy_seqno = 0;
2159 ring->preallocated_lazy_request = NULL;
2161 if (!dev_priv->ums.mm_suspended) {
2162 i915_queue_hangcheck(ring->dev);
2165 queue_delayed_work(dev_priv->wq,
2166 &dev_priv->mm.retire_work,
2167 round_jiffies_up_relative(HZ));
2168 intel_mark_busy(dev_priv->dev);
2173 *out_seqno = request->seqno;
2178 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2180 struct drm_i915_file_private *file_priv = request->file_priv;
2185 spin_lock(&file_priv->mm.lock);
2186 if (request->file_priv) {
2187 list_del(&request->client_list);
2188 request->file_priv = NULL;
2190 spin_unlock(&file_priv->mm.lock);
2193 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2194 struct i915_address_space *vm)
2196 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2197 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2203 static bool i915_head_inside_request(const u32 acthd_unmasked,
2204 const u32 request_start,
2205 const u32 request_end)
2207 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2209 if (request_start < request_end) {
2210 if (acthd >= request_start && acthd < request_end)
2212 } else if (request_start > request_end) {
2213 if (acthd >= request_start || acthd < request_end)
2220 static struct i915_address_space *
2221 request_to_vm(struct drm_i915_gem_request *request)
2223 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2224 struct i915_address_space *vm;
2226 vm = &dev_priv->gtt.base;
2231 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2232 const u32 acthd, bool *inside)
2234 /* There is a possibility that unmasked head address
2235 * pointing inside the ring, matches the batch_obj address range.
2236 * However this is extremely unlikely.
2238 if (request->batch_obj) {
2239 if (i915_head_inside_object(acthd, request->batch_obj,
2240 request_to_vm(request))) {
2246 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2254 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2256 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2261 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2262 DRM_ERROR("context hanging too fast, declaring banned!\n");
2269 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2270 struct drm_i915_gem_request *request,
2273 struct i915_ctx_hang_stats *hs = NULL;
2274 bool inside, guilty;
2275 unsigned long offset = 0;
2277 /* Innocent until proven guilty */
2280 if (request->batch_obj)
2281 offset = i915_gem_obj_offset(request->batch_obj,
2282 request_to_vm(request));
2284 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2285 i915_request_guilty(request, acthd, &inside)) {
2286 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2288 inside ? "inside" : "flushing",
2290 request->ctx ? request->ctx->id : 0,
2296 /* If contexts are disabled or this is the default context, use
2297 * file_priv->reset_state
2299 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2300 hs = &request->ctx->hang_stats;
2301 else if (request->file_priv)
2302 hs = &request->file_priv->hang_stats;
2306 hs->banned = i915_context_is_banned(hs);
2308 hs->guilty_ts = get_seconds();
2310 hs->batch_pending++;
2315 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2317 list_del(&request->list);
2318 i915_gem_request_remove_from_client(request);
2321 i915_gem_context_unreference(request->ctx);
2326 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2327 struct intel_ring_buffer *ring)
2329 u32 completed_seqno;
2332 acthd = intel_ring_get_active_head(ring);
2333 completed_seqno = ring->get_seqno(ring, false);
2335 while (!list_empty(&ring->request_list)) {
2336 struct drm_i915_gem_request *request;
2338 request = list_first_entry(&ring->request_list,
2339 struct drm_i915_gem_request,
2342 if (request->seqno > completed_seqno)
2343 i915_set_reset_status(ring, request, acthd);
2345 i915_gem_free_request(request);
2348 while (!list_empty(&ring->active_list)) {
2349 struct drm_i915_gem_object *obj;
2351 obj = list_first_entry(&ring->active_list,
2352 struct drm_i915_gem_object,
2355 i915_gem_object_move_to_inactive(obj);
2359 void i915_gem_restore_fences(struct drm_device *dev)
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2364 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2365 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2368 * Commit delayed tiling changes if we have an object still
2369 * attached to the fence, otherwise just clear the fence.
2372 i915_gem_object_update_fence(reg->obj, reg,
2373 reg->obj->tiling_mode);
2375 i915_gem_write_fence(dev, i, NULL);
2380 void i915_gem_reset(struct drm_device *dev)
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 struct intel_ring_buffer *ring;
2386 for_each_ring(ring, dev_priv, i)
2387 i915_gem_reset_ring_lists(dev_priv, ring);
2389 i915_gem_restore_fences(dev);
2393 * This function clears the request list as sequence numbers are passed.
2396 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2400 if (list_empty(&ring->request_list))
2403 WARN_ON(i915_verify_lists(ring->dev));
2405 seqno = ring->get_seqno(ring, true);
2407 while (!list_empty(&ring->request_list)) {
2408 struct drm_i915_gem_request *request;
2410 request = list_first_entry(&ring->request_list,
2411 struct drm_i915_gem_request,
2414 if (!i915_seqno_passed(seqno, request->seqno))
2417 trace_i915_gem_request_retire(ring, request->seqno);
2418 /* We know the GPU must have read the request to have
2419 * sent us the seqno + interrupt, so use the position
2420 * of tail of the request to update the last known position
2423 ring->last_retired_head = request->tail;
2425 i915_gem_free_request(request);
2428 /* Move any buffers on the active list that are no longer referenced
2429 * by the ringbuffer to the flushing/inactive lists as appropriate.
2431 while (!list_empty(&ring->active_list)) {
2432 struct drm_i915_gem_object *obj;
2434 obj = list_first_entry(&ring->active_list,
2435 struct drm_i915_gem_object,
2438 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2441 i915_gem_object_move_to_inactive(obj);
2444 if (unlikely(ring->trace_irq_seqno &&
2445 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2446 ring->irq_put(ring);
2447 ring->trace_irq_seqno = 0;
2450 WARN_ON(i915_verify_lists(ring->dev));
2454 i915_gem_retire_requests(struct drm_device *dev)
2456 drm_i915_private_t *dev_priv = dev->dev_private;
2457 struct intel_ring_buffer *ring;
2460 for_each_ring(ring, dev_priv, i)
2461 i915_gem_retire_requests_ring(ring);
2465 i915_gem_retire_work_handler(struct work_struct *work)
2467 drm_i915_private_t *dev_priv;
2468 struct drm_device *dev;
2469 struct intel_ring_buffer *ring;
2473 dev_priv = container_of(work, drm_i915_private_t,
2474 mm.retire_work.work);
2475 dev = dev_priv->dev;
2477 /* Come back later if the device is busy... */
2478 if (!mutex_trylock(&dev->struct_mutex)) {
2479 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2480 round_jiffies_up_relative(HZ));
2484 i915_gem_retire_requests(dev);
2486 /* Send a periodic flush down the ring so we don't hold onto GEM
2487 * objects indefinitely.
2490 for_each_ring(ring, dev_priv, i) {
2491 if (ring->gpu_caches_dirty)
2492 i915_add_request(ring, NULL);
2494 idle &= list_empty(&ring->request_list);
2497 if (!dev_priv->ums.mm_suspended && !idle)
2498 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2499 round_jiffies_up_relative(HZ));
2501 intel_mark_idle(dev);
2503 mutex_unlock(&dev->struct_mutex);
2507 * Ensures that an object will eventually get non-busy by flushing any required
2508 * write domains, emitting any outstanding lazy request and retiring and
2509 * completed requests.
2512 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2517 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2521 i915_gem_retire_requests_ring(obj->ring);
2528 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2529 * @DRM_IOCTL_ARGS: standard ioctl arguments
2531 * Returns 0 if successful, else an error is returned with the remaining time in
2532 * the timeout parameter.
2533 * -ETIME: object is still busy after timeout
2534 * -ERESTARTSYS: signal interrupted the wait
2535 * -ENONENT: object doesn't exist
2536 * Also possible, but rare:
2537 * -EAGAIN: GPU wedged
2539 * -ENODEV: Internal IRQ fail
2540 * -E?: The add request failed
2542 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2543 * non-zero timeout parameter the wait ioctl will wait for the given number of
2544 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2545 * without holding struct_mutex the object may become re-busied before this
2546 * function completes. A similar but shorter * race condition exists in the busy
2550 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2552 drm_i915_private_t *dev_priv = dev->dev_private;
2553 struct drm_i915_gem_wait *args = data;
2554 struct drm_i915_gem_object *obj;
2555 struct intel_ring_buffer *ring = NULL;
2556 struct timespec timeout_stack, *timeout = NULL;
2557 unsigned reset_counter;
2561 if (args->timeout_ns >= 0) {
2562 timeout_stack = ns_to_timespec(args->timeout_ns);
2563 timeout = &timeout_stack;
2566 ret = i915_mutex_lock_interruptible(dev);
2570 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2571 if (&obj->base == NULL) {
2572 mutex_unlock(&dev->struct_mutex);
2576 /* Need to make sure the object gets inactive eventually. */
2577 ret = i915_gem_object_flush_active(obj);
2582 seqno = obj->last_read_seqno;
2589 /* Do this after OLR check to make sure we make forward progress polling
2590 * on this IOCTL with a 0 timeout (like busy ioctl)
2592 if (!args->timeout_ns) {
2597 drm_gem_object_unreference(&obj->base);
2598 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2599 mutex_unlock(&dev->struct_mutex);
2601 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2603 args->timeout_ns = timespec_to_ns(timeout);
2607 drm_gem_object_unreference(&obj->base);
2608 mutex_unlock(&dev->struct_mutex);
2613 * i915_gem_object_sync - sync an object to a ring.
2615 * @obj: object which may be in use on another ring.
2616 * @to: ring we wish to use the object on. May be NULL.
2618 * This code is meant to abstract object synchronization with the GPU.
2619 * Calling with NULL implies synchronizing the object with the CPU
2620 * rather than a particular GPU ring.
2622 * Returns 0 if successful, else propagates up the lower layer error.
2625 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2626 struct intel_ring_buffer *to)
2628 struct intel_ring_buffer *from = obj->ring;
2632 if (from == NULL || to == from)
2635 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2636 return i915_gem_object_wait_rendering(obj, false);
2638 idx = intel_ring_sync_index(from, to);
2640 seqno = obj->last_read_seqno;
2641 if (seqno <= from->sync_seqno[idx])
2644 ret = i915_gem_check_olr(obj->ring, seqno);
2648 trace_i915_gem_ring_sync_to(from, to, seqno);
2649 ret = to->sync_to(to, from, seqno);
2651 /* We use last_read_seqno because sync_to()
2652 * might have just caused seqno wrap under
2655 from->sync_seqno[idx] = obj->last_read_seqno;
2660 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2662 u32 old_write_domain, old_read_domains;
2664 /* Force a pagefault for domain tracking on next user access */
2665 i915_gem_release_mmap(obj);
2667 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2670 /* Wait for any direct GTT access to complete */
2673 old_read_domains = obj->base.read_domains;
2674 old_write_domain = obj->base.write_domain;
2676 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2677 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2679 trace_i915_gem_object_change_domain(obj,
2684 int i915_vma_unbind(struct i915_vma *vma)
2686 struct drm_i915_gem_object *obj = vma->obj;
2687 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2690 /* For now we only ever use 1 vma per object */
2691 WARN_ON(!list_is_singular(&obj->vma_list));
2693 if (list_empty(&vma->vma_link))
2696 if (!drm_mm_node_allocated(&vma->node)) {
2697 i915_gem_vma_destroy(vma);
2705 BUG_ON(obj->pages == NULL);
2707 ret = i915_gem_object_finish_gpu(obj);
2710 /* Continue on if we fail due to EIO, the GPU is hung so we
2711 * should be safe and we need to cleanup or else we might
2712 * cause memory corruption through use-after-free.
2715 i915_gem_object_finish_gtt(obj);
2717 /* release the fence reg _after_ flushing */
2718 ret = i915_gem_object_put_fence(obj);
2722 trace_i915_vma_unbind(vma);
2724 if (obj->has_global_gtt_mapping)
2725 i915_gem_gtt_unbind_object(obj);
2726 if (obj->has_aliasing_ppgtt_mapping) {
2727 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2728 obj->has_aliasing_ppgtt_mapping = 0;
2730 i915_gem_gtt_finish_object(obj);
2731 i915_gem_object_unpin_pages(obj);
2733 list_del(&vma->mm_list);
2734 /* Avoid an unnecessary call to unbind on rebind. */
2735 if (i915_is_ggtt(vma->vm))
2736 obj->map_and_fenceable = true;
2738 drm_mm_remove_node(&vma->node);
2740 i915_gem_vma_destroy(vma);
2742 /* Since the unbound list is global, only move to that list if
2743 * no more VMAs exist. */
2744 if (list_empty(&obj->vma_list))
2745 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2751 * Unbinds an object from the global GTT aperture.
2754 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2756 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2757 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2759 if (!i915_gem_obj_ggtt_bound(obj))
2765 BUG_ON(obj->pages == NULL);
2767 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2770 int i915_gpu_idle(struct drm_device *dev)
2772 drm_i915_private_t *dev_priv = dev->dev_private;
2773 struct intel_ring_buffer *ring;
2776 /* Flush everything onto the inactive list. */
2777 for_each_ring(ring, dev_priv, i) {
2778 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2782 ret = intel_ring_idle(ring);
2790 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2791 struct drm_i915_gem_object *obj)
2793 drm_i915_private_t *dev_priv = dev->dev_private;
2795 int fence_pitch_shift;
2797 if (INTEL_INFO(dev)->gen >= 6) {
2798 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2799 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2801 fence_reg = FENCE_REG_965_0;
2802 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2805 fence_reg += reg * 8;
2807 /* To w/a incoherency with non-atomic 64-bit register updates,
2808 * we split the 64-bit update into two 32-bit writes. In order
2809 * for a partial fence not to be evaluated between writes, we
2810 * precede the update with write to turn off the fence register,
2811 * and only enable the fence as the last step.
2813 * For extra levels of paranoia, we make sure each step lands
2814 * before applying the next step.
2816 I915_WRITE(fence_reg, 0);
2817 POSTING_READ(fence_reg);
2820 u32 size = i915_gem_obj_ggtt_size(obj);
2823 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2825 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2826 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2827 if (obj->tiling_mode == I915_TILING_Y)
2828 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2829 val |= I965_FENCE_REG_VALID;
2831 I915_WRITE(fence_reg + 4, val >> 32);
2832 POSTING_READ(fence_reg + 4);
2834 I915_WRITE(fence_reg + 0, val);
2835 POSTING_READ(fence_reg);
2837 I915_WRITE(fence_reg + 4, 0);
2838 POSTING_READ(fence_reg + 4);
2842 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2843 struct drm_i915_gem_object *obj)
2845 drm_i915_private_t *dev_priv = dev->dev_private;
2849 u32 size = i915_gem_obj_ggtt_size(obj);
2853 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2854 (size & -size) != size ||
2855 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2856 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2857 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2859 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2864 /* Note: pitch better be a power of two tile widths */
2865 pitch_val = obj->stride / tile_width;
2866 pitch_val = ffs(pitch_val) - 1;
2868 val = i915_gem_obj_ggtt_offset(obj);
2869 if (obj->tiling_mode == I915_TILING_Y)
2870 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2871 val |= I915_FENCE_SIZE_BITS(size);
2872 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2873 val |= I830_FENCE_REG_VALID;
2878 reg = FENCE_REG_830_0 + reg * 4;
2880 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2882 I915_WRITE(reg, val);
2886 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2887 struct drm_i915_gem_object *obj)
2889 drm_i915_private_t *dev_priv = dev->dev_private;
2893 u32 size = i915_gem_obj_ggtt_size(obj);
2896 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2897 (size & -size) != size ||
2898 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2899 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2900 i915_gem_obj_ggtt_offset(obj), size);
2902 pitch_val = obj->stride / 128;
2903 pitch_val = ffs(pitch_val) - 1;
2905 val = i915_gem_obj_ggtt_offset(obj);
2906 if (obj->tiling_mode == I915_TILING_Y)
2907 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2908 val |= I830_FENCE_SIZE_BITS(size);
2909 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2910 val |= I830_FENCE_REG_VALID;
2914 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2915 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2918 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2920 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2923 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2924 struct drm_i915_gem_object *obj)
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2928 /* Ensure that all CPU reads are completed before installing a fence
2929 * and all writes before removing the fence.
2931 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2934 WARN(obj && (!obj->stride || !obj->tiling_mode),
2935 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2936 obj->stride, obj->tiling_mode);
2938 switch (INTEL_INFO(dev)->gen) {
2942 case 4: i965_write_fence_reg(dev, reg, obj); break;
2943 case 3: i915_write_fence_reg(dev, reg, obj); break;
2944 case 2: i830_write_fence_reg(dev, reg, obj); break;
2948 /* And similarly be paranoid that no direct access to this region
2949 * is reordered to before the fence is installed.
2951 if (i915_gem_object_needs_mb(obj))
2955 static inline int fence_number(struct drm_i915_private *dev_priv,
2956 struct drm_i915_fence_reg *fence)
2958 return fence - dev_priv->fence_regs;
2961 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2962 struct drm_i915_fence_reg *fence,
2965 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2966 int reg = fence_number(dev_priv, fence);
2968 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2971 obj->fence_reg = reg;
2973 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2975 obj->fence_reg = I915_FENCE_REG_NONE;
2977 list_del_init(&fence->lru_list);
2979 obj->fence_dirty = false;
2983 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2985 if (obj->last_fenced_seqno) {
2986 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2990 obj->last_fenced_seqno = 0;
2993 obj->fenced_gpu_access = false;
2998 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3000 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3001 struct drm_i915_fence_reg *fence;
3004 ret = i915_gem_object_wait_fence(obj);
3008 if (obj->fence_reg == I915_FENCE_REG_NONE)
3011 fence = &dev_priv->fence_regs[obj->fence_reg];
3013 i915_gem_object_fence_lost(obj);
3014 i915_gem_object_update_fence(obj, fence, false);
3019 static struct drm_i915_fence_reg *
3020 i915_find_fence_reg(struct drm_device *dev)
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 struct drm_i915_fence_reg *reg, *avail;
3026 /* First try to find a free reg */
3028 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3029 reg = &dev_priv->fence_regs[i];
3033 if (!reg->pin_count)
3040 /* None available, try to steal one or wait for a user to finish */
3041 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3052 * i915_gem_object_get_fence - set up fencing for an object
3053 * @obj: object to map through a fence reg
3055 * When mapping objects through the GTT, userspace wants to be able to write
3056 * to them without having to worry about swizzling if the object is tiled.
3057 * This function walks the fence regs looking for a free one for @obj,
3058 * stealing one if it can't find any.
3060 * It then sets up the reg based on the object's properties: address, pitch
3061 * and tiling format.
3063 * For an untiled surface, this removes any existing fence.
3066 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3068 struct drm_device *dev = obj->base.dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 bool enable = obj->tiling_mode != I915_TILING_NONE;
3071 struct drm_i915_fence_reg *reg;
3074 /* Have we updated the tiling parameters upon the object and so
3075 * will need to serialise the write to the associated fence register?
3077 if (obj->fence_dirty) {
3078 ret = i915_gem_object_wait_fence(obj);
3083 /* Just update our place in the LRU if our fence is getting reused. */
3084 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3085 reg = &dev_priv->fence_regs[obj->fence_reg];
3086 if (!obj->fence_dirty) {
3087 list_move_tail(®->lru_list,
3088 &dev_priv->mm.fence_list);
3091 } else if (enable) {
3092 reg = i915_find_fence_reg(dev);
3097 struct drm_i915_gem_object *old = reg->obj;
3099 ret = i915_gem_object_wait_fence(old);
3103 i915_gem_object_fence_lost(old);
3108 i915_gem_object_update_fence(obj, reg, enable);
3113 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3114 struct drm_mm_node *gtt_space,
3115 unsigned long cache_level)
3117 struct drm_mm_node *other;
3119 /* On non-LLC machines we have to be careful when putting differing
3120 * types of snoopable memory together to avoid the prefetcher
3121 * crossing memory domains and dying.
3126 if (!drm_mm_node_allocated(gtt_space))
3129 if (list_empty(>t_space->node_list))
3132 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3133 if (other->allocated && !other->hole_follows && other->color != cache_level)
3136 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3137 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3143 static void i915_gem_verify_gtt(struct drm_device *dev)
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 struct drm_i915_gem_object *obj;
3150 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3151 if (obj->gtt_space == NULL) {
3152 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3157 if (obj->cache_level != obj->gtt_space->color) {
3158 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3159 i915_gem_obj_ggtt_offset(obj),
3160 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3162 obj->gtt_space->color);
3167 if (!i915_gem_valid_gtt_space(dev,
3169 obj->cache_level)) {
3170 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3171 i915_gem_obj_ggtt_offset(obj),
3172 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3184 * Finds free space in the GTT aperture and binds the object there.
3187 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3188 struct i915_address_space *vm,
3190 bool map_and_fenceable,
3193 struct drm_device *dev = obj->base.dev;
3194 drm_i915_private_t *dev_priv = dev->dev_private;
3195 u32 size, fence_size, fence_alignment, unfenced_alignment;
3197 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3198 struct i915_vma *vma;
3201 fence_size = i915_gem_get_gtt_size(dev,
3204 fence_alignment = i915_gem_get_gtt_alignment(dev,
3206 obj->tiling_mode, true);
3207 unfenced_alignment =
3208 i915_gem_get_gtt_alignment(dev,
3210 obj->tiling_mode, false);
3213 alignment = map_and_fenceable ? fence_alignment :
3215 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3216 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3220 size = map_and_fenceable ? fence_size : obj->base.size;
3222 /* If the object is bigger than the entire aperture, reject it early
3223 * before evicting everything in a vain attempt to find space.
3225 if (obj->base.size > gtt_max) {
3226 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3228 map_and_fenceable ? "mappable" : "total",
3233 ret = i915_gem_object_get_pages(obj);
3237 i915_gem_object_pin_pages(obj);
3239 BUG_ON(!i915_is_ggtt(vm));
3241 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3247 /* For now we only ever use 1 vma per object */
3248 WARN_ON(!list_is_singular(&obj->vma_list));
3251 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3253 obj->cache_level, 0, gtt_max,
3254 DRM_MM_SEARCH_DEFAULT);
3256 ret = i915_gem_evict_something(dev, vm, size, alignment,
3265 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3266 obj->cache_level))) {
3268 goto err_remove_node;
3271 ret = i915_gem_gtt_prepare_object(obj);
3273 goto err_remove_node;
3275 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3276 list_add_tail(&vma->mm_list, &vm->inactive_list);
3278 if (i915_is_ggtt(vm)) {
3279 bool mappable, fenceable;
3281 fenceable = (vma->node.size == fence_size &&
3282 (vma->node.start & (fence_alignment - 1)) == 0);
3284 mappable = (vma->node.start + obj->base.size <=
3285 dev_priv->gtt.mappable_end);
3287 obj->map_and_fenceable = mappable && fenceable;
3290 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3292 trace_i915_vma_bind(vma, map_and_fenceable);
3293 i915_gem_verify_gtt(dev);
3297 drm_mm_remove_node(&vma->node);
3299 i915_gem_vma_destroy(vma);
3301 i915_gem_object_unpin_pages(obj);
3306 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3309 /* If we don't have a page list set up, then we're not pinned
3310 * to GPU, and we can ignore the cache flush because it'll happen
3311 * again at bind time.
3313 if (obj->pages == NULL)
3317 * Stolen memory is always coherent with the GPU as it is explicitly
3318 * marked as wc by the system, or the system is cache-coherent.
3323 /* If the GPU is snooping the contents of the CPU cache,
3324 * we do not need to manually clear the CPU cache lines. However,
3325 * the caches are only snooped when the render cache is
3326 * flushed/invalidated. As we always have to emit invalidations
3327 * and flushes when moving into and out of the RENDER domain, correct
3328 * snooping behaviour occurs naturally as the result of our domain
3331 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3334 trace_i915_gem_object_clflush(obj);
3335 drm_clflush_sg(obj->pages);
3340 /** Flushes the GTT write domain for the object if it's dirty. */
3342 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3344 uint32_t old_write_domain;
3346 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3349 /* No actual flushing is required for the GTT write domain. Writes
3350 * to it immediately go to main memory as far as we know, so there's
3351 * no chipset flush. It also doesn't land in render cache.
3353 * However, we do have to enforce the order so that all writes through
3354 * the GTT land before any writes to the device, such as updates to
3359 old_write_domain = obj->base.write_domain;
3360 obj->base.write_domain = 0;
3362 trace_i915_gem_object_change_domain(obj,
3363 obj->base.read_domains,
3367 /** Flushes the CPU write domain for the object if it's dirty. */
3369 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3372 uint32_t old_write_domain;
3374 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3377 if (i915_gem_clflush_object(obj, force))
3378 i915_gem_chipset_flush(obj->base.dev);
3380 old_write_domain = obj->base.write_domain;
3381 obj->base.write_domain = 0;
3383 trace_i915_gem_object_change_domain(obj,
3384 obj->base.read_domains,
3389 * Moves a single object to the GTT read, and possibly write domain.
3391 * This function returns when the move is complete, including waiting on
3395 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3397 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3398 uint32_t old_write_domain, old_read_domains;
3401 /* Not valid to be called on unbound objects. */
3402 if (!i915_gem_obj_bound_any(obj))
3405 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3408 ret = i915_gem_object_wait_rendering(obj, !write);
3412 i915_gem_object_flush_cpu_write_domain(obj, false);
3414 /* Serialise direct access to this object with the barriers for
3415 * coherent writes from the GPU, by effectively invalidating the
3416 * GTT domain upon first access.
3418 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3421 old_write_domain = obj->base.write_domain;
3422 old_read_domains = obj->base.read_domains;
3424 /* It should now be out of any other write domains, and we can update
3425 * the domain values for our changes.
3427 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3428 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3430 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3431 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3435 trace_i915_gem_object_change_domain(obj,
3439 /* And bump the LRU for this access */
3440 if (i915_gem_object_is_inactive(obj)) {
3441 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3443 list_move_tail(&vma->mm_list,
3444 &dev_priv->gtt.base.inactive_list);
3451 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3452 enum i915_cache_level cache_level)
3454 struct drm_device *dev = obj->base.dev;
3455 drm_i915_private_t *dev_priv = dev->dev_private;
3456 struct i915_vma *vma;
3459 if (obj->cache_level == cache_level)
3462 if (obj->pin_count) {
3463 DRM_DEBUG("can not change the cache level of pinned objects\n");
3467 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3468 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3469 ret = i915_vma_unbind(vma);
3477 if (i915_gem_obj_bound_any(obj)) {
3478 ret = i915_gem_object_finish_gpu(obj);
3482 i915_gem_object_finish_gtt(obj);
3484 /* Before SandyBridge, you could not use tiling or fence
3485 * registers with snooped memory, so relinquish any fences
3486 * currently pointing to our region in the aperture.
3488 if (INTEL_INFO(dev)->gen < 6) {
3489 ret = i915_gem_object_put_fence(obj);
3494 if (obj->has_global_gtt_mapping)
3495 i915_gem_gtt_bind_object(obj, cache_level);
3496 if (obj->has_aliasing_ppgtt_mapping)
3497 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3501 list_for_each_entry(vma, &obj->vma_list, vma_link)
3502 vma->node.color = cache_level;
3503 obj->cache_level = cache_level;
3505 if (cpu_write_needs_clflush(obj)) {
3506 u32 old_read_domains, old_write_domain;
3508 /* If we're coming from LLC cached, then we haven't
3509 * actually been tracking whether the data is in the
3510 * CPU cache or not, since we only allow one bit set
3511 * in obj->write_domain and have been skipping the clflushes.
3512 * Just set it to the CPU cache for now.
3514 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3516 old_read_domains = obj->base.read_domains;
3517 old_write_domain = obj->base.write_domain;
3519 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3520 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3522 trace_i915_gem_object_change_domain(obj,
3527 i915_gem_verify_gtt(dev);
3531 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3532 struct drm_file *file)
3534 struct drm_i915_gem_caching *args = data;
3535 struct drm_i915_gem_object *obj;
3538 ret = i915_mutex_lock_interruptible(dev);
3542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3543 if (&obj->base == NULL) {
3548 switch (obj->cache_level) {
3549 case I915_CACHE_LLC:
3550 case I915_CACHE_L3_LLC:
3551 args->caching = I915_CACHING_CACHED;
3555 args->caching = I915_CACHING_DISPLAY;
3559 args->caching = I915_CACHING_NONE;
3563 drm_gem_object_unreference(&obj->base);
3565 mutex_unlock(&dev->struct_mutex);
3569 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3570 struct drm_file *file)
3572 struct drm_i915_gem_caching *args = data;
3573 struct drm_i915_gem_object *obj;
3574 enum i915_cache_level level;
3577 switch (args->caching) {
3578 case I915_CACHING_NONE:
3579 level = I915_CACHE_NONE;
3581 case I915_CACHING_CACHED:
3582 level = I915_CACHE_LLC;
3584 case I915_CACHING_DISPLAY:
3585 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3591 ret = i915_mutex_lock_interruptible(dev);
3595 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3596 if (&obj->base == NULL) {
3601 ret = i915_gem_object_set_cache_level(obj, level);
3603 drm_gem_object_unreference(&obj->base);
3605 mutex_unlock(&dev->struct_mutex);
3609 static bool is_pin_display(struct drm_i915_gem_object *obj)
3611 /* There are 3 sources that pin objects:
3612 * 1. The display engine (scanouts, sprites, cursors);
3613 * 2. Reservations for execbuffer;
3616 * We can ignore reservations as we hold the struct_mutex and
3617 * are only called outside of the reservation path. The user
3618 * can only increment pin_count once, and so if after
3619 * subtracting the potential reference by the user, any pin_count
3620 * remains, it must be due to another use by the display engine.
3622 return obj->pin_count - !!obj->user_pin_count;
3626 * Prepare buffer for display plane (scanout, cursors, etc).
3627 * Can be called from an uninterruptible phase (modesetting) and allows
3628 * any flushes to be pipelined (for pageflips).
3631 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3633 struct intel_ring_buffer *pipelined)
3635 u32 old_read_domains, old_write_domain;
3638 if (pipelined != obj->ring) {
3639 ret = i915_gem_object_sync(obj, pipelined);
3644 /* Mark the pin_display early so that we account for the
3645 * display coherency whilst setting up the cache domains.
3647 obj->pin_display = true;
3649 /* The display engine is not coherent with the LLC cache on gen6. As
3650 * a result, we make sure that the pinning that is about to occur is
3651 * done with uncached PTEs. This is lowest common denominator for all
3654 * However for gen6+, we could do better by using the GFDT bit instead
3655 * of uncaching, which would allow us to flush all the LLC-cached data
3656 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3658 ret = i915_gem_object_set_cache_level(obj,
3659 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3661 goto err_unpin_display;
3663 /* As the user may map the buffer once pinned in the display plane
3664 * (e.g. libkms for the bootup splash), we have to ensure that we
3665 * always use map_and_fenceable for all scanout buffers.
3667 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3669 goto err_unpin_display;
3671 i915_gem_object_flush_cpu_write_domain(obj, true);
3673 old_write_domain = obj->base.write_domain;
3674 old_read_domains = obj->base.read_domains;
3676 /* It should now be out of any other write domains, and we can update
3677 * the domain values for our changes.
3679 obj->base.write_domain = 0;
3680 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3682 trace_i915_gem_object_change_domain(obj,
3689 obj->pin_display = is_pin_display(obj);
3694 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3696 i915_gem_object_unpin(obj);
3697 obj->pin_display = is_pin_display(obj);
3701 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3705 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3708 ret = i915_gem_object_wait_rendering(obj, false);
3712 /* Ensure that we invalidate the GPU's caches and TLBs. */
3713 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3718 * Moves a single object to the CPU read, and possibly write domain.
3720 * This function returns when the move is complete, including waiting on
3724 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3726 uint32_t old_write_domain, old_read_domains;
3729 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3732 ret = i915_gem_object_wait_rendering(obj, !write);
3736 i915_gem_object_flush_gtt_write_domain(obj);
3738 old_write_domain = obj->base.write_domain;
3739 old_read_domains = obj->base.read_domains;
3741 /* Flush the CPU cache if it's still invalid. */
3742 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3743 i915_gem_clflush_object(obj, false);
3745 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3748 /* It should now be out of any other write domains, and we can update
3749 * the domain values for our changes.
3751 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3753 /* If we're writing through the CPU, then the GPU read domains will
3754 * need to be invalidated at next use.
3757 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3758 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3761 trace_i915_gem_object_change_domain(obj,
3768 /* Throttle our rendering by waiting until the ring has completed our requests
3769 * emitted over 20 msec ago.
3771 * Note that if we were to use the current jiffies each time around the loop,
3772 * we wouldn't escape the function with any frames outstanding if the time to
3773 * render a frame was over 20ms.
3775 * This should get us reasonable parallelism between CPU and GPU but also
3776 * relatively low latency when blocking on a particular request to finish.
3779 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 struct drm_i915_file_private *file_priv = file->driver_priv;
3783 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3784 struct drm_i915_gem_request *request;
3785 struct intel_ring_buffer *ring = NULL;
3786 unsigned reset_counter;
3790 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3794 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3798 spin_lock(&file_priv->mm.lock);
3799 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3800 if (time_after_eq(request->emitted_jiffies, recent_enough))
3803 ring = request->ring;
3804 seqno = request->seqno;
3806 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3807 spin_unlock(&file_priv->mm.lock);
3812 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3814 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3820 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3821 struct i915_address_space *vm,
3823 bool map_and_fenceable,
3826 struct i915_vma *vma;
3829 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3832 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3834 vma = i915_gem_obj_to_vma(obj, vm);
3838 vma->node.start & (alignment - 1)) ||
3839 (map_and_fenceable && !obj->map_and_fenceable)) {
3840 WARN(obj->pin_count,
3841 "bo is already pinned with incorrect alignment:"
3842 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3843 " obj->map_and_fenceable=%d\n",
3844 i915_gem_obj_offset(obj, vm), alignment,
3846 obj->map_and_fenceable);
3847 ret = i915_vma_unbind(vma);
3853 if (!i915_gem_obj_bound(obj, vm)) {
3854 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3856 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3862 if (!dev_priv->mm.aliasing_ppgtt)
3863 i915_gem_gtt_bind_object(obj, obj->cache_level);
3866 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3867 i915_gem_gtt_bind_object(obj, obj->cache_level);
3870 obj->pin_mappable |= map_and_fenceable;
3876 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3878 BUG_ON(obj->pin_count == 0);
3879 BUG_ON(!i915_gem_obj_bound_any(obj));
3881 if (--obj->pin_count == 0)
3882 obj->pin_mappable = false;
3886 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3887 struct drm_file *file)
3889 struct drm_i915_gem_pin *args = data;
3890 struct drm_i915_gem_object *obj;
3893 ret = i915_mutex_lock_interruptible(dev);
3897 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3898 if (&obj->base == NULL) {
3903 if (obj->madv != I915_MADV_WILLNEED) {
3904 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3909 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3910 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3916 if (obj->user_pin_count == 0) {
3917 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3922 obj->user_pin_count++;
3923 obj->pin_filp = file;
3925 args->offset = i915_gem_obj_ggtt_offset(obj);
3927 drm_gem_object_unreference(&obj->base);
3929 mutex_unlock(&dev->struct_mutex);
3934 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3935 struct drm_file *file)
3937 struct drm_i915_gem_pin *args = data;
3938 struct drm_i915_gem_object *obj;
3941 ret = i915_mutex_lock_interruptible(dev);
3945 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3946 if (&obj->base == NULL) {
3951 if (obj->pin_filp != file) {
3952 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3957 obj->user_pin_count--;
3958 if (obj->user_pin_count == 0) {
3959 obj->pin_filp = NULL;
3960 i915_gem_object_unpin(obj);
3964 drm_gem_object_unreference(&obj->base);
3966 mutex_unlock(&dev->struct_mutex);
3971 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3972 struct drm_file *file)
3974 struct drm_i915_gem_busy *args = data;
3975 struct drm_i915_gem_object *obj;
3978 ret = i915_mutex_lock_interruptible(dev);
3982 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3983 if (&obj->base == NULL) {
3988 /* Count all active objects as busy, even if they are currently not used
3989 * by the gpu. Users of this interface expect objects to eventually
3990 * become non-busy without any further actions, therefore emit any
3991 * necessary flushes here.
3993 ret = i915_gem_object_flush_active(obj);
3995 args->busy = obj->active;
3997 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3998 args->busy |= intel_ring_flag(obj->ring) << 16;
4001 drm_gem_object_unreference(&obj->base);
4003 mutex_unlock(&dev->struct_mutex);
4008 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4009 struct drm_file *file_priv)
4011 return i915_gem_ring_throttle(dev, file_priv);
4015 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4016 struct drm_file *file_priv)
4018 struct drm_i915_gem_madvise *args = data;
4019 struct drm_i915_gem_object *obj;
4022 switch (args->madv) {
4023 case I915_MADV_DONTNEED:
4024 case I915_MADV_WILLNEED:
4030 ret = i915_mutex_lock_interruptible(dev);
4034 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4035 if (&obj->base == NULL) {
4040 if (obj->pin_count) {
4045 if (obj->madv != __I915_MADV_PURGED)
4046 obj->madv = args->madv;
4048 /* if the object is no longer attached, discard its backing storage */
4049 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4050 i915_gem_object_truncate(obj);
4052 args->retained = obj->madv != __I915_MADV_PURGED;
4055 drm_gem_object_unreference(&obj->base);
4057 mutex_unlock(&dev->struct_mutex);
4061 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4062 const struct drm_i915_gem_object_ops *ops)
4064 INIT_LIST_HEAD(&obj->global_list);
4065 INIT_LIST_HEAD(&obj->ring_list);
4066 INIT_LIST_HEAD(&obj->obj_exec_link);
4067 INIT_LIST_HEAD(&obj->vma_list);
4071 obj->fence_reg = I915_FENCE_REG_NONE;
4072 obj->madv = I915_MADV_WILLNEED;
4073 /* Avoid an unnecessary call to unbind on the first bind. */
4074 obj->map_and_fenceable = true;
4076 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4079 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4080 .get_pages = i915_gem_object_get_pages_gtt,
4081 .put_pages = i915_gem_object_put_pages_gtt,
4084 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4087 struct drm_i915_gem_object *obj;
4088 struct address_space *mapping;
4091 obj = i915_gem_object_alloc(dev);
4095 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4096 i915_gem_object_free(obj);
4100 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4101 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4102 /* 965gm cannot relocate objects above 4GiB. */
4103 mask &= ~__GFP_HIGHMEM;
4104 mask |= __GFP_DMA32;
4107 mapping = file_inode(obj->base.filp)->i_mapping;
4108 mapping_set_gfp_mask(mapping, mask);
4110 i915_gem_object_init(obj, &i915_gem_object_ops);
4112 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4113 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4116 /* On some devices, we can have the GPU use the LLC (the CPU
4117 * cache) for about a 10% performance improvement
4118 * compared to uncached. Graphics requests other than
4119 * display scanout are coherent with the CPU in
4120 * accessing this cache. This means in this mode we
4121 * don't need to clflush on the CPU side, and on the
4122 * GPU side we only need to flush internal caches to
4123 * get data visible to the CPU.
4125 * However, we maintain the display planes as UC, and so
4126 * need to rebind when first used as such.
4128 obj->cache_level = I915_CACHE_LLC;
4130 obj->cache_level = I915_CACHE_NONE;
4132 trace_i915_gem_object_create(obj);
4137 int i915_gem_init_object(struct drm_gem_object *obj)
4144 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4146 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4147 struct drm_device *dev = obj->base.dev;
4148 drm_i915_private_t *dev_priv = dev->dev_private;
4149 struct i915_vma *vma, *next;
4151 trace_i915_gem_object_destroy(obj);
4154 i915_gem_detach_phys_object(dev, obj);
4157 /* NB: 0 or 1 elements */
4158 WARN_ON(!list_empty(&obj->vma_list) &&
4159 !list_is_singular(&obj->vma_list));
4160 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4161 int ret = i915_vma_unbind(vma);
4162 if (WARN_ON(ret == -ERESTARTSYS)) {
4163 bool was_interruptible;
4165 was_interruptible = dev_priv->mm.interruptible;
4166 dev_priv->mm.interruptible = false;
4168 WARN_ON(i915_vma_unbind(vma));
4170 dev_priv->mm.interruptible = was_interruptible;
4174 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4175 * before progressing. */
4177 i915_gem_object_unpin_pages(obj);
4179 if (WARN_ON(obj->pages_pin_count))
4180 obj->pages_pin_count = 0;
4181 i915_gem_object_put_pages(obj);
4182 i915_gem_object_free_mmap_offset(obj);
4183 i915_gem_object_release_stolen(obj);
4187 if (obj->base.import_attach)
4188 drm_prime_gem_destroy(&obj->base, NULL);
4190 drm_gem_object_release(&obj->base);
4191 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4194 i915_gem_object_free(obj);
4197 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4198 struct i915_address_space *vm)
4200 struct i915_vma *vma;
4201 list_for_each_entry(vma, &obj->vma_list, vma_link)
4208 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4209 struct i915_address_space *vm)
4211 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4213 return ERR_PTR(-ENOMEM);
4215 INIT_LIST_HEAD(&vma->vma_link);
4216 INIT_LIST_HEAD(&vma->mm_list);
4217 INIT_LIST_HEAD(&vma->exec_list);
4221 /* Keep GGTT vmas first to make debug easier */
4222 if (i915_is_ggtt(vm))
4223 list_add(&vma->vma_link, &obj->vma_list);
4225 list_add_tail(&vma->vma_link, &obj->vma_list);
4231 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4232 struct i915_address_space *vm)
4234 struct i915_vma *vma;
4236 vma = i915_gem_obj_to_vma(obj, vm);
4238 vma = __i915_gem_vma_create(obj, vm);
4243 void i915_gem_vma_destroy(struct i915_vma *vma)
4245 WARN_ON(vma->node.allocated);
4247 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4248 if (!list_empty(&vma->exec_list))
4251 list_del(&vma->vma_link);
4257 i915_gem_idle(struct drm_device *dev)
4259 drm_i915_private_t *dev_priv = dev->dev_private;
4262 if (dev_priv->ums.mm_suspended)
4265 ret = i915_gpu_idle(dev);
4269 i915_gem_retire_requests(dev);
4271 /* Under UMS, be paranoid and evict. */
4272 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4273 i915_gem_evict_everything(dev);
4275 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4277 i915_kernel_lost_context(dev);
4278 i915_gem_cleanup_ringbuffer(dev);
4280 /* Cancel the retire work handler, which should be idle now. */
4281 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4286 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4288 struct drm_device *dev = ring->dev;
4289 drm_i915_private_t *dev_priv = dev->dev_private;
4290 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4291 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4294 if (!HAS_L3_DPF(dev) || !remap_info)
4297 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4302 * Note: We do not worry about the concurrent register cacheline hang
4303 * here because no other code should access these registers other than
4304 * at initialization time.
4306 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4307 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4308 intel_ring_emit(ring, reg_base + i);
4309 intel_ring_emit(ring, remap_info[i/4]);
4312 intel_ring_advance(ring);
4317 void i915_gem_init_swizzling(struct drm_device *dev)
4319 drm_i915_private_t *dev_priv = dev->dev_private;
4321 if (INTEL_INFO(dev)->gen < 5 ||
4322 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4325 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4326 DISP_TILE_SURFACE_SWIZZLING);
4331 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4333 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4334 else if (IS_GEN7(dev))
4335 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4341 intel_enable_blt(struct drm_device *dev)
4346 /* The blitter was dysfunctional on early prototypes */
4347 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4348 DRM_INFO("BLT not supported on this pre-production hardware;"
4349 " graphics performance will be degraded.\n");
4356 static int i915_gem_init_rings(struct drm_device *dev)
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4361 ret = intel_init_render_ring_buffer(dev);
4366 ret = intel_init_bsd_ring_buffer(dev);
4368 goto cleanup_render_ring;
4371 if (intel_enable_blt(dev)) {
4372 ret = intel_init_blt_ring_buffer(dev);
4374 goto cleanup_bsd_ring;
4377 if (HAS_VEBOX(dev)) {
4378 ret = intel_init_vebox_ring_buffer(dev);
4380 goto cleanup_blt_ring;
4384 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4386 goto cleanup_vebox_ring;
4391 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4393 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4395 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4396 cleanup_render_ring:
4397 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4403 i915_gem_init_hw(struct drm_device *dev)
4405 drm_i915_private_t *dev_priv = dev->dev_private;
4408 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4411 if (dev_priv->ellc_size)
4412 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4414 if (IS_HSW_GT3(dev))
4415 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
4417 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
4419 if (HAS_PCH_NOP(dev)) {
4420 u32 temp = I915_READ(GEN7_MSG_CTL);
4421 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4422 I915_WRITE(GEN7_MSG_CTL, temp);
4425 i915_gem_init_swizzling(dev);
4427 ret = i915_gem_init_rings(dev);
4431 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4432 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4435 * XXX: There was some w/a described somewhere suggesting loading
4436 * contexts before PPGTT.
4438 i915_gem_context_init(dev);
4439 if (dev_priv->mm.aliasing_ppgtt) {
4440 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4442 i915_gem_cleanup_aliasing_ppgtt(dev);
4443 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4450 int i915_gem_init(struct drm_device *dev)
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4455 mutex_lock(&dev->struct_mutex);
4457 if (IS_VALLEYVIEW(dev)) {
4458 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4459 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4460 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4461 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4464 i915_gem_init_global_gtt(dev);
4466 ret = i915_gem_init_hw(dev);
4467 mutex_unlock(&dev->struct_mutex);
4469 i915_gem_cleanup_aliasing_ppgtt(dev);
4473 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4474 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4475 dev_priv->dri1.allow_batchbuffer = 1;
4480 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4482 drm_i915_private_t *dev_priv = dev->dev_private;
4483 struct intel_ring_buffer *ring;
4486 for_each_ring(ring, dev_priv, i)
4487 intel_cleanup_ring_buffer(ring);
4491 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4492 struct drm_file *file_priv)
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4497 if (drm_core_check_feature(dev, DRIVER_MODESET))
4500 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4501 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4502 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4505 mutex_lock(&dev->struct_mutex);
4506 dev_priv->ums.mm_suspended = 0;
4508 ret = i915_gem_init_hw(dev);
4510 mutex_unlock(&dev->struct_mutex);
4514 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4515 mutex_unlock(&dev->struct_mutex);
4517 ret = drm_irq_install(dev);
4519 goto cleanup_ringbuffer;
4524 mutex_lock(&dev->struct_mutex);
4525 i915_gem_cleanup_ringbuffer(dev);
4526 dev_priv->ums.mm_suspended = 1;
4527 mutex_unlock(&dev->struct_mutex);
4533 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4534 struct drm_file *file_priv)
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4539 if (drm_core_check_feature(dev, DRIVER_MODESET))
4542 drm_irq_uninstall(dev);
4544 mutex_lock(&dev->struct_mutex);
4545 ret = i915_gem_idle(dev);
4547 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4548 * We need to replace this with a semaphore, or something.
4549 * And not confound ums.mm_suspended!
4552 dev_priv->ums.mm_suspended = 1;
4553 mutex_unlock(&dev->struct_mutex);
4559 i915_gem_lastclose(struct drm_device *dev)
4563 if (drm_core_check_feature(dev, DRIVER_MODESET))
4566 mutex_lock(&dev->struct_mutex);
4567 ret = i915_gem_idle(dev);
4569 DRM_ERROR("failed to idle hardware: %d\n", ret);
4570 mutex_unlock(&dev->struct_mutex);
4574 init_ring_lists(struct intel_ring_buffer *ring)
4576 INIT_LIST_HEAD(&ring->active_list);
4577 INIT_LIST_HEAD(&ring->request_list);
4580 static void i915_init_vm(struct drm_i915_private *dev_priv,
4581 struct i915_address_space *vm)
4583 vm->dev = dev_priv->dev;
4584 INIT_LIST_HEAD(&vm->active_list);
4585 INIT_LIST_HEAD(&vm->inactive_list);
4586 INIT_LIST_HEAD(&vm->global_link);
4587 list_add(&vm->global_link, &dev_priv->vm_list);
4591 i915_gem_load(struct drm_device *dev)
4593 drm_i915_private_t *dev_priv = dev->dev_private;
4597 kmem_cache_create("i915_gem_object",
4598 sizeof(struct drm_i915_gem_object), 0,
4602 INIT_LIST_HEAD(&dev_priv->vm_list);
4603 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4605 INIT_LIST_HEAD(&dev_priv->context_list);
4606 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4607 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4608 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4609 for (i = 0; i < I915_NUM_RINGS; i++)
4610 init_ring_lists(&dev_priv->ring[i]);
4611 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4612 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4613 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4614 i915_gem_retire_work_handler);
4615 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4617 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4619 I915_WRITE(MI_ARB_STATE,
4620 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4623 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4625 /* Old X drivers will take 0-2 for front, back, depth buffers */
4626 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4627 dev_priv->fence_reg_start = 3;
4629 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4630 dev_priv->num_fence_regs = 32;
4631 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4632 dev_priv->num_fence_regs = 16;
4634 dev_priv->num_fence_regs = 8;
4636 /* Initialize fence registers to zero */
4637 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4638 i915_gem_restore_fences(dev);
4640 i915_gem_detect_bit_6_swizzle(dev);
4641 init_waitqueue_head(&dev_priv->pending_flip_queue);
4643 dev_priv->mm.interruptible = true;
4645 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4646 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4647 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4648 register_shrinker(&dev_priv->mm.inactive_shrinker);
4652 * Create a physically contiguous memory object for this object
4653 * e.g. for cursor + overlay regs
4655 static int i915_gem_init_phys_object(struct drm_device *dev,
4656 int id, int size, int align)
4658 drm_i915_private_t *dev_priv = dev->dev_private;
4659 struct drm_i915_gem_phys_object *phys_obj;
4662 if (dev_priv->mm.phys_objs[id - 1] || !size)
4665 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4671 phys_obj->handle = drm_pci_alloc(dev, size, align);
4672 if (!phys_obj->handle) {
4677 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4680 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4688 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4690 drm_i915_private_t *dev_priv = dev->dev_private;
4691 struct drm_i915_gem_phys_object *phys_obj;
4693 if (!dev_priv->mm.phys_objs[id - 1])
4696 phys_obj = dev_priv->mm.phys_objs[id - 1];
4697 if (phys_obj->cur_obj) {
4698 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4702 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4704 drm_pci_free(dev, phys_obj->handle);
4706 dev_priv->mm.phys_objs[id - 1] = NULL;
4709 void i915_gem_free_all_phys_object(struct drm_device *dev)
4713 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4714 i915_gem_free_phys_object(dev, i);
4717 void i915_gem_detach_phys_object(struct drm_device *dev,
4718 struct drm_i915_gem_object *obj)
4720 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4727 vaddr = obj->phys_obj->handle->vaddr;
4729 page_count = obj->base.size / PAGE_SIZE;
4730 for (i = 0; i < page_count; i++) {
4731 struct page *page = shmem_read_mapping_page(mapping, i);
4732 if (!IS_ERR(page)) {
4733 char *dst = kmap_atomic(page);
4734 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4737 drm_clflush_pages(&page, 1);
4739 set_page_dirty(page);
4740 mark_page_accessed(page);
4741 page_cache_release(page);
4744 i915_gem_chipset_flush(dev);
4746 obj->phys_obj->cur_obj = NULL;
4747 obj->phys_obj = NULL;
4751 i915_gem_attach_phys_object(struct drm_device *dev,
4752 struct drm_i915_gem_object *obj,
4756 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4757 drm_i915_private_t *dev_priv = dev->dev_private;
4762 if (id > I915_MAX_PHYS_OBJECT)
4765 if (obj->phys_obj) {
4766 if (obj->phys_obj->id == id)
4768 i915_gem_detach_phys_object(dev, obj);
4771 /* create a new object */
4772 if (!dev_priv->mm.phys_objs[id - 1]) {
4773 ret = i915_gem_init_phys_object(dev, id,
4774 obj->base.size, align);
4776 DRM_ERROR("failed to init phys object %d size: %zu\n",
4777 id, obj->base.size);
4782 /* bind to the object */
4783 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4784 obj->phys_obj->cur_obj = obj;
4786 page_count = obj->base.size / PAGE_SIZE;
4788 for (i = 0; i < page_count; i++) {
4792 page = shmem_read_mapping_page(mapping, i);
4794 return PTR_ERR(page);
4796 src = kmap_atomic(page);
4797 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4798 memcpy(dst, src, PAGE_SIZE);
4801 mark_page_accessed(page);
4802 page_cache_release(page);
4809 i915_gem_phys_pwrite(struct drm_device *dev,
4810 struct drm_i915_gem_object *obj,
4811 struct drm_i915_gem_pwrite *args,
4812 struct drm_file *file_priv)
4814 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4815 char __user *user_data = to_user_ptr(args->data_ptr);
4817 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4818 unsigned long unwritten;
4820 /* The physical object once assigned is fixed for the lifetime
4821 * of the obj, so we can safely drop the lock and continue
4824 mutex_unlock(&dev->struct_mutex);
4825 unwritten = copy_from_user(vaddr, user_data, args->size);
4826 mutex_lock(&dev->struct_mutex);
4831 i915_gem_chipset_flush(dev);
4835 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4837 struct drm_i915_file_private *file_priv = file->driver_priv;
4839 /* Clean up our request list when the client is going away, so that
4840 * later retire_requests won't dereference our soon-to-be-gone
4843 spin_lock(&file_priv->mm.lock);
4844 while (!list_empty(&file_priv->mm.request_list)) {
4845 struct drm_i915_gem_request *request;
4847 request = list_first_entry(&file_priv->mm.request_list,
4848 struct drm_i915_gem_request,
4850 list_del(&request->client_list);
4851 request->file_priv = NULL;
4853 spin_unlock(&file_priv->mm.lock);
4856 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4858 if (!mutex_is_locked(mutex))
4861 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4862 return mutex->owner == task;
4864 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4869 static unsigned long
4870 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4872 struct drm_i915_private *dev_priv =
4873 container_of(shrinker,
4874 struct drm_i915_private,
4875 mm.inactive_shrinker);
4876 struct drm_device *dev = dev_priv->dev;
4877 struct drm_i915_gem_object *obj;
4879 unsigned long count;
4881 if (!mutex_trylock(&dev->struct_mutex)) {
4882 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4885 if (dev_priv->mm.shrinker_no_lock_stealing)
4892 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4893 if (obj->pages_pin_count == 0)
4894 count += obj->base.size >> PAGE_SHIFT;
4896 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4900 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4901 count += obj->base.size >> PAGE_SHIFT;
4905 mutex_unlock(&dev->struct_mutex);
4909 /* All the new VM stuff */
4910 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4911 struct i915_address_space *vm)
4913 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4914 struct i915_vma *vma;
4916 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4917 vm = &dev_priv->gtt.base;
4919 BUG_ON(list_empty(&o->vma_list));
4920 list_for_each_entry(vma, &o->vma_list, vma_link) {
4922 return vma->node.start;
4928 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4929 struct i915_address_space *vm)
4931 struct i915_vma *vma;
4933 list_for_each_entry(vma, &o->vma_list, vma_link)
4934 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4940 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4942 struct i915_vma *vma;
4944 list_for_each_entry(vma, &o->vma_list, vma_link)
4945 if (drm_mm_node_allocated(&vma->node))
4951 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4952 struct i915_address_space *vm)
4954 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4955 struct i915_vma *vma;
4957 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4958 vm = &dev_priv->gtt.base;
4960 BUG_ON(list_empty(&o->vma_list));
4962 list_for_each_entry(vma, &o->vma_list, vma_link)
4964 return vma->node.size;
4969 static unsigned long
4970 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
4972 struct drm_i915_private *dev_priv =
4973 container_of(shrinker,
4974 struct drm_i915_private,
4975 mm.inactive_shrinker);
4976 struct drm_device *dev = dev_priv->dev;
4977 int nr_to_scan = sc->nr_to_scan;
4978 unsigned long freed;
4981 if (!mutex_trylock(&dev->struct_mutex)) {
4982 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4985 if (dev_priv->mm.shrinker_no_lock_stealing)
4991 freed = i915_gem_purge(dev_priv, nr_to_scan);
4992 if (freed < nr_to_scan)
4993 freed += __i915_gem_shrink(dev_priv, nr_to_scan,
4995 if (freed < nr_to_scan)
4996 freed += i915_gem_shrink_all(dev_priv);
4999 mutex_unlock(&dev->struct_mutex);
5003 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5005 struct i915_vma *vma;
5007 if (WARN_ON(list_empty(&obj->vma_list)))
5010 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5011 if (WARN_ON(vma->vm != obj_to_ggtt(obj)))