2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
40 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
50 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
56 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
62 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
64 return obj_priv->gtt_space &&
66 obj_priv->pin_count == 0;
69 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
72 drm_i915_private_t *dev_priv = dev->dev_private;
75 (start & (PAGE_SIZE - 1)) != 0 ||
76 (end & (PAGE_SIZE - 1)) != 0) {
80 drm_mm_init(&dev_priv->mm.gtt_space, start,
83 dev->gtt_total = (uint32_t) (end - start);
89 i915_gem_init_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file_priv)
92 struct drm_i915_gem_init *args = data;
95 mutex_lock(&dev->struct_mutex);
96 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
97 mutex_unlock(&dev->struct_mutex);
103 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
104 struct drm_file *file_priv)
106 struct drm_i915_gem_get_aperture *args = data;
108 if (!(dev->driver->driver_features & DRIVER_GEM))
111 args->aper_size = dev->gtt_total;
112 args->aper_available_size = (args->aper_size -
113 atomic_read(&dev->pin_memory));
120 * Creates a new mm object and returns a handle to it.
123 i915_gem_create_ioctl(struct drm_device *dev, void *data,
124 struct drm_file *file_priv)
126 struct drm_i915_gem_create *args = data;
127 struct drm_gem_object *obj;
131 args->size = roundup(args->size, PAGE_SIZE);
133 /* Allocate the new object */
134 obj = i915_gem_alloc_object(dev, args->size);
138 ret = drm_gem_handle_create(file_priv, obj, &handle);
140 drm_gem_object_unreference_unlocked(obj);
144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj);
147 args->handle = handle;
152 fast_shmem_read(struct page **pages,
153 loff_t page_base, int page_offset,
160 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
163 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
164 kunmap_atomic(vaddr, KM_USER0);
172 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
174 drm_i915_private_t *dev_priv = obj->dev->dev_private;
175 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
177 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
178 obj_priv->tiling_mode != I915_TILING_NONE;
182 slow_shmem_copy(struct page *dst_page,
184 struct page *src_page,
188 char *dst_vaddr, *src_vaddr;
190 dst_vaddr = kmap(dst_page);
191 src_vaddr = kmap(src_page);
193 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
200 slow_shmem_bit17_copy(struct page *gpu_page,
202 struct page *cpu_page,
207 char *gpu_vaddr, *cpu_vaddr;
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
219 gpu_vaddr = kmap(gpu_page);
220 cpu_vaddr = kmap(cpu_page);
222 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
223 * XORing with the other bits (A9 for Y, A9 and A10 for X)
226 int cacheline_end = ALIGN(gpu_offset + 1, 64);
227 int this_length = min(cacheline_end - gpu_offset, length);
228 int swizzled_gpu_offset = gpu_offset ^ 64;
231 memcpy(cpu_vaddr + cpu_offset,
232 gpu_vaddr + swizzled_gpu_offset,
235 memcpy(gpu_vaddr + swizzled_gpu_offset,
236 cpu_vaddr + cpu_offset,
239 cpu_offset += this_length;
240 gpu_offset += this_length;
241 length -= this_length;
249 * This is the fast shmem pread path, which attempts to copy_from_user directly
250 * from the backing pages of the object to the user's address space. On a
251 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
254 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
255 struct drm_i915_gem_pread *args,
256 struct drm_file *file_priv)
258 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
260 loff_t offset, page_base;
261 char __user *user_data;
262 int page_offset, page_length;
265 user_data = (char __user *) (uintptr_t) args->data_ptr;
268 mutex_lock(&dev->struct_mutex);
270 ret = i915_gem_object_get_pages(obj, 0);
274 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
279 obj_priv = to_intel_bo(obj);
280 offset = args->offset;
283 /* Operation in this page
285 * page_base = page offset within aperture
286 * page_offset = offset within page
287 * page_length = bytes to copy for this page
289 page_base = (offset & ~(PAGE_SIZE-1));
290 page_offset = offset & (PAGE_SIZE-1);
291 page_length = remain;
292 if ((page_offset + remain) > PAGE_SIZE)
293 page_length = PAGE_SIZE - page_offset;
295 ret = fast_shmem_read(obj_priv->pages,
296 page_base, page_offset,
297 user_data, page_length);
301 remain -= page_length;
302 user_data += page_length;
303 offset += page_length;
307 i915_gem_object_put_pages(obj);
309 mutex_unlock(&dev->struct_mutex);
315 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
319 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
321 /* If we've insufficient memory to map in the pages, attempt
322 * to make some space by throwing out some old buffers.
324 if (ret == -ENOMEM) {
325 struct drm_device *dev = obj->dev;
327 ret = i915_gem_evict_something(dev, obj->size,
328 i915_gem_get_gtt_alignment(obj));
332 ret = i915_gem_object_get_pages(obj, 0);
339 * This is the fallback shmem pread path, which allocates temporary storage
340 * in kernel space to copy_to_user into outside of the struct_mutex, so we
341 * can copy out of the object's backing pages while holding the struct mutex
342 * and not take page faults.
345 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
346 struct drm_i915_gem_pread *args,
347 struct drm_file *file_priv)
349 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
350 struct mm_struct *mm = current->mm;
351 struct page **user_pages;
353 loff_t offset, pinned_pages, i;
354 loff_t first_data_page, last_data_page, num_pages;
355 int shmem_page_index, shmem_page_offset;
356 int data_page_index, data_page_offset;
359 uint64_t data_ptr = args->data_ptr;
360 int do_bit17_swizzling;
364 /* Pin the user pages containing the data. We can't fault while
365 * holding the struct mutex, yet we want to hold it while
366 * dereferencing the user data.
368 first_data_page = data_ptr / PAGE_SIZE;
369 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
370 num_pages = last_data_page - first_data_page + 1;
372 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
373 if (user_pages == NULL)
376 down_read(&mm->mmap_sem);
377 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
378 num_pages, 1, 0, user_pages, NULL);
379 up_read(&mm->mmap_sem);
380 if (pinned_pages < num_pages) {
382 goto fail_put_user_pages;
385 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
387 mutex_lock(&dev->struct_mutex);
389 ret = i915_gem_object_get_pages_or_evict(obj);
393 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
398 obj_priv = to_intel_bo(obj);
399 offset = args->offset;
402 /* Operation in this page
404 * shmem_page_index = page number within shmem file
405 * shmem_page_offset = offset within page in shmem file
406 * data_page_index = page number in get_user_pages return
407 * data_page_offset = offset with data_page_index page.
408 * page_length = bytes to copy for this page
410 shmem_page_index = offset / PAGE_SIZE;
411 shmem_page_offset = offset & ~PAGE_MASK;
412 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
413 data_page_offset = data_ptr & ~PAGE_MASK;
415 page_length = remain;
416 if ((shmem_page_offset + page_length) > PAGE_SIZE)
417 page_length = PAGE_SIZE - shmem_page_offset;
418 if ((data_page_offset + page_length) > PAGE_SIZE)
419 page_length = PAGE_SIZE - data_page_offset;
421 if (do_bit17_swizzling) {
422 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
424 user_pages[data_page_index],
429 slow_shmem_copy(user_pages[data_page_index],
431 obj_priv->pages[shmem_page_index],
436 remain -= page_length;
437 data_ptr += page_length;
438 offset += page_length;
442 i915_gem_object_put_pages(obj);
444 mutex_unlock(&dev->struct_mutex);
446 for (i = 0; i < pinned_pages; i++) {
447 SetPageDirty(user_pages[i]);
448 page_cache_release(user_pages[i]);
450 drm_free_large(user_pages);
456 * Reads data from the object referenced by handle.
458 * On error, the contents of *data are undefined.
461 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
462 struct drm_file *file_priv)
464 struct drm_i915_gem_pread *args = data;
465 struct drm_gem_object *obj;
466 struct drm_i915_gem_object *obj_priv;
469 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
472 obj_priv = to_intel_bo(obj);
474 /* Bounds check source.
476 * XXX: This could use review for overflow issues...
478 if (args->offset > obj->size || args->size > obj->size ||
479 args->offset + args->size > obj->size) {
480 drm_gem_object_unreference_unlocked(obj);
484 if (i915_gem_object_needs_bit17_swizzle(obj)) {
485 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
487 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
489 ret = i915_gem_shmem_pread_slow(dev, obj, args,
493 drm_gem_object_unreference_unlocked(obj);
498 /* This is the fast write path which cannot handle
499 * page faults in the source data
503 fast_user_write(struct io_mapping *mapping,
504 loff_t page_base, int page_offset,
505 char __user *user_data,
509 unsigned long unwritten;
511 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
512 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
514 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
520 /* Here's the write path which can sleep for
525 slow_kernel_write(struct io_mapping *mapping,
526 loff_t gtt_base, int gtt_offset,
527 struct page *user_page, int user_offset,
530 char __iomem *dst_vaddr;
533 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
534 src_vaddr = kmap(user_page);
536 memcpy_toio(dst_vaddr + gtt_offset,
537 src_vaddr + user_offset,
541 io_mapping_unmap(dst_vaddr);
545 fast_shmem_write(struct page **pages,
546 loff_t page_base, int page_offset,
551 unsigned long unwritten;
553 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
556 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
557 kunmap_atomic(vaddr, KM_USER0);
565 * This is the fast pwrite path, where we copy the data directly from the
566 * user into the GTT, uncached.
569 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
570 struct drm_i915_gem_pwrite *args,
571 struct drm_file *file_priv)
573 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
574 drm_i915_private_t *dev_priv = dev->dev_private;
576 loff_t offset, page_base;
577 char __user *user_data;
578 int page_offset, page_length;
581 user_data = (char __user *) (uintptr_t) args->data_ptr;
583 if (!access_ok(VERIFY_READ, user_data, remain))
587 mutex_lock(&dev->struct_mutex);
588 ret = i915_gem_object_pin(obj, 0);
590 mutex_unlock(&dev->struct_mutex);
593 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
597 obj_priv = to_intel_bo(obj);
598 offset = obj_priv->gtt_offset + args->offset;
601 /* Operation in this page
603 * page_base = page offset within aperture
604 * page_offset = offset within page
605 * page_length = bytes to copy for this page
607 page_base = (offset & ~(PAGE_SIZE-1));
608 page_offset = offset & (PAGE_SIZE-1);
609 page_length = remain;
610 if ((page_offset + remain) > PAGE_SIZE)
611 page_length = PAGE_SIZE - page_offset;
613 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
614 page_offset, user_data, page_length);
616 /* If we get a fault while copying data, then (presumably) our
617 * source page isn't available. Return the error and we'll
618 * retry in the slow path.
623 remain -= page_length;
624 user_data += page_length;
625 offset += page_length;
629 i915_gem_object_unpin(obj);
630 mutex_unlock(&dev->struct_mutex);
636 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
637 * the memory and maps it using kmap_atomic for copying.
639 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
640 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
643 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
644 struct drm_i915_gem_pwrite *args,
645 struct drm_file *file_priv)
647 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
648 drm_i915_private_t *dev_priv = dev->dev_private;
650 loff_t gtt_page_base, offset;
651 loff_t first_data_page, last_data_page, num_pages;
652 loff_t pinned_pages, i;
653 struct page **user_pages;
654 struct mm_struct *mm = current->mm;
655 int gtt_page_offset, data_page_offset, data_page_index, page_length;
657 uint64_t data_ptr = args->data_ptr;
661 /* Pin the user pages containing the data. We can't fault while
662 * holding the struct mutex, and all of the pwrite implementations
663 * want to hold it while dereferencing the user data.
665 first_data_page = data_ptr / PAGE_SIZE;
666 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
667 num_pages = last_data_page - first_data_page + 1;
669 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
670 if (user_pages == NULL)
673 down_read(&mm->mmap_sem);
674 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
675 num_pages, 0, 0, user_pages, NULL);
676 up_read(&mm->mmap_sem);
677 if (pinned_pages < num_pages) {
679 goto out_unpin_pages;
682 mutex_lock(&dev->struct_mutex);
683 ret = i915_gem_object_pin(obj, 0);
687 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
689 goto out_unpin_object;
691 obj_priv = to_intel_bo(obj);
692 offset = obj_priv->gtt_offset + args->offset;
695 /* Operation in this page
697 * gtt_page_base = page offset within aperture
698 * gtt_page_offset = offset within page in aperture
699 * data_page_index = page number in get_user_pages return
700 * data_page_offset = offset with data_page_index page.
701 * page_length = bytes to copy for this page
703 gtt_page_base = offset & PAGE_MASK;
704 gtt_page_offset = offset & ~PAGE_MASK;
705 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
706 data_page_offset = data_ptr & ~PAGE_MASK;
708 page_length = remain;
709 if ((gtt_page_offset + page_length) > PAGE_SIZE)
710 page_length = PAGE_SIZE - gtt_page_offset;
711 if ((data_page_offset + page_length) > PAGE_SIZE)
712 page_length = PAGE_SIZE - data_page_offset;
714 slow_kernel_write(dev_priv->mm.gtt_mapping,
715 gtt_page_base, gtt_page_offset,
716 user_pages[data_page_index],
720 remain -= page_length;
721 offset += page_length;
722 data_ptr += page_length;
726 i915_gem_object_unpin(obj);
728 mutex_unlock(&dev->struct_mutex);
730 for (i = 0; i < pinned_pages; i++)
731 page_cache_release(user_pages[i]);
732 drm_free_large(user_pages);
738 * This is the fast shmem pwrite path, which attempts to directly
739 * copy_from_user into the kmapped pages backing the object.
742 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
743 struct drm_i915_gem_pwrite *args,
744 struct drm_file *file_priv)
746 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
748 loff_t offset, page_base;
749 char __user *user_data;
750 int page_offset, page_length;
753 user_data = (char __user *) (uintptr_t) args->data_ptr;
756 mutex_lock(&dev->struct_mutex);
758 ret = i915_gem_object_get_pages(obj, 0);
762 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
766 obj_priv = to_intel_bo(obj);
767 offset = args->offset;
771 /* Operation in this page
773 * page_base = page offset within aperture
774 * page_offset = offset within page
775 * page_length = bytes to copy for this page
777 page_base = (offset & ~(PAGE_SIZE-1));
778 page_offset = offset & (PAGE_SIZE-1);
779 page_length = remain;
780 if ((page_offset + remain) > PAGE_SIZE)
781 page_length = PAGE_SIZE - page_offset;
783 ret = fast_shmem_write(obj_priv->pages,
784 page_base, page_offset,
785 user_data, page_length);
789 remain -= page_length;
790 user_data += page_length;
791 offset += page_length;
795 i915_gem_object_put_pages(obj);
797 mutex_unlock(&dev->struct_mutex);
803 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
804 * the memory and maps it using kmap_atomic for copying.
806 * This avoids taking mmap_sem for faulting on the user's address while the
807 * struct_mutex is held.
810 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
811 struct drm_i915_gem_pwrite *args,
812 struct drm_file *file_priv)
814 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
815 struct mm_struct *mm = current->mm;
816 struct page **user_pages;
818 loff_t offset, pinned_pages, i;
819 loff_t first_data_page, last_data_page, num_pages;
820 int shmem_page_index, shmem_page_offset;
821 int data_page_index, data_page_offset;
824 uint64_t data_ptr = args->data_ptr;
825 int do_bit17_swizzling;
829 /* Pin the user pages containing the data. We can't fault while
830 * holding the struct mutex, and all of the pwrite implementations
831 * want to hold it while dereferencing the user data.
833 first_data_page = data_ptr / PAGE_SIZE;
834 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
835 num_pages = last_data_page - first_data_page + 1;
837 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
838 if (user_pages == NULL)
841 down_read(&mm->mmap_sem);
842 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
843 num_pages, 0, 0, user_pages, NULL);
844 up_read(&mm->mmap_sem);
845 if (pinned_pages < num_pages) {
847 goto fail_put_user_pages;
850 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
852 mutex_lock(&dev->struct_mutex);
854 ret = i915_gem_object_get_pages_or_evict(obj);
858 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
862 obj_priv = to_intel_bo(obj);
863 offset = args->offset;
867 /* Operation in this page
869 * shmem_page_index = page number within shmem file
870 * shmem_page_offset = offset within page in shmem file
871 * data_page_index = page number in get_user_pages return
872 * data_page_offset = offset with data_page_index page.
873 * page_length = bytes to copy for this page
875 shmem_page_index = offset / PAGE_SIZE;
876 shmem_page_offset = offset & ~PAGE_MASK;
877 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
878 data_page_offset = data_ptr & ~PAGE_MASK;
880 page_length = remain;
881 if ((shmem_page_offset + page_length) > PAGE_SIZE)
882 page_length = PAGE_SIZE - shmem_page_offset;
883 if ((data_page_offset + page_length) > PAGE_SIZE)
884 page_length = PAGE_SIZE - data_page_offset;
886 if (do_bit17_swizzling) {
887 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
889 user_pages[data_page_index],
894 slow_shmem_copy(obj_priv->pages[shmem_page_index],
896 user_pages[data_page_index],
901 remain -= page_length;
902 data_ptr += page_length;
903 offset += page_length;
907 i915_gem_object_put_pages(obj);
909 mutex_unlock(&dev->struct_mutex);
911 for (i = 0; i < pinned_pages; i++)
912 page_cache_release(user_pages[i]);
913 drm_free_large(user_pages);
919 * Writes data to the object referenced by handle.
921 * On error, the contents of the buffer that were to be modified are undefined.
924 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
925 struct drm_file *file_priv)
927 struct drm_i915_gem_pwrite *args = data;
928 struct drm_gem_object *obj;
929 struct drm_i915_gem_object *obj_priv;
932 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
935 obj_priv = to_intel_bo(obj);
937 /* Bounds check destination.
939 * XXX: This could use review for overflow issues...
941 if (args->offset > obj->size || args->size > obj->size ||
942 args->offset + args->size > obj->size) {
943 drm_gem_object_unreference_unlocked(obj);
947 /* We can only do the GTT pwrite on untiled buffers, as otherwise
948 * it would end up going through the fenced access, and we'll get
949 * different detiling behavior between reading and writing.
950 * pread/pwrite currently are reading and writing from the CPU
951 * perspective, requiring manual detiling by the client.
953 if (obj_priv->phys_obj)
954 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
955 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
956 dev->gtt_total != 0 &&
957 obj->write_domain != I915_GEM_DOMAIN_CPU) {
958 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
959 if (ret == -EFAULT) {
960 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
963 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
964 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
966 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
967 if (ret == -EFAULT) {
968 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
975 DRM_INFO("pwrite failed %d\n", ret);
978 drm_gem_object_unreference_unlocked(obj);
984 * Called when user space prepares to use an object with the CPU, either
985 * through the mmap ioctl's mapping or a GTT mapping.
988 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
989 struct drm_file *file_priv)
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 struct drm_i915_gem_set_domain *args = data;
993 struct drm_gem_object *obj;
994 struct drm_i915_gem_object *obj_priv;
995 uint32_t read_domains = args->read_domains;
996 uint32_t write_domain = args->write_domain;
999 if (!(dev->driver->driver_features & DRIVER_GEM))
1002 /* Only handle setting domains to types used by the CPU. */
1003 if (write_domain & I915_GEM_GPU_DOMAINS)
1006 if (read_domains & I915_GEM_GPU_DOMAINS)
1009 /* Having something in the write domain implies it's in the read
1010 * domain, and only that read domain. Enforce that in the request.
1012 if (write_domain != 0 && read_domains != write_domain)
1015 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1018 obj_priv = to_intel_bo(obj);
1020 mutex_lock(&dev->struct_mutex);
1022 intel_mark_busy(dev, obj);
1025 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1026 obj, obj->size, read_domains, write_domain);
1028 if (read_domains & I915_GEM_DOMAIN_GTT) {
1029 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1031 /* Update the LRU on the fence for the CPU access that's
1034 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1035 struct drm_i915_fence_reg *reg =
1036 &dev_priv->fence_regs[obj_priv->fence_reg];
1037 list_move_tail(®->lru_list,
1038 &dev_priv->mm.fence_list);
1041 /* Silently promote "you're not bound, there was nothing to do"
1042 * to success, since the client was just asking us to
1043 * make sure everything was done.
1048 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1052 /* Maintain LRU order of "inactive" objects */
1053 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1054 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1056 drm_gem_object_unreference(obj);
1057 mutex_unlock(&dev->struct_mutex);
1062 * Called when user space has done writes to this buffer
1065 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1066 struct drm_file *file_priv)
1068 struct drm_i915_gem_sw_finish *args = data;
1069 struct drm_gem_object *obj;
1070 struct drm_i915_gem_object *obj_priv;
1073 if (!(dev->driver->driver_features & DRIVER_GEM))
1076 mutex_lock(&dev->struct_mutex);
1077 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1079 mutex_unlock(&dev->struct_mutex);
1084 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1085 __func__, args->handle, obj, obj->size);
1087 obj_priv = to_intel_bo(obj);
1089 /* Pinned buffers may be scanout, so flush the cache */
1090 if (obj_priv->pin_count)
1091 i915_gem_object_flush_cpu_write_domain(obj);
1093 drm_gem_object_unreference(obj);
1094 mutex_unlock(&dev->struct_mutex);
1099 * Maps the contents of an object, returning the address it is mapped
1102 * While the mapping holds a reference on the contents of the object, it doesn't
1103 * imply a ref on the object itself.
1106 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv)
1109 struct drm_i915_gem_mmap *args = data;
1110 struct drm_gem_object *obj;
1114 if (!(dev->driver->driver_features & DRIVER_GEM))
1117 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1121 offset = args->offset;
1123 down_write(¤t->mm->mmap_sem);
1124 addr = do_mmap(obj->filp, 0, args->size,
1125 PROT_READ | PROT_WRITE, MAP_SHARED,
1127 up_write(¤t->mm->mmap_sem);
1128 drm_gem_object_unreference_unlocked(obj);
1129 if (IS_ERR((void *)addr))
1132 args->addr_ptr = (uint64_t) addr;
1138 * i915_gem_fault - fault a page into the GTT
1139 * vma: VMA in question
1142 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1143 * from userspace. The fault handler takes care of binding the object to
1144 * the GTT (if needed), allocating and programming a fence register (again,
1145 * only if needed based on whether the old reg is still valid or the object
1146 * is tiled) and inserting a new PTE into the faulting process.
1148 * Note that the faulting process may involve evicting existing objects
1149 * from the GTT and/or fence registers to make room. So performance may
1150 * suffer if the GTT working set is large or there are few fence registers
1153 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1155 struct drm_gem_object *obj = vma->vm_private_data;
1156 struct drm_device *dev = obj->dev;
1157 drm_i915_private_t *dev_priv = dev->dev_private;
1158 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1159 pgoff_t page_offset;
1162 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1164 /* We don't use vmf->pgoff since that has the fake offset */
1165 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1168 /* Now bind it into the GTT if needed */
1169 mutex_lock(&dev->struct_mutex);
1170 if (!obj_priv->gtt_space) {
1171 ret = i915_gem_object_bind_to_gtt(obj, 0);
1175 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1180 /* Need a new fence register? */
1181 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1182 ret = i915_gem_object_get_fence_reg(obj);
1187 if (i915_gem_object_is_inactive(obj_priv))
1188 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1190 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1193 /* Finally, remap it using the new GTT offset */
1194 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1196 mutex_unlock(&dev->struct_mutex);
1201 return VM_FAULT_NOPAGE;
1204 return VM_FAULT_OOM;
1206 return VM_FAULT_SIGBUS;
1211 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1212 * @obj: obj in question
1214 * GEM memory mapping works by handing back to userspace a fake mmap offset
1215 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1216 * up the object based on the offset and sets up the various memory mapping
1219 * This routine allocates and attaches a fake offset for @obj.
1222 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1224 struct drm_device *dev = obj->dev;
1225 struct drm_gem_mm *mm = dev->mm_private;
1226 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1227 struct drm_map_list *list;
1228 struct drm_local_map *map;
1231 /* Set the object up for mmap'ing */
1232 list = &obj->map_list;
1233 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1238 map->type = _DRM_GEM;
1239 map->size = obj->size;
1242 /* Get a DRM GEM mmap offset allocated... */
1243 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1244 obj->size / PAGE_SIZE, 0, 0);
1245 if (!list->file_offset_node) {
1246 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1251 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1252 obj->size / PAGE_SIZE, 0);
1253 if (!list->file_offset_node) {
1258 list->hash.key = list->file_offset_node->start;
1259 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1260 DRM_ERROR("failed to add to map hash\n");
1265 /* By now we should be all set, any drm_mmap request on the offset
1266 * below will get to our mmap & fault handler */
1267 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1272 drm_mm_put_block(list->file_offset_node);
1280 * i915_gem_release_mmap - remove physical page mappings
1281 * @obj: obj in question
1283 * Preserve the reservation of the mmapping with the DRM core code, but
1284 * relinquish ownership of the pages back to the system.
1286 * It is vital that we remove the page mapping if we have mapped a tiled
1287 * object through the GTT and then lose the fence register due to
1288 * resource pressure. Similarly if the object has been moved out of the
1289 * aperture, than pages mapped into userspace must be revoked. Removing the
1290 * mapping will then trigger a page fault on the next user access, allowing
1291 * fixup by i915_gem_fault().
1294 i915_gem_release_mmap(struct drm_gem_object *obj)
1296 struct drm_device *dev = obj->dev;
1297 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1299 if (dev->dev_mapping)
1300 unmap_mapping_range(dev->dev_mapping,
1301 obj_priv->mmap_offset, obj->size, 1);
1305 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1309 struct drm_gem_mm *mm = dev->mm_private;
1310 struct drm_map_list *list;
1312 list = &obj->map_list;
1313 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1315 if (list->file_offset_node) {
1316 drm_mm_put_block(list->file_offset_node);
1317 list->file_offset_node = NULL;
1325 obj_priv->mmap_offset = 0;
1329 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1330 * @obj: object to check
1332 * Return the required GTT alignment for an object, taking into account
1333 * potential fence register mapping if needed.
1336 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1338 struct drm_device *dev = obj->dev;
1339 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1343 * Minimum alignment is 4k (GTT page size), but might be greater
1344 * if a fence register is needed for the object.
1346 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1350 * Previous chips need to be aligned to the size of the smallest
1351 * fence register that can contain the object.
1358 for (i = start; i < obj->size; i <<= 1)
1365 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1367 * @data: GTT mapping ioctl data
1368 * @file_priv: GEM object info
1370 * Simply returns the fake offset to userspace so it can mmap it.
1371 * The mmap call will end up in drm_gem_mmap(), which will set things
1372 * up so we can get faults in the handler above.
1374 * The fault handler will take care of binding the object into the GTT
1375 * (since it may have been evicted to make room for something), allocating
1376 * a fence register, and mapping the appropriate aperture address into
1380 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1381 struct drm_file *file_priv)
1383 struct drm_i915_gem_mmap_gtt *args = data;
1384 struct drm_gem_object *obj;
1385 struct drm_i915_gem_object *obj_priv;
1388 if (!(dev->driver->driver_features & DRIVER_GEM))
1391 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1395 mutex_lock(&dev->struct_mutex);
1397 obj_priv = to_intel_bo(obj);
1399 if (obj_priv->madv != I915_MADV_WILLNEED) {
1400 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1401 drm_gem_object_unreference(obj);
1402 mutex_unlock(&dev->struct_mutex);
1407 if (!obj_priv->mmap_offset) {
1408 ret = i915_gem_create_mmap_offset(obj);
1410 drm_gem_object_unreference(obj);
1411 mutex_unlock(&dev->struct_mutex);
1416 args->offset = obj_priv->mmap_offset;
1419 * Pull it into the GTT so that we have a page list (makes the
1420 * initial fault faster and any subsequent flushing possible).
1422 if (!obj_priv->agp_mem) {
1423 ret = i915_gem_object_bind_to_gtt(obj, 0);
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
1431 drm_gem_object_unreference(obj);
1432 mutex_unlock(&dev->struct_mutex);
1438 i915_gem_object_put_pages(struct drm_gem_object *obj)
1440 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1441 int page_count = obj->size / PAGE_SIZE;
1444 BUG_ON(obj_priv->pages_refcount == 0);
1445 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1447 if (--obj_priv->pages_refcount != 0)
1450 if (obj_priv->tiling_mode != I915_TILING_NONE)
1451 i915_gem_object_save_bit_17_swizzle(obj);
1453 if (obj_priv->madv == I915_MADV_DONTNEED)
1454 obj_priv->dirty = 0;
1456 for (i = 0; i < page_count; i++) {
1457 if (obj_priv->dirty)
1458 set_page_dirty(obj_priv->pages[i]);
1460 if (obj_priv->madv == I915_MADV_WILLNEED)
1461 mark_page_accessed(obj_priv->pages[i]);
1463 page_cache_release(obj_priv->pages[i]);
1465 obj_priv->dirty = 0;
1467 drm_free_large(obj_priv->pages);
1468 obj_priv->pages = NULL;
1472 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1473 struct intel_ring_buffer *ring)
1475 struct drm_device *dev = obj->dev;
1476 drm_i915_private_t *dev_priv = dev->dev_private;
1477 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1478 BUG_ON(ring == NULL);
1479 obj_priv->ring = ring;
1481 /* Add a reference if we're newly entering the active list. */
1482 if (!obj_priv->active) {
1483 drm_gem_object_reference(obj);
1484 obj_priv->active = 1;
1486 /* Move from whatever list we were on to the tail of execution. */
1487 spin_lock(&dev_priv->mm.active_list_lock);
1488 list_move_tail(&obj_priv->list, &ring->active_list);
1489 spin_unlock(&dev_priv->mm.active_list_lock);
1490 obj_priv->last_rendering_seqno = seqno;
1494 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1496 struct drm_device *dev = obj->dev;
1497 drm_i915_private_t *dev_priv = dev->dev_private;
1498 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1500 BUG_ON(!obj_priv->active);
1501 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1502 obj_priv->last_rendering_seqno = 0;
1505 /* Immediately discard the backing storage */
1507 i915_gem_object_truncate(struct drm_gem_object *obj)
1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1510 struct inode *inode;
1512 /* Our goal here is to return as much of the memory as
1513 * is possible back to the system as we are called from OOM.
1514 * To do this we must instruct the shmfs to drop all of its
1515 * backing pages, *now*. Here we mirror the actions taken
1516 * when by shmem_delete_inode() to release the backing store.
1518 inode = obj->filp->f_path.dentry->d_inode;
1519 truncate_inode_pages(inode->i_mapping, 0);
1520 if (inode->i_op->truncate_range)
1521 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1523 obj_priv->madv = __I915_MADV_PURGED;
1527 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1529 return obj_priv->madv == I915_MADV_DONTNEED;
1533 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1535 struct drm_device *dev = obj->dev;
1536 drm_i915_private_t *dev_priv = dev->dev_private;
1537 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1539 i915_verify_inactive(dev, __FILE__, __LINE__);
1540 if (obj_priv->pin_count != 0)
1541 list_del_init(&obj_priv->list);
1543 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1545 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1547 obj_priv->last_rendering_seqno = 0;
1548 obj_priv->ring = NULL;
1549 if (obj_priv->active) {
1550 obj_priv->active = 0;
1551 drm_gem_object_unreference(obj);
1553 i915_verify_inactive(dev, __FILE__, __LINE__);
1557 i915_gem_process_flushing_list(struct drm_device *dev,
1558 uint32_t flush_domains, uint32_t seqno,
1559 struct intel_ring_buffer *ring)
1561 drm_i915_private_t *dev_priv = dev->dev_private;
1562 struct drm_i915_gem_object *obj_priv, *next;
1564 list_for_each_entry_safe(obj_priv, next,
1565 &dev_priv->mm.gpu_write_list,
1567 struct drm_gem_object *obj = &obj_priv->base;
1569 if ((obj->write_domain & flush_domains) ==
1570 obj->write_domain &&
1571 obj_priv->ring->ring_flag == ring->ring_flag) {
1572 uint32_t old_write_domain = obj->write_domain;
1574 obj->write_domain = 0;
1575 list_del_init(&obj_priv->gpu_write_list);
1576 i915_gem_object_move_to_active(obj, seqno, ring);
1578 /* update the fence lru list */
1579 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1580 struct drm_i915_fence_reg *reg =
1581 &dev_priv->fence_regs[obj_priv->fence_reg];
1582 list_move_tail(®->lru_list,
1583 &dev_priv->mm.fence_list);
1586 trace_i915_gem_object_change_domain(obj,
1594 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1595 uint32_t flush_domains, struct intel_ring_buffer *ring)
1597 drm_i915_private_t *dev_priv = dev->dev_private;
1598 struct drm_i915_file_private *i915_file_priv = NULL;
1599 struct drm_i915_gem_request *request;
1603 if (file_priv != NULL)
1604 i915_file_priv = file_priv->driver_priv;
1606 request = kzalloc(sizeof(*request), GFP_KERNEL);
1607 if (request == NULL)
1610 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1612 request->seqno = seqno;
1613 request->ring = ring;
1614 request->emitted_jiffies = jiffies;
1615 was_empty = list_empty(&ring->request_list);
1616 list_add_tail(&request->list, &ring->request_list);
1618 if (i915_file_priv) {
1619 list_add_tail(&request->client_list,
1620 &i915_file_priv->mm.request_list);
1622 INIT_LIST_HEAD(&request->client_list);
1625 /* Associate any objects on the flushing list matching the write
1626 * domain we're flushing with our flush.
1628 if (flush_domains != 0)
1629 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1631 if (!dev_priv->mm.suspended) {
1632 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1634 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1640 * Command execution barrier
1642 * Ensures that all commands in the ring are finished
1643 * before signalling the CPU
1646 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1648 uint32_t flush_domains = 0;
1650 /* The sampler always gets flushed on i965 (sigh) */
1652 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1654 ring->flush(dev, ring,
1655 I915_GEM_DOMAIN_COMMAND, flush_domains);
1656 return flush_domains;
1660 * Moves buffers associated only with the given active seqno from the active
1661 * to inactive list, potentially freeing them.
1664 i915_gem_retire_request(struct drm_device *dev,
1665 struct drm_i915_gem_request *request)
1667 drm_i915_private_t *dev_priv = dev->dev_private;
1669 trace_i915_gem_request_retire(dev, request->seqno);
1671 /* Move any buffers on the active list that are no longer referenced
1672 * by the ringbuffer to the flushing/inactive lists as appropriate.
1674 spin_lock(&dev_priv->mm.active_list_lock);
1675 while (!list_empty(&request->ring->active_list)) {
1676 struct drm_gem_object *obj;
1677 struct drm_i915_gem_object *obj_priv;
1679 obj_priv = list_first_entry(&request->ring->active_list,
1680 struct drm_i915_gem_object,
1682 obj = &obj_priv->base;
1684 /* If the seqno being retired doesn't match the oldest in the
1685 * list, then the oldest in the list must still be newer than
1688 if (obj_priv->last_rendering_seqno != request->seqno)
1692 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1693 __func__, request->seqno, obj);
1696 if (obj->write_domain != 0)
1697 i915_gem_object_move_to_flushing(obj);
1699 /* Take a reference on the object so it won't be
1700 * freed while the spinlock is held. The list
1701 * protection for this spinlock is safe when breaking
1702 * the lock like this since the next thing we do
1703 * is just get the head of the list again.
1705 drm_gem_object_reference(obj);
1706 i915_gem_object_move_to_inactive(obj);
1707 spin_unlock(&dev_priv->mm.active_list_lock);
1708 drm_gem_object_unreference(obj);
1709 spin_lock(&dev_priv->mm.active_list_lock);
1713 spin_unlock(&dev_priv->mm.active_list_lock);
1717 * Returns true if seq1 is later than seq2.
1720 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1722 return (int32_t)(seq1 - seq2) >= 0;
1726 i915_get_gem_seqno(struct drm_device *dev,
1727 struct intel_ring_buffer *ring)
1729 return ring->get_gem_seqno(dev, ring);
1733 * This function clears the request list as sequence numbers are passed.
1736 i915_gem_retire_requests_ring(struct drm_device *dev,
1737 struct intel_ring_buffer *ring)
1739 drm_i915_private_t *dev_priv = dev->dev_private;
1742 if (!ring->status_page.page_addr
1743 || list_empty(&ring->request_list))
1746 seqno = i915_get_gem_seqno(dev, ring);
1748 while (!list_empty(&ring->request_list)) {
1749 struct drm_i915_gem_request *request;
1750 uint32_t retiring_seqno;
1752 request = list_first_entry(&ring->request_list,
1753 struct drm_i915_gem_request,
1755 retiring_seqno = request->seqno;
1757 if (i915_seqno_passed(seqno, retiring_seqno) ||
1758 atomic_read(&dev_priv->mm.wedged)) {
1759 i915_gem_retire_request(dev, request);
1761 list_del(&request->list);
1762 list_del(&request->client_list);
1768 if (unlikely (dev_priv->trace_irq_seqno &&
1769 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1771 ring->user_irq_put(dev, ring);
1772 dev_priv->trace_irq_seqno = 0;
1777 i915_gem_retire_requests(struct drm_device *dev)
1779 drm_i915_private_t *dev_priv = dev->dev_private;
1781 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1782 struct drm_i915_gem_object *obj_priv, *tmp;
1784 /* We must be careful that during unbind() we do not
1785 * accidentally infinitely recurse into retire requests.
1787 * retire -> free -> unbind -> wait -> retire_ring
1789 list_for_each_entry_safe(obj_priv, tmp,
1790 &dev_priv->mm.deferred_free_list,
1792 i915_gem_free_object_tail(&obj_priv->base);
1795 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1797 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1801 i915_gem_retire_work_handler(struct work_struct *work)
1803 drm_i915_private_t *dev_priv;
1804 struct drm_device *dev;
1806 dev_priv = container_of(work, drm_i915_private_t,
1807 mm.retire_work.work);
1808 dev = dev_priv->dev;
1810 mutex_lock(&dev->struct_mutex);
1811 i915_gem_retire_requests(dev);
1813 if (!dev_priv->mm.suspended &&
1814 (!list_empty(&dev_priv->render_ring.request_list) ||
1816 !list_empty(&dev_priv->bsd_ring.request_list))))
1817 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1818 mutex_unlock(&dev->struct_mutex);
1822 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1823 int interruptible, struct intel_ring_buffer *ring)
1825 drm_i915_private_t *dev_priv = dev->dev_private;
1831 if (atomic_read(&dev_priv->mm.wedged))
1834 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1835 if (HAS_PCH_SPLIT(dev))
1836 ier = I915_READ(DEIER) | I915_READ(GTIER);
1838 ier = I915_READ(IER);
1840 DRM_ERROR("something (likely vbetool) disabled "
1841 "interrupts, re-enabling\n");
1842 i915_driver_irq_preinstall(dev);
1843 i915_driver_irq_postinstall(dev);
1846 trace_i915_gem_request_wait_begin(dev, seqno);
1848 ring->waiting_gem_seqno = seqno;
1849 ring->user_irq_get(dev, ring);
1851 ret = wait_event_interruptible(ring->irq_queue,
1853 ring->get_gem_seqno(dev, ring), seqno)
1854 || atomic_read(&dev_priv->mm.wedged));
1856 wait_event(ring->irq_queue,
1858 ring->get_gem_seqno(dev, ring), seqno)
1859 || atomic_read(&dev_priv->mm.wedged));
1861 ring->user_irq_put(dev, ring);
1862 ring->waiting_gem_seqno = 0;
1864 trace_i915_gem_request_wait_end(dev, seqno);
1866 if (atomic_read(&dev_priv->mm.wedged))
1869 if (ret && ret != -ERESTARTSYS)
1870 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1873 /* Directly dispatch request retiring. While we have the work queue
1874 * to handle this, the waiter on a request often wants an associated
1875 * buffer to have made it to the inactive list, and we would need
1876 * a separate wait queue to handle that.
1879 i915_gem_retire_requests_ring(dev, ring);
1885 * Waits for a sequence number to be signaled, and cleans up the
1886 * request and object lists appropriately for that event.
1889 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1890 struct intel_ring_buffer *ring)
1892 return i915_do_wait_request(dev, seqno, 1, ring);
1896 i915_gem_flush(struct drm_device *dev,
1897 uint32_t invalidate_domains,
1898 uint32_t flush_domains)
1900 drm_i915_private_t *dev_priv = dev->dev_private;
1901 if (flush_domains & I915_GEM_DOMAIN_CPU)
1902 drm_agp_chipset_flush(dev);
1903 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1908 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1914 * Ensures that all rendering to the object has completed and the object is
1915 * safe to unbind from the GTT or access from the CPU.
1918 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1920 struct drm_device *dev = obj->dev;
1921 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1924 /* This function only exists to support waiting for existing rendering,
1925 * not for emitting required flushes.
1927 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1929 /* If there is rendering queued on the buffer being evicted, wait for
1932 if (obj_priv->active) {
1934 DRM_INFO("%s: object %p wait for seqno %08x\n",
1935 __func__, obj, obj_priv->last_rendering_seqno);
1937 ret = i915_wait_request(dev,
1938 obj_priv->last_rendering_seqno, obj_priv->ring);
1947 * Unbinds an object from the GTT aperture.
1950 i915_gem_object_unbind(struct drm_gem_object *obj)
1952 struct drm_device *dev = obj->dev;
1953 drm_i915_private_t *dev_priv = dev->dev_private;
1954 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1958 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1959 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1961 if (obj_priv->gtt_space == NULL)
1964 if (obj_priv->pin_count != 0) {
1965 DRM_ERROR("Attempting to unbind pinned buffer\n");
1969 /* blow away mappings if mapped through GTT */
1970 i915_gem_release_mmap(obj);
1972 /* Move the object to the CPU domain to ensure that
1973 * any possible CPU writes while it's not in the GTT
1974 * are flushed when we go to remap it. This will
1975 * also ensure that all pending GPU writes are finished
1978 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1979 if (ret == -ERESTARTSYS)
1981 /* Continue on if we fail due to EIO, the GPU is hung so we
1982 * should be safe and we need to cleanup or else we might
1983 * cause memory corruption through use-after-free.
1986 /* release the fence reg _after_ flushing */
1987 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1988 i915_gem_clear_fence_reg(obj);
1990 if (obj_priv->agp_mem != NULL) {
1991 drm_unbind_agp(obj_priv->agp_mem);
1992 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1993 obj_priv->agp_mem = NULL;
1996 i915_gem_object_put_pages(obj);
1997 BUG_ON(obj_priv->pages_refcount);
1999 if (obj_priv->gtt_space) {
2000 atomic_dec(&dev->gtt_count);
2001 atomic_sub(obj->size, &dev->gtt_memory);
2003 drm_mm_put_block(obj_priv->gtt_space);
2004 obj_priv->gtt_space = NULL;
2007 /* Remove ourselves from the LRU list if present. */
2008 spin_lock(&dev_priv->mm.active_list_lock);
2009 if (!list_empty(&obj_priv->list))
2010 list_del_init(&obj_priv->list);
2011 spin_unlock(&dev_priv->mm.active_list_lock);
2013 if (i915_gem_object_is_purgeable(obj_priv))
2014 i915_gem_object_truncate(obj);
2016 trace_i915_gem_object_unbind(obj);
2022 i915_gpu_idle(struct drm_device *dev)
2024 drm_i915_private_t *dev_priv = dev->dev_private;
2026 uint32_t seqno1, seqno2;
2029 spin_lock(&dev_priv->mm.active_list_lock);
2030 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2031 list_empty(&dev_priv->render_ring.active_list) &&
2033 list_empty(&dev_priv->bsd_ring.active_list)));
2034 spin_unlock(&dev_priv->mm.active_list_lock);
2039 /* Flush everything onto the inactive list. */
2040 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2041 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2042 &dev_priv->render_ring);
2045 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2048 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2049 &dev_priv->bsd_ring);
2053 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2063 i915_gem_object_get_pages(struct drm_gem_object *obj,
2066 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2068 struct address_space *mapping;
2069 struct inode *inode;
2072 BUG_ON(obj_priv->pages_refcount
2073 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2075 if (obj_priv->pages_refcount++ != 0)
2078 /* Get the list of pages out of our struct file. They'll be pinned
2079 * at this point until we release them.
2081 page_count = obj->size / PAGE_SIZE;
2082 BUG_ON(obj_priv->pages != NULL);
2083 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2084 if (obj_priv->pages == NULL) {
2085 obj_priv->pages_refcount--;
2089 inode = obj->filp->f_path.dentry->d_inode;
2090 mapping = inode->i_mapping;
2091 for (i = 0; i < page_count; i++) {
2092 page = read_cache_page_gfp(mapping, i,
2100 obj_priv->pages[i] = page;
2103 if (obj_priv->tiling_mode != I915_TILING_NONE)
2104 i915_gem_object_do_bit_17_swizzle(obj);
2110 page_cache_release(obj_priv->pages[i]);
2112 drm_free_large(obj_priv->pages);
2113 obj_priv->pages = NULL;
2114 obj_priv->pages_refcount--;
2115 return PTR_ERR(page);
2118 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2120 struct drm_gem_object *obj = reg->obj;
2121 struct drm_device *dev = obj->dev;
2122 drm_i915_private_t *dev_priv = dev->dev_private;
2123 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2124 int regnum = obj_priv->fence_reg;
2127 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2129 val |= obj_priv->gtt_offset & 0xfffff000;
2130 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2131 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2133 if (obj_priv->tiling_mode == I915_TILING_Y)
2134 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2135 val |= I965_FENCE_REG_VALID;
2137 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2140 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2142 struct drm_gem_object *obj = reg->obj;
2143 struct drm_device *dev = obj->dev;
2144 drm_i915_private_t *dev_priv = dev->dev_private;
2145 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2146 int regnum = obj_priv->fence_reg;
2149 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2151 val |= obj_priv->gtt_offset & 0xfffff000;
2152 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2153 if (obj_priv->tiling_mode == I915_TILING_Y)
2154 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2155 val |= I965_FENCE_REG_VALID;
2157 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2160 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2162 struct drm_gem_object *obj = reg->obj;
2163 struct drm_device *dev = obj->dev;
2164 drm_i915_private_t *dev_priv = dev->dev_private;
2165 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2166 int regnum = obj_priv->fence_reg;
2168 uint32_t fence_reg, val;
2171 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2172 (obj_priv->gtt_offset & (obj->size - 1))) {
2173 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2174 __func__, obj_priv->gtt_offset, obj->size);
2178 if (obj_priv->tiling_mode == I915_TILING_Y &&
2179 HAS_128_BYTE_Y_TILING(dev))
2184 /* Note: pitch better be a power of two tile widths */
2185 pitch_val = obj_priv->stride / tile_width;
2186 pitch_val = ffs(pitch_val) - 1;
2188 if (obj_priv->tiling_mode == I915_TILING_Y &&
2189 HAS_128_BYTE_Y_TILING(dev))
2190 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2192 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2194 val = obj_priv->gtt_offset;
2195 if (obj_priv->tiling_mode == I915_TILING_Y)
2196 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2197 val |= I915_FENCE_SIZE_BITS(obj->size);
2198 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2199 val |= I830_FENCE_REG_VALID;
2202 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2204 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2205 I915_WRITE(fence_reg, val);
2208 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2210 struct drm_gem_object *obj = reg->obj;
2211 struct drm_device *dev = obj->dev;
2212 drm_i915_private_t *dev_priv = dev->dev_private;
2213 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2214 int regnum = obj_priv->fence_reg;
2217 uint32_t fence_size_bits;
2219 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2220 (obj_priv->gtt_offset & (obj->size - 1))) {
2221 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2222 __func__, obj_priv->gtt_offset);
2226 pitch_val = obj_priv->stride / 128;
2227 pitch_val = ffs(pitch_val) - 1;
2228 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2230 val = obj_priv->gtt_offset;
2231 if (obj_priv->tiling_mode == I915_TILING_Y)
2232 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2233 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2234 WARN_ON(fence_size_bits & ~0x00000f00);
2235 val |= fence_size_bits;
2236 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2237 val |= I830_FENCE_REG_VALID;
2239 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2242 static int i915_find_fence_reg(struct drm_device *dev)
2244 struct drm_i915_fence_reg *reg = NULL;
2245 struct drm_i915_gem_object *obj_priv = NULL;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_gem_object *obj = NULL;
2250 /* First try to find a free reg */
2252 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2253 reg = &dev_priv->fence_regs[i];
2257 obj_priv = to_intel_bo(reg->obj);
2258 if (!obj_priv->pin_count)
2265 /* None available, try to steal one or wait for a user to finish */
2266 i = I915_FENCE_REG_NONE;
2267 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2270 obj_priv = to_intel_bo(obj);
2272 if (obj_priv->pin_count)
2276 i = obj_priv->fence_reg;
2280 BUG_ON(i == I915_FENCE_REG_NONE);
2282 /* We only have a reference on obj from the active list. put_fence_reg
2283 * might drop that one, causing a use-after-free in it. So hold a
2284 * private reference to obj like the other callers of put_fence_reg
2285 * (set_tiling ioctl) do. */
2286 drm_gem_object_reference(obj);
2287 ret = i915_gem_object_put_fence_reg(obj);
2288 drm_gem_object_unreference(obj);
2296 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2297 * @obj: object to map through a fence reg
2299 * When mapping objects through the GTT, userspace wants to be able to write
2300 * to them without having to worry about swizzling if the object is tiled.
2302 * This function walks the fence regs looking for a free one for @obj,
2303 * stealing one if it can't find any.
2305 * It then sets up the reg based on the object's properties: address, pitch
2306 * and tiling format.
2309 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2311 struct drm_device *dev = obj->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2314 struct drm_i915_fence_reg *reg = NULL;
2317 /* Just update our place in the LRU if our fence is getting used. */
2318 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2319 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2320 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2324 switch (obj_priv->tiling_mode) {
2325 case I915_TILING_NONE:
2326 WARN(1, "allocating a fence for non-tiled object?\n");
2329 if (!obj_priv->stride)
2331 WARN((obj_priv->stride & (512 - 1)),
2332 "object 0x%08x is X tiled but has non-512B pitch\n",
2333 obj_priv->gtt_offset);
2336 if (!obj_priv->stride)
2338 WARN((obj_priv->stride & (128 - 1)),
2339 "object 0x%08x is Y tiled but has non-128B pitch\n",
2340 obj_priv->gtt_offset);
2344 ret = i915_find_fence_reg(dev);
2348 obj_priv->fence_reg = ret;
2349 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2350 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2354 switch (INTEL_INFO(dev)->gen) {
2356 sandybridge_write_fence_reg(reg);
2360 i965_write_fence_reg(reg);
2363 i915_write_fence_reg(reg);
2366 i830_write_fence_reg(reg);
2370 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2371 obj_priv->tiling_mode);
2377 * i915_gem_clear_fence_reg - clear out fence register info
2378 * @obj: object to clear
2380 * Zeroes out the fence register itself and clears out the associated
2381 * data structures in dev_priv and obj_priv.
2384 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2386 struct drm_device *dev = obj->dev;
2387 drm_i915_private_t *dev_priv = dev->dev_private;
2388 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2389 struct drm_i915_fence_reg *reg =
2390 &dev_priv->fence_regs[obj_priv->fence_reg];
2393 switch (INTEL_INFO(dev)->gen) {
2395 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2396 (obj_priv->fence_reg * 8), 0);
2400 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2403 if (obj_priv->fence_reg > 8)
2404 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2407 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2409 I915_WRITE(fence_reg, 0);
2414 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2415 list_del_init(®->lru_list);
2419 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2420 * to the buffer to finish, and then resets the fence register.
2421 * @obj: tiled object holding a fence register.
2423 * Zeroes out the fence register itself and clears out the associated
2424 * data structures in dev_priv and obj_priv.
2427 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2429 struct drm_device *dev = obj->dev;
2430 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2432 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2435 /* If we've changed tiling, GTT-mappings of the object
2436 * need to re-fault to ensure that the correct fence register
2437 * setup is in place.
2439 i915_gem_release_mmap(obj);
2441 /* On the i915, GPU access to tiled buffers is via a fence,
2442 * therefore we must wait for any outstanding access to complete
2443 * before clearing the fence.
2445 if (!IS_I965G(dev)) {
2448 ret = i915_gem_object_flush_gpu_write_domain(obj);
2452 ret = i915_gem_object_wait_rendering(obj);
2457 i915_gem_object_flush_gtt_write_domain(obj);
2458 i915_gem_clear_fence_reg (obj);
2464 * Finds free space in the GTT aperture and binds the object there.
2467 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2469 struct drm_device *dev = obj->dev;
2470 drm_i915_private_t *dev_priv = dev->dev_private;
2471 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2472 struct drm_mm_node *free_space;
2473 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2476 if (obj_priv->madv != I915_MADV_WILLNEED) {
2477 DRM_ERROR("Attempting to bind a purgeable object\n");
2482 alignment = i915_gem_get_gtt_alignment(obj);
2483 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2484 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2488 /* If the object is bigger than the entire aperture, reject it early
2489 * before evicting everything in a vain attempt to find space.
2491 if (obj->size > dev->gtt_total) {
2492 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2497 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2498 obj->size, alignment, 0);
2499 if (free_space != NULL) {
2500 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2502 if (obj_priv->gtt_space != NULL)
2503 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2505 if (obj_priv->gtt_space == NULL) {
2506 /* If the gtt is empty and we're still having trouble
2507 * fitting our object in, we're out of memory.
2510 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2512 ret = i915_gem_evict_something(dev, obj->size, alignment);
2520 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2521 obj->size, obj_priv->gtt_offset);
2523 ret = i915_gem_object_get_pages(obj, gfpmask);
2525 drm_mm_put_block(obj_priv->gtt_space);
2526 obj_priv->gtt_space = NULL;
2528 if (ret == -ENOMEM) {
2529 /* first try to clear up some space from the GTT */
2530 ret = i915_gem_evict_something(dev, obj->size,
2533 /* now try to shrink everyone else */
2548 /* Create an AGP memory structure pointing at our pages, and bind it
2551 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2553 obj->size >> PAGE_SHIFT,
2554 obj_priv->gtt_offset,
2555 obj_priv->agp_type);
2556 if (obj_priv->agp_mem == NULL) {
2557 i915_gem_object_put_pages(obj);
2558 drm_mm_put_block(obj_priv->gtt_space);
2559 obj_priv->gtt_space = NULL;
2561 ret = i915_gem_evict_something(dev, obj->size, alignment);
2567 atomic_inc(&dev->gtt_count);
2568 atomic_add(obj->size, &dev->gtt_memory);
2570 /* keep track of bounds object by adding it to the inactive list */
2571 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2573 /* Assert that the object is not currently in any GPU domain. As it
2574 * wasn't in the GTT, there shouldn't be any way it could have been in
2577 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2578 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2580 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2586 i915_gem_clflush_object(struct drm_gem_object *obj)
2588 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2590 /* If we don't have a page list set up, then we're not pinned
2591 * to GPU, and we can ignore the cache flush because it'll happen
2592 * again at bind time.
2594 if (obj_priv->pages == NULL)
2597 trace_i915_gem_object_clflush(obj);
2599 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2602 /** Flushes any GPU write domain for the object if it's dirty. */
2604 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2606 struct drm_device *dev = obj->dev;
2607 uint32_t old_write_domain;
2608 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2610 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2613 /* Queue the GPU write cache flushing we need. */
2614 old_write_domain = obj->write_domain;
2615 i915_gem_flush(dev, 0, obj->write_domain);
2616 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2619 trace_i915_gem_object_change_domain(obj,
2625 /** Flushes the GTT write domain for the object if it's dirty. */
2627 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2629 uint32_t old_write_domain;
2631 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2634 /* No actual flushing is required for the GTT write domain. Writes
2635 * to it immediately go to main memory as far as we know, so there's
2636 * no chipset flush. It also doesn't land in render cache.
2638 old_write_domain = obj->write_domain;
2639 obj->write_domain = 0;
2641 trace_i915_gem_object_change_domain(obj,
2646 /** Flushes the CPU write domain for the object if it's dirty. */
2648 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2650 struct drm_device *dev = obj->dev;
2651 uint32_t old_write_domain;
2653 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2656 i915_gem_clflush_object(obj);
2657 drm_agp_chipset_flush(dev);
2658 old_write_domain = obj->write_domain;
2659 obj->write_domain = 0;
2661 trace_i915_gem_object_change_domain(obj,
2667 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2671 switch (obj->write_domain) {
2672 case I915_GEM_DOMAIN_GTT:
2673 i915_gem_object_flush_gtt_write_domain(obj);
2675 case I915_GEM_DOMAIN_CPU:
2676 i915_gem_object_flush_cpu_write_domain(obj);
2679 ret = i915_gem_object_flush_gpu_write_domain(obj);
2687 * Moves a single object to the GTT read, and possibly write domain.
2689 * This function returns when the move is complete, including waiting on
2693 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2695 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2696 uint32_t old_write_domain, old_read_domains;
2699 /* Not valid to be called on unbound objects. */
2700 if (obj_priv->gtt_space == NULL)
2703 ret = i915_gem_object_flush_gpu_write_domain(obj);
2707 /* Wait on any GPU rendering and flushing to occur. */
2708 ret = i915_gem_object_wait_rendering(obj);
2712 old_write_domain = obj->write_domain;
2713 old_read_domains = obj->read_domains;
2715 /* If we're writing through the GTT domain, then CPU and GPU caches
2716 * will need to be invalidated at next use.
2719 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2721 i915_gem_object_flush_cpu_write_domain(obj);
2723 /* It should now be out of any other write domains, and we can update
2724 * the domain values for our changes.
2726 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2727 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2729 obj->write_domain = I915_GEM_DOMAIN_GTT;
2730 obj_priv->dirty = 1;
2733 trace_i915_gem_object_change_domain(obj,
2741 * Prepare buffer for display plane. Use uninterruptible for possible flush
2742 * wait, as in modesetting process we're not supposed to be interrupted.
2745 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2747 struct drm_device *dev = obj->dev;
2748 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2749 uint32_t old_write_domain, old_read_domains;
2752 /* Not valid to be called on unbound objects. */
2753 if (obj_priv->gtt_space == NULL)
2756 ret = i915_gem_object_flush_gpu_write_domain(obj);
2760 /* Wait on any GPU rendering and flushing to occur. */
2761 if (obj_priv->active) {
2763 DRM_INFO("%s: object %p wait for seqno %08x\n",
2764 __func__, obj, obj_priv->last_rendering_seqno);
2766 ret = i915_do_wait_request(dev,
2767 obj_priv->last_rendering_seqno,
2774 i915_gem_object_flush_cpu_write_domain(obj);
2776 old_write_domain = obj->write_domain;
2777 old_read_domains = obj->read_domains;
2779 /* It should now be out of any other write domains, and we can update
2780 * the domain values for our changes.
2782 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2783 obj->read_domains = I915_GEM_DOMAIN_GTT;
2784 obj->write_domain = I915_GEM_DOMAIN_GTT;
2785 obj_priv->dirty = 1;
2787 trace_i915_gem_object_change_domain(obj,
2795 * Moves a single object to the CPU read, and possibly write domain.
2797 * This function returns when the move is complete, including waiting on
2801 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2803 uint32_t old_write_domain, old_read_domains;
2806 ret = i915_gem_object_flush_gpu_write_domain(obj);
2810 /* Wait on any GPU rendering and flushing to occur. */
2811 ret = i915_gem_object_wait_rendering(obj);
2815 i915_gem_object_flush_gtt_write_domain(obj);
2817 /* If we have a partially-valid cache of the object in the CPU,
2818 * finish invalidating it and free the per-page flags.
2820 i915_gem_object_set_to_full_cpu_read_domain(obj);
2822 old_write_domain = obj->write_domain;
2823 old_read_domains = obj->read_domains;
2825 /* Flush the CPU cache if it's still invalid. */
2826 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2827 i915_gem_clflush_object(obj);
2829 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2832 /* It should now be out of any other write domains, and we can update
2833 * the domain values for our changes.
2835 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2837 /* If we're writing through the CPU, then the GPU read domains will
2838 * need to be invalidated at next use.
2841 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2842 obj->write_domain = I915_GEM_DOMAIN_CPU;
2845 trace_i915_gem_object_change_domain(obj,
2853 * Set the next domain for the specified object. This
2854 * may not actually perform the necessary flushing/invaliding though,
2855 * as that may want to be batched with other set_domain operations
2857 * This is (we hope) the only really tricky part of gem. The goal
2858 * is fairly simple -- track which caches hold bits of the object
2859 * and make sure they remain coherent. A few concrete examples may
2860 * help to explain how it works. For shorthand, we use the notation
2861 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2862 * a pair of read and write domain masks.
2864 * Case 1: the batch buffer
2870 * 5. Unmapped from GTT
2873 * Let's take these a step at a time
2876 * Pages allocated from the kernel may still have
2877 * cache contents, so we set them to (CPU, CPU) always.
2878 * 2. Written by CPU (using pwrite)
2879 * The pwrite function calls set_domain (CPU, CPU) and
2880 * this function does nothing (as nothing changes)
2882 * This function asserts that the object is not
2883 * currently in any GPU-based read or write domains
2885 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2886 * As write_domain is zero, this function adds in the
2887 * current read domains (CPU+COMMAND, 0).
2888 * flush_domains is set to CPU.
2889 * invalidate_domains is set to COMMAND
2890 * clflush is run to get data out of the CPU caches
2891 * then i915_dev_set_domain calls i915_gem_flush to
2892 * emit an MI_FLUSH and drm_agp_chipset_flush
2893 * 5. Unmapped from GTT
2894 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2895 * flush_domains and invalidate_domains end up both zero
2896 * so no flushing/invalidating happens
2900 * Case 2: The shared render buffer
2904 * 3. Read/written by GPU
2905 * 4. set_domain to (CPU,CPU)
2906 * 5. Read/written by CPU
2907 * 6. Read/written by GPU
2910 * Same as last example, (CPU, CPU)
2912 * Nothing changes (assertions find that it is not in the GPU)
2913 * 3. Read/written by GPU
2914 * execbuffer calls set_domain (RENDER, RENDER)
2915 * flush_domains gets CPU
2916 * invalidate_domains gets GPU
2918 * MI_FLUSH and drm_agp_chipset_flush
2919 * 4. set_domain (CPU, CPU)
2920 * flush_domains gets GPU
2921 * invalidate_domains gets CPU
2922 * wait_rendering (obj) to make sure all drawing is complete.
2923 * This will include an MI_FLUSH to get the data from GPU
2925 * clflush (obj) to invalidate the CPU cache
2926 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2927 * 5. Read/written by CPU
2928 * cache lines are loaded and dirtied
2929 * 6. Read written by GPU
2930 * Same as last GPU access
2932 * Case 3: The constant buffer
2937 * 4. Updated (written) by CPU again
2946 * flush_domains = CPU
2947 * invalidate_domains = RENDER
2950 * drm_agp_chipset_flush
2951 * 4. Updated (written) by CPU again
2953 * flush_domains = 0 (no previous write domain)
2954 * invalidate_domains = 0 (no new read domains)
2957 * flush_domains = CPU
2958 * invalidate_domains = RENDER
2961 * drm_agp_chipset_flush
2964 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2966 struct drm_device *dev = obj->dev;
2967 drm_i915_private_t *dev_priv = dev->dev_private;
2968 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2969 uint32_t invalidate_domains = 0;
2970 uint32_t flush_domains = 0;
2971 uint32_t old_read_domains;
2973 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2974 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2976 intel_mark_busy(dev, obj);
2979 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2981 obj->read_domains, obj->pending_read_domains,
2982 obj->write_domain, obj->pending_write_domain);
2985 * If the object isn't moving to a new write domain,
2986 * let the object stay in multiple read domains
2988 if (obj->pending_write_domain == 0)
2989 obj->pending_read_domains |= obj->read_domains;
2991 obj_priv->dirty = 1;
2994 * Flush the current write domain if
2995 * the new read domains don't match. Invalidate
2996 * any read domains which differ from the old
2999 if (obj->write_domain &&
3000 obj->write_domain != obj->pending_read_domains) {
3001 flush_domains |= obj->write_domain;
3002 invalidate_domains |=
3003 obj->pending_read_domains & ~obj->write_domain;
3006 * Invalidate any read caches which may have
3007 * stale data. That is, any new read domains.
3009 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3010 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3012 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3013 __func__, flush_domains, invalidate_domains);
3015 i915_gem_clflush_object(obj);
3018 old_read_domains = obj->read_domains;
3020 /* The actual obj->write_domain will be updated with
3021 * pending_write_domain after we emit the accumulated flush for all
3022 * of our domain changes in execbuffers (which clears objects'
3023 * write_domains). So if we have a current write domain that we
3024 * aren't changing, set pending_write_domain to that.
3026 if (flush_domains == 0 && obj->pending_write_domain == 0)
3027 obj->pending_write_domain = obj->write_domain;
3028 obj->read_domains = obj->pending_read_domains;
3030 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3031 if (obj_priv->ring == &dev_priv->render_ring)
3032 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3033 else if (obj_priv->ring == &dev_priv->bsd_ring)
3034 dev_priv->flush_rings |= FLUSH_BSD_RING;
3037 dev->invalidate_domains |= invalidate_domains;
3038 dev->flush_domains |= flush_domains;
3040 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3042 obj->read_domains, obj->write_domain,
3043 dev->invalidate_domains, dev->flush_domains);
3046 trace_i915_gem_object_change_domain(obj,
3052 * Moves the object from a partially CPU read to a full one.
3054 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3055 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3058 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3060 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3062 if (!obj_priv->page_cpu_valid)
3065 /* If we're partially in the CPU read domain, finish moving it in.
3067 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3070 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3071 if (obj_priv->page_cpu_valid[i])
3073 drm_clflush_pages(obj_priv->pages + i, 1);
3077 /* Free the page_cpu_valid mappings which are now stale, whether
3078 * or not we've got I915_GEM_DOMAIN_CPU.
3080 kfree(obj_priv->page_cpu_valid);
3081 obj_priv->page_cpu_valid = NULL;
3085 * Set the CPU read domain on a range of the object.
3087 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3088 * not entirely valid. The page_cpu_valid member of the object flags which
3089 * pages have been flushed, and will be respected by
3090 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3091 * of the whole object.
3093 * This function returns when the move is complete, including waiting on
3097 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3098 uint64_t offset, uint64_t size)
3100 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3101 uint32_t old_read_domains;
3104 if (offset == 0 && size == obj->size)
3105 return i915_gem_object_set_to_cpu_domain(obj, 0);
3107 ret = i915_gem_object_flush_gpu_write_domain(obj);
3111 /* Wait on any GPU rendering and flushing to occur. */
3112 ret = i915_gem_object_wait_rendering(obj);
3115 i915_gem_object_flush_gtt_write_domain(obj);
3117 /* If we're already fully in the CPU read domain, we're done. */
3118 if (obj_priv->page_cpu_valid == NULL &&
3119 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3122 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3123 * newly adding I915_GEM_DOMAIN_CPU
3125 if (obj_priv->page_cpu_valid == NULL) {
3126 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3128 if (obj_priv->page_cpu_valid == NULL)
3130 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3131 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3133 /* Flush the cache on any pages that are still invalid from the CPU's
3136 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3138 if (obj_priv->page_cpu_valid[i])
3141 drm_clflush_pages(obj_priv->pages + i, 1);
3143 obj_priv->page_cpu_valid[i] = 1;
3146 /* It should now be out of any other write domains, and we can update
3147 * the domain values for our changes.
3149 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3151 old_read_domains = obj->read_domains;
3152 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3154 trace_i915_gem_object_change_domain(obj,
3162 * Pin an object to the GTT and evaluate the relocations landing in it.
3165 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3166 struct drm_file *file_priv,
3167 struct drm_i915_gem_exec_object2 *entry,
3168 struct drm_i915_gem_relocation_entry *relocs)
3170 struct drm_device *dev = obj->dev;
3171 drm_i915_private_t *dev_priv = dev->dev_private;
3172 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3174 void __iomem *reloc_page;
3177 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3178 obj_priv->tiling_mode != I915_TILING_NONE;
3180 /* Check fence reg constraints and rebind if necessary */
3182 !i915_gem_object_fence_offset_ok(obj,
3183 obj_priv->tiling_mode)) {
3184 ret = i915_gem_object_unbind(obj);
3189 /* Choose the GTT offset for our buffer and put it there. */
3190 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3195 * Pre-965 chips need a fence register set up in order to
3196 * properly handle blits to/from tiled surfaces.
3199 ret = i915_gem_object_get_fence_reg(obj);
3201 i915_gem_object_unpin(obj);
3206 entry->offset = obj_priv->gtt_offset;
3208 /* Apply the relocations, using the GTT aperture to avoid cache
3209 * flushing requirements.
3211 for (i = 0; i < entry->relocation_count; i++) {
3212 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3213 struct drm_gem_object *target_obj;
3214 struct drm_i915_gem_object *target_obj_priv;
3215 uint32_t reloc_val, reloc_offset;
3216 uint32_t __iomem *reloc_entry;
3218 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3219 reloc->target_handle);
3220 if (target_obj == NULL) {
3221 i915_gem_object_unpin(obj);
3224 target_obj_priv = to_intel_bo(target_obj);
3227 DRM_INFO("%s: obj %p offset %08x target %d "
3228 "read %08x write %08x gtt %08x "
3229 "presumed %08x delta %08x\n",
3232 (int) reloc->offset,
3233 (int) reloc->target_handle,
3234 (int) reloc->read_domains,
3235 (int) reloc->write_domain,
3236 (int) target_obj_priv->gtt_offset,
3237 (int) reloc->presumed_offset,
3241 /* The target buffer should have appeared before us in the
3242 * exec_object list, so it should have a GTT space bound by now.
3244 if (target_obj_priv->gtt_space == NULL) {
3245 DRM_ERROR("No GTT space found for object %d\n",
3246 reloc->target_handle);
3247 drm_gem_object_unreference(target_obj);
3248 i915_gem_object_unpin(obj);
3252 /* Validate that the target is in a valid r/w GPU domain */
3253 if (reloc->write_domain & (reloc->write_domain - 1)) {
3254 DRM_ERROR("reloc with multiple write domains: "
3255 "obj %p target %d offset %d "
3256 "read %08x write %08x",
3257 obj, reloc->target_handle,
3258 (int) reloc->offset,
3259 reloc->read_domains,
3260 reloc->write_domain);
3263 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3264 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3265 DRM_ERROR("reloc with read/write CPU domains: "
3266 "obj %p target %d offset %d "
3267 "read %08x write %08x",
3268 obj, reloc->target_handle,
3269 (int) reloc->offset,
3270 reloc->read_domains,
3271 reloc->write_domain);
3272 drm_gem_object_unreference(target_obj);
3273 i915_gem_object_unpin(obj);
3276 if (reloc->write_domain && target_obj->pending_write_domain &&
3277 reloc->write_domain != target_obj->pending_write_domain) {
3278 DRM_ERROR("Write domain conflict: "
3279 "obj %p target %d offset %d "
3280 "new %08x old %08x\n",
3281 obj, reloc->target_handle,
3282 (int) reloc->offset,
3283 reloc->write_domain,
3284 target_obj->pending_write_domain);
3285 drm_gem_object_unreference(target_obj);
3286 i915_gem_object_unpin(obj);
3290 target_obj->pending_read_domains |= reloc->read_domains;
3291 target_obj->pending_write_domain |= reloc->write_domain;
3293 /* If the relocation already has the right value in it, no
3294 * more work needs to be done.
3296 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3297 drm_gem_object_unreference(target_obj);
3301 /* Check that the relocation address is valid... */
3302 if (reloc->offset > obj->size - 4) {
3303 DRM_ERROR("Relocation beyond object bounds: "
3304 "obj %p target %d offset %d size %d.\n",
3305 obj, reloc->target_handle,
3306 (int) reloc->offset, (int) obj->size);
3307 drm_gem_object_unreference(target_obj);
3308 i915_gem_object_unpin(obj);
3311 if (reloc->offset & 3) {
3312 DRM_ERROR("Relocation not 4-byte aligned: "
3313 "obj %p target %d offset %d.\n",
3314 obj, reloc->target_handle,
3315 (int) reloc->offset);
3316 drm_gem_object_unreference(target_obj);
3317 i915_gem_object_unpin(obj);
3321 /* and points to somewhere within the target object. */
3322 if (reloc->delta >= target_obj->size) {
3323 DRM_ERROR("Relocation beyond target object bounds: "
3324 "obj %p target %d delta %d size %d.\n",
3325 obj, reloc->target_handle,
3326 (int) reloc->delta, (int) target_obj->size);
3327 drm_gem_object_unreference(target_obj);
3328 i915_gem_object_unpin(obj);
3332 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3334 drm_gem_object_unreference(target_obj);
3335 i915_gem_object_unpin(obj);
3339 /* Map the page containing the relocation we're going to
3342 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3343 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3347 reloc_entry = (uint32_t __iomem *)(reloc_page +
3348 (reloc_offset & (PAGE_SIZE - 1)));
3349 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3352 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3353 obj, (unsigned int) reloc->offset,
3354 readl(reloc_entry), reloc_val);
3356 writel(reloc_val, reloc_entry);
3357 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3359 /* The updated presumed offset for this entry will be
3360 * copied back out to the user.
3362 reloc->presumed_offset = target_obj_priv->gtt_offset;
3364 drm_gem_object_unreference(target_obj);
3369 i915_gem_dump_object(obj, 128, __func__, ~0);
3374 /* Throttle our rendering by waiting until the ring has completed our requests
3375 * emitted over 20 msec ago.
3377 * Note that if we were to use the current jiffies each time around the loop,
3378 * we wouldn't escape the function with any frames outstanding if the time to
3379 * render a frame was over 20ms.
3381 * This should get us reasonable parallelism between CPU and GPU but also
3382 * relatively low latency when blocking on a particular request to finish.
3385 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3387 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3389 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3391 mutex_lock(&dev->struct_mutex);
3392 while (!list_empty(&i915_file_priv->mm.request_list)) {
3393 struct drm_i915_gem_request *request;
3395 request = list_first_entry(&i915_file_priv->mm.request_list,
3396 struct drm_i915_gem_request,
3399 if (time_after_eq(request->emitted_jiffies, recent_enough))
3402 ret = i915_wait_request(dev, request->seqno, request->ring);
3406 mutex_unlock(&dev->struct_mutex);
3412 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3413 uint32_t buffer_count,
3414 struct drm_i915_gem_relocation_entry **relocs)
3416 uint32_t reloc_count = 0, reloc_index = 0, i;
3420 for (i = 0; i < buffer_count; i++) {
3421 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3423 reloc_count += exec_list[i].relocation_count;
3426 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3427 if (*relocs == NULL) {
3428 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3432 for (i = 0; i < buffer_count; i++) {
3433 struct drm_i915_gem_relocation_entry __user *user_relocs;
3435 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3437 ret = copy_from_user(&(*relocs)[reloc_index],
3439 exec_list[i].relocation_count *
3442 drm_free_large(*relocs);
3447 reloc_index += exec_list[i].relocation_count;
3454 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3455 uint32_t buffer_count,
3456 struct drm_i915_gem_relocation_entry *relocs)
3458 uint32_t reloc_count = 0, i;
3464 for (i = 0; i < buffer_count; i++) {
3465 struct drm_i915_gem_relocation_entry __user *user_relocs;
3468 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3470 unwritten = copy_to_user(user_relocs,
3471 &relocs[reloc_count],
3472 exec_list[i].relocation_count *
3480 reloc_count += exec_list[i].relocation_count;
3484 drm_free_large(relocs);
3490 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3491 uint64_t exec_offset)
3493 uint32_t exec_start, exec_len;
3495 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3496 exec_len = (uint32_t) exec->batch_len;
3498 if ((exec_start | exec_len) & 0x7)
3508 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3509 struct drm_gem_object **object_list,
3512 drm_i915_private_t *dev_priv = dev->dev_private;
3513 struct drm_i915_gem_object *obj_priv;
3518 prepare_to_wait(&dev_priv->pending_flip_queue,
3519 &wait, TASK_INTERRUPTIBLE);
3520 for (i = 0; i < count; i++) {
3521 obj_priv = to_intel_bo(object_list[i]);
3522 if (atomic_read(&obj_priv->pending_flip) > 0)
3528 if (!signal_pending(current)) {
3529 mutex_unlock(&dev->struct_mutex);
3531 mutex_lock(&dev->struct_mutex);
3537 finish_wait(&dev_priv->pending_flip_queue, &wait);
3544 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3545 struct drm_file *file_priv,
3546 struct drm_i915_gem_execbuffer2 *args,
3547 struct drm_i915_gem_exec_object2 *exec_list)
3549 drm_i915_private_t *dev_priv = dev->dev_private;
3550 struct drm_gem_object **object_list = NULL;
3551 struct drm_gem_object *batch_obj;
3552 struct drm_i915_gem_object *obj_priv;
3553 struct drm_clip_rect *cliprects = NULL;
3554 struct drm_i915_gem_relocation_entry *relocs = NULL;
3555 int ret = 0, ret2, i, pinned = 0;
3556 uint64_t exec_offset;
3557 uint32_t seqno, flush_domains, reloc_index;
3558 int pin_tries, flips;
3560 struct intel_ring_buffer *ring = NULL;
3563 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3564 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3566 if (args->flags & I915_EXEC_BSD) {
3567 if (!HAS_BSD(dev)) {
3568 DRM_ERROR("execbuf with wrong flag\n");
3571 ring = &dev_priv->bsd_ring;
3573 ring = &dev_priv->render_ring;
3576 if (args->buffer_count < 1) {
3577 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3580 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3581 if (object_list == NULL) {
3582 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3583 args->buffer_count);
3588 if (args->num_cliprects != 0) {
3589 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3591 if (cliprects == NULL) {
3596 ret = copy_from_user(cliprects,
3597 (struct drm_clip_rect __user *)
3598 (uintptr_t) args->cliprects_ptr,
3599 sizeof(*cliprects) * args->num_cliprects);
3601 DRM_ERROR("copy %d cliprects failed: %d\n",
3602 args->num_cliprects, ret);
3608 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3613 mutex_lock(&dev->struct_mutex);
3615 i915_verify_inactive(dev, __FILE__, __LINE__);
3617 if (atomic_read(&dev_priv->mm.wedged)) {
3618 mutex_unlock(&dev->struct_mutex);
3623 if (dev_priv->mm.suspended) {
3624 mutex_unlock(&dev->struct_mutex);
3629 /* Look up object handles */
3631 for (i = 0; i < args->buffer_count; i++) {
3632 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3633 exec_list[i].handle);
3634 if (object_list[i] == NULL) {
3635 DRM_ERROR("Invalid object handle %d at index %d\n",
3636 exec_list[i].handle, i);
3637 /* prevent error path from reading uninitialized data */
3638 args->buffer_count = i + 1;
3643 obj_priv = to_intel_bo(object_list[i]);
3644 if (obj_priv->in_execbuffer) {
3645 DRM_ERROR("Object %p appears more than once in object list\n",
3647 /* prevent error path from reading uninitialized data */
3648 args->buffer_count = i + 1;
3652 obj_priv->in_execbuffer = true;
3653 flips += atomic_read(&obj_priv->pending_flip);
3657 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3658 args->buffer_count);
3663 /* Pin and relocate */
3664 for (pin_tries = 0; ; pin_tries++) {
3668 for (i = 0; i < args->buffer_count; i++) {
3669 object_list[i]->pending_read_domains = 0;
3670 object_list[i]->pending_write_domain = 0;
3671 ret = i915_gem_object_pin_and_relocate(object_list[i],
3674 &relocs[reloc_index]);
3678 reloc_index += exec_list[i].relocation_count;
3684 /* error other than GTT full, or we've already tried again */
3685 if (ret != -ENOSPC || pin_tries >= 1) {
3686 if (ret != -ERESTARTSYS) {
3687 unsigned long long total_size = 0;
3689 for (i = 0; i < args->buffer_count; i++) {
3690 obj_priv = to_intel_bo(object_list[i]);
3692 total_size += object_list[i]->size;
3694 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3695 obj_priv->tiling_mode != I915_TILING_NONE;
3697 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3698 pinned+1, args->buffer_count,
3699 total_size, num_fences,
3701 DRM_ERROR("%d objects [%d pinned], "
3702 "%d object bytes [%d pinned], "
3703 "%d/%d gtt bytes\n",
3704 atomic_read(&dev->object_count),
3705 atomic_read(&dev->pin_count),
3706 atomic_read(&dev->object_memory),
3707 atomic_read(&dev->pin_memory),
3708 atomic_read(&dev->gtt_memory),
3714 /* unpin all of our buffers */
3715 for (i = 0; i < pinned; i++)
3716 i915_gem_object_unpin(object_list[i]);
3719 /* evict everyone we can from the aperture */
3720 ret = i915_gem_evict_everything(dev);
3721 if (ret && ret != -ENOSPC)
3725 /* Set the pending read domains for the batch buffer to COMMAND */
3726 batch_obj = object_list[args->buffer_count-1];
3727 if (batch_obj->pending_write_domain) {
3728 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3732 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3734 /* Sanity check the batch buffer, prior to moving objects */
3735 exec_offset = exec_list[args->buffer_count - 1].offset;
3736 ret = i915_gem_check_execbuffer (args, exec_offset);
3738 DRM_ERROR("execbuf with invalid offset/length\n");
3742 i915_verify_inactive(dev, __FILE__, __LINE__);
3744 /* Zero the global flush/invalidate flags. These
3745 * will be modified as new domains are computed
3748 dev->invalidate_domains = 0;
3749 dev->flush_domains = 0;
3750 dev_priv->flush_rings = 0;
3752 for (i = 0; i < args->buffer_count; i++) {
3753 struct drm_gem_object *obj = object_list[i];
3755 /* Compute new gpu domains and update invalidate/flush */
3756 i915_gem_object_set_to_gpu_domain(obj);
3759 i915_verify_inactive(dev, __FILE__, __LINE__);
3761 if (dev->invalidate_domains | dev->flush_domains) {
3763 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3765 dev->invalidate_domains,
3766 dev->flush_domains);
3769 dev->invalidate_domains,
3770 dev->flush_domains);
3771 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3772 (void)i915_add_request(dev, file_priv,
3774 &dev_priv->render_ring);
3775 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3776 (void)i915_add_request(dev, file_priv,
3778 &dev_priv->bsd_ring);
3781 for (i = 0; i < args->buffer_count; i++) {
3782 struct drm_gem_object *obj = object_list[i];
3783 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3784 uint32_t old_write_domain = obj->write_domain;
3786 obj->write_domain = obj->pending_write_domain;
3787 if (obj->write_domain)
3788 list_move_tail(&obj_priv->gpu_write_list,
3789 &dev_priv->mm.gpu_write_list);
3791 list_del_init(&obj_priv->gpu_write_list);
3793 trace_i915_gem_object_change_domain(obj,
3798 i915_verify_inactive(dev, __FILE__, __LINE__);
3801 for (i = 0; i < args->buffer_count; i++) {
3802 i915_gem_object_check_coherency(object_list[i],
3803 exec_list[i].handle);
3808 i915_gem_dump_object(batch_obj,
3814 /* Exec the batchbuffer */
3815 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3816 cliprects, exec_offset);
3818 DRM_ERROR("dispatch failed %d\n", ret);
3823 * Ensure that the commands in the batch buffer are
3824 * finished before the interrupt fires
3826 flush_domains = i915_retire_commands(dev, ring);
3828 i915_verify_inactive(dev, __FILE__, __LINE__);
3831 * Get a seqno representing the execution of the current buffer,
3832 * which we can wait on. We would like to mitigate these interrupts,
3833 * likely by only creating seqnos occasionally (so that we have
3834 * *some* interrupts representing completion of buffers that we can
3835 * wait on when trying to clear up gtt space).
3837 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3839 for (i = 0; i < args->buffer_count; i++) {
3840 struct drm_gem_object *obj = object_list[i];
3841 obj_priv = to_intel_bo(obj);
3843 i915_gem_object_move_to_active(obj, seqno, ring);
3845 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3849 i915_dump_lru(dev, __func__);
3852 i915_verify_inactive(dev, __FILE__, __LINE__);
3855 for (i = 0; i < pinned; i++)
3856 i915_gem_object_unpin(object_list[i]);
3858 for (i = 0; i < args->buffer_count; i++) {
3859 if (object_list[i]) {
3860 obj_priv = to_intel_bo(object_list[i]);
3861 obj_priv->in_execbuffer = false;
3863 drm_gem_object_unreference(object_list[i]);
3866 mutex_unlock(&dev->struct_mutex);
3869 /* Copy the updated relocations out regardless of current error
3870 * state. Failure to update the relocs would mean that the next
3871 * time userland calls execbuf, it would do so with presumed offset
3872 * state that didn't match the actual object state.
3874 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3877 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3883 drm_free_large(object_list);
3890 * Legacy execbuffer just creates an exec2 list from the original exec object
3891 * list array and passes it to the real function.
3894 i915_gem_execbuffer(struct drm_device *dev, void *data,
3895 struct drm_file *file_priv)
3897 struct drm_i915_gem_execbuffer *args = data;
3898 struct drm_i915_gem_execbuffer2 exec2;
3899 struct drm_i915_gem_exec_object *exec_list = NULL;
3900 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3904 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3905 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3908 if (args->buffer_count < 1) {
3909 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3913 /* Copy in the exec list from userland */
3914 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3915 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3916 if (exec_list == NULL || exec2_list == NULL) {
3917 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3918 args->buffer_count);
3919 drm_free_large(exec_list);
3920 drm_free_large(exec2_list);
3923 ret = copy_from_user(exec_list,
3924 (struct drm_i915_relocation_entry __user *)
3925 (uintptr_t) args->buffers_ptr,
3926 sizeof(*exec_list) * args->buffer_count);
3928 DRM_ERROR("copy %d exec entries failed %d\n",
3929 args->buffer_count, ret);
3930 drm_free_large(exec_list);
3931 drm_free_large(exec2_list);
3935 for (i = 0; i < args->buffer_count; i++) {
3936 exec2_list[i].handle = exec_list[i].handle;
3937 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3938 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3939 exec2_list[i].alignment = exec_list[i].alignment;
3940 exec2_list[i].offset = exec_list[i].offset;
3942 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3944 exec2_list[i].flags = 0;
3947 exec2.buffers_ptr = args->buffers_ptr;
3948 exec2.buffer_count = args->buffer_count;
3949 exec2.batch_start_offset = args->batch_start_offset;
3950 exec2.batch_len = args->batch_len;
3951 exec2.DR1 = args->DR1;
3952 exec2.DR4 = args->DR4;
3953 exec2.num_cliprects = args->num_cliprects;
3954 exec2.cliprects_ptr = args->cliprects_ptr;
3955 exec2.flags = I915_EXEC_RENDER;
3957 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3959 /* Copy the new buffer offsets back to the user's exec list. */
3960 for (i = 0; i < args->buffer_count; i++)
3961 exec_list[i].offset = exec2_list[i].offset;
3962 /* ... and back out to userspace */
3963 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3964 (uintptr_t) args->buffers_ptr,
3966 sizeof(*exec_list) * args->buffer_count);
3969 DRM_ERROR("failed to copy %d exec entries "
3970 "back to user (%d)\n",
3971 args->buffer_count, ret);
3975 drm_free_large(exec_list);
3976 drm_free_large(exec2_list);
3981 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3982 struct drm_file *file_priv)
3984 struct drm_i915_gem_execbuffer2 *args = data;
3985 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3989 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3990 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3993 if (args->buffer_count < 1) {
3994 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3998 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3999 if (exec2_list == NULL) {
4000 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4001 args->buffer_count);
4004 ret = copy_from_user(exec2_list,
4005 (struct drm_i915_relocation_entry __user *)
4006 (uintptr_t) args->buffers_ptr,
4007 sizeof(*exec2_list) * args->buffer_count);
4009 DRM_ERROR("copy %d exec entries failed %d\n",
4010 args->buffer_count, ret);
4011 drm_free_large(exec2_list);
4015 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4017 /* Copy the new buffer offsets back to the user's exec list. */
4018 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4019 (uintptr_t) args->buffers_ptr,
4021 sizeof(*exec2_list) * args->buffer_count);
4024 DRM_ERROR("failed to copy %d exec entries "
4025 "back to user (%d)\n",
4026 args->buffer_count, ret);
4030 drm_free_large(exec2_list);
4035 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4037 struct drm_device *dev = obj->dev;
4038 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4041 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4043 i915_verify_inactive(dev, __FILE__, __LINE__);
4045 if (obj_priv->gtt_space != NULL) {
4047 alignment = i915_gem_get_gtt_alignment(obj);
4048 if (obj_priv->gtt_offset & (alignment - 1)) {
4049 WARN(obj_priv->pin_count,
4050 "bo is already pinned with incorrect alignment:"
4051 " offset=%x, req.alignment=%x\n",
4052 obj_priv->gtt_offset, alignment);
4053 ret = i915_gem_object_unbind(obj);
4059 if (obj_priv->gtt_space == NULL) {
4060 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4065 obj_priv->pin_count++;
4067 /* If the object is not active and not pending a flush,
4068 * remove it from the inactive list
4070 if (obj_priv->pin_count == 1) {
4071 atomic_inc(&dev->pin_count);
4072 atomic_add(obj->size, &dev->pin_memory);
4073 if (!obj_priv->active &&
4074 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4075 list_del_init(&obj_priv->list);
4077 i915_verify_inactive(dev, __FILE__, __LINE__);
4083 i915_gem_object_unpin(struct drm_gem_object *obj)
4085 struct drm_device *dev = obj->dev;
4086 drm_i915_private_t *dev_priv = dev->dev_private;
4087 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4089 i915_verify_inactive(dev, __FILE__, __LINE__);
4090 obj_priv->pin_count--;
4091 BUG_ON(obj_priv->pin_count < 0);
4092 BUG_ON(obj_priv->gtt_space == NULL);
4094 /* If the object is no longer pinned, and is
4095 * neither active nor being flushed, then stick it on
4098 if (obj_priv->pin_count == 0) {
4099 if (!obj_priv->active &&
4100 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4101 list_move_tail(&obj_priv->list,
4102 &dev_priv->mm.inactive_list);
4103 atomic_dec(&dev->pin_count);
4104 atomic_sub(obj->size, &dev->pin_memory);
4106 i915_verify_inactive(dev, __FILE__, __LINE__);
4110 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4111 struct drm_file *file_priv)
4113 struct drm_i915_gem_pin *args = data;
4114 struct drm_gem_object *obj;
4115 struct drm_i915_gem_object *obj_priv;
4118 mutex_lock(&dev->struct_mutex);
4120 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4122 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4124 mutex_unlock(&dev->struct_mutex);
4127 obj_priv = to_intel_bo(obj);
4129 if (obj_priv->madv != I915_MADV_WILLNEED) {
4130 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4131 drm_gem_object_unreference(obj);
4132 mutex_unlock(&dev->struct_mutex);
4136 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4137 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4139 drm_gem_object_unreference(obj);
4140 mutex_unlock(&dev->struct_mutex);
4144 obj_priv->user_pin_count++;
4145 obj_priv->pin_filp = file_priv;
4146 if (obj_priv->user_pin_count == 1) {
4147 ret = i915_gem_object_pin(obj, args->alignment);
4149 drm_gem_object_unreference(obj);
4150 mutex_unlock(&dev->struct_mutex);
4155 /* XXX - flush the CPU caches for pinned objects
4156 * as the X server doesn't manage domains yet
4158 i915_gem_object_flush_cpu_write_domain(obj);
4159 args->offset = obj_priv->gtt_offset;
4160 drm_gem_object_unreference(obj);
4161 mutex_unlock(&dev->struct_mutex);
4167 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4168 struct drm_file *file_priv)
4170 struct drm_i915_gem_pin *args = data;
4171 struct drm_gem_object *obj;
4172 struct drm_i915_gem_object *obj_priv;
4174 mutex_lock(&dev->struct_mutex);
4176 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4178 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4180 mutex_unlock(&dev->struct_mutex);
4184 obj_priv = to_intel_bo(obj);
4185 if (obj_priv->pin_filp != file_priv) {
4186 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4188 drm_gem_object_unreference(obj);
4189 mutex_unlock(&dev->struct_mutex);
4192 obj_priv->user_pin_count--;
4193 if (obj_priv->user_pin_count == 0) {
4194 obj_priv->pin_filp = NULL;
4195 i915_gem_object_unpin(obj);
4198 drm_gem_object_unreference(obj);
4199 mutex_unlock(&dev->struct_mutex);
4204 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4205 struct drm_file *file_priv)
4207 struct drm_i915_gem_busy *args = data;
4208 struct drm_gem_object *obj;
4209 struct drm_i915_gem_object *obj_priv;
4211 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4213 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4218 mutex_lock(&dev->struct_mutex);
4220 /* Count all active objects as busy, even if they are currently not used
4221 * by the gpu. Users of this interface expect objects to eventually
4222 * become non-busy without any further actions, therefore emit any
4223 * necessary flushes here.
4225 obj_priv = to_intel_bo(obj);
4226 args->busy = obj_priv->active;
4228 /* Unconditionally flush objects, even when the gpu still uses this
4229 * object. Userspace calling this function indicates that it wants to
4230 * use this buffer rather sooner than later, so issuing the required
4231 * flush earlier is beneficial.
4233 if (obj->write_domain) {
4234 i915_gem_flush(dev, 0, obj->write_domain);
4235 (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4238 /* Update the active list for the hardware's current position.
4239 * Otherwise this only updates on a delayed timer or when irqs
4240 * are actually unmasked, and our working set ends up being
4241 * larger than required.
4243 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4245 args->busy = obj_priv->active;
4248 drm_gem_object_unreference(obj);
4249 mutex_unlock(&dev->struct_mutex);
4254 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4255 struct drm_file *file_priv)
4257 return i915_gem_ring_throttle(dev, file_priv);
4261 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4262 struct drm_file *file_priv)
4264 struct drm_i915_gem_madvise *args = data;
4265 struct drm_gem_object *obj;
4266 struct drm_i915_gem_object *obj_priv;
4268 switch (args->madv) {
4269 case I915_MADV_DONTNEED:
4270 case I915_MADV_WILLNEED:
4276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4278 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4283 mutex_lock(&dev->struct_mutex);
4284 obj_priv = to_intel_bo(obj);
4286 if (obj_priv->pin_count) {
4287 drm_gem_object_unreference(obj);
4288 mutex_unlock(&dev->struct_mutex);
4290 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4294 if (obj_priv->madv != __I915_MADV_PURGED)
4295 obj_priv->madv = args->madv;
4297 /* if the object is no longer bound, discard its backing storage */
4298 if (i915_gem_object_is_purgeable(obj_priv) &&
4299 obj_priv->gtt_space == NULL)
4300 i915_gem_object_truncate(obj);
4302 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4304 drm_gem_object_unreference(obj);
4305 mutex_unlock(&dev->struct_mutex);
4310 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4313 struct drm_i915_gem_object *obj;
4315 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4319 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4324 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4325 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4327 obj->agp_type = AGP_USER_MEMORY;
4328 obj->base.driver_private = NULL;
4329 obj->fence_reg = I915_FENCE_REG_NONE;
4330 INIT_LIST_HEAD(&obj->list);
4331 INIT_LIST_HEAD(&obj->gpu_write_list);
4332 obj->madv = I915_MADV_WILLNEED;
4334 trace_i915_gem_object_create(&obj->base);
4339 int i915_gem_init_object(struct drm_gem_object *obj)
4346 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4348 struct drm_device *dev = obj->dev;
4349 drm_i915_private_t *dev_priv = dev->dev_private;
4350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4353 ret = i915_gem_object_unbind(obj);
4354 if (ret == -ERESTARTSYS) {
4355 list_move(&obj_priv->list,
4356 &dev_priv->mm.deferred_free_list);
4360 if (obj_priv->mmap_offset)
4361 i915_gem_free_mmap_offset(obj);
4363 drm_gem_object_release(obj);
4365 kfree(obj_priv->page_cpu_valid);
4366 kfree(obj_priv->bit_17);
4370 void i915_gem_free_object(struct drm_gem_object *obj)
4372 struct drm_device *dev = obj->dev;
4373 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4375 trace_i915_gem_object_destroy(obj);
4377 while (obj_priv->pin_count > 0)
4378 i915_gem_object_unpin(obj);
4380 if (obj_priv->phys_obj)
4381 i915_gem_detach_phys_object(dev, obj);
4383 i915_gem_free_object_tail(obj);
4387 i915_gem_idle(struct drm_device *dev)
4389 drm_i915_private_t *dev_priv = dev->dev_private;
4392 mutex_lock(&dev->struct_mutex);
4394 if (dev_priv->mm.suspended ||
4395 (dev_priv->render_ring.gem_object == NULL) ||
4397 dev_priv->bsd_ring.gem_object == NULL)) {
4398 mutex_unlock(&dev->struct_mutex);
4402 ret = i915_gpu_idle(dev);
4404 mutex_unlock(&dev->struct_mutex);
4408 /* Under UMS, be paranoid and evict. */
4409 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4410 ret = i915_gem_evict_inactive(dev);
4412 mutex_unlock(&dev->struct_mutex);
4417 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4418 * We need to replace this with a semaphore, or something.
4419 * And not confound mm.suspended!
4421 dev_priv->mm.suspended = 1;
4422 del_timer(&dev_priv->hangcheck_timer);
4424 i915_kernel_lost_context(dev);
4425 i915_gem_cleanup_ringbuffer(dev);
4427 mutex_unlock(&dev->struct_mutex);
4429 /* Cancel the retire work handler, which should be idle now. */
4430 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4436 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4437 * over cache flushing.
4440 i915_gem_init_pipe_control(struct drm_device *dev)
4442 drm_i915_private_t *dev_priv = dev->dev_private;
4443 struct drm_gem_object *obj;
4444 struct drm_i915_gem_object *obj_priv;
4447 obj = i915_gem_alloc_object(dev, 4096);
4449 DRM_ERROR("Failed to allocate seqno page\n");
4453 obj_priv = to_intel_bo(obj);
4454 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4456 ret = i915_gem_object_pin(obj, 4096);
4460 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4461 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4462 if (dev_priv->seqno_page == NULL)
4465 dev_priv->seqno_obj = obj;
4466 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4471 i915_gem_object_unpin(obj);
4473 drm_gem_object_unreference(obj);
4480 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4482 drm_i915_private_t *dev_priv = dev->dev_private;
4483 struct drm_gem_object *obj;
4484 struct drm_i915_gem_object *obj_priv;
4486 obj = dev_priv->seqno_obj;
4487 obj_priv = to_intel_bo(obj);
4488 kunmap(obj_priv->pages[0]);
4489 i915_gem_object_unpin(obj);
4490 drm_gem_object_unreference(obj);
4491 dev_priv->seqno_obj = NULL;
4493 dev_priv->seqno_page = NULL;
4497 i915_gem_init_ringbuffer(struct drm_device *dev)
4499 drm_i915_private_t *dev_priv = dev->dev_private;
4502 dev_priv->render_ring = render_ring;
4504 if (!I915_NEED_GFX_HWS(dev)) {
4505 dev_priv->render_ring.status_page.page_addr
4506 = dev_priv->status_page_dmah->vaddr;
4507 memset(dev_priv->render_ring.status_page.page_addr,
4511 if (HAS_PIPE_CONTROL(dev)) {
4512 ret = i915_gem_init_pipe_control(dev);
4517 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4519 goto cleanup_pipe_control;
4522 dev_priv->bsd_ring = bsd_ring;
4523 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4525 goto cleanup_render_ring;
4528 dev_priv->next_seqno = 1;
4532 cleanup_render_ring:
4533 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4534 cleanup_pipe_control:
4535 if (HAS_PIPE_CONTROL(dev))
4536 i915_gem_cleanup_pipe_control(dev);
4541 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4543 drm_i915_private_t *dev_priv = dev->dev_private;
4545 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4547 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4548 if (HAS_PIPE_CONTROL(dev))
4549 i915_gem_cleanup_pipe_control(dev);
4553 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4554 struct drm_file *file_priv)
4556 drm_i915_private_t *dev_priv = dev->dev_private;
4559 if (drm_core_check_feature(dev, DRIVER_MODESET))
4562 if (atomic_read(&dev_priv->mm.wedged)) {
4563 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4564 atomic_set(&dev_priv->mm.wedged, 0);
4567 mutex_lock(&dev->struct_mutex);
4568 dev_priv->mm.suspended = 0;
4570 ret = i915_gem_init_ringbuffer(dev);
4572 mutex_unlock(&dev->struct_mutex);
4576 spin_lock(&dev_priv->mm.active_list_lock);
4577 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4578 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4579 spin_unlock(&dev_priv->mm.active_list_lock);
4581 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4582 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4583 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4584 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4585 mutex_unlock(&dev->struct_mutex);
4587 ret = drm_irq_install(dev);
4589 goto cleanup_ringbuffer;
4594 mutex_lock(&dev->struct_mutex);
4595 i915_gem_cleanup_ringbuffer(dev);
4596 dev_priv->mm.suspended = 1;
4597 mutex_unlock(&dev->struct_mutex);
4603 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4604 struct drm_file *file_priv)
4606 if (drm_core_check_feature(dev, DRIVER_MODESET))
4609 drm_irq_uninstall(dev);
4610 return i915_gem_idle(dev);
4614 i915_gem_lastclose(struct drm_device *dev)
4618 if (drm_core_check_feature(dev, DRIVER_MODESET))
4621 ret = i915_gem_idle(dev);
4623 DRM_ERROR("failed to idle hardware: %d\n", ret);
4627 i915_gem_load(struct drm_device *dev)
4630 drm_i915_private_t *dev_priv = dev->dev_private;
4632 spin_lock_init(&dev_priv->mm.active_list_lock);
4633 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4634 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4635 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4636 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4637 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4638 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4639 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4641 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4642 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4644 for (i = 0; i < 16; i++)
4645 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4646 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4647 i915_gem_retire_work_handler);
4648 spin_lock(&shrink_list_lock);
4649 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4650 spin_unlock(&shrink_list_lock);
4652 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4654 u32 tmp = I915_READ(MI_ARB_STATE);
4655 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4656 /* arb state is a masked write, so set bit + bit in mask */
4657 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4658 I915_WRITE(MI_ARB_STATE, tmp);
4662 /* Old X drivers will take 0-2 for front, back, depth buffers */
4663 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4664 dev_priv->fence_reg_start = 3;
4666 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4667 dev_priv->num_fence_regs = 16;
4669 dev_priv->num_fence_regs = 8;
4671 /* Initialize fence registers to zero */
4672 if (IS_I965G(dev)) {
4673 for (i = 0; i < 16; i++)
4674 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4676 for (i = 0; i < 8; i++)
4677 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4678 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4679 for (i = 0; i < 8; i++)
4680 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4682 i915_gem_detect_bit_6_swizzle(dev);
4683 init_waitqueue_head(&dev_priv->pending_flip_queue);
4687 * Create a physically contiguous memory object for this object
4688 * e.g. for cursor + overlay regs
4690 int i915_gem_init_phys_object(struct drm_device *dev,
4691 int id, int size, int align)
4693 drm_i915_private_t *dev_priv = dev->dev_private;
4694 struct drm_i915_gem_phys_object *phys_obj;
4697 if (dev_priv->mm.phys_objs[id - 1] || !size)
4700 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4706 phys_obj->handle = drm_pci_alloc(dev, size, align);
4707 if (!phys_obj->handle) {
4712 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4715 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4723 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4725 drm_i915_private_t *dev_priv = dev->dev_private;
4726 struct drm_i915_gem_phys_object *phys_obj;
4728 if (!dev_priv->mm.phys_objs[id - 1])
4731 phys_obj = dev_priv->mm.phys_objs[id - 1];
4732 if (phys_obj->cur_obj) {
4733 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4737 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4739 drm_pci_free(dev, phys_obj->handle);
4741 dev_priv->mm.phys_objs[id - 1] = NULL;
4744 void i915_gem_free_all_phys_object(struct drm_device *dev)
4748 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4749 i915_gem_free_phys_object(dev, i);
4752 void i915_gem_detach_phys_object(struct drm_device *dev,
4753 struct drm_gem_object *obj)
4755 struct drm_i915_gem_object *obj_priv;
4760 obj_priv = to_intel_bo(obj);
4761 if (!obj_priv->phys_obj)
4764 ret = i915_gem_object_get_pages(obj, 0);
4768 page_count = obj->size / PAGE_SIZE;
4770 for (i = 0; i < page_count; i++) {
4771 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4772 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4774 memcpy(dst, src, PAGE_SIZE);
4775 kunmap_atomic(dst, KM_USER0);
4777 drm_clflush_pages(obj_priv->pages, page_count);
4778 drm_agp_chipset_flush(dev);
4780 i915_gem_object_put_pages(obj);
4782 obj_priv->phys_obj->cur_obj = NULL;
4783 obj_priv->phys_obj = NULL;
4787 i915_gem_attach_phys_object(struct drm_device *dev,
4788 struct drm_gem_object *obj,
4792 drm_i915_private_t *dev_priv = dev->dev_private;
4793 struct drm_i915_gem_object *obj_priv;
4798 if (id > I915_MAX_PHYS_OBJECT)
4801 obj_priv = to_intel_bo(obj);
4803 if (obj_priv->phys_obj) {
4804 if (obj_priv->phys_obj->id == id)
4806 i915_gem_detach_phys_object(dev, obj);
4809 /* create a new object */
4810 if (!dev_priv->mm.phys_objs[id - 1]) {
4811 ret = i915_gem_init_phys_object(dev, id,
4814 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4819 /* bind to the object */
4820 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4821 obj_priv->phys_obj->cur_obj = obj;
4823 ret = i915_gem_object_get_pages(obj, 0);
4825 DRM_ERROR("failed to get page list\n");
4829 page_count = obj->size / PAGE_SIZE;
4831 for (i = 0; i < page_count; i++) {
4832 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4833 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4835 memcpy(dst, src, PAGE_SIZE);
4836 kunmap_atomic(src, KM_USER0);
4839 i915_gem_object_put_pages(obj);
4847 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4848 struct drm_i915_gem_pwrite *args,
4849 struct drm_file *file_priv)
4851 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4854 char __user *user_data;
4856 user_data = (char __user *) (uintptr_t) args->data_ptr;
4857 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4859 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4860 ret = copy_from_user(obj_addr, user_data, args->size);
4864 drm_agp_chipset_flush(dev);
4868 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4870 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4872 /* Clean up our request list when the client is going away, so that
4873 * later retire_requests won't dereference our soon-to-be-gone
4876 mutex_lock(&dev->struct_mutex);
4877 while (!list_empty(&i915_file_priv->mm.request_list))
4878 list_del_init(i915_file_priv->mm.request_list.next);
4879 mutex_unlock(&dev->struct_mutex);
4883 i915_gpu_is_active(struct drm_device *dev)
4885 drm_i915_private_t *dev_priv = dev->dev_private;
4888 spin_lock(&dev_priv->mm.active_list_lock);
4889 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4890 list_empty(&dev_priv->render_ring.active_list);
4892 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4893 spin_unlock(&dev_priv->mm.active_list_lock);
4895 return !lists_empty;
4899 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4901 drm_i915_private_t *dev_priv, *next_dev;
4902 struct drm_i915_gem_object *obj_priv, *next_obj;
4904 int would_deadlock = 1;
4906 /* "fast-path" to count number of available objects */
4907 if (nr_to_scan == 0) {
4908 spin_lock(&shrink_list_lock);
4909 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4910 struct drm_device *dev = dev_priv->dev;
4912 if (mutex_trylock(&dev->struct_mutex)) {
4913 list_for_each_entry(obj_priv,
4914 &dev_priv->mm.inactive_list,
4917 mutex_unlock(&dev->struct_mutex);
4920 spin_unlock(&shrink_list_lock);
4922 return (cnt / 100) * sysctl_vfs_cache_pressure;
4925 spin_lock(&shrink_list_lock);
4928 /* first scan for clean buffers */
4929 list_for_each_entry_safe(dev_priv, next_dev,
4930 &shrink_list, mm.shrink_list) {
4931 struct drm_device *dev = dev_priv->dev;
4933 if (! mutex_trylock(&dev->struct_mutex))
4936 spin_unlock(&shrink_list_lock);
4937 i915_gem_retire_requests(dev);
4939 list_for_each_entry_safe(obj_priv, next_obj,
4940 &dev_priv->mm.inactive_list,
4942 if (i915_gem_object_is_purgeable(obj_priv)) {
4943 i915_gem_object_unbind(&obj_priv->base);
4944 if (--nr_to_scan <= 0)
4949 spin_lock(&shrink_list_lock);
4950 mutex_unlock(&dev->struct_mutex);
4954 if (nr_to_scan <= 0)
4958 /* second pass, evict/count anything still on the inactive list */
4959 list_for_each_entry_safe(dev_priv, next_dev,
4960 &shrink_list, mm.shrink_list) {
4961 struct drm_device *dev = dev_priv->dev;
4963 if (! mutex_trylock(&dev->struct_mutex))
4966 spin_unlock(&shrink_list_lock);
4968 list_for_each_entry_safe(obj_priv, next_obj,
4969 &dev_priv->mm.inactive_list,
4971 if (nr_to_scan > 0) {
4972 i915_gem_object_unbind(&obj_priv->base);
4978 spin_lock(&shrink_list_lock);
4979 mutex_unlock(&dev->struct_mutex);
4988 * We are desperate for pages, so as a last resort, wait
4989 * for the GPU to finish and discard whatever we can.
4990 * This has a dramatic impact to reduce the number of
4991 * OOM-killer events whilst running the GPU aggressively.
4993 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4994 struct drm_device *dev = dev_priv->dev;
4996 if (!mutex_trylock(&dev->struct_mutex))
4999 spin_unlock(&shrink_list_lock);
5001 if (i915_gpu_is_active(dev)) {
5006 spin_lock(&shrink_list_lock);
5007 mutex_unlock(&dev->struct_mutex);
5014 spin_unlock(&shrink_list_lock);
5019 return (cnt / 100) * sysctl_vfs_cache_pressure;
5024 static struct shrinker shrinker = {
5025 .shrink = i915_gem_shrink,
5026 .seeks = DEFAULT_SEEKS,
5030 i915_gem_shrinker_init(void)
5032 register_shrinker(&shrinker);
5036 i915_gem_shrinker_exit(void)
5038 unregister_shrinker(&shrinker);