2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
92 /* This is a HW constraint. The value below is the largest known requirement
93 * I've seen in a spec to date, and that was a workaround for a non-shipping
94 * part. It should be safe to decrease this, but it's more future proof as is.
96 #define GEN6_CONTEXT_ALIGN (64<<10)
97 #define GEN7_CONTEXT_ALIGN 4096
99 static int do_switch(struct intel_ring_buffer *ring,
100 struct i915_hw_context *to);
102 static void ppgtt_release(struct kref *kref)
104 struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref);
105 struct drm_device *dev = ppgtt->base.dev;
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 struct i915_address_space *vm = &ppgtt->base;
109 if (ppgtt == dev_priv->mm.aliasing_ppgtt ||
110 (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {
111 ppgtt->base.cleanup(&ppgtt->base);
116 * Make sure vmas are unbound before we take down the drm_mm
118 * FIXME: Proper refcounting should take care of this, this shouldn't be
121 if (!list_empty(&vm->active_list)) {
122 struct i915_vma *vma;
124 list_for_each_entry(vma, &vm->active_list, mm_list)
125 if (WARN_ON(list_empty(&vma->vma_link) ||
126 list_is_singular(&vma->vma_link)))
129 i915_gem_evict_vm(&ppgtt->base, true);
131 i915_gem_retire_requests(dev);
132 i915_gem_evict_vm(&ppgtt->base, false);
135 ppgtt->base.cleanup(&ppgtt->base);
138 static size_t get_context_alignment(struct drm_device *dev)
141 return GEN6_CONTEXT_ALIGN;
143 return GEN7_CONTEXT_ALIGN;
146 static int get_context_size(struct drm_device *dev)
148 struct drm_i915_private *dev_priv = dev->dev_private;
152 switch (INTEL_INFO(dev)->gen) {
154 reg = I915_READ(CXT_SIZE);
155 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
158 reg = I915_READ(GEN7_CXT_SIZE);
160 ret = HSW_CXT_TOTAL_SIZE;
162 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
165 ret = GEN8_CXT_TOTAL_SIZE;
174 void i915_gem_context_free(struct kref *ctx_ref)
176 struct i915_hw_context *ctx = container_of(ctx_ref,
178 struct i915_hw_ppgtt *ppgtt = NULL;
180 /* We refcount even the aliasing PPGTT to keep the code symmetric */
181 if (USES_PPGTT(ctx->obj->base.dev))
182 ppgtt = ctx_to_ppgtt(ctx);
184 /* XXX: Free up the object before tearing down the address space, in
185 * case we're bound in the PPGTT */
186 drm_gem_object_unreference(&ctx->obj->base);
189 kref_put(&ppgtt->ref, ppgtt_release);
190 list_del(&ctx->link);
194 static struct i915_hw_ppgtt *
195 create_vm_for_ctx(struct drm_device *dev, struct i915_hw_context *ctx)
197 struct i915_hw_ppgtt *ppgtt;
200 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
202 return ERR_PTR(-ENOMEM);
204 ret = i915_gem_init_ppgtt(dev, ppgtt);
213 static struct i915_hw_context *
214 __create_hw_context(struct drm_device *dev,
215 struct drm_i915_file_private *file_priv)
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct i915_hw_context *ctx;
221 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
223 return ERR_PTR(-ENOMEM);
225 kref_init(&ctx->ref);
226 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
227 INIT_LIST_HEAD(&ctx->link);
228 if (ctx->obj == NULL) {
230 DRM_DEBUG_DRIVER("Context object allocated failed\n");
231 return ERR_PTR(-ENOMEM);
234 if (INTEL_INFO(dev)->gen >= 7) {
235 ret = i915_gem_object_set_cache_level(ctx->obj,
237 /* Failure shouldn't ever happen this early */
242 list_add_tail(&ctx->link, &dev_priv->context_list);
244 /* Default context will never have a file_priv */
245 if (file_priv == NULL)
248 ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID, 0,
253 ctx->file_priv = file_priv;
255 /* NB: Mark all slices as needing a remap so that when the context first
256 * loads it will restore whatever remap state already exists. If there
257 * is no remap info, it will be a NOP. */
258 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
263 i915_gem_context_unreference(ctx);
268 * The default context needs to exist per ring that uses contexts. It stores the
269 * context state of the GPU for applications that don't utilize HW contexts, as
270 * well as an idle case.
272 static struct i915_hw_context *
273 i915_gem_create_context(struct drm_device *dev,
274 struct drm_i915_file_private *file_priv,
277 const bool is_global_default_ctx = file_priv == NULL;
278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct i915_hw_context *ctx;
282 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
284 ctx = __create_hw_context(dev, file_priv);
288 if (is_global_default_ctx) {
289 /* We may need to do things with the shrinker which
290 * require us to immediately switch back to the default
291 * context. This can cause a problem as pinning the
292 * default context also requires GTT space which may not
293 * be available. To avoid this we always pin the default
296 ret = i915_gem_obj_ggtt_pin(ctx->obj,
297 get_context_alignment(dev), 0);
299 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
305 struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx);
307 if (IS_ERR_OR_NULL(ppgtt)) {
308 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
310 ret = PTR_ERR(ppgtt);
313 ctx->vm = &ppgtt->base;
315 /* This case is reserved for the global default context and
316 * should only happen once. */
317 if (is_global_default_ctx) {
318 if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) {
323 dev_priv->mm.aliasing_ppgtt = ppgtt;
325 } else if (USES_PPGTT(dev)) {
326 /* For platforms which only have aliasing PPGTT, we fake the
327 * address space and refcounting. */
328 ctx->vm = &dev_priv->mm.aliasing_ppgtt->base;
329 kref_get(&dev_priv->mm.aliasing_ppgtt->ref);
331 ctx->vm = &dev_priv->gtt.base;
336 if (is_global_default_ctx)
337 i915_gem_object_ggtt_unpin(ctx->obj);
339 i915_gem_context_unreference(ctx);
343 void i915_gem_context_reset(struct drm_device *dev)
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 struct intel_ring_buffer *ring;
349 if (!HAS_HW_CONTEXTS(dev))
352 /* Prevent the hardware from restoring the last context (which hung) on
354 for (i = 0; i < I915_NUM_RINGS; i++) {
355 struct i915_hw_context *dctx;
356 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
359 /* Do a fake switch to the default context */
360 ring = &dev_priv->ring[i];
361 dctx = ring->default_context;
365 if (!ring->last_context)
368 if (ring->last_context == dctx)
372 WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj,
373 get_context_alignment(dev), 0));
374 /* Fake a finish/inactive */
375 dctx->obj->base.write_domain = 0;
376 dctx->obj->active = 0;
379 i915_gem_context_unreference(ring->last_context);
380 i915_gem_context_reference(dctx);
381 ring->last_context = dctx;
385 int i915_gem_context_init(struct drm_device *dev)
387 struct drm_i915_private *dev_priv = dev->dev_private;
388 struct intel_ring_buffer *ring;
391 if (!HAS_HW_CONTEXTS(dev))
394 /* Init should only be called once per module load. Eventually the
395 * restriction on the context_disabled check can be loosened. */
396 if (WARN_ON(dev_priv->ring[RCS].default_context))
399 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
401 if (dev_priv->hw_context_size > (1<<20)) {
402 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
406 dev_priv->ring[RCS].default_context =
407 i915_gem_create_context(dev, NULL, USES_PPGTT(dev));
409 if (IS_ERR_OR_NULL(dev_priv->ring[RCS].default_context)) {
410 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %ld\n",
411 PTR_ERR(dev_priv->ring[RCS].default_context));
412 return PTR_ERR(dev_priv->ring[RCS].default_context);
415 for (i = RCS + 1; i < I915_NUM_RINGS; i++) {
416 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
419 ring = &dev_priv->ring[i];
421 /* NB: RCS will hold a ref for all rings */
422 ring->default_context = dev_priv->ring[RCS].default_context;
425 DRM_DEBUG_DRIVER("HW context support initialized\n");
429 void i915_gem_context_fini(struct drm_device *dev)
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
435 if (!HAS_HW_CONTEXTS(dev))
438 /* The only known way to stop the gpu from accessing the hw context is
439 * to reset it. Do this as the very last operation to avoid confusing
440 * other code, leading to spurious errors. */
441 intel_gpu_reset(dev);
443 /* When default context is created and switched to, base object refcount
444 * will be 2 (+1 from object creation and +1 from do_switch()).
445 * i915_gem_context_fini() will be called after gpu_idle() has switched
446 * to default context. So we need to unreference the base object once
447 * to offset the do_switch part, so that i915_gem_context_unreference()
448 * can then free the base object correctly. */
449 WARN_ON(!dev_priv->ring[RCS].last_context);
450 if (dev_priv->ring[RCS].last_context == dctx) {
451 /* Fake switch to NULL context */
452 WARN_ON(dctx->obj->active);
453 i915_gem_object_ggtt_unpin(dctx->obj);
454 i915_gem_context_unreference(dctx);
455 dev_priv->ring[RCS].last_context = NULL;
458 for (i = 0; i < I915_NUM_RINGS; i++) {
459 struct intel_ring_buffer *ring = &dev_priv->ring[i];
460 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
463 if (ring->last_context)
464 i915_gem_context_unreference(ring->last_context);
466 ring->default_context = NULL;
467 ring->last_context = NULL;
470 i915_gem_object_ggtt_unpin(dctx->obj);
471 i915_gem_context_unreference(dctx);
472 dev_priv->mm.aliasing_ppgtt = NULL;
475 int i915_gem_context_enable(struct drm_i915_private *dev_priv)
477 struct intel_ring_buffer *ring;
480 if (!HAS_HW_CONTEXTS(dev_priv->dev))
483 /* This is the only place the aliasing PPGTT gets enabled, which means
484 * it has to happen before we bail on reset */
485 if (dev_priv->mm.aliasing_ppgtt) {
486 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
487 ppgtt->enable(ppgtt);
490 /* FIXME: We should make this work, even in reset */
491 if (i915_reset_in_progress(&dev_priv->gpu_error))
494 BUG_ON(!dev_priv->ring[RCS].default_context);
496 for_each_ring(ring, dev_priv, i) {
497 ret = do_switch(ring, ring->default_context);
505 static int context_idr_cleanup(int id, void *p, void *data)
507 struct i915_hw_context *ctx = p;
509 /* Ignore the default context because close will handle it */
510 if (i915_gem_context_is_default(ctx))
513 i915_gem_context_unreference(ctx);
517 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
519 struct drm_i915_file_private *file_priv = file->driver_priv;
520 struct drm_i915_private *dev_priv = dev->dev_private;
522 if (!HAS_HW_CONTEXTS(dev)) {
523 /* Cheat for hang stats */
524 file_priv->private_default_ctx =
525 kzalloc(sizeof(struct i915_hw_context), GFP_KERNEL);
527 if (file_priv->private_default_ctx == NULL)
530 file_priv->private_default_ctx->vm = &dev_priv->gtt.base;
534 idr_init(&file_priv->context_idr);
536 mutex_lock(&dev->struct_mutex);
537 file_priv->private_default_ctx =
538 i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev));
539 mutex_unlock(&dev->struct_mutex);
541 if (IS_ERR(file_priv->private_default_ctx)) {
542 idr_destroy(&file_priv->context_idr);
543 return PTR_ERR(file_priv->private_default_ctx);
549 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
551 struct drm_i915_file_private *file_priv = file->driver_priv;
553 if (!HAS_HW_CONTEXTS(dev)) {
554 kfree(file_priv->private_default_ctx);
558 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
559 i915_gem_context_unreference(file_priv->private_default_ctx);
560 idr_destroy(&file_priv->context_idr);
563 struct i915_hw_context *
564 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
566 struct i915_hw_context *ctx;
568 if (!HAS_HW_CONTEXTS(file_priv->dev_priv->dev))
569 return file_priv->private_default_ctx;
571 ctx = (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
573 return ERR_PTR(-ENOENT);
579 mi_set_context(struct intel_ring_buffer *ring,
580 struct i915_hw_context *new_context,
585 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
586 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
587 * explicitly, so we rely on the value at ring init, stored in
588 * itlb_before_ctx_switch.
590 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
591 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
596 ret = intel_ring_begin(ring, 6);
600 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
601 if (IS_GEN7(ring->dev))
602 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
604 intel_ring_emit(ring, MI_NOOP);
606 intel_ring_emit(ring, MI_NOOP);
607 intel_ring_emit(ring, MI_SET_CONTEXT);
608 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
610 MI_SAVE_EXT_STATE_EN |
611 MI_RESTORE_EXT_STATE_EN |
614 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
615 * WaMiSetContext_Hang:snb,ivb,vlv
617 intel_ring_emit(ring, MI_NOOP);
619 if (IS_GEN7(ring->dev))
620 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
622 intel_ring_emit(ring, MI_NOOP);
624 intel_ring_advance(ring);
629 static int do_switch(struct intel_ring_buffer *ring,
630 struct i915_hw_context *to)
632 struct drm_i915_private *dev_priv = ring->dev->dev_private;
633 struct i915_hw_context *from = ring->last_context;
634 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to);
638 if (from != NULL && ring == &dev_priv->ring[RCS]) {
639 BUG_ON(from->obj == NULL);
640 BUG_ON(!i915_gem_obj_is_pinned(from->obj));
643 if (from == to && from->last_ring == ring && !to->remap_slice)
646 /* Trying to pin first makes error handling easier. */
647 if (ring == &dev_priv->ring[RCS]) {
648 ret = i915_gem_obj_ggtt_pin(to->obj,
649 get_context_alignment(ring->dev), 0);
655 * Pin can switch back to the default context if we end up calling into
656 * evict_everything - as a last ditch gtt defrag effort that also
657 * switches to the default context. Hence we need to reload from here.
659 from = ring->last_context;
661 if (USES_FULL_PPGTT(ring->dev)) {
662 ret = ppgtt->switch_mm(ppgtt, ring, false);
667 if (ring != &dev_priv->ring[RCS]) {
669 i915_gem_context_unreference(from);
674 * Clear this page out of any CPU caches for coherent swap-in/out. Note
675 * that thanks to write = false in this call and us not setting any gpu
676 * write domains when putting a context object onto the active list
677 * (when switching away from it), this won't block.
679 * XXX: We need a real interface to do this instead of trickery.
681 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
685 if (!to->obj->has_global_gtt_mapping) {
686 struct i915_vma *vma = i915_gem_obj_to_vma(to->obj,
687 &dev_priv->gtt.base);
688 vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND);
691 if (!to->is_initialized || i915_gem_context_is_default(to))
692 hw_flags |= MI_RESTORE_INHIBIT;
694 ret = mi_set_context(ring, to, hw_flags);
698 for (i = 0; i < MAX_L3_SLICES; i++) {
699 if (!(to->remap_slice & (1<<i)))
702 ret = i915_gem_l3_remap(ring, i);
703 /* If it failed, try again next round */
705 DRM_DEBUG_DRIVER("L3 remapping failed\n");
707 to->remap_slice &= ~(1<<i);
710 /* The backing object for the context is done after switching to the
711 * *next* context. Therefore we cannot retire the previous context until
712 * the next context has already started running. In fact, the below code
713 * is a bit suboptimal because the retiring can occur simply after the
714 * MI_SET_CONTEXT instead of when the next seqno has completed.
717 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
718 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
719 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
720 * whole damn pipeline, we don't need to explicitly mark the
721 * object dirty. The only exception is that the context must be
722 * correct in case the object gets swapped out. Ideally we'd be
723 * able to defer doing this until we know the object would be
724 * swapped, but there is no way to do that yet.
726 from->obj->dirty = 1;
727 BUG_ON(from->obj->ring != ring);
729 /* obj is kept alive until the next request by its active ref */
730 i915_gem_object_ggtt_unpin(from->obj);
731 i915_gem_context_unreference(from);
734 to->is_initialized = true;
737 i915_gem_context_reference(to);
738 ring->last_context = to;
739 to->last_ring = ring;
745 i915_gem_object_ggtt_unpin(to->obj);
750 * i915_switch_context() - perform a GPU context switch.
751 * @ring: ring for which we'll execute the context switch
752 * @file_priv: file_priv associated with the context, may be NULL
753 * @id: context id number
755 * The context life cycle is simple. The context refcount is incremented and
756 * decremented by 1 and create and destroy. If the context is in use by the GPU,
757 * it will have a refoucnt > 1. This allows us to destroy the context abstract
758 * object while letting the normal object tracking destroy the backing BO.
760 int i915_switch_context(struct intel_ring_buffer *ring,
761 struct drm_file *file,
762 struct i915_hw_context *to)
764 struct drm_i915_private *dev_priv = ring->dev->dev_private;
766 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
768 BUG_ON(file && to == NULL);
770 /* We have the fake context, but don't supports switching. */
771 if (!HAS_HW_CONTEXTS(ring->dev))
774 return do_switch(ring, to);
777 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
778 struct drm_file *file)
780 struct drm_i915_gem_context_create *args = data;
781 struct drm_i915_file_private *file_priv = file->driver_priv;
782 struct i915_hw_context *ctx;
785 if (!HAS_HW_CONTEXTS(dev))
788 ret = i915_mutex_lock_interruptible(dev);
792 ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev));
793 mutex_unlock(&dev->struct_mutex);
797 args->ctx_id = ctx->id;
798 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
803 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
804 struct drm_file *file)
806 struct drm_i915_gem_context_destroy *args = data;
807 struct drm_i915_file_private *file_priv = file->driver_priv;
808 struct i915_hw_context *ctx;
811 if (args->ctx_id == DEFAULT_CONTEXT_ID)
814 ret = i915_mutex_lock_interruptible(dev);
818 ctx = i915_gem_context_get(file_priv, args->ctx_id);
820 mutex_unlock(&dev->struct_mutex);
824 idr_remove(&ctx->file_priv->context_idr, ctx->id);
825 i915_gem_context_unreference(ctx);
826 mutex_unlock(&dev->struct_mutex);
828 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);