2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
102 static size_t get_context_alignment(struct drm_i915_private *dev_priv)
104 if (IS_GEN6(dev_priv))
105 return GEN6_CONTEXT_ALIGN;
107 return GEN7_CONTEXT_ALIGN;
110 static int get_context_size(struct drm_i915_private *dev_priv)
115 switch (INTEL_GEN(dev_priv)) {
117 reg = I915_READ(CXT_SIZE);
118 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
121 reg = I915_READ(GEN7_CXT_SIZE);
122 if (IS_HASWELL(dev_priv))
123 ret = HSW_CXT_TOTAL_SIZE;
125 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 ret = GEN8_CXT_TOTAL_SIZE;
137 void i915_gem_context_free(struct kref *ctx_ref)
139 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
142 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
143 trace_i915_context_free(ctx);
144 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
146 i915_ppgtt_put(ctx->ppgtt);
148 for (i = 0; i < I915_NUM_ENGINES; i++) {
149 struct intel_context *ce = &ctx->engine[i];
154 WARN_ON(ce->pin_count);
156 intel_ring_free(ce->ring);
158 __i915_gem_object_release_unless_active(ce->state->obj);
163 list_del(&ctx->link);
165 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
169 static struct drm_i915_gem_object *
170 alloc_context_obj(struct drm_i915_private *dev_priv, u64 size)
172 struct drm_i915_gem_object *obj;
175 lockdep_assert_held(&dev_priv->drm.struct_mutex);
177 obj = i915_gem_object_create(dev_priv, size);
182 * Try to make the context utilize L3 as well as LLC.
184 * On VLV we don't have L3 controls in the PTEs so we
185 * shouldn't touch the cache level, especially as that
186 * would make the object snooped which might have a
187 * negative performance impact.
189 * Snooping is required on non-llc platforms in execlist
190 * mode, but since all GGTT accesses use PAT entry 0 we
191 * get snooping anyway regardless of cache_level.
193 * This is only applicable for Ivy Bridge devices since
194 * later platforms don't have L3 control bits in the PTE.
196 if (IS_IVYBRIDGE(dev_priv)) {
197 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
198 /* Failure shouldn't ever happen this early */
200 i915_gem_object_put(obj);
208 static void context_close(struct i915_gem_context *ctx)
210 i915_gem_context_set_closed(ctx);
212 i915_ppgtt_close(&ctx->ppgtt->base);
213 ctx->file_priv = ERR_PTR(-EBADF);
214 i915_gem_context_put(ctx);
217 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
221 ret = ida_simple_get(&dev_priv->context_hw_ida,
222 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
224 /* Contexts are only released when no longer active.
225 * Flush any pending retires to hopefully release some
226 * stale contexts and try again.
228 i915_gem_retire_requests(dev_priv);
229 ret = ida_simple_get(&dev_priv->context_hw_ida,
230 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
239 static struct i915_gem_context *
240 __create_hw_context(struct drm_i915_private *dev_priv,
241 struct drm_i915_file_private *file_priv)
243 struct i915_gem_context *ctx;
246 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
248 return ERR_PTR(-ENOMEM);
250 ret = assign_hw_id(dev_priv, &ctx->hw_id);
256 kref_init(&ctx->ref);
257 list_add_tail(&ctx->link, &dev_priv->context_list);
258 ctx->i915 = dev_priv;
260 ctx->ggtt_alignment = get_context_alignment(dev_priv);
262 if (dev_priv->hw_context_size) {
263 struct drm_i915_gem_object *obj;
264 struct i915_vma *vma;
266 obj = alloc_context_obj(dev_priv, dev_priv->hw_context_size);
272 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
274 i915_gem_object_put(obj);
279 ctx->engine[RCS].state = vma;
282 /* Default context will never have a file_priv */
283 ret = DEFAULT_CONTEXT_HANDLE;
285 ret = idr_alloc(&file_priv->context_idr, ctx,
286 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
290 ctx->user_handle = ret;
292 ctx->file_priv = file_priv;
294 ctx->pid = get_task_pid(current, PIDTYPE_PID);
295 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
305 /* NB: Mark all slices as needing a remap so that when the context first
306 * loads it will restore whatever remap state already exists. If there
307 * is no remap info, it will be a NOP. */
308 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
310 i915_gem_context_set_bannable(ctx);
311 ctx->ring_size = 4 * PAGE_SIZE;
312 ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
313 GEN8_CTX_ADDRESSING_MODE_SHIFT;
314 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
316 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
317 * present or not in use we still need a small bias as ring wraparound
318 * at offset 0 sometimes hangs. No idea why.
320 if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
321 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
323 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
329 idr_remove(&file_priv->context_idr, ctx->user_handle);
336 * The default context needs to exist per ring that uses contexts. It stores the
337 * context state of the GPU for applications that don't utilize HW contexts, as
338 * well as an idle case.
340 static struct i915_gem_context *
341 i915_gem_create_context(struct drm_i915_private *dev_priv,
342 struct drm_i915_file_private *file_priv)
344 struct i915_gem_context *ctx;
346 lockdep_assert_held(&dev_priv->drm.struct_mutex);
348 ctx = __create_hw_context(dev_priv, file_priv);
352 if (USES_FULL_PPGTT(dev_priv)) {
353 struct i915_hw_ppgtt *ppgtt;
355 ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
357 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
359 idr_remove(&file_priv->context_idr, ctx->user_handle);
361 return ERR_CAST(ppgtt);
367 trace_i915_context_create(ctx);
373 * i915_gem_context_create_gvt - create a GVT GEM context
376 * This function is used to create a GVT specific GEM context.
379 * pointer to i915_gem_context on success, error pointer if failed
382 struct i915_gem_context *
383 i915_gem_context_create_gvt(struct drm_device *dev)
385 struct i915_gem_context *ctx;
388 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
389 return ERR_PTR(-ENODEV);
391 ret = i915_mutex_lock_interruptible(dev);
395 ctx = __create_hw_context(to_i915(dev), NULL);
399 ctx->file_priv = ERR_PTR(-EBADF);
400 i915_gem_context_set_closed(ctx); /* not user accessible */
401 i915_gem_context_clear_bannable(ctx);
402 i915_gem_context_set_force_single_submission(ctx);
403 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
405 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
407 mutex_unlock(&dev->struct_mutex);
411 int i915_gem_context_init(struct drm_i915_private *dev_priv)
413 struct i915_gem_context *ctx;
415 /* Init should only be called once per module load. Eventually the
416 * restriction on the context_disabled check can be loosened. */
417 if (WARN_ON(dev_priv->kernel_context))
420 if (intel_vgpu_active(dev_priv) &&
421 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
422 if (!i915.enable_execlists) {
423 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
428 /* Using the simple ida interface, the max is limited by sizeof(int) */
429 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
430 ida_init(&dev_priv->context_hw_ida);
432 if (i915.enable_execlists) {
433 /* NB: intentionally left blank. We will allocate our own
434 * backing objects as we need them, thank you very much */
435 dev_priv->hw_context_size = 0;
436 } else if (HAS_HW_CONTEXTS(dev_priv)) {
437 dev_priv->hw_context_size =
438 round_up(get_context_size(dev_priv),
440 if (dev_priv->hw_context_size > (1<<20)) {
441 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
442 dev_priv->hw_context_size);
443 dev_priv->hw_context_size = 0;
447 ctx = i915_gem_create_context(dev_priv, NULL);
449 DRM_ERROR("Failed to create default global context (error %ld)\n",
454 i915_gem_context_clear_bannable(ctx);
455 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
456 dev_priv->kernel_context = ctx;
458 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
460 DRM_DEBUG_DRIVER("%s context support initialized\n",
461 i915.enable_execlists ? "LR" :
462 dev_priv->hw_context_size ? "HW" : "fake");
466 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
468 struct intel_engine_cs *engine;
469 enum intel_engine_id id;
471 lockdep_assert_held(&dev_priv->drm.struct_mutex);
473 for_each_engine(engine, dev_priv, id) {
474 engine->legacy_active_context = NULL;
476 if (!engine->last_retired_context)
479 engine->context_unpin(engine, engine->last_retired_context);
480 engine->last_retired_context = NULL;
483 /* Force the GPU state to be restored on enabling */
484 if (!i915.enable_execlists) {
485 struct i915_gem_context *ctx;
487 list_for_each_entry(ctx, &dev_priv->context_list, link) {
488 if (!i915_gem_context_is_default(ctx))
491 for_each_engine(engine, dev_priv, id)
492 ctx->engine[engine->id].initialised = false;
494 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
497 for_each_engine(engine, dev_priv, id) {
498 struct intel_context *kce =
499 &dev_priv->kernel_context->engine[engine->id];
501 kce->initialised = true;
506 void i915_gem_context_fini(struct drm_i915_private *dev_priv)
508 struct i915_gem_context *dctx = dev_priv->kernel_context;
510 lockdep_assert_held(&dev_priv->drm.struct_mutex);
512 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx));
515 dev_priv->kernel_context = NULL;
517 ida_destroy(&dev_priv->context_hw_ida);
520 static int context_idr_cleanup(int id, void *p, void *data)
522 struct i915_gem_context *ctx = p;
528 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
530 struct drm_i915_file_private *file_priv = file->driver_priv;
531 struct i915_gem_context *ctx;
533 idr_init(&file_priv->context_idr);
535 mutex_lock(&dev->struct_mutex);
536 ctx = i915_gem_create_context(to_i915(dev), file_priv);
537 mutex_unlock(&dev->struct_mutex);
539 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
542 idr_destroy(&file_priv->context_idr);
549 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
551 struct drm_i915_file_private *file_priv = file->driver_priv;
553 lockdep_assert_held(&dev->struct_mutex);
555 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
556 idr_destroy(&file_priv->context_idr);
560 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
562 struct drm_i915_private *dev_priv = req->i915;
563 struct intel_ring *ring = req->ring;
564 struct intel_engine_cs *engine = req->engine;
565 enum intel_engine_id id;
566 u32 flags = hw_flags | MI_MM_SPACE_GTT;
567 const int num_rings =
568 /* Use an extended w/a on ivb+ if signalling from other rings */
570 INTEL_INFO(dev_priv)->num_rings - 1 :
574 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
575 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
576 * explicitly, so we rely on the value at ring init, stored in
577 * itlb_before_ctx_switch.
579 if (IS_GEN6(dev_priv)) {
580 ret = engine->emit_flush(req, EMIT_INVALIDATE);
585 /* These flags are for resource streamer on HSW+ */
586 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
587 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
588 else if (INTEL_GEN(dev_priv) < 8)
589 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
593 if (INTEL_GEN(dev_priv) >= 7)
594 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
596 ret = intel_ring_begin(req, len);
600 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
601 if (INTEL_GEN(dev_priv) >= 7) {
602 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
604 struct intel_engine_cs *signaller;
606 intel_ring_emit(ring,
607 MI_LOAD_REGISTER_IMM(num_rings));
608 for_each_engine(signaller, dev_priv, id) {
609 if (signaller == engine)
612 intel_ring_emit_reg(ring,
613 RING_PSMI_CTL(signaller->mmio_base));
614 intel_ring_emit(ring,
615 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
620 intel_ring_emit(ring, MI_NOOP);
621 intel_ring_emit(ring, MI_SET_CONTEXT);
622 intel_ring_emit(ring,
623 i915_ggtt_offset(req->ctx->engine[RCS].state) | flags);
625 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
626 * WaMiSetContext_Hang:snb,ivb,vlv
628 intel_ring_emit(ring, MI_NOOP);
630 if (INTEL_GEN(dev_priv) >= 7) {
632 struct intel_engine_cs *signaller;
633 i915_reg_t last_reg = {}; /* keep gcc quiet */
635 intel_ring_emit(ring,
636 MI_LOAD_REGISTER_IMM(num_rings));
637 for_each_engine(signaller, dev_priv, id) {
638 if (signaller == engine)
641 last_reg = RING_PSMI_CTL(signaller->mmio_base);
642 intel_ring_emit_reg(ring, last_reg);
643 intel_ring_emit(ring,
644 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
647 /* Insert a delay before the next switch! */
648 intel_ring_emit(ring,
649 MI_STORE_REGISTER_MEM |
650 MI_SRM_LRM_GLOBAL_GTT);
651 intel_ring_emit_reg(ring, last_reg);
652 intel_ring_emit(ring,
653 i915_ggtt_offset(engine->scratch));
654 intel_ring_emit(ring, MI_NOOP);
656 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
659 intel_ring_advance(ring);
664 static int remap_l3(struct drm_i915_gem_request *req, int slice)
666 u32 *remap_info = req->i915->l3_parity.remap_info[slice];
667 struct intel_ring *ring = req->ring;
673 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
678 * Note: We do not worry about the concurrent register cacheline hang
679 * here because no other code should access these registers other than
680 * at initialization time.
682 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
683 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
684 intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
685 intel_ring_emit(ring, remap_info[i]);
687 intel_ring_emit(ring, MI_NOOP);
688 intel_ring_advance(ring);
693 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
694 struct intel_engine_cs *engine,
695 struct i915_gem_context *to)
700 if (!to->engine[RCS].initialised)
703 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
706 return to == engine->legacy_active_context;
710 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
711 struct intel_engine_cs *engine,
712 struct i915_gem_context *to)
717 /* Always load the ppgtt on first use */
718 if (!engine->legacy_active_context)
721 /* Same context without new entries, skip */
722 if (engine->legacy_active_context == to &&
723 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
726 if (engine->id != RCS)
729 if (INTEL_GEN(engine->i915) < 8)
736 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
737 struct i915_gem_context *to,
743 if (!IS_GEN8(to->i915))
746 if (hw_flags & MI_RESTORE_INHIBIT)
752 static int do_rcs_switch(struct drm_i915_gem_request *req)
754 struct i915_gem_context *to = req->ctx;
755 struct intel_engine_cs *engine = req->engine;
756 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
757 struct i915_gem_context *from = engine->legacy_active_context;
761 GEM_BUG_ON(engine->id != RCS);
763 if (skip_rcs_switch(ppgtt, engine, to))
766 if (needs_pd_load_pre(ppgtt, engine, to)) {
767 /* Older GENs and non render rings still want the load first,
768 * "PP_DCLV followed by PP_DIR_BASE register through Load
769 * Register Immediate commands in Ring Buffer before submitting
771 trace_switch_mm(engine, to);
772 ret = ppgtt->switch_mm(ppgtt, req);
777 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
778 /* NB: If we inhibit the restore, the context is not allowed to
779 * die because future work may end up depending on valid address
780 * space. This means we must enforce that a page table load
781 * occur when this occurs. */
782 hw_flags = MI_RESTORE_INHIBIT;
783 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
784 hw_flags = MI_FORCE_RESTORE;
788 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
789 ret = mi_set_context(req, hw_flags);
793 engine->legacy_active_context = to;
796 /* GEN8 does *not* require an explicit reload if the PDPs have been
797 * setup, and we do not wish to move them.
799 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
800 trace_switch_mm(engine, to);
801 ret = ppgtt->switch_mm(ppgtt, req);
802 /* The hardware context switch is emitted, but we haven't
803 * actually changed the state - so it's probably safe to bail
804 * here. Still, let the user know something dangerous has
812 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
814 for (i = 0; i < MAX_L3_SLICES; i++) {
815 if (!(to->remap_slice & (1<<i)))
818 ret = remap_l3(req, i);
822 to->remap_slice &= ~(1<<i);
825 if (!to->engine[RCS].initialised) {
826 if (engine->init_context) {
827 ret = engine->init_context(req);
831 to->engine[RCS].initialised = true;
838 * i915_switch_context() - perform a GPU context switch.
839 * @req: request for which we'll execute the context switch
841 * The context life cycle is simple. The context refcount is incremented and
842 * decremented by 1 and create and destroy. If the context is in use by the GPU,
843 * it will have a refcount > 1. This allows us to destroy the context abstract
844 * object while letting the normal object tracking destroy the backing BO.
846 * This function should not be used in execlists mode. Instead the context is
847 * switched by writing to the ELSP and requests keep a reference to their
850 int i915_switch_context(struct drm_i915_gem_request *req)
852 struct intel_engine_cs *engine = req->engine;
854 lockdep_assert_held(&req->i915->drm.struct_mutex);
855 if (i915.enable_execlists)
858 if (!req->ctx->engine[engine->id].state) {
859 struct i915_gem_context *to = req->ctx;
860 struct i915_hw_ppgtt *ppgtt =
861 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
863 if (needs_pd_load_pre(ppgtt, engine, to)) {
866 trace_switch_mm(engine, to);
867 ret = ppgtt->switch_mm(ppgtt, req);
871 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
877 return do_rcs_switch(req);
880 static bool engine_has_kernel_context(struct intel_engine_cs *engine)
882 struct i915_gem_timeline *timeline;
884 list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
885 struct intel_timeline *tl;
887 if (timeline == &engine->i915->gt.global_timeline)
890 tl = &timeline->engine[engine->id];
891 if (i915_gem_active_peek(&tl->last_request,
892 &engine->i915->drm.struct_mutex))
896 return (!engine->last_retired_context ||
897 i915_gem_context_is_kernel(engine->last_retired_context));
900 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
902 struct intel_engine_cs *engine;
903 struct i915_gem_timeline *timeline;
904 enum intel_engine_id id;
906 lockdep_assert_held(&dev_priv->drm.struct_mutex);
908 i915_gem_retire_requests(dev_priv);
910 for_each_engine(engine, dev_priv, id) {
911 struct drm_i915_gem_request *req;
914 if (engine_has_kernel_context(engine))
917 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
921 /* Queue this switch after all other activity */
922 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
923 struct drm_i915_gem_request *prev;
924 struct intel_timeline *tl;
926 tl = &timeline->engine[engine->id];
927 prev = i915_gem_active_raw(&tl->last_request,
928 &dev_priv->drm.struct_mutex);
930 i915_sw_fence_await_sw_fence_gfp(&req->submit,
935 ret = i915_switch_context(req);
936 i915_add_request_no_flush(req);
944 static bool contexts_enabled(struct drm_device *dev)
946 return i915.enable_execlists || to_i915(dev)->hw_context_size;
949 static bool client_is_banned(struct drm_i915_file_private *file_priv)
951 return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS;
954 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
955 struct drm_file *file)
957 struct drm_i915_gem_context_create *args = data;
958 struct drm_i915_file_private *file_priv = file->driver_priv;
959 struct i915_gem_context *ctx;
962 if (!contexts_enabled(dev))
968 if (client_is_banned(file_priv)) {
969 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
971 pid_nr(get_task_pid(current, PIDTYPE_PID)));
976 ret = i915_mutex_lock_interruptible(dev);
980 ctx = i915_gem_create_context(to_i915(dev), file_priv);
981 mutex_unlock(&dev->struct_mutex);
985 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
987 args->ctx_id = ctx->user_handle;
988 DRM_DEBUG("HW context %d created\n", args->ctx_id);
993 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *file)
996 struct drm_i915_gem_context_destroy *args = data;
997 struct drm_i915_file_private *file_priv = file->driver_priv;
998 struct i915_gem_context *ctx;
1004 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1007 ret = i915_mutex_lock_interruptible(dev);
1011 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1013 mutex_unlock(&dev->struct_mutex);
1014 return PTR_ERR(ctx);
1017 idr_remove(&file_priv->context_idr, ctx->user_handle);
1019 mutex_unlock(&dev->struct_mutex);
1021 DRM_DEBUG("HW context %d destroyed\n", args->ctx_id);
1025 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1026 struct drm_file *file)
1028 struct drm_i915_file_private *file_priv = file->driver_priv;
1029 struct drm_i915_gem_context_param *args = data;
1030 struct i915_gem_context *ctx;
1033 ret = i915_mutex_lock_interruptible(dev);
1037 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1039 mutex_unlock(&dev->struct_mutex);
1040 return PTR_ERR(ctx);
1044 switch (args->param) {
1045 case I915_CONTEXT_PARAM_BAN_PERIOD:
1048 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1049 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1051 case I915_CONTEXT_PARAM_GTT_SIZE:
1053 args->value = ctx->ppgtt->base.total;
1054 else if (to_i915(dev)->mm.aliasing_ppgtt)
1055 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1057 args->value = to_i915(dev)->ggtt.base.total;
1059 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1060 args->value = i915_gem_context_no_error_capture(ctx);
1062 case I915_CONTEXT_PARAM_BANNABLE:
1063 args->value = i915_gem_context_is_bannable(ctx);
1069 mutex_unlock(&dev->struct_mutex);
1074 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file)
1077 struct drm_i915_file_private *file_priv = file->driver_priv;
1078 struct drm_i915_gem_context_param *args = data;
1079 struct i915_gem_context *ctx;
1082 ret = i915_mutex_lock_interruptible(dev);
1086 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1088 mutex_unlock(&dev->struct_mutex);
1089 return PTR_ERR(ctx);
1092 switch (args->param) {
1093 case I915_CONTEXT_PARAM_BAN_PERIOD:
1096 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1100 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1101 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1104 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1107 else if (args->value)
1108 i915_gem_context_set_no_error_capture(ctx);
1110 i915_gem_context_clear_no_error_capture(ctx);
1112 case I915_CONTEXT_PARAM_BANNABLE:
1115 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1117 else if (args->value)
1118 i915_gem_context_set_bannable(ctx);
1120 i915_gem_context_clear_bannable(ctx);
1126 mutex_unlock(&dev->struct_mutex);
1131 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1132 void *data, struct drm_file *file)
1134 struct drm_i915_private *dev_priv = to_i915(dev);
1135 struct drm_i915_reset_stats *args = data;
1136 struct i915_gem_context *ctx;
1139 if (args->flags || args->pad)
1142 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1145 ret = i915_mutex_lock_interruptible(dev);
1149 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1151 mutex_unlock(&dev->struct_mutex);
1152 return PTR_ERR(ctx);
1155 if (capable(CAP_SYS_ADMIN))
1156 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1158 args->reset_count = 0;
1160 args->batch_active = ctx->guilty_count;
1161 args->batch_pending = ctx->active_count;
1163 mutex_unlock(&dev->struct_mutex);