2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device *dev)
103 return GEN6_CONTEXT_ALIGN;
105 return GEN7_CONTEXT_ALIGN;
108 static int get_context_size(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
114 switch (INTEL_INFO(dev)->gen) {
116 reg = I915_READ(CXT_SIZE);
117 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
120 reg = I915_READ(GEN7_CXT_SIZE);
122 ret = HSW_CXT_TOTAL_SIZE;
124 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
127 ret = GEN8_CXT_TOTAL_SIZE;
136 static void i915_gem_context_clean(struct intel_context *ctx)
138 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
139 struct i915_vma *vma, *next;
144 list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
146 if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
151 void i915_gem_context_free(struct kref *ctx_ref)
153 struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
155 trace_i915_context_free(ctx);
157 if (i915.enable_execlists)
158 intel_lr_context_free(ctx);
161 * This context is going away and we need to remove all VMAs still
162 * around. This is to handle imported shared objects for which
163 * destructor did not run when their handles were closed.
165 i915_gem_context_clean(ctx);
167 i915_ppgtt_put(ctx->ppgtt);
169 if (ctx->legacy_hw_ctx.rcs_state)
170 drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
171 list_del(&ctx->link);
175 struct drm_i915_gem_object *
176 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
178 struct drm_i915_gem_object *obj;
181 obj = i915_gem_alloc_object(dev, size);
183 return ERR_PTR(-ENOMEM);
186 * Try to make the context utilize L3 as well as LLC.
188 * On VLV we don't have L3 controls in the PTEs so we
189 * shouldn't touch the cache level, especially as that
190 * would make the object snooped which might have a
191 * negative performance impact.
193 * Snooping is required on non-llc platforms in execlist
194 * mode, but since all GGTT accesses use PAT entry 0 we
195 * get snooping anyway regardless of cache_level.
197 * This is only applicable for Ivy Bridge devices since
198 * later platforms don't have L3 control bits in the PTE.
200 if (IS_IVYBRIDGE(dev)) {
201 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
202 /* Failure shouldn't ever happen this early */
204 drm_gem_object_unreference(&obj->base);
212 static struct intel_context *
213 __create_hw_context(struct drm_device *dev,
214 struct drm_i915_file_private *file_priv)
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 struct intel_context *ctx;
220 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
222 return ERR_PTR(-ENOMEM);
224 kref_init(&ctx->ref);
225 list_add_tail(&ctx->link, &dev_priv->context_list);
226 ctx->i915 = dev_priv;
228 if (dev_priv->hw_context_size) {
229 struct drm_i915_gem_object *obj =
230 i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
235 ctx->legacy_hw_ctx.rcs_state = obj;
238 /* Default context will never have a file_priv */
239 if (file_priv != NULL) {
240 ret = idr_alloc(&file_priv->context_idr, ctx,
241 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
245 ret = DEFAULT_CONTEXT_HANDLE;
247 ctx->file_priv = file_priv;
248 ctx->user_handle = ret;
249 /* NB: Mark all slices as needing a remap so that when the context first
250 * loads it will restore whatever remap state already exists. If there
251 * is no remap info, it will be a NOP. */
252 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
254 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
259 i915_gem_context_unreference(ctx);
264 * The default context needs to exist per ring that uses contexts. It stores the
265 * context state of the GPU for applications that don't utilize HW contexts, as
266 * well as an idle case.
268 static struct intel_context *
269 i915_gem_create_context(struct drm_device *dev,
270 struct drm_i915_file_private *file_priv)
272 const bool is_global_default_ctx = file_priv == NULL;
273 struct intel_context *ctx;
276 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
278 ctx = __create_hw_context(dev, file_priv);
282 if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
283 /* We may need to do things with the shrinker which
284 * require us to immediately switch back to the default
285 * context. This can cause a problem as pinning the
286 * default context also requires GTT space which may not
287 * be available. To avoid this we always pin the default
290 ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
291 get_context_alignment(dev), 0);
293 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
298 if (USES_FULL_PPGTT(dev)) {
299 struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
301 if (IS_ERR_OR_NULL(ppgtt)) {
302 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
304 ret = PTR_ERR(ppgtt);
311 trace_i915_context_create(ctx);
316 if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
317 i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
319 idr_remove(&file_priv->context_idr, ctx->user_handle);
320 i915_gem_context_unreference(ctx);
324 static void i915_gem_context_unpin(struct intel_context *ctx,
325 struct intel_engine_cs *engine)
327 if (i915.enable_execlists) {
328 intel_lr_context_unpin(ctx, engine);
330 if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state)
331 i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
332 i915_gem_context_unreference(ctx);
336 void i915_gem_context_reset(struct drm_device *dev)
338 struct drm_i915_private *dev_priv = dev->dev_private;
341 if (i915.enable_execlists) {
342 struct intel_context *ctx;
344 list_for_each_entry(ctx, &dev_priv->context_list, link)
345 intel_lr_context_reset(dev_priv, ctx);
348 for (i = 0; i < I915_NUM_ENGINES; i++) {
349 struct intel_engine_cs *engine = &dev_priv->engine[i];
351 if (engine->last_context) {
352 i915_gem_context_unpin(engine->last_context, engine);
353 engine->last_context = NULL;
357 /* Force the GPU state to be reinitialised on enabling */
358 dev_priv->kernel_context->legacy_hw_ctx.initialized = false;
361 int i915_gem_context_init(struct drm_device *dev)
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 struct intel_context *ctx;
366 /* Init should only be called once per module load. Eventually the
367 * restriction on the context_disabled check can be loosened. */
368 if (WARN_ON(dev_priv->kernel_context))
371 if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
372 if (!i915.enable_execlists) {
373 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
378 if (i915.enable_execlists) {
379 /* NB: intentionally left blank. We will allocate our own
380 * backing objects as we need them, thank you very much */
381 dev_priv->hw_context_size = 0;
382 } else if (HAS_HW_CONTEXTS(dev)) {
383 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
384 if (dev_priv->hw_context_size > (1<<20)) {
385 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
386 dev_priv->hw_context_size);
387 dev_priv->hw_context_size = 0;
391 ctx = i915_gem_create_context(dev, NULL);
393 DRM_ERROR("Failed to create default global context (error %ld)\n",
398 dev_priv->kernel_context = ctx;
400 DRM_DEBUG_DRIVER("%s context support initialized\n",
401 i915.enable_execlists ? "LR" :
402 dev_priv->hw_context_size ? "HW" : "fake");
406 void i915_gem_context_fini(struct drm_device *dev)
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct intel_context *dctx = dev_priv->kernel_context;
412 if (dctx->legacy_hw_ctx.rcs_state) {
413 /* The only known way to stop the gpu from accessing the hw context is
414 * to reset it. Do this as the very last operation to avoid confusing
415 * other code, leading to spurious errors. */
416 intel_gpu_reset(dev, ALL_ENGINES);
418 /* When default context is created and switched to, base object refcount
419 * will be 2 (+1 from object creation and +1 from do_switch()).
420 * i915_gem_context_fini() will be called after gpu_idle() has switched
421 * to default context. So we need to unreference the base object once
422 * to offset the do_switch part, so that i915_gem_context_unreference()
423 * can then free the base object correctly. */
424 WARN_ON(!dev_priv->engine[RCS].last_context);
426 i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
429 for (i = I915_NUM_ENGINES; --i >= 0;) {
430 struct intel_engine_cs *engine = &dev_priv->engine[i];
432 if (engine->last_context) {
433 i915_gem_context_unpin(engine->last_context, engine);
434 engine->last_context = NULL;
438 i915_gem_context_unreference(dctx);
439 dev_priv->kernel_context = NULL;
442 int i915_gem_context_enable(struct drm_i915_gem_request *req)
444 struct intel_engine_cs *engine = req->engine;
447 if (i915.enable_execlists) {
448 if (engine->init_context == NULL)
451 ret = engine->init_context(req);
453 ret = i915_switch_context(req);
456 DRM_ERROR("ring init context: %d\n", ret);
463 static int context_idr_cleanup(int id, void *p, void *data)
465 struct intel_context *ctx = p;
467 i915_gem_context_unreference(ctx);
471 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
473 struct drm_i915_file_private *file_priv = file->driver_priv;
474 struct intel_context *ctx;
476 idr_init(&file_priv->context_idr);
478 mutex_lock(&dev->struct_mutex);
479 ctx = i915_gem_create_context(dev, file_priv);
480 mutex_unlock(&dev->struct_mutex);
483 idr_destroy(&file_priv->context_idr);
490 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
492 struct drm_i915_file_private *file_priv = file->driver_priv;
494 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
495 idr_destroy(&file_priv->context_idr);
498 struct intel_context *
499 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
501 struct intel_context *ctx;
503 ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
505 return ERR_PTR(-ENOENT);
511 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
513 struct intel_engine_cs *engine = req->engine;
514 u32 flags = hw_flags | MI_MM_SPACE_GTT;
515 const int num_rings =
516 /* Use an extended w/a on ivb+ if signalling from other rings */
517 i915_semaphore_is_enabled(engine->dev) ?
518 hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
522 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
523 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
524 * explicitly, so we rely on the value at ring init, stored in
525 * itlb_before_ctx_switch.
527 if (IS_GEN6(engine->dev)) {
528 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
533 /* These flags are for resource streamer on HSW+ */
534 if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
535 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
536 else if (INTEL_INFO(engine->dev)->gen < 8)
537 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
541 if (INTEL_INFO(engine->dev)->gen >= 7)
542 len += 2 + (num_rings ? 4*num_rings + 2 : 0);
544 ret = intel_ring_begin(req, len);
548 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
549 if (INTEL_INFO(engine->dev)->gen >= 7) {
550 intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
552 struct intel_engine_cs *signaller;
554 intel_ring_emit(engine,
555 MI_LOAD_REGISTER_IMM(num_rings));
556 for_each_engine(signaller, to_i915(engine->dev)) {
557 if (signaller == engine)
560 intel_ring_emit_reg(engine,
561 RING_PSMI_CTL(signaller->mmio_base));
562 intel_ring_emit(engine,
563 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
568 intel_ring_emit(engine, MI_NOOP);
569 intel_ring_emit(engine, MI_SET_CONTEXT);
570 intel_ring_emit(engine,
571 i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) |
574 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
575 * WaMiSetContext_Hang:snb,ivb,vlv
577 intel_ring_emit(engine, MI_NOOP);
579 if (INTEL_INFO(engine->dev)->gen >= 7) {
581 struct intel_engine_cs *signaller;
583 intel_ring_emit(engine,
584 MI_LOAD_REGISTER_IMM(num_rings));
585 for_each_engine(signaller, to_i915(engine->dev)) {
586 if (signaller == engine)
589 intel_ring_emit_reg(engine,
590 RING_PSMI_CTL(signaller->mmio_base));
591 intel_ring_emit(engine,
592 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
595 intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE);
598 intel_ring_advance(engine);
603 static inline bool should_skip_switch(struct intel_engine_cs *engine,
604 struct intel_context *from,
605 struct intel_context *to)
610 if (to->ppgtt && from == to &&
611 !(intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings))
618 needs_pd_load_pre(struct intel_engine_cs *engine, struct intel_context *to)
620 struct drm_i915_private *dev_priv = engine->dev->dev_private;
625 if (INTEL_INFO(engine->dev)->gen < 8)
628 if (engine != &dev_priv->engine[RCS])
635 needs_pd_load_post(struct intel_engine_cs *engine, struct intel_context *to,
638 struct drm_i915_private *dev_priv = engine->dev->dev_private;
643 if (!IS_GEN8(engine->dev))
646 if (engine != &dev_priv->engine[RCS])
649 if (hw_flags & MI_RESTORE_INHIBIT)
655 static int do_switch(struct drm_i915_gem_request *req)
657 struct intel_context *to = req->ctx;
658 struct intel_engine_cs *engine = req->engine;
659 struct drm_i915_private *dev_priv = req->i915;
660 struct intel_context *from = engine->last_context;
662 bool uninitialized = false;
665 if (from != NULL && engine == &dev_priv->engine[RCS]) {
666 BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
667 BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
670 if (should_skip_switch(engine, from, to))
673 /* Trying to pin first makes error handling easier. */
674 if (engine == &dev_priv->engine[RCS]) {
675 ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
676 get_context_alignment(engine->dev),
683 * Pin can switch back to the default context if we end up calling into
684 * evict_everything - as a last ditch gtt defrag effort that also
685 * switches to the default context. Hence we need to reload from here.
687 from = engine->last_context;
689 if (needs_pd_load_pre(engine, to)) {
690 /* Older GENs and non render rings still want the load first,
691 * "PP_DCLV followed by PP_DIR_BASE register through Load
692 * Register Immediate commands in Ring Buffer before submitting
694 trace_switch_mm(engine, to);
695 ret = to->ppgtt->switch_mm(to->ppgtt, req);
699 /* Doing a PD load always reloads the page dirs */
700 to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
703 if (engine != &dev_priv->engine[RCS]) {
705 i915_gem_context_unreference(from);
710 * Clear this page out of any CPU caches for coherent swap-in/out. Note
711 * that thanks to write = false in this call and us not setting any gpu
712 * write domains when putting a context object onto the active list
713 * (when switching away from it), this won't block.
715 * XXX: We need a real interface to do this instead of trickery.
717 ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
721 if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
722 hw_flags |= MI_RESTORE_INHIBIT;
723 /* NB: If we inhibit the restore, the context is not allowed to
724 * die because future work may end up depending on valid address
725 * space. This means we must enforce that a page table load
726 * occur when this occurs. */
727 } else if (to->ppgtt &&
728 (intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings)) {
729 hw_flags |= MI_FORCE_RESTORE;
730 to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
733 /* We should never emit switch_mm more than once */
734 WARN_ON(needs_pd_load_pre(engine, to) &&
735 needs_pd_load_post(engine, to, hw_flags));
737 ret = mi_set_context(req, hw_flags);
741 /* GEN8 does *not* require an explicit reload if the PDPs have been
742 * setup, and we do not wish to move them.
744 if (needs_pd_load_post(engine, to, hw_flags)) {
745 trace_switch_mm(engine, to);
746 ret = to->ppgtt->switch_mm(to->ppgtt, req);
747 /* The hardware context switch is emitted, but we haven't
748 * actually changed the state - so it's probably safe to bail
749 * here. Still, let the user know something dangerous has
753 DRM_ERROR("Failed to change address space on context switch\n");
758 for (i = 0; i < MAX_L3_SLICES; i++) {
759 if (!(to->remap_slice & (1<<i)))
762 ret = i915_gem_l3_remap(req, i);
763 /* If it failed, try again next round */
765 DRM_DEBUG_DRIVER("L3 remapping failed\n");
767 to->remap_slice &= ~(1<<i);
770 /* The backing object for the context is done after switching to the
771 * *next* context. Therefore we cannot retire the previous context until
772 * the next context has already started running. In fact, the below code
773 * is a bit suboptimal because the retiring can occur simply after the
774 * MI_SET_CONTEXT instead of when the next seqno has completed.
777 from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
778 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
779 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
780 * whole damn pipeline, we don't need to explicitly mark the
781 * object dirty. The only exception is that the context must be
782 * correct in case the object gets swapped out. Ideally we'd be
783 * able to defer doing this until we know the object would be
784 * swapped, but there is no way to do that yet.
786 from->legacy_hw_ctx.rcs_state->dirty = 1;
788 /* obj is kept alive until the next request by its active ref */
789 i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
790 i915_gem_context_unreference(from);
793 uninitialized = !to->legacy_hw_ctx.initialized;
794 to->legacy_hw_ctx.initialized = true;
797 i915_gem_context_reference(to);
798 engine->last_context = to;
801 if (engine->init_context) {
802 ret = engine->init_context(req);
804 DRM_ERROR("ring init context: %d\n", ret);
811 if (engine->id == RCS)
812 i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
817 * i915_switch_context() - perform a GPU context switch.
818 * @req: request for which we'll execute the context switch
820 * The context life cycle is simple. The context refcount is incremented and
821 * decremented by 1 and create and destroy. If the context is in use by the GPU,
822 * it will have a refcount > 1. This allows us to destroy the context abstract
823 * object while letting the normal object tracking destroy the backing BO.
825 * This function should not be used in execlists mode. Instead the context is
826 * switched by writing to the ELSP and requests keep a reference to their
829 int i915_switch_context(struct drm_i915_gem_request *req)
831 struct intel_engine_cs *engine = req->engine;
832 struct drm_i915_private *dev_priv = req->i915;
834 WARN_ON(i915.enable_execlists);
835 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
837 if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
838 if (req->ctx != engine->last_context) {
839 i915_gem_context_reference(req->ctx);
840 if (engine->last_context)
841 i915_gem_context_unreference(engine->last_context);
842 engine->last_context = req->ctx;
847 return do_switch(req);
850 static bool contexts_enabled(struct drm_device *dev)
852 return i915.enable_execlists || to_i915(dev)->hw_context_size;
855 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
858 struct drm_i915_gem_context_create *args = data;
859 struct drm_i915_file_private *file_priv = file->driver_priv;
860 struct intel_context *ctx;
863 if (!contexts_enabled(dev))
869 ret = i915_mutex_lock_interruptible(dev);
873 ctx = i915_gem_create_context(dev, file_priv);
874 mutex_unlock(&dev->struct_mutex);
878 args->ctx_id = ctx->user_handle;
879 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
884 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
885 struct drm_file *file)
887 struct drm_i915_gem_context_destroy *args = data;
888 struct drm_i915_file_private *file_priv = file->driver_priv;
889 struct intel_context *ctx;
895 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
898 ret = i915_mutex_lock_interruptible(dev);
902 ctx = i915_gem_context_get(file_priv, args->ctx_id);
904 mutex_unlock(&dev->struct_mutex);
908 idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
909 i915_gem_context_unreference(ctx);
910 mutex_unlock(&dev->struct_mutex);
912 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
916 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
917 struct drm_file *file)
919 struct drm_i915_file_private *file_priv = file->driver_priv;
920 struct drm_i915_gem_context_param *args = data;
921 struct intel_context *ctx;
924 ret = i915_mutex_lock_interruptible(dev);
928 ctx = i915_gem_context_get(file_priv, args->ctx_id);
930 mutex_unlock(&dev->struct_mutex);
935 switch (args->param) {
936 case I915_CONTEXT_PARAM_BAN_PERIOD:
937 args->value = ctx->hang_stats.ban_period_seconds;
939 case I915_CONTEXT_PARAM_NO_ZEROMAP:
940 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
942 case I915_CONTEXT_PARAM_GTT_SIZE:
944 args->value = ctx->ppgtt->base.total;
945 else if (to_i915(dev)->mm.aliasing_ppgtt)
946 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
948 args->value = to_i915(dev)->ggtt.base.total;
954 mutex_unlock(&dev->struct_mutex);
959 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
960 struct drm_file *file)
962 struct drm_i915_file_private *file_priv = file->driver_priv;
963 struct drm_i915_gem_context_param *args = data;
964 struct intel_context *ctx;
967 ret = i915_mutex_lock_interruptible(dev);
971 ctx = i915_gem_context_get(file_priv, args->ctx_id);
973 mutex_unlock(&dev->struct_mutex);
977 switch (args->param) {
978 case I915_CONTEXT_PARAM_BAN_PERIOD:
981 else if (args->value < ctx->hang_stats.ban_period_seconds &&
982 !capable(CAP_SYS_ADMIN))
985 ctx->hang_stats.ban_period_seconds = args->value;
987 case I915_CONTEXT_PARAM_NO_ZEROMAP:
991 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
992 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
999 mutex_unlock(&dev->struct_mutex);