drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/dma_remapping.h>
  35 #include <linux/uaccess.h>
  36
  37 #define  __EXEC_OBJECT_HAS_PIN (1<<31)
  38 #define  __EXEC_OBJECT_HAS_FENCE (1<<30)
  39 #define  __EXEC_OBJECT_NEEDS_MAP (1<<29)
  40 #define  __EXEC_OBJECT_NEEDS_BIAS (1<<28)
  41
  42 #define BATCH_OFFSET_BIAS (256*1024)
  43
  44 struct eb_vmas {
  45         struct list_head vmas;
  46         int and;
  47         union {
  48                 struct i915_vma *lut[0];
  49                 struct hlist_head buckets[0];
  50         };
  51 };
  52
  53 static struct eb_vmas *
  54 eb_create(struct drm_i915_gem_execbuffer2 *args)
  55 {
  56         struct eb_vmas *eb = NULL;
  57
  58         if (args->flags & I915_EXEC_HANDLE_LUT) {
  59                 unsigned size = args->buffer_count;
  60                 size *= sizeof(struct i915_vma *);
  61                 size += sizeof(struct eb_vmas);
  62                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  63         }
  64
  65         if (eb == NULL) {
  66                 unsigned size = args->buffer_count;
  67                 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  68                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  69                 while (count > 2*size)
  70                         count >>= 1;
  71                 eb = kzalloc(count*sizeof(struct hlist_head) +
  72                              sizeof(struct eb_vmas),
  73                              GFP_TEMPORARY);
  74                 if (eb == NULL)
  75                         return eb;
  76
  77                 eb->and = count - 1;
  78         } else
  79                 eb->and = -args->buffer_count;
  80
  81         INIT_LIST_HEAD(&eb->vmas);
  82         return eb;
  83 }
  84
  85 static void
  86 eb_reset(struct eb_vmas *eb)
  87 {
  88         if (eb->and >= 0)
  89                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
  90 }
  91
  92 static int
  93 eb_lookup_vmas(struct eb_vmas *eb,
  94                struct drm_i915_gem_exec_object2 *exec,
  95                const struct drm_i915_gem_execbuffer2 *args,
  96                struct i915_address_space *vm,
  97                struct drm_file *file)
  98 {
  99         struct drm_i915_gem_object *obj;
 100         struct list_head objects;
 101         int i, ret;
 102
 103         INIT_LIST_HEAD(&objects);
 104         spin_lock(&file->table_lock);
 105         /* Grab a reference to the object and release the lock so we can lookup
 106          * or create the VMA without using GFP_ATOMIC */
 107         for (i = 0; i < args->buffer_count; i++) {
 108                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
 109                 if (obj == NULL) {
 110                         spin_unlock(&file->table_lock);
 111                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 112                                    exec[i].handle, i);
 113                         ret = -ENOENT;
 114                         goto err;
 115                 }
 116
 117                 if (!list_empty(&obj->obj_exec_link)) {
 118                         spin_unlock(&file->table_lock);
 119                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
 120                                    obj, exec[i].handle, i);
 121                         ret = -EINVAL;
 122                         goto err;
 123                 }
 124
 125                 drm_gem_object_reference(&obj->base);
 126                 list_add_tail(&obj->obj_exec_link, &objects);
 127         }
 128         spin_unlock(&file->table_lock);
 129
 130         i = 0;
 131         while (!list_empty(&objects)) {
 132                 struct i915_vma *vma;
 133
 134                 obj = list_first_entry(&objects,
 135                                        struct drm_i915_gem_object,
 136                                        obj_exec_link);
 137
 138                 /*
 139                  * NOTE: We can leak any vmas created here when something fails
 140                  * later on. But that's no issue since vma_unbind can deal with
 141                  * vmas which are not actually bound. And since only
 142                  * lookup_or_create exists as an interface to get at the vma
 143                  * from the (obj, vm) we don't run the risk of creating
 144                  * duplicated vmas for the same vm.
 145                  */
 146                 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
 147                 if (IS_ERR(vma)) {
 148                         DRM_DEBUG("Failed to lookup VMA\n");
 149                         ret = PTR_ERR(vma);
 150                         goto err;
 151                 }
 152
 153                 /* Transfer ownership from the objects list to the vmas list. */
 154                 list_add_tail(&vma->exec_list, &eb->vmas);
 155                 list_del_init(&obj->obj_exec_link);
 156
 157                 vma->exec_entry = &exec[i];
 158                 if (eb->and < 0) {
 159                         eb->lut[i] = vma;
 160                 } else {
 161                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
 162                         vma->exec_handle = handle;
 163                         hlist_add_head(&vma->exec_node,
 164                                        &eb->buckets[handle & eb->and]);
 165                 }
 166                 ++i;
 167         }
 168
 169         return 0;
 170
 171
 172 err:
 173         while (!list_empty(&objects)) {
 174                 obj = list_first_entry(&objects,
 175                                        struct drm_i915_gem_object,
 176                                        obj_exec_link);
 177                 list_del_init(&obj->obj_exec_link);
 178                 drm_gem_object_unreference(&obj->base);
 179         }
 180         /*
 181          * Objects already transfered to the vmas list will be unreferenced by
 182          * eb_destroy.
 183          */
 184
 185         return ret;
 186 }
 187
 188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 189 {
 190         if (eb->and < 0) {
 191                 if (handle >= -eb->and)
 192                         return NULL;
 193                 return eb->lut[handle];
 194         } else {
 195                 struct hlist_head *head;
 196                 struct hlist_node *node;
 197
 198                 head = &eb->buckets[handle & eb->and];
 199                 hlist_for_each(node, head) {
 200                         struct i915_vma *vma;
 201
 202                         vma = hlist_entry(node, struct i915_vma, exec_node);
 203                         if (vma->exec_handle == handle)
 204                                 return vma;
 205                 }
 206                 return NULL;
 207         }
 208 }
 209
 210 static void
 211 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 212 {
 213         struct drm_i915_gem_exec_object2 *entry;
 214         struct drm_i915_gem_object *obj = vma->obj;
 215
 216         if (!drm_mm_node_allocated(&vma->node))
 217                 return;
 218
 219         entry = vma->exec_entry;
 220
 221         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
 222                 i915_gem_object_unpin_fence(obj);
 223
 224         if (entry->flags & __EXEC_OBJECT_HAS_PIN)
 225                 vma->pin_count--;
 226
 227         entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
 228 }
 229
 230 static void eb_destroy(struct eb_vmas *eb)
 231 {
 232         while (!list_empty(&eb->vmas)) {
 233                 struct i915_vma *vma;
 234
 235                 vma = list_first_entry(&eb->vmas,
 236                                        struct i915_vma,
 237                                        exec_list);
 238                 list_del_init(&vma->exec_list);
 239                 i915_gem_execbuffer_unreserve_vma(vma);
 240                 drm_gem_object_unreference(&vma->obj->base);
 241         }
 242         kfree(eb);
 243 }
 244
 245 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 246 {
 247         return (HAS_LLC(obj->base.dev) ||
 248                 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 249                 obj->cache_level != I915_CACHE_NONE);
 250 }
 251
 252 static int
 253 relocate_entry_cpu(struct drm_i915_gem_object *obj,
 254                    struct drm_i915_gem_relocation_entry *reloc,
 255                    uint64_t target_offset)
 256 {
 257         struct drm_device *dev = obj->base.dev;
 258         uint32_t page_offset = offset_in_page(reloc->offset);
 259         uint64_t delta = reloc->delta + target_offset;
 260         char *vaddr;
 261         int ret;
 262
 263         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 264         if (ret)
 265                 return ret;
 266
 267         vaddr = kmap_atomic(i915_gem_object_get_page(obj,
 268                                 reloc->offset >> PAGE_SHIFT));
 269         *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
 270
 271         if (INTEL_INFO(dev)->gen >= 8) {
 272                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 273
 274                 if (page_offset == 0) {
 275                         kunmap_atomic(vaddr);
 276                         vaddr = kmap_atomic(i915_gem_object_get_page(obj,
 277                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 278                 }
 279
 280                 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
 281         }
 282
 283         kunmap_atomic(vaddr);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 relocate_entry_gtt(struct drm_i915_gem_object *obj,
 290                    struct drm_i915_gem_relocation_entry *reloc,
 291                    uint64_t target_offset)
 292 {
 293         struct drm_device *dev = obj->base.dev;
 294         struct drm_i915_private *dev_priv = dev->dev_private;
 295         uint64_t delta = reloc->delta + target_offset;
 296         uint64_t offset;
 297         void __iomem *reloc_page;
 298         int ret;
 299
 300         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 301         if (ret)
 302                 return ret;
 303
 304         ret = i915_gem_object_put_fence(obj);
 305         if (ret)
 306                 return ret;
 307
 308         /* Map the page containing the relocation we're going to perform.  */
 309         offset = i915_gem_obj_ggtt_offset(obj);
 310         offset += reloc->offset;
 311         reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 312                                               offset & PAGE_MASK);
 313         iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
 314
 315         if (INTEL_INFO(dev)->gen >= 8) {
 316                 offset += sizeof(uint32_t);
 317
 318                 if (offset_in_page(offset) == 0) {
 319                         io_mapping_unmap_atomic(reloc_page);
 320                         reloc_page =
 321                                 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 322                                                          offset);
 323                 }
 324
 325                 iowrite32(upper_32_bits(delta),
 326                           reloc_page + offset_in_page(offset));
 327         }
 328
 329         io_mapping_unmap_atomic(reloc_page);
 330
 331         return 0;
 332 }
 333
 334 static void
 335 clflush_write32(void *addr, uint32_t value)
 336 {
 337         /* This is not a fast path, so KISS. */
 338         drm_clflush_virt_range(addr, sizeof(uint32_t));
 339         *(uint32_t *)addr = value;
 340         drm_clflush_virt_range(addr, sizeof(uint32_t));
 341 }
 342
 343 static int
 344 relocate_entry_clflush(struct drm_i915_gem_object *obj,
 345                        struct drm_i915_gem_relocation_entry *reloc,
 346                        uint64_t target_offset)
 347 {
 348         struct drm_device *dev = obj->base.dev;
 349         uint32_t page_offset = offset_in_page(reloc->offset);
 350         uint64_t delta = (int)reloc->delta + target_offset;
 351         char *vaddr;
 352         int ret;
 353
 354         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 355         if (ret)
 356                 return ret;
 357
 358         vaddr = kmap_atomic(i915_gem_object_get_page(obj,
 359                                 reloc->offset >> PAGE_SHIFT));
 360         clflush_write32(vaddr + page_offset, lower_32_bits(delta));
 361
 362         if (INTEL_INFO(dev)->gen >= 8) {
 363                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 364
 365                 if (page_offset == 0) {
 366                         kunmap_atomic(vaddr);
 367                         vaddr = kmap_atomic(i915_gem_object_get_page(obj,
 368                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 369                 }
 370
 371                 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
 372         }
 373
 374         kunmap_atomic(vaddr);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 381                                    struct eb_vmas *eb,
 382                                    struct drm_i915_gem_relocation_entry *reloc)
 383 {
 384         struct drm_device *dev = obj->base.dev;
 385         struct drm_gem_object *target_obj;
 386         struct drm_i915_gem_object *target_i915_obj;
 387         struct i915_vma *target_vma;
 388         uint64_t target_offset;
 389         int ret;
 390
 391         /* we've already hold a reference to all valid objects */
 392         target_vma = eb_get_vma(eb, reloc->target_handle);
 393         if (unlikely(target_vma == NULL))
 394                 return -ENOENT;
 395         target_i915_obj = target_vma->obj;
 396         target_obj = &target_vma->obj->base;
 397
 398         target_offset = target_vma->node.start;
 399
 400         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 401          * pipe_control writes because the gpu doesn't properly redirect them
 402          * through the ppgtt for non_secure batchbuffers. */
 403         if (unlikely(IS_GEN6(dev) &&
 404             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
 405                 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
 406                                     PIN_GLOBAL);
 407                 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
 408                         return ret;
 409         }
 410
 411         /* Validate that the target is in a valid r/w GPU domain */
 412         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 413                 DRM_DEBUG("reloc with multiple write domains: "
 414                           "obj %p target %d offset %d "
 415                           "read %08x write %08x",
 416                           obj, reloc->target_handle,
 417                           (int) reloc->offset,
 418                           reloc->read_domains,
 419                           reloc->write_domain);
 420                 return -EINVAL;
 421         }
 422         if (unlikely((reloc->write_domain | reloc->read_domains)
 423                      & ~I915_GEM_GPU_DOMAINS)) {
 424                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 425                           "obj %p target %d offset %d "
 426                           "read %08x write %08x",
 427                           obj, reloc->target_handle,
 428                           (int) reloc->offset,
 429                           reloc->read_domains,
 430                           reloc->write_domain);
 431                 return -EINVAL;
 432         }
 433
 434         target_obj->pending_read_domains |= reloc->read_domains;
 435         target_obj->pending_write_domain |= reloc->write_domain;
 436
 437         /* If the relocation already has the right value in it, no
 438          * more work needs to be done.
 439          */
 440         if (target_offset == reloc->presumed_offset)
 441                 return 0;
 442
 443         /* Check that the relocation address is valid... */
 444         if (unlikely(reloc->offset >
 445                 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
 446                 DRM_DEBUG("Relocation beyond object bounds: "
 447                           "obj %p target %d offset %d size %d.\n",
 448                           obj, reloc->target_handle,
 449                           (int) reloc->offset,
 450                           (int) obj->base.size);
 451                 return -EINVAL;
 452         }
 453         if (unlikely(reloc->offset & 3)) {
 454                 DRM_DEBUG("Relocation not 4-byte aligned: "
 455                           "obj %p target %d offset %d.\n",
 456                           obj, reloc->target_handle,
 457                           (int) reloc->offset);
 458                 return -EINVAL;
 459         }
 460
 461         /* We can't wait for rendering with pagefaults disabled */
 462         if (obj->active && pagefault_disabled())
 463                 return -EFAULT;
 464
 465         if (use_cpu_reloc(obj))
 466                 ret = relocate_entry_cpu(obj, reloc, target_offset);
 467         else if (obj->map_and_fenceable)
 468                 ret = relocate_entry_gtt(obj, reloc, target_offset);
 469         else if (cpu_has_clflush)
 470                 ret = relocate_entry_clflush(obj, reloc, target_offset);
 471         else {
 472                 WARN_ONCE(1, "Impossible case in relocation handling\n");
 473                 ret = -ENODEV;
 474         }
 475
 476         if (ret)
 477                 return ret;
 478
 479         /* and update the user's relocation entry */
 480         reloc->presumed_offset = target_offset;
 481
 482         return 0;
 483 }
 484
 485 static int
 486 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
 487                                  struct eb_vmas *eb)
 488 {
 489 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 490         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 491         struct drm_i915_gem_relocation_entry __user *user_relocs;
 492         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 493         int remain, ret;
 494
 495         user_relocs = to_user_ptr(entry->relocs_ptr);
 496
 497         remain = entry->relocation_count;
 498         while (remain) {
 499                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 500                 int count = remain;
 501                 if (count > ARRAY_SIZE(stack_reloc))
 502                         count = ARRAY_SIZE(stack_reloc);
 503                 remain -= count;
 504
 505                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
 506                         return -EFAULT;
 507
 508                 do {
 509                         u64 offset = r->presumed_offset;
 510
 511                         ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
 512                         if (ret)
 513                                 return ret;
 514
 515                         if (r->presumed_offset != offset &&
 516                             __copy_to_user_inatomic(&user_relocs->presumed_offset,
 517                                                     &r->presumed_offset,
 518                                                     sizeof(r->presumed_offset))) {
 519                                 return -EFAULT;
 520                         }
 521
 522                         user_relocs++;
 523                         r++;
 524                 } while (--count);
 525         }
 526
 527         return 0;
 528 #undef N_RELOC
 529 }
 530
 531 static int
 532 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
 533                                       struct eb_vmas *eb,
 534                                       struct drm_i915_gem_relocation_entry *relocs)
 535 {
 536         const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 537         int i, ret;
 538
 539         for (i = 0; i < entry->relocation_count; i++) {
 540                 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
 541                 if (ret)
 542                         return ret;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int
 549 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
 550 {
 551         struct i915_vma *vma;
 552         int ret = 0;
 553
 554         /* This is the fast path and we cannot handle a pagefault whilst
 555          * holding the struct mutex lest the user pass in the relocations
 556          * contained within a mmaped bo. For in such a case we, the page
 557          * fault handler would call i915_gem_fault() and we would try to
 558          * acquire the struct mutex again. Obviously this is bad and so
 559          * lockdep complains vehemently.
 560          */
 561         pagefault_disable();
 562         list_for_each_entry(vma, &eb->vmas, exec_list) {
 563                 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
 564                 if (ret)
 565                         break;
 566         }
 567         pagefault_enable();
 568
 569         return ret;
 570 }
 571
 572 static bool only_mappable_for_reloc(unsigned int flags)
 573 {
 574         return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
 575                 __EXEC_OBJECT_NEEDS_MAP;
 576 }
 577
 578 static int
 579 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 580                                 struct intel_engine_cs *ring,
 581                                 bool *need_reloc)
 582 {
 583         struct drm_i915_gem_object *obj = vma->obj;
 584         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 585         uint64_t flags;
 586         int ret;
 587
 588         flags = PIN_USER;
 589         if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 590                 flags |= PIN_GLOBAL;
 591
 592         if (!drm_mm_node_allocated(&vma->node)) {
 593                 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 594                  * limit address to the first 4GBs for unflagged objects.
 595                  */
 596                 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
 597                         flags |= PIN_ZONE_4G;
 598                 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 599                         flags |= PIN_GLOBAL | PIN_MAPPABLE;
 600                 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
 601                         flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 602                 if (entry->flags & EXEC_OBJECT_PINNED)
 603                         flags |= entry->offset | PIN_OFFSET_FIXED;
 604                 if ((flags & PIN_MAPPABLE) == 0)
 605                         flags |= PIN_HIGH;
 606         }
 607
 608         ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
 609         if ((ret == -ENOSPC  || ret == -E2BIG) &&
 610             only_mappable_for_reloc(entry->flags))
 611                 ret = i915_gem_object_pin(obj, vma->vm,
 612                                           entry->alignment,
 613                                           flags & ~PIN_MAPPABLE);
 614         if (ret)
 615                 return ret;
 616
 617         entry->flags |= __EXEC_OBJECT_HAS_PIN;
 618
 619         if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 620                 ret = i915_gem_object_get_fence(obj);
 621                 if (ret)
 622                         return ret;
 623
 624                 if (i915_gem_object_pin_fence(obj))
 625                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 626         }
 627
 628         if (entry->offset != vma->node.start) {
 629                 entry->offset = vma->node.start;
 630                 *need_reloc = true;
 631         }
 632
 633         if (entry->flags & EXEC_OBJECT_WRITE) {
 634                 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
 635                 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static bool
 642 need_reloc_mappable(struct i915_vma *vma)
 643 {
 644         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 645
 646         if (entry->relocation_count == 0)
 647                 return false;
 648
 649         if (!i915_is_ggtt(vma->vm))
 650                 return false;
 651
 652         /* See also use_cpu_reloc() */
 653         if (HAS_LLC(vma->obj->base.dev))
 654                 return false;
 655
 656         if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 657                 return false;
 658
 659         return true;
 660 }
 661
 662 static bool
 663 eb_vma_misplaced(struct i915_vma *vma)
 664 {
 665         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 666         struct drm_i915_gem_object *obj = vma->obj;
 667
 668         WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
 669                !i915_is_ggtt(vma->vm));
 670
 671         if (entry->alignment &&
 672             vma->node.start & (entry->alignment - 1))
 673                 return true;
 674
 675         if (entry->flags & EXEC_OBJECT_PINNED &&
 676             vma->node.start != entry->offset)
 677                 return true;
 678
 679         if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
 680             vma->node.start < BATCH_OFFSET_BIAS)
 681                 return true;
 682
 683         /* avoid costly ping-pong once a batch bo ended up non-mappable */
 684         if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
 685                 return !only_mappable_for_reloc(entry->flags);
 686
 687         if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
 688             (vma->node.start + vma->node.size - 1) >> 32)
 689                 return true;
 690
 691         return false;
 692 }
 693
 694 static int
 695 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
 696                             struct list_head *vmas,
 697                             struct intel_context *ctx,
 698                             bool *need_relocs)
 699 {
 700         struct drm_i915_gem_object *obj;
 701         struct i915_vma *vma;
 702         struct i915_address_space *vm;
 703         struct list_head ordered_vmas;
 704         struct list_head pinned_vmas;
 705         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 706         int retry;
 707
 708         i915_gem_retire_requests_ring(ring);
 709
 710         vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 711
 712         INIT_LIST_HEAD(&ordered_vmas);
 713         INIT_LIST_HEAD(&pinned_vmas);
 714         while (!list_empty(vmas)) {
 715                 struct drm_i915_gem_exec_object2 *entry;
 716                 bool need_fence, need_mappable;
 717
 718                 vma = list_first_entry(vmas, struct i915_vma, exec_list);
 719                 obj = vma->obj;
 720                 entry = vma->exec_entry;
 721
 722                 if (ctx->flags & CONTEXT_NO_ZEROMAP)
 723                         entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 724
 725                 if (!has_fenced_gpu_access)
 726                         entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 727                 need_fence =
 728                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 729                         obj->tiling_mode != I915_TILING_NONE;
 730                 need_mappable = need_fence || need_reloc_mappable(vma);
 731
 732                 if (entry->flags & EXEC_OBJECT_PINNED)
 733                         list_move_tail(&vma->exec_list, &pinned_vmas);
 734                 else if (need_mappable) {
 735                         entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 736                         list_move(&vma->exec_list, &ordered_vmas);
 737                 } else
 738                         list_move_tail(&vma->exec_list, &ordered_vmas);
 739
 740                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
 741                 obj->base.pending_write_domain = 0;
 742         }
 743         list_splice(&ordered_vmas, vmas);
 744         list_splice(&pinned_vmas, vmas);
 745
 746         /* Attempt to pin all of the buffers into the GTT.
 747          * This is done in 3 phases:
 748          *
 749          * 1a. Unbind all objects that do not match the GTT constraints for
 750          *     the execbuffer (fenceable, mappable, alignment etc).
 751          * 1b. Increment pin count for already bound objects.
 752          * 2.  Bind new objects.
 753          * 3.  Decrement pin count.
 754          *
 755          * This avoid unnecessary unbinding of later objects in order to make
 756          * room for the earlier objects *unless* we need to defragment.
 757          */
 758         retry = 0;
 759         do {
 760                 int ret = 0;
 761
 762                 /* Unbind any ill-fitting objects or pin. */
 763                 list_for_each_entry(vma, vmas, exec_list) {
 764                         if (!drm_mm_node_allocated(&vma->node))
 765                                 continue;
 766
 767                         if (eb_vma_misplaced(vma))
 768                                 ret = i915_vma_unbind(vma);
 769                         else
 770                                 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
 771                         if (ret)
 772                                 goto err;
 773                 }
 774
 775                 /* Bind fresh objects */
 776                 list_for_each_entry(vma, vmas, exec_list) {
 777                         if (drm_mm_node_allocated(&vma->node))
 778                                 continue;
 779
 780                         ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
 781                         if (ret)
 782                                 goto err;
 783                 }
 784
 785 err:
 786                 if (ret != -ENOSPC || retry++)
 787                         return ret;
 788
 789                 /* Decrement pin count for bound objects */
 790                 list_for_each_entry(vma, vmas, exec_list)
 791                         i915_gem_execbuffer_unreserve_vma(vma);
 792
 793                 ret = i915_gem_evict_vm(vm, true);
 794                 if (ret)
 795                         return ret;
 796         } while (1);
 797 }
 798
 799 static int
 800 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 801                                   struct drm_i915_gem_execbuffer2 *args,
 802                                   struct drm_file *file,
 803                                   struct intel_engine_cs *ring,
 804                                   struct eb_vmas *eb,
 805                                   struct drm_i915_gem_exec_object2 *exec,
 806                                   struct intel_context *ctx)
 807 {
 808         struct drm_i915_gem_relocation_entry *reloc;
 809         struct i915_address_space *vm;
 810         struct i915_vma *vma;
 811         bool need_relocs;
 812         int *reloc_offset;
 813         int i, total, ret;
 814         unsigned count = args->buffer_count;
 815
 816         vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 817
 818         /* We may process another execbuffer during the unlock... */
 819         while (!list_empty(&eb->vmas)) {
 820                 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
 821                 list_del_init(&vma->exec_list);
 822                 i915_gem_execbuffer_unreserve_vma(vma);
 823                 drm_gem_object_unreference(&vma->obj->base);
 824         }
 825
 826         mutex_unlock(&dev->struct_mutex);
 827
 828         total = 0;
 829         for (i = 0; i < count; i++)
 830                 total += exec[i].relocation_count;
 831
 832         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 833         reloc = drm_malloc_ab(total, sizeof(*reloc));
 834         if (reloc == NULL || reloc_offset == NULL) {
 835                 drm_free_large(reloc);
 836                 drm_free_large(reloc_offset);
 837                 mutex_lock(&dev->struct_mutex);
 838                 return -ENOMEM;
 839         }
 840
 841         total = 0;
 842         for (i = 0; i < count; i++) {
 843                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 844                 u64 invalid_offset = (u64)-1;
 845                 int j;
 846
 847                 user_relocs = to_user_ptr(exec[i].relocs_ptr);
 848
 849                 if (copy_from_user(reloc+total, user_relocs,
 850                                    exec[i].relocation_count * sizeof(*reloc))) {
 851                         ret = -EFAULT;
 852                         mutex_lock(&dev->struct_mutex);
 853                         goto err;
 854                 }
 855
 856                 /* As we do not update the known relocation offsets after
 857                  * relocating (due to the complexities in lock handling),
 858                  * we need to mark them as invalid now so that we force the
 859                  * relocation processing next time. Just in case the target
 860                  * object is evicted and then rebound into its old
 861                  * presumed_offset before the next execbuffer - if that
 862                  * happened we would make the mistake of assuming that the
 863                  * relocations were valid.
 864                  */
 865                 for (j = 0; j < exec[i].relocation_count; j++) {
 866                         if (__copy_to_user(&user_relocs[j].presumed_offset,
 867                                            &invalid_offset,
 868                                            sizeof(invalid_offset))) {
 869                                 ret = -EFAULT;
 870                                 mutex_lock(&dev->struct_mutex);
 871                                 goto err;
 872                         }
 873                 }
 874
 875                 reloc_offset[i] = total;
 876                 total += exec[i].relocation_count;
 877         }
 878
 879         ret = i915_mutex_lock_interruptible(dev);
 880         if (ret) {
 881                 mutex_lock(&dev->struct_mutex);
 882                 goto err;
 883         }
 884
 885         /* reacquire the objects */
 886         eb_reset(eb);
 887         ret = eb_lookup_vmas(eb, exec, args, vm, file);
 888         if (ret)
 889                 goto err;
 890
 891         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
 892         ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
 893         if (ret)
 894                 goto err;
 895
 896         list_for_each_entry(vma, &eb->vmas, exec_list) {
 897                 int offset = vma->exec_entry - exec;
 898                 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
 899                                                             reloc + reloc_offset[offset]);
 900                 if (ret)
 901                         goto err;
 902         }
 903
 904         /* Leave the user relocations as are, this is the painfully slow path,
 905          * and we want to avoid the complication of dropping the lock whilst
 906          * having buffers reserved in the aperture and so causing spurious
 907          * ENOSPC for random operations.
 908          */
 909
 910 err:
 911         drm_free_large(reloc);
 912         drm_free_large(reloc_offset);
 913         return ret;
 914 }
 915
 916 static int
 917 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 918                                 struct list_head *vmas)
 919 {
 920         const unsigned other_rings = ~intel_ring_flag(req->ring);
 921         struct i915_vma *vma;
 922         uint32_t flush_domains = 0;
 923         bool flush_chipset = false;
 924         int ret;
 925
 926         list_for_each_entry(vma, vmas, exec_list) {
 927                 struct drm_i915_gem_object *obj = vma->obj;
 928
 929                 if (obj->active & other_rings) {
 930                         ret = i915_gem_object_sync(obj, req->ring, &req);
 931                         if (ret)
 932                                 return ret;
 933                 }
 934
 935                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 936                         flush_chipset |= i915_gem_clflush_object(obj, false);
 937
 938                 flush_domains |= obj->base.write_domain;
 939         }
 940
 941         if (flush_chipset)
 942                 i915_gem_chipset_flush(req->ring->dev);
 943
 944         if (flush_domains & I915_GEM_DOMAIN_GTT)
 945                 wmb();
 946
 947         /* Unconditionally invalidate gpu caches and ensure that we do flush
 948          * any residual writes from the previous batch.
 949          */
 950         return intel_ring_invalidate_all_caches(req);
 951 }
 952
 953 static bool
 954 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 955 {
 956         if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
 957                 return false;
 958
 959         /* Kernel clipping was a DRI1 misfeature */
 960         if (exec->num_cliprects || exec->cliprects_ptr)
 961                 return false;
 962
 963         if (exec->DR4 == 0xffffffff) {
 964                 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 965                 exec->DR4 = 0;
 966         }
 967         if (exec->DR1 || exec->DR4)
 968                 return false;
 969
 970         if ((exec->batch_start_offset | exec->batch_len) & 0x7)
 971                 return false;
 972
 973         return true;
 974 }
 975
 976 static int
 977 validate_exec_list(struct drm_device *dev,
 978                    struct drm_i915_gem_exec_object2 *exec,
 979                    int count)
 980 {
 981         unsigned relocs_total = 0;
 982         unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
 983         unsigned invalid_flags;
 984         int i;
 985
 986         invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
 987         if (USES_FULL_PPGTT(dev))
 988                 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 989
 990         for (i = 0; i < count; i++) {
 991                 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
 992                 int length; /* limited by fault_in_pages_readable() */
 993
 994                 if (exec[i].flags & invalid_flags)
 995                         return -EINVAL;
 996
 997                 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
 998                         return -EINVAL;
 999
1000                 /* First check for malicious input causing overflow in
1001                  * the worst case where we need to allocate the entire
1002                  * relocation tree as a single array.
1003                  */
1004                 if (exec[i].relocation_count > relocs_max - relocs_total)
1005                         return -EINVAL;
1006                 relocs_total += exec[i].relocation_count;
1007
1008                 length = exec[i].relocation_count *
1009                         sizeof(struct drm_i915_gem_relocation_entry);
1010                 /*
1011                  * We must check that the entire relocation array is safe
1012                  * to read, but since we may need to update the presumed
1013                  * offsets during execution, check for full write access.
1014                  */
1015                 if (!access_ok(VERIFY_WRITE, ptr, length))
1016                         return -EFAULT;
1017
1018                 if (likely(!i915.prefault_disable)) {
1019                         if (fault_in_multipages_readable(ptr, length))
1020                                 return -EFAULT;
1021                 }
1022         }
1023
1024         return 0;
1025 }
1026
1027 static struct intel_context *
1028 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1029                           struct intel_engine_cs *ring, const u32 ctx_id)
1030 {
1031         struct intel_context *ctx = NULL;
1032         struct i915_ctx_hang_stats *hs;
1033
1034         if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1035                 return ERR_PTR(-EINVAL);
1036
1037         ctx = i915_gem_context_get(file->driver_priv, ctx_id);
1038         if (IS_ERR(ctx))
1039                 return ctx;
1040
1041         hs = &ctx->hang_stats;
1042         if (hs->banned) {
1043                 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1044                 return ERR_PTR(-EIO);
1045         }
1046
1047         if (i915.enable_execlists && !ctx->engine[ring->id].state) {
1048                 int ret = intel_lr_context_deferred_alloc(ctx, ring);
1049                 if (ret) {
1050                         DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1051                         return ERR_PTR(ret);
1052                 }
1053         }
1054
1055         return ctx;
1056 }
1057
1058 void
1059 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1060                                    struct drm_i915_gem_request *req)
1061 {
1062         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1063         struct i915_vma *vma;
1064
1065         list_for_each_entry(vma, vmas, exec_list) {
1066                 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1067                 struct drm_i915_gem_object *obj = vma->obj;
1068                 u32 old_read = obj->base.read_domains;
1069                 u32 old_write = obj->base.write_domain;
1070
1071                 obj->dirty = 1; /* be paranoid  */
1072                 obj->base.write_domain = obj->base.pending_write_domain;
1073                 if (obj->base.write_domain == 0)
1074                         obj->base.pending_read_domains |= obj->base.read_domains;
1075                 obj->base.read_domains = obj->base.pending_read_domains;
1076
1077                 i915_vma_move_to_active(vma, req);
1078                 if (obj->base.write_domain) {
1079                         i915_gem_request_assign(&obj->last_write_req, req);
1080
1081                         intel_fb_obj_invalidate(obj, ORIGIN_CS);
1082
1083                         /* update for the implicit flush after a batch */
1084                         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1085                 }
1086                 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1087                         i915_gem_request_assign(&obj->last_fenced_req, req);
1088                         if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1089                                 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1090                                 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1091                                                &dev_priv->mm.fence_list);
1092                         }
1093                 }
1094
1095                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1096         }
1097 }
1098
1099 void
1100 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1101 {
1102         /* Unconditionally force add_request to emit a full flush. */
1103         params->ring->gpu_caches_dirty = true;
1104
1105         /* Add a breadcrumb for the completion of the batch buffer */
1106         __i915_add_request(params->request, params->batch_obj, true);
1107 }
1108
1109 static int
1110 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1111                             struct drm_i915_gem_request *req)
1112 {
1113         struct intel_engine_cs *ring = req->ring;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         int ret, i;
1116
1117         if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1118                 DRM_DEBUG("sol reset is gen7/rcs only\n");
1119                 return -EINVAL;
1120         }
1121
1122         ret = intel_ring_begin(req, 4 * 3);
1123         if (ret)
1124                 return ret;
1125
1126         for (i = 0; i < 4; i++) {
1127                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1128                 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1129                 intel_ring_emit(ring, 0);
1130         }
1131
1132         intel_ring_advance(ring);
1133
1134         return 0;
1135 }
1136
1137 static struct drm_i915_gem_object*
1138 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
1139                           struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1140                           struct eb_vmas *eb,
1141                           struct drm_i915_gem_object *batch_obj,
1142                           u32 batch_start_offset,
1143                           u32 batch_len,
1144                           bool is_master)
1145 {
1146         struct drm_i915_gem_object *shadow_batch_obj;
1147         struct i915_vma *vma;
1148         int ret;
1149
1150         shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
1151                                                    PAGE_ALIGN(batch_len));
1152         if (IS_ERR(shadow_batch_obj))
1153                 return shadow_batch_obj;
1154
1155         ret = i915_parse_cmds(ring,
1156                               batch_obj,
1157                               shadow_batch_obj,
1158                               batch_start_offset,
1159                               batch_len,
1160                               is_master);
1161         if (ret)
1162                 goto err;
1163
1164         ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1165         if (ret)
1166                 goto err;
1167
1168         i915_gem_object_unpin_pages(shadow_batch_obj);
1169
1170         memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1171
1172         vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1173         vma->exec_entry = shadow_exec_entry;
1174         vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1175         drm_gem_object_reference(&shadow_batch_obj->base);
1176         list_add_tail(&vma->exec_list, &eb->vmas);
1177
1178         shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1179
1180         return shadow_batch_obj;
1181
1182 err:
1183         i915_gem_object_unpin_pages(shadow_batch_obj);
1184         if (ret == -EACCES) /* unhandled chained batch */
1185                 return batch_obj;
1186         else
1187                 return ERR_PTR(ret);
1188 }
1189
1190 int
1191 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
1192                                struct drm_i915_gem_execbuffer2 *args,
1193                                struct list_head *vmas)
1194 {
1195         struct drm_device *dev = params->dev;
1196         struct intel_engine_cs *ring = params->ring;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         u64 exec_start, exec_len;
1199         int instp_mode;
1200         u32 instp_mask;
1201         int ret;
1202
1203         ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1204         if (ret)
1205                 return ret;
1206
1207         ret = i915_switch_context(params->request);
1208         if (ret)
1209                 return ret;
1210
1211         WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
1212              "%s didn't clear reload\n", ring->name);
1213
1214         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1215         instp_mask = I915_EXEC_CONSTANTS_MASK;
1216         switch (instp_mode) {
1217         case I915_EXEC_CONSTANTS_REL_GENERAL:
1218         case I915_EXEC_CONSTANTS_ABSOLUTE:
1219         case I915_EXEC_CONSTANTS_REL_SURFACE:
1220                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1221                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1222                         return -EINVAL;
1223                 }
1224
1225                 if (instp_mode != dev_priv->relative_constants_mode) {
1226                         if (INTEL_INFO(dev)->gen < 4) {
1227                                 DRM_DEBUG("no rel constants on pre-gen4\n");
1228                                 return -EINVAL;
1229                         }
1230
1231                         if (INTEL_INFO(dev)->gen > 5 &&
1232                             instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1233                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1234                                 return -EINVAL;
1235                         }
1236
1237                         /* The HW changed the meaning on this bit on gen6 */
1238                         if (INTEL_INFO(dev)->gen >= 6)
1239                                 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1240                 }
1241                 break;
1242         default:
1243                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1244                 return -EINVAL;
1245         }
1246
1247         if (ring == &dev_priv->ring[RCS] &&
1248             instp_mode != dev_priv->relative_constants_mode) {
1249                 ret = intel_ring_begin(params->request, 4);
1250                 if (ret)
1251                         return ret;
1252
1253                 intel_ring_emit(ring, MI_NOOP);
1254                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1255                 intel_ring_emit_reg(ring, INSTPM);
1256                 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1257                 intel_ring_advance(ring);
1258
1259                 dev_priv->relative_constants_mode = instp_mode;
1260         }
1261
1262         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1263                 ret = i915_reset_gen7_sol_offsets(dev, params->request);
1264                 if (ret)
1265                         return ret;
1266         }
1267
1268         exec_len   = args->batch_len;
1269         exec_start = params->batch_obj_vm_offset +
1270                      params->args_batch_start_offset;
1271
1272         ret = ring->dispatch_execbuffer(params->request,
1273                                         exec_start, exec_len,
1274                                         params->dispatch_flags);
1275         if (ret)
1276                 return ret;
1277
1278         trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1279
1280         i915_gem_execbuffer_move_to_active(vmas, params->request);
1281         i915_gem_execbuffer_retire_commands(params);
1282
1283         return 0;
1284 }
1285
1286 /**
1287  * Find one BSD ring to dispatch the corresponding BSD command.
1288  * The Ring ID is returned.
1289  */
1290 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1291                                   struct drm_file *file)
1292 {
1293         struct drm_i915_private *dev_priv = dev->dev_private;
1294         struct drm_i915_file_private *file_priv = file->driver_priv;
1295
1296         /* Check whether the file_priv is using one ring */
1297         if (file_priv->bsd_ring)
1298                 return file_priv->bsd_ring->id;
1299         else {
1300                 /* If no, use the ping-pong mechanism to select one ring */
1301                 int ring_id;
1302
1303                 mutex_lock(&dev->struct_mutex);
1304                 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1305                         ring_id = VCS;
1306                         dev_priv->mm.bsd_ring_dispatch_index = 1;
1307                 } else {
1308                         ring_id = VCS2;
1309                         dev_priv->mm.bsd_ring_dispatch_index = 0;
1310                 }
1311                 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1312                 mutex_unlock(&dev->struct_mutex);
1313                 return ring_id;
1314         }
1315 }
1316
1317 static struct drm_i915_gem_object *
1318 eb_get_batch(struct eb_vmas *eb)
1319 {
1320         struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1321
1322         /*
1323          * SNA is doing fancy tricks with compressing batch buffers, which leads
1324          * to negative relocation deltas. Usually that works out ok since the
1325          * relocate address is still positive, except when the batch is placed
1326          * very low in the GTT. Ensure this doesn't happen.
1327          *
1328          * Note that actual hangs have only been observed on gen7, but for
1329          * paranoia do it everywhere.
1330          */
1331         if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
1332                 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1333
1334         return vma->obj;
1335 }
1336
1337 static int
1338 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1339                        struct drm_file *file,
1340                        struct drm_i915_gem_execbuffer2 *args,
1341                        struct drm_i915_gem_exec_object2 *exec)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct eb_vmas *eb;
1345         struct drm_i915_gem_object *batch_obj;
1346         struct drm_i915_gem_exec_object2 shadow_exec_entry;
1347         struct intel_engine_cs *ring;
1348         struct intel_context *ctx;
1349         struct i915_address_space *vm;
1350         struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1351         struct i915_execbuffer_params *params = &params_master;
1352         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1353         u32 dispatch_flags;
1354         int ret;
1355         bool need_relocs;
1356
1357         if (!i915_gem_check_execbuffer(args))
1358                 return -EINVAL;
1359
1360         ret = validate_exec_list(dev, exec, args->buffer_count);
1361         if (ret)
1362                 return ret;
1363
1364         dispatch_flags = 0;
1365         if (args->flags & I915_EXEC_SECURE) {
1366                 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1367                     return -EPERM;
1368
1369                 dispatch_flags |= I915_DISPATCH_SECURE;
1370         }
1371         if (args->flags & I915_EXEC_IS_PINNED)
1372                 dispatch_flags |= I915_DISPATCH_PINNED;
1373
1374         if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1375                 DRM_DEBUG("execbuf with unknown ring: %d\n",
1376                           (int)(args->flags & I915_EXEC_RING_MASK));
1377                 return -EINVAL;
1378         }
1379
1380         if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1381             ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1382                 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1383                         "bsd dispatch flags: %d\n", (int)(args->flags));
1384                 return -EINVAL;
1385         }
1386
1387         if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1388                 ring = &dev_priv->ring[RCS];
1389         else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1390                 if (HAS_BSD2(dev)) {
1391                         int ring_id;
1392
1393                         switch (args->flags & I915_EXEC_BSD_MASK) {
1394                         case I915_EXEC_BSD_DEFAULT:
1395                                 ring_id = gen8_dispatch_bsd_ring(dev, file);
1396                                 ring = &dev_priv->ring[ring_id];
1397                                 break;
1398                         case I915_EXEC_BSD_RING1:
1399                                 ring = &dev_priv->ring[VCS];
1400                                 break;
1401                         case I915_EXEC_BSD_RING2:
1402                                 ring = &dev_priv->ring[VCS2];
1403                                 break;
1404                         default:
1405                                 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1406                                           (int)(args->flags & I915_EXEC_BSD_MASK));
1407                                 return -EINVAL;
1408                         }
1409                 } else
1410                         ring = &dev_priv->ring[VCS];
1411         } else
1412                 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1413
1414         if (!intel_ring_initialized(ring)) {
1415                 DRM_DEBUG("execbuf with invalid ring: %d\n",
1416                           (int)(args->flags & I915_EXEC_RING_MASK));
1417                 return -EINVAL;
1418         }
1419
1420         if (args->buffer_count < 1) {
1421                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1422                 return -EINVAL;
1423         }
1424
1425         if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1426                 if (!HAS_RESOURCE_STREAMER(dev)) {
1427                         DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1428                         return -EINVAL;
1429                 }
1430                 if (ring->id != RCS) {
1431                         DRM_DEBUG("RS is not available on %s\n",
1432                                  ring->name);
1433                         return -EINVAL;
1434                 }
1435
1436                 dispatch_flags |= I915_DISPATCH_RS;
1437         }
1438
1439         intel_runtime_pm_get(dev_priv);
1440
1441         ret = i915_mutex_lock_interruptible(dev);
1442         if (ret)
1443                 goto pre_mutex_err;
1444
1445         ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1446         if (IS_ERR(ctx)) {
1447                 mutex_unlock(&dev->struct_mutex);
1448                 ret = PTR_ERR(ctx);
1449                 goto pre_mutex_err;
1450         }
1451
1452         i915_gem_context_reference(ctx);
1453
1454         if (ctx->ppgtt)
1455                 vm = &ctx->ppgtt->base;
1456         else
1457                 vm = &dev_priv->gtt.base;
1458
1459         memset(&params_master, 0x00, sizeof(params_master));
1460
1461         eb = eb_create(args);
1462         if (eb == NULL) {
1463                 i915_gem_context_unreference(ctx);
1464                 mutex_unlock(&dev->struct_mutex);
1465                 ret = -ENOMEM;
1466                 goto pre_mutex_err;
1467         }
1468
1469         /* Look up object handles */
1470         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1471         if (ret)
1472                 goto err;
1473
1474         /* take note of the batch buffer before we might reorder the lists */
1475         batch_obj = eb_get_batch(eb);
1476
1477         /* Move the objects en-masse into the GTT, evicting if necessary. */
1478         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1479         ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
1480         if (ret)
1481                 goto err;
1482
1483         /* The objects are in their final locations, apply the relocations. */
1484         if (need_relocs)
1485                 ret = i915_gem_execbuffer_relocate(eb);
1486         if (ret) {
1487                 if (ret == -EFAULT) {
1488                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1489                                                                 eb, exec, ctx);
1490                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1491                 }
1492                 if (ret)
1493                         goto err;
1494         }
1495
1496         /* Set the pending read domains for the batch buffer to COMMAND */
1497         if (batch_obj->base.pending_write_domain) {
1498                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1499                 ret = -EINVAL;
1500                 goto err;
1501         }
1502
1503         params->args_batch_start_offset = args->batch_start_offset;
1504         if (i915_needs_cmd_parser(ring) && args->batch_len) {
1505                 struct drm_i915_gem_object *parsed_batch_obj;
1506
1507                 parsed_batch_obj = i915_gem_execbuffer_parse(ring,
1508                                                       &shadow_exec_entry,
1509                                                       eb,
1510                                                       batch_obj,
1511                                                       args->batch_start_offset,
1512                                                       args->batch_len,
1513                                                       file->is_master);
1514                 if (IS_ERR(parsed_batch_obj)) {
1515                         ret = PTR_ERR(parsed_batch_obj);
1516                         goto err;
1517                 }
1518
1519                 /*
1520                  * parsed_batch_obj == batch_obj means batch not fully parsed:
1521                  * Accept, but don't promote to secure.
1522                  */
1523
1524                 if (parsed_batch_obj != batch_obj) {
1525                         /*
1526                          * Batch parsed and accepted:
1527                          *
1528                          * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1529                          * bit from MI_BATCH_BUFFER_START commands issued in
1530                          * the dispatch_execbuffer implementations. We
1531                          * specifically don't want that set on batches the
1532                          * command parser has accepted.
1533                          */
1534                         dispatch_flags |= I915_DISPATCH_SECURE;
1535                         params->args_batch_start_offset = 0;
1536                         batch_obj = parsed_batch_obj;
1537                 }
1538         }
1539
1540         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1541
1542         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1543          * batch" bit. Hence we need to pin secure batches into the global gtt.
1544          * hsw should have this fixed, but bdw mucks it up again. */
1545         if (dispatch_flags & I915_DISPATCH_SECURE) {
1546                 /*
1547                  * So on first glance it looks freaky that we pin the batch here
1548                  * outside of the reservation loop. But:
1549                  * - The batch is already pinned into the relevant ppgtt, so we
1550                  *   already have the backing storage fully allocated.
1551                  * - No other BO uses the global gtt (well contexts, but meh),
1552                  *   so we don't really have issues with multiple objects not
1553                  *   fitting due to fragmentation.
1554                  * So this is actually safe.
1555                  */
1556                 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1557                 if (ret)
1558                         goto err;
1559
1560                 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1561         } else
1562                 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1563
1564         /* Allocate a request for this batch buffer nice and early. */
1565         ret = i915_gem_request_alloc(ring, ctx, &params->request);
1566         if (ret)
1567                 goto err_batch_unpin;
1568
1569         ret = i915_gem_request_add_to_client(params->request, file);
1570         if (ret)
1571                 goto err_batch_unpin;
1572
1573         /*
1574          * Save assorted stuff away to pass through to *_submission().
1575          * NB: This data should be 'persistent' and not local as it will
1576          * kept around beyond the duration of the IOCTL once the GPU
1577          * scheduler arrives.
1578          */
1579         params->dev                     = dev;
1580         params->file                    = file;
1581         params->ring                    = ring;
1582         params->dispatch_flags          = dispatch_flags;
1583         params->batch_obj               = batch_obj;
1584         params->ctx                     = ctx;
1585
1586         ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
1587
1588 err_batch_unpin:
1589         /*
1590          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1591          * batch vma for correctness. For less ugly and less fragility this
1592          * needs to be adjusted to also track the ggtt batch vma properly as
1593          * active.
1594          */
1595         if (dispatch_flags & I915_DISPATCH_SECURE)
1596                 i915_gem_object_ggtt_unpin(batch_obj);
1597
1598 err:
1599         /* the request owns the ref now */
1600         i915_gem_context_unreference(ctx);
1601         eb_destroy(eb);
1602
1603         /*
1604          * If the request was created but not successfully submitted then it
1605          * must be freed again. If it was submitted then it is being tracked
1606          * on the active request list and no clean up is required here.
1607          */
1608         if (ret && params->request)
1609                 i915_gem_request_cancel(params->request);
1610
1611         mutex_unlock(&dev->struct_mutex);
1612
1613 pre_mutex_err:
1614         /* intel_gpu_busy should also get a ref, so it will free when the device
1615          * is really idle. */
1616         intel_runtime_pm_put(dev_priv);
1617         return ret;
1618 }
1619
1620 /*
1621  * Legacy execbuffer just creates an exec2 list from the original exec object
1622  * list array and passes it to the real function.
1623  */
1624 int
1625 i915_gem_execbuffer(struct drm_device *dev, void *data,
1626                     struct drm_file *file)
1627 {
1628         struct drm_i915_gem_execbuffer *args = data;
1629         struct drm_i915_gem_execbuffer2 exec2;
1630         struct drm_i915_gem_exec_object *exec_list = NULL;
1631         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1632         int ret, i;
1633
1634         if (args->buffer_count < 1) {
1635                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1636                 return -EINVAL;
1637         }
1638
1639         /* Copy in the exec list from userland */
1640         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1641         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1642         if (exec_list == NULL || exec2_list == NULL) {
1643                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1644                           args->buffer_count);
1645                 drm_free_large(exec_list);
1646                 drm_free_large(exec2_list);
1647                 return -ENOMEM;
1648         }
1649         ret = copy_from_user(exec_list,
1650                              to_user_ptr(args->buffers_ptr),
1651                              sizeof(*exec_list) * args->buffer_count);
1652         if (ret != 0) {
1653                 DRM_DEBUG("copy %d exec entries failed %d\n",
1654                           args->buffer_count, ret);
1655                 drm_free_large(exec_list);
1656                 drm_free_large(exec2_list);
1657                 return -EFAULT;
1658         }
1659
1660         for (i = 0; i < args->buffer_count; i++) {
1661                 exec2_list[i].handle = exec_list[i].handle;
1662                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1663                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1664                 exec2_list[i].alignment = exec_list[i].alignment;
1665                 exec2_list[i].offset = exec_list[i].offset;
1666                 if (INTEL_INFO(dev)->gen < 4)
1667                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1668                 else
1669                         exec2_list[i].flags = 0;
1670         }
1671
1672         exec2.buffers_ptr = args->buffers_ptr;
1673         exec2.buffer_count = args->buffer_count;
1674         exec2.batch_start_offset = args->batch_start_offset;
1675         exec2.batch_len = args->batch_len;
1676         exec2.DR1 = args->DR1;
1677         exec2.DR4 = args->DR4;
1678         exec2.num_cliprects = args->num_cliprects;
1679         exec2.cliprects_ptr = args->cliprects_ptr;
1680         exec2.flags = I915_EXEC_RENDER;
1681         i915_execbuffer2_set_context_id(exec2, 0);
1682
1683         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1684         if (!ret) {
1685                 struct drm_i915_gem_exec_object __user *user_exec_list =
1686                         to_user_ptr(args->buffers_ptr);
1687
1688                 /* Copy the new buffer offsets back to the user's exec list. */
1689                 for (i = 0; i < args->buffer_count; i++) {
1690                         ret = __copy_to_user(&user_exec_list[i].offset,
1691                                              &exec2_list[i].offset,
1692                                              sizeof(user_exec_list[i].offset));
1693                         if (ret) {
1694                                 ret = -EFAULT;
1695                                 DRM_DEBUG("failed to copy %d exec entries "
1696                                           "back to user (%d)\n",
1697                                           args->buffer_count, ret);
1698                                 break;
1699                         }
1700                 }
1701         }
1702
1703         drm_free_large(exec_list);
1704         drm_free_large(exec2_list);
1705         return ret;
1706 }
1707
1708 int
1709 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1710                      struct drm_file *file)
1711 {
1712         struct drm_i915_gem_execbuffer2 *args = data;
1713         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1714         int ret;
1715
1716         if (args->buffer_count < 1 ||
1717             args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1718                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1719                 return -EINVAL;
1720         }
1721
1722         if (args->rsvd2 != 0) {
1723                 DRM_DEBUG("dirty rvsd2 field\n");
1724                 return -EINVAL;
1725         }
1726
1727         exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1728                              GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1729         if (exec2_list == NULL)
1730                 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1731                                            args->buffer_count);
1732         if (exec2_list == NULL) {
1733                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1734                           args->buffer_count);
1735                 return -ENOMEM;
1736         }
1737         ret = copy_from_user(exec2_list,
1738                              to_user_ptr(args->buffers_ptr),
1739                              sizeof(*exec2_list) * args->buffer_count);
1740         if (ret != 0) {
1741                 DRM_DEBUG("copy %d exec entries failed %d\n",
1742                           args->buffer_count, ret);
1743                 drm_free_large(exec2_list);
1744                 return -EFAULT;
1745         }
1746
1747         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1748         if (!ret) {
1749                 /* Copy the new buffer offsets back to the user's exec list. */
1750                 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1751                                    to_user_ptr(args->buffers_ptr);
1752                 int i;
1753
1754                 for (i = 0; i < args->buffer_count; i++) {
1755                         ret = __copy_to_user(&user_exec_list[i].offset,
1756                                              &exec2_list[i].offset,
1757                                              sizeof(user_exec_list[i].offset));
1758                         if (ret) {
1759                                 ret = -EFAULT;
1760                                 DRM_DEBUG("failed to copy %d exec entries "
1761                                           "back to user\n",
1762                                           args->buffer_count);
1763                                 break;
1764                         }
1765                 }
1766         }
1767
1768         drm_free_large(exec2_list);
1769         return ret;
1770 }