2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/dma_remapping.h>
37 struct change_domains {
38 uint32_t invalidate_domains;
39 uint32_t flush_domains;
45 * Set the next domain for the specified object. This
46 * may not actually perform the necessary flushing/invaliding though,
47 * as that may want to be batched with other set_domain operations
49 * This is (we hope) the only really tricky part of gem. The goal
50 * is fairly simple -- track which caches hold bits of the object
51 * and make sure they remain coherent. A few concrete examples may
52 * help to explain how it works. For shorthand, we use the notation
53 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
54 * a pair of read and write domain masks.
56 * Case 1: the batch buffer
62 * 5. Unmapped from GTT
65 * Let's take these a step at a time
68 * Pages allocated from the kernel may still have
69 * cache contents, so we set them to (CPU, CPU) always.
70 * 2. Written by CPU (using pwrite)
71 * The pwrite function calls set_domain (CPU, CPU) and
72 * this function does nothing (as nothing changes)
74 * This function asserts that the object is not
75 * currently in any GPU-based read or write domains
77 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
78 * As write_domain is zero, this function adds in the
79 * current read domains (CPU+COMMAND, 0).
80 * flush_domains is set to CPU.
81 * invalidate_domains is set to COMMAND
82 * clflush is run to get data out of the CPU caches
83 * then i915_dev_set_domain calls i915_gem_flush to
84 * emit an MI_FLUSH and drm_agp_chipset_flush
85 * 5. Unmapped from GTT
86 * i915_gem_object_unbind calls set_domain (CPU, CPU)
87 * flush_domains and invalidate_domains end up both zero
88 * so no flushing/invalidating happens
92 * Case 2: The shared render buffer
96 * 3. Read/written by GPU
97 * 4. set_domain to (CPU,CPU)
98 * 5. Read/written by CPU
99 * 6. Read/written by GPU
102 * Same as last example, (CPU, CPU)
104 * Nothing changes (assertions find that it is not in the GPU)
105 * 3. Read/written by GPU
106 * execbuffer calls set_domain (RENDER, RENDER)
107 * flush_domains gets CPU
108 * invalidate_domains gets GPU
110 * MI_FLUSH and drm_agp_chipset_flush
111 * 4. set_domain (CPU, CPU)
112 * flush_domains gets GPU
113 * invalidate_domains gets CPU
114 * wait_rendering (obj) to make sure all drawing is complete.
115 * This will include an MI_FLUSH to get the data from GPU
117 * clflush (obj) to invalidate the CPU cache
118 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
119 * 5. Read/written by CPU
120 * cache lines are loaded and dirtied
121 * 6. Read written by GPU
122 * Same as last GPU access
124 * Case 3: The constant buffer
129 * 4. Updated (written) by CPU again
138 * flush_domains = CPU
139 * invalidate_domains = RENDER
142 * drm_agp_chipset_flush
143 * 4. Updated (written) by CPU again
145 * flush_domains = 0 (no previous write domain)
146 * invalidate_domains = 0 (no new read domains)
149 * flush_domains = CPU
150 * invalidate_domains = RENDER
153 * drm_agp_chipset_flush
156 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
157 struct intel_ring_buffer *ring,
158 struct change_domains *cd)
160 uint32_t invalidate_domains = 0, flush_domains = 0;
163 * If the object isn't moving to a new write domain,
164 * let the object stay in multiple read domains
166 if (obj->base.pending_write_domain == 0)
167 obj->base.pending_read_domains |= obj->base.read_domains;
170 * Flush the current write domain if
171 * the new read domains don't match. Invalidate
172 * any read domains which differ from the old
175 if (obj->base.write_domain &&
176 (((obj->base.write_domain != obj->base.pending_read_domains ||
177 obj->ring != ring)) ||
178 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
179 flush_domains |= obj->base.write_domain;
180 invalidate_domains |=
181 obj->base.pending_read_domains & ~obj->base.write_domain;
184 * Invalidate any read caches which may have
185 * stale data. That is, any new read domains.
187 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
188 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
189 i915_gem_clflush_object(obj);
191 if (obj->base.pending_write_domain)
192 cd->flips |= atomic_read(&obj->pending_flip);
194 /* The actual obj->write_domain will be updated with
195 * pending_write_domain after we emit the accumulated flush for all
196 * of our domain changes in execbuffers (which clears objects'
197 * write_domains). So if we have a current write domain that we
198 * aren't changing, set pending_write_domain to that.
200 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
201 obj->base.pending_write_domain = obj->base.write_domain;
203 cd->invalidate_domains |= invalidate_domains;
204 cd->flush_domains |= flush_domains;
205 if (flush_domains & I915_GEM_GPU_DOMAINS)
206 cd->flush_rings |= intel_ring_flag(obj->ring);
207 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
208 cd->flush_rings |= intel_ring_flag(ring);
213 struct hlist_head buckets[0];
216 static struct eb_objects *
219 struct eb_objects *eb;
220 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
223 eb = kzalloc(count*sizeof(struct hlist_head) +
224 sizeof(struct eb_objects),
234 eb_reset(struct eb_objects *eb)
236 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
240 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
242 hlist_add_head(&obj->exec_node,
243 &eb->buckets[obj->exec_handle & eb->and]);
246 static struct drm_i915_gem_object *
247 eb_get_object(struct eb_objects *eb, unsigned long handle)
249 struct hlist_head *head;
250 struct hlist_node *node;
251 struct drm_i915_gem_object *obj;
253 head = &eb->buckets[handle & eb->and];
254 hlist_for_each(node, head) {
255 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
256 if (obj->exec_handle == handle)
264 eb_destroy(struct eb_objects *eb)
269 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
271 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
272 obj->cache_level != I915_CACHE_NONE);
276 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
277 struct eb_objects *eb,
278 struct drm_i915_gem_relocation_entry *reloc)
280 struct drm_device *dev = obj->base.dev;
281 struct drm_gem_object *target_obj;
282 struct drm_i915_gem_object *target_i915_obj;
283 uint32_t target_offset;
286 /* we've already hold a reference to all valid objects */
287 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
288 if (unlikely(target_obj == NULL))
291 target_i915_obj = to_intel_bo(target_obj);
292 target_offset = target_i915_obj->gtt_offset;
294 /* The target buffer should have appeared before us in the
295 * exec_object list, so it should have a GTT space bound by now.
297 if (unlikely(target_offset == 0)) {
298 DRM_DEBUG("No GTT space found for object %d\n",
299 reloc->target_handle);
303 /* Validate that the target is in a valid r/w GPU domain */
304 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
305 DRM_DEBUG("reloc with multiple write domains: "
306 "obj %p target %d offset %d "
307 "read %08x write %08x",
308 obj, reloc->target_handle,
311 reloc->write_domain);
314 if (unlikely((reloc->write_domain | reloc->read_domains)
315 & ~I915_GEM_GPU_DOMAINS)) {
316 DRM_DEBUG("reloc with read/write non-GPU domains: "
317 "obj %p target %d offset %d "
318 "read %08x write %08x",
319 obj, reloc->target_handle,
322 reloc->write_domain);
325 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
326 reloc->write_domain != target_obj->pending_write_domain)) {
327 DRM_DEBUG("Write domain conflict: "
328 "obj %p target %d offset %d "
329 "new %08x old %08x\n",
330 obj, reloc->target_handle,
333 target_obj->pending_write_domain);
337 target_obj->pending_read_domains |= reloc->read_domains;
338 target_obj->pending_write_domain |= reloc->write_domain;
340 /* If the relocation already has the right value in it, no
341 * more work needs to be done.
343 if (target_offset == reloc->presumed_offset)
346 /* Check that the relocation address is valid... */
347 if (unlikely(reloc->offset > obj->base.size - 4)) {
348 DRM_DEBUG("Relocation beyond object bounds: "
349 "obj %p target %d offset %d size %d.\n",
350 obj, reloc->target_handle,
352 (int) obj->base.size);
355 if (unlikely(reloc->offset & 3)) {
356 DRM_DEBUG("Relocation not 4-byte aligned: "
357 "obj %p target %d offset %d.\n",
358 obj, reloc->target_handle,
359 (int) reloc->offset);
363 /* We can't wait for rendering with pagefaults disabled */
364 if (obj->active && in_atomic())
367 reloc->delta += target_offset;
368 if (use_cpu_reloc(obj)) {
369 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
372 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
376 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
377 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
378 kunmap_atomic(vaddr);
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 uint32_t __iomem *reloc_entry;
382 void __iomem *reloc_page;
384 ret = i915_gem_object_set_to_gtt_domain(obj, true);
388 ret = i915_gem_object_put_fence(obj);
392 /* Map the page containing the relocation we're going to perform. */
393 reloc->offset += obj->gtt_offset;
394 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
395 reloc->offset & PAGE_MASK);
396 reloc_entry = (uint32_t __iomem *)
397 (reloc_page + (reloc->offset & ~PAGE_MASK));
398 iowrite32(reloc->delta, reloc_entry);
399 io_mapping_unmap_atomic(reloc_page);
402 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
403 * pipe_control writes because the gpu doesn't properly redirect them
404 * through the ppgtt for non_secure batchbuffers. */
405 if (unlikely(IS_GEN6(dev) &&
406 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
407 !target_i915_obj->has_global_gtt_mapping)) {
408 i915_gem_gtt_bind_object(target_i915_obj,
409 target_i915_obj->cache_level);
412 /* and update the user's relocation entry */
413 reloc->presumed_offset = target_offset;
419 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
420 struct eb_objects *eb)
422 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
423 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
424 struct drm_i915_gem_relocation_entry __user *user_relocs;
425 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
428 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
430 remain = entry->relocation_count;
432 struct drm_i915_gem_relocation_entry *r = stack_reloc;
434 if (count > ARRAY_SIZE(stack_reloc))
435 count = ARRAY_SIZE(stack_reloc);
438 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
442 u64 offset = r->presumed_offset;
444 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
448 if (r->presumed_offset != offset &&
449 __copy_to_user_inatomic(&user_relocs->presumed_offset,
451 sizeof(r->presumed_offset))) {
465 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
466 struct eb_objects *eb,
467 struct drm_i915_gem_relocation_entry *relocs)
469 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
472 for (i = 0; i < entry->relocation_count; i++) {
473 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
482 i915_gem_execbuffer_relocate(struct drm_device *dev,
483 struct eb_objects *eb,
484 struct list_head *objects)
486 struct drm_i915_gem_object *obj;
489 /* This is the fast path and we cannot handle a pagefault whilst
490 * holding the struct mutex lest the user pass in the relocations
491 * contained within a mmaped bo. For in such a case we, the page
492 * fault handler would call i915_gem_fault() and we would try to
493 * acquire the struct mutex again. Obviously this is bad and so
494 * lockdep complains vehemently.
497 list_for_each_entry(obj, objects, exec_list) {
498 ret = i915_gem_execbuffer_relocate_object(obj, eb);
507 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
510 need_reloc_mappable(struct drm_i915_gem_object *obj)
512 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
513 return entry->relocation_count && !use_cpu_reloc(obj);
517 pin_and_fence_object(struct drm_i915_gem_object *obj,
518 struct intel_ring_buffer *ring)
520 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
521 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
522 bool need_fence, need_mappable;
526 has_fenced_gpu_access &&
527 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
528 obj->tiling_mode != I915_TILING_NONE;
529 need_mappable = need_fence || need_reloc_mappable(obj);
531 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
535 if (has_fenced_gpu_access) {
536 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
537 ret = i915_gem_object_get_fence(obj);
541 if (i915_gem_object_pin_fence(obj))
542 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
544 obj->pending_fenced_gpu_access = true;
548 entry->offset = obj->gtt_offset;
552 i915_gem_object_unpin(obj);
557 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
558 struct drm_file *file,
559 struct list_head *objects)
561 drm_i915_private_t *dev_priv = ring->dev->dev_private;
562 struct drm_i915_gem_object *obj;
564 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
565 struct list_head ordered_objects;
567 INIT_LIST_HEAD(&ordered_objects);
568 while (!list_empty(objects)) {
569 struct drm_i915_gem_exec_object2 *entry;
570 bool need_fence, need_mappable;
572 obj = list_first_entry(objects,
573 struct drm_i915_gem_object,
575 entry = obj->exec_entry;
578 has_fenced_gpu_access &&
579 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
580 obj->tiling_mode != I915_TILING_NONE;
581 need_mappable = need_fence || need_reloc_mappable(obj);
584 list_move(&obj->exec_list, &ordered_objects);
586 list_move_tail(&obj->exec_list, &ordered_objects);
588 obj->base.pending_read_domains = 0;
589 obj->base.pending_write_domain = 0;
591 list_splice(&ordered_objects, objects);
593 /* Attempt to pin all of the buffers into the GTT.
594 * This is done in 3 phases:
596 * 1a. Unbind all objects that do not match the GTT constraints for
597 * the execbuffer (fenceable, mappable, alignment etc).
598 * 1b. Increment pin count for already bound objects.
599 * 2. Bind new objects.
600 * 3. Decrement pin count.
602 * This avoid unnecessary unbinding of later objects in order to makr
603 * room for the earlier objects *unless* we need to defragment.
609 /* Unbind any ill-fitting objects or pin. */
610 list_for_each_entry(obj, objects, exec_list) {
611 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
612 bool need_fence, need_mappable;
618 has_fenced_gpu_access &&
619 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
620 obj->tiling_mode != I915_TILING_NONE;
621 need_mappable = need_fence || need_reloc_mappable(obj);
623 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
624 (need_mappable && !obj->map_and_fenceable))
625 ret = i915_gem_object_unbind(obj);
627 ret = pin_and_fence_object(obj, ring);
632 /* Bind fresh objects */
633 list_for_each_entry(obj, objects, exec_list) {
637 ret = pin_and_fence_object(obj, ring);
641 /* This can potentially raise a harmless
642 * -EINVAL if we failed to bind in the above
643 * call. It cannot raise -EINTR since we know
644 * that the bo is freshly bound and so will
645 * not need to be flushed or waited upon.
647 ret_ignore = i915_gem_object_unbind(obj);
649 WARN_ON(obj->gtt_space);
654 /* Decrement pin count for bound objects */
655 list_for_each_entry(obj, objects, exec_list) {
656 struct drm_i915_gem_exec_object2 *entry;
661 entry = obj->exec_entry;
662 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
663 i915_gem_object_unpin_fence(obj);
664 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
667 i915_gem_object_unpin(obj);
669 /* ... and ensure ppgtt mapping exist if needed. */
670 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
671 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
672 obj, obj->cache_level);
674 obj->has_aliasing_ppgtt_mapping = 1;
678 if (ret != -ENOSPC || retry > 1)
681 /* First attempt, just clear anything that is purgeable.
682 * Second attempt, clear the entire GTT.
684 ret = i915_gem_evict_everything(ring->dev, retry == 0);
692 list_for_each_entry_continue_reverse(obj, objects, exec_list) {
693 struct drm_i915_gem_exec_object2 *entry;
698 entry = obj->exec_entry;
699 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
700 i915_gem_object_unpin_fence(obj);
701 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
704 i915_gem_object_unpin(obj);
711 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
712 struct drm_file *file,
713 struct intel_ring_buffer *ring,
714 struct list_head *objects,
715 struct eb_objects *eb,
716 struct drm_i915_gem_exec_object2 *exec,
719 struct drm_i915_gem_relocation_entry *reloc;
720 struct drm_i915_gem_object *obj;
724 /* We may process another execbuffer during the unlock... */
725 while (!list_empty(objects)) {
726 obj = list_first_entry(objects,
727 struct drm_i915_gem_object,
729 list_del_init(&obj->exec_list);
730 drm_gem_object_unreference(&obj->base);
733 mutex_unlock(&dev->struct_mutex);
736 for (i = 0; i < count; i++)
737 total += exec[i].relocation_count;
739 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
740 reloc = drm_malloc_ab(total, sizeof(*reloc));
741 if (reloc == NULL || reloc_offset == NULL) {
742 drm_free_large(reloc);
743 drm_free_large(reloc_offset);
744 mutex_lock(&dev->struct_mutex);
749 for (i = 0; i < count; i++) {
750 struct drm_i915_gem_relocation_entry __user *user_relocs;
752 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
754 if (copy_from_user(reloc+total, user_relocs,
755 exec[i].relocation_count * sizeof(*reloc))) {
757 mutex_lock(&dev->struct_mutex);
761 reloc_offset[i] = total;
762 total += exec[i].relocation_count;
765 ret = i915_mutex_lock_interruptible(dev);
767 mutex_lock(&dev->struct_mutex);
771 /* reacquire the objects */
773 for (i = 0; i < count; i++) {
774 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
776 if (&obj->base == NULL) {
777 DRM_DEBUG("Invalid object handle %d at index %d\n",
783 list_add_tail(&obj->exec_list, objects);
784 obj->exec_handle = exec[i].handle;
785 obj->exec_entry = &exec[i];
786 eb_add_object(eb, obj);
789 ret = i915_gem_execbuffer_reserve(ring, file, objects);
793 list_for_each_entry(obj, objects, exec_list) {
794 int offset = obj->exec_entry - exec;
795 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
796 reloc + reloc_offset[offset]);
801 /* Leave the user relocations as are, this is the painfully slow path,
802 * and we want to avoid the complication of dropping the lock whilst
803 * having buffers reserved in the aperture and so causing spurious
804 * ENOSPC for random operations.
808 drm_free_large(reloc);
809 drm_free_large(reloc_offset);
814 i915_gem_execbuffer_flush(struct drm_device *dev,
815 uint32_t invalidate_domains,
816 uint32_t flush_domains)
818 if (flush_domains & I915_GEM_DOMAIN_CPU)
819 intel_gtt_chipset_flush();
821 if (flush_domains & I915_GEM_DOMAIN_GTT)
826 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
828 u32 plane, flip_mask;
831 /* Check for any pending flips. As we only maintain a flip queue depth
832 * of 1, we can simply insert a WAIT for the next display flip prior
833 * to executing the batch and avoid stalling the CPU.
836 for (plane = 0; flips >> plane; plane++) {
837 if (((flips >> plane) & 1) == 0)
841 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
843 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
845 ret = intel_ring_begin(ring, 2);
849 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
850 intel_ring_emit(ring, MI_NOOP);
851 intel_ring_advance(ring);
859 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
860 struct list_head *objects)
862 struct drm_i915_gem_object *obj;
863 struct change_domains cd;
866 memset(&cd, 0, sizeof(cd));
867 list_for_each_entry(obj, objects, exec_list)
868 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
870 if (cd.invalidate_domains | cd.flush_domains) {
871 i915_gem_execbuffer_flush(ring->dev,
872 cd.invalidate_domains,
877 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
882 list_for_each_entry(obj, objects, exec_list) {
883 ret = i915_gem_object_sync(obj, ring);
888 /* Unconditionally invalidate gpu caches and ensure that we do flush
889 * any residual writes from the previous batch.
891 ret = i915_gem_flush_ring(ring,
892 I915_GEM_GPU_DOMAINS,
893 ring->gpu_caches_dirty ? I915_GEM_GPU_DOMAINS : 0);
897 ring->gpu_caches_dirty = false;
902 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
904 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
908 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
913 for (i = 0; i < count; i++) {
914 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
915 int length; /* limited by fault_in_pages_readable() */
917 /* First check for malicious input causing overflow */
918 if (exec[i].relocation_count >
919 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
922 length = exec[i].relocation_count *
923 sizeof(struct drm_i915_gem_relocation_entry);
924 if (!access_ok(VERIFY_READ, ptr, length))
927 /* we may also need to update the presumed offsets */
928 if (!access_ok(VERIFY_WRITE, ptr, length))
931 if (fault_in_multipages_readable(ptr, length))
939 i915_gem_execbuffer_move_to_active(struct list_head *objects,
940 struct intel_ring_buffer *ring,
943 struct drm_i915_gem_object *obj;
945 list_for_each_entry(obj, objects, exec_list) {
946 u32 old_read = obj->base.read_domains;
947 u32 old_write = obj->base.write_domain;
950 obj->base.read_domains = obj->base.pending_read_domains;
951 obj->base.write_domain = obj->base.pending_write_domain;
952 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
954 i915_gem_object_move_to_active(obj, ring, seqno);
955 if (obj->base.write_domain) {
957 obj->pending_gpu_write = true;
958 list_move_tail(&obj->gpu_write_list,
959 &ring->gpu_write_list);
960 if (obj->pin_count) /* check for potential scanout */
961 intel_mark_busy(ring->dev, obj);
964 trace_i915_gem_object_change_domain(obj, old_read, old_write);
967 intel_mark_busy(ring->dev, NULL);
971 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
972 struct drm_file *file,
973 struct intel_ring_buffer *ring)
975 struct drm_i915_gem_request *request;
977 /* Unconditionally force add_request to emit a full flush. */
978 ring->gpu_caches_dirty = true;
980 /* Add a breadcrumb for the completion of the batch buffer */
981 request = kzalloc(sizeof(*request), GFP_KERNEL);
982 if (request == NULL || i915_add_request(ring, file, request)) {
988 i915_reset_gen7_sol_offsets(struct drm_device *dev,
989 struct intel_ring_buffer *ring)
991 drm_i915_private_t *dev_priv = dev->dev_private;
994 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
997 ret = intel_ring_begin(ring, 4 * 3);
1001 for (i = 0; i < 4; i++) {
1002 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1003 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1004 intel_ring_emit(ring, 0);
1007 intel_ring_advance(ring);
1013 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1014 struct drm_file *file,
1015 struct drm_i915_gem_execbuffer2 *args,
1016 struct drm_i915_gem_exec_object2 *exec)
1018 drm_i915_private_t *dev_priv = dev->dev_private;
1019 struct list_head objects;
1020 struct eb_objects *eb;
1021 struct drm_i915_gem_object *batch_obj;
1022 struct drm_clip_rect *cliprects = NULL;
1023 struct intel_ring_buffer *ring;
1024 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1025 u32 exec_start, exec_len;
1030 if (!i915_gem_check_execbuffer(args)) {
1031 DRM_DEBUG("execbuf with invalid offset/length\n");
1035 ret = validate_exec_list(exec, args->buffer_count);
1039 switch (args->flags & I915_EXEC_RING_MASK) {
1040 case I915_EXEC_DEFAULT:
1041 case I915_EXEC_RENDER:
1042 ring = &dev_priv->ring[RCS];
1045 ring = &dev_priv->ring[VCS];
1047 DRM_DEBUG("Ring %s doesn't support contexts\n",
1053 ring = &dev_priv->ring[BCS];
1055 DRM_DEBUG("Ring %s doesn't support contexts\n",
1061 DRM_DEBUG("execbuf with unknown ring: %d\n",
1062 (int)(args->flags & I915_EXEC_RING_MASK));
1065 if (!intel_ring_initialized(ring)) {
1066 DRM_DEBUG("execbuf with invalid ring: %d\n",
1067 (int)(args->flags & I915_EXEC_RING_MASK));
1071 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1072 mask = I915_EXEC_CONSTANTS_MASK;
1074 case I915_EXEC_CONSTANTS_REL_GENERAL:
1075 case I915_EXEC_CONSTANTS_ABSOLUTE:
1076 case I915_EXEC_CONSTANTS_REL_SURFACE:
1077 if (ring == &dev_priv->ring[RCS] &&
1078 mode != dev_priv->relative_constants_mode) {
1079 if (INTEL_INFO(dev)->gen < 4)
1082 if (INTEL_INFO(dev)->gen > 5 &&
1083 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1086 /* The HW changed the meaning on this bit on gen6 */
1087 if (INTEL_INFO(dev)->gen >= 6)
1088 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1092 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1096 if (args->buffer_count < 1) {
1097 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1101 if (args->num_cliprects != 0) {
1102 if (ring != &dev_priv->ring[RCS]) {
1103 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1107 if (INTEL_INFO(dev)->gen >= 5) {
1108 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1112 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1113 DRM_DEBUG("execbuf with %u cliprects\n",
1114 args->num_cliprects);
1118 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1120 if (cliprects == NULL) {
1125 if (copy_from_user(cliprects,
1126 (struct drm_clip_rect __user *)(uintptr_t)
1127 args->cliprects_ptr,
1128 sizeof(*cliprects)*args->num_cliprects)) {
1134 ret = i915_mutex_lock_interruptible(dev);
1138 if (dev_priv->mm.suspended) {
1139 mutex_unlock(&dev->struct_mutex);
1144 eb = eb_create(args->buffer_count);
1146 mutex_unlock(&dev->struct_mutex);
1151 /* Look up object handles */
1152 INIT_LIST_HEAD(&objects);
1153 for (i = 0; i < args->buffer_count; i++) {
1154 struct drm_i915_gem_object *obj;
1156 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1158 if (&obj->base == NULL) {
1159 DRM_DEBUG("Invalid object handle %d at index %d\n",
1161 /* prevent error path from reading uninitialized data */
1166 if (!list_empty(&obj->exec_list)) {
1167 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1168 obj, exec[i].handle, i);
1173 list_add_tail(&obj->exec_list, &objects);
1174 obj->exec_handle = exec[i].handle;
1175 obj->exec_entry = &exec[i];
1176 eb_add_object(eb, obj);
1179 /* take note of the batch buffer before we might reorder the lists */
1180 batch_obj = list_entry(objects.prev,
1181 struct drm_i915_gem_object,
1184 /* Move the objects en-masse into the GTT, evicting if necessary. */
1185 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1189 /* The objects are in their final locations, apply the relocations. */
1190 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1192 if (ret == -EFAULT) {
1193 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1196 args->buffer_count);
1197 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1203 /* Set the pending read domains for the batch buffer to COMMAND */
1204 if (batch_obj->base.pending_write_domain) {
1205 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1209 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1211 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1215 seqno = i915_gem_next_request_seqno(ring);
1216 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1217 if (seqno < ring->sync_seqno[i]) {
1218 /* The GPU can not handle its semaphore value wrapping,
1219 * so every billion or so execbuffers, we need to stall
1220 * the GPU in order to reset the counters.
1222 ret = i915_gpu_idle(dev);
1225 i915_gem_retire_requests(dev);
1227 BUG_ON(ring->sync_seqno[i]);
1231 ret = i915_switch_context(ring, file, ctx_id);
1235 if (ring == &dev_priv->ring[RCS] &&
1236 mode != dev_priv->relative_constants_mode) {
1237 ret = intel_ring_begin(ring, 4);
1241 intel_ring_emit(ring, MI_NOOP);
1242 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1243 intel_ring_emit(ring, INSTPM);
1244 intel_ring_emit(ring, mask << 16 | mode);
1245 intel_ring_advance(ring);
1247 dev_priv->relative_constants_mode = mode;
1250 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1251 ret = i915_reset_gen7_sol_offsets(dev, ring);
1256 trace_i915_gem_ring_dispatch(ring, seqno);
1258 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1259 exec_len = args->batch_len;
1261 for (i = 0; i < args->num_cliprects; i++) {
1262 ret = i915_emit_box(dev, &cliprects[i],
1263 args->DR1, args->DR4);
1267 ret = ring->dispatch_execbuffer(ring,
1268 exec_start, exec_len);
1273 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1278 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1279 i915_gem_execbuffer_retire_commands(dev, file, ring);
1283 while (!list_empty(&objects)) {
1284 struct drm_i915_gem_object *obj;
1286 obj = list_first_entry(&objects,
1287 struct drm_i915_gem_object,
1289 list_del_init(&obj->exec_list);
1290 drm_gem_object_unreference(&obj->base);
1293 mutex_unlock(&dev->struct_mutex);
1301 * Legacy execbuffer just creates an exec2 list from the original exec object
1302 * list array and passes it to the real function.
1305 i915_gem_execbuffer(struct drm_device *dev, void *data,
1306 struct drm_file *file)
1308 struct drm_i915_gem_execbuffer *args = data;
1309 struct drm_i915_gem_execbuffer2 exec2;
1310 struct drm_i915_gem_exec_object *exec_list = NULL;
1311 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1314 if (args->buffer_count < 1) {
1315 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1319 /* Copy in the exec list from userland */
1320 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1321 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1322 if (exec_list == NULL || exec2_list == NULL) {
1323 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1324 args->buffer_count);
1325 drm_free_large(exec_list);
1326 drm_free_large(exec2_list);
1329 ret = copy_from_user(exec_list,
1330 (struct drm_i915_relocation_entry __user *)
1331 (uintptr_t) args->buffers_ptr,
1332 sizeof(*exec_list) * args->buffer_count);
1334 DRM_DEBUG("copy %d exec entries failed %d\n",
1335 args->buffer_count, ret);
1336 drm_free_large(exec_list);
1337 drm_free_large(exec2_list);
1341 for (i = 0; i < args->buffer_count; i++) {
1342 exec2_list[i].handle = exec_list[i].handle;
1343 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1344 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1345 exec2_list[i].alignment = exec_list[i].alignment;
1346 exec2_list[i].offset = exec_list[i].offset;
1347 if (INTEL_INFO(dev)->gen < 4)
1348 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1350 exec2_list[i].flags = 0;
1353 exec2.buffers_ptr = args->buffers_ptr;
1354 exec2.buffer_count = args->buffer_count;
1355 exec2.batch_start_offset = args->batch_start_offset;
1356 exec2.batch_len = args->batch_len;
1357 exec2.DR1 = args->DR1;
1358 exec2.DR4 = args->DR4;
1359 exec2.num_cliprects = args->num_cliprects;
1360 exec2.cliprects_ptr = args->cliprects_ptr;
1361 exec2.flags = I915_EXEC_RENDER;
1362 i915_execbuffer2_set_context_id(exec2, 0);
1364 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1366 /* Copy the new buffer offsets back to the user's exec list. */
1367 for (i = 0; i < args->buffer_count; i++)
1368 exec_list[i].offset = exec2_list[i].offset;
1369 /* ... and back out to userspace */
1370 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1371 (uintptr_t) args->buffers_ptr,
1373 sizeof(*exec_list) * args->buffer_count);
1376 DRM_DEBUG("failed to copy %d exec entries "
1377 "back to user (%d)\n",
1378 args->buffer_count, ret);
1382 drm_free_large(exec_list);
1383 drm_free_large(exec2_list);
1388 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1389 struct drm_file *file)
1391 struct drm_i915_gem_execbuffer2 *args = data;
1392 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1395 if (args->buffer_count < 1 ||
1396 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1397 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1401 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1402 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1403 if (exec2_list == NULL)
1404 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1405 args->buffer_count);
1406 if (exec2_list == NULL) {
1407 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1408 args->buffer_count);
1411 ret = copy_from_user(exec2_list,
1412 (struct drm_i915_relocation_entry __user *)
1413 (uintptr_t) args->buffers_ptr,
1414 sizeof(*exec2_list) * args->buffer_count);
1416 DRM_DEBUG("copy %d exec entries failed %d\n",
1417 args->buffer_count, ret);
1418 drm_free_large(exec2_list);
1422 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1424 /* Copy the new buffer offsets back to the user's exec list. */
1425 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1426 (uintptr_t) args->buffers_ptr,
1428 sizeof(*exec2_list) * args->buffer_count);
1431 DRM_DEBUG("failed to copy %d exec entries "
1432 "back to user (%d)\n",
1433 args->buffer_count, ret);
1437 drm_free_large(exec2_list);