drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 struct change_domains {
  37         uint32_t invalidate_domains;
  38         uint32_t flush_domains;
  39         uint32_t flush_rings;
  40 };
  41
  42 /*
  43  * Set the next domain for the specified object. This
  44  * may not actually perform the necessary flushing/invaliding though,
  45  * as that may want to be batched with other set_domain operations
  46  *
  47  * This is (we hope) the only really tricky part of gem. The goal
  48  * is fairly simple -- track which caches hold bits of the object
  49  * and make sure they remain coherent. A few concrete examples may
  50  * help to explain how it works. For shorthand, we use the notation
  51  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
  52  * a pair of read and write domain masks.
  53  *
  54  * Case 1: the batch buffer
  55  *
  56  *      1. Allocated
  57  *      2. Written by CPU
  58  *      3. Mapped to GTT
  59  *      4. Read by GPU
  60  *      5. Unmapped from GTT
  61  *      6. Freed
  62  *
  63  *      Let's take these a step at a time
  64  *
  65  *      1. Allocated
  66  *              Pages allocated from the kernel may still have
  67  *              cache contents, so we set them to (CPU, CPU) always.
  68  *      2. Written by CPU (using pwrite)
  69  *              The pwrite function calls set_domain (CPU, CPU) and
  70  *              this function does nothing (as nothing changes)
  71  *      3. Mapped by GTT
  72  *              This function asserts that the object is not
  73  *              currently in any GPU-based read or write domains
  74  *      4. Read by GPU
  75  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
  76  *              As write_domain is zero, this function adds in the
  77  *              current read domains (CPU+COMMAND, 0).
  78  *              flush_domains is set to CPU.
  79  *              invalidate_domains is set to COMMAND
  80  *              clflush is run to get data out of the CPU caches
  81  *              then i915_dev_set_domain calls i915_gem_flush to
  82  *              emit an MI_FLUSH and drm_agp_chipset_flush
  83  *      5. Unmapped from GTT
  84  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
  85  *              flush_domains and invalidate_domains end up both zero
  86  *              so no flushing/invalidating happens
  87  *      6. Freed
  88  *              yay, done
  89  *
  90  * Case 2: The shared render buffer
  91  *
  92  *      1. Allocated
  93  *      2. Mapped to GTT
  94  *      3. Read/written by GPU
  95  *      4. set_domain to (CPU,CPU)
  96  *      5. Read/written by CPU
  97  *      6. Read/written by GPU
  98  *
  99  *      1. Allocated
 100  *              Same as last example, (CPU, CPU)
 101  *      2. Mapped to GTT
 102  *              Nothing changes (assertions find that it is not in the GPU)
 103  *      3. Read/written by GPU
 104  *              execbuffer calls set_domain (RENDER, RENDER)
 105  *              flush_domains gets CPU
 106  *              invalidate_domains gets GPU
 107  *              clflush (obj)
 108  *              MI_FLUSH and drm_agp_chipset_flush
 109  *      4. set_domain (CPU, CPU)
 110  *              flush_domains gets GPU
 111  *              invalidate_domains gets CPU
 112  *              wait_rendering (obj) to make sure all drawing is complete.
 113  *              This will include an MI_FLUSH to get the data from GPU
 114  *              to memory
 115  *              clflush (obj) to invalidate the CPU cache
 116  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
 117  *      5. Read/written by CPU
 118  *              cache lines are loaded and dirtied
 119  *      6. Read written by GPU
 120  *              Same as last GPU access
 121  *
 122  * Case 3: The constant buffer
 123  *
 124  *      1. Allocated
 125  *      2. Written by CPU
 126  *      3. Read by GPU
 127  *      4. Updated (written) by CPU again
 128  *      5. Read by GPU
 129  *
 130  *      1. Allocated
 131  *              (CPU, CPU)
 132  *      2. Written by CPU
 133  *              (CPU, CPU)
 134  *      3. Read by GPU
 135  *              (CPU+RENDER, 0)
 136  *              flush_domains = CPU
 137  *              invalidate_domains = RENDER
 138  *              clflush (obj)
 139  *              MI_FLUSH
 140  *              drm_agp_chipset_flush
 141  *      4. Updated (written) by CPU again
 142  *              (CPU, CPU)
 143  *              flush_domains = 0 (no previous write domain)
 144  *              invalidate_domains = 0 (no new read domains)
 145  *      5. Read by GPU
 146  *              (CPU+RENDER, 0)
 147  *              flush_domains = CPU
 148  *              invalidate_domains = RENDER
 149  *              clflush (obj)
 150  *              MI_FLUSH
 151  *              drm_agp_chipset_flush
 152  */
 153 static void
 154 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
 155                                   struct intel_ring_buffer *ring,
 156                                   struct change_domains *cd)
 157 {
 158         uint32_t invalidate_domains = 0, flush_domains = 0;
 159
 160         /*
 161          * If the object isn't moving to a new write domain,
 162          * let the object stay in multiple read domains
 163          */
 164         if (obj->base.pending_write_domain == 0)
 165                 obj->base.pending_read_domains |= obj->base.read_domains;
 166
 167         /*
 168          * Flush the current write domain if
 169          * the new read domains don't match. Invalidate
 170          * any read domains which differ from the old
 171          * write domain
 172          */
 173         if (obj->base.write_domain &&
 174             (((obj->base.write_domain != obj->base.pending_read_domains ||
 175                obj->ring != ring)) ||
 176              (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
 177                 flush_domains |= obj->base.write_domain;
 178                 invalidate_domains |=
 179                         obj->base.pending_read_domains & ~obj->base.write_domain;
 180         }
 181         /*
 182          * Invalidate any read caches which may have
 183          * stale data. That is, any new read domains.
 184          */
 185         invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
 186         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
 187                 i915_gem_clflush_object(obj);
 188
 189         /* blow away mappings if mapped through GTT */
 190         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
 191                 i915_gem_release_mmap(obj);
 192
 193         /* The actual obj->write_domain will be updated with
 194          * pending_write_domain after we emit the accumulated flush for all
 195          * of our domain changes in execbuffers (which clears objects'
 196          * write_domains).  So if we have a current write domain that we
 197          * aren't changing, set pending_write_domain to that.
 198          */
 199         if (flush_domains == 0 && obj->base.pending_write_domain == 0)
 200                 obj->base.pending_write_domain = obj->base.write_domain;
 201
 202         cd->invalidate_domains |= invalidate_domains;
 203         cd->flush_domains |= flush_domains;
 204         if (flush_domains & I915_GEM_GPU_DOMAINS)
 205                 cd->flush_rings |= obj->ring->id;
 206         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
 207                 cd->flush_rings |= ring->id;
 208 }
 209
 210 struct eb_objects {
 211         int and;
 212         struct hlist_head buckets[0];
 213 };
 214
 215 static struct eb_objects *
 216 eb_create(int size)
 217 {
 218         struct eb_objects *eb;
 219         int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
 220         while (count > size)
 221                 count >>= 1;
 222         eb = kzalloc(count*sizeof(struct hlist_head) +
 223                      sizeof(struct eb_objects),
 224                      GFP_KERNEL);
 225         if (eb == NULL)
 226                 return eb;
 227
 228         eb->and = count - 1;
 229         return eb;
 230 }
 231
 232 static void
 233 eb_reset(struct eb_objects *eb)
 234 {
 235         memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 236 }
 237
 238 static void
 239 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
 240 {
 241         hlist_add_head(&obj->exec_node,
 242                        &eb->buckets[obj->exec_handle & eb->and]);
 243 }
 244
 245 static struct drm_i915_gem_object *
 246 eb_get_object(struct eb_objects *eb, unsigned long handle)
 247 {
 248         struct hlist_head *head;
 249         struct hlist_node *node;
 250         struct drm_i915_gem_object *obj;
 251
 252         head = &eb->buckets[handle & eb->and];
 253         hlist_for_each(node, head) {
 254                 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
 255                 if (obj->exec_handle == handle)
 256                         return obj;
 257         }
 258
 259         return NULL;
 260 }
 261
 262 static void
 263 eb_destroy(struct eb_objects *eb)
 264 {
 265         kfree(eb);
 266 }
 267
 268 static int
 269 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 270                                    struct eb_objects *eb,
 271                                    struct drm_i915_gem_relocation_entry *reloc)
 272 {
 273         struct drm_device *dev = obj->base.dev;
 274         struct drm_gem_object *target_obj;
 275         uint32_t target_offset;
 276         int ret = -EINVAL;
 277
 278         /* we've already hold a reference to all valid objects */
 279         target_obj = &eb_get_object(eb, reloc->target_handle)->base;
 280         if (unlikely(target_obj == NULL))
 281                 return -ENOENT;
 282
 283         target_offset = to_intel_bo(target_obj)->gtt_offset;
 284
 285 #if WATCH_RELOC
 286         DRM_INFO("%s: obj %p offset %08x target %d "
 287                  "read %08x write %08x gtt %08x "
 288                  "presumed %08x delta %08x\n",
 289                  __func__,
 290                  obj,
 291                  (int) reloc->offset,
 292                  (int) reloc->target_handle,
 293                  (int) reloc->read_domains,
 294                  (int) reloc->write_domain,
 295                  (int) target_offset,
 296                  (int) reloc->presumed_offset,
 297                  reloc->delta);
 298 #endif
 299
 300         /* The target buffer should have appeared before us in the
 301          * exec_object list, so it should have a GTT space bound by now.
 302          */
 303         if (unlikely(target_offset == 0)) {
 304                 DRM_ERROR("No GTT space found for object %d\n",
 305                           reloc->target_handle);
 306                 return ret;
 307         }
 308
 309         /* Validate that the target is in a valid r/w GPU domain */
 310         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 311                 DRM_ERROR("reloc with multiple write domains: "
 312                           "obj %p target %d offset %d "
 313                           "read %08x write %08x",
 314                           obj, reloc->target_handle,
 315                           (int) reloc->offset,
 316                           reloc->read_domains,
 317                           reloc->write_domain);
 318                 return ret;
 319         }
 320         if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) {
 321                 DRM_ERROR("reloc with read/write CPU domains: "
 322                           "obj %p target %d offset %d "
 323                           "read %08x write %08x",
 324                           obj, reloc->target_handle,
 325                           (int) reloc->offset,
 326                           reloc->read_domains,
 327                           reloc->write_domain);
 328                 return ret;
 329         }
 330         if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
 331                      reloc->write_domain != target_obj->pending_write_domain)) {
 332                 DRM_ERROR("Write domain conflict: "
 333                           "obj %p target %d offset %d "
 334                           "new %08x old %08x\n",
 335                           obj, reloc->target_handle,
 336                           (int) reloc->offset,
 337                           reloc->write_domain,
 338                           target_obj->pending_write_domain);
 339                 return ret;
 340         }
 341
 342         target_obj->pending_read_domains |= reloc->read_domains;
 343         target_obj->pending_write_domain |= reloc->write_domain;
 344
 345         /* If the relocation already has the right value in it, no
 346          * more work needs to be done.
 347          */
 348         if (target_offset == reloc->presumed_offset)
 349                 return 0;
 350
 351         /* Check that the relocation address is valid... */
 352         if (unlikely(reloc->offset > obj->base.size - 4)) {
 353                 DRM_ERROR("Relocation beyond object bounds: "
 354                           "obj %p target %d offset %d size %d.\n",
 355                           obj, reloc->target_handle,
 356                           (int) reloc->offset,
 357                           (int) obj->base.size);
 358                 return ret;
 359         }
 360         if (unlikely(reloc->offset & 3)) {
 361                 DRM_ERROR("Relocation not 4-byte aligned: "
 362                           "obj %p target %d offset %d.\n",
 363                           obj, reloc->target_handle,
 364                           (int) reloc->offset);
 365                 return ret;
 366         }
 367
 368         /* and points to somewhere within the target object. */
 369         if (unlikely(reloc->delta >= target_obj->size)) {
 370                 DRM_ERROR("Relocation beyond target object bounds: "
 371                           "obj %p target %d delta %d size %d.\n",
 372                           obj, reloc->target_handle,
 373                           (int) reloc->delta,
 374                           (int) target_obj->size);
 375                 return ret;
 376         }
 377
 378         reloc->delta += target_offset;
 379         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
 380                 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
 381                 char *vaddr;
 382
 383                 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
 384                 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
 385                 kunmap_atomic(vaddr);
 386         } else {
 387                 struct drm_i915_private *dev_priv = dev->dev_private;
 388                 uint32_t __iomem *reloc_entry;
 389                 void __iomem *reloc_page;
 390
 391                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 392                 if (ret)
 393                         return ret;
 394
 395                 /* Map the page containing the relocation we're going to perform.  */
 396                 reloc->offset += obj->gtt_offset;
 397                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 398                                                       reloc->offset & PAGE_MASK);
 399                 reloc_entry = (uint32_t __iomem *)
 400                         (reloc_page + (reloc->offset & ~PAGE_MASK));
 401                 iowrite32(reloc->delta, reloc_entry);
 402                 io_mapping_unmap_atomic(reloc_page);
 403         }
 404
 405         /* and update the user's relocation entry */
 406         reloc->presumed_offset = target_offset;
 407
 408         return 0;
 409 }
 410
 411 static int
 412 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
 413                                     struct eb_objects *eb)
 414 {
 415         struct drm_i915_gem_relocation_entry __user *user_relocs;
 416         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 417         int i, ret;
 418
 419         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
 420         for (i = 0; i < entry->relocation_count; i++) {
 421                 struct drm_i915_gem_relocation_entry reloc;
 422
 423                 if (__copy_from_user_inatomic(&reloc,
 424                                               user_relocs+i,
 425                                               sizeof(reloc)))
 426                         return -EFAULT;
 427
 428                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
 429                 if (ret)
 430                         return ret;
 431
 432                 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
 433                                             &reloc.presumed_offset,
 434                                             sizeof(reloc.presumed_offset)))
 435                         return -EFAULT;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int
 442 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
 443                                          struct eb_objects *eb,
 444                                          struct drm_i915_gem_relocation_entry *relocs)
 445 {
 446         const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 447         int i, ret;
 448
 449         for (i = 0; i < entry->relocation_count; i++) {
 450                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
 451                 if (ret)
 452                         return ret;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int
 459 i915_gem_execbuffer_relocate(struct drm_device *dev,
 460                              struct eb_objects *eb,
 461                              struct list_head *objects)
 462 {
 463         struct drm_i915_gem_object *obj;
 464         int ret;
 465
 466         list_for_each_entry(obj, objects, exec_list) {
 467                 obj->base.pending_read_domains = 0;
 468                 obj->base.pending_write_domain = 0;
 469                 ret = i915_gem_execbuffer_relocate_object(obj, eb);
 470                 if (ret)
 471                         return ret;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int
 478 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 479                             struct drm_file *file,
 480                             struct list_head *objects)
 481 {
 482         struct drm_i915_gem_object *obj;
 483         int ret, retry;
 484         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 485         struct list_head ordered_objects;
 486
 487         INIT_LIST_HEAD(&ordered_objects);
 488         while (!list_empty(objects)) {
 489                 struct drm_i915_gem_exec_object2 *entry;
 490                 bool need_fence, need_mappable;
 491
 492                 obj = list_first_entry(objects,
 493                                        struct drm_i915_gem_object,
 494                                        exec_list);
 495                 entry = obj->exec_entry;
 496
 497                 need_fence =
 498                         has_fenced_gpu_access &&
 499                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 500                         obj->tiling_mode != I915_TILING_NONE;
 501                 need_mappable =
 502                         entry->relocation_count ? true : need_fence;
 503
 504                 if (need_mappable)
 505                         list_move(&obj->exec_list, &ordered_objects);
 506                 else
 507                         list_move_tail(&obj->exec_list, &ordered_objects);
 508         }
 509         list_splice(&ordered_objects, objects);
 510
 511         /* Attempt to pin all of the buffers into the GTT.
 512          * This is done in 3 phases:
 513          *
 514          * 1a. Unbind all objects that do not match the GTT constraints for
 515          *     the execbuffer (fenceable, mappable, alignment etc).
 516          * 1b. Increment pin count for already bound objects.
 517          * 2.  Bind new objects.
 518          * 3.  Decrement pin count.
 519          *
 520          * This avoid unnecessary unbinding of later objects in order to makr
 521          * room for the earlier objects *unless* we need to defragment.
 522          */
 523         retry = 0;
 524         do {
 525                 ret = 0;
 526
 527                 /* Unbind any ill-fitting objects or pin. */
 528                 list_for_each_entry(obj, objects, exec_list) {
 529                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 530                         bool need_fence, need_mappable;
 531                         if (!obj->gtt_space)
 532                                 continue;
 533
 534                         need_fence =
 535                                 has_fenced_gpu_access &&
 536                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 537                                 obj->tiling_mode != I915_TILING_NONE;
 538                         need_mappable =
 539                                 entry->relocation_count ? true : need_fence;
 540
 541                         if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
 542                             (need_mappable && !obj->map_and_fenceable))
 543                                 ret = i915_gem_object_unbind(obj);
 544                         else
 545                                 ret = i915_gem_object_pin(obj,
 546                                                           entry->alignment,
 547                                                           need_mappable);
 548                         if (ret)
 549                                 goto err;
 550
 551                         entry++;
 552                 }
 553
 554                 /* Bind fresh objects */
 555                 list_for_each_entry(obj, objects, exec_list) {
 556                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 557                         bool need_fence;
 558
 559                         need_fence =
 560                                 has_fenced_gpu_access &&
 561                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 562                                 obj->tiling_mode != I915_TILING_NONE;
 563
 564                         if (!obj->gtt_space) {
 565                                 bool need_mappable =
 566                                         entry->relocation_count ? true : need_fence;
 567
 568                                 ret = i915_gem_object_pin(obj,
 569                                                           entry->alignment,
 570                                                           need_mappable);
 571                                 if (ret)
 572                                         break;
 573                         }
 574
 575                         if (has_fenced_gpu_access) {
 576                                 if (need_fence) {
 577                                         ret = i915_gem_object_get_fence(obj, ring, 1);
 578                                         if (ret)
 579                                                 break;
 580                                 } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 581                                            obj->tiling_mode == I915_TILING_NONE) {
 582                                         /* XXX pipelined! */
 583                                         ret = i915_gem_object_put_fence(obj);
 584                                         if (ret)
 585                                                 break;
 586                                 }
 587                                 obj->pending_fenced_gpu_access = need_fence;
 588                         }
 589
 590                         entry->offset = obj->gtt_offset;
 591                 }
 592
 593                 /* Decrement pin count for bound objects */
 594                 list_for_each_entry(obj, objects, exec_list) {
 595                         if (obj->gtt_space)
 596                                 i915_gem_object_unpin(obj);
 597                 }
 598
 599                 if (ret != -ENOSPC || retry > 1)
 600                         return ret;
 601
 602                 /* First attempt, just clear anything that is purgeable.
 603                  * Second attempt, clear the entire GTT.
 604                  */
 605                 ret = i915_gem_evict_everything(ring->dev, retry == 0);
 606                 if (ret)
 607                         return ret;
 608
 609                 retry++;
 610         } while (1);
 611
 612 err:
 613         obj = list_entry(obj->exec_list.prev,
 614                          struct drm_i915_gem_object,
 615                          exec_list);
 616         while (objects != &obj->exec_list) {
 617                 if (obj->gtt_space)
 618                         i915_gem_object_unpin(obj);
 619
 620                 obj = list_entry(obj->exec_list.prev,
 621                                  struct drm_i915_gem_object,
 622                                  exec_list);
 623         }
 624
 625         return ret;
 626 }
 627
 628 static int
 629 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 630                                   struct drm_file *file,
 631                                   struct intel_ring_buffer *ring,
 632                                   struct list_head *objects,
 633                                   struct eb_objects *eb,
 634                                   struct drm_i915_gem_exec_object2 *exec,
 635                                   int count)
 636 {
 637         struct drm_i915_gem_relocation_entry *reloc;
 638         struct drm_i915_gem_object *obj;
 639         int i, total, ret;
 640
 641         /* We may process another execbuffer during the unlock... */
 642         while (!list_empty(objects)) {
 643                 obj = list_first_entry(objects,
 644                                        struct drm_i915_gem_object,
 645                                        exec_list);
 646                 list_del_init(&obj->exec_list);
 647                 drm_gem_object_unreference(&obj->base);
 648         }
 649
 650         mutex_unlock(&dev->struct_mutex);
 651
 652         total = 0;
 653         for (i = 0; i < count; i++)
 654                 total += exec[i].relocation_count;
 655
 656         reloc = drm_malloc_ab(total, sizeof(*reloc));
 657         if (reloc == NULL) {
 658                 mutex_lock(&dev->struct_mutex);
 659                 return -ENOMEM;
 660         }
 661
 662         total = 0;
 663         for (i = 0; i < count; i++) {
 664                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 665
 666                 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
 667
 668                 if (copy_from_user(reloc+total, user_relocs,
 669                                    exec[i].relocation_count * sizeof(*reloc))) {
 670                         ret = -EFAULT;
 671                         mutex_lock(&dev->struct_mutex);
 672                         goto err;
 673                 }
 674
 675                 total += exec[i].relocation_count;
 676         }
 677
 678         ret = i915_mutex_lock_interruptible(dev);
 679         if (ret) {
 680                 mutex_lock(&dev->struct_mutex);
 681                 goto err;
 682         }
 683
 684         /* reacquire the objects */
 685         eb_reset(eb);
 686         for (i = 0; i < count; i++) {
 687                 struct drm_i915_gem_object *obj;
 688
 689                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
 690                                                         exec[i].handle));
 691                 if (obj == NULL) {
 692                         DRM_ERROR("Invalid object handle %d at index %d\n",
 693                                    exec[i].handle, i);
 694                         ret = -ENOENT;
 695                         goto err;
 696                 }
 697
 698                 list_add_tail(&obj->exec_list, objects);
 699                 obj->exec_handle = exec[i].handle;
 700                 obj->exec_entry = &exec[i];
 701                 eb_add_object(eb, obj);
 702         }
 703
 704         ret = i915_gem_execbuffer_reserve(ring, file, objects);
 705         if (ret)
 706                 goto err;
 707
 708         total = 0;
 709         list_for_each_entry(obj, objects, exec_list) {
 710                 obj->base.pending_read_domains = 0;
 711                 obj->base.pending_write_domain = 0;
 712                 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
 713                                                                reloc + total);
 714                 if (ret)
 715                         goto err;
 716
 717                 total += exec->relocation_count;
 718                 exec++;
 719         }
 720
 721         /* Leave the user relocations as are, this is the painfully slow path,
 722          * and we want to avoid the complication of dropping the lock whilst
 723          * having buffers reserved in the aperture and so causing spurious
 724          * ENOSPC for random operations.
 725          */
 726
 727 err:
 728         drm_free_large(reloc);
 729         return ret;
 730 }
 731
 732 static int
 733 i915_gem_execbuffer_flush(struct drm_device *dev,
 734                           uint32_t invalidate_domains,
 735                           uint32_t flush_domains,
 736                           uint32_t flush_rings)
 737 {
 738         drm_i915_private_t *dev_priv = dev->dev_private;
 739         int i, ret;
 740
 741         if (flush_domains & I915_GEM_DOMAIN_CPU)
 742                 intel_gtt_chipset_flush();
 743
 744         if (flush_domains & I915_GEM_DOMAIN_GTT)
 745                 wmb();
 746
 747         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
 748                 for (i = 0; i < I915_NUM_RINGS; i++)
 749                         if (flush_rings & (1 << i)) {
 750                                 ret = i915_gem_flush_ring(dev,
 751                                                           &dev_priv->ring[i],
 752                                                           invalidate_domains,
 753                                                           flush_domains);
 754                                 if (ret)
 755                                         return ret;
 756                         }
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int
 763 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
 764                                struct intel_ring_buffer *to)
 765 {
 766         struct intel_ring_buffer *from = obj->ring;
 767         u32 seqno;
 768         int ret, idx;
 769
 770         if (from == NULL || to == from)
 771                 return 0;
 772
 773         if (INTEL_INFO(obj->base.dev)->gen < 6)
 774                 return i915_gem_object_wait_rendering(obj, true);
 775
 776         idx = intel_ring_sync_index(from, to);
 777
 778         seqno = obj->last_rendering_seqno;
 779         if (seqno <= from->sync_seqno[idx])
 780                 return 0;
 781
 782         if (seqno == from->outstanding_lazy_request) {
 783                 struct drm_i915_gem_request *request;
 784
 785                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 786                 if (request == NULL)
 787                         return -ENOMEM;
 788
 789                 ret = i915_add_request(obj->base.dev, NULL, request, from);
 790                 if (ret) {
 791                         kfree(request);
 792                         return ret;
 793                 }
 794
 795                 seqno = request->seqno;
 796         }
 797
 798         from->sync_seqno[idx] = seqno;
 799         return intel_ring_sync(to, from, seqno - 1);
 800 }
 801
 802 static int
 803 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
 804                                 struct list_head *objects)
 805 {
 806         struct drm_i915_gem_object *obj;
 807         struct change_domains cd;
 808         int ret;
 809
 810         cd.invalidate_domains = 0;
 811         cd.flush_domains = 0;
 812         cd.flush_rings = 0;
 813         list_for_each_entry(obj, objects, exec_list)
 814                 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 815
 816         if (cd.invalidate_domains | cd.flush_domains) {
 817 #if WATCH_EXEC
 818                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
 819                           __func__,
 820                          cd.invalidate_domains,
 821                          cd.flush_domains);
 822 #endif
 823                 ret = i915_gem_execbuffer_flush(ring->dev,
 824                                                 cd.invalidate_domains,
 825                                                 cd.flush_domains,
 826                                                 cd.flush_rings);
 827                 if (ret)
 828                         return ret;
 829         }
 830
 831         list_for_each_entry(obj, objects, exec_list) {
 832                 ret = i915_gem_execbuffer_sync_rings(obj, ring);
 833                 if (ret)
 834                         return ret;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static bool
 841 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 842 {
 843         return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
 844 }
 845
 846 static int
 847 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 848                    int count)
 849 {
 850         int i;
 851
 852         for (i = 0; i < count; i++) {
 853                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
 854                 int length; /* limited by fault_in_pages_readable() */
 855
 856                 /* First check for malicious input causing overflow */
 857                 if (exec[i].relocation_count >
 858                     INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
 859                         return -EINVAL;
 860
 861                 length = exec[i].relocation_count *
 862                         sizeof(struct drm_i915_gem_relocation_entry);
 863                 if (!access_ok(VERIFY_READ, ptr, length))
 864                         return -EFAULT;
 865
 866                 /* we may also need to update the presumed offsets */
 867                 if (!access_ok(VERIFY_WRITE, ptr, length))
 868                         return -EFAULT;
 869
 870                 if (fault_in_pages_readable(ptr, length))
 871                         return -EFAULT;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int
 878 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring,
 879                                    struct list_head *objects)
 880 {
 881         struct drm_i915_gem_object *obj;
 882         int flips;
 883
 884         /* Check for any pending flips. As we only maintain a flip queue depth
 885          * of 1, we can simply insert a WAIT for the next display flip prior
 886          * to executing the batch and avoid stalling the CPU.
 887          */
 888         flips = 0;
 889         list_for_each_entry(obj, objects, exec_list) {
 890                 if (obj->base.write_domain)
 891                         flips |= atomic_read(&obj->pending_flip);
 892         }
 893         if (flips) {
 894                 int plane, flip_mask, ret;
 895
 896                 for (plane = 0; flips >> plane; plane++) {
 897                         if (((flips >> plane) & 1) == 0)
 898                                 continue;
 899
 900                         if (plane)
 901                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 902                         else
 903                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 904
 905                         ret = intel_ring_begin(ring, 2);
 906                         if (ret)
 907                                 return ret;
 908
 909                         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
 910                         intel_ring_emit(ring, MI_NOOP);
 911                         intel_ring_advance(ring);
 912                 }
 913         }
 914
 915         return 0;
 916 }
 917
 918 static void
 919 i915_gem_execbuffer_move_to_active(struct list_head *objects,
 920                                    struct intel_ring_buffer *ring,
 921                                    u32 seqno)
 922 {
 923         struct drm_i915_gem_object *obj;
 924
 925         list_for_each_entry(obj, objects, exec_list) {
 926                 obj->base.read_domains = obj->base.pending_read_domains;
 927                 obj->base.write_domain = obj->base.pending_write_domain;
 928                 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
 929
 930                 i915_gem_object_move_to_active(obj, ring, seqno);
 931                 if (obj->base.write_domain) {
 932                         obj->dirty = 1;
 933                         obj->pending_gpu_write = true;
 934                         list_move_tail(&obj->gpu_write_list,
 935                                        &ring->gpu_write_list);
 936                         intel_mark_busy(ring->dev, obj);
 937                 }
 938
 939                 trace_i915_gem_object_change_domain(obj,
 940                                                     obj->base.read_domains,
 941                                                     obj->base.write_domain);
 942         }
 943 }
 944
 945 static void
 946 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
 947                                     struct drm_file *file,
 948                                     struct intel_ring_buffer *ring)
 949 {
 950         struct drm_i915_gem_request *request;
 951         u32 invalidate;
 952
 953         /*
 954          * Ensure that the commands in the batch buffer are
 955          * finished before the interrupt fires.
 956          *
 957          * The sampler always gets flushed on i965 (sigh).
 958          */
 959         invalidate = I915_GEM_DOMAIN_COMMAND;
 960         if (INTEL_INFO(dev)->gen >= 4)
 961                 invalidate |= I915_GEM_DOMAIN_SAMPLER;
 962         if (ring->flush(ring, invalidate, 0)) {
 963                 i915_gem_next_request_seqno(dev, ring);
 964                 return;
 965         }
 966
 967         /* Add a breadcrumb for the completion of the batch buffer */
 968         request = kzalloc(sizeof(*request), GFP_KERNEL);
 969         if (request == NULL || i915_add_request(dev, file, request, ring)) {
 970                 i915_gem_next_request_seqno(dev, ring);
 971                 kfree(request);
 972         }
 973 }
 974
 975 static int
 976 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 977                        struct drm_file *file,
 978                        struct drm_i915_gem_execbuffer2 *args,
 979                        struct drm_i915_gem_exec_object2 *exec)
 980 {
 981         drm_i915_private_t *dev_priv = dev->dev_private;
 982         struct list_head objects;
 983         struct eb_objects *eb;
 984         struct drm_i915_gem_object *batch_obj;
 985         struct drm_clip_rect *cliprects = NULL;
 986         struct intel_ring_buffer *ring;
 987         u32 exec_start, exec_len;
 988         u32 seqno;
 989         int ret, mode, i;
 990
 991         if (!i915_gem_check_execbuffer(args)) {
 992                 DRM_ERROR("execbuf with invalid offset/length\n");
 993                 return -EINVAL;
 994         }
 995
 996         ret = validate_exec_list(exec, args->buffer_count);
 997         if (ret)
 998                 return ret;
 999
1000 #if WATCH_EXEC
1001         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1002                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1003 #endif
1004         switch (args->flags & I915_EXEC_RING_MASK) {
1005         case I915_EXEC_DEFAULT:
1006         case I915_EXEC_RENDER:
1007                 ring = &dev_priv->ring[RCS];
1008                 break;
1009         case I915_EXEC_BSD:
1010                 if (!HAS_BSD(dev)) {
1011                         DRM_ERROR("execbuf with invalid ring (BSD)\n");
1012                         return -EINVAL;
1013                 }
1014                 ring = &dev_priv->ring[VCS];
1015                 break;
1016         case I915_EXEC_BLT:
1017                 if (!HAS_BLT(dev)) {
1018                         DRM_ERROR("execbuf with invalid ring (BLT)\n");
1019                         return -EINVAL;
1020                 }
1021                 ring = &dev_priv->ring[BCS];
1022                 break;
1023         default:
1024                 DRM_ERROR("execbuf with unknown ring: %d\n",
1025                           (int)(args->flags & I915_EXEC_RING_MASK));
1026                 return -EINVAL;
1027         }
1028
1029         mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1030         switch (mode) {
1031         case I915_EXEC_CONSTANTS_REL_GENERAL:
1032         case I915_EXEC_CONSTANTS_ABSOLUTE:
1033         case I915_EXEC_CONSTANTS_REL_SURFACE:
1034                 if (ring == &dev_priv->ring[RCS] &&
1035                     mode != dev_priv->relative_constants_mode) {
1036                         if (INTEL_INFO(dev)->gen < 4)
1037                                 return -EINVAL;
1038
1039                         if (INTEL_INFO(dev)->gen > 5 &&
1040                             mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1041                                 return -EINVAL;
1042
1043                         ret = intel_ring_begin(ring, 4);
1044                         if (ret)
1045                                 return ret;
1046
1047                         intel_ring_emit(ring, MI_NOOP);
1048                         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1049                         intel_ring_emit(ring, INSTPM);
1050                         intel_ring_emit(ring,
1051                                         I915_EXEC_CONSTANTS_MASK << 16 | mode);
1052                         intel_ring_advance(ring);
1053
1054                         dev_priv->relative_constants_mode = mode;
1055                 }
1056                 break;
1057         default:
1058                 DRM_ERROR("execbuf with unknown constants: %d\n", mode);
1059                 return -EINVAL;
1060         }
1061
1062         if (args->buffer_count < 1) {
1063                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1064                 return -EINVAL;
1065         }
1066
1067         if (args->num_cliprects != 0) {
1068                 if (ring != &dev_priv->ring[RCS]) {
1069                         DRM_ERROR("clip rectangles are only valid with the render ring\n");
1070                         return -EINVAL;
1071                 }
1072
1073                 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1074                                     GFP_KERNEL);
1075                 if (cliprects == NULL) {
1076                         ret = -ENOMEM;
1077                         goto pre_mutex_err;
1078                 }
1079
1080                 if (copy_from_user(cliprects,
1081                                      (struct drm_clip_rect __user *)(uintptr_t)
1082                                      args->cliprects_ptr,
1083                                      sizeof(*cliprects)*args->num_cliprects)) {
1084                         ret = -EFAULT;
1085                         goto pre_mutex_err;
1086                 }
1087         }
1088
1089         ret = i915_mutex_lock_interruptible(dev);
1090         if (ret)
1091                 goto pre_mutex_err;
1092
1093         if (dev_priv->mm.suspended) {
1094                 mutex_unlock(&dev->struct_mutex);
1095                 ret = -EBUSY;
1096                 goto pre_mutex_err;
1097         }
1098
1099         eb = eb_create(args->buffer_count);
1100         if (eb == NULL) {
1101                 mutex_unlock(&dev->struct_mutex);
1102                 ret = -ENOMEM;
1103                 goto pre_mutex_err;
1104         }
1105
1106         /* Look up object handles */
1107         INIT_LIST_HEAD(&objects);
1108         for (i = 0; i < args->buffer_count; i++) {
1109                 struct drm_i915_gem_object *obj;
1110
1111                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1112                                                         exec[i].handle));
1113                 if (obj == NULL) {
1114                         DRM_ERROR("Invalid object handle %d at index %d\n",
1115                                    exec[i].handle, i);
1116                         /* prevent error path from reading uninitialized data */
1117                         ret = -ENOENT;
1118                         goto err;
1119                 }
1120
1121                 if (!list_empty(&obj->exec_list)) {
1122                         DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1123                                    obj, exec[i].handle, i);
1124                         ret = -EINVAL;
1125                         goto err;
1126                 }
1127
1128                 list_add_tail(&obj->exec_list, &objects);
1129                 obj->exec_handle = exec[i].handle;
1130                 obj->exec_entry = &exec[i];
1131                 eb_add_object(eb, obj);
1132         }
1133
1134         /* take note of the batch buffer before we might reorder the lists */
1135         batch_obj = list_entry(objects.prev,
1136                                struct drm_i915_gem_object,
1137                                exec_list);
1138
1139         /* Move the objects en-masse into the GTT, evicting if necessary. */
1140         ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1141         if (ret)
1142                 goto err;
1143
1144         /* The objects are in their final locations, apply the relocations. */
1145         ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1146         if (ret) {
1147                 if (ret == -EFAULT) {
1148                         ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1149                                                                 &objects, eb,
1150                                                                 exec,
1151                                                                 args->buffer_count);
1152                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1153                 }
1154                 if (ret)
1155                         goto err;
1156         }
1157
1158         /* Set the pending read domains for the batch buffer to COMMAND */
1159         if (batch_obj->base.pending_write_domain) {
1160                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1161                 ret = -EINVAL;
1162                 goto err;
1163         }
1164         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1165
1166         ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1167         if (ret)
1168                 goto err;
1169
1170         ret = i915_gem_execbuffer_wait_for_flips(ring, &objects);
1171         if (ret)
1172                 goto err;
1173
1174         seqno = i915_gem_next_request_seqno(dev, ring);
1175         for (i = 0; i < I915_NUM_RINGS-1; i++) {
1176                 if (seqno < ring->sync_seqno[i]) {
1177                         /* The GPU can not handle its semaphore value wrapping,
1178                          * so every billion or so execbuffers, we need to stall
1179                          * the GPU in order to reset the counters.
1180                          */
1181                         ret = i915_gpu_idle(dev);
1182                         if (ret)
1183                                 goto err;
1184
1185                         BUG_ON(ring->sync_seqno[i]);
1186                 }
1187         }
1188
1189         exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1190         exec_len = args->batch_len;
1191         if (cliprects) {
1192                 for (i = 0; i < args->num_cliprects; i++) {
1193                         ret = i915_emit_box(dev, &cliprects[i],
1194                                             args->DR1, args->DR4);
1195                         if (ret)
1196                                 goto err;
1197
1198                         ret = ring->dispatch_execbuffer(ring,
1199                                                         exec_start, exec_len);
1200                         if (ret)
1201                                 goto err;
1202                 }
1203         } else {
1204                 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1205                 if (ret)
1206                         goto err;
1207         }
1208
1209         i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1210         i915_gem_execbuffer_retire_commands(dev, file, ring);
1211
1212 err:
1213         eb_destroy(eb);
1214         while (!list_empty(&objects)) {
1215                 struct drm_i915_gem_object *obj;
1216
1217                 obj = list_first_entry(&objects,
1218                                        struct drm_i915_gem_object,
1219                                        exec_list);
1220                 list_del_init(&obj->exec_list);
1221                 drm_gem_object_unreference(&obj->base);
1222         }
1223
1224         mutex_unlock(&dev->struct_mutex);
1225
1226 pre_mutex_err:
1227         kfree(cliprects);
1228         return ret;
1229 }
1230
1231 /*
1232  * Legacy execbuffer just creates an exec2 list from the original exec object
1233  * list array and passes it to the real function.
1234  */
1235 int
1236 i915_gem_execbuffer(struct drm_device *dev, void *data,
1237                     struct drm_file *file)
1238 {
1239         struct drm_i915_gem_execbuffer *args = data;
1240         struct drm_i915_gem_execbuffer2 exec2;
1241         struct drm_i915_gem_exec_object *exec_list = NULL;
1242         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1243         int ret, i;
1244
1245 #if WATCH_EXEC
1246         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1247                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1248 #endif
1249
1250         if (args->buffer_count < 1) {
1251                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1252                 return -EINVAL;
1253         }
1254
1255         /* Copy in the exec list from userland */
1256         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1257         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1258         if (exec_list == NULL || exec2_list == NULL) {
1259                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1260                           args->buffer_count);
1261                 drm_free_large(exec_list);
1262                 drm_free_large(exec2_list);
1263                 return -ENOMEM;
1264         }
1265         ret = copy_from_user(exec_list,
1266                              (struct drm_i915_relocation_entry __user *)
1267                              (uintptr_t) args->buffers_ptr,
1268                              sizeof(*exec_list) * args->buffer_count);
1269         if (ret != 0) {
1270                 DRM_ERROR("copy %d exec entries failed %d\n",
1271                           args->buffer_count, ret);
1272                 drm_free_large(exec_list);
1273                 drm_free_large(exec2_list);
1274                 return -EFAULT;
1275         }
1276
1277         for (i = 0; i < args->buffer_count; i++) {
1278                 exec2_list[i].handle = exec_list[i].handle;
1279                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1280                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1281                 exec2_list[i].alignment = exec_list[i].alignment;
1282                 exec2_list[i].offset = exec_list[i].offset;
1283                 if (INTEL_INFO(dev)->gen < 4)
1284                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1285                 else
1286                         exec2_list[i].flags = 0;
1287         }
1288
1289         exec2.buffers_ptr = args->buffers_ptr;
1290         exec2.buffer_count = args->buffer_count;
1291         exec2.batch_start_offset = args->batch_start_offset;
1292         exec2.batch_len = args->batch_len;
1293         exec2.DR1 = args->DR1;
1294         exec2.DR4 = args->DR4;
1295         exec2.num_cliprects = args->num_cliprects;
1296         exec2.cliprects_ptr = args->cliprects_ptr;
1297         exec2.flags = I915_EXEC_RENDER;
1298
1299         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1300         if (!ret) {
1301                 /* Copy the new buffer offsets back to the user's exec list. */
1302                 for (i = 0; i < args->buffer_count; i++)
1303                         exec_list[i].offset = exec2_list[i].offset;
1304                 /* ... and back out to userspace */
1305                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1306                                    (uintptr_t) args->buffers_ptr,
1307                                    exec_list,
1308                                    sizeof(*exec_list) * args->buffer_count);
1309                 if (ret) {
1310                         ret = -EFAULT;
1311                         DRM_ERROR("failed to copy %d exec entries "
1312                                   "back to user (%d)\n",
1313                                   args->buffer_count, ret);
1314                 }
1315         }
1316
1317         drm_free_large(exec_list);
1318         drm_free_large(exec2_list);
1319         return ret;
1320 }
1321
1322 int
1323 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1324                      struct drm_file *file)
1325 {
1326         struct drm_i915_gem_execbuffer2 *args = data;
1327         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1328         int ret;
1329
1330 #if WATCH_EXEC
1331         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1332                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1333 #endif
1334
1335         if (args->buffer_count < 1) {
1336                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1337                 return -EINVAL;
1338         }
1339
1340         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1341         if (exec2_list == NULL) {
1342                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1343                           args->buffer_count);
1344                 return -ENOMEM;
1345         }
1346         ret = copy_from_user(exec2_list,
1347                              (struct drm_i915_relocation_entry __user *)
1348                              (uintptr_t) args->buffers_ptr,
1349                              sizeof(*exec2_list) * args->buffer_count);
1350         if (ret != 0) {
1351                 DRM_ERROR("copy %d exec entries failed %d\n",
1352                           args->buffer_count, ret);
1353                 drm_free_large(exec2_list);
1354                 return -EFAULT;
1355         }
1356
1357         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1358         if (!ret) {
1359                 /* Copy the new buffer offsets back to the user's exec list. */
1360                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1361                                    (uintptr_t) args->buffers_ptr,
1362                                    exec2_list,
1363                                    sizeof(*exec2_list) * args->buffer_count);
1364                 if (ret) {
1365                         ret = -EFAULT;
1366                         DRM_ERROR("failed to copy %d exec entries "
1367                                   "back to user (%d)\n",
1368                                   args->buffer_count, ret);
1369                 }
1370         }
1371
1372         drm_free_large(exec2_list);
1373         return ret;
1374 }