2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/i915_drm.h>
38 #include "i915_gem_clflush.h"
39 #include "i915_trace.h"
40 #include "intel_drv.h"
41 #include "intel_frontbuffer.h"
47 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
50 #define __EXEC_OBJECT_HAS_REF BIT(31)
51 #define __EXEC_OBJECT_HAS_PIN BIT(30)
52 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
53 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
54 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
55 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
56 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
58 #define __EXEC_HAS_RELOC BIT(31)
59 #define __EXEC_VALIDATED BIT(30)
60 #define UPDATE PIN_OFFSET_FIXED
62 #define BATCH_OFFSET_BIAS (256*1024)
64 #define __I915_EXEC_ILLEGAL_FLAGS \
65 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
68 * DOC: User command execution
70 * Userspace submits commands to be executed on the GPU as an instruction
71 * stream within a GEM object we call a batchbuffer. This instructions may
72 * refer to other GEM objects containing auxiliary state such as kernels,
73 * samplers, render targets and even secondary batchbuffers. Userspace does
74 * not know where in the GPU memory these objects reside and so before the
75 * batchbuffer is passed to the GPU for execution, those addresses in the
76 * batchbuffer and auxiliary objects are updated. This is known as relocation,
77 * or patching. To try and avoid having to relocate each object on the next
78 * execution, userspace is told the location of those objects in this pass,
79 * but this remains just a hint as the kernel may choose a new location for
80 * any object in the future.
82 * Processing an execbuf ioctl is conceptually split up into a few phases.
84 * 1. Validation - Ensure all the pointers, handles and flags are valid.
85 * 2. Reservation - Assign GPU address space for every object
86 * 3. Relocation - Update any addresses to point to the final locations
87 * 4. Serialisation - Order the request with respect to its dependencies
88 * 5. Construction - Construct a request to execute the batchbuffer
89 * 6. Submission (at some point in the future execution)
91 * Reserving resources for the execbuf is the most complicated phase. We
92 * neither want to have to migrate the object in the address space, nor do
93 * we want to have to update any relocations pointing to this object. Ideally,
94 * we want to leave the object where it is and for all the existing relocations
95 * to match. If the object is given a new address, or if userspace thinks the
96 * object is elsewhere, we have to parse all the relocation entries and update
97 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
98 * all the target addresses in all of its objects match the value in the
99 * relocation entries and that they all match the presumed offsets given by the
100 * list of execbuffer objects. Using this knowledge, we know that if we haven't
101 * moved any buffers, all the relocation entries are valid and we can skip
102 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
103 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
105 * The addresses written in the objects must match the corresponding
106 * reloc.presumed_offset which in turn must match the corresponding
109 * Any render targets written to in the batch must be flagged with
112 * To avoid stalling, execobject.offset should match the current
113 * address of that object within the active context.
115 * The reservation is done is multiple phases. First we try and keep any
116 * object already bound in its current location - so as long as meets the
117 * constraints imposed by the new execbuffer. Any object left unbound after the
118 * first pass is then fitted into any available idle space. If an object does
119 * not fit, all objects are removed from the reservation and the process rerun
120 * after sorting the objects into a priority order (more difficult to fit
121 * objects are tried first). Failing that, the entire VM is cleared and we try
122 * to fit the execbuf once last time before concluding that it simply will not
125 * A small complication to all of this is that we allow userspace not only to
126 * specify an alignment and a size for the object in the address space, but
127 * we also allow userspace to specify the exact offset. This objects are
128 * simpler to place (the location is known a priori) all we have to do is make
129 * sure the space is available.
131 * Once all the objects are in place, patching up the buried pointers to point
132 * to the final locations is a fairly simple job of walking over the relocation
133 * entry arrays, looking up the right address and rewriting the value into
134 * the object. Simple! ... The relocation entries are stored in user memory
135 * and so to access them we have to copy them into a local buffer. That copy
136 * has to avoid taking any pagefaults as they may lead back to a GEM object
137 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
138 * the relocation into multiple passes. First we try to do everything within an
139 * atomic context (avoid the pagefaults) which requires that we never wait. If
140 * we detect that we may wait, or if we need to fault, then we have to fallback
141 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
142 * bells yet?) Dropping the mutex means that we lose all the state we have
143 * built up so far for the execbuf and we must reset any global data. However,
144 * we do leave the objects pinned in their final locations - which is a
145 * potential issue for concurrent execbufs. Once we have left the mutex, we can
146 * allocate and copy all the relocation entries into a large array at our
147 * leisure, reacquire the mutex, reclaim all the objects and other state and
148 * then proceed to update any incorrect addresses with the objects.
150 * As we process the relocation entries, we maintain a record of whether the
151 * object is being written to. Using NORELOC, we expect userspace to provide
152 * this information instead. We also check whether we can skip the relocation
153 * by comparing the expected value inside the relocation entry with the target's
154 * final address. If they differ, we have to map the current object and rewrite
155 * the 4 or 8 byte pointer within.
157 * Serialising an execbuf is quite simple according to the rules of the GEM
158 * ABI. Execution within each context is ordered by the order of submission.
159 * Writes to any GEM object are in order of submission and are exclusive. Reads
160 * from a GEM object are unordered with respect to other reads, but ordered by
161 * writes. A write submitted after a read cannot occur before the read, and
162 * similarly any read submitted after a write cannot occur before the write.
163 * Writes are ordered between engines such that only one write occurs at any
164 * time (completing any reads beforehand) - using semaphores where available
165 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
166 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
167 * reads before starting, and any read (either using set-domain or pread) must
168 * flush all GPU writes before starting. (Note we only employ a barrier before,
169 * we currently rely on userspace not concurrently starting a new execution
170 * whilst reading or writing to an object. This may be an advantage or not
171 * depending on how much you trust userspace not to shoot themselves in the
172 * foot.) Serialisation may just result in the request being inserted into
173 * a DAG awaiting its turn, but most simple is to wait on the CPU until
174 * all dependencies are resolved.
176 * After all of that, is just a matter of closing the request and handing it to
177 * the hardware (well, leaving it in a queue to be executed). However, we also
178 * offer the ability for batchbuffers to be run with elevated privileges so
179 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
180 * Before any batch is given extra privileges we first must check that it
181 * contains no nefarious instructions, we check that each instruction is from
182 * our whitelist and all registers are also from an allowed list. We first
183 * copy the user's batchbuffer to a shadow (so that the user doesn't have
184 * access to it, either by the CPU or GPU as we scan it) and then parse each
185 * instruction. If everything is ok, we set a flag telling the hardware to run
186 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
189 struct i915_execbuffer {
190 struct drm_i915_private *i915; /** i915 backpointer */
191 struct drm_file *file; /** per-file lookup tables and limits */
192 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
193 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
195 struct intel_engine_cs *engine; /** engine to queue the request to */
196 struct i915_gem_context *ctx; /** context for building the request */
197 struct i915_address_space *vm; /** GTT and vma for the request */
199 struct drm_i915_gem_request *request; /** our request to build */
200 struct i915_vma *batch; /** identity of the batch obj/vma */
202 /** actual size of execobj[] as we may extend it for the cmdparser */
203 unsigned int buffer_count;
205 /** list of vma not yet bound during reservation phase */
206 struct list_head unbound;
208 /** list of vma that have execobj.relocation_count */
209 struct list_head relocs;
212 * Track the most recently used object for relocations, as we
213 * frequently have to perform multiple relocations within the same
217 struct drm_mm_node node; /** temporary GTT binding */
218 unsigned long vaddr; /** Current kmap address */
219 unsigned long page; /** Currently mapped page index */
220 unsigned int gen; /** Cached value of INTEL_GEN */
221 bool use_64bit_reloc : 1;
224 bool needs_unfenced : 1;
226 struct drm_i915_gem_request *rq;
228 unsigned int rq_size;
231 u64 invalid_flags; /** Set of execobj.flags that are invalid */
232 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
234 u32 batch_start_offset; /** Location within object of batch */
235 u32 batch_len; /** Length of batch within object */
236 u32 batch_flags; /** Flags composed for emit_bb_start() */
239 * Indicate either the size of the hastable used to resolve
240 * relocation handles, or if negative that we are using a direct
241 * index into the execobj[].
244 struct hlist_head *buckets; /** ht for relocation handles */
248 * As an alternative to creating a hashtable of handle-to-vma for a batch,
249 * we used the last available reserved field in the execobject[] and stash
250 * a link from the execobj to its vma.
252 #define __exec_to_vma(ee) (ee)->rsvd2
253 #define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee))
256 * Used to convert any address to canonical form.
257 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
258 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
259 * addresses to be in a canonical form:
260 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
261 * canonical form [63:48] == [47]."
263 #define GEN8_HIGH_ADDRESS_BIT 47
264 static inline u64 gen8_canonical_addr(u64 address)
266 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
269 static inline u64 gen8_noncanonical_addr(u64 address)
271 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
274 static int eb_create(struct i915_execbuffer *eb)
276 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
277 unsigned int size = 1 + ilog2(eb->buffer_count);
280 * Without a 1:1 association between relocation handles and
281 * the execobject[] index, we instead create a hashtable.
282 * We size it dynamically based on available memory, starting
283 * first with 1:1 assocative hash and scaling back until
284 * the allocation succeeds.
286 * Later on we use a positive lut_size to indicate we are
287 * using this hashtable, and a negative value to indicate a
291 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
299 if (unlikely(!eb->buckets)) {
300 eb->buckets = kzalloc(sizeof(struct hlist_head),
302 if (unlikely(!eb->buckets))
308 eb->lut_size = -eb->buffer_count;
315 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
316 const struct i915_vma *vma)
318 if (!(entry->flags & __EXEC_OBJECT_HAS_PIN))
321 if (vma->node.size < entry->pad_to_size)
324 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
327 if (entry->flags & EXEC_OBJECT_PINNED &&
328 vma->node.start != entry->offset)
331 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
332 vma->node.start < BATCH_OFFSET_BIAS)
335 if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
336 (vma->node.start + vma->node.size - 1) >> 32)
343 eb_pin_vma(struct i915_execbuffer *eb,
344 struct drm_i915_gem_exec_object2 *entry,
345 struct i915_vma *vma)
350 flags = vma->node.start;
352 flags = entry->offset & PIN_OFFSET_MASK;
354 flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
355 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT))
358 if (unlikely(i915_vma_pin(vma, 0, 0, flags)))
361 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
362 if (unlikely(i915_vma_get_fence(vma))) {
367 if (i915_vma_pin_fence(vma))
368 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
371 entry->flags |= __EXEC_OBJECT_HAS_PIN;
375 __eb_unreserve_vma(struct i915_vma *vma,
376 const struct drm_i915_gem_exec_object2 *entry)
378 GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN));
380 if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE))
381 i915_vma_unpin_fence(vma);
383 __i915_vma_unpin(vma);
387 eb_unreserve_vma(struct i915_vma *vma,
388 struct drm_i915_gem_exec_object2 *entry)
390 if (!(entry->flags & __EXEC_OBJECT_HAS_PIN))
393 __eb_unreserve_vma(vma, entry);
394 entry->flags &= ~__EXEC_OBJECT_RESERVED;
398 eb_validate_vma(struct i915_execbuffer *eb,
399 struct drm_i915_gem_exec_object2 *entry,
400 struct i915_vma *vma)
402 if (unlikely(entry->flags & eb->invalid_flags))
405 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
409 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
410 * any non-page-aligned or non-canonical addresses.
412 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
413 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
416 /* pad_to_size was once a reserved field, so sanitize it */
417 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
418 if (unlikely(offset_in_page(entry->pad_to_size)))
421 entry->pad_to_size = 0;
424 if (unlikely(vma->exec_entry)) {
425 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
426 entry->handle, (int)(entry - eb->exec));
431 * From drm_mm perspective address space is continuous,
432 * so from this point we're always using non-canonical
435 entry->offset = gen8_noncanonical_addr(entry->offset);
441 eb_add_vma(struct i915_execbuffer *eb,
442 struct drm_i915_gem_exec_object2 *entry,
443 struct i915_vma *vma)
447 GEM_BUG_ON(i915_vma_is_closed(vma));
449 if (!(eb->args->flags & __EXEC_VALIDATED)) {
450 err = eb_validate_vma(eb, entry, vma);
455 if (eb->lut_size >= 0) {
456 vma->exec_handle = entry->handle;
457 hlist_add_head(&vma->exec_node,
458 &eb->buckets[hash_32(entry->handle,
462 if (entry->relocation_count)
463 list_add_tail(&vma->reloc_link, &eb->relocs);
465 if (!eb->reloc_cache.has_fence) {
466 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
468 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
469 eb->reloc_cache.needs_unfenced) &&
470 i915_gem_object_is_tiled(vma->obj))
471 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
474 if (!(entry->flags & EXEC_OBJECT_PINNED))
475 entry->flags |= eb->context_flags;
478 * Stash a pointer from the vma to execobj, so we can query its flags,
479 * size, alignment etc as provided by the user. Also we stash a pointer
480 * to the vma inside the execobj so that we can use a direct lookup
481 * to find the right target VMA when doing relocations.
483 vma->exec_entry = entry;
484 __exec_to_vma(entry) = (uintptr_t)vma;
487 eb_pin_vma(eb, entry, vma);
488 if (eb_vma_misplaced(entry, vma)) {
489 eb_unreserve_vma(vma, entry);
491 list_add_tail(&vma->exec_link, &eb->unbound);
492 if (drm_mm_node_allocated(&vma->node))
493 err = i915_vma_unbind(vma);
495 if (entry->offset != vma->node.start) {
496 entry->offset = vma->node.start | UPDATE;
497 eb->args->flags |= __EXEC_HAS_RELOC;
503 static inline int use_cpu_reloc(const struct reloc_cache *cache,
504 const struct drm_i915_gem_object *obj)
506 if (!i915_gem_object_has_struct_page(obj))
509 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
512 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
515 return (cache->has_llc ||
517 obj->cache_level != I915_CACHE_NONE);
520 static int eb_reserve_vma(const struct i915_execbuffer *eb,
521 struct i915_vma *vma)
523 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
527 flags = PIN_USER | PIN_NONBLOCK;
528 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
532 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
533 * limit address to the first 4GBs for unflagged objects.
535 if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
536 flags |= PIN_ZONE_4G;
538 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
539 flags |= PIN_MAPPABLE;
541 if (entry->flags & EXEC_OBJECT_PINNED) {
542 flags |= entry->offset | PIN_OFFSET_FIXED;
543 flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */
544 } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) {
545 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
548 err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags);
552 if (entry->offset != vma->node.start) {
553 entry->offset = vma->node.start | UPDATE;
554 eb->args->flags |= __EXEC_HAS_RELOC;
557 entry->flags |= __EXEC_OBJECT_HAS_PIN;
558 GEM_BUG_ON(eb_vma_misplaced(entry, vma));
560 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
561 err = i915_vma_get_fence(vma);
567 if (i915_vma_pin_fence(vma))
568 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
574 static int eb_reserve(struct i915_execbuffer *eb)
576 const unsigned int count = eb->buffer_count;
577 struct list_head last;
578 struct i915_vma *vma;
579 unsigned int i, pass;
583 * Attempt to pin all of the buffers into the GTT.
584 * This is done in 3 phases:
586 * 1a. Unbind all objects that do not match the GTT constraints for
587 * the execbuffer (fenceable, mappable, alignment etc).
588 * 1b. Increment pin count for already bound objects.
589 * 2. Bind new objects.
590 * 3. Decrement pin count.
592 * This avoid unnecessary unbinding of later objects in order to make
593 * room for the earlier objects *unless* we need to defragment.
599 list_for_each_entry(vma, &eb->unbound, exec_link) {
600 err = eb_reserve_vma(eb, vma);
607 /* Resort *all* the objects into priority order */
608 INIT_LIST_HEAD(&eb->unbound);
609 INIT_LIST_HEAD(&last);
610 for (i = 0; i < count; i++) {
611 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
613 if (entry->flags & EXEC_OBJECT_PINNED &&
614 entry->flags & __EXEC_OBJECT_HAS_PIN)
617 vma = exec_to_vma(entry);
618 eb_unreserve_vma(vma, entry);
620 if (entry->flags & EXEC_OBJECT_PINNED)
621 list_add(&vma->exec_link, &eb->unbound);
622 else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
623 list_add_tail(&vma->exec_link, &eb->unbound);
625 list_add_tail(&vma->exec_link, &last);
627 list_splice_tail(&last, &eb->unbound);
634 /* Too fragmented, unbind everything and retry */
635 err = i915_gem_evict_vm(eb->vm);
646 static inline struct hlist_head *
647 ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle)
649 return &lut->ht[hash_32(handle, lut->ht_bits)];
653 ht_needs_resize(const struct i915_gem_context_vma_lut *lut)
655 return (4*lut->ht_count > 3*lut->ht_size ||
656 4*lut->ht_count + 1 < lut->ht_size);
659 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
661 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
664 return eb->buffer_count - 1;
667 static int eb_select_context(struct i915_execbuffer *eb)
669 struct i915_gem_context *ctx;
671 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
672 if (unlikely(IS_ERR(ctx)))
675 if (unlikely(i915_gem_context_is_banned(ctx))) {
676 DRM_DEBUG("Context %u tried to submit while banned\n",
681 eb->ctx = i915_gem_context_get(ctx);
682 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
684 eb->context_flags = 0;
685 if (ctx->flags & CONTEXT_NO_ZEROMAP)
686 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
691 static int eb_lookup_vmas(struct i915_execbuffer *eb)
693 #define INTERMEDIATE BIT(0)
694 const unsigned int count = eb->buffer_count;
695 struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut;
696 struct i915_vma *vma;
702 INIT_LIST_HEAD(&eb->relocs);
703 INIT_LIST_HEAD(&eb->unbound);
705 if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS))
706 flush_work(&lut->resize);
707 GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS);
709 for (i = 0; i < count; i++) {
710 __exec_to_vma(&eb->exec[i]) = 0;
712 hlist_for_each_entry(vma,
713 ht_head(lut, eb->exec[i].handle),
715 if (vma->ctx_handle != eb->exec[i].handle)
718 err = eb_add_vma(eb, &eb->exec[i], vma);
733 spin_lock(&eb->file->table_lock);
735 * Grab a reference to the object and release the lock so we can lookup
736 * or create the VMA without using GFP_ATOMIC
738 idr = &eb->file->object_idr;
739 for (i = slow_pass; i < count; i++) {
740 struct drm_i915_gem_object *obj;
742 if (__exec_to_vma(&eb->exec[i]))
745 obj = to_intel_bo(idr_find(idr, eb->exec[i].handle));
746 if (unlikely(!obj)) {
747 spin_unlock(&eb->file->table_lock);
748 DRM_DEBUG("Invalid object handle %d at index %d\n",
749 eb->exec[i].handle, i);
754 __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj;
756 spin_unlock(&eb->file->table_lock);
758 for (i = slow_pass; i < count; i++) {
759 struct drm_i915_gem_object *obj;
761 if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE))
765 * NOTE: We can leak any vmas created here when something fails
766 * later on. But that's no issue since vma_unbind can deal with
767 * vmas which are not actually bound. And since only
768 * lookup_or_create exists as an interface to get at the vma
769 * from the (obj, vm) we don't run the risk of creating
770 * duplicated vmas for the same vm.
772 obj = u64_to_ptr(typeof(*obj),
773 __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE);
774 vma = i915_vma_instance(obj, eb->vm, NULL);
775 if (unlikely(IS_ERR(vma))) {
776 DRM_DEBUG("Failed to lookup VMA\n");
781 /* First come, first served */
784 vma->ctx_handle = eb->exec[i].handle;
785 hlist_add_head(&vma->ctx_node,
786 ht_head(lut, eb->exec[i].handle));
788 lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS;
789 if (i915_vma_is_ggtt(vma)) {
790 GEM_BUG_ON(obj->vma_hashed);
791 obj->vma_hashed = vma;
797 err = eb_add_vma(eb, &eb->exec[i], vma);
801 /* Only after we validated the user didn't use our bits */
802 if (vma->ctx != eb->ctx) {
804 eb->exec[i].flags |= __EXEC_OBJECT_HAS_REF;
808 if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) {
809 if (ht_needs_resize(lut))
810 queue_work(system_highpri_wq, &lut->resize);
812 lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS;
816 /* take note of the batch buffer before we might reorder the lists */
817 i = eb_batch_index(eb);
818 eb->batch = exec_to_vma(&eb->exec[i]);
821 * SNA is doing fancy tricks with compressing batch buffers, which leads
822 * to negative relocation deltas. Usually that works out ok since the
823 * relocate address is still positive, except when the batch is placed
824 * very low in the GTT. Ensure this doesn't happen.
826 * Note that actual hangs have only been observed on gen7, but for
827 * paranoia do it everywhere.
829 if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED))
830 eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS;
831 if (eb->reloc_cache.has_fence)
832 eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE;
834 eb->args->flags |= __EXEC_VALIDATED;
835 return eb_reserve(eb);
838 for (i = slow_pass; i < count; i++) {
839 if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)
840 __exec_to_vma(&eb->exec[i]) = 0;
842 lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS;
847 static struct i915_vma *
848 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
850 if (eb->lut_size < 0) {
851 if (handle >= -eb->lut_size)
853 return exec_to_vma(&eb->exec[handle]);
855 struct hlist_head *head;
856 struct i915_vma *vma;
858 head = &eb->buckets[hash_32(handle, eb->lut_size)];
859 hlist_for_each_entry(vma, head, exec_node) {
860 if (vma->exec_handle == handle)
867 static void eb_release_vmas(const struct i915_execbuffer *eb)
869 const unsigned int count = eb->buffer_count;
872 for (i = 0; i < count; i++) {
873 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
874 struct i915_vma *vma = exec_to_vma(entry);
879 GEM_BUG_ON(vma->exec_entry != entry);
880 vma->exec_entry = NULL;
881 __exec_to_vma(entry) = 0;
883 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
884 __eb_unreserve_vma(vma, entry);
886 if (entry->flags & __EXEC_OBJECT_HAS_REF)
890 ~(__EXEC_OBJECT_RESERVED | __EXEC_OBJECT_HAS_REF);
894 static void eb_reset_vmas(const struct i915_execbuffer *eb)
897 if (eb->lut_size >= 0)
898 memset(eb->buckets, 0,
899 sizeof(struct hlist_head) << eb->lut_size);
902 static void eb_destroy(const struct i915_execbuffer *eb)
904 GEM_BUG_ON(eb->reloc_cache.rq);
906 if (eb->lut_size >= 0)
911 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
912 const struct i915_vma *target)
914 return gen8_canonical_addr((int)reloc->delta + target->node.start);
917 static void reloc_cache_init(struct reloc_cache *cache,
918 struct drm_i915_private *i915)
922 /* Must be a variable in the struct to allow GCC to unroll. */
923 cache->gen = INTEL_GEN(i915);
924 cache->has_llc = HAS_LLC(i915);
925 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
926 cache->has_fence = cache->gen < 4;
927 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
928 cache->node.allocated = false;
933 static inline void *unmask_page(unsigned long p)
935 return (void *)(uintptr_t)(p & PAGE_MASK);
938 static inline unsigned int unmask_flags(unsigned long p)
940 return p & ~PAGE_MASK;
943 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
945 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
947 struct drm_i915_private *i915 =
948 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
952 static void reloc_gpu_flush(struct reloc_cache *cache)
954 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
955 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
956 i915_gem_object_unpin_map(cache->rq->batch->obj);
957 i915_gem_chipset_flush(cache->rq->i915);
959 __i915_add_request(cache->rq, true);
963 static void reloc_cache_reset(struct reloc_cache *cache)
968 reloc_gpu_flush(cache);
973 vaddr = unmask_page(cache->vaddr);
974 if (cache->vaddr & KMAP) {
975 if (cache->vaddr & CLFLUSH_AFTER)
978 kunmap_atomic(vaddr);
979 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
982 io_mapping_unmap_atomic((void __iomem *)vaddr);
983 if (cache->node.allocated) {
984 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
986 ggtt->base.clear_range(&ggtt->base,
989 drm_mm_remove_node(&cache->node);
991 i915_vma_unpin((struct i915_vma *)cache->node.mm);
999 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1000 struct reloc_cache *cache,
1006 kunmap_atomic(unmask_page(cache->vaddr));
1008 unsigned int flushes;
1011 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
1013 return ERR_PTR(err);
1015 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1016 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1018 cache->vaddr = flushes | KMAP;
1019 cache->node.mm = (void *)obj;
1024 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
1025 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1031 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1032 struct reloc_cache *cache,
1035 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1036 unsigned long offset;
1040 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1042 struct i915_vma *vma;
1045 if (use_cpu_reloc(cache, obj))
1048 err = i915_gem_object_set_to_gtt_domain(obj, true);
1050 return ERR_PTR(err);
1052 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1053 PIN_MAPPABLE | PIN_NONBLOCK);
1055 memset(&cache->node, 0, sizeof(cache->node));
1056 err = drm_mm_insert_node_in_range
1057 (&ggtt->base.mm, &cache->node,
1058 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1059 0, ggtt->mappable_end,
1061 if (err) /* no inactive aperture space, use cpu reloc */
1064 err = i915_vma_put_fence(vma);
1066 i915_vma_unpin(vma);
1067 return ERR_PTR(err);
1070 cache->node.start = vma->node.start;
1071 cache->node.mm = (void *)vma;
1075 offset = cache->node.start;
1076 if (cache->node.allocated) {
1078 ggtt->base.insert_page(&ggtt->base,
1079 i915_gem_object_get_dma_address(obj, page),
1080 offset, I915_CACHE_NONE, 0);
1082 offset += page << PAGE_SHIFT;
1085 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable,
1088 cache->vaddr = (unsigned long)vaddr;
1093 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1094 struct reloc_cache *cache,
1099 if (cache->page == page) {
1100 vaddr = unmask_page(cache->vaddr);
1103 if ((cache->vaddr & KMAP) == 0)
1104 vaddr = reloc_iomap(obj, cache, page);
1106 vaddr = reloc_kmap(obj, cache, page);
1112 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1114 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1115 if (flushes & CLFLUSH_BEFORE) {
1123 * Writes to the same cacheline are serialised by the CPU
1124 * (including clflush). On the write path, we only require
1125 * that it hits memory in an orderly fashion and place
1126 * mb barriers at the start and end of the relocation phase
1127 * to ensure ordering of clflush wrt to the system.
1129 if (flushes & CLFLUSH_AFTER)
1135 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1136 struct i915_vma *vma,
1139 struct reloc_cache *cache = &eb->reloc_cache;
1140 struct drm_i915_gem_object *obj;
1141 struct drm_i915_gem_request *rq;
1142 struct i915_vma *batch;
1146 GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU);
1148 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1150 return PTR_ERR(obj);
1152 cmd = i915_gem_object_pin_map(obj,
1153 cache->has_llc ? I915_MAP_WB : I915_MAP_WC);
1154 i915_gem_object_unpin_pages(obj);
1156 return PTR_ERR(cmd);
1158 err = i915_gem_object_set_to_wc_domain(obj, false);
1162 batch = i915_vma_instance(obj, vma->vm, NULL);
1163 if (IS_ERR(batch)) {
1164 err = PTR_ERR(batch);
1168 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1172 rq = i915_gem_request_alloc(eb->engine, eb->ctx);
1178 err = i915_gem_request_await_object(rq, vma->obj, true);
1182 err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
1186 err = i915_switch_context(rq);
1190 err = eb->engine->emit_bb_start(rq,
1191 batch->node.start, PAGE_SIZE,
1192 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1196 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1197 i915_vma_move_to_active(batch, rq, 0);
1198 reservation_object_lock(batch->resv, NULL);
1199 reservation_object_add_excl_fence(batch->resv, &rq->fence);
1200 reservation_object_unlock(batch->resv);
1201 i915_vma_unpin(batch);
1203 i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1204 reservation_object_lock(vma->resv, NULL);
1205 reservation_object_add_excl_fence(vma->resv, &rq->fence);
1206 reservation_object_unlock(vma->resv);
1211 cache->rq_cmd = cmd;
1214 /* Return with batch mapping (cmd) still pinned */
1218 i915_add_request(rq);
1220 i915_vma_unpin(batch);
1222 i915_gem_object_unpin_map(obj);
1226 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1227 struct i915_vma *vma,
1230 struct reloc_cache *cache = &eb->reloc_cache;
1233 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1234 reloc_gpu_flush(cache);
1236 if (unlikely(!cache->rq)) {
1239 err = __reloc_gpu_alloc(eb, vma, len);
1241 return ERR_PTR(err);
1244 cmd = cache->rq_cmd + cache->rq_size;
1245 cache->rq_size += len;
1251 relocate_entry(struct i915_vma *vma,
1252 const struct drm_i915_gem_relocation_entry *reloc,
1253 struct i915_execbuffer *eb,
1254 const struct i915_vma *target)
1256 u64 offset = reloc->offset;
1257 u64 target_offset = relocation_target(reloc, target);
1258 bool wide = eb->reloc_cache.use_64bit_reloc;
1261 if (!eb->reloc_cache.vaddr &&
1262 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1263 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1264 const unsigned int gen = eb->reloc_cache.gen;
1270 len = offset & 7 ? 8 : 5;
1275 else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */
1278 batch = reloc_gpu(eb, vma, len);
1282 addr = gen8_canonical_addr(vma->node.start + offset);
1285 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1286 *batch++ = lower_32_bits(addr);
1287 *batch++ = upper_32_bits(addr);
1288 *batch++ = lower_32_bits(target_offset);
1290 addr = gen8_canonical_addr(addr + 4);
1292 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1293 *batch++ = lower_32_bits(addr);
1294 *batch++ = upper_32_bits(addr);
1295 *batch++ = upper_32_bits(target_offset);
1297 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1298 *batch++ = lower_32_bits(addr);
1299 *batch++ = upper_32_bits(addr);
1300 *batch++ = lower_32_bits(target_offset);
1301 *batch++ = upper_32_bits(target_offset);
1303 } else if (gen >= 6) {
1304 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1307 *batch++ = target_offset;
1308 } else if (gen >= 4) {
1309 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1312 *batch++ = target_offset;
1314 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1316 *batch++ = target_offset;
1323 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1325 return PTR_ERR(vaddr);
1327 clflush_write32(vaddr + offset_in_page(offset),
1328 lower_32_bits(target_offset),
1329 eb->reloc_cache.vaddr);
1332 offset += sizeof(u32);
1333 target_offset >>= 32;
1339 return target->node.start | UPDATE;
1343 eb_relocate_entry(struct i915_execbuffer *eb,
1344 struct i915_vma *vma,
1345 const struct drm_i915_gem_relocation_entry *reloc)
1347 struct i915_vma *target;
1350 /* we've already hold a reference to all valid objects */
1351 target = eb_get_vma(eb, reloc->target_handle);
1352 if (unlikely(!target))
1355 /* Validate that the target is in a valid r/w GPU domain */
1356 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1357 DRM_DEBUG("reloc with multiple write domains: "
1358 "target %d offset %d "
1359 "read %08x write %08x",
1360 reloc->target_handle,
1361 (int) reloc->offset,
1362 reloc->read_domains,
1363 reloc->write_domain);
1366 if (unlikely((reloc->write_domain | reloc->read_domains)
1367 & ~I915_GEM_GPU_DOMAINS)) {
1368 DRM_DEBUG("reloc with read/write non-GPU domains: "
1369 "target %d offset %d "
1370 "read %08x write %08x",
1371 reloc->target_handle,
1372 (int) reloc->offset,
1373 reloc->read_domains,
1374 reloc->write_domain);
1378 if (reloc->write_domain) {
1379 target->exec_entry->flags |= EXEC_OBJECT_WRITE;
1382 * Sandybridge PPGTT errata: We need a global gtt mapping
1383 * for MI and pipe_control writes because the gpu doesn't
1384 * properly redirect them through the ppgtt for non_secure
1387 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1388 IS_GEN6(eb->i915)) {
1389 err = i915_vma_bind(target, target->obj->cache_level,
1392 "Unexpected failure to bind target VMA!"))
1398 * If the relocation already has the right value in it, no
1399 * more work needs to be done.
1401 if (!DBG_FORCE_RELOC &&
1402 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1405 /* Check that the relocation address is valid... */
1406 if (unlikely(reloc->offset >
1407 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1408 DRM_DEBUG("Relocation beyond object bounds: "
1409 "target %d offset %d size %d.\n",
1410 reloc->target_handle,
1415 if (unlikely(reloc->offset & 3)) {
1416 DRM_DEBUG("Relocation not 4-byte aligned: "
1417 "target %d offset %d.\n",
1418 reloc->target_handle,
1419 (int)reloc->offset);
1424 * If we write into the object, we need to force the synchronisation
1425 * barrier, either with an asynchronous clflush or if we executed the
1426 * patching using the GPU (though that should be serialised by the
1427 * timeline). To be completely sure, and since we are required to
1428 * do relocations we are already stalling, disable the user's opt
1429 * of our synchronisation.
1431 vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC;
1433 /* and update the user's relocation entry */
1434 return relocate_entry(vma, reloc, eb, target);
1437 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1439 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1440 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1441 struct drm_i915_gem_relocation_entry __user *urelocs;
1442 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1443 unsigned int remain;
1445 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1446 remain = entry->relocation_count;
1447 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1451 * We must check that the entire relocation array is safe
1452 * to read. However, if the array is not writable the user loses
1453 * the updated relocation values.
1455 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs))))
1459 struct drm_i915_gem_relocation_entry *r = stack;
1460 unsigned int count =
1461 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1462 unsigned int copied;
1465 * This is the fast path and we cannot handle a pagefault
1466 * whilst holding the struct mutex lest the user pass in the
1467 * relocations contained within a mmaped bo. For in such a case
1468 * we, the page fault handler would call i915_gem_fault() and
1469 * we would try to acquire the struct mutex again. Obviously
1470 * this is bad and so lockdep complains vehemently.
1472 pagefault_disable();
1473 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1475 if (unlikely(copied)) {
1482 u64 offset = eb_relocate_entry(eb, vma, r);
1484 if (likely(offset == 0)) {
1485 } else if ((s64)offset < 0) {
1486 remain = (int)offset;
1490 * Note that reporting an error now
1491 * leaves everything in an inconsistent
1492 * state as we have *already* changed
1493 * the relocation value inside the
1494 * object. As we have not changed the
1495 * reloc.presumed_offset or will not
1496 * change the execobject.offset, on the
1497 * call we may not rewrite the value
1498 * inside the object, leaving it
1499 * dangling and causing a GPU hang. Unless
1500 * userspace dynamically rebuilds the
1501 * relocations on each execbuf rather than
1502 * presume a static tree.
1504 * We did previously check if the relocations
1505 * were writable (access_ok), an error now
1506 * would be a strange race with mprotect,
1507 * having already demonstrated that we
1508 * can read from this userspace address.
1510 offset = gen8_canonical_addr(offset & ~UPDATE);
1512 &urelocs[r-stack].presumed_offset);
1514 } while (r++, --count);
1515 urelocs += ARRAY_SIZE(stack);
1518 reloc_cache_reset(&eb->reloc_cache);
1523 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1525 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1526 struct drm_i915_gem_relocation_entry *relocs =
1527 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1531 for (i = 0; i < entry->relocation_count; i++) {
1532 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1534 if ((s64)offset < 0) {
1541 reloc_cache_reset(&eb->reloc_cache);
1545 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1547 const char __user *addr, *end;
1549 char __maybe_unused c;
1551 size = entry->relocation_count;
1555 if (size > N_RELOC(ULONG_MAX))
1558 addr = u64_to_user_ptr(entry->relocs_ptr);
1559 size *= sizeof(struct drm_i915_gem_relocation_entry);
1560 if (!access_ok(VERIFY_READ, addr, size))
1564 for (; addr < end; addr += PAGE_SIZE) {
1565 int err = __get_user(c, addr);
1569 return __get_user(c, end - 1);
1572 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1574 const unsigned int count = eb->buffer_count;
1578 for (i = 0; i < count; i++) {
1579 const unsigned int nreloc = eb->exec[i].relocation_count;
1580 struct drm_i915_gem_relocation_entry __user *urelocs;
1581 struct drm_i915_gem_relocation_entry *relocs;
1583 unsigned long copied;
1588 err = check_relocations(&eb->exec[i]);
1592 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1593 size = nreloc * sizeof(*relocs);
1595 relocs = kvmalloc_array(size, 1, GFP_TEMPORARY);
1602 /* copy_from_user is limited to < 4GiB */
1606 min_t(u64, BIT_ULL(31), size - copied);
1608 if (__copy_from_user((char *)relocs + copied,
1609 (char *)urelocs + copied,
1617 } while (copied < size);
1620 * As we do not update the known relocation offsets after
1621 * relocating (due to the complexities in lock handling),
1622 * we need to mark them as invalid now so that we force the
1623 * relocation processing next time. Just in case the target
1624 * object is evicted and then rebound into its old
1625 * presumed_offset before the next execbuffer - if that
1626 * happened we would make the mistake of assuming that the
1627 * relocations were valid.
1629 user_access_begin();
1630 for (copied = 0; copied < nreloc; copied++)
1632 &urelocs[copied].presumed_offset,
1637 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1644 struct drm_i915_gem_relocation_entry *relocs =
1645 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1646 if (eb->exec[i].relocation_count)
1652 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1654 const unsigned int count = eb->buffer_count;
1657 if (unlikely(i915.prefault_disable))
1660 for (i = 0; i < count; i++) {
1663 err = check_relocations(&eb->exec[i]);
1671 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1673 struct drm_device *dev = &eb->i915->drm;
1674 bool have_copy = false;
1675 struct i915_vma *vma;
1679 if (signal_pending(current)) {
1684 /* We may process another execbuffer during the unlock... */
1686 mutex_unlock(&dev->struct_mutex);
1689 * We take 3 passes through the slowpatch.
1691 * 1 - we try to just prefault all the user relocation entries and
1692 * then attempt to reuse the atomic pagefault disabled fast path again.
1694 * 2 - we copy the user entries to a local buffer here outside of the
1695 * local and allow ourselves to wait upon any rendering before
1698 * 3 - we already have a local copy of the relocation entries, but
1699 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1702 err = eb_prefault_relocations(eb);
1703 } else if (!have_copy) {
1704 err = eb_copy_relocations(eb);
1705 have_copy = err == 0;
1711 mutex_lock(&dev->struct_mutex);
1715 /* A frequent cause for EAGAIN are currently unavailable client pages */
1716 flush_workqueue(eb->i915->mm.userptr_wq);
1718 err = i915_mutex_lock_interruptible(dev);
1720 mutex_lock(&dev->struct_mutex);
1724 /* reacquire the objects */
1725 err = eb_lookup_vmas(eb);
1729 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1731 pagefault_disable();
1732 err = eb_relocate_vma(eb, vma);
1737 err = eb_relocate_vma_slow(eb, vma);
1744 * Leave the user relocations as are, this is the painfully slow path,
1745 * and we want to avoid the complication of dropping the lock whilst
1746 * having buffers reserved in the aperture and so causing spurious
1747 * ENOSPC for random operations.
1756 const unsigned int count = eb->buffer_count;
1759 for (i = 0; i < count; i++) {
1760 const struct drm_i915_gem_exec_object2 *entry =
1762 struct drm_i915_gem_relocation_entry *relocs;
1764 if (!entry->relocation_count)
1767 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1772 return err ?: have_copy;
1775 static int eb_relocate(struct i915_execbuffer *eb)
1777 if (eb_lookup_vmas(eb))
1780 /* The objects are in their final locations, apply the relocations. */
1781 if (eb->args->flags & __EXEC_HAS_RELOC) {
1782 struct i915_vma *vma;
1784 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1785 if (eb_relocate_vma(eb, vma))
1793 return eb_relocate_slow(eb);
1796 static void eb_export_fence(struct i915_vma *vma,
1797 struct drm_i915_gem_request *req,
1800 struct reservation_object *resv = vma->resv;
1803 * Ignore errors from failing to allocate the new fence, we can't
1804 * handle an error right now. Worst case should be missed
1805 * synchronisation leading to rendering corruption.
1807 reservation_object_lock(resv, NULL);
1808 if (flags & EXEC_OBJECT_WRITE)
1809 reservation_object_add_excl_fence(resv, &req->fence);
1810 else if (reservation_object_reserve_shared(resv) == 0)
1811 reservation_object_add_shared_fence(resv, &req->fence);
1812 reservation_object_unlock(resv);
1815 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1817 const unsigned int count = eb->buffer_count;
1821 for (i = 0; i < count; i++) {
1822 const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1823 struct i915_vma *vma = exec_to_vma(entry);
1824 struct drm_i915_gem_object *obj = vma->obj;
1826 if (entry->flags & EXEC_OBJECT_CAPTURE) {
1827 struct i915_gem_capture_list *capture;
1829 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1830 if (unlikely(!capture))
1833 capture->next = eb->request->capture_list;
1835 eb->request->capture_list = capture;
1838 if (entry->flags & EXEC_OBJECT_ASYNC)
1841 if (unlikely(obj->cache_dirty && !obj->cache_coherent))
1842 i915_gem_clflush_object(obj, 0);
1844 err = i915_gem_request_await_object
1845 (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE);
1850 i915_vma_move_to_active(vma, eb->request, entry->flags);
1851 __eb_unreserve_vma(vma, entry);
1852 vma->exec_entry = NULL;
1855 for (i = 0; i < count; i++) {
1856 const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1857 struct i915_vma *vma = exec_to_vma(entry);
1859 eb_export_fence(vma, eb->request, entry->flags);
1860 if (unlikely(entry->flags & __EXEC_OBJECT_HAS_REF))
1865 /* Unconditionally flush any chipset caches (for streaming writes). */
1866 i915_gem_chipset_flush(eb->i915);
1868 /* Unconditionally invalidate GPU caches and TLBs. */
1869 return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
1872 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1874 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1877 /* Kernel clipping was a DRI1 misfeature */
1878 if (exec->num_cliprects || exec->cliprects_ptr)
1881 if (exec->DR4 == 0xffffffff) {
1882 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1885 if (exec->DR1 || exec->DR4)
1888 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1894 void i915_vma_move_to_active(struct i915_vma *vma,
1895 struct drm_i915_gem_request *req,
1898 struct drm_i915_gem_object *obj = vma->obj;
1899 const unsigned int idx = req->engine->id;
1901 lockdep_assert_held(&req->i915->drm.struct_mutex);
1902 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1905 * Add a reference if we're newly entering the active list.
1906 * The order in which we add operations to the retirement queue is
1907 * vital here: mark_active adds to the start of the callback list,
1908 * such that subsequent callbacks are called first. Therefore we
1909 * add the active reference first and queue for it to be dropped
1912 if (!i915_vma_is_active(vma))
1913 obj->active_count++;
1914 i915_vma_set_active(vma, idx);
1915 i915_gem_active_set(&vma->last_read[idx], req);
1916 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1918 obj->base.write_domain = 0;
1919 if (flags & EXEC_OBJECT_WRITE) {
1920 obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
1922 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1923 i915_gem_active_set(&obj->frontbuffer_write, req);
1925 obj->base.read_domains = 0;
1927 obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
1929 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1930 i915_gem_active_set(&vma->last_fence, req);
1933 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1938 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1939 DRM_DEBUG("sol reset is gen7/rcs only\n");
1943 cs = intel_ring_begin(req, 4 * 2 + 2);
1947 *cs++ = MI_LOAD_REGISTER_IMM(4);
1948 for (i = 0; i < 4; i++) {
1949 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1953 intel_ring_advance(req, cs);
1958 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1960 struct drm_i915_gem_object *shadow_batch_obj;
1961 struct i915_vma *vma;
1964 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1965 PAGE_ALIGN(eb->batch_len));
1966 if (IS_ERR(shadow_batch_obj))
1967 return ERR_CAST(shadow_batch_obj);
1969 err = intel_engine_cmd_parser(eb->engine,
1972 eb->batch_start_offset,
1976 if (err == -EACCES) /* unhandled chained batch */
1983 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1988 memset(&eb->exec[eb->buffer_count++],
1989 0, sizeof(*vma->exec_entry));
1990 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
1991 __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma);
1994 i915_gem_object_unpin_pages(shadow_batch_obj);
1999 add_to_client(struct drm_i915_gem_request *req, struct drm_file *file)
2001 req->file_priv = file->driver_priv;
2002 list_add_tail(&req->client_link, &req->file_priv->mm.request_list);
2005 static int eb_submit(struct i915_execbuffer *eb)
2009 err = eb_move_to_gpu(eb);
2013 err = i915_switch_context(eb->request);
2017 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2018 err = i915_reset_gen7_sol_offsets(eb->request);
2023 err = eb->engine->emit_bb_start(eb->request,
2024 eb->batch->node.start +
2025 eb->batch_start_offset,
2035 * Find one BSD ring to dispatch the corresponding BSD command.
2036 * The engine index is returned.
2039 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2040 struct drm_file *file)
2042 struct drm_i915_file_private *file_priv = file->driver_priv;
2044 /* Check whether the file_priv has already selected one ring. */
2045 if ((int)file_priv->bsd_engine < 0)
2046 file_priv->bsd_engine = atomic_fetch_xor(1,
2047 &dev_priv->mm.bsd_engine_dispatch_index);
2049 return file_priv->bsd_engine;
2052 #define I915_USER_RINGS (4)
2054 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
2055 [I915_EXEC_DEFAULT] = RCS,
2056 [I915_EXEC_RENDER] = RCS,
2057 [I915_EXEC_BLT] = BCS,
2058 [I915_EXEC_BSD] = VCS,
2059 [I915_EXEC_VEBOX] = VECS
2062 static struct intel_engine_cs *
2063 eb_select_engine(struct drm_i915_private *dev_priv,
2064 struct drm_file *file,
2065 struct drm_i915_gem_execbuffer2 *args)
2067 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2068 struct intel_engine_cs *engine;
2070 if (user_ring_id > I915_USER_RINGS) {
2071 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2075 if ((user_ring_id != I915_EXEC_BSD) &&
2076 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
2077 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2078 "bsd dispatch flags: %d\n", (int)(args->flags));
2082 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
2083 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2085 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2086 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
2087 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2088 bsd_idx <= I915_EXEC_BSD_RING2) {
2089 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2092 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2097 engine = dev_priv->engine[_VCS(bsd_idx)];
2099 engine = dev_priv->engine[user_ring_map[user_ring_id]];
2103 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
2111 i915_gem_do_execbuffer(struct drm_device *dev,
2112 struct drm_file *file,
2113 struct drm_i915_gem_execbuffer2 *args,
2114 struct drm_i915_gem_exec_object2 *exec)
2116 struct i915_execbuffer eb;
2117 struct dma_fence *in_fence = NULL;
2118 struct sync_file *out_fence = NULL;
2119 int out_fence_fd = -1;
2122 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2123 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2125 eb.i915 = to_i915(dev);
2128 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2129 args->flags |= __EXEC_HAS_RELOC;
2132 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2133 if (USES_FULL_PPGTT(eb.i915))
2134 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
2135 reloc_cache_init(&eb.reloc_cache, eb.i915);
2137 eb.buffer_count = args->buffer_count;
2138 eb.batch_start_offset = args->batch_start_offset;
2139 eb.batch_len = args->batch_len;
2142 if (args->flags & I915_EXEC_SECURE) {
2143 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2146 eb.batch_flags |= I915_DISPATCH_SECURE;
2148 if (args->flags & I915_EXEC_IS_PINNED)
2149 eb.batch_flags |= I915_DISPATCH_PINNED;
2151 eb.engine = eb_select_engine(eb.i915, file, args);
2155 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2156 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2157 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2160 if (eb.engine->id != RCS) {
2161 DRM_DEBUG("RS is not available on %s\n",
2166 eb.batch_flags |= I915_DISPATCH_RS;
2169 if (args->flags & I915_EXEC_FENCE_IN) {
2170 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2175 if (args->flags & I915_EXEC_FENCE_OUT) {
2176 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2177 if (out_fence_fd < 0) {
2187 * Take a local wakeref for preparing to dispatch the execbuf as
2188 * we expect to access the hardware fairly frequently in the
2189 * process. Upon first dispatch, we acquire another prolonged
2190 * wakeref that we hold until the GPU has been idle for at least
2193 intel_runtime_pm_get(eb.i915);
2194 err = i915_mutex_lock_interruptible(dev);
2198 err = eb_select_context(&eb);
2202 err = eb_relocate(&eb);
2205 * If the user expects the execobject.offset and
2206 * reloc.presumed_offset to be an exact match,
2207 * as for using NO_RELOC, then we cannot update
2208 * the execobject.offset until we have completed
2211 args->flags &= ~__EXEC_HAS_RELOC;
2215 if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) {
2216 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2220 if (eb.batch_start_offset > eb.batch->size ||
2221 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2222 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2227 if (eb.engine->needs_cmd_parser && eb.batch_len) {
2228 struct i915_vma *vma;
2230 vma = eb_parse(&eb, drm_is_current_master(file));
2238 * Batch parsed and accepted:
2240 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2241 * bit from MI_BATCH_BUFFER_START commands issued in
2242 * the dispatch_execbuffer implementations. We
2243 * specifically don't want that set on batches the
2244 * command parser has accepted.
2246 eb.batch_flags |= I915_DISPATCH_SECURE;
2247 eb.batch_start_offset = 0;
2252 if (eb.batch_len == 0)
2253 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2256 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2257 * batch" bit. Hence we need to pin secure batches into the global gtt.
2258 * hsw should have this fixed, but bdw mucks it up again. */
2259 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2260 struct i915_vma *vma;
2263 * So on first glance it looks freaky that we pin the batch here
2264 * outside of the reservation loop. But:
2265 * - The batch is already pinned into the relevant ppgtt, so we
2266 * already have the backing storage fully allocated.
2267 * - No other BO uses the global gtt (well contexts, but meh),
2268 * so we don't really have issues with multiple objects not
2269 * fitting due to fragmentation.
2270 * So this is actually safe.
2272 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2281 /* All GPU relocation batches must be submitted prior to the user rq */
2282 GEM_BUG_ON(eb.reloc_cache.rq);
2284 /* Allocate a request for this batch buffer nice and early. */
2285 eb.request = i915_gem_request_alloc(eb.engine, eb.ctx);
2286 if (IS_ERR(eb.request)) {
2287 err = PTR_ERR(eb.request);
2288 goto err_batch_unpin;
2292 err = i915_gem_request_await_dma_fence(eb.request, in_fence);
2297 if (out_fence_fd != -1) {
2298 out_fence = sync_file_create(&eb.request->fence);
2306 * Whilst this request exists, batch_obj will be on the
2307 * active_list, and so will hold the active reference. Only when this
2308 * request is retired will the the batch_obj be moved onto the
2309 * inactive_list and lose its active reference. Hence we do not need
2310 * to explicitly hold another reference here.
2312 eb.request->batch = eb.batch;
2314 trace_i915_gem_request_queue(eb.request, eb.batch_flags);
2315 err = eb_submit(&eb);
2317 __i915_add_request(eb.request, err == 0);
2318 add_to_client(eb.request, file);
2322 fd_install(out_fence_fd, out_fence->file);
2323 args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
2324 args->rsvd2 |= (u64)out_fence_fd << 32;
2327 fput(out_fence->file);
2332 if (eb.batch_flags & I915_DISPATCH_SECURE)
2333 i915_vma_unpin(eb.batch);
2336 eb_release_vmas(&eb);
2337 i915_gem_context_put(eb.ctx);
2339 mutex_unlock(&dev->struct_mutex);
2341 intel_runtime_pm_put(eb.i915);
2343 if (out_fence_fd != -1)
2344 put_unused_fd(out_fence_fd);
2346 dma_fence_put(in_fence);
2351 * Legacy execbuffer just creates an exec2 list from the original exec object
2352 * list array and passes it to the real function.
2355 i915_gem_execbuffer(struct drm_device *dev, void *data,
2356 struct drm_file *file)
2358 const size_t sz = sizeof(struct drm_i915_gem_exec_object2);
2359 struct drm_i915_gem_execbuffer *args = data;
2360 struct drm_i915_gem_execbuffer2 exec2;
2361 struct drm_i915_gem_exec_object *exec_list = NULL;
2362 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2366 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2367 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2371 exec2.buffers_ptr = args->buffers_ptr;
2372 exec2.buffer_count = args->buffer_count;
2373 exec2.batch_start_offset = args->batch_start_offset;
2374 exec2.batch_len = args->batch_len;
2375 exec2.DR1 = args->DR1;
2376 exec2.DR4 = args->DR4;
2377 exec2.num_cliprects = args->num_cliprects;
2378 exec2.cliprects_ptr = args->cliprects_ptr;
2379 exec2.flags = I915_EXEC_RENDER;
2380 i915_execbuffer2_set_context_id(exec2, 0);
2382 if (!i915_gem_check_execbuffer(&exec2))
2385 /* Copy in the exec list from userland */
2386 exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list),
2387 __GFP_NOWARN | GFP_TEMPORARY);
2388 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2389 __GFP_NOWARN | GFP_TEMPORARY);
2390 if (exec_list == NULL || exec2_list == NULL) {
2391 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2392 args->buffer_count);
2397 err = copy_from_user(exec_list,
2398 u64_to_user_ptr(args->buffers_ptr),
2399 sizeof(*exec_list) * args->buffer_count);
2401 DRM_DEBUG("copy %d exec entries failed %d\n",
2402 args->buffer_count, err);
2408 for (i = 0; i < args->buffer_count; i++) {
2409 exec2_list[i].handle = exec_list[i].handle;
2410 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2411 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2412 exec2_list[i].alignment = exec_list[i].alignment;
2413 exec2_list[i].offset = exec_list[i].offset;
2414 if (INTEL_GEN(to_i915(dev)) < 4)
2415 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2417 exec2_list[i].flags = 0;
2420 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
2421 if (exec2.flags & __EXEC_HAS_RELOC) {
2422 struct drm_i915_gem_exec_object __user *user_exec_list =
2423 u64_to_user_ptr(args->buffers_ptr);
2425 /* Copy the new buffer offsets back to the user's exec list. */
2426 for (i = 0; i < args->buffer_count; i++) {
2427 if (!(exec2_list[i].offset & UPDATE))
2430 exec2_list[i].offset =
2431 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2432 exec2_list[i].offset &= PIN_OFFSET_MASK;
2433 if (__copy_to_user(&user_exec_list[i].offset,
2434 &exec2_list[i].offset,
2435 sizeof(user_exec_list[i].offset)))
2446 i915_gem_execbuffer2(struct drm_device *dev, void *data,
2447 struct drm_file *file)
2449 const size_t sz = sizeof(struct drm_i915_gem_exec_object2);
2450 struct drm_i915_gem_execbuffer2 *args = data;
2451 struct drm_i915_gem_exec_object2 *exec2_list;
2454 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2455 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2459 if (!i915_gem_check_execbuffer(args))
2462 /* Allocate an extra slot for use by the command parser */
2463 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2464 __GFP_NOWARN | GFP_TEMPORARY);
2465 if (exec2_list == NULL) {
2466 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2467 args->buffer_count);
2470 if (copy_from_user(exec2_list,
2471 u64_to_user_ptr(args->buffers_ptr),
2472 sizeof(*exec2_list) * args->buffer_count)) {
2473 DRM_DEBUG("copy %d exec entries failed\n", args->buffer_count);
2478 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
2481 * Now that we have begun execution of the batchbuffer, we ignore
2482 * any new error after this point. Also given that we have already
2483 * updated the associated relocations, we try to write out the current
2484 * object locations irrespective of any error.
2486 if (args->flags & __EXEC_HAS_RELOC) {
2487 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2488 u64_to_user_ptr(args->buffers_ptr);
2491 /* Copy the new buffer offsets back to the user's exec list. */
2492 user_access_begin();
2493 for (i = 0; i < args->buffer_count; i++) {
2494 if (!(exec2_list[i].offset & UPDATE))
2497 exec2_list[i].offset =
2498 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2499 unsafe_put_user(exec2_list[i].offset,
2500 &user_exec_list[i].offset,
2507 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;