drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_trace.h"
  31 #include "intel_drv.h"
  32
  33 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
  34
  35 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
  36 {
  37         if (i915.enable_ppgtt == 0)
  38                 return false;
  39
  40         if (i915.enable_ppgtt == 1 && full)
  41                 return false;
  42
  43         return true;
  44 }
  45
  46 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
  47 {
  48         if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
  49                 return 0;
  50
  51         if (enable_ppgtt == 1)
  52                 return 1;
  53
  54         if (enable_ppgtt == 2 && HAS_PPGTT(dev))
  55                 return 2;
  56
  57 #ifdef CONFIG_INTEL_IOMMU
  58         /* Disable ppgtt on SNB if VT-d is on. */
  59         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
  60                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
  61                 return 0;
  62         }
  63 #endif
  64
  65         return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
  66 }
  67
  68 #define GEN6_PPGTT_PD_ENTRIES 512
  69 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  70 typedef uint64_t gen8_gtt_pte_t;
  71 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  72
  73 /* PPGTT stuff */
  74 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  75 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  76
  77 #define GEN6_PDE_VALID                  (1 << 0)
  78 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  79 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  80
  81 #define GEN6_PTE_VALID                  (1 << 0)
  82 #define GEN6_PTE_UNCACHED               (1 << 1)
  83 #define HSW_PTE_UNCACHED                (0)
  84 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  85 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  86 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  87 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  88
  89 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  90  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  91  */
  92 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  93                                          (((bits) & 0x8) << (11 - 3)))
  94 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  95 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  96 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  97 #define HSW_WB_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x8)
  98 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  99 #define HSW_WT_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x7)
 100
 101 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
 102 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
 103
 104 /* GEN8 legacy style addressis defined as a 3 level page table:
 105  * 31:30 | 29:21 | 20:12 |  11:0
 106  * PDPE  |  PDE  |  PTE  | offset
 107  * The difference as compared to normal x86 3 level page table is the PDPEs are
 108  * programmed via register.
 109  */
 110 #define GEN8_PDPE_SHIFT                 30
 111 #define GEN8_PDPE_MASK                  0x3
 112 #define GEN8_PDE_SHIFT                  21
 113 #define GEN8_PDE_MASK                   0x1ff
 114 #define GEN8_PTE_SHIFT                  12
 115 #define GEN8_PTE_MASK                   0x1ff
 116
 117 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
 118 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
 119 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
 120 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
 121
 122 static void ppgtt_bind_vma(struct i915_vma *vma,
 123                            enum i915_cache_level cache_level,
 124                            u32 flags);
 125 static void ppgtt_unbind_vma(struct i915_vma *vma);
 126 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
 127
 128 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 129                                              enum i915_cache_level level,
 130                                              bool valid)
 131 {
 132         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 133         pte |= addr;
 134         if (level != I915_CACHE_NONE)
 135                 pte |= PPAT_CACHED_INDEX;
 136         else
 137                 pte |= PPAT_UNCACHED_INDEX;
 138         return pte;
 139 }
 140
 141 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
 142                                              dma_addr_t addr,
 143                                              enum i915_cache_level level)
 144 {
 145         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 146         pde |= addr;
 147         if (level != I915_CACHE_NONE)
 148                 pde |= PPAT_CACHED_PDE_INDEX;
 149         else
 150                 pde |= PPAT_UNCACHED_INDEX;
 151         return pde;
 152 }
 153
 154 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 155                                      enum i915_cache_level level,
 156                                      bool valid)
 157 {
 158         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 159         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 160
 161         switch (level) {
 162         case I915_CACHE_L3_LLC:
 163         case I915_CACHE_LLC:
 164                 pte |= GEN6_PTE_CACHE_LLC;
 165                 break;
 166         case I915_CACHE_NONE:
 167                 pte |= GEN6_PTE_UNCACHED;
 168                 break;
 169         default:
 170                 WARN_ON(1);
 171         }
 172
 173         return pte;
 174 }
 175
 176 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 177                                      enum i915_cache_level level,
 178                                      bool valid)
 179 {
 180         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 181         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 182
 183         switch (level) {
 184         case I915_CACHE_L3_LLC:
 185                 pte |= GEN7_PTE_CACHE_L3_LLC;
 186                 break;
 187         case I915_CACHE_LLC:
 188                 pte |= GEN6_PTE_CACHE_LLC;
 189                 break;
 190         case I915_CACHE_NONE:
 191                 pte |= GEN6_PTE_UNCACHED;
 192                 break;
 193         default:
 194                 WARN_ON(1);
 195         }
 196
 197         return pte;
 198 }
 199
 200 #define BYT_PTE_WRITEABLE               (1 << 1)
 201 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 202
 203 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 204                                      enum i915_cache_level level,
 205                                      bool valid)
 206 {
 207         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 208         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 209
 210         /* Mark the page as writeable.  Other platforms don't have a
 211          * setting for read-only/writable, so this matches that behavior.
 212          */
 213         pte |= BYT_PTE_WRITEABLE;
 214
 215         if (level != I915_CACHE_NONE)
 216                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 217
 218         return pte;
 219 }
 220
 221 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 222                                      enum i915_cache_level level,
 223                                      bool valid)
 224 {
 225         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 226         pte |= HSW_PTE_ADDR_ENCODE(addr);
 227
 228         if (level != I915_CACHE_NONE)
 229                 pte |= HSW_WB_LLC_AGE3;
 230
 231         return pte;
 232 }
 233
 234 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 235                                       enum i915_cache_level level,
 236                                       bool valid)
 237 {
 238         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 239         pte |= HSW_PTE_ADDR_ENCODE(addr);
 240
 241         switch (level) {
 242         case I915_CACHE_NONE:
 243                 break;
 244         case I915_CACHE_WT:
 245                 pte |= HSW_WT_ELLC_LLC_AGE3;
 246                 break;
 247         default:
 248                 pte |= HSW_WB_ELLC_LLC_AGE3;
 249                 break;
 250         }
 251
 252         return pte;
 253 }
 254
 255 /* Broadwell Page Directory Pointer Descriptors */
 256 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 257                            uint64_t val, bool synchronous)
 258 {
 259         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 260         int ret;
 261
 262         BUG_ON(entry >= 4);
 263
 264         if (synchronous) {
 265                 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
 266                 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 267                 return 0;
 268         }
 269
 270         ret = intel_ring_begin(ring, 6);
 271         if (ret)
 272                 return ret;
 273
 274         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 275         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 276         intel_ring_emit(ring, (u32)(val >> 32));
 277         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 278         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 279         intel_ring_emit(ring, (u32)(val));
 280         intel_ring_advance(ring);
 281
 282         return 0;
 283 }
 284
 285 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 286                           struct intel_ring_buffer *ring,
 287                           bool synchronous)
 288 {
 289         int i, ret;
 290
 291         /* bit of a hack to find the actual last used pd */
 292         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 293
 294         for (i = used_pd - 1; i >= 0; i--) {
 295                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 296                 ret = gen8_write_pdp(ring, i, addr, synchronous);
 297                 if (ret)
 298                         return ret;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 305                                    uint64_t start,
 306                                    uint64_t length,
 307                                    bool use_scratch)
 308 {
 309         struct i915_hw_ppgtt *ppgtt =
 310                 container_of(vm, struct i915_hw_ppgtt, base);
 311         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 312         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 313         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 314         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 315         unsigned num_entries = length >> PAGE_SHIFT;
 316         unsigned last_pte, i;
 317
 318         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 319                                       I915_CACHE_LLC, use_scratch);
 320
 321         while (num_entries) {
 322                 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
 323
 324                 last_pte = pte + num_entries;
 325                 if (last_pte > GEN8_PTES_PER_PAGE)
 326                         last_pte = GEN8_PTES_PER_PAGE;
 327
 328                 pt_vaddr = kmap_atomic(page_table);
 329
 330                 for (i = pte; i < last_pte; i++) {
 331                         pt_vaddr[i] = scratch_pte;
 332                         num_entries--;
 333                 }
 334
 335                 kunmap_atomic(pt_vaddr);
 336
 337                 pte = 0;
 338                 if (++pde == GEN8_PDES_PER_PAGE) {
 339                         pdpe++;
 340                         pde = 0;
 341                 }
 342         }
 343 }
 344
 345 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 346                                       struct sg_table *pages,
 347                                       uint64_t start,
 348                                       enum i915_cache_level cache_level)
 349 {
 350         struct i915_hw_ppgtt *ppgtt =
 351                 container_of(vm, struct i915_hw_ppgtt, base);
 352         gen8_gtt_pte_t *pt_vaddr;
 353         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 354         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 355         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 356         struct sg_page_iter sg_iter;
 357
 358         pt_vaddr = NULL;
 359
 360         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 361                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
 362                         break;
 363
 364                 if (pt_vaddr == NULL)
 365                         pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
 366
 367                 pt_vaddr[pte] =
 368                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 369                                         cache_level, true);
 370                 if (++pte == GEN8_PTES_PER_PAGE) {
 371                         kunmap_atomic(pt_vaddr);
 372                         pt_vaddr = NULL;
 373                         if (++pde == GEN8_PDES_PER_PAGE) {
 374                                 pdpe++;
 375                                 pde = 0;
 376                         }
 377                         pte = 0;
 378                 }
 379         }
 380         if (pt_vaddr)
 381                 kunmap_atomic(pt_vaddr);
 382 }
 383
 384 static void gen8_free_page_tables(struct page **pt_pages)
 385 {
 386         int i;
 387
 388         if (pt_pages == NULL)
 389                 return;
 390
 391         for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
 392                 if (pt_pages[i])
 393                         __free_pages(pt_pages[i], 0);
 394 }
 395
 396 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
 397 {
 398         int i;
 399
 400         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 401                 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
 402                 kfree(ppgtt->gen8_pt_pages[i]);
 403                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 404         }
 405
 406         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 407 }
 408
 409 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 410 {
 411         struct pci_dev *hwdev = ppgtt->base.dev->pdev;
 412         int i, j;
 413
 414         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 415                 /* TODO: In the future we'll support sparse mappings, so this
 416                  * will have to change. */
 417                 if (!ppgtt->pd_dma_addr[i])
 418                         continue;
 419
 420                 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
 421                                PCI_DMA_BIDIRECTIONAL);
 422
 423                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 424                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 425                         if (addr)
 426                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
 427                                                PCI_DMA_BIDIRECTIONAL);
 428                 }
 429         }
 430 }
 431
 432 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 433 {
 434         struct i915_hw_ppgtt *ppgtt =
 435                 container_of(vm, struct i915_hw_ppgtt, base);
 436
 437         list_del(&vm->global_link);
 438         drm_mm_takedown(&vm->mm);
 439
 440         gen8_ppgtt_unmap_pages(ppgtt);
 441         gen8_ppgtt_free(ppgtt);
 442 }
 443
 444 static struct page **__gen8_alloc_page_tables(void)
 445 {
 446         struct page **pt_pages;
 447         int i;
 448
 449         pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
 450         if (!pt_pages)
 451                 return ERR_PTR(-ENOMEM);
 452
 453         for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
 454                 pt_pages[i] = alloc_page(GFP_KERNEL);
 455                 if (!pt_pages[i])
 456                         goto bail;
 457         }
 458
 459         return pt_pages;
 460
 461 bail:
 462         gen8_free_page_tables(pt_pages);
 463         kfree(pt_pages);
 464         return ERR_PTR(-ENOMEM);
 465 }
 466
 467 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
 468                                            const int max_pdp)
 469 {
 470         struct page **pt_pages[GEN8_LEGACY_PDPS];
 471         int i, ret;
 472
 473         for (i = 0; i < max_pdp; i++) {
 474                 pt_pages[i] = __gen8_alloc_page_tables();
 475                 if (IS_ERR(pt_pages[i])) {
 476                         ret = PTR_ERR(pt_pages[i]);
 477                         goto unwind_out;
 478                 }
 479         }
 480
 481         /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
 482          * "atomic" - for cleanup purposes.
 483          */
 484         for (i = 0; i < max_pdp; i++)
 485                 ppgtt->gen8_pt_pages[i] = pt_pages[i];
 486
 487         return 0;
 488
 489 unwind_out:
 490         while (i--) {
 491                 gen8_free_page_tables(pt_pages[i]);
 492                 kfree(pt_pages[i]);
 493         }
 494
 495         return ret;
 496 }
 497
 498 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
 499 {
 500         int i;
 501
 502         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 503                 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
 504                                                      sizeof(dma_addr_t),
 505                                                      GFP_KERNEL);
 506                 if (!ppgtt->gen8_pt_dma_addr[i])
 507                         return -ENOMEM;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
 514                                                 const int max_pdp)
 515 {
 516         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 517         if (!ppgtt->pd_pages)
 518                 return -ENOMEM;
 519
 520         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 521         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 522
 523         return 0;
 524 }
 525
 526 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
 527                             const int max_pdp)
 528 {
 529         int ret;
 530
 531         ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
 532         if (ret)
 533                 return ret;
 534
 535         ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
 536         if (ret) {
 537                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 538                 return ret;
 539         }
 540
 541         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 542
 543         ret = gen8_ppgtt_allocate_dma(ppgtt);
 544         if (ret)
 545                 gen8_ppgtt_free(ppgtt);
 546
 547         return ret;
 548 }
 549
 550 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
 551                                              const int pd)
 552 {
 553         dma_addr_t pd_addr;
 554         int ret;
 555
 556         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
 557                                &ppgtt->pd_pages[pd], 0,
 558                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 559
 560         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
 561         if (ret)
 562                 return ret;
 563
 564         ppgtt->pd_dma_addr[pd] = pd_addr;
 565
 566         return 0;
 567 }
 568
 569 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
 570                                         const int pd,
 571                                         const int pt)
 572 {
 573         dma_addr_t pt_addr;
 574         struct page *p;
 575         int ret;
 576
 577         p = ppgtt->gen8_pt_pages[pd][pt];
 578         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
 579                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 580         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
 581         if (ret)
 582                 return ret;
 583
 584         ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
 585
 586         return 0;
 587 }
 588
 589 /**
 590  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 591  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 592  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 593  * space.
 594  *
 595  * FIXME: split allocation into smaller pieces. For now we only ever do this
 596  * once, but with full PPGTT, the multiple contiguous allocations will be bad.
 597  * TODO: Do something with the size parameter
 598  */
 599 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 600 {
 601         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 602         const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 603         int i, j, ret;
 604
 605         if (size % (1<<30))
 606                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 607
 608         /* 1. Do all our allocations for page directories and page tables. */
 609         ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
 610         if (ret)
 611                 return ret;
 612
 613         /*
 614          * 2. Create DMA mappings for the page directories and page tables.
 615          */
 616         for (i = 0; i < max_pdp; i++) {
 617                 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
 618                 if (ret)
 619                         goto bail;
 620
 621                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 622                         ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
 623                         if (ret)
 624                                 goto bail;
 625                 }
 626         }
 627
 628         /*
 629          * 3. Map all the page directory entires to point to the page tables
 630          * we've allocated.
 631          *
 632          * For now, the PPGTT helper functions all require that the PDEs are
 633          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 634          * will never need to touch the PDEs again.
 635          */
 636         for (i = 0; i < max_pdp; i++) {
 637                 gen8_ppgtt_pde_t *pd_vaddr;
 638                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 639                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 640                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 641                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 642                                                       I915_CACHE_LLC);
 643                 }
 644                 kunmap_atomic(pd_vaddr);
 645         }
 646
 647         ppgtt->enable = gen8_ppgtt_enable;
 648         ppgtt->switch_mm = gen8_mm_switch;
 649         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 650         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 651         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 652         ppgtt->base.start = 0;
 653         ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 654
 655         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 656
 657         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 658                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 659         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 660                          ppgtt->num_pd_entries,
 661                          (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
 662         return 0;
 663
 664 bail:
 665         gen8_ppgtt_unmap_pages(ppgtt);
 666         gen8_ppgtt_free(ppgtt);
 667         return ret;
 668 }
 669
 670 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 671 {
 672         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 673         struct i915_address_space *vm = &ppgtt->base;
 674         gen6_gtt_pte_t __iomem *pd_addr;
 675         gen6_gtt_pte_t scratch_pte;
 676         uint32_t pd_entry;
 677         int pte, pde;
 678
 679         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 680
 681         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 682                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 683
 684         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
 685                    ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
 686         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
 687                 u32 expected;
 688                 gen6_gtt_pte_t *pt_vaddr;
 689                 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
 690                 pd_entry = readl(pd_addr + pde);
 691                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 692
 693                 if (pd_entry != expected)
 694                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 695                                    pde,
 696                                    pd_entry,
 697                                    expected);
 698                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 699
 700                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
 701                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
 702                         unsigned long va =
 703                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
 704                                 (pte * PAGE_SIZE);
 705                         int i;
 706                         bool found = false;
 707                         for (i = 0; i < 4; i++)
 708                                 if (pt_vaddr[pte + i] != scratch_pte)
 709                                         found = true;
 710                         if (!found)
 711                                 continue;
 712
 713                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 714                         for (i = 0; i < 4; i++) {
 715                                 if (pt_vaddr[pte + i] != scratch_pte)
 716                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
 717                                 else
 718                                         seq_puts(m, "  SCRATCH ");
 719                         }
 720                         seq_puts(m, "\n");
 721                 }
 722                 kunmap_atomic(pt_vaddr);
 723         }
 724 }
 725
 726 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 727 {
 728         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 729         gen6_gtt_pte_t __iomem *pd_addr;
 730         uint32_t pd_entry;
 731         int i;
 732
 733         WARN_ON(ppgtt->pd_offset & 0x3f);
 734         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 735                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 736         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 737                 dma_addr_t pt_addr;
 738
 739                 pt_addr = ppgtt->pt_dma_addr[i];
 740                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 741                 pd_entry |= GEN6_PDE_VALID;
 742
 743                 writel(pd_entry, pd_addr + i);
 744         }
 745         readl(pd_addr);
 746 }
 747
 748 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 749 {
 750         BUG_ON(ppgtt->pd_offset & 0x3f);
 751
 752         return (ppgtt->pd_offset / 64) << 16;
 753 }
 754
 755 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 756                          struct intel_ring_buffer *ring,
 757                          bool synchronous)
 758 {
 759         struct drm_device *dev = ppgtt->base.dev;
 760         struct drm_i915_private *dev_priv = dev->dev_private;
 761         int ret;
 762
 763         /* If we're in reset, we can assume the GPU is sufficiently idle to
 764          * manually frob these bits. Ideally we could use the ring functions,
 765          * except our error handling makes it quite difficult (can't use
 766          * intel_ring_begin, ring->flush, or intel_ring_advance)
 767          *
 768          * FIXME: We should try not to special case reset
 769          */
 770         if (synchronous ||
 771             i915_reset_in_progress(&dev_priv->gpu_error)) {
 772                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 773                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 774                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 775                 POSTING_READ(RING_PP_DIR_BASE(ring));
 776                 return 0;
 777         }
 778
 779         /* NB: TLBs must be flushed and invalidated before a switch */
 780         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 781         if (ret)
 782                 return ret;
 783
 784         ret = intel_ring_begin(ring, 6);
 785         if (ret)
 786                 return ret;
 787
 788         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 789         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 790         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 791         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 792         intel_ring_emit(ring, get_pd_offset(ppgtt));
 793         intel_ring_emit(ring, MI_NOOP);
 794         intel_ring_advance(ring);
 795
 796         return 0;
 797 }
 798
 799 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 800                           struct intel_ring_buffer *ring,
 801                           bool synchronous)
 802 {
 803         struct drm_device *dev = ppgtt->base.dev;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         int ret;
 806
 807         /* If we're in reset, we can assume the GPU is sufficiently idle to
 808          * manually frob these bits. Ideally we could use the ring functions,
 809          * except our error handling makes it quite difficult (can't use
 810          * intel_ring_begin, ring->flush, or intel_ring_advance)
 811          *
 812          * FIXME: We should try not to special case reset
 813          */
 814         if (synchronous ||
 815             i915_reset_in_progress(&dev_priv->gpu_error)) {
 816                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 817                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 818                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 819                 POSTING_READ(RING_PP_DIR_BASE(ring));
 820                 return 0;
 821         }
 822
 823         /* NB: TLBs must be flushed and invalidated before a switch */
 824         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 825         if (ret)
 826                 return ret;
 827
 828         ret = intel_ring_begin(ring, 6);
 829         if (ret)
 830                 return ret;
 831
 832         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 833         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 834         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 835         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 836         intel_ring_emit(ring, get_pd_offset(ppgtt));
 837         intel_ring_emit(ring, MI_NOOP);
 838         intel_ring_advance(ring);
 839
 840         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 841         if (ring->id != RCS) {
 842                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 843                 if (ret)
 844                         return ret;
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 851                           struct intel_ring_buffer *ring,
 852                           bool synchronous)
 853 {
 854         struct drm_device *dev = ppgtt->base.dev;
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856
 857         if (!synchronous)
 858                 return 0;
 859
 860         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 861         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 862
 863         POSTING_READ(RING_PP_DIR_DCLV(ring));
 864
 865         return 0;
 866 }
 867
 868 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 869 {
 870         struct drm_device *dev = ppgtt->base.dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         struct intel_ring_buffer *ring;
 873         int j, ret;
 874
 875         for_each_ring(ring, dev_priv, j) {
 876                 I915_WRITE(RING_MODE_GEN7(ring),
 877                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 878
 879                 /* We promise to do a switch later with FULL PPGTT. If this is
 880                  * aliasing, this is the one and only switch we'll do */
 881                 if (USES_FULL_PPGTT(dev))
 882                         continue;
 883
 884                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 885                 if (ret)
 886                         goto err_out;
 887         }
 888
 889         return 0;
 890
 891 err_out:
 892         for_each_ring(ring, dev_priv, j)
 893                 I915_WRITE(RING_MODE_GEN7(ring),
 894                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 895         return ret;
 896 }
 897
 898 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 899 {
 900         struct drm_device *dev = ppgtt->base.dev;
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902         struct intel_ring_buffer *ring;
 903         uint32_t ecochk, ecobits;
 904         int i;
 905
 906         ecobits = I915_READ(GAC_ECO_BITS);
 907         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 908
 909         ecochk = I915_READ(GAM_ECOCHK);
 910         if (IS_HASWELL(dev)) {
 911                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 912         } else {
 913                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 914                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 915         }
 916         I915_WRITE(GAM_ECOCHK, ecochk);
 917
 918         for_each_ring(ring, dev_priv, i) {
 919                 int ret;
 920                 /* GFX_MODE is per-ring on gen7+ */
 921                 I915_WRITE(RING_MODE_GEN7(ring),
 922                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 923
 924                 /* We promise to do a switch later with FULL PPGTT. If this is
 925                  * aliasing, this is the one and only switch we'll do */
 926                 if (USES_FULL_PPGTT(dev))
 927                         continue;
 928
 929                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 930                 if (ret)
 931                         return ret;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 938 {
 939         struct drm_device *dev = ppgtt->base.dev;
 940         struct drm_i915_private *dev_priv = dev->dev_private;
 941         struct intel_ring_buffer *ring;
 942         uint32_t ecochk, gab_ctl, ecobits;
 943         int i;
 944
 945         ecobits = I915_READ(GAC_ECO_BITS);
 946         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 947                    ECOBITS_PPGTT_CACHE64B);
 948
 949         gab_ctl = I915_READ(GAB_CTL);
 950         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 951
 952         ecochk = I915_READ(GAM_ECOCHK);
 953         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 954
 955         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 956
 957         for_each_ring(ring, dev_priv, i) {
 958                 int ret = ppgtt->switch_mm(ppgtt, ring, true);
 959                 if (ret)
 960                         return ret;
 961         }
 962
 963         return 0;
 964 }
 965
 966 /* PPGTT support for Sandybdrige/Gen6 and later */
 967 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 968                                    uint64_t start,
 969                                    uint64_t length,
 970                                    bool use_scratch)
 971 {
 972         struct i915_hw_ppgtt *ppgtt =
 973                 container_of(vm, struct i915_hw_ppgtt, base);
 974         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 975         unsigned first_entry = start >> PAGE_SHIFT;
 976         unsigned num_entries = length >> PAGE_SHIFT;
 977         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 978         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 979         unsigned last_pte, i;
 980
 981         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 982
 983         while (num_entries) {
 984                 last_pte = first_pte + num_entries;
 985                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 986                         last_pte = I915_PPGTT_PT_ENTRIES;
 987
 988                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 989
 990                 for (i = first_pte; i < last_pte; i++)
 991                         pt_vaddr[i] = scratch_pte;
 992
 993                 kunmap_atomic(pt_vaddr);
 994
 995                 num_entries -= last_pte - first_pte;
 996                 first_pte = 0;
 997                 act_pt++;
 998         }
 999 }
1000
1001 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1002                                       struct sg_table *pages,
1003                                       uint64_t start,
1004                                       enum i915_cache_level cache_level)
1005 {
1006         struct i915_hw_ppgtt *ppgtt =
1007                 container_of(vm, struct i915_hw_ppgtt, base);
1008         gen6_gtt_pte_t *pt_vaddr;
1009         unsigned first_entry = start >> PAGE_SHIFT;
1010         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
1011         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
1012         struct sg_page_iter sg_iter;
1013
1014         pt_vaddr = NULL;
1015         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1016                 if (pt_vaddr == NULL)
1017                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
1018
1019                 pt_vaddr[act_pte] =
1020                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1021                                        cache_level, true);
1022                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
1023                         kunmap_atomic(pt_vaddr);
1024                         pt_vaddr = NULL;
1025                         act_pt++;
1026                         act_pte = 0;
1027                 }
1028         }
1029         if (pt_vaddr)
1030                 kunmap_atomic(pt_vaddr);
1031 }
1032
1033 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1034 {
1035         int i;
1036
1037         if (ppgtt->pt_dma_addr) {
1038                 for (i = 0; i < ppgtt->num_pd_entries; i++)
1039                         pci_unmap_page(ppgtt->base.dev->pdev,
1040                                        ppgtt->pt_dma_addr[i],
1041                                        4096, PCI_DMA_BIDIRECTIONAL);
1042         }
1043 }
1044
1045 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1046 {
1047         int i;
1048
1049         kfree(ppgtt->pt_dma_addr);
1050         for (i = 0; i < ppgtt->num_pd_entries; i++)
1051                 __free_page(ppgtt->pt_pages[i]);
1052         kfree(ppgtt->pt_pages);
1053 }
1054
1055 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1056 {
1057         struct i915_hw_ppgtt *ppgtt =
1058                 container_of(vm, struct i915_hw_ppgtt, base);
1059
1060         list_del(&vm->global_link);
1061         drm_mm_takedown(&ppgtt->base.mm);
1062         drm_mm_remove_node(&ppgtt->node);
1063
1064         gen6_ppgtt_unmap_pages(ppgtt);
1065         gen6_ppgtt_free(ppgtt);
1066 }
1067
1068 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1069 {
1070 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
1071 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
1072         struct drm_device *dev = ppgtt->base.dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         bool retried = false;
1075         int ret;
1076
1077         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1078          * allocator works in address space sizes, so it's multiplied by page
1079          * size. We allocate at the top of the GTT to avoid fragmentation.
1080          */
1081         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1082 alloc:
1083         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1084                                                   &ppgtt->node, GEN6_PD_SIZE,
1085                                                   GEN6_PD_ALIGN, 0,
1086                                                   0, dev_priv->gtt.base.total,
1087                                                   DRM_MM_SEARCH_DEFAULT,
1088                                                   DRM_MM_CREATE_DEFAULT);
1089         if (ret == -ENOSPC && !retried) {
1090                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1091                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1092                                                I915_CACHE_NONE,
1093                                                0, dev_priv->gtt.base.total,
1094                                                0);
1095                 if (ret)
1096                         return ret;
1097
1098                 retried = true;
1099                 goto alloc;
1100         }
1101
1102         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1103                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1104
1105         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1106         return ret;
1107 }
1108
1109 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1110 {
1111         int i;
1112
1113         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1114                                   GFP_KERNEL);
1115
1116         if (!ppgtt->pt_pages)
1117                 return -ENOMEM;
1118
1119         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1120                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1121                 if (!ppgtt->pt_pages[i]) {
1122                         gen6_ppgtt_free(ppgtt);
1123                         return -ENOMEM;
1124                 }
1125         }
1126
1127         return 0;
1128 }
1129
1130 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1131 {
1132         int ret;
1133
1134         ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1135         if (ret)
1136                 return ret;
1137
1138         ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1139         if (ret) {
1140                 drm_mm_remove_node(&ppgtt->node);
1141                 return ret;
1142         }
1143
1144         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1145                                      GFP_KERNEL);
1146         if (!ppgtt->pt_dma_addr) {
1147                 drm_mm_remove_node(&ppgtt->node);
1148                 gen6_ppgtt_free(ppgtt);
1149                 return -ENOMEM;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1156 {
1157         struct drm_device *dev = ppgtt->base.dev;
1158         int i;
1159
1160         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1161                 dma_addr_t pt_addr;
1162
1163                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1164                                        PCI_DMA_BIDIRECTIONAL);
1165
1166                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1167                         gen6_ppgtt_unmap_pages(ppgtt);
1168                         return -EIO;
1169                 }
1170
1171                 ppgtt->pt_dma_addr[i] = pt_addr;
1172         }
1173
1174         return 0;
1175 }
1176
1177 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1178 {
1179         struct drm_device *dev = ppgtt->base.dev;
1180         struct drm_i915_private *dev_priv = dev->dev_private;
1181         int ret;
1182
1183         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1184         if (IS_GEN6(dev)) {
1185                 ppgtt->enable = gen6_ppgtt_enable;
1186                 ppgtt->switch_mm = gen6_mm_switch;
1187         } else if (IS_HASWELL(dev)) {
1188                 ppgtt->enable = gen7_ppgtt_enable;
1189                 ppgtt->switch_mm = hsw_mm_switch;
1190         } else if (IS_GEN7(dev)) {
1191                 ppgtt->enable = gen7_ppgtt_enable;
1192                 ppgtt->switch_mm = gen7_mm_switch;
1193         } else
1194                 BUG();
1195
1196         ret = gen6_ppgtt_alloc(ppgtt);
1197         if (ret)
1198                 return ret;
1199
1200         ret = gen6_ppgtt_setup_page_tables(ppgtt);
1201         if (ret) {
1202                 gen6_ppgtt_free(ppgtt);
1203                 return ret;
1204         }
1205
1206         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1207         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1208         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1209         ppgtt->base.start = 0;
1210         ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1211         ppgtt->debug_dump = gen6_dump_ppgtt;
1212
1213         ppgtt->pd_offset =
1214                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1215
1216         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1217
1218         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1219                          ppgtt->node.size >> 20,
1220                          ppgtt->node.start / PAGE_SIZE);
1221
1222         return 0;
1223 }
1224
1225 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1226 {
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         int ret = 0;
1229
1230         ppgtt->base.dev = dev;
1231         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1232
1233         if (INTEL_INFO(dev)->gen < 8)
1234                 ret = gen6_ppgtt_init(ppgtt);
1235         else if (IS_GEN8(dev))
1236                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1237         else
1238                 BUG();
1239
1240         if (!ret) {
1241                 struct drm_i915_private *dev_priv = dev->dev_private;
1242                 kref_init(&ppgtt->ref);
1243                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1244                             ppgtt->base.total);
1245                 i915_init_vm(dev_priv, &ppgtt->base);
1246                 if (INTEL_INFO(dev)->gen < 8) {
1247                         gen6_write_pdes(ppgtt);
1248                         DRM_DEBUG("Adding PPGTT at offset %x\n",
1249                                   ppgtt->pd_offset << 10);
1250                 }
1251         }
1252
1253         return ret;
1254 }
1255
1256 static void
1257 ppgtt_bind_vma(struct i915_vma *vma,
1258                enum i915_cache_level cache_level,
1259                u32 flags)
1260 {
1261         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1262                                 cache_level);
1263 }
1264
1265 static void ppgtt_unbind_vma(struct i915_vma *vma)
1266 {
1267         vma->vm->clear_range(vma->vm,
1268                              vma->node.start,
1269                              vma->obj->base.size,
1270                              true);
1271 }
1272
1273 extern int intel_iommu_gfx_mapped;
1274 /* Certain Gen5 chipsets require require idling the GPU before
1275  * unmapping anything from the GTT when VT-d is enabled.
1276  */
1277 static inline bool needs_idle_maps(struct drm_device *dev)
1278 {
1279 #ifdef CONFIG_INTEL_IOMMU
1280         /* Query intel_iommu to see if we need the workaround. Presumably that
1281          * was loaded first.
1282          */
1283         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1284                 return true;
1285 #endif
1286         return false;
1287 }
1288
1289 static bool do_idling(struct drm_i915_private *dev_priv)
1290 {
1291         bool ret = dev_priv->mm.interruptible;
1292
1293         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1294                 dev_priv->mm.interruptible = false;
1295                 if (i915_gpu_idle(dev_priv->dev)) {
1296                         DRM_ERROR("Couldn't idle GPU\n");
1297                         /* Wait a bit, in hopes it avoids the hang */
1298                         udelay(10);
1299                 }
1300         }
1301
1302         return ret;
1303 }
1304
1305 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1306 {
1307         if (unlikely(dev_priv->gtt.do_idle_maps))
1308                 dev_priv->mm.interruptible = interruptible;
1309 }
1310
1311 void i915_check_and_clear_faults(struct drm_device *dev)
1312 {
1313         struct drm_i915_private *dev_priv = dev->dev_private;
1314         struct intel_ring_buffer *ring;
1315         int i;
1316
1317         if (INTEL_INFO(dev)->gen < 6)
1318                 return;
1319
1320         for_each_ring(ring, dev_priv, i) {
1321                 u32 fault_reg;
1322                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1323                 if (fault_reg & RING_FAULT_VALID) {
1324                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1325                                          "\tAddr: 0x%08lx\\n"
1326                                          "\tAddress space: %s\n"
1327                                          "\tSource ID: %d\n"
1328                                          "\tType: %d\n",
1329                                          fault_reg & PAGE_MASK,
1330                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1331                                          RING_FAULT_SRCID(fault_reg),
1332                                          RING_FAULT_FAULT_TYPE(fault_reg));
1333                         I915_WRITE(RING_FAULT_REG(ring),
1334                                    fault_reg & ~RING_FAULT_VALID);
1335                 }
1336         }
1337         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1338 }
1339
1340 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1341 {
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343
1344         /* Don't bother messing with faults pre GEN6 as we have little
1345          * documentation supporting that it's a good idea.
1346          */
1347         if (INTEL_INFO(dev)->gen < 6)
1348                 return;
1349
1350         i915_check_and_clear_faults(dev);
1351
1352         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1353                                        dev_priv->gtt.base.start,
1354                                        dev_priv->gtt.base.total,
1355                                        true);
1356 }
1357
1358 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1359 {
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         struct drm_i915_gem_object *obj;
1362         struct i915_address_space *vm;
1363
1364         i915_check_and_clear_faults(dev);
1365
1366         /* First fill our portion of the GTT with scratch pages */
1367         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1368                                        dev_priv->gtt.base.start,
1369                                        dev_priv->gtt.base.total,
1370                                        true);
1371
1372         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1373                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1374                                                            &dev_priv->gtt.base);
1375                 if (!vma)
1376                         continue;
1377
1378                 i915_gem_clflush_object(obj, obj->pin_display);
1379                 /* The bind_vma code tries to be smart about tracking mappings.
1380                  * Unfortunately above, we've just wiped out the mappings
1381                  * without telling our object about it. So we need to fake it.
1382                  */
1383                 obj->has_global_gtt_mapping = 0;
1384                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1385         }
1386
1387
1388         if (INTEL_INFO(dev)->gen >= 8) {
1389                 gen8_setup_private_ppat(dev_priv);
1390                 return;
1391         }
1392
1393         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1394                 /* TODO: Perhaps it shouldn't be gen6 specific */
1395                 if (i915_is_ggtt(vm)) {
1396                         if (dev_priv->mm.aliasing_ppgtt)
1397                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1398                         continue;
1399                 }
1400
1401                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1402         }
1403
1404         i915_gem_chipset_flush(dev);
1405 }
1406
1407 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1408 {
1409         if (obj->has_dma_mapping)
1410                 return 0;
1411
1412         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1413                         obj->pages->sgl, obj->pages->nents,
1414                         PCI_DMA_BIDIRECTIONAL))
1415                 return -ENOSPC;
1416
1417         return 0;
1418 }
1419
1420 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1421 {
1422 #ifdef writeq
1423         writeq(pte, addr);
1424 #else
1425         iowrite32((u32)pte, addr);
1426         iowrite32(pte >> 32, addr + 4);
1427 #endif
1428 }
1429
1430 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1431                                      struct sg_table *st,
1432                                      uint64_t start,
1433                                      enum i915_cache_level level)
1434 {
1435         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1436         unsigned first_entry = start >> PAGE_SHIFT;
1437         gen8_gtt_pte_t __iomem *gtt_entries =
1438                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1439         int i = 0;
1440         struct sg_page_iter sg_iter;
1441         dma_addr_t addr;
1442
1443         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1444                 addr = sg_dma_address(sg_iter.sg) +
1445                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1446                 gen8_set_pte(&gtt_entries[i],
1447                              gen8_pte_encode(addr, level, true));
1448                 i++;
1449         }
1450
1451         /*
1452          * XXX: This serves as a posting read to make sure that the PTE has
1453          * actually been updated. There is some concern that even though
1454          * registers and PTEs are within the same BAR that they are potentially
1455          * of NUMA access patterns. Therefore, even with the way we assume
1456          * hardware should work, we must keep this posting read for paranoia.
1457          */
1458         if (i != 0)
1459                 WARN_ON(readq(&gtt_entries[i-1])
1460                         != gen8_pte_encode(addr, level, true));
1461
1462         /* This next bit makes the above posting read even more important. We
1463          * want to flush the TLBs only after we're certain all the PTE updates
1464          * have finished.
1465          */
1466         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1467         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1468 }
1469
1470 /*
1471  * Binds an object into the global gtt with the specified cache level. The object
1472  * will be accessible to the GPU via commands whose operands reference offsets
1473  * within the global GTT as well as accessible by the GPU through the GMADR
1474  * mapped BAR (dev_priv->mm.gtt->gtt).
1475  */
1476 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1477                                      struct sg_table *st,
1478                                      uint64_t start,
1479                                      enum i915_cache_level level)
1480 {
1481         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1482         unsigned first_entry = start >> PAGE_SHIFT;
1483         gen6_gtt_pte_t __iomem *gtt_entries =
1484                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1485         int i = 0;
1486         struct sg_page_iter sg_iter;
1487         dma_addr_t addr;
1488
1489         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1490                 addr = sg_page_iter_dma_address(&sg_iter);
1491                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1492                 i++;
1493         }
1494
1495         /* XXX: This serves as a posting read to make sure that the PTE has
1496          * actually been updated. There is some concern that even though
1497          * registers and PTEs are within the same BAR that they are potentially
1498          * of NUMA access patterns. Therefore, even with the way we assume
1499          * hardware should work, we must keep this posting read for paranoia.
1500          */
1501         if (i != 0)
1502                 WARN_ON(readl(&gtt_entries[i-1]) !=
1503                         vm->pte_encode(addr, level, true));
1504
1505         /* This next bit makes the above posting read even more important. We
1506          * want to flush the TLBs only after we're certain all the PTE updates
1507          * have finished.
1508          */
1509         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1510         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1511 }
1512
1513 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1514                                   uint64_t start,
1515                                   uint64_t length,
1516                                   bool use_scratch)
1517 {
1518         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1519         unsigned first_entry = start >> PAGE_SHIFT;
1520         unsigned num_entries = length >> PAGE_SHIFT;
1521         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1522                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1523         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1524         int i;
1525
1526         if (WARN(num_entries > max_entries,
1527                  "First entry = %d; Num entries = %d (max=%d)\n",
1528                  first_entry, num_entries, max_entries))
1529                 num_entries = max_entries;
1530
1531         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1532                                       I915_CACHE_LLC,
1533                                       use_scratch);
1534         for (i = 0; i < num_entries; i++)
1535                 gen8_set_pte(&gtt_base[i], scratch_pte);
1536         readl(gtt_base);
1537 }
1538
1539 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1540                                   uint64_t start,
1541                                   uint64_t length,
1542                                   bool use_scratch)
1543 {
1544         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1545         unsigned first_entry = start >> PAGE_SHIFT;
1546         unsigned num_entries = length >> PAGE_SHIFT;
1547         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1548                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1549         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1550         int i;
1551
1552         if (WARN(num_entries > max_entries,
1553                  "First entry = %d; Num entries = %d (max=%d)\n",
1554                  first_entry, num_entries, max_entries))
1555                 num_entries = max_entries;
1556
1557         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1558
1559         for (i = 0; i < num_entries; i++)
1560                 iowrite32(scratch_pte, &gtt_base[i]);
1561         readl(gtt_base);
1562 }
1563
1564
1565 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1566                                enum i915_cache_level cache_level,
1567                                u32 unused)
1568 {
1569         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1570         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1571                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1572
1573         BUG_ON(!i915_is_ggtt(vma->vm));
1574         intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1575         vma->obj->has_global_gtt_mapping = 1;
1576 }
1577
1578 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1579                                   uint64_t start,
1580                                   uint64_t length,
1581                                   bool unused)
1582 {
1583         unsigned first_entry = start >> PAGE_SHIFT;
1584         unsigned num_entries = length >> PAGE_SHIFT;
1585         intel_gtt_clear_range(first_entry, num_entries);
1586 }
1587
1588 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1589 {
1590         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1591         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1592
1593         BUG_ON(!i915_is_ggtt(vma->vm));
1594         vma->obj->has_global_gtt_mapping = 0;
1595         intel_gtt_clear_range(first, size);
1596 }
1597
1598 static void ggtt_bind_vma(struct i915_vma *vma,
1599                           enum i915_cache_level cache_level,
1600                           u32 flags)
1601 {
1602         struct drm_device *dev = vma->vm->dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         struct drm_i915_gem_object *obj = vma->obj;
1605
1606         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1607          * or we have a global mapping already but the cacheability flags have
1608          * changed, set the global PTEs.
1609          *
1610          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1611          * instead if none of the above hold true.
1612          *
1613          * NB: A global mapping should only be needed for special regions like
1614          * "gtt mappable", SNB errata, or if specified via special execbuf
1615          * flags. At all other times, the GPU will use the aliasing PPGTT.
1616          */
1617         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1618                 if (!obj->has_global_gtt_mapping ||
1619                     (cache_level != obj->cache_level)) {
1620                         vma->vm->insert_entries(vma->vm, obj->pages,
1621                                                 vma->node.start,
1622                                                 cache_level);
1623                         obj->has_global_gtt_mapping = 1;
1624                 }
1625         }
1626
1627         if (dev_priv->mm.aliasing_ppgtt &&
1628             (!obj->has_aliasing_ppgtt_mapping ||
1629              (cache_level != obj->cache_level))) {
1630                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1631                 appgtt->base.insert_entries(&appgtt->base,
1632                                             vma->obj->pages,
1633                                             vma->node.start,
1634                                             cache_level);
1635                 vma->obj->has_aliasing_ppgtt_mapping = 1;
1636         }
1637 }
1638
1639 static void ggtt_unbind_vma(struct i915_vma *vma)
1640 {
1641         struct drm_device *dev = vma->vm->dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         struct drm_i915_gem_object *obj = vma->obj;
1644
1645         if (obj->has_global_gtt_mapping) {
1646                 vma->vm->clear_range(vma->vm,
1647                                      vma->node.start,
1648                                      obj->base.size,
1649                                      true);
1650                 obj->has_global_gtt_mapping = 0;
1651         }
1652
1653         if (obj->has_aliasing_ppgtt_mapping) {
1654                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1655                 appgtt->base.clear_range(&appgtt->base,
1656                                          vma->node.start,
1657                                          obj->base.size,
1658                                          true);
1659                 obj->has_aliasing_ppgtt_mapping = 0;
1660         }
1661 }
1662
1663 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1664 {
1665         struct drm_device *dev = obj->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         bool interruptible;
1668
1669         interruptible = do_idling(dev_priv);
1670
1671         if (!obj->has_dma_mapping)
1672                 dma_unmap_sg(&dev->pdev->dev,
1673                              obj->pages->sgl, obj->pages->nents,
1674                              PCI_DMA_BIDIRECTIONAL);
1675
1676         undo_idling(dev_priv, interruptible);
1677 }
1678
1679 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1680                                   unsigned long color,
1681                                   unsigned long *start,
1682                                   unsigned long *end)
1683 {
1684         if (node->color != color)
1685                 *start += 4096;
1686
1687         if (!list_empty(&node->node_list)) {
1688                 node = list_entry(node->node_list.next,
1689                                   struct drm_mm_node,
1690                                   node_list);
1691                 if (node->allocated && node->color != color)
1692                         *end -= 4096;
1693         }
1694 }
1695
1696 void i915_gem_setup_global_gtt(struct drm_device *dev,
1697                                unsigned long start,
1698                                unsigned long mappable_end,
1699                                unsigned long end)
1700 {
1701         /* Let GEM Manage all of the aperture.
1702          *
1703          * However, leave one page at the end still bound to the scratch page.
1704          * There are a number of places where the hardware apparently prefetches
1705          * past the end of the object, and we've seen multiple hangs with the
1706          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1707          * aperture.  One page should be enough to keep any prefetching inside
1708          * of the aperture.
1709          */
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1712         struct drm_mm_node *entry;
1713         struct drm_i915_gem_object *obj;
1714         unsigned long hole_start, hole_end;
1715
1716         BUG_ON(mappable_end > end);
1717
1718         /* Subtract the guard page ... */
1719         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1720         if (!HAS_LLC(dev))
1721                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1722
1723         /* Mark any preallocated objects as occupied */
1724         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1725                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1726                 int ret;
1727                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1728                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1729
1730                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1731                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1732                 if (ret)
1733                         DRM_DEBUG_KMS("Reservation failed\n");
1734                 obj->has_global_gtt_mapping = 1;
1735         }
1736
1737         dev_priv->gtt.base.start = start;
1738         dev_priv->gtt.base.total = end - start;
1739
1740         /* Clear any non-preallocated blocks */
1741         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1742                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1743                               hole_start, hole_end);
1744                 ggtt_vm->clear_range(ggtt_vm, hole_start,
1745                                      hole_end - hole_start, true);
1746         }
1747
1748         /* And finally clear the reserved guard page */
1749         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1750 }
1751
1752 void i915_gem_init_global_gtt(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         unsigned long gtt_size, mappable_size;
1756
1757         gtt_size = dev_priv->gtt.base.total;
1758         mappable_size = dev_priv->gtt.mappable_end;
1759
1760         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1761 }
1762
1763 static int setup_scratch_page(struct drm_device *dev)
1764 {
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         struct page *page;
1767         dma_addr_t dma_addr;
1768
1769         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1770         if (page == NULL)
1771                 return -ENOMEM;
1772         get_page(page);
1773         set_pages_uc(page, 1);
1774
1775 #ifdef CONFIG_INTEL_IOMMU
1776         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1777                                 PCI_DMA_BIDIRECTIONAL);
1778         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1779                 return -EINVAL;
1780 #else
1781         dma_addr = page_to_phys(page);
1782 #endif
1783         dev_priv->gtt.base.scratch.page = page;
1784         dev_priv->gtt.base.scratch.addr = dma_addr;
1785
1786         return 0;
1787 }
1788
1789 static void teardown_scratch_page(struct drm_device *dev)
1790 {
1791         struct drm_i915_private *dev_priv = dev->dev_private;
1792         struct page *page = dev_priv->gtt.base.scratch.page;
1793
1794         set_pages_wb(page, 1);
1795         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1796                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1797         put_page(page);
1798         __free_page(page);
1799 }
1800
1801 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1802 {
1803         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1804         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1805         return snb_gmch_ctl << 20;
1806 }
1807
1808 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1809 {
1810         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1811         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1812         if (bdw_gmch_ctl)
1813                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1814         return bdw_gmch_ctl << 20;
1815 }
1816
1817 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1818 {
1819         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1820         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1821         return snb_gmch_ctl << 25; /* 32 MB units */
1822 }
1823
1824 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1825 {
1826         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1827         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1828         return bdw_gmch_ctl << 25; /* 32 MB units */
1829 }
1830
1831 static int ggtt_probe_common(struct drm_device *dev,
1832                              size_t gtt_size)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         phys_addr_t gtt_phys_addr;
1836         int ret;
1837
1838         /* For Modern GENs the PTEs and register space are split in the BAR */
1839         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1840                 (pci_resource_len(dev->pdev, 0) / 2);
1841
1842         dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1843         if (!dev_priv->gtt.gsm) {
1844                 DRM_ERROR("Failed to map the gtt page table\n");
1845                 return -ENOMEM;
1846         }
1847
1848         ret = setup_scratch_page(dev);
1849         if (ret) {
1850                 DRM_ERROR("Scratch setup failed\n");
1851                 /* iounmap will also get called at remove, but meh */
1852                 iounmap(dev_priv->gtt.gsm);
1853         }
1854
1855         return ret;
1856 }
1857
1858 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1859  * bits. When using advanced contexts each context stores its own PAT, but
1860  * writing this data shouldn't be harmful even in those cases. */
1861 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1862 {
1863 #define GEN8_PPAT_UC            (0<<0)
1864 #define GEN8_PPAT_WC            (1<<0)
1865 #define GEN8_PPAT_WT            (2<<0)
1866 #define GEN8_PPAT_WB            (3<<0)
1867 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1868 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1869 #define GEN8_PPAT_LLC           (1<<2)
1870 #define GEN8_PPAT_LLCELLC       (2<<2)
1871 #define GEN8_PPAT_LLCeLLC       (3<<2)
1872 #define GEN8_PPAT_AGE(x)        (x<<4)
1873 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1874         uint64_t pat;
1875
1876         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1877               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1878               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1879               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1880               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1881               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1882               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1883               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1884
1885         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1886          * write would work. */
1887         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1888         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1889 }
1890
1891 static int gen8_gmch_probe(struct drm_device *dev,
1892                            size_t *gtt_total,
1893                            size_t *stolen,
1894                            phys_addr_t *mappable_base,
1895                            unsigned long *mappable_end)
1896 {
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898         unsigned int gtt_size;
1899         u16 snb_gmch_ctl;
1900         int ret;
1901
1902         /* TODO: We're not aware of mappable constraints on gen8 yet */
1903         *mappable_base = pci_resource_start(dev->pdev, 2);
1904         *mappable_end = pci_resource_len(dev->pdev, 2);
1905
1906         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1907                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1908
1909         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1910
1911         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1912
1913         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1914         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1915
1916         gen8_setup_private_ppat(dev_priv);
1917
1918         ret = ggtt_probe_common(dev, gtt_size);
1919
1920         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1921         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1922
1923         return ret;
1924 }
1925
1926 static int gen6_gmch_probe(struct drm_device *dev,
1927                            size_t *gtt_total,
1928                            size_t *stolen,
1929                            phys_addr_t *mappable_base,
1930                            unsigned long *mappable_end)
1931 {
1932         struct drm_i915_private *dev_priv = dev->dev_private;
1933         unsigned int gtt_size;
1934         u16 snb_gmch_ctl;
1935         int ret;
1936
1937         *mappable_base = pci_resource_start(dev->pdev, 2);
1938         *mappable_end = pci_resource_len(dev->pdev, 2);
1939
1940         /* 64/512MB is the current min/max we actually know of, but this is just
1941          * a coarse sanity check.
1942          */
1943         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1944                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1945                           dev_priv->gtt.mappable_end);
1946                 return -ENXIO;
1947         }
1948
1949         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1950                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1951         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1952
1953         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1954
1955         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1956         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1957
1958         ret = ggtt_probe_common(dev, gtt_size);
1959
1960         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1961         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1962
1963         return ret;
1964 }
1965
1966 static void gen6_gmch_remove(struct i915_address_space *vm)
1967 {
1968
1969         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1970
1971         drm_mm_takedown(&vm->mm);
1972         iounmap(gtt->gsm);
1973         teardown_scratch_page(vm->dev);
1974 }
1975
1976 static int i915_gmch_probe(struct drm_device *dev,
1977                            size_t *gtt_total,
1978                            size_t *stolen,
1979                            phys_addr_t *mappable_base,
1980                            unsigned long *mappable_end)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         int ret;
1984
1985         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1986         if (!ret) {
1987                 DRM_ERROR("failed to set up gmch\n");
1988                 return -EIO;
1989         }
1990
1991         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1992
1993         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1994         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1995
1996         if (unlikely(dev_priv->gtt.do_idle_maps))
1997                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1998
1999         return 0;
2000 }
2001
2002 static void i915_gmch_remove(struct i915_address_space *vm)
2003 {
2004         intel_gmch_remove();
2005 }
2006
2007 int i915_gem_gtt_init(struct drm_device *dev)
2008 {
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         struct i915_gtt *gtt = &dev_priv->gtt;
2011         int ret;
2012
2013         if (INTEL_INFO(dev)->gen <= 5) {
2014                 gtt->gtt_probe = i915_gmch_probe;
2015                 gtt->base.cleanup = i915_gmch_remove;
2016         } else if (INTEL_INFO(dev)->gen < 8) {
2017                 gtt->gtt_probe = gen6_gmch_probe;
2018                 gtt->base.cleanup = gen6_gmch_remove;
2019                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2020                         gtt->base.pte_encode = iris_pte_encode;
2021                 else if (IS_HASWELL(dev))
2022                         gtt->base.pte_encode = hsw_pte_encode;
2023                 else if (IS_VALLEYVIEW(dev))
2024                         gtt->base.pte_encode = byt_pte_encode;
2025                 else if (INTEL_INFO(dev)->gen >= 7)
2026                         gtt->base.pte_encode = ivb_pte_encode;
2027                 else
2028                         gtt->base.pte_encode = snb_pte_encode;
2029         } else {
2030                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2031                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2032         }
2033
2034         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2035                              &gtt->mappable_base, &gtt->mappable_end);
2036         if (ret)
2037                 return ret;
2038
2039         gtt->base.dev = dev;
2040
2041         /* GMADR is the PCI mmio aperture into the global GTT. */
2042         DRM_INFO("Memory usable by graphics device = %zdM\n",
2043                  gtt->base.total >> 20);
2044         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2045         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2046         /*
2047          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2048          * user's requested state against the hardware/driver capabilities.  We
2049          * do this now so that we can print out any log messages once rather
2050          * than every time we check intel_enable_ppgtt().
2051          */
2052         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2053         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2054
2055         return 0;
2056 }
2057
2058 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2059                                               struct i915_address_space *vm)
2060 {
2061         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2062         if (vma == NULL)
2063                 return ERR_PTR(-ENOMEM);
2064
2065         INIT_LIST_HEAD(&vma->vma_link);
2066         INIT_LIST_HEAD(&vma->mm_list);
2067         INIT_LIST_HEAD(&vma->exec_list);
2068         vma->vm = vm;
2069         vma->obj = obj;
2070
2071         switch (INTEL_INFO(vm->dev)->gen) {
2072         case 8:
2073         case 7:
2074         case 6:
2075                 if (i915_is_ggtt(vm)) {
2076                         vma->unbind_vma = ggtt_unbind_vma;
2077                         vma->bind_vma = ggtt_bind_vma;
2078                 } else {
2079                         vma->unbind_vma = ppgtt_unbind_vma;
2080                         vma->bind_vma = ppgtt_bind_vma;
2081                 }
2082                 break;
2083         case 5:
2084         case 4:
2085         case 3:
2086         case 2:
2087                 BUG_ON(!i915_is_ggtt(vm));
2088                 vma->unbind_vma = i915_ggtt_unbind_vma;
2089                 vma->bind_vma = i915_ggtt_bind_vma;
2090                 break;
2091         default:
2092                 BUG();
2093         }
2094
2095         /* Keep GGTT vmas first to make debug easier */
2096         if (i915_is_ggtt(vm))
2097                 list_add(&vma->vma_link, &obj->vma_list);
2098         else
2099                 list_add_tail(&vma->vma_link, &obj->vma_list);
2100
2101         return vma;
2102 }
2103
2104 struct i915_vma *
2105 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2106                                   struct i915_address_space *vm)
2107 {
2108         struct i915_vma *vma;
2109
2110         vma = i915_gem_obj_to_vma(obj, vm);
2111         if (!vma)
2112                 vma = __i915_gem_vma_create(obj, vm);
2113
2114         return vma;
2115 }