drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/seq_file.h>
  26 #include <drm/drmP.h>
  27 #include <drm/i915_drm.h>
  28 #include "i915_drv.h"
  29 #include "i915_trace.h"
  30 #include "intel_drv.h"
  31
  32 #define GEN6_PPGTT_PD_ENTRIES 512
  33 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  34 typedef uint64_t gen8_gtt_pte_t;
  35 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  36
  37 /* PPGTT stuff */
  38 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  39 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  40
  41 #define GEN6_PDE_VALID                  (1 << 0)
  42 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  43 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  44
  45 #define GEN6_PTE_VALID                  (1 << 0)
  46 #define GEN6_PTE_UNCACHED               (1 << 1)
  47 #define HSW_PTE_UNCACHED                (0)
  48 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  49 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  50 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  51 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  52
  53 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  54  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  55  */
  56 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  57                                          (((bits) & 0x8) << (11 - 3)))
  58 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  59 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  60 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  61 #define HSW_WB_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x8)
  62 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  63 #define HSW_WT_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x7)
  64
  65 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  66 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  67 #define GEN8_LEGACY_PDPS                4
  68
  69 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  70 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  71 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  72 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  73
  74 static void ppgtt_bind_vma(struct i915_vma *vma,
  75                            enum i915_cache_level cache_level,
  76                            u32 flags);
  77 static void ppgtt_unbind_vma(struct i915_vma *vma);
  78 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
  79
  80 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  81                                              enum i915_cache_level level,
  82                                              bool valid)
  83 {
  84         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  85         pte |= addr;
  86         if (level != I915_CACHE_NONE)
  87                 pte |= PPAT_CACHED_INDEX;
  88         else
  89                 pte |= PPAT_UNCACHED_INDEX;
  90         return pte;
  91 }
  92
  93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
  94                                              dma_addr_t addr,
  95                                              enum i915_cache_level level)
  96 {
  97         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  98         pde |= addr;
  99         if (level != I915_CACHE_NONE)
 100                 pde |= PPAT_CACHED_PDE_INDEX;
 101         else
 102                 pde |= PPAT_UNCACHED_INDEX;
 103         return pde;
 104 }
 105
 106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 107                                      enum i915_cache_level level,
 108                                      bool valid)
 109 {
 110         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 111         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 112
 113         switch (level) {
 114         case I915_CACHE_L3_LLC:
 115         case I915_CACHE_LLC:
 116                 pte |= GEN6_PTE_CACHE_LLC;
 117                 break;
 118         case I915_CACHE_NONE:
 119                 pte |= GEN6_PTE_UNCACHED;
 120                 break;
 121         default:
 122                 WARN_ON(1);
 123         }
 124
 125         return pte;
 126 }
 127
 128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 129                                      enum i915_cache_level level,
 130                                      bool valid)
 131 {
 132         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 133         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 134
 135         switch (level) {
 136         case I915_CACHE_L3_LLC:
 137                 pte |= GEN7_PTE_CACHE_L3_LLC;
 138                 break;
 139         case I915_CACHE_LLC:
 140                 pte |= GEN6_PTE_CACHE_LLC;
 141                 break;
 142         case I915_CACHE_NONE:
 143                 pte |= GEN6_PTE_UNCACHED;
 144                 break;
 145         default:
 146                 WARN_ON(1);
 147         }
 148
 149         return pte;
 150 }
 151
 152 #define BYT_PTE_WRITEABLE               (1 << 1)
 153 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 154
 155 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 156                                      enum i915_cache_level level,
 157                                      bool valid)
 158 {
 159         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 160         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 161
 162         /* Mark the page as writeable.  Other platforms don't have a
 163          * setting for read-only/writable, so this matches that behavior.
 164          */
 165         pte |= BYT_PTE_WRITEABLE;
 166
 167         if (level != I915_CACHE_NONE)
 168                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 169
 170         return pte;
 171 }
 172
 173 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 174                                      enum i915_cache_level level,
 175                                      bool valid)
 176 {
 177         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 178         pte |= HSW_PTE_ADDR_ENCODE(addr);
 179
 180         if (level != I915_CACHE_NONE)
 181                 pte |= HSW_WB_LLC_AGE3;
 182
 183         return pte;
 184 }
 185
 186 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 187                                       enum i915_cache_level level,
 188                                       bool valid)
 189 {
 190         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 191         pte |= HSW_PTE_ADDR_ENCODE(addr);
 192
 193         switch (level) {
 194         case I915_CACHE_NONE:
 195                 break;
 196         case I915_CACHE_WT:
 197                 pte |= HSW_WT_ELLC_LLC_AGE3;
 198                 break;
 199         default:
 200                 pte |= HSW_WB_ELLC_LLC_AGE3;
 201                 break;
 202         }
 203
 204         return pte;
 205 }
 206
 207 /* Broadwell Page Directory Pointer Descriptors */
 208 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 209                            uint64_t val, bool synchronous)
 210 {
 211         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 212         int ret;
 213
 214         BUG_ON(entry >= 4);
 215
 216         if (synchronous) {
 217                 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
 218                 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 219                 return 0;
 220         }
 221
 222         ret = intel_ring_begin(ring, 6);
 223         if (ret)
 224                 return ret;
 225
 226         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 227         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 228         intel_ring_emit(ring, (u32)(val >> 32));
 229         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 230         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 231         intel_ring_emit(ring, (u32)(val));
 232         intel_ring_advance(ring);
 233
 234         return 0;
 235 }
 236
 237 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 238                           struct intel_ring_buffer *ring,
 239                           bool synchronous)
 240 {
 241         int i, ret;
 242
 243         /* bit of a hack to find the actual last used pd */
 244         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 245
 246         for (i = used_pd - 1; i >= 0; i--) {
 247                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 248                 ret = gen8_write_pdp(ring, i, addr, synchronous);
 249                 if (ret)
 250                         return ret;
 251         }
 252
 253         return 0;
 254 }
 255
 256 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 257                                    unsigned first_entry,
 258                                    unsigned num_entries,
 259                                    bool use_scratch)
 260 {
 261         struct i915_hw_ppgtt *ppgtt =
 262                 container_of(vm, struct i915_hw_ppgtt, base);
 263         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 264         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 265         unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
 266         unsigned last_pte, i;
 267
 268         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 269                                       I915_CACHE_LLC, use_scratch);
 270
 271         while (num_entries) {
 272                 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
 273
 274                 last_pte = first_pte + num_entries;
 275                 if (last_pte > GEN8_PTES_PER_PAGE)
 276                         last_pte = GEN8_PTES_PER_PAGE;
 277
 278                 pt_vaddr = kmap_atomic(page_table);
 279
 280                 for (i = first_pte; i < last_pte; i++)
 281                         pt_vaddr[i] = scratch_pte;
 282
 283                 kunmap_atomic(pt_vaddr);
 284
 285                 num_entries -= last_pte - first_pte;
 286                 first_pte = 0;
 287                 act_pt++;
 288         }
 289 }
 290
 291 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 292                                       struct sg_table *pages,
 293                                       unsigned first_entry,
 294                                       enum i915_cache_level cache_level)
 295 {
 296         struct i915_hw_ppgtt *ppgtt =
 297                 container_of(vm, struct i915_hw_ppgtt, base);
 298         gen8_gtt_pte_t *pt_vaddr;
 299         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 300         unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
 301         struct sg_page_iter sg_iter;
 302
 303         pt_vaddr = NULL;
 304         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 305                 if (pt_vaddr == NULL)
 306                         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 307
 308                 pt_vaddr[act_pte] =
 309                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 310                                         cache_level, true);
 311                 if (++act_pte == GEN8_PTES_PER_PAGE) {
 312                         kunmap_atomic(pt_vaddr);
 313                         pt_vaddr = NULL;
 314                         act_pt++;
 315                         act_pte = 0;
 316                 }
 317         }
 318         if (pt_vaddr)
 319                 kunmap_atomic(pt_vaddr);
 320 }
 321
 322 static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 323 {
 324         int i;
 325
 326         for (i = 0; i < ppgtt->num_pd_pages ; i++)
 327                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 328
 329         __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
 330         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 331 }
 332
 333 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 334 {
 335         struct pci_dev *hwdev = ppgtt->base.dev->pdev;
 336         int i, j;
 337
 338         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 339                 /* TODO: In the future we'll support sparse mappings, so this
 340                  * will have to change. */
 341                 if (!ppgtt->pd_dma_addr[i])
 342                         continue;
 343
 344                 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
 345                                PCI_DMA_BIDIRECTIONAL);
 346
 347                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 348                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 349                         if (addr)
 350                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
 351                                                PCI_DMA_BIDIRECTIONAL);
 352                 }
 353         }
 354 }
 355
 356 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 357 {
 358         struct i915_hw_ppgtt *ppgtt =
 359                 container_of(vm, struct i915_hw_ppgtt, base);
 360
 361         list_del(&vm->global_link);
 362         drm_mm_takedown(&vm->mm);
 363
 364         gen8_ppgtt_unmap_pages(ppgtt);
 365         gen8_ppgtt_free(ppgtt);
 366 }
 367
 368 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
 369                                            const int max_pdp)
 370 {
 371         struct page *pt_pages;
 372         const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 373
 374         pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
 375         if (!pt_pages)
 376                 return -ENOMEM;
 377
 378         ppgtt->gen8_pt_pages = pt_pages;
 379         ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 380
 381         return 0;
 382 }
 383
 384 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
 385 {
 386         int i;
 387
 388         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 389                 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
 390                                                      sizeof(dma_addr_t),
 391                                                      GFP_KERNEL);
 392                 if (!ppgtt->gen8_pt_dma_addr[i])
 393                         return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
 400                                                 const int max_pdp)
 401 {
 402         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 403         if (!ppgtt->pd_pages)
 404                 return -ENOMEM;
 405
 406         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 407         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 408
 409         return 0;
 410 }
 411
 412 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
 413                             const int max_pdp)
 414 {
 415         int ret;
 416
 417         ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
 418         if (ret)
 419                 return ret;
 420
 421         ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
 422         if (ret) {
 423                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 424                 return ret;
 425         }
 426
 427         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 428
 429         ret = gen8_ppgtt_allocate_dma(ppgtt);
 430         if (ret)
 431                 gen8_ppgtt_free(ppgtt);
 432
 433         return ret;
 434 }
 435
 436 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
 437                                              const int pd)
 438 {
 439         dma_addr_t pd_addr;
 440         int ret;
 441
 442         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
 443                                &ppgtt->pd_pages[pd], 0,
 444                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 445
 446         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
 447         if (ret)
 448                 return ret;
 449
 450         ppgtt->pd_dma_addr[pd] = pd_addr;
 451
 452         return 0;
 453 }
 454
 455 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
 456                                         const int pd,
 457                                         const int pt)
 458 {
 459         dma_addr_t pt_addr;
 460         struct page *p;
 461         int ret;
 462
 463         p = &ppgtt->gen8_pt_pages[pd * GEN8_PDES_PER_PAGE + pt];
 464         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
 465                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 466         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
 467         if (ret)
 468                 return ret;
 469
 470         ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
 471
 472         return 0;
 473 }
 474
 475 /**
 476  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 477  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 478  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 479  * space.
 480  *
 481  * FIXME: split allocation into smaller pieces. For now we only ever do this
 482  * once, but with full PPGTT, the multiple contiguous allocations will be bad.
 483  * TODO: Do something with the size parameter
 484  */
 485 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 486 {
 487         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 488         const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 489         int i, j, ret;
 490
 491         if (size % (1<<30))
 492                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 493
 494         /* 1. Do all our allocations for page directories and page tables. */
 495         ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
 496         if (ret)
 497                 return ret;
 498
 499         /*
 500          * 2. Create DMA mappings for the page directories and page tables.
 501          */
 502         for (i = 0; i < max_pdp; i++) {
 503                 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
 504                 if (ret)
 505                         goto bail;
 506
 507                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 508                         ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
 509                         if (ret)
 510                                 goto bail;
 511                 }
 512         }
 513
 514         /*
 515          * 3. Map all the page directory entires to point to the page tables
 516          * we've allocated.
 517          *
 518          * For now, the PPGTT helper functions all require that the PDEs are
 519          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 520          * will never need to touch the PDEs again.
 521          */
 522         for (i = 0; i < max_pdp; i++) {
 523                 gen8_ppgtt_pde_t *pd_vaddr;
 524                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 525                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 526                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 527                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 528                                                       I915_CACHE_LLC);
 529                 }
 530                 kunmap_atomic(pd_vaddr);
 531         }
 532
 533         ppgtt->enable = gen8_ppgtt_enable;
 534         ppgtt->switch_mm = gen8_mm_switch;
 535         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 536         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 537         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 538         ppgtt->base.start = 0;
 539         ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 540
 541         ppgtt->base.clear_range(&ppgtt->base, 0,
 542                                 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
 543                                 true);
 544
 545         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 546                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 547         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 548                          ppgtt->num_pt_pages,
 549                          (ppgtt->num_pt_pages - min_pt_pages) +
 550                          size % (1<<30));
 551         return 0;
 552
 553 bail:
 554         gen8_ppgtt_unmap_pages(ppgtt);
 555         gen8_ppgtt_free(ppgtt);
 556         return ret;
 557 }
 558
 559 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 560 {
 561         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 562         struct i915_address_space *vm = &ppgtt->base;
 563         gen6_gtt_pte_t __iomem *pd_addr;
 564         gen6_gtt_pte_t scratch_pte;
 565         uint32_t pd_entry;
 566         int pte, pde;
 567
 568         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 569
 570         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 571                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 572
 573         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
 574                    ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
 575         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
 576                 u32 expected;
 577                 gen6_gtt_pte_t *pt_vaddr;
 578                 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
 579                 pd_entry = readl(pd_addr + pde);
 580                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 581
 582                 if (pd_entry != expected)
 583                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 584                                    pde,
 585                                    pd_entry,
 586                                    expected);
 587                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 588
 589                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
 590                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
 591                         unsigned long va =
 592                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
 593                                 (pte * PAGE_SIZE);
 594                         int i;
 595                         bool found = false;
 596                         for (i = 0; i < 4; i++)
 597                                 if (pt_vaddr[pte + i] != scratch_pte)
 598                                         found = true;
 599                         if (!found)
 600                                 continue;
 601
 602                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 603                         for (i = 0; i < 4; i++) {
 604                                 if (pt_vaddr[pte + i] != scratch_pte)
 605                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
 606                                 else
 607                                         seq_puts(m, "  SCRATCH ");
 608                         }
 609                         seq_puts(m, "\n");
 610                 }
 611                 kunmap_atomic(pt_vaddr);
 612         }
 613 }
 614
 615 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 616 {
 617         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 618         gen6_gtt_pte_t __iomem *pd_addr;
 619         uint32_t pd_entry;
 620         int i;
 621
 622         WARN_ON(ppgtt->pd_offset & 0x3f);
 623         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 624                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 625         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 626                 dma_addr_t pt_addr;
 627
 628                 pt_addr = ppgtt->pt_dma_addr[i];
 629                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 630                 pd_entry |= GEN6_PDE_VALID;
 631
 632                 writel(pd_entry, pd_addr + i);
 633         }
 634         readl(pd_addr);
 635 }
 636
 637 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 638 {
 639         BUG_ON(ppgtt->pd_offset & 0x3f);
 640
 641         return (ppgtt->pd_offset / 64) << 16;
 642 }
 643
 644 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 645                          struct intel_ring_buffer *ring,
 646                          bool synchronous)
 647 {
 648         struct drm_device *dev = ppgtt->base.dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         int ret;
 651
 652         /* If we're in reset, we can assume the GPU is sufficiently idle to
 653          * manually frob these bits. Ideally we could use the ring functions,
 654          * except our error handling makes it quite difficult (can't use
 655          * intel_ring_begin, ring->flush, or intel_ring_advance)
 656          *
 657          * FIXME: We should try not to special case reset
 658          */
 659         if (synchronous ||
 660             i915_reset_in_progress(&dev_priv->gpu_error)) {
 661                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 662                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 663                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 664                 POSTING_READ(RING_PP_DIR_BASE(ring));
 665                 return 0;
 666         }
 667
 668         /* NB: TLBs must be flushed and invalidated before a switch */
 669         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 670         if (ret)
 671                 return ret;
 672
 673         ret = intel_ring_begin(ring, 6);
 674         if (ret)
 675                 return ret;
 676
 677         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 678         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 679         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 680         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 681         intel_ring_emit(ring, get_pd_offset(ppgtt));
 682         intel_ring_emit(ring, MI_NOOP);
 683         intel_ring_advance(ring);
 684
 685         return 0;
 686 }
 687
 688 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 689                           struct intel_ring_buffer *ring,
 690                           bool synchronous)
 691 {
 692         struct drm_device *dev = ppgtt->base.dev;
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         int ret;
 695
 696         /* If we're in reset, we can assume the GPU is sufficiently idle to
 697          * manually frob these bits. Ideally we could use the ring functions,
 698          * except our error handling makes it quite difficult (can't use
 699          * intel_ring_begin, ring->flush, or intel_ring_advance)
 700          *
 701          * FIXME: We should try not to special case reset
 702          */
 703         if (synchronous ||
 704             i915_reset_in_progress(&dev_priv->gpu_error)) {
 705                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 706                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 707                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 708                 POSTING_READ(RING_PP_DIR_BASE(ring));
 709                 return 0;
 710         }
 711
 712         /* NB: TLBs must be flushed and invalidated before a switch */
 713         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 714         if (ret)
 715                 return ret;
 716
 717         ret = intel_ring_begin(ring, 6);
 718         if (ret)
 719                 return ret;
 720
 721         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 722         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 723         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 724         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 725         intel_ring_emit(ring, get_pd_offset(ppgtt));
 726         intel_ring_emit(ring, MI_NOOP);
 727         intel_ring_advance(ring);
 728
 729         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 730         if (ring->id != RCS) {
 731                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 732                 if (ret)
 733                         return ret;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 740                           struct intel_ring_buffer *ring,
 741                           bool synchronous)
 742 {
 743         struct drm_device *dev = ppgtt->base.dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745
 746         if (!synchronous)
 747                 return 0;
 748
 749         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 750         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 751
 752         POSTING_READ(RING_PP_DIR_DCLV(ring));
 753
 754         return 0;
 755 }
 756
 757 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 758 {
 759         struct drm_device *dev = ppgtt->base.dev;
 760         struct drm_i915_private *dev_priv = dev->dev_private;
 761         struct intel_ring_buffer *ring;
 762         int j, ret;
 763
 764         for_each_ring(ring, dev_priv, j) {
 765                 I915_WRITE(RING_MODE_GEN7(ring),
 766                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 767
 768                 /* We promise to do a switch later with FULL PPGTT. If this is
 769                  * aliasing, this is the one and only switch we'll do */
 770                 if (USES_FULL_PPGTT(dev))
 771                         continue;
 772
 773                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 774                 if (ret)
 775                         goto err_out;
 776         }
 777
 778         return 0;
 779
 780 err_out:
 781         for_each_ring(ring, dev_priv, j)
 782                 I915_WRITE(RING_MODE_GEN7(ring),
 783                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 784         return ret;
 785 }
 786
 787 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 788 {
 789         struct drm_device *dev = ppgtt->base.dev;
 790         drm_i915_private_t *dev_priv = dev->dev_private;
 791         struct intel_ring_buffer *ring;
 792         uint32_t ecochk, ecobits;
 793         int i;
 794
 795         ecobits = I915_READ(GAC_ECO_BITS);
 796         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 797
 798         ecochk = I915_READ(GAM_ECOCHK);
 799         if (IS_HASWELL(dev)) {
 800                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 801         } else {
 802                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 803                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 804         }
 805         I915_WRITE(GAM_ECOCHK, ecochk);
 806
 807         for_each_ring(ring, dev_priv, i) {
 808                 int ret;
 809                 /* GFX_MODE is per-ring on gen7+ */
 810                 I915_WRITE(RING_MODE_GEN7(ring),
 811                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 812
 813                 /* We promise to do a switch later with FULL PPGTT. If this is
 814                  * aliasing, this is the one and only switch we'll do */
 815                 if (USES_FULL_PPGTT(dev))
 816                         continue;
 817
 818                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 819                 if (ret)
 820                         return ret;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 827 {
 828         struct drm_device *dev = ppgtt->base.dev;
 829         drm_i915_private_t *dev_priv = dev->dev_private;
 830         struct intel_ring_buffer *ring;
 831         uint32_t ecochk, gab_ctl, ecobits;
 832         int i;
 833
 834         ecobits = I915_READ(GAC_ECO_BITS);
 835         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 836                    ECOBITS_PPGTT_CACHE64B);
 837
 838         gab_ctl = I915_READ(GAB_CTL);
 839         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 840
 841         ecochk = I915_READ(GAM_ECOCHK);
 842         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 843
 844         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 845
 846         for_each_ring(ring, dev_priv, i) {
 847                 int ret = ppgtt->switch_mm(ppgtt, ring, true);
 848                 if (ret)
 849                         return ret;
 850         }
 851
 852         return 0;
 853 }
 854
 855 /* PPGTT support for Sandybdrige/Gen6 and later */
 856 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 857                                    unsigned first_entry,
 858                                    unsigned num_entries,
 859                                    bool use_scratch)
 860 {
 861         struct i915_hw_ppgtt *ppgtt =
 862                 container_of(vm, struct i915_hw_ppgtt, base);
 863         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 864         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 865         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 866         unsigned last_pte, i;
 867
 868         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 869
 870         while (num_entries) {
 871                 last_pte = first_pte + num_entries;
 872                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 873                         last_pte = I915_PPGTT_PT_ENTRIES;
 874
 875                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 876
 877                 for (i = first_pte; i < last_pte; i++)
 878                         pt_vaddr[i] = scratch_pte;
 879
 880                 kunmap_atomic(pt_vaddr);
 881
 882                 num_entries -= last_pte - first_pte;
 883                 first_pte = 0;
 884                 act_pt++;
 885         }
 886 }
 887
 888 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 889                                       struct sg_table *pages,
 890                                       unsigned first_entry,
 891                                       enum i915_cache_level cache_level)
 892 {
 893         struct i915_hw_ppgtt *ppgtt =
 894                 container_of(vm, struct i915_hw_ppgtt, base);
 895         gen6_gtt_pte_t *pt_vaddr;
 896         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 897         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 898         struct sg_page_iter sg_iter;
 899
 900         pt_vaddr = NULL;
 901         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 902                 if (pt_vaddr == NULL)
 903                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 904
 905                 pt_vaddr[act_pte] =
 906                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
 907                                        cache_level, true);
 908                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 909                         kunmap_atomic(pt_vaddr);
 910                         pt_vaddr = NULL;
 911                         act_pt++;
 912                         act_pte = 0;
 913                 }
 914         }
 915         if (pt_vaddr)
 916                 kunmap_atomic(pt_vaddr);
 917 }
 918
 919 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 920 {
 921         struct i915_hw_ppgtt *ppgtt =
 922                 container_of(vm, struct i915_hw_ppgtt, base);
 923         int i;
 924
 925         list_del(&vm->global_link);
 926         drm_mm_takedown(&ppgtt->base.mm);
 927         drm_mm_remove_node(&ppgtt->node);
 928
 929         if (ppgtt->pt_dma_addr) {
 930                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 931                         pci_unmap_page(ppgtt->base.dev->pdev,
 932                                        ppgtt->pt_dma_addr[i],
 933                                        4096, PCI_DMA_BIDIRECTIONAL);
 934         }
 935
 936         kfree(ppgtt->pt_dma_addr);
 937         for (i = 0; i < ppgtt->num_pd_entries; i++)
 938                 __free_page(ppgtt->pt_pages[i]);
 939         kfree(ppgtt->pt_pages);
 940 }
 941
 942 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 943 {
 944 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
 945 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
 946         struct drm_device *dev = ppgtt->base.dev;
 947         struct drm_i915_private *dev_priv = dev->dev_private;
 948         bool retried = false;
 949         int i, ret;
 950
 951         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 952          * allocator works in address space sizes, so it's multiplied by page
 953          * size. We allocate at the top of the GTT to avoid fragmentation.
 954          */
 955         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
 956 alloc:
 957         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 958                                                   &ppgtt->node, GEN6_PD_SIZE,
 959                                                   GEN6_PD_ALIGN, 0,
 960                                                   0, dev_priv->gtt.base.total,
 961                                                   DRM_MM_SEARCH_DEFAULT);
 962         if (ret == -ENOSPC && !retried) {
 963                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
 964                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
 965                                                I915_CACHE_NONE, 0);
 966                 if (ret)
 967                         return ret;
 968
 969                 retried = true;
 970                 goto alloc;
 971         }
 972
 973         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
 974                 DRM_DEBUG("Forced to use aperture for PDEs\n");
 975
 976         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 977         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 978         if (IS_GEN6(dev)) {
 979                 ppgtt->enable = gen6_ppgtt_enable;
 980                 ppgtt->switch_mm = gen6_mm_switch;
 981         } else if (IS_HASWELL(dev)) {
 982                 ppgtt->enable = gen7_ppgtt_enable;
 983                 ppgtt->switch_mm = hsw_mm_switch;
 984         } else if (IS_GEN7(dev)) {
 985                 ppgtt->enable = gen7_ppgtt_enable;
 986                 ppgtt->switch_mm = gen7_mm_switch;
 987         } else
 988                 BUG();
 989         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 990         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 991         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 992         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 993         ppgtt->base.start = 0;
 994         ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
 995         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 996                                   GFP_KERNEL);
 997         if (!ppgtt->pt_pages) {
 998                 drm_mm_remove_node(&ppgtt->node);
 999                 return -ENOMEM;
1000         }
1001
1002         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1003                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1004                 if (!ppgtt->pt_pages[i])
1005                         goto err_pt_alloc;
1006         }
1007
1008         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1009                                      GFP_KERNEL);
1010         if (!ppgtt->pt_dma_addr)
1011                 goto err_pt_alloc;
1012
1013         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1014                 dma_addr_t pt_addr;
1015
1016                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1017                                        PCI_DMA_BIDIRECTIONAL);
1018
1019                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1020                         ret = -EIO;
1021                         goto err_pd_pin;
1022
1023                 }
1024                 ppgtt->pt_dma_addr[i] = pt_addr;
1025         }
1026
1027         ppgtt->base.clear_range(&ppgtt->base, 0,
1028                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
1029         ppgtt->debug_dump = gen6_dump_ppgtt;
1030
1031         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1032                          ppgtt->node.size >> 20,
1033                          ppgtt->node.start / PAGE_SIZE);
1034         ppgtt->pd_offset =
1035                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1036
1037         return 0;
1038
1039 err_pd_pin:
1040         if (ppgtt->pt_dma_addr) {
1041                 for (i--; i >= 0; i--)
1042                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
1043                                        4096, PCI_DMA_BIDIRECTIONAL);
1044         }
1045 err_pt_alloc:
1046         kfree(ppgtt->pt_dma_addr);
1047         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1048                 if (ppgtt->pt_pages[i])
1049                         __free_page(ppgtt->pt_pages[i]);
1050         }
1051         kfree(ppgtt->pt_pages);
1052         drm_mm_remove_node(&ppgtt->node);
1053
1054         return ret;
1055 }
1056
1057 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1058 {
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060         int ret = 0;
1061
1062         ppgtt->base.dev = dev;
1063
1064         if (INTEL_INFO(dev)->gen < 8)
1065                 ret = gen6_ppgtt_init(ppgtt);
1066         else if (IS_GEN8(dev))
1067                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1068         else
1069                 BUG();
1070
1071         if (!ret) {
1072                 struct drm_i915_private *dev_priv = dev->dev_private;
1073                 kref_init(&ppgtt->ref);
1074                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1075                             ppgtt->base.total);
1076                 i915_init_vm(dev_priv, &ppgtt->base);
1077                 if (INTEL_INFO(dev)->gen < 8) {
1078                         gen6_write_pdes(ppgtt);
1079                         DRM_DEBUG("Adding PPGTT at offset %x\n",
1080                                   ppgtt->pd_offset << 10);
1081                 }
1082         }
1083
1084         return ret;
1085 }
1086
1087 static void
1088 ppgtt_bind_vma(struct i915_vma *vma,
1089                enum i915_cache_level cache_level,
1090                u32 flags)
1091 {
1092         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1093
1094         WARN_ON(flags);
1095
1096         vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
1097 }
1098
1099 static void ppgtt_unbind_vma(struct i915_vma *vma)
1100 {
1101         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1102
1103         vma->vm->clear_range(vma->vm,
1104                              entry,
1105                              vma->obj->base.size >> PAGE_SHIFT,
1106                              true);
1107 }
1108
1109 extern int intel_iommu_gfx_mapped;
1110 /* Certain Gen5 chipsets require require idling the GPU before
1111  * unmapping anything from the GTT when VT-d is enabled.
1112  */
1113 static inline bool needs_idle_maps(struct drm_device *dev)
1114 {
1115 #ifdef CONFIG_INTEL_IOMMU
1116         /* Query intel_iommu to see if we need the workaround. Presumably that
1117          * was loaded first.
1118          */
1119         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1120                 return true;
1121 #endif
1122         return false;
1123 }
1124
1125 static bool do_idling(struct drm_i915_private *dev_priv)
1126 {
1127         bool ret = dev_priv->mm.interruptible;
1128
1129         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1130                 dev_priv->mm.interruptible = false;
1131                 if (i915_gpu_idle(dev_priv->dev)) {
1132                         DRM_ERROR("Couldn't idle GPU\n");
1133                         /* Wait a bit, in hopes it avoids the hang */
1134                         udelay(10);
1135                 }
1136         }
1137
1138         return ret;
1139 }
1140
1141 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1142 {
1143         if (unlikely(dev_priv->gtt.do_idle_maps))
1144                 dev_priv->mm.interruptible = interruptible;
1145 }
1146
1147 void i915_check_and_clear_faults(struct drm_device *dev)
1148 {
1149         struct drm_i915_private *dev_priv = dev->dev_private;
1150         struct intel_ring_buffer *ring;
1151         int i;
1152
1153         if (INTEL_INFO(dev)->gen < 6)
1154                 return;
1155
1156         for_each_ring(ring, dev_priv, i) {
1157                 u32 fault_reg;
1158                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1159                 if (fault_reg & RING_FAULT_VALID) {
1160                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1161                                          "\tAddr: 0x%08lx\\n"
1162                                          "\tAddress space: %s\n"
1163                                          "\tSource ID: %d\n"
1164                                          "\tType: %d\n",
1165                                          fault_reg & PAGE_MASK,
1166                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1167                                          RING_FAULT_SRCID(fault_reg),
1168                                          RING_FAULT_FAULT_TYPE(fault_reg));
1169                         I915_WRITE(RING_FAULT_REG(ring),
1170                                    fault_reg & ~RING_FAULT_VALID);
1171                 }
1172         }
1173         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1174 }
1175
1176 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1177 {
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180         /* Don't bother messing with faults pre GEN6 as we have little
1181          * documentation supporting that it's a good idea.
1182          */
1183         if (INTEL_INFO(dev)->gen < 6)
1184                 return;
1185
1186         i915_check_and_clear_faults(dev);
1187
1188         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1189                                        dev_priv->gtt.base.start / PAGE_SIZE,
1190                                        dev_priv->gtt.base.total / PAGE_SIZE,
1191                                        false);
1192 }
1193
1194 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         struct drm_i915_gem_object *obj;
1198         struct i915_address_space *vm;
1199
1200         i915_check_and_clear_faults(dev);
1201
1202         /* First fill our portion of the GTT with scratch pages */
1203         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1204                                        dev_priv->gtt.base.start / PAGE_SIZE,
1205                                        dev_priv->gtt.base.total / PAGE_SIZE,
1206                                        true);
1207
1208         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1209                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1210                                                            &dev_priv->gtt.base);
1211                 if (!vma)
1212                         continue;
1213
1214                 i915_gem_clflush_object(obj, obj->pin_display);
1215                 /* The bind_vma code tries to be smart about tracking mappings.
1216                  * Unfortunately above, we've just wiped out the mappings
1217                  * without telling our object about it. So we need to fake it.
1218                  */
1219                 obj->has_global_gtt_mapping = 0;
1220                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1221         }
1222
1223
1224         if (INTEL_INFO(dev)->gen >= 8)
1225                 return;
1226
1227         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1228                 /* TODO: Perhaps it shouldn't be gen6 specific */
1229                 if (i915_is_ggtt(vm)) {
1230                         if (dev_priv->mm.aliasing_ppgtt)
1231                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1232                         continue;
1233                 }
1234
1235                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1236         }
1237
1238         i915_gem_chipset_flush(dev);
1239 }
1240
1241 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1242 {
1243         if (obj->has_dma_mapping)
1244                 return 0;
1245
1246         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1247                         obj->pages->sgl, obj->pages->nents,
1248                         PCI_DMA_BIDIRECTIONAL))
1249                 return -ENOSPC;
1250
1251         return 0;
1252 }
1253
1254 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1255 {
1256 #ifdef writeq
1257         writeq(pte, addr);
1258 #else
1259         iowrite32((u32)pte, addr);
1260         iowrite32(pte >> 32, addr + 4);
1261 #endif
1262 }
1263
1264 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1265                                      struct sg_table *st,
1266                                      unsigned int first_entry,
1267                                      enum i915_cache_level level)
1268 {
1269         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1270         gen8_gtt_pte_t __iomem *gtt_entries =
1271                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1272         int i = 0;
1273         struct sg_page_iter sg_iter;
1274         dma_addr_t addr;
1275
1276         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1277                 addr = sg_dma_address(sg_iter.sg) +
1278                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1279                 gen8_set_pte(&gtt_entries[i],
1280                              gen8_pte_encode(addr, level, true));
1281                 i++;
1282         }
1283
1284         /*
1285          * XXX: This serves as a posting read to make sure that the PTE has
1286          * actually been updated. There is some concern that even though
1287          * registers and PTEs are within the same BAR that they are potentially
1288          * of NUMA access patterns. Therefore, even with the way we assume
1289          * hardware should work, we must keep this posting read for paranoia.
1290          */
1291         if (i != 0)
1292                 WARN_ON(readq(&gtt_entries[i-1])
1293                         != gen8_pte_encode(addr, level, true));
1294
1295         /* This next bit makes the above posting read even more important. We
1296          * want to flush the TLBs only after we're certain all the PTE updates
1297          * have finished.
1298          */
1299         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1300         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1301 }
1302
1303 /*
1304  * Binds an object into the global gtt with the specified cache level. The object
1305  * will be accessible to the GPU via commands whose operands reference offsets
1306  * within the global GTT as well as accessible by the GPU through the GMADR
1307  * mapped BAR (dev_priv->mm.gtt->gtt).
1308  */
1309 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1310                                      struct sg_table *st,
1311                                      unsigned int first_entry,
1312                                      enum i915_cache_level level)
1313 {
1314         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1315         gen6_gtt_pte_t __iomem *gtt_entries =
1316                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1317         int i = 0;
1318         struct sg_page_iter sg_iter;
1319         dma_addr_t addr;
1320
1321         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1322                 addr = sg_page_iter_dma_address(&sg_iter);
1323                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1324                 i++;
1325         }
1326
1327         /* XXX: This serves as a posting read to make sure that the PTE has
1328          * actually been updated. There is some concern that even though
1329          * registers and PTEs are within the same BAR that they are potentially
1330          * of NUMA access patterns. Therefore, even with the way we assume
1331          * hardware should work, we must keep this posting read for paranoia.
1332          */
1333         if (i != 0)
1334                 WARN_ON(readl(&gtt_entries[i-1]) !=
1335                         vm->pte_encode(addr, level, true));
1336
1337         /* This next bit makes the above posting read even more important. We
1338          * want to flush the TLBs only after we're certain all the PTE updates
1339          * have finished.
1340          */
1341         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1342         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1343 }
1344
1345 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1346                                   unsigned int first_entry,
1347                                   unsigned int num_entries,
1348                                   bool use_scratch)
1349 {
1350         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1351         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1352                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1353         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1354         int i;
1355
1356         if (WARN(num_entries > max_entries,
1357                  "First entry = %d; Num entries = %d (max=%d)\n",
1358                  first_entry, num_entries, max_entries))
1359                 num_entries = max_entries;
1360
1361         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1362                                       I915_CACHE_LLC,
1363                                       use_scratch);
1364         for (i = 0; i < num_entries; i++)
1365                 gen8_set_pte(&gtt_base[i], scratch_pte);
1366         readl(gtt_base);
1367 }
1368
1369 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1370                                   unsigned int first_entry,
1371                                   unsigned int num_entries,
1372                                   bool use_scratch)
1373 {
1374         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1375         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1376                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1377         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1378         int i;
1379
1380         if (WARN(num_entries > max_entries,
1381                  "First entry = %d; Num entries = %d (max=%d)\n",
1382                  first_entry, num_entries, max_entries))
1383                 num_entries = max_entries;
1384
1385         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1386
1387         for (i = 0; i < num_entries; i++)
1388                 iowrite32(scratch_pte, &gtt_base[i]);
1389         readl(gtt_base);
1390 }
1391
1392
1393 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1394                                enum i915_cache_level cache_level,
1395                                u32 unused)
1396 {
1397         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1398         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1399                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1400
1401         BUG_ON(!i915_is_ggtt(vma->vm));
1402         intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1403         vma->obj->has_global_gtt_mapping = 1;
1404 }
1405
1406 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1407                                   unsigned int first_entry,
1408                                   unsigned int num_entries,
1409                                   bool unused)
1410 {
1411         intel_gtt_clear_range(first_entry, num_entries);
1412 }
1413
1414 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1415 {
1416         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1417         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1418
1419         BUG_ON(!i915_is_ggtt(vma->vm));
1420         vma->obj->has_global_gtt_mapping = 0;
1421         intel_gtt_clear_range(first, size);
1422 }
1423
1424 static void ggtt_bind_vma(struct i915_vma *vma,
1425                           enum i915_cache_level cache_level,
1426                           u32 flags)
1427 {
1428         struct drm_device *dev = vma->vm->dev;
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         struct drm_i915_gem_object *obj = vma->obj;
1431         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1432
1433         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1434          * or we have a global mapping already but the cacheability flags have
1435          * changed, set the global PTEs.
1436          *
1437          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1438          * instead if none of the above hold true.
1439          *
1440          * NB: A global mapping should only be needed for special regions like
1441          * "gtt mappable", SNB errata, or if specified via special execbuf
1442          * flags. At all other times, the GPU will use the aliasing PPGTT.
1443          */
1444         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1445                 if (!obj->has_global_gtt_mapping ||
1446                     (cache_level != obj->cache_level)) {
1447                         vma->vm->insert_entries(vma->vm, obj->pages, entry,
1448                                                 cache_level);
1449                         obj->has_global_gtt_mapping = 1;
1450                 }
1451         }
1452
1453         if (dev_priv->mm.aliasing_ppgtt &&
1454             (!obj->has_aliasing_ppgtt_mapping ||
1455              (cache_level != obj->cache_level))) {
1456                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1457                 appgtt->base.insert_entries(&appgtt->base,
1458                                             vma->obj->pages, entry, cache_level);
1459                 vma->obj->has_aliasing_ppgtt_mapping = 1;
1460         }
1461 }
1462
1463 static void ggtt_unbind_vma(struct i915_vma *vma)
1464 {
1465         struct drm_device *dev = vma->vm->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         struct drm_i915_gem_object *obj = vma->obj;
1468         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1469
1470         if (obj->has_global_gtt_mapping) {
1471                 vma->vm->clear_range(vma->vm, entry,
1472                                      vma->obj->base.size >> PAGE_SHIFT,
1473                                      true);
1474                 obj->has_global_gtt_mapping = 0;
1475         }
1476
1477         if (obj->has_aliasing_ppgtt_mapping) {
1478                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1479                 appgtt->base.clear_range(&appgtt->base,
1480                                          entry,
1481                                          obj->base.size >> PAGE_SHIFT,
1482                                          true);
1483                 obj->has_aliasing_ppgtt_mapping = 0;
1484         }
1485 }
1486
1487 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1488 {
1489         struct drm_device *dev = obj->base.dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         bool interruptible;
1492
1493         interruptible = do_idling(dev_priv);
1494
1495         if (!obj->has_dma_mapping)
1496                 dma_unmap_sg(&dev->pdev->dev,
1497                              obj->pages->sgl, obj->pages->nents,
1498                              PCI_DMA_BIDIRECTIONAL);
1499
1500         undo_idling(dev_priv, interruptible);
1501 }
1502
1503 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1504                                   unsigned long color,
1505                                   unsigned long *start,
1506                                   unsigned long *end)
1507 {
1508         if (node->color != color)
1509                 *start += 4096;
1510
1511         if (!list_empty(&node->node_list)) {
1512                 node = list_entry(node->node_list.next,
1513                                   struct drm_mm_node,
1514                                   node_list);
1515                 if (node->allocated && node->color != color)
1516                         *end -= 4096;
1517         }
1518 }
1519
1520 void i915_gem_setup_global_gtt(struct drm_device *dev,
1521                                unsigned long start,
1522                                unsigned long mappable_end,
1523                                unsigned long end)
1524 {
1525         /* Let GEM Manage all of the aperture.
1526          *
1527          * However, leave one page at the end still bound to the scratch page.
1528          * There are a number of places where the hardware apparently prefetches
1529          * past the end of the object, and we've seen multiple hangs with the
1530          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1531          * aperture.  One page should be enough to keep any prefetching inside
1532          * of the aperture.
1533          */
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1536         struct drm_mm_node *entry;
1537         struct drm_i915_gem_object *obj;
1538         unsigned long hole_start, hole_end;
1539
1540         BUG_ON(mappable_end > end);
1541
1542         /* Subtract the guard page ... */
1543         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1544         if (!HAS_LLC(dev))
1545                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1546
1547         /* Mark any preallocated objects as occupied */
1548         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1549                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1550                 int ret;
1551                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1552                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1553
1554                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1555                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1556                 if (ret)
1557                         DRM_DEBUG_KMS("Reservation failed\n");
1558                 obj->has_global_gtt_mapping = 1;
1559         }
1560
1561         dev_priv->gtt.base.start = start;
1562         dev_priv->gtt.base.total = end - start;
1563
1564         /* Clear any non-preallocated blocks */
1565         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1566                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1567                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1568                               hole_start, hole_end);
1569                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1570         }
1571
1572         /* And finally clear the reserved guard page */
1573         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1574 }
1575
1576 void i915_gem_init_global_gtt(struct drm_device *dev)
1577 {
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         unsigned long gtt_size, mappable_size;
1580
1581         gtt_size = dev_priv->gtt.base.total;
1582         mappable_size = dev_priv->gtt.mappable_end;
1583
1584         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1585 }
1586
1587 static int setup_scratch_page(struct drm_device *dev)
1588 {
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         struct page *page;
1591         dma_addr_t dma_addr;
1592
1593         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1594         if (page == NULL)
1595                 return -ENOMEM;
1596         get_page(page);
1597         set_pages_uc(page, 1);
1598
1599 #ifdef CONFIG_INTEL_IOMMU
1600         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1601                                 PCI_DMA_BIDIRECTIONAL);
1602         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1603                 return -EINVAL;
1604 #else
1605         dma_addr = page_to_phys(page);
1606 #endif
1607         dev_priv->gtt.base.scratch.page = page;
1608         dev_priv->gtt.base.scratch.addr = dma_addr;
1609
1610         return 0;
1611 }
1612
1613 static void teardown_scratch_page(struct drm_device *dev)
1614 {
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         struct page *page = dev_priv->gtt.base.scratch.page;
1617
1618         set_pages_wb(page, 1);
1619         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1620                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1621         put_page(page);
1622         __free_page(page);
1623 }
1624
1625 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1626 {
1627         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1628         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1629         return snb_gmch_ctl << 20;
1630 }
1631
1632 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1633 {
1634         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1635         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1636         if (bdw_gmch_ctl)
1637                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1638         if (bdw_gmch_ctl > 4) {
1639                 WARN_ON(!i915.preliminary_hw_support);
1640                 return 4<<20;
1641         }
1642
1643         return bdw_gmch_ctl << 20;
1644 }
1645
1646 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1647 {
1648         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1649         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1650         return snb_gmch_ctl << 25; /* 32 MB units */
1651 }
1652
1653 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1654 {
1655         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1656         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1657         return bdw_gmch_ctl << 25; /* 32 MB units */
1658 }
1659
1660 static int ggtt_probe_common(struct drm_device *dev,
1661                              size_t gtt_size)
1662 {
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664         phys_addr_t gtt_bus_addr;
1665         int ret;
1666
1667         /* For Modern GENs the PTEs and register space are split in the BAR */
1668         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1669                 (pci_resource_len(dev->pdev, 0) / 2);
1670
1671         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1672         if (!dev_priv->gtt.gsm) {
1673                 DRM_ERROR("Failed to map the gtt page table\n");
1674                 return -ENOMEM;
1675         }
1676
1677         ret = setup_scratch_page(dev);
1678         if (ret) {
1679                 DRM_ERROR("Scratch setup failed\n");
1680                 /* iounmap will also get called at remove, but meh */
1681                 iounmap(dev_priv->gtt.gsm);
1682         }
1683
1684         return ret;
1685 }
1686
1687 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1688  * bits. When using advanced contexts each context stores its own PAT, but
1689  * writing this data shouldn't be harmful even in those cases. */
1690 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1691 {
1692 #define GEN8_PPAT_UC            (0<<0)
1693 #define GEN8_PPAT_WC            (1<<0)
1694 #define GEN8_PPAT_WT            (2<<0)
1695 #define GEN8_PPAT_WB            (3<<0)
1696 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1697 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1698 #define GEN8_PPAT_LLC           (1<<2)
1699 #define GEN8_PPAT_LLCELLC       (2<<2)
1700 #define GEN8_PPAT_LLCeLLC       (3<<2)
1701 #define GEN8_PPAT_AGE(x)        (x<<4)
1702 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1703         uint64_t pat;
1704
1705         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1706               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1707               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1708               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1709               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1710               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1711               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1712               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1713
1714         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1715          * write would work. */
1716         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1717         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1718 }
1719
1720 static int gen8_gmch_probe(struct drm_device *dev,
1721                            size_t *gtt_total,
1722                            size_t *stolen,
1723                            phys_addr_t *mappable_base,
1724                            unsigned long *mappable_end)
1725 {
1726         struct drm_i915_private *dev_priv = dev->dev_private;
1727         unsigned int gtt_size;
1728         u16 snb_gmch_ctl;
1729         int ret;
1730
1731         /* TODO: We're not aware of mappable constraints on gen8 yet */
1732         *mappable_base = pci_resource_start(dev->pdev, 2);
1733         *mappable_end = pci_resource_len(dev->pdev, 2);
1734
1735         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1736                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1737
1738         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1739
1740         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1741
1742         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1743         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1744
1745         gen8_setup_private_ppat(dev_priv);
1746
1747         ret = ggtt_probe_common(dev, gtt_size);
1748
1749         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1750         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1751
1752         return ret;
1753 }
1754
1755 static int gen6_gmch_probe(struct drm_device *dev,
1756                            size_t *gtt_total,
1757                            size_t *stolen,
1758                            phys_addr_t *mappable_base,
1759                            unsigned long *mappable_end)
1760 {
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762         unsigned int gtt_size;
1763         u16 snb_gmch_ctl;
1764         int ret;
1765
1766         *mappable_base = pci_resource_start(dev->pdev, 2);
1767         *mappable_end = pci_resource_len(dev->pdev, 2);
1768
1769         /* 64/512MB is the current min/max we actually know of, but this is just
1770          * a coarse sanity check.
1771          */
1772         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1773                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1774                           dev_priv->gtt.mappable_end);
1775                 return -ENXIO;
1776         }
1777
1778         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1779                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1780         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1781
1782         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1783
1784         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1785         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1786
1787         ret = ggtt_probe_common(dev, gtt_size);
1788
1789         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1790         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1791
1792         return ret;
1793 }
1794
1795 static void gen6_gmch_remove(struct i915_address_space *vm)
1796 {
1797
1798         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1799
1800         drm_mm_takedown(&vm->mm);
1801         iounmap(gtt->gsm);
1802         teardown_scratch_page(vm->dev);
1803 }
1804
1805 static int i915_gmch_probe(struct drm_device *dev,
1806                            size_t *gtt_total,
1807                            size_t *stolen,
1808                            phys_addr_t *mappable_base,
1809                            unsigned long *mappable_end)
1810 {
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         int ret;
1813
1814         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1815         if (!ret) {
1816                 DRM_ERROR("failed to set up gmch\n");
1817                 return -EIO;
1818         }
1819
1820         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1821
1822         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1823         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1824
1825         if (unlikely(dev_priv->gtt.do_idle_maps))
1826                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1827
1828         return 0;
1829 }
1830
1831 static void i915_gmch_remove(struct i915_address_space *vm)
1832 {
1833         intel_gmch_remove();
1834 }
1835
1836 int i915_gem_gtt_init(struct drm_device *dev)
1837 {
1838         struct drm_i915_private *dev_priv = dev->dev_private;
1839         struct i915_gtt *gtt = &dev_priv->gtt;
1840         int ret;
1841
1842         if (INTEL_INFO(dev)->gen <= 5) {
1843                 gtt->gtt_probe = i915_gmch_probe;
1844                 gtt->base.cleanup = i915_gmch_remove;
1845         } else if (INTEL_INFO(dev)->gen < 8) {
1846                 gtt->gtt_probe = gen6_gmch_probe;
1847                 gtt->base.cleanup = gen6_gmch_remove;
1848                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1849                         gtt->base.pte_encode = iris_pte_encode;
1850                 else if (IS_HASWELL(dev))
1851                         gtt->base.pte_encode = hsw_pte_encode;
1852                 else if (IS_VALLEYVIEW(dev))
1853                         gtt->base.pte_encode = byt_pte_encode;
1854                 else if (INTEL_INFO(dev)->gen >= 7)
1855                         gtt->base.pte_encode = ivb_pte_encode;
1856                 else
1857                         gtt->base.pte_encode = snb_pte_encode;
1858         } else {
1859                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1860                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1861         }
1862
1863         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1864                              &gtt->mappable_base, &gtt->mappable_end);
1865         if (ret)
1866                 return ret;
1867
1868         gtt->base.dev = dev;
1869
1870         /* GMADR is the PCI mmio aperture into the global GTT. */
1871         DRM_INFO("Memory usable by graphics device = %zdM\n",
1872                  gtt->base.total >> 20);
1873         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1874         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1875
1876         return 0;
1877 }
1878
1879 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1880                                               struct i915_address_space *vm)
1881 {
1882         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1883         if (vma == NULL)
1884                 return ERR_PTR(-ENOMEM);
1885
1886         INIT_LIST_HEAD(&vma->vma_link);
1887         INIT_LIST_HEAD(&vma->mm_list);
1888         INIT_LIST_HEAD(&vma->exec_list);
1889         vma->vm = vm;
1890         vma->obj = obj;
1891
1892         switch (INTEL_INFO(vm->dev)->gen) {
1893         case 8:
1894         case 7:
1895         case 6:
1896                 if (i915_is_ggtt(vm)) {
1897                         vma->unbind_vma = ggtt_unbind_vma;
1898                         vma->bind_vma = ggtt_bind_vma;
1899                 } else {
1900                         vma->unbind_vma = ppgtt_unbind_vma;
1901                         vma->bind_vma = ppgtt_bind_vma;
1902                 }
1903                 break;
1904         case 5:
1905         case 4:
1906         case 3:
1907         case 2:
1908                 BUG_ON(!i915_is_ggtt(vm));
1909                 vma->unbind_vma = i915_ggtt_unbind_vma;
1910                 vma->bind_vma = i915_ggtt_bind_vma;
1911                 break;
1912         default:
1913                 BUG();
1914         }
1915
1916         /* Keep GGTT vmas first to make debug easier */
1917         if (i915_is_ggtt(vm))
1918                 list_add(&vma->vma_link, &obj->vma_list);
1919         else
1920                 list_add_tail(&vma->vma_link, &obj->vma_list);
1921
1922         return vma;
1923 }
1924
1925 struct i915_vma *
1926 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1927                                   struct i915_address_space *vm)
1928 {
1929         struct i915_vma *vma;
1930
1931         vma = i915_gem_obj_to_vma(obj, vm);
1932         if (!vma)
1933                 vma = __i915_gem_vma_create(obj, vm);
1934
1935         return vma;
1936 }