drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/stop_machine.h>
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_vgpu.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: Global GTT views
  37  *
  38  * Background and previous state
  39  *
  40  * Historically objects could exists (be bound) in global GTT space only as
  41  * singular instances with a view representing all of the object's backing pages
  42  * in a linear fashion. This view will be called a normal view.
  43  *
  44  * To support multiple views of the same object, where the number of mapped
  45  * pages is not equal to the backing store, or where the layout of the pages
  46  * is not linear, concept of a GGTT view was added.
  47  *
  48  * One example of an alternative view is a stereo display driven by a single
  49  * image. In this case we would have a framebuffer looking like this
  50  * (2x2 pages):
  51  *
  52  *    12
  53  *    34
  54  *
  55  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  56  * rendering. In contrast, fed to the display engine would be an alternative
  57  * view which could look something like this:
  58  *
  59  *   1212
  60  *   3434
  61  *
  62  * In this example both the size and layout of pages in the alternative view is
  63  * different from the normal view.
  64  *
  65  * Implementation and usage
  66  *
  67  * GGTT views are implemented using VMAs and are distinguished via enum
  68  * i915_ggtt_view_type and struct i915_ggtt_view.
  69  *
  70  * A new flavour of core GEM functions which work with GGTT bound objects were
  71  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  72  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  73  * parameter encapsulating all metadata required to implement a view.
  74  *
  75  * As a helper for callers which are only interested in the normal view,
  76  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  77  * GEM API functions, the ones not taking the view parameter, are operating on,
  78  * or with the normal GGTT view.
  79  *
  80  * Code wanting to add or use a new GGTT view needs to:
  81  *
  82  * 1. Add a new enum with a suitable name.
  83  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  84  * 3. Add support to i915_get_vma_pages().
  85  *
  86  * New views are required to build a scatter-gather table from within the
  87  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  88  * exists for the lifetime of an VMA.
  89  *
  90  * Core API is designed to have copy semantics which means that passed in
  91  * struct i915_ggtt_view does not need to be persistent (left around after
  92  * calling the core API functions).
  93  *
  94  */
  95
  96 static int
  97 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  98
  99 const struct i915_ggtt_view i915_ggtt_view_normal;
 100 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 101         .type = I915_GGTT_VIEW_ROTATED
 102 };
 103
 104 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 105 {
 106         bool has_aliasing_ppgtt;
 107         bool has_full_ppgtt;
 108         bool has_full_48bit_ppgtt;
 109
 110         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 111         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 112         has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
 113
 114         if (intel_vgpu_active(dev))
 115                 has_full_ppgtt = false; /* emulation is too hard */
 116
 117         /*
 118          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 119          * execlists, the sole mechanism available to submit work.
 120          */
 121         if (INTEL_INFO(dev)->gen < 9 &&
 122             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 123                 return 0;
 124
 125         if (enable_ppgtt == 1)
 126                 return 1;
 127
 128         if (enable_ppgtt == 2 && has_full_ppgtt)
 129                 return 2;
 130
 131         if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
 132                 return 3;
 133
 134 #ifdef CONFIG_INTEL_IOMMU
 135         /* Disable ppgtt on SNB if VT-d is on. */
 136         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 137                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 138                 return 0;
 139         }
 140 #endif
 141
 142         /* Early VLV doesn't have this */
 143         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 144             dev->pdev->revision < 0xb) {
 145                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 146                 return 0;
 147         }
 148
 149         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 150                 return has_full_48bit_ppgtt ? 3 : 2;
 151         else
 152                 return has_aliasing_ppgtt ? 1 : 0;
 153 }
 154
 155 static int ppgtt_bind_vma(struct i915_vma *vma,
 156                           enum i915_cache_level cache_level,
 157                           u32 unused)
 158 {
 159         u32 pte_flags = 0;
 160
 161         /* Currently applicable only to VLV */
 162         if (vma->obj->gt_ro)
 163                 pte_flags |= PTE_READ_ONLY;
 164
 165         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 166                                 cache_level, pte_flags);
 167
 168         return 0;
 169 }
 170
 171 static void ppgtt_unbind_vma(struct i915_vma *vma)
 172 {
 173         vma->vm->clear_range(vma->vm,
 174                              vma->node.start,
 175                              vma->obj->base.size,
 176                              true);
 177 }
 178
 179 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 180                                   enum i915_cache_level level,
 181                                   bool valid)
 182 {
 183         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 184         pte |= addr;
 185
 186         switch (level) {
 187         case I915_CACHE_NONE:
 188                 pte |= PPAT_UNCACHED_INDEX;
 189                 break;
 190         case I915_CACHE_WT:
 191                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 192                 break;
 193         default:
 194                 pte |= PPAT_CACHED_INDEX;
 195                 break;
 196         }
 197
 198         return pte;
 199 }
 200
 201 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 202                                   const enum i915_cache_level level)
 203 {
 204         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 205         pde |= addr;
 206         if (level != I915_CACHE_NONE)
 207                 pde |= PPAT_CACHED_PDE_INDEX;
 208         else
 209                 pde |= PPAT_UNCACHED_INDEX;
 210         return pde;
 211 }
 212
 213 #define gen8_pdpe_encode gen8_pde_encode
 214 #define gen8_pml4e_encode gen8_pde_encode
 215
 216 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 217                                  enum i915_cache_level level,
 218                                  bool valid, u32 unused)
 219 {
 220         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 221         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 222
 223         switch (level) {
 224         case I915_CACHE_L3_LLC:
 225         case I915_CACHE_LLC:
 226                 pte |= GEN6_PTE_CACHE_LLC;
 227                 break;
 228         case I915_CACHE_NONE:
 229                 pte |= GEN6_PTE_UNCACHED;
 230                 break;
 231         default:
 232                 MISSING_CASE(level);
 233         }
 234
 235         return pte;
 236 }
 237
 238 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 239                                  enum i915_cache_level level,
 240                                  bool valid, u32 unused)
 241 {
 242         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 243         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 244
 245         switch (level) {
 246         case I915_CACHE_L3_LLC:
 247                 pte |= GEN7_PTE_CACHE_L3_LLC;
 248                 break;
 249         case I915_CACHE_LLC:
 250                 pte |= GEN6_PTE_CACHE_LLC;
 251                 break;
 252         case I915_CACHE_NONE:
 253                 pte |= GEN6_PTE_UNCACHED;
 254                 break;
 255         default:
 256                 MISSING_CASE(level);
 257         }
 258
 259         return pte;
 260 }
 261
 262 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 263                                  enum i915_cache_level level,
 264                                  bool valid, u32 flags)
 265 {
 266         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 267         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 268
 269         if (!(flags & PTE_READ_ONLY))
 270                 pte |= BYT_PTE_WRITEABLE;
 271
 272         if (level != I915_CACHE_NONE)
 273                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 274
 275         return pte;
 276 }
 277
 278 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 279                                  enum i915_cache_level level,
 280                                  bool valid, u32 unused)
 281 {
 282         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 283         pte |= HSW_PTE_ADDR_ENCODE(addr);
 284
 285         if (level != I915_CACHE_NONE)
 286                 pte |= HSW_WB_LLC_AGE3;
 287
 288         return pte;
 289 }
 290
 291 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 292                                   enum i915_cache_level level,
 293                                   bool valid, u32 unused)
 294 {
 295         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 296         pte |= HSW_PTE_ADDR_ENCODE(addr);
 297
 298         switch (level) {
 299         case I915_CACHE_NONE:
 300                 break;
 301         case I915_CACHE_WT:
 302                 pte |= HSW_WT_ELLC_LLC_AGE3;
 303                 break;
 304         default:
 305                 pte |= HSW_WB_ELLC_LLC_AGE3;
 306                 break;
 307         }
 308
 309         return pte;
 310 }
 311
 312 static int __setup_page_dma(struct drm_device *dev,
 313                             struct i915_page_dma *p, gfp_t flags)
 314 {
 315         struct device *device = &dev->pdev->dev;
 316
 317         p->page = alloc_page(flags);
 318         if (!p->page)
 319                 return -ENOMEM;
 320
 321         p->daddr = dma_map_page(device,
 322                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 323
 324         if (dma_mapping_error(device, p->daddr)) {
 325                 __free_page(p->page);
 326                 return -EINVAL;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 333 {
 334         return __setup_page_dma(dev, p, GFP_KERNEL);
 335 }
 336
 337 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 338 {
 339         if (WARN_ON(!p->page))
 340                 return;
 341
 342         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 343         __free_page(p->page);
 344         memset(p, 0, sizeof(*p));
 345 }
 346
 347 static void *kmap_page_dma(struct i915_page_dma *p)
 348 {
 349         return kmap_atomic(p->page);
 350 }
 351
 352 /* We use the flushing unmap only with ppgtt structures:
 353  * page directories, page tables and scratch pages.
 354  */
 355 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 356 {
 357         /* There are only few exceptions for gen >=6. chv and bxt.
 358          * And we are not sure about the latter so play safe for now.
 359          */
 360         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 361                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 362
 363         kunmap_atomic(vaddr);
 364 }
 365
 366 #define kmap_px(px) kmap_page_dma(px_base(px))
 367 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 368
 369 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 370 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 371 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 372 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 373
 374 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 375                           const uint64_t val)
 376 {
 377         int i;
 378         uint64_t * const vaddr = kmap_page_dma(p);
 379
 380         for (i = 0; i < 512; i++)
 381                 vaddr[i] = val;
 382
 383         kunmap_page_dma(dev, vaddr);
 384 }
 385
 386 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 387                              const uint32_t val32)
 388 {
 389         uint64_t v = val32;
 390
 391         v = v << 32 | val32;
 392
 393         fill_page_dma(dev, p, v);
 394 }
 395
 396 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 397 {
 398         struct i915_page_scratch *sp;
 399         int ret;
 400
 401         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 402         if (sp == NULL)
 403                 return ERR_PTR(-ENOMEM);
 404
 405         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 406         if (ret) {
 407                 kfree(sp);
 408                 return ERR_PTR(ret);
 409         }
 410
 411         set_pages_uc(px_page(sp), 1);
 412
 413         return sp;
 414 }
 415
 416 static void free_scratch_page(struct drm_device *dev,
 417                               struct i915_page_scratch *sp)
 418 {
 419         set_pages_wb(px_page(sp), 1);
 420
 421         cleanup_px(dev, sp);
 422         kfree(sp);
 423 }
 424
 425 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 426 {
 427         struct i915_page_table *pt;
 428         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 429                 GEN8_PTES : GEN6_PTES;
 430         int ret = -ENOMEM;
 431
 432         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 433         if (!pt)
 434                 return ERR_PTR(-ENOMEM);
 435
 436         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 437                                 GFP_KERNEL);
 438
 439         if (!pt->used_ptes)
 440                 goto fail_bitmap;
 441
 442         ret = setup_px(dev, pt);
 443         if (ret)
 444                 goto fail_page_m;
 445
 446         return pt;
 447
 448 fail_page_m:
 449         kfree(pt->used_ptes);
 450 fail_bitmap:
 451         kfree(pt);
 452
 453         return ERR_PTR(ret);
 454 }
 455
 456 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 457 {
 458         cleanup_px(dev, pt);
 459         kfree(pt->used_ptes);
 460         kfree(pt);
 461 }
 462
 463 static void gen8_initialize_pt(struct i915_address_space *vm,
 464                                struct i915_page_table *pt)
 465 {
 466         gen8_pte_t scratch_pte;
 467
 468         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 469                                       I915_CACHE_LLC, true);
 470
 471         fill_px(vm->dev, pt, scratch_pte);
 472 }
 473
 474 static void gen6_initialize_pt(struct i915_address_space *vm,
 475                                struct i915_page_table *pt)
 476 {
 477         gen6_pte_t scratch_pte;
 478
 479         WARN_ON(px_dma(vm->scratch_page) == 0);
 480
 481         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 482                                      I915_CACHE_LLC, true, 0);
 483
 484         fill32_px(vm->dev, pt, scratch_pte);
 485 }
 486
 487 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 488 {
 489         struct i915_page_directory *pd;
 490         int ret = -ENOMEM;
 491
 492         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 493         if (!pd)
 494                 return ERR_PTR(-ENOMEM);
 495
 496         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 497                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 498         if (!pd->used_pdes)
 499                 goto fail_bitmap;
 500
 501         ret = setup_px(dev, pd);
 502         if (ret)
 503                 goto fail_page_m;
 504
 505         return pd;
 506
 507 fail_page_m:
 508         kfree(pd->used_pdes);
 509 fail_bitmap:
 510         kfree(pd);
 511
 512         return ERR_PTR(ret);
 513 }
 514
 515 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 516 {
 517         if (px_page(pd)) {
 518                 cleanup_px(dev, pd);
 519                 kfree(pd->used_pdes);
 520                 kfree(pd);
 521         }
 522 }
 523
 524 static void gen8_initialize_pd(struct i915_address_space *vm,
 525                                struct i915_page_directory *pd)
 526 {
 527         gen8_pde_t scratch_pde;
 528
 529         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 530
 531         fill_px(vm->dev, pd, scratch_pde);
 532 }
 533
 534 static int __pdp_init(struct drm_device *dev,
 535                       struct i915_page_directory_pointer *pdp)
 536 {
 537         size_t pdpes = I915_PDPES_PER_PDP(dev);
 538
 539         pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
 540                                   sizeof(unsigned long),
 541                                   GFP_KERNEL);
 542         if (!pdp->used_pdpes)
 543                 return -ENOMEM;
 544
 545         pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
 546                                       GFP_KERNEL);
 547         if (!pdp->page_directory) {
 548                 kfree(pdp->used_pdpes);
 549                 /* the PDP might be the statically allocated top level. Keep it
 550                  * as clean as possible */
 551                 pdp->used_pdpes = NULL;
 552                 return -ENOMEM;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 559 {
 560         kfree(pdp->used_pdpes);
 561         kfree(pdp->page_directory);
 562         pdp->page_directory = NULL;
 563 }
 564
 565 static struct
 566 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
 567 {
 568         struct i915_page_directory_pointer *pdp;
 569         int ret = -ENOMEM;
 570
 571         WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
 572
 573         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 574         if (!pdp)
 575                 return ERR_PTR(-ENOMEM);
 576
 577         ret = __pdp_init(dev, pdp);
 578         if (ret)
 579                 goto fail_bitmap;
 580
 581         ret = setup_px(dev, pdp);
 582         if (ret)
 583                 goto fail_page_m;
 584
 585         return pdp;
 586
 587 fail_page_m:
 588         __pdp_fini(pdp);
 589 fail_bitmap:
 590         kfree(pdp);
 591
 592         return ERR_PTR(ret);
 593 }
 594
 595 static void free_pdp(struct drm_device *dev,
 596                      struct i915_page_directory_pointer *pdp)
 597 {
 598         __pdp_fini(pdp);
 599         if (USES_FULL_48BIT_PPGTT(dev)) {
 600                 cleanup_px(dev, pdp);
 601                 kfree(pdp);
 602         }
 603 }
 604
 605 static void gen8_initialize_pdp(struct i915_address_space *vm,
 606                                 struct i915_page_directory_pointer *pdp)
 607 {
 608         gen8_ppgtt_pdpe_t scratch_pdpe;
 609
 610         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 611
 612         fill_px(vm->dev, pdp, scratch_pdpe);
 613 }
 614
 615 static void gen8_initialize_pml4(struct i915_address_space *vm,
 616                                  struct i915_pml4 *pml4)
 617 {
 618         gen8_ppgtt_pml4e_t scratch_pml4e;
 619
 620         scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
 621                                           I915_CACHE_LLC);
 622
 623         fill_px(vm->dev, pml4, scratch_pml4e);
 624 }
 625
 626 static void
 627 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
 628                           struct i915_page_directory_pointer *pdp,
 629                           struct i915_page_directory *pd,
 630                           int index)
 631 {
 632         gen8_ppgtt_pdpe_t *page_directorypo;
 633
 634         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 635                 return;
 636
 637         page_directorypo = kmap_px(pdp);
 638         page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 639         kunmap_px(ppgtt, page_directorypo);
 640 }
 641
 642 static void
 643 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
 644                                   struct i915_pml4 *pml4,
 645                                   struct i915_page_directory_pointer *pdp,
 646                                   int index)
 647 {
 648         gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 649
 650         WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
 651         pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 652         kunmap_px(ppgtt, pagemap);
 653 }
 654
 655 /* Broadwell Page Directory Pointer Descriptors */
 656 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 657                           unsigned entry,
 658                           dma_addr_t addr)
 659 {
 660         struct intel_engine_cs *ring = req->ring;
 661         int ret;
 662
 663         BUG_ON(entry >= 4);
 664
 665         ret = intel_ring_begin(req, 6);
 666         if (ret)
 667                 return ret;
 668
 669         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 670         intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(ring, entry));
 671         intel_ring_emit(ring, upper_32_bits(addr));
 672         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 673         intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(ring, entry));
 674         intel_ring_emit(ring, lower_32_bits(addr));
 675         intel_ring_advance(ring);
 676
 677         return 0;
 678 }
 679
 680 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
 681                                  struct drm_i915_gem_request *req)
 682 {
 683         int i, ret;
 684
 685         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 686                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 687
 688                 ret = gen8_write_pdp(req, i, pd_daddr);
 689                 if (ret)
 690                         return ret;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
 697                               struct drm_i915_gem_request *req)
 698 {
 699         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
 700 }
 701
 702 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
 703                                        struct i915_page_directory_pointer *pdp,
 704                                        uint64_t start,
 705                                        uint64_t length,
 706                                        gen8_pte_t scratch_pte)
 707 {
 708         struct i915_hw_ppgtt *ppgtt =
 709                 container_of(vm, struct i915_hw_ppgtt, base);
 710         gen8_pte_t *pt_vaddr;
 711         unsigned pdpe = gen8_pdpe_index(start);
 712         unsigned pde = gen8_pde_index(start);
 713         unsigned pte = gen8_pte_index(start);
 714         unsigned num_entries = length >> PAGE_SHIFT;
 715         unsigned last_pte, i;
 716
 717         if (WARN_ON(!pdp))
 718                 return;
 719
 720         while (num_entries) {
 721                 struct i915_page_directory *pd;
 722                 struct i915_page_table *pt;
 723
 724                 if (WARN_ON(!pdp->page_directory[pdpe]))
 725                         break;
 726
 727                 pd = pdp->page_directory[pdpe];
 728
 729                 if (WARN_ON(!pd->page_table[pde]))
 730                         break;
 731
 732                 pt = pd->page_table[pde];
 733
 734                 if (WARN_ON(!px_page(pt)))
 735                         break;
 736
 737                 last_pte = pte + num_entries;
 738                 if (last_pte > GEN8_PTES)
 739                         last_pte = GEN8_PTES;
 740
 741                 pt_vaddr = kmap_px(pt);
 742
 743                 for (i = pte; i < last_pte; i++) {
 744                         pt_vaddr[i] = scratch_pte;
 745                         num_entries--;
 746                 }
 747
 748                 kunmap_px(ppgtt, pt);
 749
 750                 pte = 0;
 751                 if (++pde == I915_PDES) {
 752                         if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 753                                 break;
 754                         pde = 0;
 755                 }
 756         }
 757 }
 758
 759 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 760                                    uint64_t start,
 761                                    uint64_t length,
 762                                    bool use_scratch)
 763 {
 764         struct i915_hw_ppgtt *ppgtt =
 765                 container_of(vm, struct i915_hw_ppgtt, base);
 766         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 767                                                  I915_CACHE_LLC, use_scratch);
 768
 769         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 770                 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
 771                                            scratch_pte);
 772         } else {
 773                 uint64_t pml4e;
 774                 struct i915_page_directory_pointer *pdp;
 775
 776                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 777                         gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
 778                                                    scratch_pte);
 779                 }
 780         }
 781 }
 782
 783 static void
 784 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
 785                               struct i915_page_directory_pointer *pdp,
 786                               struct sg_page_iter *sg_iter,
 787                               uint64_t start,
 788                               enum i915_cache_level cache_level)
 789 {
 790         struct i915_hw_ppgtt *ppgtt =
 791                 container_of(vm, struct i915_hw_ppgtt, base);
 792         gen8_pte_t *pt_vaddr;
 793         unsigned pdpe = gen8_pdpe_index(start);
 794         unsigned pde = gen8_pde_index(start);
 795         unsigned pte = gen8_pte_index(start);
 796
 797         pt_vaddr = NULL;
 798
 799         while (__sg_page_iter_next(sg_iter)) {
 800                 if (pt_vaddr == NULL) {
 801                         struct i915_page_directory *pd = pdp->page_directory[pdpe];
 802                         struct i915_page_table *pt = pd->page_table[pde];
 803                         pt_vaddr = kmap_px(pt);
 804                 }
 805
 806                 pt_vaddr[pte] =
 807                         gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
 808                                         cache_level, true);
 809                 if (++pte == GEN8_PTES) {
 810                         kunmap_px(ppgtt, pt_vaddr);
 811                         pt_vaddr = NULL;
 812                         if (++pde == I915_PDES) {
 813                                 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 814                                         break;
 815                                 pde = 0;
 816                         }
 817                         pte = 0;
 818                 }
 819         }
 820
 821         if (pt_vaddr)
 822                 kunmap_px(ppgtt, pt_vaddr);
 823 }
 824
 825 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 826                                       struct sg_table *pages,
 827                                       uint64_t start,
 828                                       enum i915_cache_level cache_level,
 829                                       u32 unused)
 830 {
 831         struct i915_hw_ppgtt *ppgtt =
 832                 container_of(vm, struct i915_hw_ppgtt, base);
 833         struct sg_page_iter sg_iter;
 834
 835         __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
 836
 837         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 838                 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
 839                                               cache_level);
 840         } else {
 841                 struct i915_page_directory_pointer *pdp;
 842                 uint64_t pml4e;
 843                 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
 844
 845                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 846                         gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
 847                                                       start, cache_level);
 848                 }
 849         }
 850 }
 851
 852 static void gen8_free_page_tables(struct drm_device *dev,
 853                                   struct i915_page_directory *pd)
 854 {
 855         int i;
 856
 857         if (!px_page(pd))
 858                 return;
 859
 860         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 861                 if (WARN_ON(!pd->page_table[i]))
 862                         continue;
 863
 864                 free_pt(dev, pd->page_table[i]);
 865                 pd->page_table[i] = NULL;
 866         }
 867 }
 868
 869 static int gen8_init_scratch(struct i915_address_space *vm)
 870 {
 871         struct drm_device *dev = vm->dev;
 872
 873         vm->scratch_page = alloc_scratch_page(dev);
 874         if (IS_ERR(vm->scratch_page))
 875                 return PTR_ERR(vm->scratch_page);
 876
 877         vm->scratch_pt = alloc_pt(dev);
 878         if (IS_ERR(vm->scratch_pt)) {
 879                 free_scratch_page(dev, vm->scratch_page);
 880                 return PTR_ERR(vm->scratch_pt);
 881         }
 882
 883         vm->scratch_pd = alloc_pd(dev);
 884         if (IS_ERR(vm->scratch_pd)) {
 885                 free_pt(dev, vm->scratch_pt);
 886                 free_scratch_page(dev, vm->scratch_page);
 887                 return PTR_ERR(vm->scratch_pd);
 888         }
 889
 890         if (USES_FULL_48BIT_PPGTT(dev)) {
 891                 vm->scratch_pdp = alloc_pdp(dev);
 892                 if (IS_ERR(vm->scratch_pdp)) {
 893                         free_pd(dev, vm->scratch_pd);
 894                         free_pt(dev, vm->scratch_pt);
 895                         free_scratch_page(dev, vm->scratch_page);
 896                         return PTR_ERR(vm->scratch_pdp);
 897                 }
 898         }
 899
 900         gen8_initialize_pt(vm, vm->scratch_pt);
 901         gen8_initialize_pd(vm, vm->scratch_pd);
 902         if (USES_FULL_48BIT_PPGTT(dev))
 903                 gen8_initialize_pdp(vm, vm->scratch_pdp);
 904
 905         return 0;
 906 }
 907
 908 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
 909 {
 910         enum vgt_g2v_type msg;
 911         struct drm_device *dev = ppgtt->base.dev;
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         int i;
 914
 915         if (USES_FULL_48BIT_PPGTT(dev)) {
 916                 u64 daddr = px_dma(&ppgtt->pml4);
 917
 918                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
 919                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
 920
 921                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 922                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 923         } else {
 924                 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 925                         u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
 926
 927                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
 928                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
 929                 }
 930
 931                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 932                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
 933         }
 934
 935         I915_WRITE(vgtif_reg(g2v_notify), msg);
 936
 937         return 0;
 938 }
 939
 940 static void gen8_free_scratch(struct i915_address_space *vm)
 941 {
 942         struct drm_device *dev = vm->dev;
 943
 944         if (USES_FULL_48BIT_PPGTT(dev))
 945                 free_pdp(dev, vm->scratch_pdp);
 946         free_pd(dev, vm->scratch_pd);
 947         free_pt(dev, vm->scratch_pt);
 948         free_scratch_page(dev, vm->scratch_page);
 949 }
 950
 951 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
 952                                     struct i915_page_directory_pointer *pdp)
 953 {
 954         int i;
 955
 956         for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
 957                 if (WARN_ON(!pdp->page_directory[i]))
 958                         continue;
 959
 960                 gen8_free_page_tables(dev, pdp->page_directory[i]);
 961                 free_pd(dev, pdp->page_directory[i]);
 962         }
 963
 964         free_pdp(dev, pdp);
 965 }
 966
 967 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
 968 {
 969         int i;
 970
 971         for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
 972                 if (WARN_ON(!ppgtt->pml4.pdps[i]))
 973                         continue;
 974
 975                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
 976         }
 977
 978         cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
 979 }
 980
 981 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 982 {
 983         struct i915_hw_ppgtt *ppgtt =
 984                 container_of(vm, struct i915_hw_ppgtt, base);
 985
 986         if (intel_vgpu_active(vm->dev))
 987                 gen8_ppgtt_notify_vgt(ppgtt, false);
 988
 989         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 990                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
 991         else
 992                 gen8_ppgtt_cleanup_4lvl(ppgtt);
 993
 994         gen8_free_scratch(vm);
 995 }
 996
 997 /**
 998  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 999  * @vm: Master vm structure.
1000  * @pd: Page directory for this address range.
1001  * @start:      Starting virtual address to begin allocations.
1002  * @length:     Size of the allocations.
1003  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
1004  *              caller to free on error.
1005  *
1006  * Allocate the required number of page tables. Extremely similar to
1007  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1008  * the page directory boundary (instead of the page directory pointer). That
1009  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1010  * possible, and likely that the caller will need to use multiple calls of this
1011  * function to achieve the appropriate allocation.
1012  *
1013  * Return: 0 if success; negative error code otherwise.
1014  */
1015 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1016                                      struct i915_page_directory *pd,
1017                                      uint64_t start,
1018                                      uint64_t length,
1019                                      unsigned long *new_pts)
1020 {
1021         struct drm_device *dev = vm->dev;
1022         struct i915_page_table *pt;
1023         uint32_t pde;
1024
1025         gen8_for_each_pde(pt, pd, start, length, pde) {
1026                 /* Don't reallocate page tables */
1027                 if (test_bit(pde, pd->used_pdes)) {
1028                         /* Scratch is never allocated this way */
1029                         WARN_ON(pt == vm->scratch_pt);
1030                         continue;
1031                 }
1032
1033                 pt = alloc_pt(dev);
1034                 if (IS_ERR(pt))
1035                         goto unwind_out;
1036
1037                 gen8_initialize_pt(vm, pt);
1038                 pd->page_table[pde] = pt;
1039                 __set_bit(pde, new_pts);
1040                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1041         }
1042
1043         return 0;
1044
1045 unwind_out:
1046         for_each_set_bit(pde, new_pts, I915_PDES)
1047                 free_pt(dev, pd->page_table[pde]);
1048
1049         return -ENOMEM;
1050 }
1051
1052 /**
1053  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1054  * @vm: Master vm structure.
1055  * @pdp:        Page directory pointer for this address range.
1056  * @start:      Starting virtual address to begin allocations.
1057  * @length:     Size of the allocations.
1058  * @new_pds:    Bitmap set by function with new allocations. Likely used by the
1059  *              caller to free on error.
1060  *
1061  * Allocate the required number of page directories starting at the pde index of
1062  * @start, and ending at the pde index @start + @length. This function will skip
1063  * over already allocated page directories within the range, and only allocate
1064  * new ones, setting the appropriate pointer within the pdp as well as the
1065  * correct position in the bitmap @new_pds.
1066  *
1067  * The function will only allocate the pages within the range for a give page
1068  * directory pointer. In other words, if @start + @length straddles a virtually
1069  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1070  * required by the caller, This is not currently possible, and the BUG in the
1071  * code will prevent it.
1072  *
1073  * Return: 0 if success; negative error code otherwise.
1074  */
1075 static int
1076 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1077                                   struct i915_page_directory_pointer *pdp,
1078                                   uint64_t start,
1079                                   uint64_t length,
1080                                   unsigned long *new_pds)
1081 {
1082         struct drm_device *dev = vm->dev;
1083         struct i915_page_directory *pd;
1084         uint32_t pdpe;
1085         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1086
1087         WARN_ON(!bitmap_empty(new_pds, pdpes));
1088
1089         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1090                 if (test_bit(pdpe, pdp->used_pdpes))
1091                         continue;
1092
1093                 pd = alloc_pd(dev);
1094                 if (IS_ERR(pd))
1095                         goto unwind_out;
1096
1097                 gen8_initialize_pd(vm, pd);
1098                 pdp->page_directory[pdpe] = pd;
1099                 __set_bit(pdpe, new_pds);
1100                 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1101         }
1102
1103         return 0;
1104
1105 unwind_out:
1106         for_each_set_bit(pdpe, new_pds, pdpes)
1107                 free_pd(dev, pdp->page_directory[pdpe]);
1108
1109         return -ENOMEM;
1110 }
1111
1112 /**
1113  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1114  * @vm: Master vm structure.
1115  * @pml4:       Page map level 4 for this address range.
1116  * @start:      Starting virtual address to begin allocations.
1117  * @length:     Size of the allocations.
1118  * @new_pdps:   Bitmap set by function with new allocations. Likely used by the
1119  *              caller to free on error.
1120  *
1121  * Allocate the required number of page directory pointers. Extremely similar to
1122  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1123  * The main difference is here we are limited by the pml4 boundary (instead of
1124  * the page directory pointer).
1125  *
1126  * Return: 0 if success; negative error code otherwise.
1127  */
1128 static int
1129 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1130                                   struct i915_pml4 *pml4,
1131                                   uint64_t start,
1132                                   uint64_t length,
1133                                   unsigned long *new_pdps)
1134 {
1135         struct drm_device *dev = vm->dev;
1136         struct i915_page_directory_pointer *pdp;
1137         uint32_t pml4e;
1138
1139         WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1140
1141         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1142                 if (!test_bit(pml4e, pml4->used_pml4es)) {
1143                         pdp = alloc_pdp(dev);
1144                         if (IS_ERR(pdp))
1145                                 goto unwind_out;
1146
1147                         gen8_initialize_pdp(vm, pdp);
1148                         pml4->pdps[pml4e] = pdp;
1149                         __set_bit(pml4e, new_pdps);
1150                         trace_i915_page_directory_pointer_entry_alloc(vm,
1151                                                                       pml4e,
1152                                                                       start,
1153                                                                       GEN8_PML4E_SHIFT);
1154                 }
1155         }
1156
1157         return 0;
1158
1159 unwind_out:
1160         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1161                 free_pdp(dev, pml4->pdps[pml4e]);
1162
1163         return -ENOMEM;
1164 }
1165
1166 static void
1167 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1168 {
1169         kfree(new_pts);
1170         kfree(new_pds);
1171 }
1172
1173 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1174  * of these are based on the number of PDPEs in the system.
1175  */
1176 static
1177 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1178                                          unsigned long **new_pts,
1179                                          uint32_t pdpes)
1180 {
1181         unsigned long *pds;
1182         unsigned long *pts;
1183
1184         pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1185         if (!pds)
1186                 return -ENOMEM;
1187
1188         pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1189                       GFP_TEMPORARY);
1190         if (!pts)
1191                 goto err_out;
1192
1193         *new_pds = pds;
1194         *new_pts = pts;
1195
1196         return 0;
1197
1198 err_out:
1199         free_gen8_temp_bitmaps(pds, pts);
1200         return -ENOMEM;
1201 }
1202
1203 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1204  * the page table structures, we mark them dirty so that
1205  * context switching/execlist queuing code takes extra steps
1206  * to ensure that tlbs are flushed.
1207  */
1208 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1209 {
1210         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1211 }
1212
1213 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1214                                     struct i915_page_directory_pointer *pdp,
1215                                     uint64_t start,
1216                                     uint64_t length)
1217 {
1218         struct i915_hw_ppgtt *ppgtt =
1219                 container_of(vm, struct i915_hw_ppgtt, base);
1220         unsigned long *new_page_dirs, *new_page_tables;
1221         struct drm_device *dev = vm->dev;
1222         struct i915_page_directory *pd;
1223         const uint64_t orig_start = start;
1224         const uint64_t orig_length = length;
1225         uint32_t pdpe;
1226         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1227         int ret;
1228
1229         /* Wrap is never okay since we can only represent 48b, and we don't
1230          * actually use the other side of the canonical address space.
1231          */
1232         if (WARN_ON(start + length < start))
1233                 return -ENODEV;
1234
1235         if (WARN_ON(start + length > vm->total))
1236                 return -ENODEV;
1237
1238         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1239         if (ret)
1240                 return ret;
1241
1242         /* Do the allocations first so we can easily bail out */
1243         ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1244                                                 new_page_dirs);
1245         if (ret) {
1246                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1247                 return ret;
1248         }
1249
1250         /* For every page directory referenced, allocate page tables */
1251         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1252                 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1253                                                 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1254                 if (ret)
1255                         goto err_out;
1256         }
1257
1258         start = orig_start;
1259         length = orig_length;
1260
1261         /* Allocations have completed successfully, so set the bitmaps, and do
1262          * the mappings. */
1263         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1264                 gen8_pde_t *const page_directory = kmap_px(pd);
1265                 struct i915_page_table *pt;
1266                 uint64_t pd_len = length;
1267                 uint64_t pd_start = start;
1268                 uint32_t pde;
1269
1270                 /* Every pd should be allocated, we just did that above. */
1271                 WARN_ON(!pd);
1272
1273                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1274                         /* Same reasoning as pd */
1275                         WARN_ON(!pt);
1276                         WARN_ON(!pd_len);
1277                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
1278
1279                         /* Set our used ptes within the page table */
1280                         bitmap_set(pt->used_ptes,
1281                                    gen8_pte_index(pd_start),
1282                                    gen8_pte_count(pd_start, pd_len));
1283
1284                         /* Our pde is now pointing to the pagetable, pt */
1285                         __set_bit(pde, pd->used_pdes);
1286
1287                         /* Map the PDE to the page table */
1288                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
1289                                                               I915_CACHE_LLC);
1290                         trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1291                                                         gen8_pte_index(start),
1292                                                         gen8_pte_count(start, length),
1293                                                         GEN8_PTES);
1294
1295                         /* NB: We haven't yet mapped ptes to pages. At this
1296                          * point we're still relying on insert_entries() */
1297                 }
1298
1299                 kunmap_px(ppgtt, page_directory);
1300                 __set_bit(pdpe, pdp->used_pdpes);
1301                 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1302         }
1303
1304         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1305         mark_tlbs_dirty(ppgtt);
1306         return 0;
1307
1308 err_out:
1309         while (pdpe--) {
1310                 unsigned long temp;
1311
1312                 for_each_set_bit(temp, new_page_tables + pdpe *
1313                                 BITS_TO_LONGS(I915_PDES), I915_PDES)
1314                         free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1315         }
1316
1317         for_each_set_bit(pdpe, new_page_dirs, pdpes)
1318                 free_pd(dev, pdp->page_directory[pdpe]);
1319
1320         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1321         mark_tlbs_dirty(ppgtt);
1322         return ret;
1323 }
1324
1325 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1326                                     struct i915_pml4 *pml4,
1327                                     uint64_t start,
1328                                     uint64_t length)
1329 {
1330         DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1331         struct i915_hw_ppgtt *ppgtt =
1332                         container_of(vm, struct i915_hw_ppgtt, base);
1333         struct i915_page_directory_pointer *pdp;
1334         uint64_t pml4e;
1335         int ret = 0;
1336
1337         /* Do the pml4 allocations first, so we don't need to track the newly
1338          * allocated tables below the pdp */
1339         bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1340
1341         /* The pagedirectory and pagetable allocations are done in the shared 3
1342          * and 4 level code. Just allocate the pdps.
1343          */
1344         ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1345                                                 new_pdps);
1346         if (ret)
1347                 return ret;
1348
1349         WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1350              "The allocation has spanned more than 512GB. "
1351              "It is highly likely this is incorrect.");
1352
1353         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1354                 WARN_ON(!pdp);
1355
1356                 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1357                 if (ret)
1358                         goto err_out;
1359
1360                 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1361         }
1362
1363         bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1364                   GEN8_PML4ES_PER_PML4);
1365
1366         return 0;
1367
1368 err_out:
1369         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1370                 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1371
1372         return ret;
1373 }
1374
1375 static int gen8_alloc_va_range(struct i915_address_space *vm,
1376                                uint64_t start, uint64_t length)
1377 {
1378         struct i915_hw_ppgtt *ppgtt =
1379                 container_of(vm, struct i915_hw_ppgtt, base);
1380
1381         if (USES_FULL_48BIT_PPGTT(vm->dev))
1382                 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1383         else
1384                 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1385 }
1386
1387 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1388                           uint64_t start, uint64_t length,
1389                           gen8_pte_t scratch_pte,
1390                           struct seq_file *m)
1391 {
1392         struct i915_page_directory *pd;
1393         uint32_t pdpe;
1394
1395         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1396                 struct i915_page_table *pt;
1397                 uint64_t pd_len = length;
1398                 uint64_t pd_start = start;
1399                 uint32_t pde;
1400
1401                 if (!test_bit(pdpe, pdp->used_pdpes))
1402                         continue;
1403
1404                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1405                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1406                         uint32_t  pte;
1407                         gen8_pte_t *pt_vaddr;
1408
1409                         if (!test_bit(pde, pd->used_pdes))
1410                                 continue;
1411
1412                         pt_vaddr = kmap_px(pt);
1413                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1414                                 uint64_t va =
1415                                         (pdpe << GEN8_PDPE_SHIFT) |
1416                                         (pde << GEN8_PDE_SHIFT) |
1417                                         (pte << GEN8_PTE_SHIFT);
1418                                 int i;
1419                                 bool found = false;
1420
1421                                 for (i = 0; i < 4; i++)
1422                                         if (pt_vaddr[pte + i] != scratch_pte)
1423                                                 found = true;
1424                                 if (!found)
1425                                         continue;
1426
1427                                 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1428                                 for (i = 0; i < 4; i++) {
1429                                         if (pt_vaddr[pte + i] != scratch_pte)
1430                                                 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1431                                         else
1432                                                 seq_puts(m, "  SCRATCH ");
1433                                 }
1434                                 seq_puts(m, "\n");
1435                         }
1436                         /* don't use kunmap_px, it could trigger
1437                          * an unnecessary flush.
1438                          */
1439                         kunmap_atomic(pt_vaddr);
1440                 }
1441         }
1442 }
1443
1444 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1445 {
1446         struct i915_address_space *vm = &ppgtt->base;
1447         uint64_t start = ppgtt->base.start;
1448         uint64_t length = ppgtt->base.total;
1449         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1450                                                  I915_CACHE_LLC, true);
1451
1452         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1453                 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1454         } else {
1455                 uint64_t pml4e;
1456                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1457                 struct i915_page_directory_pointer *pdp;
1458
1459                 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1460                         if (!test_bit(pml4e, pml4->used_pml4es))
1461                                 continue;
1462
1463                         seq_printf(m, "    PML4E #%llu\n", pml4e);
1464                         gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1465                 }
1466         }
1467 }
1468
1469 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1470 {
1471         unsigned long *new_page_dirs, *new_page_tables;
1472         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1473         int ret;
1474
1475         /* We allocate temp bitmap for page tables for no gain
1476          * but as this is for init only, lets keep the things simple
1477          */
1478         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1479         if (ret)
1480                 return ret;
1481
1482         /* Allocate for all pdps regardless of how the ppgtt
1483          * was defined.
1484          */
1485         ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1486                                                 0, 1ULL << 32,
1487                                                 new_page_dirs);
1488         if (!ret)
1489                 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1490
1491         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1492
1493         return ret;
1494 }
1495
1496 /*
1497  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1498  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1499  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1500  * space.
1501  *
1502  */
1503 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1504 {
1505         int ret;
1506
1507         ret = gen8_init_scratch(&ppgtt->base);
1508         if (ret)
1509                 return ret;
1510
1511         ppgtt->base.start = 0;
1512         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1513         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1514         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1515         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1516         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1517         ppgtt->base.bind_vma = ppgtt_bind_vma;
1518         ppgtt->debug_dump = gen8_dump_ppgtt;
1519
1520         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1521                 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1522                 if (ret)
1523                         goto free_scratch;
1524
1525                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1526
1527                 ppgtt->base.total = 1ULL << 48;
1528                 ppgtt->switch_mm = gen8_48b_mm_switch;
1529         } else {
1530                 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1531                 if (ret)
1532                         goto free_scratch;
1533
1534                 ppgtt->base.total = 1ULL << 32;
1535                 ppgtt->switch_mm = gen8_legacy_mm_switch;
1536                 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1537                                                               0, 0,
1538                                                               GEN8_PML4E_SHIFT);
1539
1540                 if (intel_vgpu_active(ppgtt->base.dev)) {
1541                         ret = gen8_preallocate_top_level_pdps(ppgtt);
1542                         if (ret)
1543                                 goto free_scratch;
1544                 }
1545         }
1546
1547         if (intel_vgpu_active(ppgtt->base.dev))
1548                 gen8_ppgtt_notify_vgt(ppgtt, true);
1549
1550         return 0;
1551
1552 free_scratch:
1553         gen8_free_scratch(&ppgtt->base);
1554         return ret;
1555 }
1556
1557 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1558 {
1559         struct i915_address_space *vm = &ppgtt->base;
1560         struct i915_page_table *unused;
1561         gen6_pte_t scratch_pte;
1562         uint32_t pd_entry;
1563         uint32_t  pte, pde, temp;
1564         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1565
1566         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1567                                      I915_CACHE_LLC, true, 0);
1568
1569         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1570                 u32 expected;
1571                 gen6_pte_t *pt_vaddr;
1572                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1573                 pd_entry = readl(ppgtt->pd_addr + pde);
1574                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1575
1576                 if (pd_entry != expected)
1577                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1578                                    pde,
1579                                    pd_entry,
1580                                    expected);
1581                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1582
1583                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1584
1585                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1586                         unsigned long va =
1587                                 (pde * PAGE_SIZE * GEN6_PTES) +
1588                                 (pte * PAGE_SIZE);
1589                         int i;
1590                         bool found = false;
1591                         for (i = 0; i < 4; i++)
1592                                 if (pt_vaddr[pte + i] != scratch_pte)
1593                                         found = true;
1594                         if (!found)
1595                                 continue;
1596
1597                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1598                         for (i = 0; i < 4; i++) {
1599                                 if (pt_vaddr[pte + i] != scratch_pte)
1600                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1601                                 else
1602                                         seq_puts(m, "  SCRATCH ");
1603                         }
1604                         seq_puts(m, "\n");
1605                 }
1606                 kunmap_px(ppgtt, pt_vaddr);
1607         }
1608 }
1609
1610 /* Write pde (index) from the page directory @pd to the page table @pt */
1611 static void gen6_write_pde(struct i915_page_directory *pd,
1612                             const int pde, struct i915_page_table *pt)
1613 {
1614         /* Caller needs to make sure the write completes if necessary */
1615         struct i915_hw_ppgtt *ppgtt =
1616                 container_of(pd, struct i915_hw_ppgtt, pd);
1617         u32 pd_entry;
1618
1619         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1620         pd_entry |= GEN6_PDE_VALID;
1621
1622         writel(pd_entry, ppgtt->pd_addr + pde);
1623 }
1624
1625 /* Write all the page tables found in the ppgtt structure to incrementing page
1626  * directories. */
1627 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1628                                   struct i915_page_directory *pd,
1629                                   uint32_t start, uint32_t length)
1630 {
1631         struct i915_page_table *pt;
1632         uint32_t pde, temp;
1633
1634         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1635                 gen6_write_pde(pd, pde, pt);
1636
1637         /* Make sure write is complete before other code can use this page
1638          * table. Also require for WC mapped PTEs */
1639         readl(dev_priv->gtt.gsm);
1640 }
1641
1642 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1643 {
1644         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1645
1646         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1647 }
1648
1649 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1650                          struct drm_i915_gem_request *req)
1651 {
1652         struct intel_engine_cs *ring = req->ring;
1653         int ret;
1654
1655         /* NB: TLBs must be flushed and invalidated before a switch */
1656         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1657         if (ret)
1658                 return ret;
1659
1660         ret = intel_ring_begin(req, 6);
1661         if (ret)
1662                 return ret;
1663
1664         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1665         intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
1666         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1667         intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
1668         intel_ring_emit(ring, get_pd_offset(ppgtt));
1669         intel_ring_emit(ring, MI_NOOP);
1670         intel_ring_advance(ring);
1671
1672         return 0;
1673 }
1674
1675 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1676                           struct drm_i915_gem_request *req)
1677 {
1678         struct intel_engine_cs *ring = req->ring;
1679         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1680
1681         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1682         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1683         return 0;
1684 }
1685
1686 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1687                           struct drm_i915_gem_request *req)
1688 {
1689         struct intel_engine_cs *ring = req->ring;
1690         int ret;
1691
1692         /* NB: TLBs must be flushed and invalidated before a switch */
1693         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1694         if (ret)
1695                 return ret;
1696
1697         ret = intel_ring_begin(req, 6);
1698         if (ret)
1699                 return ret;
1700
1701         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1702         intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
1703         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1704         intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
1705         intel_ring_emit(ring, get_pd_offset(ppgtt));
1706         intel_ring_emit(ring, MI_NOOP);
1707         intel_ring_advance(ring);
1708
1709         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1710         if (ring->id != RCS) {
1711                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1712                 if (ret)
1713                         return ret;
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1720                           struct drm_i915_gem_request *req)
1721 {
1722         struct intel_engine_cs *ring = req->ring;
1723         struct drm_device *dev = ppgtt->base.dev;
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725
1726
1727         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1728         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1729
1730         POSTING_READ(RING_PP_DIR_DCLV(ring));
1731
1732         return 0;
1733 }
1734
1735 static void gen8_ppgtt_enable(struct drm_device *dev)
1736 {
1737         struct drm_i915_private *dev_priv = dev->dev_private;
1738         struct intel_engine_cs *ring;
1739         int j;
1740
1741         for_each_ring(ring, dev_priv, j) {
1742                 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1743                 I915_WRITE(RING_MODE_GEN7(ring),
1744                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1745         }
1746 }
1747
1748 static void gen7_ppgtt_enable(struct drm_device *dev)
1749 {
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751         struct intel_engine_cs *ring;
1752         uint32_t ecochk, ecobits;
1753         int i;
1754
1755         ecobits = I915_READ(GAC_ECO_BITS);
1756         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1757
1758         ecochk = I915_READ(GAM_ECOCHK);
1759         if (IS_HASWELL(dev)) {
1760                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1761         } else {
1762                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1763                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1764         }
1765         I915_WRITE(GAM_ECOCHK, ecochk);
1766
1767         for_each_ring(ring, dev_priv, i) {
1768                 /* GFX_MODE is per-ring on gen7+ */
1769                 I915_WRITE(RING_MODE_GEN7(ring),
1770                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1771         }
1772 }
1773
1774 static void gen6_ppgtt_enable(struct drm_device *dev)
1775 {
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         uint32_t ecochk, gab_ctl, ecobits;
1778
1779         ecobits = I915_READ(GAC_ECO_BITS);
1780         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1781                    ECOBITS_PPGTT_CACHE64B);
1782
1783         gab_ctl = I915_READ(GAB_CTL);
1784         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1785
1786         ecochk = I915_READ(GAM_ECOCHK);
1787         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1788
1789         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1790 }
1791
1792 /* PPGTT support for Sandybdrige/Gen6 and later */
1793 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1794                                    uint64_t start,
1795                                    uint64_t length,
1796                                    bool use_scratch)
1797 {
1798         struct i915_hw_ppgtt *ppgtt =
1799                 container_of(vm, struct i915_hw_ppgtt, base);
1800         gen6_pte_t *pt_vaddr, scratch_pte;
1801         unsigned first_entry = start >> PAGE_SHIFT;
1802         unsigned num_entries = length >> PAGE_SHIFT;
1803         unsigned act_pt = first_entry / GEN6_PTES;
1804         unsigned first_pte = first_entry % GEN6_PTES;
1805         unsigned last_pte, i;
1806
1807         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1808                                      I915_CACHE_LLC, true, 0);
1809
1810         while (num_entries) {
1811                 last_pte = first_pte + num_entries;
1812                 if (last_pte > GEN6_PTES)
1813                         last_pte = GEN6_PTES;
1814
1815                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1816
1817                 for (i = first_pte; i < last_pte; i++)
1818                         pt_vaddr[i] = scratch_pte;
1819
1820                 kunmap_px(ppgtt, pt_vaddr);
1821
1822                 num_entries -= last_pte - first_pte;
1823                 first_pte = 0;
1824                 act_pt++;
1825         }
1826 }
1827
1828 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1829                                       struct sg_table *pages,
1830                                       uint64_t start,
1831                                       enum i915_cache_level cache_level, u32 flags)
1832 {
1833         struct i915_hw_ppgtt *ppgtt =
1834                 container_of(vm, struct i915_hw_ppgtt, base);
1835         gen6_pte_t *pt_vaddr;
1836         unsigned first_entry = start >> PAGE_SHIFT;
1837         unsigned act_pt = first_entry / GEN6_PTES;
1838         unsigned act_pte = first_entry % GEN6_PTES;
1839         struct sg_page_iter sg_iter;
1840
1841         pt_vaddr = NULL;
1842         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1843                 if (pt_vaddr == NULL)
1844                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1845
1846                 pt_vaddr[act_pte] =
1847                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1848                                        cache_level, true, flags);
1849
1850                 if (++act_pte == GEN6_PTES) {
1851                         kunmap_px(ppgtt, pt_vaddr);
1852                         pt_vaddr = NULL;
1853                         act_pt++;
1854                         act_pte = 0;
1855                 }
1856         }
1857         if (pt_vaddr)
1858                 kunmap_px(ppgtt, pt_vaddr);
1859 }
1860
1861 static int gen6_alloc_va_range(struct i915_address_space *vm,
1862                                uint64_t start_in, uint64_t length_in)
1863 {
1864         DECLARE_BITMAP(new_page_tables, I915_PDES);
1865         struct drm_device *dev = vm->dev;
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct i915_hw_ppgtt *ppgtt =
1868                                 container_of(vm, struct i915_hw_ppgtt, base);
1869         struct i915_page_table *pt;
1870         uint32_t start, length, start_save, length_save;
1871         uint32_t pde, temp;
1872         int ret;
1873
1874         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1875                 return -ENODEV;
1876
1877         start = start_save = start_in;
1878         length = length_save = length_in;
1879
1880         bitmap_zero(new_page_tables, I915_PDES);
1881
1882         /* The allocation is done in two stages so that we can bail out with
1883          * minimal amount of pain. The first stage finds new page tables that
1884          * need allocation. The second stage marks use ptes within the page
1885          * tables.
1886          */
1887         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1888                 if (pt != vm->scratch_pt) {
1889                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1890                         continue;
1891                 }
1892
1893                 /* We've already allocated a page table */
1894                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1895
1896                 pt = alloc_pt(dev);
1897                 if (IS_ERR(pt)) {
1898                         ret = PTR_ERR(pt);
1899                         goto unwind_out;
1900                 }
1901
1902                 gen6_initialize_pt(vm, pt);
1903
1904                 ppgtt->pd.page_table[pde] = pt;
1905                 __set_bit(pde, new_page_tables);
1906                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1907         }
1908
1909         start = start_save;
1910         length = length_save;
1911
1912         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1913                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1914
1915                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1916                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1917                            gen6_pte_count(start, length));
1918
1919                 if (__test_and_clear_bit(pde, new_page_tables))
1920                         gen6_write_pde(&ppgtt->pd, pde, pt);
1921
1922                 trace_i915_page_table_entry_map(vm, pde, pt,
1923                                          gen6_pte_index(start),
1924                                          gen6_pte_count(start, length),
1925                                          GEN6_PTES);
1926                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1927                                 GEN6_PTES);
1928         }
1929
1930         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1931
1932         /* Make sure write is complete before other code can use this page
1933          * table. Also require for WC mapped PTEs */
1934         readl(dev_priv->gtt.gsm);
1935
1936         mark_tlbs_dirty(ppgtt);
1937         return 0;
1938
1939 unwind_out:
1940         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1941                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1942
1943                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1944                 free_pt(vm->dev, pt);
1945         }
1946
1947         mark_tlbs_dirty(ppgtt);
1948         return ret;
1949 }
1950
1951 static int gen6_init_scratch(struct i915_address_space *vm)
1952 {
1953         struct drm_device *dev = vm->dev;
1954
1955         vm->scratch_page = alloc_scratch_page(dev);
1956         if (IS_ERR(vm->scratch_page))
1957                 return PTR_ERR(vm->scratch_page);
1958
1959         vm->scratch_pt = alloc_pt(dev);
1960         if (IS_ERR(vm->scratch_pt)) {
1961                 free_scratch_page(dev, vm->scratch_page);
1962                 return PTR_ERR(vm->scratch_pt);
1963         }
1964
1965         gen6_initialize_pt(vm, vm->scratch_pt);
1966
1967         return 0;
1968 }
1969
1970 static void gen6_free_scratch(struct i915_address_space *vm)
1971 {
1972         struct drm_device *dev = vm->dev;
1973
1974         free_pt(dev, vm->scratch_pt);
1975         free_scratch_page(dev, vm->scratch_page);
1976 }
1977
1978 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1979 {
1980         struct i915_hw_ppgtt *ppgtt =
1981                 container_of(vm, struct i915_hw_ppgtt, base);
1982         struct i915_page_table *pt;
1983         uint32_t pde;
1984
1985         drm_mm_remove_node(&ppgtt->node);
1986
1987         gen6_for_all_pdes(pt, ppgtt, pde) {
1988                 if (pt != vm->scratch_pt)
1989                         free_pt(ppgtt->base.dev, pt);
1990         }
1991
1992         gen6_free_scratch(vm);
1993 }
1994
1995 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1996 {
1997         struct i915_address_space *vm = &ppgtt->base;
1998         struct drm_device *dev = ppgtt->base.dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         bool retried = false;
2001         int ret;
2002
2003         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2004          * allocator works in address space sizes, so it's multiplied by page
2005          * size. We allocate at the top of the GTT to avoid fragmentation.
2006          */
2007         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
2008
2009         ret = gen6_init_scratch(vm);
2010         if (ret)
2011                 return ret;
2012
2013 alloc:
2014         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2015                                                   &ppgtt->node, GEN6_PD_SIZE,
2016                                                   GEN6_PD_ALIGN, 0,
2017                                                   0, dev_priv->gtt.base.total,
2018                                                   DRM_MM_TOPDOWN);
2019         if (ret == -ENOSPC && !retried) {
2020                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2021                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
2022                                                I915_CACHE_NONE,
2023                                                0, dev_priv->gtt.base.total,
2024                                                0);
2025                 if (ret)
2026                         goto err_out;
2027
2028                 retried = true;
2029                 goto alloc;
2030         }
2031
2032         if (ret)
2033                 goto err_out;
2034
2035
2036         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2037                 DRM_DEBUG("Forced to use aperture for PDEs\n");
2038
2039         return 0;
2040
2041 err_out:
2042         gen6_free_scratch(vm);
2043         return ret;
2044 }
2045
2046 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2047 {
2048         return gen6_ppgtt_allocate_page_directories(ppgtt);
2049 }
2050
2051 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2052                                   uint64_t start, uint64_t length)
2053 {
2054         struct i915_page_table *unused;
2055         uint32_t pde, temp;
2056
2057         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2058                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2059 }
2060
2061 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2062 {
2063         struct drm_device *dev = ppgtt->base.dev;
2064         struct drm_i915_private *dev_priv = dev->dev_private;
2065         int ret;
2066
2067         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2068         if (IS_GEN6(dev)) {
2069                 ppgtt->switch_mm = gen6_mm_switch;
2070         } else if (IS_HASWELL(dev)) {
2071                 ppgtt->switch_mm = hsw_mm_switch;
2072         } else if (IS_GEN7(dev)) {
2073                 ppgtt->switch_mm = gen7_mm_switch;
2074         } else
2075                 BUG();
2076
2077         if (intel_vgpu_active(dev))
2078                 ppgtt->switch_mm = vgpu_mm_switch;
2079
2080         ret = gen6_ppgtt_alloc(ppgtt);
2081         if (ret)
2082                 return ret;
2083
2084         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2085         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2086         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2087         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2088         ppgtt->base.bind_vma = ppgtt_bind_vma;
2089         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2090         ppgtt->base.start = 0;
2091         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2092         ppgtt->debug_dump = gen6_dump_ppgtt;
2093
2094         ppgtt->pd.base.ggtt_offset =
2095                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2096
2097         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
2098                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2099
2100         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2101
2102         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2103
2104         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2105                          ppgtt->node.size >> 20,
2106                          ppgtt->node.start / PAGE_SIZE);
2107
2108         DRM_DEBUG("Adding PPGTT at offset %x\n",
2109                   ppgtt->pd.base.ggtt_offset << 10);
2110
2111         return 0;
2112 }
2113
2114 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2115 {
2116         ppgtt->base.dev = dev;
2117
2118         if (INTEL_INFO(dev)->gen < 8)
2119                 return gen6_ppgtt_init(ppgtt);
2120         else
2121                 return gen8_ppgtt_init(ppgtt);
2122 }
2123
2124 static void i915_address_space_init(struct i915_address_space *vm,
2125                                     struct drm_i915_private *dev_priv)
2126 {
2127         drm_mm_init(&vm->mm, vm->start, vm->total);
2128         vm->dev = dev_priv->dev;
2129         INIT_LIST_HEAD(&vm->active_list);
2130         INIT_LIST_HEAD(&vm->inactive_list);
2131         list_add_tail(&vm->global_link, &dev_priv->vm_list);
2132 }
2133
2134 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2135 {
2136         struct drm_i915_private *dev_priv = dev->dev_private;
2137         int ret = 0;
2138
2139         ret = __hw_ppgtt_init(dev, ppgtt);
2140         if (ret == 0) {
2141                 kref_init(&ppgtt->ref);
2142                 i915_address_space_init(&ppgtt->base, dev_priv);
2143         }
2144
2145         return ret;
2146 }
2147
2148 int i915_ppgtt_init_hw(struct drm_device *dev)
2149 {
2150         /* In the case of execlists, PPGTT is enabled by the context descriptor
2151          * and the PDPs are contained within the context itself.  We don't
2152          * need to do anything here. */
2153         if (i915.enable_execlists)
2154                 return 0;
2155
2156         if (!USES_PPGTT(dev))
2157                 return 0;
2158
2159         if (IS_GEN6(dev))
2160                 gen6_ppgtt_enable(dev);
2161         else if (IS_GEN7(dev))
2162                 gen7_ppgtt_enable(dev);
2163         else if (INTEL_INFO(dev)->gen >= 8)
2164                 gen8_ppgtt_enable(dev);
2165         else
2166                 MISSING_CASE(INTEL_INFO(dev)->gen);
2167
2168         return 0;
2169 }
2170
2171 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2172 {
2173         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
2174         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2175
2176         if (i915.enable_execlists)
2177                 return 0;
2178
2179         if (!ppgtt)
2180                 return 0;
2181
2182         return ppgtt->switch_mm(ppgtt, req);
2183 }
2184
2185 struct i915_hw_ppgtt *
2186 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2187 {
2188         struct i915_hw_ppgtt *ppgtt;
2189         int ret;
2190
2191         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2192         if (!ppgtt)
2193                 return ERR_PTR(-ENOMEM);
2194
2195         ret = i915_ppgtt_init(dev, ppgtt);
2196         if (ret) {
2197                 kfree(ppgtt);
2198                 return ERR_PTR(ret);
2199         }
2200
2201         ppgtt->file_priv = fpriv;
2202
2203         trace_i915_ppgtt_create(&ppgtt->base);
2204
2205         return ppgtt;
2206 }
2207
2208 void  i915_ppgtt_release(struct kref *kref)
2209 {
2210         struct i915_hw_ppgtt *ppgtt =
2211                 container_of(kref, struct i915_hw_ppgtt, ref);
2212
2213         trace_i915_ppgtt_release(&ppgtt->base);
2214
2215         /* vmas should already be unbound */
2216         WARN_ON(!list_empty(&ppgtt->base.active_list));
2217         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2218
2219         list_del(&ppgtt->base.global_link);
2220         drm_mm_takedown(&ppgtt->base.mm);
2221
2222         ppgtt->base.cleanup(&ppgtt->base);
2223         kfree(ppgtt);
2224 }
2225
2226 extern int intel_iommu_gfx_mapped;
2227 /* Certain Gen5 chipsets require require idling the GPU before
2228  * unmapping anything from the GTT when VT-d is enabled.
2229  */
2230 static bool needs_idle_maps(struct drm_device *dev)
2231 {
2232 #ifdef CONFIG_INTEL_IOMMU
2233         /* Query intel_iommu to see if we need the workaround. Presumably that
2234          * was loaded first.
2235          */
2236         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2237                 return true;
2238 #endif
2239         return false;
2240 }
2241
2242 static bool do_idling(struct drm_i915_private *dev_priv)
2243 {
2244         bool ret = dev_priv->mm.interruptible;
2245
2246         if (unlikely(dev_priv->gtt.do_idle_maps)) {
2247                 dev_priv->mm.interruptible = false;
2248                 if (i915_gpu_idle(dev_priv->dev)) {
2249                         DRM_ERROR("Couldn't idle GPU\n");
2250                         /* Wait a bit, in hopes it avoids the hang */
2251                         udelay(10);
2252                 }
2253         }
2254
2255         return ret;
2256 }
2257
2258 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2259 {
2260         if (unlikely(dev_priv->gtt.do_idle_maps))
2261                 dev_priv->mm.interruptible = interruptible;
2262 }
2263
2264 void i915_check_and_clear_faults(struct drm_device *dev)
2265 {
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct intel_engine_cs *ring;
2268         int i;
2269
2270         if (INTEL_INFO(dev)->gen < 6)
2271                 return;
2272
2273         for_each_ring(ring, dev_priv, i) {
2274                 u32 fault_reg;
2275                 fault_reg = I915_READ(RING_FAULT_REG(ring));
2276                 if (fault_reg & RING_FAULT_VALID) {
2277                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2278                                          "\tAddr: 0x%08lx\n"
2279                                          "\tAddress space: %s\n"
2280                                          "\tSource ID: %d\n"
2281                                          "\tType: %d\n",
2282                                          fault_reg & PAGE_MASK,
2283                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2284                                          RING_FAULT_SRCID(fault_reg),
2285                                          RING_FAULT_FAULT_TYPE(fault_reg));
2286                         I915_WRITE(RING_FAULT_REG(ring),
2287                                    fault_reg & ~RING_FAULT_VALID);
2288                 }
2289         }
2290         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2291 }
2292
2293 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2294 {
2295         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2296                 intel_gtt_chipset_flush();
2297         } else {
2298                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2299                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2300         }
2301 }
2302
2303 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2304 {
2305         struct drm_i915_private *dev_priv = dev->dev_private;
2306
2307         /* Don't bother messing with faults pre GEN6 as we have little
2308          * documentation supporting that it's a good idea.
2309          */
2310         if (INTEL_INFO(dev)->gen < 6)
2311                 return;
2312
2313         i915_check_and_clear_faults(dev);
2314
2315         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2316                                        dev_priv->gtt.base.start,
2317                                        dev_priv->gtt.base.total,
2318                                        true);
2319
2320         i915_ggtt_flush(dev_priv);
2321 }
2322
2323 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2324 {
2325         if (!dma_map_sg(&obj->base.dev->pdev->dev,
2326                         obj->pages->sgl, obj->pages->nents,
2327                         PCI_DMA_BIDIRECTIONAL))
2328                 return -ENOSPC;
2329
2330         return 0;
2331 }
2332
2333 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2334 {
2335 #ifdef writeq
2336         writeq(pte, addr);
2337 #else
2338         iowrite32((u32)pte, addr);
2339         iowrite32(pte >> 32, addr + 4);
2340 #endif
2341 }
2342
2343 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2344                                      struct sg_table *st,
2345                                      uint64_t start,
2346                                      enum i915_cache_level level, u32 unused)
2347 {
2348         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2349         unsigned first_entry = start >> PAGE_SHIFT;
2350         gen8_pte_t __iomem *gtt_entries =
2351                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2352         int i = 0;
2353         struct sg_page_iter sg_iter;
2354         dma_addr_t addr = 0; /* shut up gcc */
2355
2356         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2357                 addr = sg_dma_address(sg_iter.sg) +
2358                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
2359                 gen8_set_pte(&gtt_entries[i],
2360                              gen8_pte_encode(addr, level, true));
2361                 i++;
2362         }
2363
2364         /*
2365          * XXX: This serves as a posting read to make sure that the PTE has
2366          * actually been updated. There is some concern that even though
2367          * registers and PTEs are within the same BAR that they are potentially
2368          * of NUMA access patterns. Therefore, even with the way we assume
2369          * hardware should work, we must keep this posting read for paranoia.
2370          */
2371         if (i != 0)
2372                 WARN_ON(readq(&gtt_entries[i-1])
2373                         != gen8_pte_encode(addr, level, true));
2374
2375         /* This next bit makes the above posting read even more important. We
2376          * want to flush the TLBs only after we're certain all the PTE updates
2377          * have finished.
2378          */
2379         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2380         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2381 }
2382
2383 /*
2384  * Binds an object into the global gtt with the specified cache level. The object
2385  * will be accessible to the GPU via commands whose operands reference offsets
2386  * within the global GTT as well as accessible by the GPU through the GMADR
2387  * mapped BAR (dev_priv->mm.gtt->gtt).
2388  */
2389 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2390                                      struct sg_table *st,
2391                                      uint64_t start,
2392                                      enum i915_cache_level level, u32 flags)
2393 {
2394         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2395         unsigned first_entry = start >> PAGE_SHIFT;
2396         gen6_pte_t __iomem *gtt_entries =
2397                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2398         int i = 0;
2399         struct sg_page_iter sg_iter;
2400         dma_addr_t addr = 0;
2401
2402         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2403                 addr = sg_page_iter_dma_address(&sg_iter);
2404                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
2405                 i++;
2406         }
2407
2408         /* XXX: This serves as a posting read to make sure that the PTE has
2409          * actually been updated. There is some concern that even though
2410          * registers and PTEs are within the same BAR that they are potentially
2411          * of NUMA access patterns. Therefore, even with the way we assume
2412          * hardware should work, we must keep this posting read for paranoia.
2413          */
2414         if (i != 0) {
2415                 unsigned long gtt = readl(&gtt_entries[i-1]);
2416                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2417         }
2418
2419         /* This next bit makes the above posting read even more important. We
2420          * want to flush the TLBs only after we're certain all the PTE updates
2421          * have finished.
2422          */
2423         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2424         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2425 }
2426
2427 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2428                                   uint64_t start,
2429                                   uint64_t length,
2430                                   bool use_scratch)
2431 {
2432         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2433         unsigned first_entry = start >> PAGE_SHIFT;
2434         unsigned num_entries = length >> PAGE_SHIFT;
2435         gen8_pte_t scratch_pte, __iomem *gtt_base =
2436                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2437         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2438         int i;
2439
2440         if (WARN(num_entries > max_entries,
2441                  "First entry = %d; Num entries = %d (max=%d)\n",
2442                  first_entry, num_entries, max_entries))
2443                 num_entries = max_entries;
2444
2445         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2446                                       I915_CACHE_LLC,
2447                                       use_scratch);
2448         for (i = 0; i < num_entries; i++)
2449                 gen8_set_pte(&gtt_base[i], scratch_pte);
2450         readl(gtt_base);
2451 }
2452
2453 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2454                                   uint64_t start,
2455                                   uint64_t length,
2456                                   bool use_scratch)
2457 {
2458         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2459         unsigned first_entry = start >> PAGE_SHIFT;
2460         unsigned num_entries = length >> PAGE_SHIFT;
2461         gen6_pte_t scratch_pte, __iomem *gtt_base =
2462                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2463         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2464         int i;
2465
2466         if (WARN(num_entries > max_entries,
2467                  "First entry = %d; Num entries = %d (max=%d)\n",
2468                  first_entry, num_entries, max_entries))
2469                 num_entries = max_entries;
2470
2471         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2472                                      I915_CACHE_LLC, use_scratch, 0);
2473
2474         for (i = 0; i < num_entries; i++)
2475                 iowrite32(scratch_pte, &gtt_base[i]);
2476         readl(gtt_base);
2477 }
2478
2479 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2480                                      struct sg_table *pages,
2481                                      uint64_t start,
2482                                      enum i915_cache_level cache_level, u32 unused)
2483 {
2484         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2485                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2486
2487         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2488
2489 }
2490
2491 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2492                                   uint64_t start,
2493                                   uint64_t length,
2494                                   bool unused)
2495 {
2496         unsigned first_entry = start >> PAGE_SHIFT;
2497         unsigned num_entries = length >> PAGE_SHIFT;
2498         intel_gtt_clear_range(first_entry, num_entries);
2499 }
2500
2501 static int ggtt_bind_vma(struct i915_vma *vma,
2502                          enum i915_cache_level cache_level,
2503                          u32 flags)
2504 {
2505         struct drm_i915_gem_object *obj = vma->obj;
2506         u32 pte_flags = 0;
2507         int ret;
2508
2509         ret = i915_get_ggtt_vma_pages(vma);
2510         if (ret)
2511                 return ret;
2512
2513         /* Currently applicable only to VLV */
2514         if (obj->gt_ro)
2515                 pte_flags |= PTE_READ_ONLY;
2516
2517         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2518                                 vma->node.start,
2519                                 cache_level, pte_flags);
2520
2521         /*
2522          * Without aliasing PPGTT there's no difference between
2523          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2524          * upgrade to both bound if we bind either to avoid double-binding.
2525          */
2526         vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2527
2528         return 0;
2529 }
2530
2531 struct ggtt_bind_vma__cb {
2532         struct i915_vma *vma;
2533         enum i915_cache_level cache_level;
2534         u32 flags;
2535 };
2536
2537 static int ggtt_bind_vma__cb(void *_arg)
2538 {
2539         struct ggtt_bind_vma__cb *arg = _arg;
2540         return ggtt_bind_vma(arg->vma, arg->cache_level, arg->flags);
2541 }
2542
2543 static int ggtt_bind_vma__BKL(struct i915_vma *vma,
2544                               enum i915_cache_level cache_level,
2545                               u32 flags)
2546 {
2547         struct ggtt_bind_vma__cb arg = { vma, cache_level, flags };
2548         return stop_machine(ggtt_bind_vma__cb, &arg, NULL);
2549 }
2550
2551 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2552                                  enum i915_cache_level cache_level,
2553                                  u32 flags)
2554 {
2555         struct drm_device *dev = vma->vm->dev;
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         struct drm_i915_gem_object *obj = vma->obj;
2558         struct sg_table *pages = obj->pages;
2559         u32 pte_flags = 0;
2560         int ret;
2561
2562         ret = i915_get_ggtt_vma_pages(vma);
2563         if (ret)
2564                 return ret;
2565         pages = vma->ggtt_view.pages;
2566
2567         /* Currently applicable only to VLV */
2568         if (obj->gt_ro)
2569                 pte_flags |= PTE_READ_ONLY;
2570
2571
2572         if (flags & GLOBAL_BIND) {
2573                 vma->vm->insert_entries(vma->vm, pages,
2574                                         vma->node.start,
2575                                         cache_level, pte_flags);
2576         }
2577
2578         if (flags & LOCAL_BIND) {
2579                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2580                 appgtt->base.insert_entries(&appgtt->base, pages,
2581                                             vma->node.start,
2582                                             cache_level, pte_flags);
2583         }
2584
2585         return 0;
2586 }
2587
2588 static void ggtt_unbind_vma(struct i915_vma *vma)
2589 {
2590         struct drm_device *dev = vma->vm->dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct drm_i915_gem_object *obj = vma->obj;
2593         const uint64_t size = min_t(uint64_t,
2594                                     obj->base.size,
2595                                     vma->node.size);
2596
2597         if (vma->bound & GLOBAL_BIND) {
2598                 vma->vm->clear_range(vma->vm,
2599                                      vma->node.start,
2600                                      size,
2601                                      true);
2602         }
2603
2604         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2605                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2606
2607                 appgtt->base.clear_range(&appgtt->base,
2608                                          vma->node.start,
2609                                          size,
2610                                          true);
2611         }
2612 }
2613
2614 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2615 {
2616         struct drm_device *dev = obj->base.dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         bool interruptible;
2619
2620         interruptible = do_idling(dev_priv);
2621
2622         dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2623                      PCI_DMA_BIDIRECTIONAL);
2624
2625         undo_idling(dev_priv, interruptible);
2626 }
2627
2628 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2629                                   unsigned long color,
2630                                   u64 *start,
2631                                   u64 *end)
2632 {
2633         if (node->color != color)
2634                 *start += 4096;
2635
2636         if (!list_empty(&node->node_list)) {
2637                 node = list_entry(node->node_list.next,
2638                                   struct drm_mm_node,
2639                                   node_list);
2640                 if (node->allocated && node->color != color)
2641                         *end -= 4096;
2642         }
2643 }
2644
2645 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2646                                      u64 start,
2647                                      u64 mappable_end,
2648                                      u64 end)
2649 {
2650         /* Let GEM Manage all of the aperture.
2651          *
2652          * However, leave one page at the end still bound to the scratch page.
2653          * There are a number of places where the hardware apparently prefetches
2654          * past the end of the object, and we've seen multiple hangs with the
2655          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2656          * aperture.  One page should be enough to keep any prefetching inside
2657          * of the aperture.
2658          */
2659         struct drm_i915_private *dev_priv = dev->dev_private;
2660         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2661         struct drm_mm_node *entry;
2662         struct drm_i915_gem_object *obj;
2663         unsigned long hole_start, hole_end;
2664         int ret;
2665
2666         BUG_ON(mappable_end > end);
2667
2668         ggtt_vm->start = start;
2669
2670         /* Subtract the guard page before address space initialization to
2671          * shrink the range used by drm_mm */
2672         ggtt_vm->total = end - start - PAGE_SIZE;
2673         i915_address_space_init(ggtt_vm, dev_priv);
2674         ggtt_vm->total += PAGE_SIZE;
2675
2676         if (intel_vgpu_active(dev)) {
2677                 ret = intel_vgt_balloon(dev);
2678                 if (ret)
2679                         return ret;
2680         }
2681
2682         if (!HAS_LLC(dev))
2683                 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
2684
2685         /* Mark any preallocated objects as occupied */
2686         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2687                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2688
2689                 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2690                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2691
2692                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2693                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2694                 if (ret) {
2695                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2696                         return ret;
2697                 }
2698                 vma->bound |= GLOBAL_BIND;
2699                 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2700         }
2701
2702         /* Clear any non-preallocated blocks */
2703         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2704                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2705                               hole_start, hole_end);
2706                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2707                                      hole_end - hole_start, true);
2708         }
2709
2710         /* And finally clear the reserved guard page */
2711         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2712
2713         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2714                 struct i915_hw_ppgtt *ppgtt;
2715
2716                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2717                 if (!ppgtt)
2718                         return -ENOMEM;
2719
2720                 ret = __hw_ppgtt_init(dev, ppgtt);
2721                 if (ret) {
2722                         ppgtt->base.cleanup(&ppgtt->base);
2723                         kfree(ppgtt);
2724                         return ret;
2725                 }
2726
2727                 if (ppgtt->base.allocate_va_range)
2728                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2729                                                             ppgtt->base.total);
2730                 if (ret) {
2731                         ppgtt->base.cleanup(&ppgtt->base);
2732                         kfree(ppgtt);
2733                         return ret;
2734                 }
2735
2736                 ppgtt->base.clear_range(&ppgtt->base,
2737                                         ppgtt->base.start,
2738                                         ppgtt->base.total,
2739                                         true);
2740
2741                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2742                 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
2743                 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
2744         }
2745
2746         return 0;
2747 }
2748
2749 void i915_gem_init_global_gtt(struct drm_device *dev)
2750 {
2751         struct drm_i915_private *dev_priv = dev->dev_private;
2752         u64 gtt_size, mappable_size;
2753
2754         gtt_size = dev_priv->gtt.base.total;
2755         mappable_size = dev_priv->gtt.mappable_end;
2756
2757         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2758 }
2759
2760 void i915_global_gtt_cleanup(struct drm_device *dev)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         struct i915_address_space *vm = &dev_priv->gtt.base;
2764
2765         if (dev_priv->mm.aliasing_ppgtt) {
2766                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2767
2768                 ppgtt->base.cleanup(&ppgtt->base);
2769         }
2770
2771         if (drm_mm_initialized(&vm->mm)) {
2772                 if (intel_vgpu_active(dev))
2773                         intel_vgt_deballoon();
2774
2775                 drm_mm_takedown(&vm->mm);
2776                 list_del(&vm->global_link);
2777         }
2778
2779         vm->cleanup(vm);
2780 }
2781
2782 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2783 {
2784         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2785         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2786         return snb_gmch_ctl << 20;
2787 }
2788
2789 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2790 {
2791         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2792         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2793         if (bdw_gmch_ctl)
2794                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2795
2796 #ifdef CONFIG_X86_32
2797         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2798         if (bdw_gmch_ctl > 4)
2799                 bdw_gmch_ctl = 4;
2800 #endif
2801
2802         return bdw_gmch_ctl << 20;
2803 }
2804
2805 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2806 {
2807         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2808         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2809
2810         if (gmch_ctrl)
2811                 return 1 << (20 + gmch_ctrl);
2812
2813         return 0;
2814 }
2815
2816 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2817 {
2818         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2819         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2820         return snb_gmch_ctl << 25; /* 32 MB units */
2821 }
2822
2823 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2824 {
2825         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2826         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2827         return bdw_gmch_ctl << 25; /* 32 MB units */
2828 }
2829
2830 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2831 {
2832         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2833         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2834
2835         /*
2836          * 0x0  to 0x10: 32MB increments starting at 0MB
2837          * 0x11 to 0x16: 4MB increments starting at 8MB
2838          * 0x17 to 0x1d: 4MB increments start at 36MB
2839          */
2840         if (gmch_ctrl < 0x11)
2841                 return gmch_ctrl << 25;
2842         else if (gmch_ctrl < 0x17)
2843                 return (gmch_ctrl - 0x11 + 2) << 22;
2844         else
2845                 return (gmch_ctrl - 0x17 + 9) << 22;
2846 }
2847
2848 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2849 {
2850         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2851         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2852
2853         if (gen9_gmch_ctl < 0xf0)
2854                 return gen9_gmch_ctl << 25; /* 32 MB units */
2855         else
2856                 /* 4MB increments starting at 0xf0 for 4MB */
2857                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2858 }
2859
2860 static int ggtt_probe_common(struct drm_device *dev,
2861                              size_t gtt_size)
2862 {
2863         struct drm_i915_private *dev_priv = dev->dev_private;
2864         struct i915_page_scratch *scratch_page;
2865         phys_addr_t gtt_phys_addr;
2866
2867         /* For Modern GENs the PTEs and register space are split in the BAR */
2868         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2869                 (pci_resource_len(dev->pdev, 0) / 2);
2870
2871         /*
2872          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2873          * dropped. For WC mappings in general we have 64 byte burst writes
2874          * when the WC buffer is flushed, so we can't use it, but have to
2875          * resort to an uncached mapping. The WC issue is easily caught by the
2876          * readback check when writing GTT PTE entries.
2877          */
2878         if (IS_BROXTON(dev))
2879                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2880         else
2881                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2882         if (!dev_priv->gtt.gsm) {
2883                 DRM_ERROR("Failed to map the gtt page table\n");
2884                 return -ENOMEM;
2885         }
2886
2887         scratch_page = alloc_scratch_page(dev);
2888         if (IS_ERR(scratch_page)) {
2889                 DRM_ERROR("Scratch setup failed\n");
2890                 /* iounmap will also get called at remove, but meh */
2891                 iounmap(dev_priv->gtt.gsm);
2892                 return PTR_ERR(scratch_page);
2893         }
2894
2895         dev_priv->gtt.base.scratch_page = scratch_page;
2896
2897         return 0;
2898 }
2899
2900 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2901  * bits. When using advanced contexts each context stores its own PAT, but
2902  * writing this data shouldn't be harmful even in those cases. */
2903 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2904 {
2905         uint64_t pat;
2906
2907         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2908               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2909               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2910               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2911               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2912               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2913               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2914               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2915
2916         if (!USES_PPGTT(dev_priv->dev))
2917                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2918                  * so RTL will always use the value corresponding to
2919                  * pat_sel = 000".
2920                  * So let's disable cache for GGTT to avoid screen corruptions.
2921                  * MOCS still can be used though.
2922                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2923                  * before this patch, i.e. the same uncached + snooping access
2924                  * like on gen6/7 seems to be in effect.
2925                  * - So this just fixes blitter/render access. Again it looks
2926                  * like it's not just uncached access, but uncached + snooping.
2927                  * So we can still hold onto all our assumptions wrt cpu
2928                  * clflushing on LLC machines.
2929                  */
2930                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2931
2932         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2933          * write would work. */
2934         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2935         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2936 }
2937
2938 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2939 {
2940         uint64_t pat;
2941
2942         /*
2943          * Map WB on BDW to snooped on CHV.
2944          *
2945          * Only the snoop bit has meaning for CHV, the rest is
2946          * ignored.
2947          *
2948          * The hardware will never snoop for certain types of accesses:
2949          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2950          * - PPGTT page tables
2951          * - some other special cycles
2952          *
2953          * As with BDW, we also need to consider the following for GT accesses:
2954          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2955          * so RTL will always use the value corresponding to
2956          * pat_sel = 000".
2957          * Which means we must set the snoop bit in PAT entry 0
2958          * in order to keep the global status page working.
2959          */
2960         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2961               GEN8_PPAT(1, 0) |
2962               GEN8_PPAT(2, 0) |
2963               GEN8_PPAT(3, 0) |
2964               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2965               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2966               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2967               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2968
2969         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2970         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2971 }
2972
2973 static int gen8_gmch_probe(struct drm_device *dev,
2974                            u64 *gtt_total,
2975                            size_t *stolen,
2976                            phys_addr_t *mappable_base,
2977                            u64 *mappable_end)
2978 {
2979         struct drm_i915_private *dev_priv = dev->dev_private;
2980         u64 gtt_size;
2981         u16 snb_gmch_ctl;
2982         int ret;
2983
2984         /* TODO: We're not aware of mappable constraints on gen8 yet */
2985         *mappable_base = pci_resource_start(dev->pdev, 2);
2986         *mappable_end = pci_resource_len(dev->pdev, 2);
2987
2988         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2989                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2990
2991         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2992
2993         if (INTEL_INFO(dev)->gen >= 9) {
2994                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2995                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2996         } else if (IS_CHERRYVIEW(dev)) {
2997                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2998                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2999         } else {
3000                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
3001                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
3002         }
3003
3004         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3005
3006         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3007                 chv_setup_private_ppat(dev_priv);
3008         else
3009                 bdw_setup_private_ppat(dev_priv);
3010
3011         ret = ggtt_probe_common(dev, gtt_size);
3012
3013         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
3014         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
3015         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3016         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3017
3018         if (IS_CHERRYVIEW(dev))
3019                 dev_priv->gtt.base.bind_vma = ggtt_bind_vma__BKL;
3020
3021         return ret;
3022 }
3023
3024 static int gen6_gmch_probe(struct drm_device *dev,
3025                            u64 *gtt_total,
3026                            size_t *stolen,
3027                            phys_addr_t *mappable_base,
3028                            u64 *mappable_end)
3029 {
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         unsigned int gtt_size;
3032         u16 snb_gmch_ctl;
3033         int ret;
3034
3035         *mappable_base = pci_resource_start(dev->pdev, 2);
3036         *mappable_end = pci_resource_len(dev->pdev, 2);
3037
3038         /* 64/512MB is the current min/max we actually know of, but this is just
3039          * a coarse sanity check.
3040          */
3041         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
3042                 DRM_ERROR("Unknown GMADR size (%llx)\n",
3043                           dev_priv->gtt.mappable_end);
3044                 return -ENXIO;
3045         }
3046
3047         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3048                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3049         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3050
3051         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
3052
3053         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
3054         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3055
3056         ret = ggtt_probe_common(dev, gtt_size);
3057
3058         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3059         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
3060         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3061         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3062
3063         return ret;
3064 }
3065
3066 static void gen6_gmch_remove(struct i915_address_space *vm)
3067 {
3068
3069         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
3070
3071         iounmap(gtt->gsm);
3072         free_scratch_page(vm->dev, vm->scratch_page);
3073 }
3074
3075 static int i915_gmch_probe(struct drm_device *dev,
3076                            u64 *gtt_total,
3077                            size_t *stolen,
3078                            phys_addr_t *mappable_base,
3079                            u64 *mappable_end)
3080 {
3081         struct drm_i915_private *dev_priv = dev->dev_private;
3082         int ret;
3083
3084         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3085         if (!ret) {
3086                 DRM_ERROR("failed to set up gmch\n");
3087                 return -EIO;
3088         }
3089
3090         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
3091
3092         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
3093         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
3094         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
3095         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3096         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3097
3098         if (unlikely(dev_priv->gtt.do_idle_maps))
3099                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3100
3101         return 0;
3102 }
3103
3104 static void i915_gmch_remove(struct i915_address_space *vm)
3105 {
3106         intel_gmch_remove();
3107 }
3108
3109 int i915_gem_gtt_init(struct drm_device *dev)
3110 {
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112         struct i915_gtt *gtt = &dev_priv->gtt;
3113         int ret;
3114
3115         if (INTEL_INFO(dev)->gen <= 5) {
3116                 gtt->gtt_probe = i915_gmch_probe;
3117                 gtt->base.cleanup = i915_gmch_remove;
3118         } else if (INTEL_INFO(dev)->gen < 8) {
3119                 gtt->gtt_probe = gen6_gmch_probe;
3120                 gtt->base.cleanup = gen6_gmch_remove;
3121                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
3122                         gtt->base.pte_encode = iris_pte_encode;
3123                 else if (IS_HASWELL(dev))
3124                         gtt->base.pte_encode = hsw_pte_encode;
3125                 else if (IS_VALLEYVIEW(dev))
3126                         gtt->base.pte_encode = byt_pte_encode;
3127                 else if (INTEL_INFO(dev)->gen >= 7)
3128                         gtt->base.pte_encode = ivb_pte_encode;
3129                 else
3130                         gtt->base.pte_encode = snb_pte_encode;
3131         } else {
3132                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3133                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
3134         }
3135
3136         gtt->base.dev = dev;
3137
3138         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
3139                              &gtt->mappable_base, &gtt->mappable_end);
3140         if (ret)
3141                 return ret;
3142
3143         /* GMADR is the PCI mmio aperture into the global GTT. */
3144         DRM_INFO("Memory usable by graphics device = %lluM\n",
3145                  gtt->base.total >> 20);
3146         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
3147         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
3148 #ifdef CONFIG_INTEL_IOMMU
3149         if (intel_iommu_gfx_mapped)
3150                 DRM_INFO("VT-d active for gfx access\n");
3151 #endif
3152         /*
3153          * i915.enable_ppgtt is read-only, so do an early pass to validate the
3154          * user's requested state against the hardware/driver capabilities.  We
3155          * do this now so that we can print out any log messages once rather
3156          * than every time we check intel_enable_ppgtt().
3157          */
3158         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3159         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3160
3161         return 0;
3162 }
3163
3164 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3165 {
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct drm_i915_gem_object *obj;
3168         struct i915_address_space *vm;
3169         struct i915_vma *vma;
3170         bool flush;
3171
3172         i915_check_and_clear_faults(dev);
3173
3174         /* First fill our portion of the GTT with scratch pages */
3175         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3176                                        dev_priv->gtt.base.start,
3177                                        dev_priv->gtt.base.total,
3178                                        true);
3179
3180         /* Cache flush objects bound into GGTT and rebind them. */
3181         vm = &dev_priv->gtt.base;
3182         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3183                 flush = false;
3184                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3185                         if (vma->vm != vm)
3186                                 continue;
3187
3188                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
3189                                               PIN_UPDATE));
3190
3191                         flush = true;
3192                 }
3193
3194                 if (flush)
3195                         i915_gem_clflush_object(obj, obj->pin_display);
3196         }
3197
3198         if (INTEL_INFO(dev)->gen >= 8) {
3199                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3200                         chv_setup_private_ppat(dev_priv);
3201                 else
3202                         bdw_setup_private_ppat(dev_priv);
3203
3204                 return;
3205         }
3206
3207         if (USES_PPGTT(dev)) {
3208                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3209                         /* TODO: Perhaps it shouldn't be gen6 specific */
3210
3211                         struct i915_hw_ppgtt *ppgtt =
3212                                         container_of(vm, struct i915_hw_ppgtt,
3213                                                      base);
3214
3215                         if (i915_is_ggtt(vm))
3216                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3217
3218                         gen6_write_page_range(dev_priv, &ppgtt->pd,
3219                                               0, ppgtt->base.total);
3220                 }
3221         }
3222
3223         i915_ggtt_flush(dev_priv);
3224 }
3225
3226 static struct i915_vma *
3227 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3228                       struct i915_address_space *vm,
3229                       const struct i915_ggtt_view *ggtt_view)
3230 {
3231         struct i915_vma *vma;
3232
3233         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3234                 return ERR_PTR(-EINVAL);
3235
3236         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3237         if (vma == NULL)
3238                 return ERR_PTR(-ENOMEM);
3239
3240         INIT_LIST_HEAD(&vma->vma_link);
3241         INIT_LIST_HEAD(&vma->mm_list);
3242         INIT_LIST_HEAD(&vma->exec_list);
3243         vma->vm = vm;
3244         vma->obj = obj;
3245
3246         if (i915_is_ggtt(vm))
3247                 vma->ggtt_view = *ggtt_view;
3248
3249         list_add_tail(&vma->vma_link, &obj->vma_list);
3250         if (!i915_is_ggtt(vm))
3251                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3252
3253         return vma;
3254 }
3255
3256 struct i915_vma *
3257 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3258                                   struct i915_address_space *vm)
3259 {
3260         struct i915_vma *vma;
3261
3262         vma = i915_gem_obj_to_vma(obj, vm);
3263         if (!vma)
3264                 vma = __i915_gem_vma_create(obj, vm,
3265                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3266
3267         return vma;
3268 }
3269
3270 struct i915_vma *
3271 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3272                                        const struct i915_ggtt_view *view)
3273 {
3274         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
3275         struct i915_vma *vma;
3276
3277         if (WARN_ON(!view))
3278                 return ERR_PTR(-EINVAL);
3279
3280         vma = i915_gem_obj_to_ggtt_view(obj, view);
3281
3282         if (IS_ERR(vma))
3283                 return vma;
3284
3285         if (!vma)
3286                 vma = __i915_gem_vma_create(obj, ggtt, view);
3287
3288         return vma;
3289
3290 }
3291
3292 static struct scatterlist *
3293 rotate_pages(dma_addr_t *in, unsigned int offset,
3294              unsigned int width, unsigned int height,
3295              struct sg_table *st, struct scatterlist *sg)
3296 {
3297         unsigned int column, row;
3298         unsigned int src_idx;
3299
3300         if (!sg) {
3301                 st->nents = 0;
3302                 sg = st->sgl;
3303         }
3304
3305         for (column = 0; column < width; column++) {
3306                 src_idx = width * (height - 1) + column;
3307                 for (row = 0; row < height; row++) {
3308                         st->nents++;
3309                         /* We don't need the pages, but need to initialize
3310                          * the entries so the sg list can be happily traversed.
3311                          * The only thing we need are DMA addresses.
3312                          */
3313                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3314                         sg_dma_address(sg) = in[offset + src_idx];
3315                         sg_dma_len(sg) = PAGE_SIZE;
3316                         sg = sg_next(sg);
3317                         src_idx -= width;
3318                 }
3319         }
3320
3321         return sg;
3322 }
3323
3324 static struct sg_table *
3325 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3326                           struct drm_i915_gem_object *obj)
3327 {
3328         struct intel_rotation_info *rot_info = &ggtt_view->params.rotation_info;
3329         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
3330         unsigned int size_pages_uv;
3331         struct sg_page_iter sg_iter;
3332         unsigned long i;
3333         dma_addr_t *page_addr_list;
3334         struct sg_table *st;
3335         unsigned int uv_start_page;
3336         struct scatterlist *sg;
3337         int ret = -ENOMEM;
3338
3339         /* Allocate a temporary list of source pages for random access. */
3340         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3341                                        sizeof(dma_addr_t));
3342         if (!page_addr_list)
3343                 return ERR_PTR(ret);
3344
3345         /* Account for UV plane with NV12. */
3346         if (rot_info->pixel_format == DRM_FORMAT_NV12)
3347                 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3348         else
3349                 size_pages_uv = 0;
3350
3351         /* Allocate target SG list. */
3352         st = kmalloc(sizeof(*st), GFP_KERNEL);
3353         if (!st)
3354                 goto err_st_alloc;
3355
3356         ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3357         if (ret)
3358                 goto err_sg_alloc;
3359
3360         /* Populate source page list from the object. */
3361         i = 0;
3362         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3363                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3364                 i++;
3365         }
3366
3367         /* Rotate the pages. */
3368         sg = rotate_pages(page_addr_list, 0,
3369                      rot_info->width_pages, rot_info->height_pages,
3370                      st, NULL);
3371
3372         /* Append the UV plane if NV12. */
3373         if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3374                 uv_start_page = size_pages;
3375
3376                 /* Check for tile-row un-alignment. */
3377                 if (offset_in_page(rot_info->uv_offset))
3378                         uv_start_page--;
3379
3380                 rot_info->uv_start_page = uv_start_page;
3381
3382                 rotate_pages(page_addr_list, uv_start_page,
3383                              rot_info->width_pages_uv,
3384                              rot_info->height_pages_uv,
3385                              st, sg);
3386         }
3387
3388         DRM_DEBUG_KMS(
3389                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3390                       obj->base.size, rot_info->pitch, rot_info->height,
3391                       rot_info->pixel_format, rot_info->width_pages,
3392                       rot_info->height_pages, size_pages + size_pages_uv,
3393                       size_pages);
3394
3395         drm_free_large(page_addr_list);
3396
3397         return st;
3398
3399 err_sg_alloc:
3400         kfree(st);
3401 err_st_alloc:
3402         drm_free_large(page_addr_list);
3403
3404         DRM_DEBUG_KMS(
3405                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3406                       obj->base.size, ret, rot_info->pitch, rot_info->height,
3407                       rot_info->pixel_format, rot_info->width_pages,
3408                       rot_info->height_pages, size_pages + size_pages_uv,
3409                       size_pages);
3410         return ERR_PTR(ret);
3411 }
3412
3413 static struct sg_table *
3414 intel_partial_pages(const struct i915_ggtt_view *view,
3415                     struct drm_i915_gem_object *obj)
3416 {
3417         struct sg_table *st;
3418         struct scatterlist *sg;
3419         struct sg_page_iter obj_sg_iter;
3420         int ret = -ENOMEM;
3421
3422         st = kmalloc(sizeof(*st), GFP_KERNEL);
3423         if (!st)
3424                 goto err_st_alloc;
3425
3426         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3427         if (ret)
3428                 goto err_sg_alloc;
3429
3430         sg = st->sgl;
3431         st->nents = 0;
3432         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3433                 view->params.partial.offset)
3434         {
3435                 if (st->nents >= view->params.partial.size)
3436                         break;
3437
3438                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3439                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3440                 sg_dma_len(sg) = PAGE_SIZE;
3441
3442                 sg = sg_next(sg);
3443                 st->nents++;
3444         }
3445
3446         return st;
3447
3448 err_sg_alloc:
3449         kfree(st);
3450 err_st_alloc:
3451         return ERR_PTR(ret);
3452 }
3453
3454 static int
3455 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3456 {
3457         int ret = 0;
3458
3459         if (vma->ggtt_view.pages)
3460                 return 0;
3461
3462         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3463                 vma->ggtt_view.pages = vma->obj->pages;
3464         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3465                 vma->ggtt_view.pages =
3466                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
3467         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3468                 vma->ggtt_view.pages =
3469                         intel_partial_pages(&vma->ggtt_view, vma->obj);
3470         else
3471                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3472                           vma->ggtt_view.type);
3473
3474         if (!vma->ggtt_view.pages) {
3475                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3476                           vma->ggtt_view.type);
3477                 ret = -EINVAL;
3478         } else if (IS_ERR(vma->ggtt_view.pages)) {
3479                 ret = PTR_ERR(vma->ggtt_view.pages);
3480                 vma->ggtt_view.pages = NULL;
3481                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3482                           vma->ggtt_view.type, ret);
3483         }
3484
3485         return ret;
3486 }
3487
3488 /**
3489  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3490  * @vma: VMA to map
3491  * @cache_level: mapping cache level
3492  * @flags: flags like global or local mapping
3493  *
3494  * DMA addresses are taken from the scatter-gather table of this object (or of
3495  * this VMA in case of non-default GGTT views) and PTE entries set up.
3496  * Note that DMA addresses are also the only part of the SG table we care about.
3497  */
3498 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3499                   u32 flags)
3500 {
3501         int ret;
3502         u32 bind_flags;
3503
3504         if (WARN_ON(flags == 0))
3505                 return -EINVAL;
3506
3507         bind_flags = 0;
3508         if (flags & PIN_GLOBAL)
3509                 bind_flags |= GLOBAL_BIND;
3510         if (flags & PIN_USER)
3511                 bind_flags |= LOCAL_BIND;
3512
3513         if (flags & PIN_UPDATE)
3514                 bind_flags |= vma->bound;
3515         else
3516                 bind_flags &= ~vma->bound;
3517
3518         if (bind_flags == 0)
3519                 return 0;
3520
3521         if (vma->bound == 0 && vma->vm->allocate_va_range) {
3522                 trace_i915_va_alloc(vma->vm,
3523                                     vma->node.start,
3524                                     vma->node.size,
3525                                     VM_TO_TRACE_NAME(vma->vm));
3526
3527                 /* XXX: i915_vma_pin() will fix this +- hack */
3528                 vma->pin_count++;
3529                 ret = vma->vm->allocate_va_range(vma->vm,
3530                                                  vma->node.start,
3531                                                  vma->node.size);
3532                 vma->pin_count--;
3533                 if (ret)
3534                         return ret;
3535         }
3536
3537         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3538         if (ret)
3539                 return ret;
3540
3541         vma->bound |= bind_flags;
3542
3543         return 0;
3544 }
3545
3546 /**
3547  * i915_ggtt_view_size - Get the size of a GGTT view.
3548  * @obj: Object the view is of.
3549  * @view: The view in question.
3550  *
3551  * @return The size of the GGTT view in bytes.
3552  */
3553 size_t
3554 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3555                     const struct i915_ggtt_view *view)
3556 {
3557         if (view->type == I915_GGTT_VIEW_NORMAL) {
3558                 return obj->base.size;
3559         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3560                 return view->params.rotation_info.size;
3561         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3562                 return view->params.partial.size << PAGE_SHIFT;
3563         } else {
3564                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3565                 return obj->base.size;
3566         }
3567 }