drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/stop_machine.h>
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_vgpu.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: Global GTT views
  37  *
  38  * Background and previous state
  39  *
  40  * Historically objects could exists (be bound) in global GTT space only as
  41  * singular instances with a view representing all of the object's backing pages
  42  * in a linear fashion. This view will be called a normal view.
  43  *
  44  * To support multiple views of the same object, where the number of mapped
  45  * pages is not equal to the backing store, or where the layout of the pages
  46  * is not linear, concept of a GGTT view was added.
  47  *
  48  * One example of an alternative view is a stereo display driven by a single
  49  * image. In this case we would have a framebuffer looking like this
  50  * (2x2 pages):
  51  *
  52  *    12
  53  *    34
  54  *
  55  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  56  * rendering. In contrast, fed to the display engine would be an alternative
  57  * view which could look something like this:
  58  *
  59  *   1212
  60  *   3434
  61  *
  62  * In this example both the size and layout of pages in the alternative view is
  63  * different from the normal view.
  64  *
  65  * Implementation and usage
  66  *
  67  * GGTT views are implemented using VMAs and are distinguished via enum
  68  * i915_ggtt_view_type and struct i915_ggtt_view.
  69  *
  70  * A new flavour of core GEM functions which work with GGTT bound objects were
  71  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  72  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  73  * parameter encapsulating all metadata required to implement a view.
  74  *
  75  * As a helper for callers which are only interested in the normal view,
  76  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  77  * GEM API functions, the ones not taking the view parameter, are operating on,
  78  * or with the normal GGTT view.
  79  *
  80  * Code wanting to add or use a new GGTT view needs to:
  81  *
  82  * 1. Add a new enum with a suitable name.
  83  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  84  * 3. Add support to i915_get_vma_pages().
  85  *
  86  * New views are required to build a scatter-gather table from within the
  87  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  88  * exists for the lifetime of an VMA.
  89  *
  90  * Core API is designed to have copy semantics which means that passed in
  91  * struct i915_ggtt_view does not need to be persistent (left around after
  92  * calling the core API functions).
  93  *
  94  */
  95
  96 static int
  97 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  98
  99 const struct i915_ggtt_view i915_ggtt_view_normal;
 100 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 101         .type = I915_GGTT_VIEW_ROTATED
 102 };
 103
 104 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 105 {
 106         bool has_aliasing_ppgtt;
 107         bool has_full_ppgtt;
 108         bool has_full_48bit_ppgtt;
 109
 110         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 111         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 112         has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
 113
 114         if (intel_vgpu_active(dev))
 115                 has_full_ppgtt = false; /* emulation is too hard */
 116
 117         /*
 118          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 119          * execlists, the sole mechanism available to submit work.
 120          */
 121         if (INTEL_INFO(dev)->gen < 9 &&
 122             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 123                 return 0;
 124
 125         if (enable_ppgtt == 1)
 126                 return 1;
 127
 128         if (enable_ppgtt == 2 && has_full_ppgtt)
 129                 return 2;
 130
 131         if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
 132                 return 3;
 133
 134 #ifdef CONFIG_INTEL_IOMMU
 135         /* Disable ppgtt on SNB if VT-d is on. */
 136         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 137                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 138                 return 0;
 139         }
 140 #endif
 141
 142         /* Early VLV doesn't have this */
 143         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 144             dev->pdev->revision < 0xb) {
 145                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 146                 return 0;
 147         }
 148
 149         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 150                 return has_full_48bit_ppgtt ? 3 : 2;
 151         else
 152                 return has_aliasing_ppgtt ? 1 : 0;
 153 }
 154
 155 static int ppgtt_bind_vma(struct i915_vma *vma,
 156                           enum i915_cache_level cache_level,
 157                           u32 unused)
 158 {
 159         u32 pte_flags = 0;
 160
 161         /* Currently applicable only to VLV */
 162         if (vma->obj->gt_ro)
 163                 pte_flags |= PTE_READ_ONLY;
 164
 165         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 166                                 cache_level, pte_flags);
 167
 168         return 0;
 169 }
 170
 171 static void ppgtt_unbind_vma(struct i915_vma *vma)
 172 {
 173         vma->vm->clear_range(vma->vm,
 174                              vma->node.start,
 175                              vma->obj->base.size,
 176                              true);
 177 }
 178
 179 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 180                                   enum i915_cache_level level,
 181                                   bool valid)
 182 {
 183         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 184         pte |= addr;
 185
 186         switch (level) {
 187         case I915_CACHE_NONE:
 188                 pte |= PPAT_UNCACHED_INDEX;
 189                 break;
 190         case I915_CACHE_WT:
 191                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 192                 break;
 193         default:
 194                 pte |= PPAT_CACHED_INDEX;
 195                 break;
 196         }
 197
 198         return pte;
 199 }
 200
 201 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 202                                   const enum i915_cache_level level)
 203 {
 204         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 205         pde |= addr;
 206         if (level != I915_CACHE_NONE)
 207                 pde |= PPAT_CACHED_PDE_INDEX;
 208         else
 209                 pde |= PPAT_UNCACHED_INDEX;
 210         return pde;
 211 }
 212
 213 #define gen8_pdpe_encode gen8_pde_encode
 214 #define gen8_pml4e_encode gen8_pde_encode
 215
 216 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 217                                  enum i915_cache_level level,
 218                                  bool valid, u32 unused)
 219 {
 220         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 221         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 222
 223         switch (level) {
 224         case I915_CACHE_L3_LLC:
 225         case I915_CACHE_LLC:
 226                 pte |= GEN6_PTE_CACHE_LLC;
 227                 break;
 228         case I915_CACHE_NONE:
 229                 pte |= GEN6_PTE_UNCACHED;
 230                 break;
 231         default:
 232                 MISSING_CASE(level);
 233         }
 234
 235         return pte;
 236 }
 237
 238 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 239                                  enum i915_cache_level level,
 240                                  bool valid, u32 unused)
 241 {
 242         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 243         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 244
 245         switch (level) {
 246         case I915_CACHE_L3_LLC:
 247                 pte |= GEN7_PTE_CACHE_L3_LLC;
 248                 break;
 249         case I915_CACHE_LLC:
 250                 pte |= GEN6_PTE_CACHE_LLC;
 251                 break;
 252         case I915_CACHE_NONE:
 253                 pte |= GEN6_PTE_UNCACHED;
 254                 break;
 255         default:
 256                 MISSING_CASE(level);
 257         }
 258
 259         return pte;
 260 }
 261
 262 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 263                                  enum i915_cache_level level,
 264                                  bool valid, u32 flags)
 265 {
 266         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 267         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 268
 269         if (!(flags & PTE_READ_ONLY))
 270                 pte |= BYT_PTE_WRITEABLE;
 271
 272         if (level != I915_CACHE_NONE)
 273                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 274
 275         return pte;
 276 }
 277
 278 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 279                                  enum i915_cache_level level,
 280                                  bool valid, u32 unused)
 281 {
 282         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 283         pte |= HSW_PTE_ADDR_ENCODE(addr);
 284
 285         if (level != I915_CACHE_NONE)
 286                 pte |= HSW_WB_LLC_AGE3;
 287
 288         return pte;
 289 }
 290
 291 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 292                                   enum i915_cache_level level,
 293                                   bool valid, u32 unused)
 294 {
 295         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 296         pte |= HSW_PTE_ADDR_ENCODE(addr);
 297
 298         switch (level) {
 299         case I915_CACHE_NONE:
 300                 break;
 301         case I915_CACHE_WT:
 302                 pte |= HSW_WT_ELLC_LLC_AGE3;
 303                 break;
 304         default:
 305                 pte |= HSW_WB_ELLC_LLC_AGE3;
 306                 break;
 307         }
 308
 309         return pte;
 310 }
 311
 312 static int __setup_page_dma(struct drm_device *dev,
 313                             struct i915_page_dma *p, gfp_t flags)
 314 {
 315         struct device *device = &dev->pdev->dev;
 316
 317         p->page = alloc_page(flags);
 318         if (!p->page)
 319                 return -ENOMEM;
 320
 321         p->daddr = dma_map_page(device,
 322                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 323
 324         if (dma_mapping_error(device, p->daddr)) {
 325                 __free_page(p->page);
 326                 return -EINVAL;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 333 {
 334         return __setup_page_dma(dev, p, GFP_KERNEL);
 335 }
 336
 337 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 338 {
 339         if (WARN_ON(!p->page))
 340                 return;
 341
 342         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 343         __free_page(p->page);
 344         memset(p, 0, sizeof(*p));
 345 }
 346
 347 static void *kmap_page_dma(struct i915_page_dma *p)
 348 {
 349         return kmap_atomic(p->page);
 350 }
 351
 352 /* We use the flushing unmap only with ppgtt structures:
 353  * page directories, page tables and scratch pages.
 354  */
 355 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 356 {
 357         /* There are only few exceptions for gen >=6. chv and bxt.
 358          * And we are not sure about the latter so play safe for now.
 359          */
 360         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 361                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 362
 363         kunmap_atomic(vaddr);
 364 }
 365
 366 #define kmap_px(px) kmap_page_dma(px_base(px))
 367 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 368
 369 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 370 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 371 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 372 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 373
 374 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 375                           const uint64_t val)
 376 {
 377         int i;
 378         uint64_t * const vaddr = kmap_page_dma(p);
 379
 380         for (i = 0; i < 512; i++)
 381                 vaddr[i] = val;
 382
 383         kunmap_page_dma(dev, vaddr);
 384 }
 385
 386 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 387                              const uint32_t val32)
 388 {
 389         uint64_t v = val32;
 390
 391         v = v << 32 | val32;
 392
 393         fill_page_dma(dev, p, v);
 394 }
 395
 396 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 397 {
 398         struct i915_page_scratch *sp;
 399         int ret;
 400
 401         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 402         if (sp == NULL)
 403                 return ERR_PTR(-ENOMEM);
 404
 405         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 406         if (ret) {
 407                 kfree(sp);
 408                 return ERR_PTR(ret);
 409         }
 410
 411         set_pages_uc(px_page(sp), 1);
 412
 413         return sp;
 414 }
 415
 416 static void free_scratch_page(struct drm_device *dev,
 417                               struct i915_page_scratch *sp)
 418 {
 419         set_pages_wb(px_page(sp), 1);
 420
 421         cleanup_px(dev, sp);
 422         kfree(sp);
 423 }
 424
 425 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 426 {
 427         struct i915_page_table *pt;
 428         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 429                 GEN8_PTES : GEN6_PTES;
 430         int ret = -ENOMEM;
 431
 432         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 433         if (!pt)
 434                 return ERR_PTR(-ENOMEM);
 435
 436         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 437                                 GFP_KERNEL);
 438
 439         if (!pt->used_ptes)
 440                 goto fail_bitmap;
 441
 442         ret = setup_px(dev, pt);
 443         if (ret)
 444                 goto fail_page_m;
 445
 446         return pt;
 447
 448 fail_page_m:
 449         kfree(pt->used_ptes);
 450 fail_bitmap:
 451         kfree(pt);
 452
 453         return ERR_PTR(ret);
 454 }
 455
 456 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 457 {
 458         cleanup_px(dev, pt);
 459         kfree(pt->used_ptes);
 460         kfree(pt);
 461 }
 462
 463 static void gen8_initialize_pt(struct i915_address_space *vm,
 464                                struct i915_page_table *pt)
 465 {
 466         gen8_pte_t scratch_pte;
 467
 468         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 469                                       I915_CACHE_LLC, true);
 470
 471         fill_px(vm->dev, pt, scratch_pte);
 472 }
 473
 474 static void gen6_initialize_pt(struct i915_address_space *vm,
 475                                struct i915_page_table *pt)
 476 {
 477         gen6_pte_t scratch_pte;
 478
 479         WARN_ON(px_dma(vm->scratch_page) == 0);
 480
 481         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 482                                      I915_CACHE_LLC, true, 0);
 483
 484         fill32_px(vm->dev, pt, scratch_pte);
 485 }
 486
 487 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 488 {
 489         struct i915_page_directory *pd;
 490         int ret = -ENOMEM;
 491
 492         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 493         if (!pd)
 494                 return ERR_PTR(-ENOMEM);
 495
 496         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 497                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 498         if (!pd->used_pdes)
 499                 goto fail_bitmap;
 500
 501         ret = setup_px(dev, pd);
 502         if (ret)
 503                 goto fail_page_m;
 504
 505         return pd;
 506
 507 fail_page_m:
 508         kfree(pd->used_pdes);
 509 fail_bitmap:
 510         kfree(pd);
 511
 512         return ERR_PTR(ret);
 513 }
 514
 515 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 516 {
 517         if (px_page(pd)) {
 518                 cleanup_px(dev, pd);
 519                 kfree(pd->used_pdes);
 520                 kfree(pd);
 521         }
 522 }
 523
 524 static void gen8_initialize_pd(struct i915_address_space *vm,
 525                                struct i915_page_directory *pd)
 526 {
 527         gen8_pde_t scratch_pde;
 528
 529         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 530
 531         fill_px(vm->dev, pd, scratch_pde);
 532 }
 533
 534 static int __pdp_init(struct drm_device *dev,
 535                       struct i915_page_directory_pointer *pdp)
 536 {
 537         size_t pdpes = I915_PDPES_PER_PDP(dev);
 538
 539         pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
 540                                   sizeof(unsigned long),
 541                                   GFP_KERNEL);
 542         if (!pdp->used_pdpes)
 543                 return -ENOMEM;
 544
 545         pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
 546                                       GFP_KERNEL);
 547         if (!pdp->page_directory) {
 548                 kfree(pdp->used_pdpes);
 549                 /* the PDP might be the statically allocated top level. Keep it
 550                  * as clean as possible */
 551                 pdp->used_pdpes = NULL;
 552                 return -ENOMEM;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 559 {
 560         kfree(pdp->used_pdpes);
 561         kfree(pdp->page_directory);
 562         pdp->page_directory = NULL;
 563 }
 564
 565 static struct
 566 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
 567 {
 568         struct i915_page_directory_pointer *pdp;
 569         int ret = -ENOMEM;
 570
 571         WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
 572
 573         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 574         if (!pdp)
 575                 return ERR_PTR(-ENOMEM);
 576
 577         ret = __pdp_init(dev, pdp);
 578         if (ret)
 579                 goto fail_bitmap;
 580
 581         ret = setup_px(dev, pdp);
 582         if (ret)
 583                 goto fail_page_m;
 584
 585         return pdp;
 586
 587 fail_page_m:
 588         __pdp_fini(pdp);
 589 fail_bitmap:
 590         kfree(pdp);
 591
 592         return ERR_PTR(ret);
 593 }
 594
 595 static void free_pdp(struct drm_device *dev,
 596                      struct i915_page_directory_pointer *pdp)
 597 {
 598         __pdp_fini(pdp);
 599         if (USES_FULL_48BIT_PPGTT(dev)) {
 600                 cleanup_px(dev, pdp);
 601                 kfree(pdp);
 602         }
 603 }
 604
 605 static void gen8_initialize_pdp(struct i915_address_space *vm,
 606                                 struct i915_page_directory_pointer *pdp)
 607 {
 608         gen8_ppgtt_pdpe_t scratch_pdpe;
 609
 610         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 611
 612         fill_px(vm->dev, pdp, scratch_pdpe);
 613 }
 614
 615 static void gen8_initialize_pml4(struct i915_address_space *vm,
 616                                  struct i915_pml4 *pml4)
 617 {
 618         gen8_ppgtt_pml4e_t scratch_pml4e;
 619
 620         scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
 621                                           I915_CACHE_LLC);
 622
 623         fill_px(vm->dev, pml4, scratch_pml4e);
 624 }
 625
 626 static void
 627 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
 628                           struct i915_page_directory_pointer *pdp,
 629                           struct i915_page_directory *pd,
 630                           int index)
 631 {
 632         gen8_ppgtt_pdpe_t *page_directorypo;
 633
 634         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 635                 return;
 636
 637         page_directorypo = kmap_px(pdp);
 638         page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 639         kunmap_px(ppgtt, page_directorypo);
 640 }
 641
 642 static void
 643 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
 644                                   struct i915_pml4 *pml4,
 645                                   struct i915_page_directory_pointer *pdp,
 646                                   int index)
 647 {
 648         gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 649
 650         WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
 651         pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 652         kunmap_px(ppgtt, pagemap);
 653 }
 654
 655 /* Broadwell Page Directory Pointer Descriptors */
 656 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 657                           unsigned entry,
 658                           dma_addr_t addr)
 659 {
 660         struct intel_engine_cs *ring = req->ring;
 661         int ret;
 662
 663         BUG_ON(entry >= 4);
 664
 665         ret = intel_ring_begin(req, 6);
 666         if (ret)
 667                 return ret;
 668
 669         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 670         intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(ring, entry));
 671         intel_ring_emit(ring, upper_32_bits(addr));
 672         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 673         intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(ring, entry));
 674         intel_ring_emit(ring, lower_32_bits(addr));
 675         intel_ring_advance(ring);
 676
 677         return 0;
 678 }
 679
 680 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
 681                                  struct drm_i915_gem_request *req)
 682 {
 683         int i, ret;
 684
 685         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 686                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 687
 688                 ret = gen8_write_pdp(req, i, pd_daddr);
 689                 if (ret)
 690                         return ret;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
 697                               struct drm_i915_gem_request *req)
 698 {
 699         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
 700 }
 701
 702 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
 703                                        struct i915_page_directory_pointer *pdp,
 704                                        uint64_t start,
 705                                        uint64_t length,
 706                                        gen8_pte_t scratch_pte)
 707 {
 708         struct i915_hw_ppgtt *ppgtt =
 709                 container_of(vm, struct i915_hw_ppgtt, base);
 710         gen8_pte_t *pt_vaddr;
 711         unsigned pdpe = gen8_pdpe_index(start);
 712         unsigned pde = gen8_pde_index(start);
 713         unsigned pte = gen8_pte_index(start);
 714         unsigned num_entries = length >> PAGE_SHIFT;
 715         unsigned last_pte, i;
 716
 717         if (WARN_ON(!pdp))
 718                 return;
 719
 720         while (num_entries) {
 721                 struct i915_page_directory *pd;
 722                 struct i915_page_table *pt;
 723
 724                 if (WARN_ON(!pdp->page_directory[pdpe]))
 725                         break;
 726
 727                 pd = pdp->page_directory[pdpe];
 728
 729                 if (WARN_ON(!pd->page_table[pde]))
 730                         break;
 731
 732                 pt = pd->page_table[pde];
 733
 734                 if (WARN_ON(!px_page(pt)))
 735                         break;
 736
 737                 last_pte = pte + num_entries;
 738                 if (last_pte > GEN8_PTES)
 739                         last_pte = GEN8_PTES;
 740
 741                 pt_vaddr = kmap_px(pt);
 742
 743                 for (i = pte; i < last_pte; i++) {
 744                         pt_vaddr[i] = scratch_pte;
 745                         num_entries--;
 746                 }
 747
 748                 kunmap_px(ppgtt, pt);
 749
 750                 pte = 0;
 751                 if (++pde == I915_PDES) {
 752                         if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 753                                 break;
 754                         pde = 0;
 755                 }
 756         }
 757 }
 758
 759 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 760                                    uint64_t start,
 761                                    uint64_t length,
 762                                    bool use_scratch)
 763 {
 764         struct i915_hw_ppgtt *ppgtt =
 765                 container_of(vm, struct i915_hw_ppgtt, base);
 766         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 767                                                  I915_CACHE_LLC, use_scratch);
 768
 769         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 770                 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
 771                                            scratch_pte);
 772         } else {
 773                 uint64_t templ4, pml4e;
 774                 struct i915_page_directory_pointer *pdp;
 775
 776                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
 777                         gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
 778                                                    scratch_pte);
 779                 }
 780         }
 781 }
 782
 783 static void
 784 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
 785                               struct i915_page_directory_pointer *pdp,
 786                               struct sg_page_iter *sg_iter,
 787                               uint64_t start,
 788                               enum i915_cache_level cache_level)
 789 {
 790         struct i915_hw_ppgtt *ppgtt =
 791                 container_of(vm, struct i915_hw_ppgtt, base);
 792         gen8_pte_t *pt_vaddr;
 793         unsigned pdpe = gen8_pdpe_index(start);
 794         unsigned pde = gen8_pde_index(start);
 795         unsigned pte = gen8_pte_index(start);
 796
 797         pt_vaddr = NULL;
 798
 799         while (__sg_page_iter_next(sg_iter)) {
 800                 if (pt_vaddr == NULL) {
 801                         struct i915_page_directory *pd = pdp->page_directory[pdpe];
 802                         struct i915_page_table *pt = pd->page_table[pde];
 803                         pt_vaddr = kmap_px(pt);
 804                 }
 805
 806                 pt_vaddr[pte] =
 807                         gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
 808                                         cache_level, true);
 809                 if (++pte == GEN8_PTES) {
 810                         kunmap_px(ppgtt, pt_vaddr);
 811                         pt_vaddr = NULL;
 812                         if (++pde == I915_PDES) {
 813                                 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 814                                         break;
 815                                 pde = 0;
 816                         }
 817                         pte = 0;
 818                 }
 819         }
 820
 821         if (pt_vaddr)
 822                 kunmap_px(ppgtt, pt_vaddr);
 823 }
 824
 825 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 826                                       struct sg_table *pages,
 827                                       uint64_t start,
 828                                       enum i915_cache_level cache_level,
 829                                       u32 unused)
 830 {
 831         struct i915_hw_ppgtt *ppgtt =
 832                 container_of(vm, struct i915_hw_ppgtt, base);
 833         struct sg_page_iter sg_iter;
 834
 835         __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
 836
 837         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 838                 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
 839                                               cache_level);
 840         } else {
 841                 struct i915_page_directory_pointer *pdp;
 842                 uint64_t templ4, pml4e;
 843                 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
 844
 845                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
 846                         gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
 847                                                       start, cache_level);
 848                 }
 849         }
 850 }
 851
 852 static void gen8_free_page_tables(struct drm_device *dev,
 853                                   struct i915_page_directory *pd)
 854 {
 855         int i;
 856
 857         if (!px_page(pd))
 858                 return;
 859
 860         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 861                 if (WARN_ON(!pd->page_table[i]))
 862                         continue;
 863
 864                 free_pt(dev, pd->page_table[i]);
 865                 pd->page_table[i] = NULL;
 866         }
 867 }
 868
 869 static int gen8_init_scratch(struct i915_address_space *vm)
 870 {
 871         struct drm_device *dev = vm->dev;
 872
 873         vm->scratch_page = alloc_scratch_page(dev);
 874         if (IS_ERR(vm->scratch_page))
 875                 return PTR_ERR(vm->scratch_page);
 876
 877         vm->scratch_pt = alloc_pt(dev);
 878         if (IS_ERR(vm->scratch_pt)) {
 879                 free_scratch_page(dev, vm->scratch_page);
 880                 return PTR_ERR(vm->scratch_pt);
 881         }
 882
 883         vm->scratch_pd = alloc_pd(dev);
 884         if (IS_ERR(vm->scratch_pd)) {
 885                 free_pt(dev, vm->scratch_pt);
 886                 free_scratch_page(dev, vm->scratch_page);
 887                 return PTR_ERR(vm->scratch_pd);
 888         }
 889
 890         if (USES_FULL_48BIT_PPGTT(dev)) {
 891                 vm->scratch_pdp = alloc_pdp(dev);
 892                 if (IS_ERR(vm->scratch_pdp)) {
 893                         free_pd(dev, vm->scratch_pd);
 894                         free_pt(dev, vm->scratch_pt);
 895                         free_scratch_page(dev, vm->scratch_page);
 896                         return PTR_ERR(vm->scratch_pdp);
 897                 }
 898         }
 899
 900         gen8_initialize_pt(vm, vm->scratch_pt);
 901         gen8_initialize_pd(vm, vm->scratch_pd);
 902         if (USES_FULL_48BIT_PPGTT(dev))
 903                 gen8_initialize_pdp(vm, vm->scratch_pdp);
 904
 905         return 0;
 906 }
 907
 908 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
 909 {
 910         enum vgt_g2v_type msg;
 911         struct drm_device *dev = ppgtt->base.dev;
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         int i;
 914
 915         if (USES_FULL_48BIT_PPGTT(dev)) {
 916                 u64 daddr = px_dma(&ppgtt->pml4);
 917
 918                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
 919                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
 920
 921                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 922                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 923         } else {
 924                 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 925                         u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
 926
 927                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
 928                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
 929                 }
 930
 931                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 932                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
 933         }
 934
 935         I915_WRITE(vgtif_reg(g2v_notify), msg);
 936
 937         return 0;
 938 }
 939
 940 static void gen8_free_scratch(struct i915_address_space *vm)
 941 {
 942         struct drm_device *dev = vm->dev;
 943
 944         if (USES_FULL_48BIT_PPGTT(dev))
 945                 free_pdp(dev, vm->scratch_pdp);
 946         free_pd(dev, vm->scratch_pd);
 947         free_pt(dev, vm->scratch_pt);
 948         free_scratch_page(dev, vm->scratch_page);
 949 }
 950
 951 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
 952                                     struct i915_page_directory_pointer *pdp)
 953 {
 954         int i;
 955
 956         for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
 957                 if (WARN_ON(!pdp->page_directory[i]))
 958                         continue;
 959
 960                 gen8_free_page_tables(dev, pdp->page_directory[i]);
 961                 free_pd(dev, pdp->page_directory[i]);
 962         }
 963
 964         free_pdp(dev, pdp);
 965 }
 966
 967 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
 968 {
 969         int i;
 970
 971         for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
 972                 if (WARN_ON(!ppgtt->pml4.pdps[i]))
 973                         continue;
 974
 975                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
 976         }
 977
 978         cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
 979 }
 980
 981 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 982 {
 983         struct i915_hw_ppgtt *ppgtt =
 984                 container_of(vm, struct i915_hw_ppgtt, base);
 985
 986         if (intel_vgpu_active(vm->dev))
 987                 gen8_ppgtt_notify_vgt(ppgtt, false);
 988
 989         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 990                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
 991         else
 992                 gen8_ppgtt_cleanup_4lvl(ppgtt);
 993
 994         gen8_free_scratch(vm);
 995 }
 996
 997 /**
 998  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 999  * @vm: Master vm structure.
1000  * @pd: Page directory for this address range.
1001  * @start:      Starting virtual address to begin allocations.
1002  * @length:     Size of the allocations.
1003  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
1004  *              caller to free on error.
1005  *
1006  * Allocate the required number of page tables. Extremely similar to
1007  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1008  * the page directory boundary (instead of the page directory pointer). That
1009  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1010  * possible, and likely that the caller will need to use multiple calls of this
1011  * function to achieve the appropriate allocation.
1012  *
1013  * Return: 0 if success; negative error code otherwise.
1014  */
1015 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1016                                      struct i915_page_directory *pd,
1017                                      uint64_t start,
1018                                      uint64_t length,
1019                                      unsigned long *new_pts)
1020 {
1021         struct drm_device *dev = vm->dev;
1022         struct i915_page_table *pt;
1023         uint64_t temp;
1024         uint32_t pde;
1025
1026         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
1027                 /* Don't reallocate page tables */
1028                 if (test_bit(pde, pd->used_pdes)) {
1029                         /* Scratch is never allocated this way */
1030                         WARN_ON(pt == vm->scratch_pt);
1031                         continue;
1032                 }
1033
1034                 pt = alloc_pt(dev);
1035                 if (IS_ERR(pt))
1036                         goto unwind_out;
1037
1038                 gen8_initialize_pt(vm, pt);
1039                 pd->page_table[pde] = pt;
1040                 __set_bit(pde, new_pts);
1041                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1042         }
1043
1044         return 0;
1045
1046 unwind_out:
1047         for_each_set_bit(pde, new_pts, I915_PDES)
1048                 free_pt(dev, pd->page_table[pde]);
1049
1050         return -ENOMEM;
1051 }
1052
1053 /**
1054  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1055  * @vm: Master vm structure.
1056  * @pdp:        Page directory pointer for this address range.
1057  * @start:      Starting virtual address to begin allocations.
1058  * @length:     Size of the allocations.
1059  * @new_pds:    Bitmap set by function with new allocations. Likely used by the
1060  *              caller to free on error.
1061  *
1062  * Allocate the required number of page directories starting at the pde index of
1063  * @start, and ending at the pde index @start + @length. This function will skip
1064  * over already allocated page directories within the range, and only allocate
1065  * new ones, setting the appropriate pointer within the pdp as well as the
1066  * correct position in the bitmap @new_pds.
1067  *
1068  * The function will only allocate the pages within the range for a give page
1069  * directory pointer. In other words, if @start + @length straddles a virtually
1070  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1071  * required by the caller, This is not currently possible, and the BUG in the
1072  * code will prevent it.
1073  *
1074  * Return: 0 if success; negative error code otherwise.
1075  */
1076 static int
1077 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1078                                   struct i915_page_directory_pointer *pdp,
1079                                   uint64_t start,
1080                                   uint64_t length,
1081                                   unsigned long *new_pds)
1082 {
1083         struct drm_device *dev = vm->dev;
1084         struct i915_page_directory *pd;
1085         uint64_t temp;
1086         uint32_t pdpe;
1087         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1088
1089         WARN_ON(!bitmap_empty(new_pds, pdpes));
1090
1091         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1092                 if (test_bit(pdpe, pdp->used_pdpes))
1093                         continue;
1094
1095                 pd = alloc_pd(dev);
1096                 if (IS_ERR(pd))
1097                         goto unwind_out;
1098
1099                 gen8_initialize_pd(vm, pd);
1100                 pdp->page_directory[pdpe] = pd;
1101                 __set_bit(pdpe, new_pds);
1102                 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1103         }
1104
1105         return 0;
1106
1107 unwind_out:
1108         for_each_set_bit(pdpe, new_pds, pdpes)
1109                 free_pd(dev, pdp->page_directory[pdpe]);
1110
1111         return -ENOMEM;
1112 }
1113
1114 /**
1115  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1116  * @vm: Master vm structure.
1117  * @pml4:       Page map level 4 for this address range.
1118  * @start:      Starting virtual address to begin allocations.
1119  * @length:     Size of the allocations.
1120  * @new_pdps:   Bitmap set by function with new allocations. Likely used by the
1121  *              caller to free on error.
1122  *
1123  * Allocate the required number of page directory pointers. Extremely similar to
1124  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1125  * The main difference is here we are limited by the pml4 boundary (instead of
1126  * the page directory pointer).
1127  *
1128  * Return: 0 if success; negative error code otherwise.
1129  */
1130 static int
1131 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1132                                   struct i915_pml4 *pml4,
1133                                   uint64_t start,
1134                                   uint64_t length,
1135                                   unsigned long *new_pdps)
1136 {
1137         struct drm_device *dev = vm->dev;
1138         struct i915_page_directory_pointer *pdp;
1139         uint64_t temp;
1140         uint32_t pml4e;
1141
1142         WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1143
1144         gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1145                 if (!test_bit(pml4e, pml4->used_pml4es)) {
1146                         pdp = alloc_pdp(dev);
1147                         if (IS_ERR(pdp))
1148                                 goto unwind_out;
1149
1150                         gen8_initialize_pdp(vm, pdp);
1151                         pml4->pdps[pml4e] = pdp;
1152                         __set_bit(pml4e, new_pdps);
1153                         trace_i915_page_directory_pointer_entry_alloc(vm,
1154                                                                       pml4e,
1155                                                                       start,
1156                                                                       GEN8_PML4E_SHIFT);
1157                 }
1158         }
1159
1160         return 0;
1161
1162 unwind_out:
1163         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1164                 free_pdp(dev, pml4->pdps[pml4e]);
1165
1166         return -ENOMEM;
1167 }
1168
1169 static void
1170 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1171 {
1172         kfree(new_pts);
1173         kfree(new_pds);
1174 }
1175
1176 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1177  * of these are based on the number of PDPEs in the system.
1178  */
1179 static
1180 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1181                                          unsigned long **new_pts,
1182                                          uint32_t pdpes)
1183 {
1184         unsigned long *pds;
1185         unsigned long *pts;
1186
1187         pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1188         if (!pds)
1189                 return -ENOMEM;
1190
1191         pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1192                       GFP_TEMPORARY);
1193         if (!pts)
1194                 goto err_out;
1195
1196         *new_pds = pds;
1197         *new_pts = pts;
1198
1199         return 0;
1200
1201 err_out:
1202         free_gen8_temp_bitmaps(pds, pts);
1203         return -ENOMEM;
1204 }
1205
1206 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1207  * the page table structures, we mark them dirty so that
1208  * context switching/execlist queuing code takes extra steps
1209  * to ensure that tlbs are flushed.
1210  */
1211 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1212 {
1213         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1214 }
1215
1216 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1217                                     struct i915_page_directory_pointer *pdp,
1218                                     uint64_t start,
1219                                     uint64_t length)
1220 {
1221         struct i915_hw_ppgtt *ppgtt =
1222                 container_of(vm, struct i915_hw_ppgtt, base);
1223         unsigned long *new_page_dirs, *new_page_tables;
1224         struct drm_device *dev = vm->dev;
1225         struct i915_page_directory *pd;
1226         const uint64_t orig_start = start;
1227         const uint64_t orig_length = length;
1228         uint64_t temp;
1229         uint32_t pdpe;
1230         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1231         int ret;
1232
1233         /* Wrap is never okay since we can only represent 48b, and we don't
1234          * actually use the other side of the canonical address space.
1235          */
1236         if (WARN_ON(start + length < start))
1237                 return -ENODEV;
1238
1239         if (WARN_ON(start + length > vm->total))
1240                 return -ENODEV;
1241
1242         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1243         if (ret)
1244                 return ret;
1245
1246         /* Do the allocations first so we can easily bail out */
1247         ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1248                                                 new_page_dirs);
1249         if (ret) {
1250                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1251                 return ret;
1252         }
1253
1254         /* For every page directory referenced, allocate page tables */
1255         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1256                 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1257                                                 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1258                 if (ret)
1259                         goto err_out;
1260         }
1261
1262         start = orig_start;
1263         length = orig_length;
1264
1265         /* Allocations have completed successfully, so set the bitmaps, and do
1266          * the mappings. */
1267         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1268                 gen8_pde_t *const page_directory = kmap_px(pd);
1269                 struct i915_page_table *pt;
1270                 uint64_t pd_len = length;
1271                 uint64_t pd_start = start;
1272                 uint32_t pde;
1273
1274                 /* Every pd should be allocated, we just did that above. */
1275                 WARN_ON(!pd);
1276
1277                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1278                         /* Same reasoning as pd */
1279                         WARN_ON(!pt);
1280                         WARN_ON(!pd_len);
1281                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
1282
1283                         /* Set our used ptes within the page table */
1284                         bitmap_set(pt->used_ptes,
1285                                    gen8_pte_index(pd_start),
1286                                    gen8_pte_count(pd_start, pd_len));
1287
1288                         /* Our pde is now pointing to the pagetable, pt */
1289                         __set_bit(pde, pd->used_pdes);
1290
1291                         /* Map the PDE to the page table */
1292                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
1293                                                               I915_CACHE_LLC);
1294                         trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1295                                                         gen8_pte_index(start),
1296                                                         gen8_pte_count(start, length),
1297                                                         GEN8_PTES);
1298
1299                         /* NB: We haven't yet mapped ptes to pages. At this
1300                          * point we're still relying on insert_entries() */
1301                 }
1302
1303                 kunmap_px(ppgtt, page_directory);
1304                 __set_bit(pdpe, pdp->used_pdpes);
1305                 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1306         }
1307
1308         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1309         mark_tlbs_dirty(ppgtt);
1310         return 0;
1311
1312 err_out:
1313         while (pdpe--) {
1314                 for_each_set_bit(temp, new_page_tables + pdpe *
1315                                 BITS_TO_LONGS(I915_PDES), I915_PDES)
1316                         free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1317         }
1318
1319         for_each_set_bit(pdpe, new_page_dirs, pdpes)
1320                 free_pd(dev, pdp->page_directory[pdpe]);
1321
1322         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1323         mark_tlbs_dirty(ppgtt);
1324         return ret;
1325 }
1326
1327 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1328                                     struct i915_pml4 *pml4,
1329                                     uint64_t start,
1330                                     uint64_t length)
1331 {
1332         DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1333         struct i915_hw_ppgtt *ppgtt =
1334                         container_of(vm, struct i915_hw_ppgtt, base);
1335         struct i915_page_directory_pointer *pdp;
1336         uint64_t temp, pml4e;
1337         int ret = 0;
1338
1339         /* Do the pml4 allocations first, so we don't need to track the newly
1340          * allocated tables below the pdp */
1341         bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1342
1343         /* The pagedirectory and pagetable allocations are done in the shared 3
1344          * and 4 level code. Just allocate the pdps.
1345          */
1346         ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1347                                                 new_pdps);
1348         if (ret)
1349                 return ret;
1350
1351         WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1352              "The allocation has spanned more than 512GB. "
1353              "It is highly likely this is incorrect.");
1354
1355         gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1356                 WARN_ON(!pdp);
1357
1358                 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1359                 if (ret)
1360                         goto err_out;
1361
1362                 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1363         }
1364
1365         bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1366                   GEN8_PML4ES_PER_PML4);
1367
1368         return 0;
1369
1370 err_out:
1371         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1372                 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1373
1374         return ret;
1375 }
1376
1377 static int gen8_alloc_va_range(struct i915_address_space *vm,
1378                                uint64_t start, uint64_t length)
1379 {
1380         struct i915_hw_ppgtt *ppgtt =
1381                 container_of(vm, struct i915_hw_ppgtt, base);
1382
1383         if (USES_FULL_48BIT_PPGTT(vm->dev))
1384                 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1385         else
1386                 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1387 }
1388
1389 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1390                           uint64_t start, uint64_t length,
1391                           gen8_pte_t scratch_pte,
1392                           struct seq_file *m)
1393 {
1394         struct i915_page_directory *pd;
1395         uint64_t temp;
1396         uint32_t pdpe;
1397
1398         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1399                 struct i915_page_table *pt;
1400                 uint64_t pd_len = length;
1401                 uint64_t pd_start = start;
1402                 uint32_t pde;
1403
1404                 if (!test_bit(pdpe, pdp->used_pdpes))
1405                         continue;
1406
1407                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1408                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1409                         uint32_t  pte;
1410                         gen8_pte_t *pt_vaddr;
1411
1412                         if (!test_bit(pde, pd->used_pdes))
1413                                 continue;
1414
1415                         pt_vaddr = kmap_px(pt);
1416                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1417                                 uint64_t va =
1418                                         (pdpe << GEN8_PDPE_SHIFT) |
1419                                         (pde << GEN8_PDE_SHIFT) |
1420                                         (pte << GEN8_PTE_SHIFT);
1421                                 int i;
1422                                 bool found = false;
1423
1424                                 for (i = 0; i < 4; i++)
1425                                         if (pt_vaddr[pte + i] != scratch_pte)
1426                                                 found = true;
1427                                 if (!found)
1428                                         continue;
1429
1430                                 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1431                                 for (i = 0; i < 4; i++) {
1432                                         if (pt_vaddr[pte + i] != scratch_pte)
1433                                                 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1434                                         else
1435                                                 seq_puts(m, "  SCRATCH ");
1436                                 }
1437                                 seq_puts(m, "\n");
1438                         }
1439                         /* don't use kunmap_px, it could trigger
1440                          * an unnecessary flush.
1441                          */
1442                         kunmap_atomic(pt_vaddr);
1443                 }
1444         }
1445 }
1446
1447 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1448 {
1449         struct i915_address_space *vm = &ppgtt->base;
1450         uint64_t start = ppgtt->base.start;
1451         uint64_t length = ppgtt->base.total;
1452         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1453                                                  I915_CACHE_LLC, true);
1454
1455         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1456                 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1457         } else {
1458                 uint64_t templ4, pml4e;
1459                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1460                 struct i915_page_directory_pointer *pdp;
1461
1462                 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
1463                         if (!test_bit(pml4e, pml4->used_pml4es))
1464                                 continue;
1465
1466                         seq_printf(m, "    PML4E #%llu\n", pml4e);
1467                         gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1468                 }
1469         }
1470 }
1471
1472 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1473 {
1474         unsigned long *new_page_dirs, *new_page_tables;
1475         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1476         int ret;
1477
1478         /* We allocate temp bitmap for page tables for no gain
1479          * but as this is for init only, lets keep the things simple
1480          */
1481         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1482         if (ret)
1483                 return ret;
1484
1485         /* Allocate for all pdps regardless of how the ppgtt
1486          * was defined.
1487          */
1488         ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1489                                                 0, 1ULL << 32,
1490                                                 new_page_dirs);
1491         if (!ret)
1492                 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1493
1494         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1495
1496         return ret;
1497 }
1498
1499 /*
1500  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1501  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1502  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1503  * space.
1504  *
1505  */
1506 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1507 {
1508         int ret;
1509
1510         ret = gen8_init_scratch(&ppgtt->base);
1511         if (ret)
1512                 return ret;
1513
1514         ppgtt->base.start = 0;
1515         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1516         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1517         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1518         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1519         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1520         ppgtt->base.bind_vma = ppgtt_bind_vma;
1521         ppgtt->debug_dump = gen8_dump_ppgtt;
1522
1523         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1524                 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1525                 if (ret)
1526                         goto free_scratch;
1527
1528                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1529
1530                 ppgtt->base.total = 1ULL << 48;
1531                 ppgtt->switch_mm = gen8_48b_mm_switch;
1532         } else {
1533                 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1534                 if (ret)
1535                         goto free_scratch;
1536
1537                 ppgtt->base.total = 1ULL << 32;
1538                 ppgtt->switch_mm = gen8_legacy_mm_switch;
1539                 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1540                                                               0, 0,
1541                                                               GEN8_PML4E_SHIFT);
1542
1543                 if (intel_vgpu_active(ppgtt->base.dev)) {
1544                         ret = gen8_preallocate_top_level_pdps(ppgtt);
1545                         if (ret)
1546                                 goto free_scratch;
1547                 }
1548         }
1549
1550         if (intel_vgpu_active(ppgtt->base.dev))
1551                 gen8_ppgtt_notify_vgt(ppgtt, true);
1552
1553         return 0;
1554
1555 free_scratch:
1556         gen8_free_scratch(&ppgtt->base);
1557         return ret;
1558 }
1559
1560 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1561 {
1562         struct i915_address_space *vm = &ppgtt->base;
1563         struct i915_page_table *unused;
1564         gen6_pte_t scratch_pte;
1565         uint32_t pd_entry;
1566         uint32_t  pte, pde, temp;
1567         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1568
1569         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1570                                      I915_CACHE_LLC, true, 0);
1571
1572         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1573                 u32 expected;
1574                 gen6_pte_t *pt_vaddr;
1575                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1576                 pd_entry = readl(ppgtt->pd_addr + pde);
1577                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1578
1579                 if (pd_entry != expected)
1580                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1581                                    pde,
1582                                    pd_entry,
1583                                    expected);
1584                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1585
1586                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1587
1588                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1589                         unsigned long va =
1590                                 (pde * PAGE_SIZE * GEN6_PTES) +
1591                                 (pte * PAGE_SIZE);
1592                         int i;
1593                         bool found = false;
1594                         for (i = 0; i < 4; i++)
1595                                 if (pt_vaddr[pte + i] != scratch_pte)
1596                                         found = true;
1597                         if (!found)
1598                                 continue;
1599
1600                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1601                         for (i = 0; i < 4; i++) {
1602                                 if (pt_vaddr[pte + i] != scratch_pte)
1603                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1604                                 else
1605                                         seq_puts(m, "  SCRATCH ");
1606                         }
1607                         seq_puts(m, "\n");
1608                 }
1609                 kunmap_px(ppgtt, pt_vaddr);
1610         }
1611 }
1612
1613 /* Write pde (index) from the page directory @pd to the page table @pt */
1614 static void gen6_write_pde(struct i915_page_directory *pd,
1615                             const int pde, struct i915_page_table *pt)
1616 {
1617         /* Caller needs to make sure the write completes if necessary */
1618         struct i915_hw_ppgtt *ppgtt =
1619                 container_of(pd, struct i915_hw_ppgtt, pd);
1620         u32 pd_entry;
1621
1622         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1623         pd_entry |= GEN6_PDE_VALID;
1624
1625         writel(pd_entry, ppgtt->pd_addr + pde);
1626 }
1627
1628 /* Write all the page tables found in the ppgtt structure to incrementing page
1629  * directories. */
1630 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1631                                   struct i915_page_directory *pd,
1632                                   uint32_t start, uint32_t length)
1633 {
1634         struct i915_page_table *pt;
1635         uint32_t pde, temp;
1636
1637         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1638                 gen6_write_pde(pd, pde, pt);
1639
1640         /* Make sure write is complete before other code can use this page
1641          * table. Also require for WC mapped PTEs */
1642         readl(dev_priv->gtt.gsm);
1643 }
1644
1645 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1646 {
1647         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1648
1649         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1650 }
1651
1652 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1653                          struct drm_i915_gem_request *req)
1654 {
1655         struct intel_engine_cs *ring = req->ring;
1656         int ret;
1657
1658         /* NB: TLBs must be flushed and invalidated before a switch */
1659         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1660         if (ret)
1661                 return ret;
1662
1663         ret = intel_ring_begin(req, 6);
1664         if (ret)
1665                 return ret;
1666
1667         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1668         intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
1669         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1670         intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
1671         intel_ring_emit(ring, get_pd_offset(ppgtt));
1672         intel_ring_emit(ring, MI_NOOP);
1673         intel_ring_advance(ring);
1674
1675         return 0;
1676 }
1677
1678 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1679                           struct drm_i915_gem_request *req)
1680 {
1681         struct intel_engine_cs *ring = req->ring;
1682         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1683
1684         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1685         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1686         return 0;
1687 }
1688
1689 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1690                           struct drm_i915_gem_request *req)
1691 {
1692         struct intel_engine_cs *ring = req->ring;
1693         int ret;
1694
1695         /* NB: TLBs must be flushed and invalidated before a switch */
1696         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1697         if (ret)
1698                 return ret;
1699
1700         ret = intel_ring_begin(req, 6);
1701         if (ret)
1702                 return ret;
1703
1704         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1705         intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
1706         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1707         intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
1708         intel_ring_emit(ring, get_pd_offset(ppgtt));
1709         intel_ring_emit(ring, MI_NOOP);
1710         intel_ring_advance(ring);
1711
1712         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1713         if (ring->id != RCS) {
1714                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1715                 if (ret)
1716                         return ret;
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1723                           struct drm_i915_gem_request *req)
1724 {
1725         struct intel_engine_cs *ring = req->ring;
1726         struct drm_device *dev = ppgtt->base.dev;
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729
1730         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1731         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1732
1733         POSTING_READ(RING_PP_DIR_DCLV(ring));
1734
1735         return 0;
1736 }
1737
1738 static void gen8_ppgtt_enable(struct drm_device *dev)
1739 {
1740         struct drm_i915_private *dev_priv = dev->dev_private;
1741         struct intel_engine_cs *ring;
1742         int j;
1743
1744         for_each_ring(ring, dev_priv, j) {
1745                 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1746                 I915_WRITE(RING_MODE_GEN7(ring),
1747                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1748         }
1749 }
1750
1751 static void gen7_ppgtt_enable(struct drm_device *dev)
1752 {
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         struct intel_engine_cs *ring;
1755         uint32_t ecochk, ecobits;
1756         int i;
1757
1758         ecobits = I915_READ(GAC_ECO_BITS);
1759         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1760
1761         ecochk = I915_READ(GAM_ECOCHK);
1762         if (IS_HASWELL(dev)) {
1763                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1764         } else {
1765                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1766                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1767         }
1768         I915_WRITE(GAM_ECOCHK, ecochk);
1769
1770         for_each_ring(ring, dev_priv, i) {
1771                 /* GFX_MODE is per-ring on gen7+ */
1772                 I915_WRITE(RING_MODE_GEN7(ring),
1773                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1774         }
1775 }
1776
1777 static void gen6_ppgtt_enable(struct drm_device *dev)
1778 {
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         uint32_t ecochk, gab_ctl, ecobits;
1781
1782         ecobits = I915_READ(GAC_ECO_BITS);
1783         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1784                    ECOBITS_PPGTT_CACHE64B);
1785
1786         gab_ctl = I915_READ(GAB_CTL);
1787         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1788
1789         ecochk = I915_READ(GAM_ECOCHK);
1790         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1791
1792         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1793 }
1794
1795 /* PPGTT support for Sandybdrige/Gen6 and later */
1796 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1797                                    uint64_t start,
1798                                    uint64_t length,
1799                                    bool use_scratch)
1800 {
1801         struct i915_hw_ppgtt *ppgtt =
1802                 container_of(vm, struct i915_hw_ppgtt, base);
1803         gen6_pte_t *pt_vaddr, scratch_pte;
1804         unsigned first_entry = start >> PAGE_SHIFT;
1805         unsigned num_entries = length >> PAGE_SHIFT;
1806         unsigned act_pt = first_entry / GEN6_PTES;
1807         unsigned first_pte = first_entry % GEN6_PTES;
1808         unsigned last_pte, i;
1809
1810         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1811                                      I915_CACHE_LLC, true, 0);
1812
1813         while (num_entries) {
1814                 last_pte = first_pte + num_entries;
1815                 if (last_pte > GEN6_PTES)
1816                         last_pte = GEN6_PTES;
1817
1818                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1819
1820                 for (i = first_pte; i < last_pte; i++)
1821                         pt_vaddr[i] = scratch_pte;
1822
1823                 kunmap_px(ppgtt, pt_vaddr);
1824
1825                 num_entries -= last_pte - first_pte;
1826                 first_pte = 0;
1827                 act_pt++;
1828         }
1829 }
1830
1831 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1832                                       struct sg_table *pages,
1833                                       uint64_t start,
1834                                       enum i915_cache_level cache_level, u32 flags)
1835 {
1836         struct i915_hw_ppgtt *ppgtt =
1837                 container_of(vm, struct i915_hw_ppgtt, base);
1838         gen6_pte_t *pt_vaddr;
1839         unsigned first_entry = start >> PAGE_SHIFT;
1840         unsigned act_pt = first_entry / GEN6_PTES;
1841         unsigned act_pte = first_entry % GEN6_PTES;
1842         struct sg_page_iter sg_iter;
1843
1844         pt_vaddr = NULL;
1845         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1846                 if (pt_vaddr == NULL)
1847                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1848
1849                 pt_vaddr[act_pte] =
1850                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1851                                        cache_level, true, flags);
1852
1853                 if (++act_pte == GEN6_PTES) {
1854                         kunmap_px(ppgtt, pt_vaddr);
1855                         pt_vaddr = NULL;
1856                         act_pt++;
1857                         act_pte = 0;
1858                 }
1859         }
1860         if (pt_vaddr)
1861                 kunmap_px(ppgtt, pt_vaddr);
1862 }
1863
1864 static int gen6_alloc_va_range(struct i915_address_space *vm,
1865                                uint64_t start_in, uint64_t length_in)
1866 {
1867         DECLARE_BITMAP(new_page_tables, I915_PDES);
1868         struct drm_device *dev = vm->dev;
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870         struct i915_hw_ppgtt *ppgtt =
1871                                 container_of(vm, struct i915_hw_ppgtt, base);
1872         struct i915_page_table *pt;
1873         uint32_t start, length, start_save, length_save;
1874         uint32_t pde, temp;
1875         int ret;
1876
1877         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1878                 return -ENODEV;
1879
1880         start = start_save = start_in;
1881         length = length_save = length_in;
1882
1883         bitmap_zero(new_page_tables, I915_PDES);
1884
1885         /* The allocation is done in two stages so that we can bail out with
1886          * minimal amount of pain. The first stage finds new page tables that
1887          * need allocation. The second stage marks use ptes within the page
1888          * tables.
1889          */
1890         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1891                 if (pt != vm->scratch_pt) {
1892                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1893                         continue;
1894                 }
1895
1896                 /* We've already allocated a page table */
1897                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1898
1899                 pt = alloc_pt(dev);
1900                 if (IS_ERR(pt)) {
1901                         ret = PTR_ERR(pt);
1902                         goto unwind_out;
1903                 }
1904
1905                 gen6_initialize_pt(vm, pt);
1906
1907                 ppgtt->pd.page_table[pde] = pt;
1908                 __set_bit(pde, new_page_tables);
1909                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1910         }
1911
1912         start = start_save;
1913         length = length_save;
1914
1915         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1916                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1917
1918                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1919                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1920                            gen6_pte_count(start, length));
1921
1922                 if (__test_and_clear_bit(pde, new_page_tables))
1923                         gen6_write_pde(&ppgtt->pd, pde, pt);
1924
1925                 trace_i915_page_table_entry_map(vm, pde, pt,
1926                                          gen6_pte_index(start),
1927                                          gen6_pte_count(start, length),
1928                                          GEN6_PTES);
1929                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1930                                 GEN6_PTES);
1931         }
1932
1933         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1934
1935         /* Make sure write is complete before other code can use this page
1936          * table. Also require for WC mapped PTEs */
1937         readl(dev_priv->gtt.gsm);
1938
1939         mark_tlbs_dirty(ppgtt);
1940         return 0;
1941
1942 unwind_out:
1943         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1944                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1945
1946                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1947                 free_pt(vm->dev, pt);
1948         }
1949
1950         mark_tlbs_dirty(ppgtt);
1951         return ret;
1952 }
1953
1954 static int gen6_init_scratch(struct i915_address_space *vm)
1955 {
1956         struct drm_device *dev = vm->dev;
1957
1958         vm->scratch_page = alloc_scratch_page(dev);
1959         if (IS_ERR(vm->scratch_page))
1960                 return PTR_ERR(vm->scratch_page);
1961
1962         vm->scratch_pt = alloc_pt(dev);
1963         if (IS_ERR(vm->scratch_pt)) {
1964                 free_scratch_page(dev, vm->scratch_page);
1965                 return PTR_ERR(vm->scratch_pt);
1966         }
1967
1968         gen6_initialize_pt(vm, vm->scratch_pt);
1969
1970         return 0;
1971 }
1972
1973 static void gen6_free_scratch(struct i915_address_space *vm)
1974 {
1975         struct drm_device *dev = vm->dev;
1976
1977         free_pt(dev, vm->scratch_pt);
1978         free_scratch_page(dev, vm->scratch_page);
1979 }
1980
1981 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1982 {
1983         struct i915_hw_ppgtt *ppgtt =
1984                 container_of(vm, struct i915_hw_ppgtt, base);
1985         struct i915_page_table *pt;
1986         uint32_t pde;
1987
1988         drm_mm_remove_node(&ppgtt->node);
1989
1990         gen6_for_all_pdes(pt, ppgtt, pde) {
1991                 if (pt != vm->scratch_pt)
1992                         free_pt(ppgtt->base.dev, pt);
1993         }
1994
1995         gen6_free_scratch(vm);
1996 }
1997
1998 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1999 {
2000         struct i915_address_space *vm = &ppgtt->base;
2001         struct drm_device *dev = ppgtt->base.dev;
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003         bool retried = false;
2004         int ret;
2005
2006         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2007          * allocator works in address space sizes, so it's multiplied by page
2008          * size. We allocate at the top of the GTT to avoid fragmentation.
2009          */
2010         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
2011
2012         ret = gen6_init_scratch(vm);
2013         if (ret)
2014                 return ret;
2015
2016 alloc:
2017         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2018                                                   &ppgtt->node, GEN6_PD_SIZE,
2019                                                   GEN6_PD_ALIGN, 0,
2020                                                   0, dev_priv->gtt.base.total,
2021                                                   DRM_MM_TOPDOWN);
2022         if (ret == -ENOSPC && !retried) {
2023                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2024                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
2025                                                I915_CACHE_NONE,
2026                                                0, dev_priv->gtt.base.total,
2027                                                0);
2028                 if (ret)
2029                         goto err_out;
2030
2031                 retried = true;
2032                 goto alloc;
2033         }
2034
2035         if (ret)
2036                 goto err_out;
2037
2038
2039         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2040                 DRM_DEBUG("Forced to use aperture for PDEs\n");
2041
2042         return 0;
2043
2044 err_out:
2045         gen6_free_scratch(vm);
2046         return ret;
2047 }
2048
2049 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2050 {
2051         return gen6_ppgtt_allocate_page_directories(ppgtt);
2052 }
2053
2054 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2055                                   uint64_t start, uint64_t length)
2056 {
2057         struct i915_page_table *unused;
2058         uint32_t pde, temp;
2059
2060         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2061                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2062 }
2063
2064 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2065 {
2066         struct drm_device *dev = ppgtt->base.dev;
2067         struct drm_i915_private *dev_priv = dev->dev_private;
2068         int ret;
2069
2070         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2071         if (IS_GEN6(dev)) {
2072                 ppgtt->switch_mm = gen6_mm_switch;
2073         } else if (IS_HASWELL(dev)) {
2074                 ppgtt->switch_mm = hsw_mm_switch;
2075         } else if (IS_GEN7(dev)) {
2076                 ppgtt->switch_mm = gen7_mm_switch;
2077         } else
2078                 BUG();
2079
2080         if (intel_vgpu_active(dev))
2081                 ppgtt->switch_mm = vgpu_mm_switch;
2082
2083         ret = gen6_ppgtt_alloc(ppgtt);
2084         if (ret)
2085                 return ret;
2086
2087         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2088         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2089         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2090         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2091         ppgtt->base.bind_vma = ppgtt_bind_vma;
2092         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2093         ppgtt->base.start = 0;
2094         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2095         ppgtt->debug_dump = gen6_dump_ppgtt;
2096
2097         ppgtt->pd.base.ggtt_offset =
2098                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2099
2100         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
2101                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2102
2103         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2104
2105         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2106
2107         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2108                          ppgtt->node.size >> 20,
2109                          ppgtt->node.start / PAGE_SIZE);
2110
2111         DRM_DEBUG("Adding PPGTT at offset %x\n",
2112                   ppgtt->pd.base.ggtt_offset << 10);
2113
2114         return 0;
2115 }
2116
2117 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2118 {
2119         ppgtt->base.dev = dev;
2120
2121         if (INTEL_INFO(dev)->gen < 8)
2122                 return gen6_ppgtt_init(ppgtt);
2123         else
2124                 return gen8_ppgtt_init(ppgtt);
2125 }
2126
2127 static void i915_address_space_init(struct i915_address_space *vm,
2128                                     struct drm_i915_private *dev_priv)
2129 {
2130         drm_mm_init(&vm->mm, vm->start, vm->total);
2131         vm->dev = dev_priv->dev;
2132         INIT_LIST_HEAD(&vm->active_list);
2133         INIT_LIST_HEAD(&vm->inactive_list);
2134         list_add_tail(&vm->global_link, &dev_priv->vm_list);
2135 }
2136
2137 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2138 {
2139         struct drm_i915_private *dev_priv = dev->dev_private;
2140         int ret = 0;
2141
2142         ret = __hw_ppgtt_init(dev, ppgtt);
2143         if (ret == 0) {
2144                 kref_init(&ppgtt->ref);
2145                 i915_address_space_init(&ppgtt->base, dev_priv);
2146         }
2147
2148         return ret;
2149 }
2150
2151 int i915_ppgtt_init_hw(struct drm_device *dev)
2152 {
2153         /* In the case of execlists, PPGTT is enabled by the context descriptor
2154          * and the PDPs are contained within the context itself.  We don't
2155          * need to do anything here. */
2156         if (i915.enable_execlists)
2157                 return 0;
2158
2159         if (!USES_PPGTT(dev))
2160                 return 0;
2161
2162         if (IS_GEN6(dev))
2163                 gen6_ppgtt_enable(dev);
2164         else if (IS_GEN7(dev))
2165                 gen7_ppgtt_enable(dev);
2166         else if (INTEL_INFO(dev)->gen >= 8)
2167                 gen8_ppgtt_enable(dev);
2168         else
2169                 MISSING_CASE(INTEL_INFO(dev)->gen);
2170
2171         return 0;
2172 }
2173
2174 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2175 {
2176         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
2177         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2178
2179         if (i915.enable_execlists)
2180                 return 0;
2181
2182         if (!ppgtt)
2183                 return 0;
2184
2185         return ppgtt->switch_mm(ppgtt, req);
2186 }
2187
2188 struct i915_hw_ppgtt *
2189 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2190 {
2191         struct i915_hw_ppgtt *ppgtt;
2192         int ret;
2193
2194         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2195         if (!ppgtt)
2196                 return ERR_PTR(-ENOMEM);
2197
2198         ret = i915_ppgtt_init(dev, ppgtt);
2199         if (ret) {
2200                 kfree(ppgtt);
2201                 return ERR_PTR(ret);
2202         }
2203
2204         ppgtt->file_priv = fpriv;
2205
2206         trace_i915_ppgtt_create(&ppgtt->base);
2207
2208         return ppgtt;
2209 }
2210
2211 void  i915_ppgtt_release(struct kref *kref)
2212 {
2213         struct i915_hw_ppgtt *ppgtt =
2214                 container_of(kref, struct i915_hw_ppgtt, ref);
2215
2216         trace_i915_ppgtt_release(&ppgtt->base);
2217
2218         /* vmas should already be unbound */
2219         WARN_ON(!list_empty(&ppgtt->base.active_list));
2220         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2221
2222         list_del(&ppgtt->base.global_link);
2223         drm_mm_takedown(&ppgtt->base.mm);
2224
2225         ppgtt->base.cleanup(&ppgtt->base);
2226         kfree(ppgtt);
2227 }
2228
2229 extern int intel_iommu_gfx_mapped;
2230 /* Certain Gen5 chipsets require require idling the GPU before
2231  * unmapping anything from the GTT when VT-d is enabled.
2232  */
2233 static bool needs_idle_maps(struct drm_device *dev)
2234 {
2235 #ifdef CONFIG_INTEL_IOMMU
2236         /* Query intel_iommu to see if we need the workaround. Presumably that
2237          * was loaded first.
2238          */
2239         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2240                 return true;
2241 #endif
2242         return false;
2243 }
2244
2245 static bool do_idling(struct drm_i915_private *dev_priv)
2246 {
2247         bool ret = dev_priv->mm.interruptible;
2248
2249         if (unlikely(dev_priv->gtt.do_idle_maps)) {
2250                 dev_priv->mm.interruptible = false;
2251                 if (i915_gpu_idle(dev_priv->dev)) {
2252                         DRM_ERROR("Couldn't idle GPU\n");
2253                         /* Wait a bit, in hopes it avoids the hang */
2254                         udelay(10);
2255                 }
2256         }
2257
2258         return ret;
2259 }
2260
2261 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2262 {
2263         if (unlikely(dev_priv->gtt.do_idle_maps))
2264                 dev_priv->mm.interruptible = interruptible;
2265 }
2266
2267 void i915_check_and_clear_faults(struct drm_device *dev)
2268 {
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         struct intel_engine_cs *ring;
2271         int i;
2272
2273         if (INTEL_INFO(dev)->gen < 6)
2274                 return;
2275
2276         for_each_ring(ring, dev_priv, i) {
2277                 u32 fault_reg;
2278                 fault_reg = I915_READ(RING_FAULT_REG(ring));
2279                 if (fault_reg & RING_FAULT_VALID) {
2280                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2281                                          "\tAddr: 0x%08lx\n"
2282                                          "\tAddress space: %s\n"
2283                                          "\tSource ID: %d\n"
2284                                          "\tType: %d\n",
2285                                          fault_reg & PAGE_MASK,
2286                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2287                                          RING_FAULT_SRCID(fault_reg),
2288                                          RING_FAULT_FAULT_TYPE(fault_reg));
2289                         I915_WRITE(RING_FAULT_REG(ring),
2290                                    fault_reg & ~RING_FAULT_VALID);
2291                 }
2292         }
2293         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2294 }
2295
2296 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2297 {
2298         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2299                 intel_gtt_chipset_flush();
2300         } else {
2301                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2302                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2303         }
2304 }
2305
2306 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2307 {
2308         struct drm_i915_private *dev_priv = dev->dev_private;
2309
2310         /* Don't bother messing with faults pre GEN6 as we have little
2311          * documentation supporting that it's a good idea.
2312          */
2313         if (INTEL_INFO(dev)->gen < 6)
2314                 return;
2315
2316         i915_check_and_clear_faults(dev);
2317
2318         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2319                                        dev_priv->gtt.base.start,
2320                                        dev_priv->gtt.base.total,
2321                                        true);
2322
2323         i915_ggtt_flush(dev_priv);
2324 }
2325
2326 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2327 {
2328         if (!dma_map_sg(&obj->base.dev->pdev->dev,
2329                         obj->pages->sgl, obj->pages->nents,
2330                         PCI_DMA_BIDIRECTIONAL))
2331                 return -ENOSPC;
2332
2333         return 0;
2334 }
2335
2336 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2337 {
2338 #ifdef writeq
2339         writeq(pte, addr);
2340 #else
2341         iowrite32((u32)pte, addr);
2342         iowrite32(pte >> 32, addr + 4);
2343 #endif
2344 }
2345
2346 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2347                                      struct sg_table *st,
2348                                      uint64_t start,
2349                                      enum i915_cache_level level, u32 unused)
2350 {
2351         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2352         unsigned first_entry = start >> PAGE_SHIFT;
2353         gen8_pte_t __iomem *gtt_entries =
2354                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2355         int i = 0;
2356         struct sg_page_iter sg_iter;
2357         dma_addr_t addr = 0; /* shut up gcc */
2358
2359         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2360                 addr = sg_dma_address(sg_iter.sg) +
2361                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
2362                 gen8_set_pte(&gtt_entries[i],
2363                              gen8_pte_encode(addr, level, true));
2364                 i++;
2365         }
2366
2367         /*
2368          * XXX: This serves as a posting read to make sure that the PTE has
2369          * actually been updated. There is some concern that even though
2370          * registers and PTEs are within the same BAR that they are potentially
2371          * of NUMA access patterns. Therefore, even with the way we assume
2372          * hardware should work, we must keep this posting read for paranoia.
2373          */
2374         if (i != 0)
2375                 WARN_ON(readq(&gtt_entries[i-1])
2376                         != gen8_pte_encode(addr, level, true));
2377
2378         /* This next bit makes the above posting read even more important. We
2379          * want to flush the TLBs only after we're certain all the PTE updates
2380          * have finished.
2381          */
2382         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2383         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2384 }
2385
2386 /*
2387  * Binds an object into the global gtt with the specified cache level. The object
2388  * will be accessible to the GPU via commands whose operands reference offsets
2389  * within the global GTT as well as accessible by the GPU through the GMADR
2390  * mapped BAR (dev_priv->mm.gtt->gtt).
2391  */
2392 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2393                                      struct sg_table *st,
2394                                      uint64_t start,
2395                                      enum i915_cache_level level, u32 flags)
2396 {
2397         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2398         unsigned first_entry = start >> PAGE_SHIFT;
2399         gen6_pte_t __iomem *gtt_entries =
2400                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2401         int i = 0;
2402         struct sg_page_iter sg_iter;
2403         dma_addr_t addr = 0;
2404
2405         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2406                 addr = sg_page_iter_dma_address(&sg_iter);
2407                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
2408                 i++;
2409         }
2410
2411         /* XXX: This serves as a posting read to make sure that the PTE has
2412          * actually been updated. There is some concern that even though
2413          * registers and PTEs are within the same BAR that they are potentially
2414          * of NUMA access patterns. Therefore, even with the way we assume
2415          * hardware should work, we must keep this posting read for paranoia.
2416          */
2417         if (i != 0) {
2418                 unsigned long gtt = readl(&gtt_entries[i-1]);
2419                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2420         }
2421
2422         /* This next bit makes the above posting read even more important. We
2423          * want to flush the TLBs only after we're certain all the PTE updates
2424          * have finished.
2425          */
2426         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2427         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2428 }
2429
2430 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2431                                   uint64_t start,
2432                                   uint64_t length,
2433                                   bool use_scratch)
2434 {
2435         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2436         unsigned first_entry = start >> PAGE_SHIFT;
2437         unsigned num_entries = length >> PAGE_SHIFT;
2438         gen8_pte_t scratch_pte, __iomem *gtt_base =
2439                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2440         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2441         int i;
2442
2443         if (WARN(num_entries > max_entries,
2444                  "First entry = %d; Num entries = %d (max=%d)\n",
2445                  first_entry, num_entries, max_entries))
2446                 num_entries = max_entries;
2447
2448         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2449                                       I915_CACHE_LLC,
2450                                       use_scratch);
2451         for (i = 0; i < num_entries; i++)
2452                 gen8_set_pte(&gtt_base[i], scratch_pte);
2453         readl(gtt_base);
2454 }
2455
2456 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2457                                   uint64_t start,
2458                                   uint64_t length,
2459                                   bool use_scratch)
2460 {
2461         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2462         unsigned first_entry = start >> PAGE_SHIFT;
2463         unsigned num_entries = length >> PAGE_SHIFT;
2464         gen6_pte_t scratch_pte, __iomem *gtt_base =
2465                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2466         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2467         int i;
2468
2469         if (WARN(num_entries > max_entries,
2470                  "First entry = %d; Num entries = %d (max=%d)\n",
2471                  first_entry, num_entries, max_entries))
2472                 num_entries = max_entries;
2473
2474         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2475                                      I915_CACHE_LLC, use_scratch, 0);
2476
2477         for (i = 0; i < num_entries; i++)
2478                 iowrite32(scratch_pte, &gtt_base[i]);
2479         readl(gtt_base);
2480 }
2481
2482 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2483                                      struct sg_table *pages,
2484                                      uint64_t start,
2485                                      enum i915_cache_level cache_level, u32 unused)
2486 {
2487         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2488                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2489
2490         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2491
2492 }
2493
2494 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2495                                   uint64_t start,
2496                                   uint64_t length,
2497                                   bool unused)
2498 {
2499         unsigned first_entry = start >> PAGE_SHIFT;
2500         unsigned num_entries = length >> PAGE_SHIFT;
2501         intel_gtt_clear_range(first_entry, num_entries);
2502 }
2503
2504 static int ggtt_bind_vma(struct i915_vma *vma,
2505                          enum i915_cache_level cache_level,
2506                          u32 flags)
2507 {
2508         struct drm_i915_gem_object *obj = vma->obj;
2509         u32 pte_flags = 0;
2510         int ret;
2511
2512         ret = i915_get_ggtt_vma_pages(vma);
2513         if (ret)
2514                 return ret;
2515
2516         /* Currently applicable only to VLV */
2517         if (obj->gt_ro)
2518                 pte_flags |= PTE_READ_ONLY;
2519
2520         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2521                                 vma->node.start,
2522                                 cache_level, pte_flags);
2523
2524         /*
2525          * Without aliasing PPGTT there's no difference between
2526          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2527          * upgrade to both bound if we bind either to avoid double-binding.
2528          */
2529         vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2530
2531         return 0;
2532 }
2533
2534 struct ggtt_bind_vma__cb {
2535         struct i915_vma *vma;
2536         enum i915_cache_level cache_level;
2537         u32 flags;
2538 };
2539
2540 static int ggtt_bind_vma__cb(void *_arg)
2541 {
2542         struct ggtt_bind_vma__cb *arg = _arg;
2543         return ggtt_bind_vma(arg->vma, arg->cache_level, arg->flags);
2544 }
2545
2546 static int ggtt_bind_vma__BKL(struct i915_vma *vma,
2547                               enum i915_cache_level cache_level,
2548                               u32 flags)
2549 {
2550         struct ggtt_bind_vma__cb arg = { vma, cache_level, flags };
2551         return stop_machine(ggtt_bind_vma__cb, &arg, NULL);
2552 }
2553
2554 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2555                                  enum i915_cache_level cache_level,
2556                                  u32 flags)
2557 {
2558         struct drm_device *dev = vma->vm->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct drm_i915_gem_object *obj = vma->obj;
2561         struct sg_table *pages = obj->pages;
2562         u32 pte_flags = 0;
2563         int ret;
2564
2565         ret = i915_get_ggtt_vma_pages(vma);
2566         if (ret)
2567                 return ret;
2568         pages = vma->ggtt_view.pages;
2569
2570         /* Currently applicable only to VLV */
2571         if (obj->gt_ro)
2572                 pte_flags |= PTE_READ_ONLY;
2573
2574
2575         if (flags & GLOBAL_BIND) {
2576                 vma->vm->insert_entries(vma->vm, pages,
2577                                         vma->node.start,
2578                                         cache_level, pte_flags);
2579         }
2580
2581         if (flags & LOCAL_BIND) {
2582                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2583                 appgtt->base.insert_entries(&appgtt->base, pages,
2584                                             vma->node.start,
2585                                             cache_level, pte_flags);
2586         }
2587
2588         return 0;
2589 }
2590
2591 static void ggtt_unbind_vma(struct i915_vma *vma)
2592 {
2593         struct drm_device *dev = vma->vm->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_i915_gem_object *obj = vma->obj;
2596         const uint64_t size = min_t(uint64_t,
2597                                     obj->base.size,
2598                                     vma->node.size);
2599
2600         if (vma->bound & GLOBAL_BIND) {
2601                 vma->vm->clear_range(vma->vm,
2602                                      vma->node.start,
2603                                      size,
2604                                      true);
2605         }
2606
2607         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2608                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2609
2610                 appgtt->base.clear_range(&appgtt->base,
2611                                          vma->node.start,
2612                                          size,
2613                                          true);
2614         }
2615 }
2616
2617 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2618 {
2619         struct drm_device *dev = obj->base.dev;
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         bool interruptible;
2622
2623         interruptible = do_idling(dev_priv);
2624
2625         dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2626                      PCI_DMA_BIDIRECTIONAL);
2627
2628         undo_idling(dev_priv, interruptible);
2629 }
2630
2631 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2632                                   unsigned long color,
2633                                   u64 *start,
2634                                   u64 *end)
2635 {
2636         if (node->color != color)
2637                 *start += 4096;
2638
2639         if (!list_empty(&node->node_list)) {
2640                 node = list_entry(node->node_list.next,
2641                                   struct drm_mm_node,
2642                                   node_list);
2643                 if (node->allocated && node->color != color)
2644                         *end -= 4096;
2645         }
2646 }
2647
2648 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2649                                      u64 start,
2650                                      u64 mappable_end,
2651                                      u64 end)
2652 {
2653         /* Let GEM Manage all of the aperture.
2654          *
2655          * However, leave one page at the end still bound to the scratch page.
2656          * There are a number of places where the hardware apparently prefetches
2657          * past the end of the object, and we've seen multiple hangs with the
2658          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2659          * aperture.  One page should be enough to keep any prefetching inside
2660          * of the aperture.
2661          */
2662         struct drm_i915_private *dev_priv = dev->dev_private;
2663         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2664         struct drm_mm_node *entry;
2665         struct drm_i915_gem_object *obj;
2666         unsigned long hole_start, hole_end;
2667         int ret;
2668
2669         BUG_ON(mappable_end > end);
2670
2671         ggtt_vm->start = start;
2672
2673         /* Subtract the guard page before address space initialization to
2674          * shrink the range used by drm_mm */
2675         ggtt_vm->total = end - start - PAGE_SIZE;
2676         i915_address_space_init(ggtt_vm, dev_priv);
2677         ggtt_vm->total += PAGE_SIZE;
2678
2679         if (intel_vgpu_active(dev)) {
2680                 ret = intel_vgt_balloon(dev);
2681                 if (ret)
2682                         return ret;
2683         }
2684
2685         if (!HAS_LLC(dev))
2686                 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
2687
2688         /* Mark any preallocated objects as occupied */
2689         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2690                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2691
2692                 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2693                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2694
2695                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2696                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2697                 if (ret) {
2698                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2699                         return ret;
2700                 }
2701                 vma->bound |= GLOBAL_BIND;
2702                 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2703         }
2704
2705         /* Clear any non-preallocated blocks */
2706         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2707                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2708                               hole_start, hole_end);
2709                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2710                                      hole_end - hole_start, true);
2711         }
2712
2713         /* And finally clear the reserved guard page */
2714         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2715
2716         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2717                 struct i915_hw_ppgtt *ppgtt;
2718
2719                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2720                 if (!ppgtt)
2721                         return -ENOMEM;
2722
2723                 ret = __hw_ppgtt_init(dev, ppgtt);
2724                 if (ret) {
2725                         ppgtt->base.cleanup(&ppgtt->base);
2726                         kfree(ppgtt);
2727                         return ret;
2728                 }
2729
2730                 if (ppgtt->base.allocate_va_range)
2731                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2732                                                             ppgtt->base.total);
2733                 if (ret) {
2734                         ppgtt->base.cleanup(&ppgtt->base);
2735                         kfree(ppgtt);
2736                         return ret;
2737                 }
2738
2739                 ppgtt->base.clear_range(&ppgtt->base,
2740                                         ppgtt->base.start,
2741                                         ppgtt->base.total,
2742                                         true);
2743
2744                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2745                 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
2746                 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
2747         }
2748
2749         return 0;
2750 }
2751
2752 void i915_gem_init_global_gtt(struct drm_device *dev)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         u64 gtt_size, mappable_size;
2756
2757         gtt_size = dev_priv->gtt.base.total;
2758         mappable_size = dev_priv->gtt.mappable_end;
2759
2760         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2761 }
2762
2763 void i915_global_gtt_cleanup(struct drm_device *dev)
2764 {
2765         struct drm_i915_private *dev_priv = dev->dev_private;
2766         struct i915_address_space *vm = &dev_priv->gtt.base;
2767
2768         if (dev_priv->mm.aliasing_ppgtt) {
2769                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2770
2771                 ppgtt->base.cleanup(&ppgtt->base);
2772         }
2773
2774         if (drm_mm_initialized(&vm->mm)) {
2775                 if (intel_vgpu_active(dev))
2776                         intel_vgt_deballoon();
2777
2778                 drm_mm_takedown(&vm->mm);
2779                 list_del(&vm->global_link);
2780         }
2781
2782         vm->cleanup(vm);
2783 }
2784
2785 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2786 {
2787         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2788         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2789         return snb_gmch_ctl << 20;
2790 }
2791
2792 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2793 {
2794         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2795         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2796         if (bdw_gmch_ctl)
2797                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2798
2799 #ifdef CONFIG_X86_32
2800         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2801         if (bdw_gmch_ctl > 4)
2802                 bdw_gmch_ctl = 4;
2803 #endif
2804
2805         return bdw_gmch_ctl << 20;
2806 }
2807
2808 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2809 {
2810         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2811         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2812
2813         if (gmch_ctrl)
2814                 return 1 << (20 + gmch_ctrl);
2815
2816         return 0;
2817 }
2818
2819 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2820 {
2821         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2822         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2823         return snb_gmch_ctl << 25; /* 32 MB units */
2824 }
2825
2826 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2827 {
2828         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2829         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2830         return bdw_gmch_ctl << 25; /* 32 MB units */
2831 }
2832
2833 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2834 {
2835         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2836         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2837
2838         /*
2839          * 0x0  to 0x10: 32MB increments starting at 0MB
2840          * 0x11 to 0x16: 4MB increments starting at 8MB
2841          * 0x17 to 0x1d: 4MB increments start at 36MB
2842          */
2843         if (gmch_ctrl < 0x11)
2844                 return gmch_ctrl << 25;
2845         else if (gmch_ctrl < 0x17)
2846                 return (gmch_ctrl - 0x11 + 2) << 22;
2847         else
2848                 return (gmch_ctrl - 0x17 + 9) << 22;
2849 }
2850
2851 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2852 {
2853         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2854         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2855
2856         if (gen9_gmch_ctl < 0xf0)
2857                 return gen9_gmch_ctl << 25; /* 32 MB units */
2858         else
2859                 /* 4MB increments starting at 0xf0 for 4MB */
2860                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2861 }
2862
2863 static int ggtt_probe_common(struct drm_device *dev,
2864                              size_t gtt_size)
2865 {
2866         struct drm_i915_private *dev_priv = dev->dev_private;
2867         struct i915_page_scratch *scratch_page;
2868         phys_addr_t gtt_phys_addr;
2869
2870         /* For Modern GENs the PTEs and register space are split in the BAR */
2871         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2872                 (pci_resource_len(dev->pdev, 0) / 2);
2873
2874         /*
2875          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2876          * dropped. For WC mappings in general we have 64 byte burst writes
2877          * when the WC buffer is flushed, so we can't use it, but have to
2878          * resort to an uncached mapping. The WC issue is easily caught by the
2879          * readback check when writing GTT PTE entries.
2880          */
2881         if (IS_BROXTON(dev))
2882                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2883         else
2884                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2885         if (!dev_priv->gtt.gsm) {
2886                 DRM_ERROR("Failed to map the gtt page table\n");
2887                 return -ENOMEM;
2888         }
2889
2890         scratch_page = alloc_scratch_page(dev);
2891         if (IS_ERR(scratch_page)) {
2892                 DRM_ERROR("Scratch setup failed\n");
2893                 /* iounmap will also get called at remove, but meh */
2894                 iounmap(dev_priv->gtt.gsm);
2895                 return PTR_ERR(scratch_page);
2896         }
2897
2898         dev_priv->gtt.base.scratch_page = scratch_page;
2899
2900         return 0;
2901 }
2902
2903 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2904  * bits. When using advanced contexts each context stores its own PAT, but
2905  * writing this data shouldn't be harmful even in those cases. */
2906 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2907 {
2908         uint64_t pat;
2909
2910         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2911               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2912               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2913               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2914               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2915               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2916               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2917               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2918
2919         if (!USES_PPGTT(dev_priv->dev))
2920                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2921                  * so RTL will always use the value corresponding to
2922                  * pat_sel = 000".
2923                  * So let's disable cache for GGTT to avoid screen corruptions.
2924                  * MOCS still can be used though.
2925                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2926                  * before this patch, i.e. the same uncached + snooping access
2927                  * like on gen6/7 seems to be in effect.
2928                  * - So this just fixes blitter/render access. Again it looks
2929                  * like it's not just uncached access, but uncached + snooping.
2930                  * So we can still hold onto all our assumptions wrt cpu
2931                  * clflushing on LLC machines.
2932                  */
2933                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2934
2935         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2936          * write would work. */
2937         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2938         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2939 }
2940
2941 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2942 {
2943         uint64_t pat;
2944
2945         /*
2946          * Map WB on BDW to snooped on CHV.
2947          *
2948          * Only the snoop bit has meaning for CHV, the rest is
2949          * ignored.
2950          *
2951          * The hardware will never snoop for certain types of accesses:
2952          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2953          * - PPGTT page tables
2954          * - some other special cycles
2955          *
2956          * As with BDW, we also need to consider the following for GT accesses:
2957          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2958          * so RTL will always use the value corresponding to
2959          * pat_sel = 000".
2960          * Which means we must set the snoop bit in PAT entry 0
2961          * in order to keep the global status page working.
2962          */
2963         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2964               GEN8_PPAT(1, 0) |
2965               GEN8_PPAT(2, 0) |
2966               GEN8_PPAT(3, 0) |
2967               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2968               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2969               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2970               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2971
2972         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2973         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2974 }
2975
2976 static int gen8_gmch_probe(struct drm_device *dev,
2977                            u64 *gtt_total,
2978                            size_t *stolen,
2979                            phys_addr_t *mappable_base,
2980                            u64 *mappable_end)
2981 {
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983         u64 gtt_size;
2984         u16 snb_gmch_ctl;
2985         int ret;
2986
2987         /* TODO: We're not aware of mappable constraints on gen8 yet */
2988         *mappable_base = pci_resource_start(dev->pdev, 2);
2989         *mappable_end = pci_resource_len(dev->pdev, 2);
2990
2991         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2992                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2993
2994         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2995
2996         if (INTEL_INFO(dev)->gen >= 9) {
2997                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2998                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2999         } else if (IS_CHERRYVIEW(dev)) {
3000                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
3001                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
3002         } else {
3003                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
3004                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
3005         }
3006
3007         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3008
3009         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3010                 chv_setup_private_ppat(dev_priv);
3011         else
3012                 bdw_setup_private_ppat(dev_priv);
3013
3014         ret = ggtt_probe_common(dev, gtt_size);
3015
3016         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
3017         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
3018         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3019         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3020
3021         if (IS_CHERRYVIEW(dev))
3022                 dev_priv->gtt.base.bind_vma = ggtt_bind_vma__BKL;
3023
3024         return ret;
3025 }
3026
3027 static int gen6_gmch_probe(struct drm_device *dev,
3028                            u64 *gtt_total,
3029                            size_t *stolen,
3030                            phys_addr_t *mappable_base,
3031                            u64 *mappable_end)
3032 {
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         unsigned int gtt_size;
3035         u16 snb_gmch_ctl;
3036         int ret;
3037
3038         *mappable_base = pci_resource_start(dev->pdev, 2);
3039         *mappable_end = pci_resource_len(dev->pdev, 2);
3040
3041         /* 64/512MB is the current min/max we actually know of, but this is just
3042          * a coarse sanity check.
3043          */
3044         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
3045                 DRM_ERROR("Unknown GMADR size (%llx)\n",
3046                           dev_priv->gtt.mappable_end);
3047                 return -ENXIO;
3048         }
3049
3050         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3051                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3052         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3053
3054         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
3055
3056         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
3057         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3058
3059         ret = ggtt_probe_common(dev, gtt_size);
3060
3061         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3062         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
3063         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3064         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3065
3066         return ret;
3067 }
3068
3069 static void gen6_gmch_remove(struct i915_address_space *vm)
3070 {
3071
3072         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
3073
3074         iounmap(gtt->gsm);
3075         free_scratch_page(vm->dev, vm->scratch_page);
3076 }
3077
3078 static int i915_gmch_probe(struct drm_device *dev,
3079                            u64 *gtt_total,
3080                            size_t *stolen,
3081                            phys_addr_t *mappable_base,
3082                            u64 *mappable_end)
3083 {
3084         struct drm_i915_private *dev_priv = dev->dev_private;
3085         int ret;
3086
3087         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3088         if (!ret) {
3089                 DRM_ERROR("failed to set up gmch\n");
3090                 return -EIO;
3091         }
3092
3093         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
3094
3095         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
3096         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
3097         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
3098         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3099         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3100
3101         if (unlikely(dev_priv->gtt.do_idle_maps))
3102                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3103
3104         return 0;
3105 }
3106
3107 static void i915_gmch_remove(struct i915_address_space *vm)
3108 {
3109         intel_gmch_remove();
3110 }
3111
3112 int i915_gem_gtt_init(struct drm_device *dev)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct i915_gtt *gtt = &dev_priv->gtt;
3116         int ret;
3117
3118         if (INTEL_INFO(dev)->gen <= 5) {
3119                 gtt->gtt_probe = i915_gmch_probe;
3120                 gtt->base.cleanup = i915_gmch_remove;
3121         } else if (INTEL_INFO(dev)->gen < 8) {
3122                 gtt->gtt_probe = gen6_gmch_probe;
3123                 gtt->base.cleanup = gen6_gmch_remove;
3124                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
3125                         gtt->base.pte_encode = iris_pte_encode;
3126                 else if (IS_HASWELL(dev))
3127                         gtt->base.pte_encode = hsw_pte_encode;
3128                 else if (IS_VALLEYVIEW(dev))
3129                         gtt->base.pte_encode = byt_pte_encode;
3130                 else if (INTEL_INFO(dev)->gen >= 7)
3131                         gtt->base.pte_encode = ivb_pte_encode;
3132                 else
3133                         gtt->base.pte_encode = snb_pte_encode;
3134         } else {
3135                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3136                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
3137         }
3138
3139         gtt->base.dev = dev;
3140
3141         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
3142                              &gtt->mappable_base, &gtt->mappable_end);
3143         if (ret)
3144                 return ret;
3145
3146         /* GMADR is the PCI mmio aperture into the global GTT. */
3147         DRM_INFO("Memory usable by graphics device = %lluM\n",
3148                  gtt->base.total >> 20);
3149         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
3150         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
3151 #ifdef CONFIG_INTEL_IOMMU
3152         if (intel_iommu_gfx_mapped)
3153                 DRM_INFO("VT-d active for gfx access\n");
3154 #endif
3155         /*
3156          * i915.enable_ppgtt is read-only, so do an early pass to validate the
3157          * user's requested state against the hardware/driver capabilities.  We
3158          * do this now so that we can print out any log messages once rather
3159          * than every time we check intel_enable_ppgtt().
3160          */
3161         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3162         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3163
3164         return 0;
3165 }
3166
3167 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3168 {
3169         struct drm_i915_private *dev_priv = dev->dev_private;
3170         struct drm_i915_gem_object *obj;
3171         struct i915_address_space *vm;
3172         struct i915_vma *vma;
3173         bool flush;
3174
3175         i915_check_and_clear_faults(dev);
3176
3177         /* First fill our portion of the GTT with scratch pages */
3178         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3179                                        dev_priv->gtt.base.start,
3180                                        dev_priv->gtt.base.total,
3181                                        true);
3182
3183         /* Cache flush objects bound into GGTT and rebind them. */
3184         vm = &dev_priv->gtt.base;
3185         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3186                 flush = false;
3187                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3188                         if (vma->vm != vm)
3189                                 continue;
3190
3191                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
3192                                               PIN_UPDATE));
3193
3194                         flush = true;
3195                 }
3196
3197                 if (flush)
3198                         i915_gem_clflush_object(obj, obj->pin_display);
3199         }
3200
3201         if (INTEL_INFO(dev)->gen >= 8) {
3202                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3203                         chv_setup_private_ppat(dev_priv);
3204                 else
3205                         bdw_setup_private_ppat(dev_priv);
3206
3207                 return;
3208         }
3209
3210         if (USES_PPGTT(dev)) {
3211                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3212                         /* TODO: Perhaps it shouldn't be gen6 specific */
3213
3214                         struct i915_hw_ppgtt *ppgtt =
3215                                         container_of(vm, struct i915_hw_ppgtt,
3216                                                      base);
3217
3218                         if (i915_is_ggtt(vm))
3219                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3220
3221                         gen6_write_page_range(dev_priv, &ppgtt->pd,
3222                                               0, ppgtt->base.total);
3223                 }
3224         }
3225
3226         i915_ggtt_flush(dev_priv);
3227 }
3228
3229 static struct i915_vma *
3230 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3231                       struct i915_address_space *vm,
3232                       const struct i915_ggtt_view *ggtt_view)
3233 {
3234         struct i915_vma *vma;
3235
3236         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3237                 return ERR_PTR(-EINVAL);
3238
3239         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3240         if (vma == NULL)
3241                 return ERR_PTR(-ENOMEM);
3242
3243         INIT_LIST_HEAD(&vma->vma_link);
3244         INIT_LIST_HEAD(&vma->mm_list);
3245         INIT_LIST_HEAD(&vma->exec_list);
3246         vma->vm = vm;
3247         vma->obj = obj;
3248
3249         if (i915_is_ggtt(vm))
3250                 vma->ggtt_view = *ggtt_view;
3251
3252         list_add_tail(&vma->vma_link, &obj->vma_list);
3253         if (!i915_is_ggtt(vm))
3254                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3255
3256         return vma;
3257 }
3258
3259 struct i915_vma *
3260 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3261                                   struct i915_address_space *vm)
3262 {
3263         struct i915_vma *vma;
3264
3265         vma = i915_gem_obj_to_vma(obj, vm);
3266         if (!vma)
3267                 vma = __i915_gem_vma_create(obj, vm,
3268                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3269
3270         return vma;
3271 }
3272
3273 struct i915_vma *
3274 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3275                                        const struct i915_ggtt_view *view)
3276 {
3277         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
3278         struct i915_vma *vma;
3279
3280         if (WARN_ON(!view))
3281                 return ERR_PTR(-EINVAL);
3282
3283         vma = i915_gem_obj_to_ggtt_view(obj, view);
3284
3285         if (IS_ERR(vma))
3286                 return vma;
3287
3288         if (!vma)
3289                 vma = __i915_gem_vma_create(obj, ggtt, view);
3290
3291         return vma;
3292
3293 }
3294
3295 static struct scatterlist *
3296 rotate_pages(dma_addr_t *in, unsigned int offset,
3297              unsigned int width, unsigned int height,
3298              struct sg_table *st, struct scatterlist *sg)
3299 {
3300         unsigned int column, row;
3301         unsigned int src_idx;
3302
3303         if (!sg) {
3304                 st->nents = 0;
3305                 sg = st->sgl;
3306         }
3307
3308         for (column = 0; column < width; column++) {
3309                 src_idx = width * (height - 1) + column;
3310                 for (row = 0; row < height; row++) {
3311                         st->nents++;
3312                         /* We don't need the pages, but need to initialize
3313                          * the entries so the sg list can be happily traversed.
3314                          * The only thing we need are DMA addresses.
3315                          */
3316                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3317                         sg_dma_address(sg) = in[offset + src_idx];
3318                         sg_dma_len(sg) = PAGE_SIZE;
3319                         sg = sg_next(sg);
3320                         src_idx -= width;
3321                 }
3322         }
3323
3324         return sg;
3325 }
3326
3327 static struct sg_table *
3328 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3329                           struct drm_i915_gem_object *obj)
3330 {
3331         struct intel_rotation_info *rot_info = &ggtt_view->params.rotation_info;
3332         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
3333         unsigned int size_pages_uv;
3334         struct sg_page_iter sg_iter;
3335         unsigned long i;
3336         dma_addr_t *page_addr_list;
3337         struct sg_table *st;
3338         unsigned int uv_start_page;
3339         struct scatterlist *sg;
3340         int ret = -ENOMEM;
3341
3342         /* Allocate a temporary list of source pages for random access. */
3343         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3344                                        sizeof(dma_addr_t));
3345         if (!page_addr_list)
3346                 return ERR_PTR(ret);
3347
3348         /* Account for UV plane with NV12. */
3349         if (rot_info->pixel_format == DRM_FORMAT_NV12)
3350                 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3351         else
3352                 size_pages_uv = 0;
3353
3354         /* Allocate target SG list. */
3355         st = kmalloc(sizeof(*st), GFP_KERNEL);
3356         if (!st)
3357                 goto err_st_alloc;
3358
3359         ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3360         if (ret)
3361                 goto err_sg_alloc;
3362
3363         /* Populate source page list from the object. */
3364         i = 0;
3365         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3366                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3367                 i++;
3368         }
3369
3370         /* Rotate the pages. */
3371         sg = rotate_pages(page_addr_list, 0,
3372                      rot_info->width_pages, rot_info->height_pages,
3373                      st, NULL);
3374
3375         /* Append the UV plane if NV12. */
3376         if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3377                 uv_start_page = size_pages;
3378
3379                 /* Check for tile-row un-alignment. */
3380                 if (offset_in_page(rot_info->uv_offset))
3381                         uv_start_page--;
3382
3383                 rot_info->uv_start_page = uv_start_page;
3384
3385                 rotate_pages(page_addr_list, uv_start_page,
3386                              rot_info->width_pages_uv,
3387                              rot_info->height_pages_uv,
3388                              st, sg);
3389         }
3390
3391         DRM_DEBUG_KMS(
3392                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3393                       obj->base.size, rot_info->pitch, rot_info->height,
3394                       rot_info->pixel_format, rot_info->width_pages,
3395                       rot_info->height_pages, size_pages + size_pages_uv,
3396                       size_pages);
3397
3398         drm_free_large(page_addr_list);
3399
3400         return st;
3401
3402 err_sg_alloc:
3403         kfree(st);
3404 err_st_alloc:
3405         drm_free_large(page_addr_list);
3406
3407         DRM_DEBUG_KMS(
3408                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3409                       obj->base.size, ret, rot_info->pitch, rot_info->height,
3410                       rot_info->pixel_format, rot_info->width_pages,
3411                       rot_info->height_pages, size_pages + size_pages_uv,
3412                       size_pages);
3413         return ERR_PTR(ret);
3414 }
3415
3416 static struct sg_table *
3417 intel_partial_pages(const struct i915_ggtt_view *view,
3418                     struct drm_i915_gem_object *obj)
3419 {
3420         struct sg_table *st;
3421         struct scatterlist *sg;
3422         struct sg_page_iter obj_sg_iter;
3423         int ret = -ENOMEM;
3424
3425         st = kmalloc(sizeof(*st), GFP_KERNEL);
3426         if (!st)
3427                 goto err_st_alloc;
3428
3429         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3430         if (ret)
3431                 goto err_sg_alloc;
3432
3433         sg = st->sgl;
3434         st->nents = 0;
3435         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3436                 view->params.partial.offset)
3437         {
3438                 if (st->nents >= view->params.partial.size)
3439                         break;
3440
3441                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3442                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3443                 sg_dma_len(sg) = PAGE_SIZE;
3444
3445                 sg = sg_next(sg);
3446                 st->nents++;
3447         }
3448
3449         return st;
3450
3451 err_sg_alloc:
3452         kfree(st);
3453 err_st_alloc:
3454         return ERR_PTR(ret);
3455 }
3456
3457 static int
3458 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3459 {
3460         int ret = 0;
3461
3462         if (vma->ggtt_view.pages)
3463                 return 0;
3464
3465         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3466                 vma->ggtt_view.pages = vma->obj->pages;
3467         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3468                 vma->ggtt_view.pages =
3469                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
3470         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3471                 vma->ggtt_view.pages =
3472                         intel_partial_pages(&vma->ggtt_view, vma->obj);
3473         else
3474                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3475                           vma->ggtt_view.type);
3476
3477         if (!vma->ggtt_view.pages) {
3478                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3479                           vma->ggtt_view.type);
3480                 ret = -EINVAL;
3481         } else if (IS_ERR(vma->ggtt_view.pages)) {
3482                 ret = PTR_ERR(vma->ggtt_view.pages);
3483                 vma->ggtt_view.pages = NULL;
3484                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3485                           vma->ggtt_view.type, ret);
3486         }
3487
3488         return ret;
3489 }
3490
3491 /**
3492  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3493  * @vma: VMA to map
3494  * @cache_level: mapping cache level
3495  * @flags: flags like global or local mapping
3496  *
3497  * DMA addresses are taken from the scatter-gather table of this object (or of
3498  * this VMA in case of non-default GGTT views) and PTE entries set up.
3499  * Note that DMA addresses are also the only part of the SG table we care about.
3500  */
3501 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3502                   u32 flags)
3503 {
3504         int ret;
3505         u32 bind_flags;
3506
3507         if (WARN_ON(flags == 0))
3508                 return -EINVAL;
3509
3510         bind_flags = 0;
3511         if (flags & PIN_GLOBAL)
3512                 bind_flags |= GLOBAL_BIND;
3513         if (flags & PIN_USER)
3514                 bind_flags |= LOCAL_BIND;
3515
3516         if (flags & PIN_UPDATE)
3517                 bind_flags |= vma->bound;
3518         else
3519                 bind_flags &= ~vma->bound;
3520
3521         if (bind_flags == 0)
3522                 return 0;
3523
3524         if (vma->bound == 0 && vma->vm->allocate_va_range) {
3525                 trace_i915_va_alloc(vma->vm,
3526                                     vma->node.start,
3527                                     vma->node.size,
3528                                     VM_TO_TRACE_NAME(vma->vm));
3529
3530                 /* XXX: i915_vma_pin() will fix this +- hack */
3531                 vma->pin_count++;
3532                 ret = vma->vm->allocate_va_range(vma->vm,
3533                                                  vma->node.start,
3534                                                  vma->node.size);
3535                 vma->pin_count--;
3536                 if (ret)
3537                         return ret;
3538         }
3539
3540         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3541         if (ret)
3542                 return ret;
3543
3544         vma->bound |= bind_flags;
3545
3546         return 0;
3547 }
3548
3549 /**
3550  * i915_ggtt_view_size - Get the size of a GGTT view.
3551  * @obj: Object the view is of.
3552  * @view: The view in question.
3553  *
3554  * @return The size of the GGTT view in bytes.
3555  */
3556 size_t
3557 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3558                     const struct i915_ggtt_view *view)
3559 {
3560         if (view->type == I915_GGTT_VIEW_NORMAL) {
3561                 return obj->base.size;
3562         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3563                 return view->params.rotation_info.size;
3564         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3565                 return view->params.partial.size << PAGE_SHIFT;
3566         } else {
3567                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3568                 return obj->base.size;
3569         }
3570 }