2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_trace.h"
31 #include "intel_drv.h"
33 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
35 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
37 if (i915.enable_ppgtt == 0)
40 if (i915.enable_ppgtt == 1 && full)
46 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
48 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
51 if (enable_ppgtt == 1)
54 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
57 #ifdef CONFIG_INTEL_IOMMU
58 /* Disable ppgtt on SNB if VT-d is on. */
59 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
60 DRM_INFO("Disabling PPGTT because VT-d is on\n");
65 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
68 #define GEN6_PPGTT_PD_ENTRIES 512
69 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
70 typedef uint64_t gen8_gtt_pte_t;
71 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
74 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
75 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
77 #define GEN6_PDE_VALID (1 << 0)
78 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
79 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
81 #define GEN6_PTE_VALID (1 << 0)
82 #define GEN6_PTE_UNCACHED (1 << 1)
83 #define HSW_PTE_UNCACHED (0)
84 #define GEN6_PTE_CACHE_LLC (2 << 1)
85 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
86 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
87 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
89 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
90 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
92 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
93 (((bits) & 0x8) << (11 - 3)))
94 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
95 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
96 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
97 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
98 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
99 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
101 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
102 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
104 /* GEN8 legacy style addressis defined as a 3 level page table:
105 * 31:30 | 29:21 | 20:12 | 11:0
106 * PDPE | PDE | PTE | offset
107 * The difference as compared to normal x86 3 level page table is the PDPEs are
108 * programmed via register.
110 #define GEN8_PDPE_SHIFT 30
111 #define GEN8_PDPE_MASK 0x3
112 #define GEN8_PDE_SHIFT 21
113 #define GEN8_PDE_MASK 0x1ff
114 #define GEN8_PTE_SHIFT 12
115 #define GEN8_PTE_MASK 0x1ff
117 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
118 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
119 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
120 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
122 static void ppgtt_bind_vma(struct i915_vma *vma,
123 enum i915_cache_level cache_level,
125 static void ppgtt_unbind_vma(struct i915_vma *vma);
126 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
128 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
132 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
134 if (level != I915_CACHE_NONE)
135 pte |= PPAT_CACHED_INDEX;
137 pte |= PPAT_UNCACHED_INDEX;
141 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
143 enum i915_cache_level level)
145 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
147 if (level != I915_CACHE_NONE)
148 pde |= PPAT_CACHED_PDE_INDEX;
150 pde |= PPAT_UNCACHED_INDEX;
154 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
155 enum i915_cache_level level,
158 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
159 pte |= GEN6_PTE_ADDR_ENCODE(addr);
162 case I915_CACHE_L3_LLC:
164 pte |= GEN6_PTE_CACHE_LLC;
166 case I915_CACHE_NONE:
167 pte |= GEN6_PTE_UNCACHED;
176 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
177 enum i915_cache_level level,
180 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
181 pte |= GEN6_PTE_ADDR_ENCODE(addr);
184 case I915_CACHE_L3_LLC:
185 pte |= GEN7_PTE_CACHE_L3_LLC;
188 pte |= GEN6_PTE_CACHE_LLC;
190 case I915_CACHE_NONE:
191 pte |= GEN6_PTE_UNCACHED;
200 #define BYT_PTE_WRITEABLE (1 << 1)
201 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
203 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
204 enum i915_cache_level level,
207 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
208 pte |= GEN6_PTE_ADDR_ENCODE(addr);
210 /* Mark the page as writeable. Other platforms don't have a
211 * setting for read-only/writable, so this matches that behavior.
213 pte |= BYT_PTE_WRITEABLE;
215 if (level != I915_CACHE_NONE)
216 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
221 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
222 enum i915_cache_level level,
225 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
226 pte |= HSW_PTE_ADDR_ENCODE(addr);
228 if (level != I915_CACHE_NONE)
229 pte |= HSW_WB_LLC_AGE3;
234 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
235 enum i915_cache_level level,
238 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
239 pte |= HSW_PTE_ADDR_ENCODE(addr);
242 case I915_CACHE_NONE:
245 pte |= HSW_WT_ELLC_LLC_AGE3;
248 pte |= HSW_WB_ELLC_LLC_AGE3;
255 /* Broadwell Page Directory Pointer Descriptors */
256 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
257 uint64_t val, bool synchronous)
259 struct drm_i915_private *dev_priv = ring->dev->dev_private;
265 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
266 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
270 ret = intel_ring_begin(ring, 6);
274 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
275 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
276 intel_ring_emit(ring, (u32)(val >> 32));
277 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
278 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
279 intel_ring_emit(ring, (u32)(val));
280 intel_ring_advance(ring);
285 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
286 struct intel_ring_buffer *ring,
291 /* bit of a hack to find the actual last used pd */
292 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
294 for (i = used_pd - 1; i >= 0; i--) {
295 dma_addr_t addr = ppgtt->pd_dma_addr[i];
296 ret = gen8_write_pdp(ring, i, addr, synchronous);
304 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
309 struct i915_hw_ppgtt *ppgtt =
310 container_of(vm, struct i915_hw_ppgtt, base);
311 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
312 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
313 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
314 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
315 unsigned num_entries = length >> PAGE_SHIFT;
316 unsigned last_pte, i;
318 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
319 I915_CACHE_LLC, use_scratch);
321 while (num_entries) {
322 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
324 last_pte = pte + num_entries;
325 if (last_pte > GEN8_PTES_PER_PAGE)
326 last_pte = GEN8_PTES_PER_PAGE;
328 pt_vaddr = kmap_atomic(page_table);
330 for (i = pte; i < last_pte; i++) {
331 pt_vaddr[i] = scratch_pte;
335 kunmap_atomic(pt_vaddr);
338 if (++pde == GEN8_PDES_PER_PAGE) {
345 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
346 struct sg_table *pages,
348 enum i915_cache_level cache_level)
350 struct i915_hw_ppgtt *ppgtt =
351 container_of(vm, struct i915_hw_ppgtt, base);
352 gen8_gtt_pte_t *pt_vaddr;
353 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
354 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
355 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
356 struct sg_page_iter sg_iter;
360 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
361 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
364 if (pt_vaddr == NULL)
365 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
368 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
370 if (++pte == GEN8_PTES_PER_PAGE) {
371 kunmap_atomic(pt_vaddr);
373 if (++pde == GEN8_PDES_PER_PAGE) {
381 kunmap_atomic(pt_vaddr);
384 static void gen8_free_page_tables(struct page **pt_pages)
388 if (pt_pages == NULL)
391 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
393 __free_pages(pt_pages[i], 0);
396 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
400 for (i = 0; i < ppgtt->num_pd_pages; i++) {
401 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
402 kfree(ppgtt->gen8_pt_pages[i]);
403 kfree(ppgtt->gen8_pt_dma_addr[i]);
406 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
409 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
411 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
414 for (i = 0; i < ppgtt->num_pd_pages; i++) {
415 /* TODO: In the future we'll support sparse mappings, so this
416 * will have to change. */
417 if (!ppgtt->pd_dma_addr[i])
420 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
421 PCI_DMA_BIDIRECTIONAL);
423 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
424 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
426 pci_unmap_page(hwdev, addr, PAGE_SIZE,
427 PCI_DMA_BIDIRECTIONAL);
432 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
434 struct i915_hw_ppgtt *ppgtt =
435 container_of(vm, struct i915_hw_ppgtt, base);
437 list_del(&vm->global_link);
438 drm_mm_takedown(&vm->mm);
440 gen8_ppgtt_unmap_pages(ppgtt);
441 gen8_ppgtt_free(ppgtt);
444 static struct page **__gen8_alloc_page_tables(void)
446 struct page **pt_pages;
449 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
451 return ERR_PTR(-ENOMEM);
453 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
454 pt_pages[i] = alloc_page(GFP_KERNEL);
462 gen8_free_page_tables(pt_pages);
464 return ERR_PTR(-ENOMEM);
467 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
470 struct page **pt_pages[GEN8_LEGACY_PDPS];
473 for (i = 0; i < max_pdp; i++) {
474 pt_pages[i] = __gen8_alloc_page_tables();
475 if (IS_ERR(pt_pages[i])) {
476 ret = PTR_ERR(pt_pages[i]);
481 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
482 * "atomic" - for cleanup purposes.
484 for (i = 0; i < max_pdp; i++)
485 ppgtt->gen8_pt_pages[i] = pt_pages[i];
491 gen8_free_page_tables(pt_pages[i]);
498 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
502 for (i = 0; i < ppgtt->num_pd_pages; i++) {
503 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
506 if (!ppgtt->gen8_pt_dma_addr[i])
513 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
516 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
517 if (!ppgtt->pd_pages)
520 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
521 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
526 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
531 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
535 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
537 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
541 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
543 ret = gen8_ppgtt_allocate_dma(ppgtt);
545 gen8_ppgtt_free(ppgtt);
550 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
556 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
557 &ppgtt->pd_pages[pd], 0,
558 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
560 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
564 ppgtt->pd_dma_addr[pd] = pd_addr;
569 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
577 p = ppgtt->gen8_pt_pages[pd][pt];
578 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
579 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
580 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
584 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
590 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
591 * with a net effect resembling a 2-level page table in normal x86 terms. Each
592 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
595 * FIXME: split allocation into smaller pieces. For now we only ever do this
596 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
597 * TODO: Do something with the size parameter
599 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
601 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
602 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
606 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
608 /* 1. Do all our allocations for page directories and page tables. */
609 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
614 * 2. Create DMA mappings for the page directories and page tables.
616 for (i = 0; i < max_pdp; i++) {
617 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
621 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
622 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
629 * 3. Map all the page directory entires to point to the page tables
632 * For now, the PPGTT helper functions all require that the PDEs are
633 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
634 * will never need to touch the PDEs again.
636 for (i = 0; i < max_pdp; i++) {
637 gen8_ppgtt_pde_t *pd_vaddr;
638 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
639 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
640 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
641 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
644 kunmap_atomic(pd_vaddr);
647 ppgtt->enable = gen8_ppgtt_enable;
648 ppgtt->switch_mm = gen8_mm_switch;
649 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
650 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
651 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
652 ppgtt->base.start = 0;
653 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
655 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
657 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
658 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
659 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
660 ppgtt->num_pd_entries,
661 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
665 gen8_ppgtt_unmap_pages(ppgtt);
666 gen8_ppgtt_free(ppgtt);
670 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
672 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
673 struct i915_address_space *vm = &ppgtt->base;
674 gen6_gtt_pte_t __iomem *pd_addr;
675 gen6_gtt_pte_t scratch_pte;
679 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
681 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
682 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
684 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
685 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
686 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
688 gen6_gtt_pte_t *pt_vaddr;
689 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
690 pd_entry = readl(pd_addr + pde);
691 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
693 if (pd_entry != expected)
694 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
698 seq_printf(m, "\tPDE: %x\n", pd_entry);
700 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
701 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
703 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
707 for (i = 0; i < 4; i++)
708 if (pt_vaddr[pte + i] != scratch_pte)
713 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
714 for (i = 0; i < 4; i++) {
715 if (pt_vaddr[pte + i] != scratch_pte)
716 seq_printf(m, " %08x", pt_vaddr[pte + i]);
718 seq_puts(m, " SCRATCH ");
722 kunmap_atomic(pt_vaddr);
726 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
728 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
729 gen6_gtt_pte_t __iomem *pd_addr;
733 WARN_ON(ppgtt->pd_offset & 0x3f);
734 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
735 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
736 for (i = 0; i < ppgtt->num_pd_entries; i++) {
739 pt_addr = ppgtt->pt_dma_addr[i];
740 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
741 pd_entry |= GEN6_PDE_VALID;
743 writel(pd_entry, pd_addr + i);
748 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
750 BUG_ON(ppgtt->pd_offset & 0x3f);
752 return (ppgtt->pd_offset / 64) << 16;
755 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
756 struct intel_ring_buffer *ring,
759 struct drm_device *dev = ppgtt->base.dev;
760 struct drm_i915_private *dev_priv = dev->dev_private;
763 /* If we're in reset, we can assume the GPU is sufficiently idle to
764 * manually frob these bits. Ideally we could use the ring functions,
765 * except our error handling makes it quite difficult (can't use
766 * intel_ring_begin, ring->flush, or intel_ring_advance)
768 * FIXME: We should try not to special case reset
771 i915_reset_in_progress(&dev_priv->gpu_error)) {
772 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
773 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
774 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
775 POSTING_READ(RING_PP_DIR_BASE(ring));
779 /* NB: TLBs must be flushed and invalidated before a switch */
780 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
784 ret = intel_ring_begin(ring, 6);
788 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
789 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
790 intel_ring_emit(ring, PP_DIR_DCLV_2G);
791 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
792 intel_ring_emit(ring, get_pd_offset(ppgtt));
793 intel_ring_emit(ring, MI_NOOP);
794 intel_ring_advance(ring);
799 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
800 struct intel_ring_buffer *ring,
803 struct drm_device *dev = ppgtt->base.dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
807 /* If we're in reset, we can assume the GPU is sufficiently idle to
808 * manually frob these bits. Ideally we could use the ring functions,
809 * except our error handling makes it quite difficult (can't use
810 * intel_ring_begin, ring->flush, or intel_ring_advance)
812 * FIXME: We should try not to special case reset
815 i915_reset_in_progress(&dev_priv->gpu_error)) {
816 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
817 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
818 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
819 POSTING_READ(RING_PP_DIR_BASE(ring));
823 /* NB: TLBs must be flushed and invalidated before a switch */
824 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
828 ret = intel_ring_begin(ring, 6);
832 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
833 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
834 intel_ring_emit(ring, PP_DIR_DCLV_2G);
835 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
836 intel_ring_emit(ring, get_pd_offset(ppgtt));
837 intel_ring_emit(ring, MI_NOOP);
838 intel_ring_advance(ring);
840 /* XXX: RCS is the only one to auto invalidate the TLBs? */
841 if (ring->id != RCS) {
842 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
850 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
851 struct intel_ring_buffer *ring,
854 struct drm_device *dev = ppgtt->base.dev;
855 struct drm_i915_private *dev_priv = dev->dev_private;
860 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
861 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
863 POSTING_READ(RING_PP_DIR_DCLV(ring));
868 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
870 struct drm_device *dev = ppgtt->base.dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 struct intel_ring_buffer *ring;
875 for_each_ring(ring, dev_priv, j) {
876 I915_WRITE(RING_MODE_GEN7(ring),
877 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
879 /* We promise to do a switch later with FULL PPGTT. If this is
880 * aliasing, this is the one and only switch we'll do */
881 if (USES_FULL_PPGTT(dev))
884 ret = ppgtt->switch_mm(ppgtt, ring, true);
892 for_each_ring(ring, dev_priv, j)
893 I915_WRITE(RING_MODE_GEN7(ring),
894 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
898 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
900 struct drm_device *dev = ppgtt->base.dev;
901 struct drm_i915_private *dev_priv = dev->dev_private;
902 struct intel_ring_buffer *ring;
903 uint32_t ecochk, ecobits;
906 ecobits = I915_READ(GAC_ECO_BITS);
907 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
909 ecochk = I915_READ(GAM_ECOCHK);
910 if (IS_HASWELL(dev)) {
911 ecochk |= ECOCHK_PPGTT_WB_HSW;
913 ecochk |= ECOCHK_PPGTT_LLC_IVB;
914 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
916 I915_WRITE(GAM_ECOCHK, ecochk);
918 for_each_ring(ring, dev_priv, i) {
920 /* GFX_MODE is per-ring on gen7+ */
921 I915_WRITE(RING_MODE_GEN7(ring),
922 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
924 /* We promise to do a switch later with FULL PPGTT. If this is
925 * aliasing, this is the one and only switch we'll do */
926 if (USES_FULL_PPGTT(dev))
929 ret = ppgtt->switch_mm(ppgtt, ring, true);
937 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
939 struct drm_device *dev = ppgtt->base.dev;
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 struct intel_ring_buffer *ring;
942 uint32_t ecochk, gab_ctl, ecobits;
945 ecobits = I915_READ(GAC_ECO_BITS);
946 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
947 ECOBITS_PPGTT_CACHE64B);
949 gab_ctl = I915_READ(GAB_CTL);
950 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
952 ecochk = I915_READ(GAM_ECOCHK);
953 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
955 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
957 for_each_ring(ring, dev_priv, i) {
958 int ret = ppgtt->switch_mm(ppgtt, ring, true);
966 /* PPGTT support for Sandybdrige/Gen6 and later */
967 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
972 struct i915_hw_ppgtt *ppgtt =
973 container_of(vm, struct i915_hw_ppgtt, base);
974 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
975 unsigned first_entry = start >> PAGE_SHIFT;
976 unsigned num_entries = length >> PAGE_SHIFT;
977 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
978 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
979 unsigned last_pte, i;
981 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
983 while (num_entries) {
984 last_pte = first_pte + num_entries;
985 if (last_pte > I915_PPGTT_PT_ENTRIES)
986 last_pte = I915_PPGTT_PT_ENTRIES;
988 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
990 for (i = first_pte; i < last_pte; i++)
991 pt_vaddr[i] = scratch_pte;
993 kunmap_atomic(pt_vaddr);
995 num_entries -= last_pte - first_pte;
1001 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1002 struct sg_table *pages,
1004 enum i915_cache_level cache_level)
1006 struct i915_hw_ppgtt *ppgtt =
1007 container_of(vm, struct i915_hw_ppgtt, base);
1008 gen6_gtt_pte_t *pt_vaddr;
1009 unsigned first_entry = start >> PAGE_SHIFT;
1010 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
1011 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
1012 struct sg_page_iter sg_iter;
1015 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1016 if (pt_vaddr == NULL)
1017 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
1020 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1022 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
1023 kunmap_atomic(pt_vaddr);
1030 kunmap_atomic(pt_vaddr);
1033 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1037 if (ppgtt->pt_dma_addr) {
1038 for (i = 0; i < ppgtt->num_pd_entries; i++)
1039 pci_unmap_page(ppgtt->base.dev->pdev,
1040 ppgtt->pt_dma_addr[i],
1041 4096, PCI_DMA_BIDIRECTIONAL);
1045 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1049 kfree(ppgtt->pt_dma_addr);
1050 for (i = 0; i < ppgtt->num_pd_entries; i++)
1051 __free_page(ppgtt->pt_pages[i]);
1052 kfree(ppgtt->pt_pages);
1055 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1057 struct i915_hw_ppgtt *ppgtt =
1058 container_of(vm, struct i915_hw_ppgtt, base);
1060 list_del(&vm->global_link);
1061 drm_mm_takedown(&ppgtt->base.mm);
1062 drm_mm_remove_node(&ppgtt->node);
1064 gen6_ppgtt_unmap_pages(ppgtt);
1065 gen6_ppgtt_free(ppgtt);
1068 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1070 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
1071 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
1072 struct drm_device *dev = ppgtt->base.dev;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 bool retried = false;
1077 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1078 * allocator works in address space sizes, so it's multiplied by page
1079 * size. We allocate at the top of the GTT to avoid fragmentation.
1081 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1083 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1084 &ppgtt->node, GEN6_PD_SIZE,
1086 0, dev_priv->gtt.base.total,
1087 DRM_MM_SEARCH_DEFAULT,
1088 DRM_MM_CREATE_DEFAULT);
1089 if (ret == -ENOSPC && !retried) {
1090 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1091 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1092 I915_CACHE_NONE, 0);
1100 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1101 DRM_DEBUG("Forced to use aperture for PDEs\n");
1103 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1107 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1111 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1114 if (!ppgtt->pt_pages)
1117 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1118 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1119 if (!ppgtt->pt_pages[i]) {
1120 gen6_ppgtt_free(ppgtt);
1128 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1132 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1136 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1138 drm_mm_remove_node(&ppgtt->node);
1142 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1144 if (!ppgtt->pt_dma_addr) {
1145 drm_mm_remove_node(&ppgtt->node);
1146 gen6_ppgtt_free(ppgtt);
1153 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1155 struct drm_device *dev = ppgtt->base.dev;
1158 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1161 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1162 PCI_DMA_BIDIRECTIONAL);
1164 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1165 gen6_ppgtt_unmap_pages(ppgtt);
1169 ppgtt->pt_dma_addr[i] = pt_addr;
1175 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1177 struct drm_device *dev = ppgtt->base.dev;
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1181 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1183 ppgtt->enable = gen6_ppgtt_enable;
1184 ppgtt->switch_mm = gen6_mm_switch;
1185 } else if (IS_HASWELL(dev)) {
1186 ppgtt->enable = gen7_ppgtt_enable;
1187 ppgtt->switch_mm = hsw_mm_switch;
1188 } else if (IS_GEN7(dev)) {
1189 ppgtt->enable = gen7_ppgtt_enable;
1190 ppgtt->switch_mm = gen7_mm_switch;
1194 ret = gen6_ppgtt_alloc(ppgtt);
1198 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1200 gen6_ppgtt_free(ppgtt);
1204 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1205 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1206 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1207 ppgtt->base.start = 0;
1208 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1209 ppgtt->debug_dump = gen6_dump_ppgtt;
1212 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1214 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1216 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1217 ppgtt->node.size >> 20,
1218 ppgtt->node.start / PAGE_SIZE);
1223 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1228 ppgtt->base.dev = dev;
1229 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1231 if (INTEL_INFO(dev)->gen < 8)
1232 ret = gen6_ppgtt_init(ppgtt);
1233 else if (IS_GEN8(dev))
1234 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 kref_init(&ppgtt->ref);
1241 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1243 i915_init_vm(dev_priv, &ppgtt->base);
1244 if (INTEL_INFO(dev)->gen < 8) {
1245 gen6_write_pdes(ppgtt);
1246 DRM_DEBUG("Adding PPGTT at offset %x\n",
1247 ppgtt->pd_offset << 10);
1255 ppgtt_bind_vma(struct i915_vma *vma,
1256 enum i915_cache_level cache_level,
1259 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1263 static void ppgtt_unbind_vma(struct i915_vma *vma)
1265 vma->vm->clear_range(vma->vm,
1267 vma->obj->base.size,
1271 extern int intel_iommu_gfx_mapped;
1272 /* Certain Gen5 chipsets require require idling the GPU before
1273 * unmapping anything from the GTT when VT-d is enabled.
1275 static inline bool needs_idle_maps(struct drm_device *dev)
1277 #ifdef CONFIG_INTEL_IOMMU
1278 /* Query intel_iommu to see if we need the workaround. Presumably that
1281 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1287 static bool do_idling(struct drm_i915_private *dev_priv)
1289 bool ret = dev_priv->mm.interruptible;
1291 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1292 dev_priv->mm.interruptible = false;
1293 if (i915_gpu_idle(dev_priv->dev)) {
1294 DRM_ERROR("Couldn't idle GPU\n");
1295 /* Wait a bit, in hopes it avoids the hang */
1303 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1305 if (unlikely(dev_priv->gtt.do_idle_maps))
1306 dev_priv->mm.interruptible = interruptible;
1309 void i915_check_and_clear_faults(struct drm_device *dev)
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 struct intel_ring_buffer *ring;
1315 if (INTEL_INFO(dev)->gen < 6)
1318 for_each_ring(ring, dev_priv, i) {
1320 fault_reg = I915_READ(RING_FAULT_REG(ring));
1321 if (fault_reg & RING_FAULT_VALID) {
1322 DRM_DEBUG_DRIVER("Unexpected fault\n"
1323 "\tAddr: 0x%08lx\\n"
1324 "\tAddress space: %s\n"
1327 fault_reg & PAGE_MASK,
1328 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1329 RING_FAULT_SRCID(fault_reg),
1330 RING_FAULT_FAULT_TYPE(fault_reg));
1331 I915_WRITE(RING_FAULT_REG(ring),
1332 fault_reg & ~RING_FAULT_VALID);
1335 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1338 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1342 /* Don't bother messing with faults pre GEN6 as we have little
1343 * documentation supporting that it's a good idea.
1345 if (INTEL_INFO(dev)->gen < 6)
1348 i915_check_and_clear_faults(dev);
1350 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1351 dev_priv->gtt.base.start,
1352 dev_priv->gtt.base.total,
1356 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 struct drm_i915_gem_object *obj;
1360 struct i915_address_space *vm;
1362 i915_check_and_clear_faults(dev);
1364 /* First fill our portion of the GTT with scratch pages */
1365 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1366 dev_priv->gtt.base.start,
1367 dev_priv->gtt.base.total,
1370 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1371 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1372 &dev_priv->gtt.base);
1376 i915_gem_clflush_object(obj, obj->pin_display);
1377 /* The bind_vma code tries to be smart about tracking mappings.
1378 * Unfortunately above, we've just wiped out the mappings
1379 * without telling our object about it. So we need to fake it.
1381 obj->has_global_gtt_mapping = 0;
1382 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1386 if (INTEL_INFO(dev)->gen >= 8) {
1387 gen8_setup_private_ppat(dev_priv);
1391 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1392 /* TODO: Perhaps it shouldn't be gen6 specific */
1393 if (i915_is_ggtt(vm)) {
1394 if (dev_priv->mm.aliasing_ppgtt)
1395 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1399 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1402 i915_gem_chipset_flush(dev);
1405 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1407 if (obj->has_dma_mapping)
1410 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1411 obj->pages->sgl, obj->pages->nents,
1412 PCI_DMA_BIDIRECTIONAL))
1418 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1423 iowrite32((u32)pte, addr);
1424 iowrite32(pte >> 32, addr + 4);
1428 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1429 struct sg_table *st,
1431 enum i915_cache_level level)
1433 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1434 unsigned first_entry = start >> PAGE_SHIFT;
1435 gen8_gtt_pte_t __iomem *gtt_entries =
1436 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1438 struct sg_page_iter sg_iter;
1441 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1442 addr = sg_dma_address(sg_iter.sg) +
1443 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1444 gen8_set_pte(>t_entries[i],
1445 gen8_pte_encode(addr, level, true));
1450 * XXX: This serves as a posting read to make sure that the PTE has
1451 * actually been updated. There is some concern that even though
1452 * registers and PTEs are within the same BAR that they are potentially
1453 * of NUMA access patterns. Therefore, even with the way we assume
1454 * hardware should work, we must keep this posting read for paranoia.
1457 WARN_ON(readq(>t_entries[i-1])
1458 != gen8_pte_encode(addr, level, true));
1460 /* This next bit makes the above posting read even more important. We
1461 * want to flush the TLBs only after we're certain all the PTE updates
1464 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1465 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1469 * Binds an object into the global gtt with the specified cache level. The object
1470 * will be accessible to the GPU via commands whose operands reference offsets
1471 * within the global GTT as well as accessible by the GPU through the GMADR
1472 * mapped BAR (dev_priv->mm.gtt->gtt).
1474 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1475 struct sg_table *st,
1477 enum i915_cache_level level)
1479 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1480 unsigned first_entry = start >> PAGE_SHIFT;
1481 gen6_gtt_pte_t __iomem *gtt_entries =
1482 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1484 struct sg_page_iter sg_iter;
1487 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1488 addr = sg_page_iter_dma_address(&sg_iter);
1489 iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]);
1493 /* XXX: This serves as a posting read to make sure that the PTE has
1494 * actually been updated. There is some concern that even though
1495 * registers and PTEs are within the same BAR that they are potentially
1496 * of NUMA access patterns. Therefore, even with the way we assume
1497 * hardware should work, we must keep this posting read for paranoia.
1500 WARN_ON(readl(>t_entries[i-1]) !=
1501 vm->pte_encode(addr, level, true));
1503 /* This next bit makes the above posting read even more important. We
1504 * want to flush the TLBs only after we're certain all the PTE updates
1507 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1508 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1511 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1516 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1517 unsigned first_entry = start >> PAGE_SHIFT;
1518 unsigned num_entries = length >> PAGE_SHIFT;
1519 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1520 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1521 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1524 if (WARN(num_entries > max_entries,
1525 "First entry = %d; Num entries = %d (max=%d)\n",
1526 first_entry, num_entries, max_entries))
1527 num_entries = max_entries;
1529 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1532 for (i = 0; i < num_entries; i++)
1533 gen8_set_pte(>t_base[i], scratch_pte);
1537 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1542 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1543 unsigned first_entry = start >> PAGE_SHIFT;
1544 unsigned num_entries = length >> PAGE_SHIFT;
1545 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1546 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1547 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1550 if (WARN(num_entries > max_entries,
1551 "First entry = %d; Num entries = %d (max=%d)\n",
1552 first_entry, num_entries, max_entries))
1553 num_entries = max_entries;
1555 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1557 for (i = 0; i < num_entries; i++)
1558 iowrite32(scratch_pte, >t_base[i]);
1563 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1564 enum i915_cache_level cache_level,
1567 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1568 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1569 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1571 BUG_ON(!i915_is_ggtt(vma->vm));
1572 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1573 vma->obj->has_global_gtt_mapping = 1;
1576 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1581 unsigned first_entry = start >> PAGE_SHIFT;
1582 unsigned num_entries = length >> PAGE_SHIFT;
1583 intel_gtt_clear_range(first_entry, num_entries);
1586 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1588 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1589 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1591 BUG_ON(!i915_is_ggtt(vma->vm));
1592 vma->obj->has_global_gtt_mapping = 0;
1593 intel_gtt_clear_range(first, size);
1596 static void ggtt_bind_vma(struct i915_vma *vma,
1597 enum i915_cache_level cache_level,
1600 struct drm_device *dev = vma->vm->dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 struct drm_i915_gem_object *obj = vma->obj;
1604 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1605 * or we have a global mapping already but the cacheability flags have
1606 * changed, set the global PTEs.
1608 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1609 * instead if none of the above hold true.
1611 * NB: A global mapping should only be needed for special regions like
1612 * "gtt mappable", SNB errata, or if specified via special execbuf
1613 * flags. At all other times, the GPU will use the aliasing PPGTT.
1615 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1616 if (!obj->has_global_gtt_mapping ||
1617 (cache_level != obj->cache_level)) {
1618 vma->vm->insert_entries(vma->vm, obj->pages,
1621 obj->has_global_gtt_mapping = 1;
1625 if (dev_priv->mm.aliasing_ppgtt &&
1626 (!obj->has_aliasing_ppgtt_mapping ||
1627 (cache_level != obj->cache_level))) {
1628 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1629 appgtt->base.insert_entries(&appgtt->base,
1633 vma->obj->has_aliasing_ppgtt_mapping = 1;
1637 static void ggtt_unbind_vma(struct i915_vma *vma)
1639 struct drm_device *dev = vma->vm->dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_i915_gem_object *obj = vma->obj;
1643 if (obj->has_global_gtt_mapping) {
1644 vma->vm->clear_range(vma->vm,
1648 obj->has_global_gtt_mapping = 0;
1651 if (obj->has_aliasing_ppgtt_mapping) {
1652 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1653 appgtt->base.clear_range(&appgtt->base,
1657 obj->has_aliasing_ppgtt_mapping = 0;
1661 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1663 struct drm_device *dev = obj->base.dev;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1667 interruptible = do_idling(dev_priv);
1669 if (!obj->has_dma_mapping)
1670 dma_unmap_sg(&dev->pdev->dev,
1671 obj->pages->sgl, obj->pages->nents,
1672 PCI_DMA_BIDIRECTIONAL);
1674 undo_idling(dev_priv, interruptible);
1677 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1678 unsigned long color,
1679 unsigned long *start,
1682 if (node->color != color)
1685 if (!list_empty(&node->node_list)) {
1686 node = list_entry(node->node_list.next,
1689 if (node->allocated && node->color != color)
1694 void i915_gem_setup_global_gtt(struct drm_device *dev,
1695 unsigned long start,
1696 unsigned long mappable_end,
1699 /* Let GEM Manage all of the aperture.
1701 * However, leave one page at the end still bound to the scratch page.
1702 * There are a number of places where the hardware apparently prefetches
1703 * past the end of the object, and we've seen multiple hangs with the
1704 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1705 * aperture. One page should be enough to keep any prefetching inside
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1710 struct drm_mm_node *entry;
1711 struct drm_i915_gem_object *obj;
1712 unsigned long hole_start, hole_end;
1714 BUG_ON(mappable_end > end);
1716 /* Subtract the guard page ... */
1717 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1719 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1721 /* Mark any preallocated objects as occupied */
1722 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1723 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1725 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1726 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1728 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1729 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1731 DRM_DEBUG_KMS("Reservation failed\n");
1732 obj->has_global_gtt_mapping = 1;
1735 dev_priv->gtt.base.start = start;
1736 dev_priv->gtt.base.total = end - start;
1738 /* Clear any non-preallocated blocks */
1739 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1740 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1741 hole_start, hole_end);
1742 ggtt_vm->clear_range(ggtt_vm, hole_start,
1743 hole_end - hole_start, true);
1746 /* And finally clear the reserved guard page */
1747 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1750 void i915_gem_init_global_gtt(struct drm_device *dev)
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 unsigned long gtt_size, mappable_size;
1755 gtt_size = dev_priv->gtt.base.total;
1756 mappable_size = dev_priv->gtt.mappable_end;
1758 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1761 static int setup_scratch_page(struct drm_device *dev)
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1765 dma_addr_t dma_addr;
1767 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1771 set_pages_uc(page, 1);
1773 #ifdef CONFIG_INTEL_IOMMU
1774 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1775 PCI_DMA_BIDIRECTIONAL);
1776 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1779 dma_addr = page_to_phys(page);
1781 dev_priv->gtt.base.scratch.page = page;
1782 dev_priv->gtt.base.scratch.addr = dma_addr;
1787 static void teardown_scratch_page(struct drm_device *dev)
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 struct page *page = dev_priv->gtt.base.scratch.page;
1792 set_pages_wb(page, 1);
1793 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1794 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1799 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1801 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1802 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1803 return snb_gmch_ctl << 20;
1806 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1808 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1809 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1811 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1812 return bdw_gmch_ctl << 20;
1815 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1817 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1818 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1819 return snb_gmch_ctl << 25; /* 32 MB units */
1822 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1824 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1825 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1826 return bdw_gmch_ctl << 25; /* 32 MB units */
1829 static int ggtt_probe_common(struct drm_device *dev,
1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833 phys_addr_t gtt_phys_addr;
1836 /* For Modern GENs the PTEs and register space are split in the BAR */
1837 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1838 (pci_resource_len(dev->pdev, 0) / 2);
1840 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1841 if (!dev_priv->gtt.gsm) {
1842 DRM_ERROR("Failed to map the gtt page table\n");
1846 ret = setup_scratch_page(dev);
1848 DRM_ERROR("Scratch setup failed\n");
1849 /* iounmap will also get called at remove, but meh */
1850 iounmap(dev_priv->gtt.gsm);
1856 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1857 * bits. When using advanced contexts each context stores its own PAT, but
1858 * writing this data shouldn't be harmful even in those cases. */
1859 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1861 #define GEN8_PPAT_UC (0<<0)
1862 #define GEN8_PPAT_WC (1<<0)
1863 #define GEN8_PPAT_WT (2<<0)
1864 #define GEN8_PPAT_WB (3<<0)
1865 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1866 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1867 #define GEN8_PPAT_LLC (1<<2)
1868 #define GEN8_PPAT_LLCELLC (2<<2)
1869 #define GEN8_PPAT_LLCeLLC (3<<2)
1870 #define GEN8_PPAT_AGE(x) (x<<4)
1871 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1874 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1875 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1876 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1877 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1878 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1879 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1880 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1881 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1883 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1884 * write would work. */
1885 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1886 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1889 static int gen8_gmch_probe(struct drm_device *dev,
1892 phys_addr_t *mappable_base,
1893 unsigned long *mappable_end)
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 unsigned int gtt_size;
1900 /* TODO: We're not aware of mappable constraints on gen8 yet */
1901 *mappable_base = pci_resource_start(dev->pdev, 2);
1902 *mappable_end = pci_resource_len(dev->pdev, 2);
1904 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1905 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1907 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1909 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1911 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1912 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1914 gen8_setup_private_ppat(dev_priv);
1916 ret = ggtt_probe_common(dev, gtt_size);
1918 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1919 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1924 static int gen6_gmch_probe(struct drm_device *dev,
1927 phys_addr_t *mappable_base,
1928 unsigned long *mappable_end)
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1931 unsigned int gtt_size;
1935 *mappable_base = pci_resource_start(dev->pdev, 2);
1936 *mappable_end = pci_resource_len(dev->pdev, 2);
1938 /* 64/512MB is the current min/max we actually know of, but this is just
1939 * a coarse sanity check.
1941 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1942 DRM_ERROR("Unknown GMADR size (%lx)\n",
1943 dev_priv->gtt.mappable_end);
1947 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1948 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1949 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1951 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1953 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1954 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1956 ret = ggtt_probe_common(dev, gtt_size);
1958 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1959 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1964 static void gen6_gmch_remove(struct i915_address_space *vm)
1967 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1969 drm_mm_takedown(&vm->mm);
1971 teardown_scratch_page(vm->dev);
1974 static int i915_gmch_probe(struct drm_device *dev,
1977 phys_addr_t *mappable_base,
1978 unsigned long *mappable_end)
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1983 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1985 DRM_ERROR("failed to set up gmch\n");
1989 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1991 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1992 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1994 if (unlikely(dev_priv->gtt.do_idle_maps))
1995 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2000 static void i915_gmch_remove(struct i915_address_space *vm)
2002 intel_gmch_remove();
2005 int i915_gem_gtt_init(struct drm_device *dev)
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct i915_gtt *gtt = &dev_priv->gtt;
2011 if (INTEL_INFO(dev)->gen <= 5) {
2012 gtt->gtt_probe = i915_gmch_probe;
2013 gtt->base.cleanup = i915_gmch_remove;
2014 } else if (INTEL_INFO(dev)->gen < 8) {
2015 gtt->gtt_probe = gen6_gmch_probe;
2016 gtt->base.cleanup = gen6_gmch_remove;
2017 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2018 gtt->base.pte_encode = iris_pte_encode;
2019 else if (IS_HASWELL(dev))
2020 gtt->base.pte_encode = hsw_pte_encode;
2021 else if (IS_VALLEYVIEW(dev))
2022 gtt->base.pte_encode = byt_pte_encode;
2023 else if (INTEL_INFO(dev)->gen >= 7)
2024 gtt->base.pte_encode = ivb_pte_encode;
2026 gtt->base.pte_encode = snb_pte_encode;
2028 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2029 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2032 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2033 >t->mappable_base, >t->mappable_end);
2037 gtt->base.dev = dev;
2039 /* GMADR is the PCI mmio aperture into the global GTT. */
2040 DRM_INFO("Memory usable by graphics device = %zdM\n",
2041 gtt->base.total >> 20);
2042 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2043 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2045 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2046 * user's requested state against the hardware/driver capabilities. We
2047 * do this now so that we can print out any log messages once rather
2048 * than every time we check intel_enable_ppgtt().
2050 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2051 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2056 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2057 struct i915_address_space *vm)
2059 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2061 return ERR_PTR(-ENOMEM);
2063 INIT_LIST_HEAD(&vma->vma_link);
2064 INIT_LIST_HEAD(&vma->mm_list);
2065 INIT_LIST_HEAD(&vma->exec_list);
2069 switch (INTEL_INFO(vm->dev)->gen) {
2073 if (i915_is_ggtt(vm)) {
2074 vma->unbind_vma = ggtt_unbind_vma;
2075 vma->bind_vma = ggtt_bind_vma;
2077 vma->unbind_vma = ppgtt_unbind_vma;
2078 vma->bind_vma = ppgtt_bind_vma;
2085 BUG_ON(!i915_is_ggtt(vm));
2086 vma->unbind_vma = i915_ggtt_unbind_vma;
2087 vma->bind_vma = i915_ggtt_bind_vma;
2093 /* Keep GGTT vmas first to make debug easier */
2094 if (i915_is_ggtt(vm))
2095 list_add(&vma->vma_link, &obj->vma_list);
2097 list_add_tail(&vma->vma_link, &obj->vma_list);
2103 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2104 struct i915_address_space *vm)
2106 struct i915_vma *vma;
2108 vma = i915_gem_obj_to_vma(obj, vm);
2110 vma = __i915_gem_vma_create(obj, vm);