2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 #include <linux/io-mapping.h>
39 #include "i915_gem_request.h"
41 #define I915_FENCE_REG_NONE -1
42 #define I915_MAX_NUM_FENCES 32
43 /* 32 fences + sign bit for FENCE_REG_NONE */
44 #define I915_MAX_NUM_FENCE_BITS 6
46 struct drm_i915_file_private;
47 struct drm_i915_fence_reg;
49 typedef uint32_t gen6_pte_t;
50 typedef uint64_t gen8_pte_t;
51 typedef uint64_t gen8_pde_t;
52 typedef uint64_t gen8_ppgtt_pdpe_t;
53 typedef uint64_t gen8_ppgtt_pml4e_t;
55 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
57 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
58 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
59 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
60 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
61 #define GEN6_PTE_CACHE_LLC (2 << 1)
62 #define GEN6_PTE_UNCACHED (1 << 1)
63 #define GEN6_PTE_VALID (1 << 0)
65 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
66 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
68 #define I915_PDE_MASK (I915_PDES - 1)
69 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
71 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
72 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
73 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
74 #define GEN6_PDE_SHIFT 22
75 #define GEN6_PDE_VALID (1 << 0)
77 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
79 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
80 #define BYT_PTE_WRITEABLE (1 << 1)
82 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
83 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
85 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
86 (((bits) & 0x8) << (11 - 3)))
87 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
88 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
89 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
90 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
91 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
92 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
93 #define HSW_PTE_UNCACHED (0)
94 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
95 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
97 /* GEN8 legacy style address is defined as a 3 level page table:
98 * 31:30 | 29:21 | 20:12 | 11:0
99 * PDPE | PDE | PTE | offset
100 * The difference as compared to normal x86 3 level page table is the PDPEs are
101 * programmed via register.
103 * GEN8 48b legacy style address is defined as a 4 level page table:
104 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
105 * PML4E | PDPE | PDE | PTE | offset
107 #define GEN8_PML4ES_PER_PML4 512
108 #define GEN8_PML4E_SHIFT 39
109 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
110 #define GEN8_PDPE_SHIFT 30
111 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
113 #define GEN8_PDPE_MASK 0x1ff
114 #define GEN8_PDE_SHIFT 21
115 #define GEN8_PDE_MASK 0x1ff
116 #define GEN8_PTE_SHIFT 12
117 #define GEN8_PTE_MASK 0x1ff
118 #define GEN8_LEGACY_PDPES 4
119 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
121 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
122 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
124 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
125 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
126 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
127 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
129 #define CHV_PPAT_SNOOP (1<<6)
130 #define GEN8_PPAT_AGE(x) (x<<4)
131 #define GEN8_PPAT_LLCeLLC (3<<2)
132 #define GEN8_PPAT_LLCELLC (2<<2)
133 #define GEN8_PPAT_LLC (1<<2)
134 #define GEN8_PPAT_WB (3<<0)
135 #define GEN8_PPAT_WT (2<<0)
136 #define GEN8_PPAT_WC (1<<0)
137 #define GEN8_PPAT_UC (0<<0)
138 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
139 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
141 enum i915_ggtt_view_type {
142 I915_GGTT_VIEW_NORMAL = 0,
143 I915_GGTT_VIEW_ROTATED,
144 I915_GGTT_VIEW_PARTIAL,
147 struct intel_rotation_info {
150 unsigned int width, height, stride, offset;
154 struct i915_ggtt_view {
155 enum i915_ggtt_view_type type;
162 struct intel_rotation_info rotated;
166 extern const struct i915_ggtt_view i915_ggtt_view_normal;
167 extern const struct i915_ggtt_view i915_ggtt_view_rotated;
169 enum i915_cache_level;
172 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
173 * VMA's presence cannot be guaranteed before binding, or after unbinding the
174 * object into/from the address space.
176 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
177 * will always be <= an objects lifetime. So object refcounting should cover us.
180 struct drm_mm_node node;
181 struct drm_i915_gem_object *obj;
182 struct i915_address_space *vm;
183 struct drm_i915_fence_reg *fence;
184 struct sg_table *pages;
187 u64 display_alignment;
191 * How many users have pinned this object in GTT space. The following
192 * users can each hold at most one reference: pwrite/pread, execbuffer
193 * (objects are not allowed multiple times for the same batchbuffer),
194 * and the framebuffer code. When switching/pageflipping, the
195 * framebuffer code has at most two buffers pinned per crtc.
197 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
198 * bits with absolutely no headroom. So use 4 bits.
200 #define I915_VMA_PIN_MASK 0xf
201 #define I915_VMA_PIN_OVERFLOW BIT(5)
203 /** Flags and address space this VMA is bound to */
204 #define I915_VMA_GLOBAL_BIND BIT(6)
205 #define I915_VMA_LOCAL_BIND BIT(7)
206 #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW)
208 #define I915_VMA_GGTT BIT(8)
209 #define I915_VMA_CAN_FENCE BIT(9)
210 #define I915_VMA_CLOSED BIT(10)
213 struct i915_gem_active last_read[I915_NUM_ENGINES];
214 struct i915_gem_active last_fence;
217 * Support different GGTT views into the same object.
218 * This means there can be multiple VMA mappings per object and per VM.
219 * i915_ggtt_view_type is used to distinguish between those entries.
220 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
221 * assumed in GEM functions which take no ggtt view parameter.
223 struct i915_ggtt_view ggtt_view;
225 /** This object's place on the active/inactive lists */
226 struct list_head vm_link;
228 struct list_head obj_link; /* Link in the object's VMA list */
230 /** This vma's place in the batchbuffer or on the eviction list */
231 struct list_head exec_list;
234 * Used for performing relocations during execbuffer insertion.
236 struct hlist_node exec_node;
237 unsigned long exec_handle;
238 struct drm_i915_gem_exec_object2 *exec_entry;
242 i915_vma_create(struct drm_i915_gem_object *obj,
243 struct i915_address_space *vm,
244 const struct i915_ggtt_view *view);
245 void i915_vma_unpin_and_release(struct i915_vma **p_vma);
247 static inline bool i915_vma_is_ggtt(const struct i915_vma *vma)
249 return vma->flags & I915_VMA_GGTT;
252 static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma)
254 return vma->flags & I915_VMA_CAN_FENCE;
257 static inline bool i915_vma_is_closed(const struct i915_vma *vma)
259 return vma->flags & I915_VMA_CLOSED;
262 static inline unsigned int i915_vma_get_active(const struct i915_vma *vma)
267 static inline bool i915_vma_is_active(const struct i915_vma *vma)
269 return i915_vma_get_active(vma);
272 static inline void i915_vma_set_active(struct i915_vma *vma,
275 vma->active |= BIT(engine);
278 static inline void i915_vma_clear_active(struct i915_vma *vma,
281 vma->active &= ~BIT(engine);
284 static inline bool i915_vma_has_active_engine(const struct i915_vma *vma,
287 return vma->active & BIT(engine);
290 static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
292 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
293 GEM_BUG_ON(!vma->node.allocated);
294 GEM_BUG_ON(upper_32_bits(vma->node.start));
295 GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
296 return lower_32_bits(vma->node.start);
299 struct i915_page_dma {
304 /* For gen6/gen7 only. This is the offset in the GGTT
305 * where the page directory entries for PPGTT begin
307 uint32_t ggtt_offset;
311 #define px_base(px) (&(px)->base)
312 #define px_page(px) (px_base(px)->page)
313 #define px_dma(px) (px_base(px)->daddr)
315 struct i915_page_scratch {
316 struct i915_page_dma base;
319 struct i915_page_table {
320 struct i915_page_dma base;
322 unsigned long *used_ptes;
325 struct i915_page_directory {
326 struct i915_page_dma base;
328 unsigned long *used_pdes;
329 struct i915_page_table *page_table[I915_PDES]; /* PDEs */
332 struct i915_page_directory_pointer {
333 struct i915_page_dma base;
335 unsigned long *used_pdpes;
336 struct i915_page_directory **page_directory;
340 struct i915_page_dma base;
342 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
343 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
346 struct i915_address_space {
348 struct drm_device *dev;
349 /* Every address space belongs to a struct file - except for the global
350 * GTT that is owned by the driver (and so @file is set to NULL). In
351 * principle, no information should leak from one context to another
352 * (or between files/processes etc) unless explicitly shared by the
353 * owner. Tracking the owner is important in order to free up per-file
354 * objects along with the file, to aide resource tracking, and to
357 struct drm_i915_file_private *file;
358 struct list_head global_link;
359 u64 start; /* Start offset always 0 for dri2 */
360 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
364 struct i915_page_scratch *scratch_page;
365 struct i915_page_table *scratch_pt;
366 struct i915_page_directory *scratch_pd;
367 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
370 * List of objects currently involved in rendering.
372 * Includes buffers having the contents of their GPU caches
373 * flushed, not necessarily primitives. last_read_req
374 * represents when the rendering involved will be completed.
376 * A reference is held on the buffer while on this list.
378 struct list_head active_list;
381 * LRU list of objects which are not in the ringbuffer and
382 * are ready to unbind, but are still in the GTT.
384 * last_read_req is NULL while an object is in this list.
386 * A reference is not held on the buffer while on this list,
387 * as merely being GTT-bound shouldn't prevent its being
388 * freed, and we'll pull it off the list in the free path.
390 struct list_head inactive_list;
393 * List of vma that have been unbound.
395 * A reference is not held on the buffer while on this list.
397 struct list_head unbound_list;
399 /* FIXME: Need a more generic return type */
400 gen6_pte_t (*pte_encode)(dma_addr_t addr,
401 enum i915_cache_level level,
402 bool valid, u32 flags); /* Create a valid PTE */
403 /* flags for pte_encode */
404 #define PTE_READ_ONLY (1<<0)
405 int (*allocate_va_range)(struct i915_address_space *vm,
408 void (*clear_range)(struct i915_address_space *vm,
412 void (*insert_page)(struct i915_address_space *vm,
415 enum i915_cache_level cache_level,
417 void (*insert_entries)(struct i915_address_space *vm,
420 enum i915_cache_level cache_level, u32 flags);
421 void (*cleanup)(struct i915_address_space *vm);
422 /** Unmap an object from an address space. This usually consists of
423 * setting the valid PTE entries to a reserved scratch page. */
424 void (*unbind_vma)(struct i915_vma *vma);
425 /* Map an object into an address space with the given cache flags. */
426 int (*bind_vma)(struct i915_vma *vma,
427 enum i915_cache_level cache_level,
431 #define i915_is_ggtt(V) (!(V)->file)
433 /* The Graphics Translation Table is the way in which GEN hardware translates a
434 * Graphics Virtual Address into a Physical Address. In addition to the normal
435 * collateral associated with any va->pa translations GEN hardware also has a
436 * portion of the GTT which can be mapped by the CPU and remain both coherent
437 * and correct (in cases like swizzling). That region is referred to as GMADR in
441 struct i915_address_space base;
442 struct io_mapping mappable; /* Mapping to our CPU mappable region */
444 size_t stolen_size; /* Total size of stolen memory */
445 size_t stolen_usable_size; /* Total size minus BIOS reserved */
446 size_t stolen_reserved_base;
447 size_t stolen_reserved_size;
448 u64 mappable_end; /* End offset that we can CPU map */
449 phys_addr_t mappable_base; /* PA of our GMADR */
451 /** "Graphics Stolen Memory" holds the global PTEs */
459 struct i915_hw_ppgtt {
460 struct i915_address_space base;
462 struct drm_mm_node node;
463 unsigned long pd_dirty_rings;
465 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
466 struct i915_page_directory_pointer pdp; /* GEN8+ */
467 struct i915_page_directory pd; /* GEN6-7 */
470 gen6_pte_t __iomem *pd_addr;
472 int (*enable)(struct i915_hw_ppgtt *ppgtt);
473 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
474 struct drm_i915_gem_request *req);
475 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
479 * gen6_for_each_pde() iterates over every pde from start until start+length.
480 * If start and start+length are not perfectly divisible, the macro will round
481 * down and up as needed. Start=0 and length=2G effectively iterates over
482 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
483 * so each of the other parameters should preferably be a simple variable, or
484 * at most an lvalue with no side-effects!
486 #define gen6_for_each_pde(pt, pd, start, length, iter) \
487 for (iter = gen6_pde_index(start); \
488 length > 0 && iter < I915_PDES && \
489 (pt = (pd)->page_table[iter], true); \
490 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
491 temp = min(temp - start, length); \
492 start += temp, length -= temp; }), ++iter)
494 #define gen6_for_all_pdes(pt, pd, iter) \
496 iter < I915_PDES && \
497 (pt = (pd)->page_table[iter], true); \
500 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
502 const uint32_t mask = NUM_PTE(pde_shift) - 1;
504 return (address >> PAGE_SHIFT) & mask;
507 /* Helper to counts the number of PTEs within the given length. This count
508 * does not cross a page table boundary, so the max value would be
509 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
511 static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
514 const uint64_t mask = ~((1ULL << pde_shift) - 1);
517 WARN_ON(length == 0);
518 WARN_ON(offset_in_page(addr|length));
522 if ((addr & mask) != (end & mask))
523 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
525 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
528 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
530 return (addr >> shift) & I915_PDE_MASK;
533 static inline uint32_t gen6_pte_index(uint32_t addr)
535 return i915_pte_index(addr, GEN6_PDE_SHIFT);
538 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
540 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
543 static inline uint32_t gen6_pde_index(uint32_t addr)
545 return i915_pde_index(addr, GEN6_PDE_SHIFT);
548 /* Equivalent to the gen6 version, For each pde iterates over every pde
549 * between from start until start + length. On gen8+ it simply iterates
550 * over every page directory entry in a page directory.
552 #define gen8_for_each_pde(pt, pd, start, length, iter) \
553 for (iter = gen8_pde_index(start); \
554 length > 0 && iter < I915_PDES && \
555 (pt = (pd)->page_table[iter], true); \
556 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
557 temp = min(temp - start, length); \
558 start += temp, length -= temp; }), ++iter)
560 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
561 for (iter = gen8_pdpe_index(start); \
562 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \
563 (pd = (pdp)->page_directory[iter], true); \
564 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
565 temp = min(temp - start, length); \
566 start += temp, length -= temp; }), ++iter)
568 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
569 for (iter = gen8_pml4e_index(start); \
570 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
571 (pdp = (pml4)->pdps[iter], true); \
572 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
573 temp = min(temp - start, length); \
574 start += temp, length -= temp; }), ++iter)
576 static inline uint32_t gen8_pte_index(uint64_t address)
578 return i915_pte_index(address, GEN8_PDE_SHIFT);
581 static inline uint32_t gen8_pde_index(uint64_t address)
583 return i915_pde_index(address, GEN8_PDE_SHIFT);
586 static inline uint32_t gen8_pdpe_index(uint64_t address)
588 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
591 static inline uint32_t gen8_pml4e_index(uint64_t address)
593 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
596 static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
598 return i915_pte_count(address, length, GEN8_PDE_SHIFT);
601 static inline dma_addr_t
602 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
604 return test_bit(n, ppgtt->pdp.used_pdpes) ?
605 px_dma(ppgtt->pdp.page_directory[n]) :
606 px_dma(ppgtt->base.scratch_pd);
609 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
610 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
611 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
612 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
613 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
615 int i915_ppgtt_init_hw(struct drm_device *dev);
616 void i915_ppgtt_release(struct kref *kref);
617 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
618 struct drm_i915_file_private *fpriv);
619 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
622 kref_get(&ppgtt->ref);
624 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
627 kref_put(&ppgtt->ref, i915_ppgtt_release);
630 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
631 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
632 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
634 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
635 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
637 /* Flags used by pin/bind&friends. */
638 #define PIN_NONBLOCK BIT(0)
639 #define PIN_MAPPABLE BIT(1)
640 #define PIN_ZONE_4G BIT(2)
641 #define PIN_NONFAULT BIT(3)
643 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
644 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
645 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
646 #define PIN_UPDATE BIT(8)
648 #define PIN_HIGH BIT(9)
649 #define PIN_OFFSET_BIAS BIT(10)
650 #define PIN_OFFSET_FIXED BIT(11)
651 #define PIN_OFFSET_MASK (~4095)
653 int __i915_vma_do_pin(struct i915_vma *vma,
654 u64 size, u64 alignment, u64 flags);
655 static inline int __must_check
656 i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
658 BUILD_BUG_ON(PIN_MBZ != I915_VMA_PIN_OVERFLOW);
659 BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
660 BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND);
662 /* Pin early to prevent the shrinker/eviction logic from destroying
663 * our vma as we insert and bind.
665 if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0))
668 return __i915_vma_do_pin(vma, size, alignment, flags);
671 static inline int i915_vma_pin_count(const struct i915_vma *vma)
673 return vma->flags & I915_VMA_PIN_MASK;
676 static inline bool i915_vma_is_pinned(const struct i915_vma *vma)
678 return i915_vma_pin_count(vma);
681 static inline void __i915_vma_pin(struct i915_vma *vma)
684 GEM_BUG_ON(vma->flags & I915_VMA_PIN_OVERFLOW);
687 static inline void __i915_vma_unpin(struct i915_vma *vma)
689 GEM_BUG_ON(!i915_vma_is_pinned(vma));
693 static inline void i915_vma_unpin(struct i915_vma *vma)
695 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
696 __i915_vma_unpin(vma);
700 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture
703 * The passed in VMA has to be pinned in the global GTT mappable region.
704 * An extra pinning of the VMA is acquired for the return iomapping,
705 * the caller must call i915_vma_unpin_iomap to relinquish the pinning
706 * after the iomapping is no longer required.
708 * Callers must hold the struct_mutex.
710 * Returns a valid iomapped pointer or ERR_PTR.
712 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma);
713 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x))
716 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap
719 * Unpins the previously iomapped VMA from i915_vma_pin_iomap().
721 * Callers must hold the struct_mutex. This function is only valid to be
722 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap().
724 static inline void i915_vma_unpin_iomap(struct i915_vma *vma)
726 lockdep_assert_held(&vma->vm->dev->struct_mutex);
727 GEM_BUG_ON(vma->iomap == NULL);
731 static inline struct page *i915_vma_first_page(struct i915_vma *vma)
733 GEM_BUG_ON(!vma->pages);
734 return sg_page(vma->pages->sgl);