2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
27 #include <linux/sched.h>
28 #include <linux/sched/clock.h>
29 #include <linux/sched/signal.h>
33 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
38 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
40 /* The timeline struct (as part of the ppgtt underneath a context)
41 * may be freed when the request is no longer in use by the GPU.
42 * We could extend the life of a context to beyond that of all
43 * fences, possibly keeping the hw resource around indefinitely,
44 * or we just give them a false name. Since
45 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
46 * lie seems justifiable.
48 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
51 return to_request(fence)->timeline->common->name;
54 static bool i915_fence_signaled(struct dma_fence *fence)
56 return i915_gem_request_completed(to_request(fence));
59 static bool i915_fence_enable_signaling(struct dma_fence *fence)
61 if (i915_fence_signaled(fence))
64 intel_engine_enable_signaling(to_request(fence));
68 static signed long i915_fence_wait(struct dma_fence *fence,
72 return i915_wait_request(to_request(fence), interruptible, timeout);
75 static void i915_fence_release(struct dma_fence *fence)
77 struct drm_i915_gem_request *req = to_request(fence);
79 /* The request is put onto a RCU freelist (i.e. the address
80 * is immediately reused), mark the fences as being freed now.
81 * Otherwise the debugobjects for the fences are only marked as
82 * freed when the slab cache itself is freed, and so we would get
83 * caught trying to reuse dead objects.
85 i915_sw_fence_fini(&req->submit);
87 kmem_cache_free(req->i915->requests, req);
90 const struct dma_fence_ops i915_fence_ops = {
91 .get_driver_name = i915_fence_get_driver_name,
92 .get_timeline_name = i915_fence_get_timeline_name,
93 .enable_signaling = i915_fence_enable_signaling,
94 .signaled = i915_fence_signaled,
95 .wait = i915_fence_wait,
96 .release = i915_fence_release,
100 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
102 struct drm_i915_file_private *file_priv;
104 file_priv = request->file_priv;
108 spin_lock(&file_priv->mm.lock);
109 if (request->file_priv) {
110 list_del(&request->client_link);
111 request->file_priv = NULL;
113 spin_unlock(&file_priv->mm.lock);
116 static struct i915_dependency *
117 i915_dependency_alloc(struct drm_i915_private *i915)
119 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
123 i915_dependency_free(struct drm_i915_private *i915,
124 struct i915_dependency *dep)
126 kmem_cache_free(i915->dependencies, dep);
130 __i915_priotree_add_dependency(struct i915_priotree *pt,
131 struct i915_priotree *signal,
132 struct i915_dependency *dep,
135 INIT_LIST_HEAD(&dep->dfs_link);
136 list_add(&dep->wait_link, &signal->waiters_list);
137 list_add(&dep->signal_link, &pt->signalers_list);
138 dep->signaler = signal;
143 i915_priotree_add_dependency(struct drm_i915_private *i915,
144 struct i915_priotree *pt,
145 struct i915_priotree *signal)
147 struct i915_dependency *dep;
149 dep = i915_dependency_alloc(i915);
153 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
158 i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
160 struct i915_dependency *dep, *next;
162 GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
164 /* Everyone we depended upon (the fences we wait to be signaled)
165 * should retire before us and remove themselves from our list.
166 * However, retirement is run independently on each timeline and
167 * so we may be called out-of-order.
169 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
170 list_del(&dep->wait_link);
171 if (dep->flags & I915_DEPENDENCY_ALLOC)
172 i915_dependency_free(i915, dep);
175 /* Remove ourselves from everyone who depends upon us */
176 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
177 list_del(&dep->signal_link);
178 if (dep->flags & I915_DEPENDENCY_ALLOC)
179 i915_dependency_free(i915, dep);
184 i915_priotree_init(struct i915_priotree *pt)
186 INIT_LIST_HEAD(&pt->signalers_list);
187 INIT_LIST_HEAD(&pt->waiters_list);
188 RB_CLEAR_NODE(&pt->node);
189 pt->priority = INT_MIN;
192 static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
194 struct intel_engine_cs *engine;
195 enum intel_engine_id id;
198 /* Carefully retire all requests without writing to the rings */
199 ret = i915_gem_wait_for_idle(i915,
200 I915_WAIT_INTERRUPTIBLE |
205 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
206 for_each_engine(engine, i915, id) {
207 struct i915_gem_timeline *timeline;
208 struct intel_timeline *tl = engine->timeline;
210 if (!i915_seqno_passed(seqno, tl->seqno)) {
211 /* spin until threads are complete */
212 while (intel_breadcrumbs_busy(engine))
216 /* Finally reset hw state */
218 intel_engine_init_global_seqno(engine, seqno);
220 list_for_each_entry(timeline, &i915->gt.timelines, link)
221 memset(timeline->engine[id].sync_seqno, 0,
222 sizeof(timeline->engine[id].sync_seqno));
228 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
230 struct drm_i915_private *dev_priv = to_i915(dev);
232 lockdep_assert_held(&dev_priv->drm.struct_mutex);
237 /* HWS page needs to be set less than what we
238 * will inject to ring
240 return reset_all_global_seqno(dev_priv, seqno - 1);
243 static int reserve_seqno(struct intel_engine_cs *engine)
245 u32 active = ++engine->timeline->inflight_seqnos;
246 u32 seqno = engine->timeline->seqno;
249 /* Reservation is fine until we need to wrap around */
250 if (likely(!add_overflows(seqno, active)))
253 ret = reset_all_global_seqno(engine->i915, 0);
255 engine->timeline->inflight_seqnos--;
262 static void unreserve_seqno(struct intel_engine_cs *engine)
264 GEM_BUG_ON(!engine->timeline->inflight_seqnos);
265 engine->timeline->inflight_seqnos--;
268 void i915_gem_retire_noop(struct i915_gem_active *active,
269 struct drm_i915_gem_request *request)
271 /* Space left intentionally blank */
274 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
276 struct intel_engine_cs *engine = request->engine;
277 struct i915_gem_active *active, *next;
279 lockdep_assert_held(&request->i915->drm.struct_mutex);
280 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
281 GEM_BUG_ON(!i915_gem_request_completed(request));
282 GEM_BUG_ON(!request->i915->gt.active_requests);
284 trace_i915_gem_request_retire(request);
286 spin_lock_irq(&engine->timeline->lock);
287 list_del_init(&request->link);
288 spin_unlock_irq(&engine->timeline->lock);
290 /* We know the GPU must have read the request to have
291 * sent us the seqno + interrupt, so use the position
292 * of tail of the request to update the last known position
295 * Note this requires that we are always called in request
298 list_del(&request->ring_link);
299 request->ring->head = request->postfix;
300 if (!--request->i915->gt.active_requests) {
301 GEM_BUG_ON(!request->i915->gt.awake);
302 mod_delayed_work(request->i915->wq,
303 &request->i915->gt.idle_work,
304 msecs_to_jiffies(100));
306 unreserve_seqno(request->engine);
308 /* Walk through the active list, calling retire on each. This allows
309 * objects to track their GPU activity and mark themselves as idle
310 * when their *last* active request is completed (updating state
311 * tracking lists for eviction, active references for GEM, etc).
313 * As the ->retire() may free the node, we decouple it first and
314 * pass along the auxiliary information (to avoid dereferencing
315 * the node after the callback).
317 list_for_each_entry_safe(active, next, &request->active_list, link) {
318 /* In microbenchmarks or focusing upon time inside the kernel,
319 * we may spend an inordinate amount of time simply handling
320 * the retirement of requests and processing their callbacks.
321 * Of which, this loop itself is particularly hot due to the
322 * cache misses when jumping around the list of i915_gem_active.
323 * So we try to keep this loop as streamlined as possible and
324 * also prefetch the next i915_gem_active to try and hide
325 * the likely cache miss.
329 INIT_LIST_HEAD(&active->link);
330 RCU_INIT_POINTER(active->request, NULL);
332 active->retire(active, request);
335 i915_gem_request_remove_from_client(request);
337 /* Retirement decays the ban score as it is a sign of ctx progress */
338 if (request->ctx->ban_score > 0)
339 request->ctx->ban_score--;
341 /* The backing object for the context is done after switching to the
342 * *next* context. Therefore we cannot retire the previous context until
343 * the next context has already started running. However, since we
344 * cannot take the required locks at i915_gem_request_submit() we
345 * defer the unpinning of the active context to now, retirement of
346 * the subsequent request.
348 if (engine->last_retired_context)
349 engine->context_unpin(engine, engine->last_retired_context);
350 engine->last_retired_context = request->ctx;
352 dma_fence_signal(&request->fence);
354 i915_priotree_fini(request->i915, &request->priotree);
355 i915_gem_request_put(request);
358 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
360 struct intel_engine_cs *engine = req->engine;
361 struct drm_i915_gem_request *tmp;
363 lockdep_assert_held(&req->i915->drm.struct_mutex);
364 GEM_BUG_ON(!i915_gem_request_completed(req));
366 if (list_empty(&req->link))
370 tmp = list_first_entry(&engine->timeline->requests,
373 i915_gem_request_retire(tmp);
374 } while (tmp != req);
377 static u32 timeline_get_seqno(struct intel_timeline *tl)
382 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
384 struct intel_engine_cs *engine = request->engine;
385 struct intel_timeline *timeline;
388 GEM_BUG_ON(!irqs_disabled());
389 lockdep_assert_held(&engine->timeline->lock);
391 trace_i915_gem_request_execute(request);
393 /* Transfer from per-context onto the global per-engine timeline */
394 timeline = engine->timeline;
395 GEM_BUG_ON(timeline == request->timeline);
397 seqno = timeline_get_seqno(timeline);
399 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
401 /* We may be recursing from the signal callback of another i915 fence */
402 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
403 request->global_seqno = seqno;
404 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
405 intel_engine_enable_signaling(request);
406 spin_unlock(&request->lock);
408 engine->emit_breadcrumb(request,
409 request->ring->vaddr + request->postfix);
411 spin_lock(&request->timeline->lock);
412 list_move_tail(&request->link, &timeline->requests);
413 spin_unlock(&request->timeline->lock);
415 wake_up_all(&request->execute);
418 void i915_gem_request_submit(struct drm_i915_gem_request *request)
420 struct intel_engine_cs *engine = request->engine;
423 /* Will be called from irq-context when using foreign fences. */
424 spin_lock_irqsave(&engine->timeline->lock, flags);
426 __i915_gem_request_submit(request);
428 spin_unlock_irqrestore(&engine->timeline->lock, flags);
431 void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
433 struct intel_engine_cs *engine = request->engine;
434 struct intel_timeline *timeline;
436 GEM_BUG_ON(!irqs_disabled());
437 lockdep_assert_held(&engine->timeline->lock);
439 /* Only unwind in reverse order, required so that the per-context list
440 * is kept in seqno/ring order.
442 GEM_BUG_ON(request->global_seqno != engine->timeline->seqno);
443 engine->timeline->seqno--;
445 /* We may be recursing from the signal callback of another i915 fence */
446 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
447 request->global_seqno = 0;
448 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
449 intel_engine_cancel_signaling(request);
450 spin_unlock(&request->lock);
452 /* Transfer back from the global per-engine timeline to per-context */
453 timeline = request->timeline;
454 GEM_BUG_ON(timeline == engine->timeline);
456 spin_lock(&timeline->lock);
457 list_move(&request->link, &timeline->requests);
458 spin_unlock(&timeline->lock);
460 /* We don't need to wake_up any waiters on request->execute, they
461 * will get woken by any other event or us re-adding this request
462 * to the engine timeline (__i915_gem_request_submit()). The waiters
463 * should be quite adapt at finding that the request now has a new
464 * global_seqno to the one they went to sleep on.
468 void i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
470 struct intel_engine_cs *engine = request->engine;
473 /* Will be called from irq-context when using foreign fences. */
474 spin_lock_irqsave(&engine->timeline->lock, flags);
476 __i915_gem_request_unsubmit(request);
478 spin_unlock_irqrestore(&engine->timeline->lock, flags);
481 static int __i915_sw_fence_call
482 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
484 struct drm_i915_gem_request *request =
485 container_of(fence, typeof(*request), submit);
489 trace_i915_gem_request_submit(request);
490 request->engine->submit_request(request);
494 i915_gem_request_put(request);
502 * i915_gem_request_alloc - allocate a request structure
504 * @engine: engine that we wish to issue the request on.
505 * @ctx: context that the request will be associated with.
506 * This can be NULL if the request is not directly related to
507 * any specific user context, in which case this function will
508 * choose an appropriate context to use.
510 * Returns a pointer to the allocated request if successful,
511 * or an error code if not.
513 struct drm_i915_gem_request *
514 i915_gem_request_alloc(struct intel_engine_cs *engine,
515 struct i915_gem_context *ctx)
517 struct drm_i915_private *dev_priv = engine->i915;
518 struct drm_i915_gem_request *req;
521 lockdep_assert_held(&dev_priv->drm.struct_mutex);
523 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
524 * EIO if the GPU is already wedged.
526 if (i915_terminally_wedged(&dev_priv->gpu_error))
527 return ERR_PTR(-EIO);
529 /* Pinning the contexts may generate requests in order to acquire
530 * GGTT space, so do this first before we reserve a seqno for
533 ret = engine->context_pin(engine, ctx);
537 ret = reserve_seqno(engine);
541 /* Move the oldest request to the slab-cache (if not in use!) */
542 req = list_first_entry_or_null(&engine->timeline->requests,
544 if (req && i915_gem_request_completed(req))
545 i915_gem_request_retire(req);
547 /* Beware: Dragons be flying overhead.
549 * We use RCU to look up requests in flight. The lookups may
550 * race with the request being allocated from the slab freelist.
551 * That is the request we are writing to here, may be in the process
552 * of being read by __i915_gem_active_get_rcu(). As such,
553 * we have to be very careful when overwriting the contents. During
554 * the RCU lookup, we change chase the request->engine pointer,
555 * read the request->global_seqno and increment the reference count.
557 * The reference count is incremented atomically. If it is zero,
558 * the lookup knows the request is unallocated and complete. Otherwise,
559 * it is either still in use, or has been reallocated and reset
560 * with dma_fence_init(). This increment is safe for release as we
561 * check that the request we have a reference to and matches the active
564 * Before we increment the refcount, we chase the request->engine
565 * pointer. We must not call kmem_cache_zalloc() or else we set
566 * that pointer to NULL and cause a crash during the lookup. If
567 * we see the request is completed (based on the value of the
568 * old engine and seqno), the lookup is complete and reports NULL.
569 * If we decide the request is not completed (new engine or seqno),
570 * then we grab a reference and double check that it is still the
571 * active request - which it won't be and restart the lookup.
573 * Do not use kmem_cache_zalloc() here!
575 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
581 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
582 GEM_BUG_ON(req->timeline == engine->timeline);
584 spin_lock_init(&req->lock);
585 dma_fence_init(&req->fence,
588 req->timeline->fence_context,
589 timeline_get_seqno(req->timeline));
591 /* We bump the ref for the fence chain */
592 i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
593 init_waitqueue_head(&req->execute);
595 i915_priotree_init(&req->priotree);
597 INIT_LIST_HEAD(&req->active_list);
598 req->i915 = dev_priv;
599 req->engine = engine;
602 /* No zalloc, must clear what we need by hand */
603 req->global_seqno = 0;
604 req->file_priv = NULL;
608 * Reserve space in the ring buffer for all the commands required to
609 * eventually emit this request. This is to guarantee that the
610 * i915_add_request() call can't fail. Note that the reserve may need
611 * to be redone if the request is not actually submitted straight
612 * away, e.g. because a GPU scheduler has deferred it.
614 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
615 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
617 ret = engine->request_alloc(req);
621 /* Record the position of the start of the request so that
622 * should we detect the updated seqno part-way through the
623 * GPU processing the request, we never over-estimate the
624 * position of the head.
626 req->head = req->ring->tail;
628 /* Check that we didn't interrupt ourselves with a new request */
629 GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
633 /* Make sure we didn't add ourselves to external state before freeing */
634 GEM_BUG_ON(!list_empty(&req->active_list));
635 GEM_BUG_ON(!list_empty(&req->priotree.signalers_list));
636 GEM_BUG_ON(!list_empty(&req->priotree.waiters_list));
638 kmem_cache_free(dev_priv->requests, req);
640 unreserve_seqno(engine);
642 engine->context_unpin(engine, ctx);
647 i915_gem_request_await_request(struct drm_i915_gem_request *to,
648 struct drm_i915_gem_request *from)
653 GEM_BUG_ON(to == from);
655 if (to->engine->schedule) {
656 ret = i915_priotree_add_dependency(to->i915,
663 if (to->timeline == from->timeline)
666 if (to->engine == from->engine) {
667 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
670 return ret < 0 ? ret : 0;
673 seqno = i915_gem_request_global_seqno(from);
675 ret = i915_sw_fence_await_dma_fence(&to->submit,
678 return ret < 0 ? ret : 0;
681 if (seqno <= to->timeline->sync_seqno[from->engine->id])
684 trace_i915_gem_ring_sync_to(to, from);
685 if (!i915.semaphores) {
686 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
687 ret = i915_sw_fence_await_dma_fence(&to->submit,
694 ret = to->engine->semaphore.sync_to(to, from);
699 to->timeline->sync_seqno[from->engine->id] = seqno;
704 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
705 struct dma_fence *fence)
707 struct dma_fence_array *array;
711 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
714 if (dma_fence_is_i915(fence))
715 return i915_gem_request_await_request(req, to_request(fence));
717 if (!dma_fence_is_array(fence)) {
718 ret = i915_sw_fence_await_dma_fence(&req->submit,
719 fence, I915_FENCE_TIMEOUT,
721 return ret < 0 ? ret : 0;
724 /* Note that if the fence-array was created in signal-on-any mode,
725 * we should *not* decompose it into its individual fences. However,
726 * we don't currently store which mode the fence-array is operating
727 * in. Fortunately, the only user of signal-on-any is private to
728 * amdgpu and we should not see any incoming fence-array from
729 * sync-file being in signal-on-any mode.
732 array = to_dma_fence_array(fence);
733 for (i = 0; i < array->num_fences; i++) {
734 struct dma_fence *child = array->fences[i];
736 if (dma_fence_is_i915(child))
737 ret = i915_gem_request_await_request(req,
740 ret = i915_sw_fence_await_dma_fence(&req->submit,
741 child, I915_FENCE_TIMEOUT,
751 * i915_gem_request_await_object - set this request to (async) wait upon a bo
753 * @to: request we are wishing to use
754 * @obj: object which may be in use on another ring.
756 * This code is meant to abstract object synchronization with the GPU.
757 * Conceptually we serialise writes between engines inside the GPU.
758 * We only allow one engine to write into a buffer at any time, but
759 * multiple readers. To ensure each has a coherent view of memory, we must:
761 * - If there is an outstanding write request to the object, the new
762 * request must wait for it to complete (either CPU or in hw, requests
763 * on the same ring will be naturally ordered).
765 * - If we are a write request (pending_write_domain is set), the new
766 * request must wait for outstanding read requests to complete.
768 * Returns 0 if successful, else propagates up the lower layer error.
771 i915_gem_request_await_object(struct drm_i915_gem_request *to,
772 struct drm_i915_gem_object *obj,
775 struct dma_fence *excl;
779 struct dma_fence **shared;
780 unsigned int count, i;
782 ret = reservation_object_get_fences_rcu(obj->resv,
783 &excl, &count, &shared);
787 for (i = 0; i < count; i++) {
788 ret = i915_gem_request_await_dma_fence(to, shared[i]);
792 dma_fence_put(shared[i]);
795 for (; i < count; i++)
796 dma_fence_put(shared[i]);
799 excl = reservation_object_get_excl_rcu(obj->resv);
804 ret = i915_gem_request_await_dma_fence(to, excl);
812 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
814 struct drm_i915_private *dev_priv = engine->i915;
816 if (dev_priv->gt.awake)
819 GEM_BUG_ON(!dev_priv->gt.active_requests);
821 intel_runtime_pm_get_noresume(dev_priv);
822 dev_priv->gt.awake = true;
824 intel_enable_gt_powersave(dev_priv);
825 i915_update_gfx_val(dev_priv);
826 if (INTEL_GEN(dev_priv) >= 6)
827 gen6_rps_busy(dev_priv);
829 queue_delayed_work(dev_priv->wq,
830 &dev_priv->gt.retire_work,
831 round_jiffies_up_relative(HZ));
835 * NB: This function is not allowed to fail. Doing so would mean the the
836 * request is not being tracked for completion but the work itself is
837 * going to happen on the hardware. This would be a Bad Thing(tm).
839 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
841 struct intel_engine_cs *engine = request->engine;
842 struct intel_ring *ring = request->ring;
843 struct intel_timeline *timeline = request->timeline;
844 struct drm_i915_gem_request *prev;
848 lockdep_assert_held(&request->i915->drm.struct_mutex);
849 trace_i915_gem_request_add(request);
851 /* Make sure that no request gazumped us - if it was allocated after
852 * our i915_gem_request_alloc() and called __i915_add_request() before
853 * us, the timeline will hold its seqno which is later than ours.
855 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
858 * To ensure that this call will not fail, space for its emissions
859 * should already have been reserved in the ring buffer. Let the ring
860 * know that it is time to use that space up.
862 request->reserved_space = 0;
865 * Emit any outstanding flushes - execbuf can fail to emit the flush
866 * after having emitted the batchbuffer command. Hence we need to fix
867 * things up similar to emitting the lazy request. The difference here
868 * is that the flush _must_ happen before the next request, no matter
872 err = engine->emit_flush(request, EMIT_FLUSH);
874 /* Not allowed to fail! */
875 WARN(err, "engine->emit_flush() failed: %d!\n", err);
878 /* Record the position of the start of the breadcrumb so that
879 * should we detect the updated seqno part-way through the
880 * GPU processing the request, we never over-estimate the
881 * position of the ring's HEAD.
883 cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
884 GEM_BUG_ON(IS_ERR(cs));
885 request->postfix = intel_ring_offset(request, cs);
887 /* Seal the request and mark it as pending execution. Note that
888 * we may inspect this state, without holding any locks, during
889 * hangcheck. Hence we apply the barrier to ensure that we do not
890 * see a more recent value in the hws than we are tracking.
893 prev = i915_gem_active_raw(&timeline->last_request,
894 &request->i915->drm.struct_mutex);
896 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
898 if (engine->schedule)
899 __i915_priotree_add_dependency(&request->priotree,
905 spin_lock_irq(&timeline->lock);
906 list_add_tail(&request->link, &timeline->requests);
907 spin_unlock_irq(&timeline->lock);
909 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
910 i915_gem_active_set(&timeline->last_request, request);
912 list_add_tail(&request->ring_link, &ring->request_list);
913 request->emitted_jiffies = jiffies;
915 if (!request->i915->gt.active_requests++)
916 i915_gem_mark_busy(engine);
918 /* Let the backend know a new request has arrived that may need
919 * to adjust the existing execution schedule due to a high priority
920 * request - i.e. we may want to preempt the current request in order
921 * to run a high priority dependency chain *before* we can execute this
924 * This is called before the request is ready to run so that we can
925 * decide whether to preempt the entire chain so that it is ready to
926 * run at the earliest possible convenience.
928 if (engine->schedule)
929 engine->schedule(request, request->ctx->priority);
932 i915_sw_fence_commit(&request->submit);
933 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
936 static unsigned long local_clock_us(unsigned int *cpu)
940 /* Cheaply and approximately convert from nanoseconds to microseconds.
941 * The result and subsequent calculations are also defined in the same
942 * approximate microseconds units. The principal source of timing
943 * error here is from the simple truncation.
945 * Note that local_clock() is only defined wrt to the current CPU;
946 * the comparisons are no longer valid if we switch CPUs. Instead of
947 * blocking preemption for the entire busywait, we can detect the CPU
948 * switch and use that as indicator of system load and a reason to
949 * stop busywaiting, see busywait_stop().
952 t = local_clock() >> 10;
958 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
960 unsigned int this_cpu;
962 if (time_after(local_clock_us(&this_cpu), timeout))
965 return this_cpu != cpu;
968 bool __i915_spin_request(const struct drm_i915_gem_request *req,
969 u32 seqno, int state, unsigned long timeout_us)
971 struct intel_engine_cs *engine = req->engine;
972 unsigned int irq, cpu;
974 /* When waiting for high frequency requests, e.g. during synchronous
975 * rendering split between the CPU and GPU, the finite amount of time
976 * required to set up the irq and wait upon it limits the response
977 * rate. By busywaiting on the request completion for a short while we
978 * can service the high frequency waits as quick as possible. However,
979 * if it is a slow request, we want to sleep as quickly as possible.
980 * The tradeoff between waiting and sleeping is roughly the time it
981 * takes to sleep on a request, on the order of a microsecond.
984 irq = atomic_read(&engine->irq_count);
985 timeout_us += local_clock_us(&cpu);
987 if (seqno != i915_gem_request_global_seqno(req))
990 if (i915_seqno_passed(intel_engine_get_seqno(req->engine),
994 /* Seqno are meant to be ordered *before* the interrupt. If
995 * we see an interrupt without a corresponding seqno advance,
996 * assume we won't see one in the near future but require
997 * the engine->seqno_barrier() to fixup coherency.
999 if (atomic_read(&engine->irq_count) != irq)
1002 if (signal_pending_state(state, current))
1005 if (busywait_stop(timeout_us, cpu))
1009 } while (!need_resched());
1014 static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *request)
1016 if (likely(!i915_reset_handoff(&request->i915->gpu_error)))
1019 __set_current_state(TASK_RUNNING);
1020 i915_reset(request->i915);
1025 * i915_wait_request - wait until execution of request has finished
1026 * @req: the request to wait upon
1027 * @flags: how to wait
1028 * @timeout: how long to wait in jiffies
1030 * i915_wait_request() waits for the request to be completed, for a
1031 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1034 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1035 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1036 * must not specify that the wait is locked.
1038 * Returns the remaining time (in jiffies) if the request completed, which may
1039 * be zero or -ETIME if the request is unfinished after the timeout expires.
1040 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1041 * pending before the request completes.
1043 long i915_wait_request(struct drm_i915_gem_request *req,
1047 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1048 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1049 wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
1050 DEFINE_WAIT_FUNC(reset, default_wake_function);
1051 DEFINE_WAIT_FUNC(exec, default_wake_function);
1052 struct intel_wait wait;
1055 #if IS_ENABLED(CONFIG_LOCKDEP)
1056 GEM_BUG_ON(debug_locks &&
1057 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
1058 !!(flags & I915_WAIT_LOCKED));
1060 GEM_BUG_ON(timeout < 0);
1062 if (i915_gem_request_completed(req))
1068 trace_i915_gem_request_wait_begin(req, flags);
1070 add_wait_queue(&req->execute, &exec);
1071 if (flags & I915_WAIT_LOCKED)
1072 add_wait_queue(errq, &reset);
1074 intel_wait_init(&wait, req);
1078 set_current_state(state);
1079 if (intel_wait_update_request(&wait, req))
1082 if (flags & I915_WAIT_LOCKED &&
1083 __i915_wait_request_check_and_reset(req))
1086 if (signal_pending_state(state, current)) {
1087 timeout = -ERESTARTSYS;
1096 timeout = io_schedule_timeout(timeout);
1099 GEM_BUG_ON(!intel_wait_has_seqno(&wait));
1100 GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
1102 /* Optimistic short spin before touching IRQs */
1103 if (i915_spin_request(req, state, 5))
1106 set_current_state(state);
1107 if (intel_engine_add_wait(req->engine, &wait))
1108 /* In order to check that we haven't missed the interrupt
1109 * as we enabled it, we need to kick ourselves to do a
1110 * coherent check on the seqno before we sleep.
1114 if (flags & I915_WAIT_LOCKED)
1115 __i915_wait_request_check_and_reset(req);
1118 if (signal_pending_state(state, current)) {
1119 timeout = -ERESTARTSYS;
1128 timeout = io_schedule_timeout(timeout);
1130 if (intel_wait_complete(&wait) &&
1131 intel_wait_check_request(&wait, req))
1134 set_current_state(state);
1137 /* Carefully check if the request is complete, giving time
1138 * for the seqno to be visible following the interrupt.
1139 * We also have to check in case we are kicked by the GPU
1140 * reset in order to drop the struct_mutex.
1142 if (__i915_request_irq_complete(req))
1145 /* If the GPU is hung, and we hold the lock, reset the GPU
1146 * and then check for completion. On a full reset, the engine's
1147 * HW seqno will be advanced passed us and we are complete.
1148 * If we do a partial reset, we have to wait for the GPU to
1149 * resume and update the breadcrumb.
1151 * If we don't hold the mutex, we can just wait for the worker
1152 * to come along and update the breadcrumb (either directly
1153 * itself, or indirectly by recovering the GPU).
1155 if (flags & I915_WAIT_LOCKED &&
1156 __i915_wait_request_check_and_reset(req))
1159 /* Only spin if we know the GPU is processing this request */
1160 if (i915_spin_request(req, state, 2))
1163 if (!intel_wait_check_request(&wait, req)) {
1164 intel_engine_remove_wait(req->engine, &wait);
1169 intel_engine_remove_wait(req->engine, &wait);
1171 __set_current_state(TASK_RUNNING);
1172 if (flags & I915_WAIT_LOCKED)
1173 remove_wait_queue(errq, &reset);
1174 remove_wait_queue(&req->execute, &exec);
1175 trace_i915_gem_request_wait_end(req);
1180 static void engine_retire_requests(struct intel_engine_cs *engine)
1182 struct drm_i915_gem_request *request, *next;
1183 u32 seqno = intel_engine_get_seqno(engine);
1186 spin_lock_irq(&engine->timeline->lock);
1187 list_for_each_entry_safe(request, next,
1188 &engine->timeline->requests, link) {
1189 if (!i915_seqno_passed(seqno, request->global_seqno))
1192 list_move_tail(&request->link, &retire);
1194 spin_unlock_irq(&engine->timeline->lock);
1196 list_for_each_entry_safe(request, next, &retire, link)
1197 i915_gem_request_retire(request);
1200 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1202 struct intel_engine_cs *engine;
1203 enum intel_engine_id id;
1205 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1207 if (!dev_priv->gt.active_requests)
1210 for_each_engine(engine, dev_priv, id)
1211 engine_retire_requests(engine);
1214 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1215 #include "selftests/mock_request.c"
1216 #include "selftests/i915_gem_request.c"