2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
30 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
35 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
37 /* Timelines are bound by eviction to a VM. However, since
38 * we only have a global seqno at the moment, we only have
39 * a single timeline. Note that each timeline will have
40 * multiple execution contexts (fence contexts) as we allow
41 * engines within a single timeline to execute in parallel.
43 return to_request(fence)->timeline->common->name;
46 static bool i915_fence_signaled(struct dma_fence *fence)
48 return i915_gem_request_completed(to_request(fence));
51 static bool i915_fence_enable_signaling(struct dma_fence *fence)
53 if (i915_fence_signaled(fence))
56 intel_engine_enable_signaling(to_request(fence));
60 static signed long i915_fence_wait(struct dma_fence *fence,
64 return i915_wait_request(to_request(fence), interruptible, timeout);
67 static void i915_fence_value_str(struct dma_fence *fence, char *str, int size)
69 snprintf(str, size, "%u", fence->seqno);
72 static void i915_fence_timeline_value_str(struct dma_fence *fence, char *str,
75 snprintf(str, size, "%u",
76 intel_engine_get_seqno(to_request(fence)->engine));
79 static void i915_fence_release(struct dma_fence *fence)
81 struct drm_i915_gem_request *req = to_request(fence);
83 kmem_cache_free(req->i915->requests, req);
86 const struct dma_fence_ops i915_fence_ops = {
87 .get_driver_name = i915_fence_get_driver_name,
88 .get_timeline_name = i915_fence_get_timeline_name,
89 .enable_signaling = i915_fence_enable_signaling,
90 .signaled = i915_fence_signaled,
91 .wait = i915_fence_wait,
92 .release = i915_fence_release,
93 .fence_value_str = i915_fence_value_str,
94 .timeline_value_str = i915_fence_timeline_value_str,
97 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
98 struct drm_file *file)
100 struct drm_i915_private *dev_private;
101 struct drm_i915_file_private *file_priv;
103 WARN_ON(!req || !file || req->file_priv);
111 dev_private = req->i915;
112 file_priv = file->driver_priv;
114 spin_lock(&file_priv->mm.lock);
115 req->file_priv = file_priv;
116 list_add_tail(&req->client_list, &file_priv->mm.request_list);
117 spin_unlock(&file_priv->mm.lock);
123 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
125 struct drm_i915_file_private *file_priv = request->file_priv;
130 spin_lock(&file_priv->mm.lock);
131 list_del(&request->client_list);
132 request->file_priv = NULL;
133 spin_unlock(&file_priv->mm.lock);
136 void i915_gem_retire_noop(struct i915_gem_active *active,
137 struct drm_i915_gem_request *request)
139 /* Space left intentionally blank */
142 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
144 struct i915_gem_active *active, *next;
146 lockdep_assert_held(&request->i915->drm.struct_mutex);
147 GEM_BUG_ON(!i915_gem_request_completed(request));
149 trace_i915_gem_request_retire(request);
150 list_del_init(&request->link);
152 /* We know the GPU must have read the request to have
153 * sent us the seqno + interrupt, so use the position
154 * of tail of the request to update the last known position
157 * Note this requires that we are always called in request
160 list_del(&request->ring_link);
161 request->ring->last_retired_head = request->postfix;
163 /* Walk through the active list, calling retire on each. This allows
164 * objects to track their GPU activity and mark themselves as idle
165 * when their *last* active request is completed (updating state
166 * tracking lists for eviction, active references for GEM, etc).
168 * As the ->retire() may free the node, we decouple it first and
169 * pass along the auxiliary information (to avoid dereferencing
170 * the node after the callback).
172 list_for_each_entry_safe(active, next, &request->active_list, link) {
173 /* In microbenchmarks or focusing upon time inside the kernel,
174 * we may spend an inordinate amount of time simply handling
175 * the retirement of requests and processing their callbacks.
176 * Of which, this loop itself is particularly hot due to the
177 * cache misses when jumping around the list of i915_gem_active.
178 * So we try to keep this loop as streamlined as possible and
179 * also prefetch the next i915_gem_active to try and hide
180 * the likely cache miss.
184 INIT_LIST_HEAD(&active->link);
185 RCU_INIT_POINTER(active->request, NULL);
187 active->retire(active, request);
190 i915_gem_request_remove_from_client(request);
192 if (request->previous_context) {
193 if (i915.enable_execlists)
194 intel_lr_context_unpin(request->previous_context,
198 i915_gem_context_put(request->ctx);
200 dma_fence_signal(&request->fence);
201 i915_gem_request_put(request);
204 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
206 struct intel_engine_cs *engine = req->engine;
207 struct drm_i915_gem_request *tmp;
209 lockdep_assert_held(&req->i915->drm.struct_mutex);
210 if (list_empty(&req->link))
214 tmp = list_first_entry(&engine->timeline->requests,
217 i915_gem_request_retire(tmp);
218 } while (tmp != req);
221 static int i915_gem_check_wedge(struct drm_i915_private *dev_priv)
223 struct i915_gpu_error *error = &dev_priv->gpu_error;
225 if (i915_terminally_wedged(error))
228 if (i915_reset_in_progress(error)) {
229 /* Non-interruptible callers can't handle -EAGAIN, hence return
230 * -EIO unconditionally for these.
232 if (!dev_priv->mm.interruptible)
241 static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
243 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
244 struct intel_engine_cs *engine;
245 enum intel_engine_id id;
248 /* Carefully retire all requests without writing to the rings */
249 ret = i915_gem_wait_for_idle(i915,
250 I915_WAIT_INTERRUPTIBLE |
255 i915_gem_retire_requests(i915);
257 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
258 if (!i915_seqno_passed(seqno, timeline->next_seqno)) {
259 while (intel_kick_waiters(i915) || intel_kick_signalers(i915))
264 /* Finally reset hw state */
265 for_each_engine(engine, i915, id)
266 intel_engine_init_global_seqno(engine, seqno);
268 list_for_each_entry(timeline, &i915->gt.timelines, link) {
269 for_each_engine(engine, i915, id) {
270 struct intel_timeline *tl = &timeline->engine[id];
272 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
279 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
281 struct drm_i915_private *dev_priv = to_i915(dev);
284 lockdep_assert_held(&dev_priv->drm.struct_mutex);
289 /* HWS page needs to be set less than what we
290 * will inject to ring
292 ret = i915_gem_init_global_seqno(dev_priv, seqno - 1);
296 dev_priv->gt.global_timeline.next_seqno = seqno;
300 static int i915_gem_get_global_seqno(struct drm_i915_private *dev_priv,
303 struct i915_gem_timeline *tl = &dev_priv->gt.global_timeline;
305 /* reserve 0 for non-seqno */
306 if (unlikely(tl->next_seqno == 0)) {
309 ret = i915_gem_init_global_seqno(dev_priv, 0);
316 *seqno = tl->next_seqno++;
320 static int __i915_sw_fence_call
321 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
323 struct drm_i915_gem_request *request =
324 container_of(fence, typeof(*request), submit);
325 struct intel_engine_cs *engine = request->engine;
327 if (state != FENCE_COMPLETE)
330 /* Will be called from irq-context when using foreign DMA fences */
332 engine->timeline->last_submitted_seqno = request->fence.seqno;
334 engine->emit_breadcrumb(request,
335 request->ring->vaddr + request->postfix);
336 engine->submit_request(request);
342 * i915_gem_request_alloc - allocate a request structure
344 * @engine: engine that we wish to issue the request on.
345 * @ctx: context that the request will be associated with.
346 * This can be NULL if the request is not directly related to
347 * any specific user context, in which case this function will
348 * choose an appropriate context to use.
350 * Returns a pointer to the allocated request if successful,
351 * or an error code if not.
353 struct drm_i915_gem_request *
354 i915_gem_request_alloc(struct intel_engine_cs *engine,
355 struct i915_gem_context *ctx)
357 struct drm_i915_private *dev_priv = engine->i915;
358 struct drm_i915_gem_request *req;
362 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
363 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
366 ret = i915_gem_check_wedge(dev_priv);
370 /* Move the oldest request to the slab-cache (if not in use!) */
371 req = list_first_entry_or_null(&engine->timeline->requests,
373 if (req && i915_gem_request_completed(req))
374 i915_gem_request_retire(req);
376 /* Beware: Dragons be flying overhead.
378 * We use RCU to look up requests in flight. The lookups may
379 * race with the request being allocated from the slab freelist.
380 * That is the request we are writing to here, may be in the process
381 * of being read by __i915_gem_active_get_rcu(). As such,
382 * we have to be very careful when overwriting the contents. During
383 * the RCU lookup, we change chase the request->engine pointer,
384 * read the request->global_seqno and increment the reference count.
386 * The reference count is incremented atomically. If it is zero,
387 * the lookup knows the request is unallocated and complete. Otherwise,
388 * it is either still in use, or has been reallocated and reset
389 * with dma_fence_init(). This increment is safe for release as we
390 * check that the request we have a reference to and matches the active
393 * Before we increment the refcount, we chase the request->engine
394 * pointer. We must not call kmem_cache_zalloc() or else we set
395 * that pointer to NULL and cause a crash during the lookup. If
396 * we see the request is completed (based on the value of the
397 * old engine and seqno), the lookup is complete and reports NULL.
398 * If we decide the request is not completed (new engine or seqno),
399 * then we grab a reference and double check that it is still the
400 * active request - which it won't be and restart the lookup.
402 * Do not use kmem_cache_zalloc() here!
404 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
406 return ERR_PTR(-ENOMEM);
408 ret = i915_gem_get_global_seqno(dev_priv, &seqno);
412 req->timeline = engine->timeline;
414 spin_lock_init(&req->lock);
415 dma_fence_init(&req->fence,
418 req->timeline->fence_context,
421 i915_sw_fence_init(&req->submit, submit_notify);
423 INIT_LIST_HEAD(&req->active_list);
424 req->i915 = dev_priv;
425 req->engine = engine;
426 req->global_seqno = seqno;
427 req->ctx = i915_gem_context_get(ctx);
429 /* No zalloc, must clear what we need by hand */
430 req->previous_context = NULL;
431 req->file_priv = NULL;
435 * Reserve space in the ring buffer for all the commands required to
436 * eventually emit this request. This is to guarantee that the
437 * i915_add_request() call can't fail. Note that the reserve may need
438 * to be redone if the request is not actually submitted straight
439 * away, e.g. because a GPU scheduler has deferred it.
441 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
442 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
444 if (i915.enable_execlists)
445 ret = intel_logical_ring_alloc_request_extras(req);
447 ret = intel_ring_alloc_request_extras(req);
451 /* Record the position of the start of the request so that
452 * should we detect the updated seqno part-way through the
453 * GPU processing the request, we never over-estimate the
454 * position of the head.
456 req->head = req->ring->tail;
461 i915_gem_context_put(ctx);
463 kmem_cache_free(dev_priv->requests, req);
468 i915_gem_request_await_request(struct drm_i915_gem_request *to,
469 struct drm_i915_gem_request *from)
473 GEM_BUG_ON(to == from);
475 if (to->timeline == from->timeline)
478 if (to->engine == from->engine) {
479 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
482 return ret < 0 ? ret : 0;
485 if (!from->global_seqno) {
486 ret = i915_sw_fence_await_dma_fence(&to->submit,
489 return ret < 0 ? ret : 0;
492 if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id])
495 trace_i915_gem_ring_sync_to(to, from);
496 if (!i915.semaphores) {
497 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
498 ret = i915_sw_fence_await_dma_fence(&to->submit,
505 ret = to->engine->semaphore.sync_to(to, from);
510 to->timeline->sync_seqno[from->engine->id] = from->global_seqno;
515 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
516 struct dma_fence *fence)
518 struct dma_fence_array *array;
522 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
525 if (dma_fence_is_i915(fence))
526 return i915_gem_request_await_request(req, to_request(fence));
528 if (!dma_fence_is_array(fence)) {
529 ret = i915_sw_fence_await_dma_fence(&req->submit,
530 fence, I915_FENCE_TIMEOUT,
532 return ret < 0 ? ret : 0;
535 /* Note that if the fence-array was created in signal-on-any mode,
536 * we should *not* decompose it into its individual fences. However,
537 * we don't currently store which mode the fence-array is operating
538 * in. Fortunately, the only user of signal-on-any is private to
539 * amdgpu and we should not see any incoming fence-array from
540 * sync-file being in signal-on-any mode.
543 array = to_dma_fence_array(fence);
544 for (i = 0; i < array->num_fences; i++) {
545 struct dma_fence *child = array->fences[i];
547 if (dma_fence_is_i915(child))
548 ret = i915_gem_request_await_request(req,
551 ret = i915_sw_fence_await_dma_fence(&req->submit,
552 child, I915_FENCE_TIMEOUT,
562 * i915_gem_request_await_object - set this request to (async) wait upon a bo
564 * @to: request we are wishing to use
565 * @obj: object which may be in use on another ring.
567 * This code is meant to abstract object synchronization with the GPU.
568 * Conceptually we serialise writes between engines inside the GPU.
569 * We only allow one engine to write into a buffer at any time, but
570 * multiple readers. To ensure each has a coherent view of memory, we must:
572 * - If there is an outstanding write request to the object, the new
573 * request must wait for it to complete (either CPU or in hw, requests
574 * on the same ring will be naturally ordered).
576 * - If we are a write request (pending_write_domain is set), the new
577 * request must wait for outstanding read requests to complete.
579 * Returns 0 if successful, else propagates up the lower layer error.
582 i915_gem_request_await_object(struct drm_i915_gem_request *to,
583 struct drm_i915_gem_object *obj,
586 struct dma_fence *excl;
590 struct dma_fence **shared;
591 unsigned int count, i;
593 ret = reservation_object_get_fences_rcu(obj->resv,
594 &excl, &count, &shared);
598 for (i = 0; i < count; i++) {
599 ret = i915_gem_request_await_dma_fence(to, shared[i]);
603 dma_fence_put(shared[i]);
606 for (; i < count; i++)
607 dma_fence_put(shared[i]);
610 excl = reservation_object_get_excl_rcu(obj->resv);
615 ret = i915_gem_request_await_dma_fence(to, excl);
623 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
625 struct drm_i915_private *dev_priv = engine->i915;
627 dev_priv->gt.active_engines |= intel_engine_flag(engine);
628 if (dev_priv->gt.awake)
631 intel_runtime_pm_get_noresume(dev_priv);
632 dev_priv->gt.awake = true;
634 intel_enable_gt_powersave(dev_priv);
635 i915_update_gfx_val(dev_priv);
636 if (INTEL_GEN(dev_priv) >= 6)
637 gen6_rps_busy(dev_priv);
639 queue_delayed_work(dev_priv->wq,
640 &dev_priv->gt.retire_work,
641 round_jiffies_up_relative(HZ));
645 * NB: This function is not allowed to fail. Doing so would mean the the
646 * request is not being tracked for completion but the work itself is
647 * going to happen on the hardware. This would be a Bad Thing(tm).
649 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
651 struct intel_engine_cs *engine = request->engine;
652 struct intel_ring *ring = request->ring;
653 struct intel_timeline *timeline = request->timeline;
654 struct drm_i915_gem_request *prev;
657 lockdep_assert_held(&request->i915->drm.struct_mutex);
658 trace_i915_gem_request_add(request);
661 * To ensure that this call will not fail, space for its emissions
662 * should already have been reserved in the ring buffer. Let the ring
663 * know that it is time to use that space up.
665 request->reserved_space = 0;
668 * Emit any outstanding flushes - execbuf can fail to emit the flush
669 * after having emitted the batchbuffer command. Hence we need to fix
670 * things up similar to emitting the lazy request. The difference here
671 * is that the flush _must_ happen before the next request, no matter
675 err = engine->emit_flush(request, EMIT_FLUSH);
677 /* Not allowed to fail! */
678 WARN(err, "engine->emit_flush() failed: %d!\n", err);
681 /* Record the position of the start of the breadcrumb so that
682 * should we detect the updated seqno part-way through the
683 * GPU processing the request, we never over-estimate the
684 * position of the ring's HEAD.
686 err = intel_ring_begin(request, engine->emit_breadcrumb_sz);
688 request->postfix = ring->tail;
689 ring->tail += engine->emit_breadcrumb_sz * sizeof(u32);
691 /* Seal the request and mark it as pending execution. Note that
692 * we may inspect this state, without holding any locks, during
693 * hangcheck. Hence we apply the barrier to ensure that we do not
694 * see a more recent value in the hws than we are tracking.
697 prev = i915_gem_active_raw(&timeline->last_request,
698 &request->i915->drm.struct_mutex);
700 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
703 request->emitted_jiffies = jiffies;
704 request->previous_seqno = timeline->last_pending_seqno;
705 timeline->last_pending_seqno = request->fence.seqno;
706 i915_gem_active_set(&timeline->last_request, request);
707 list_add_tail(&request->link, &timeline->requests);
708 list_add_tail(&request->ring_link, &ring->request_list);
710 i915_gem_mark_busy(engine);
713 i915_sw_fence_commit(&request->submit);
714 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
717 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
721 spin_lock_irqsave(&q->lock, flags);
722 if (list_empty(&wait->task_list))
723 __add_wait_queue(q, wait);
724 spin_unlock_irqrestore(&q->lock, flags);
727 static unsigned long local_clock_us(unsigned int *cpu)
731 /* Cheaply and approximately convert from nanoseconds to microseconds.
732 * The result and subsequent calculations are also defined in the same
733 * approximate microseconds units. The principal source of timing
734 * error here is from the simple truncation.
736 * Note that local_clock() is only defined wrt to the current CPU;
737 * the comparisons are no longer valid if we switch CPUs. Instead of
738 * blocking preemption for the entire busywait, we can detect the CPU
739 * switch and use that as indicator of system load and a reason to
740 * stop busywaiting, see busywait_stop().
743 t = local_clock() >> 10;
749 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
751 unsigned int this_cpu;
753 if (time_after(local_clock_us(&this_cpu), timeout))
756 return this_cpu != cpu;
759 bool __i915_spin_request(const struct drm_i915_gem_request *req,
760 int state, unsigned long timeout_us)
764 /* When waiting for high frequency requests, e.g. during synchronous
765 * rendering split between the CPU and GPU, the finite amount of time
766 * required to set up the irq and wait upon it limits the response
767 * rate. By busywaiting on the request completion for a short while we
768 * can service the high frequency waits as quick as possible. However,
769 * if it is a slow request, we want to sleep as quickly as possible.
770 * The tradeoff between waiting and sleeping is roughly the time it
771 * takes to sleep on a request, on the order of a microsecond.
774 timeout_us += local_clock_us(&cpu);
776 if (__i915_gem_request_completed(req))
779 if (signal_pending_state(state, current))
782 if (busywait_stop(timeout_us, cpu))
785 cpu_relax_lowlatency();
786 } while (!need_resched());
792 __i915_request_wait_for_submit(struct drm_i915_gem_request *request,
796 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
797 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
798 wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
802 if (flags & I915_WAIT_LOCKED)
803 add_wait_queue(q, &reset);
806 prepare_to_wait(&request->submit.wait, &wait, state);
808 if (i915_sw_fence_done(&request->submit))
811 if (flags & I915_WAIT_LOCKED &&
812 i915_reset_in_progress(&request->i915->gpu_error)) {
813 __set_current_state(TASK_RUNNING);
814 i915_reset(request->i915);
815 reset_wait_queue(q, &reset);
819 if (signal_pending_state(state, current)) {
820 timeout = -ERESTARTSYS;
824 timeout = io_schedule_timeout(timeout);
826 finish_wait(&request->submit.wait, &wait);
828 if (flags & I915_WAIT_LOCKED)
829 remove_wait_queue(q, &reset);
835 * i915_wait_request - wait until execution of request has finished
836 * @req: the request to wait upon
837 * @flags: how to wait
838 * @timeout: how long to wait in jiffies
840 * i915_wait_request() waits for the request to be completed, for a
841 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
844 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
845 * in via the flags, and vice versa if the struct_mutex is not held, the caller
846 * must not specify that the wait is locked.
848 * Returns the remaining time (in jiffies) if the request completed, which may
849 * be zero or -ETIME if the request is unfinished after the timeout expires.
850 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
851 * pending before the request completes.
853 long i915_wait_request(struct drm_i915_gem_request *req,
857 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
858 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
860 struct intel_wait wait;
863 #if IS_ENABLED(CONFIG_LOCKDEP)
864 GEM_BUG_ON(debug_locks &&
865 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
866 !!(flags & I915_WAIT_LOCKED));
868 GEM_BUG_ON(timeout < 0);
870 if (i915_gem_request_completed(req))
876 trace_i915_gem_request_wait_begin(req);
878 if (!i915_sw_fence_done(&req->submit)) {
879 timeout = __i915_request_wait_for_submit(req, flags, timeout);
883 GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
885 GEM_BUG_ON(!req->global_seqno);
887 /* Optimistic short spin before touching IRQs */
888 if (i915_spin_request(req, state, 5))
891 set_current_state(state);
892 if (flags & I915_WAIT_LOCKED)
893 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
895 intel_wait_init(&wait, req->global_seqno);
896 if (intel_engine_add_wait(req->engine, &wait))
897 /* In order to check that we haven't missed the interrupt
898 * as we enabled it, we need to kick ourselves to do a
899 * coherent check on the seqno before we sleep.
904 if (signal_pending_state(state, current)) {
905 timeout = -ERESTARTSYS;
914 timeout = io_schedule_timeout(timeout);
916 if (intel_wait_complete(&wait))
919 set_current_state(state);
922 /* Carefully check if the request is complete, giving time
923 * for the seqno to be visible following the interrupt.
924 * We also have to check in case we are kicked by the GPU
925 * reset in order to drop the struct_mutex.
927 if (__i915_request_irq_complete(req))
930 /* If the GPU is hung, and we hold the lock, reset the GPU
931 * and then check for completion. On a full reset, the engine's
932 * HW seqno will be advanced passed us and we are complete.
933 * If we do a partial reset, we have to wait for the GPU to
934 * resume and update the breadcrumb.
936 * If we don't hold the mutex, we can just wait for the worker
937 * to come along and update the breadcrumb (either directly
938 * itself, or indirectly by recovering the GPU).
940 if (flags & I915_WAIT_LOCKED &&
941 i915_reset_in_progress(&req->i915->gpu_error)) {
942 __set_current_state(TASK_RUNNING);
943 i915_reset(req->i915);
944 reset_wait_queue(&req->i915->gpu_error.wait_queue,
949 /* Only spin if we know the GPU is processing this request */
950 if (i915_spin_request(req, state, 2))
954 intel_engine_remove_wait(req->engine, &wait);
955 if (flags & I915_WAIT_LOCKED)
956 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
957 __set_current_state(TASK_RUNNING);
960 trace_i915_gem_request_wait_end(req);
965 static bool engine_retire_requests(struct intel_engine_cs *engine)
967 struct drm_i915_gem_request *request, *next;
969 list_for_each_entry_safe(request, next,
970 &engine->timeline->requests, link) {
971 if (!i915_gem_request_completed(request))
974 i915_gem_request_retire(request);
980 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
982 struct intel_engine_cs *engine;
985 lockdep_assert_held(&dev_priv->drm.struct_mutex);
987 if (dev_priv->gt.active_engines == 0)
990 GEM_BUG_ON(!dev_priv->gt.awake);
992 for_each_engine_masked(engine, dev_priv, dev_priv->gt.active_engines, tmp)
993 if (engine_retire_requests(engine))
994 dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
996 if (dev_priv->gt.active_engines == 0)
997 queue_delayed_work(dev_priv->wq,
998 &dev_priv->gt.idle_work,
999 msecs_to_jiffies(100));