2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/string.h>
29 #include <linux/bitops.h>
31 #include <drm/i915_drm.h>
35 * DOC: buffer object tiling
37 * i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
38 * interface to declare fence register requirements.
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
62 * i915_gem_fence_size - required global GTT size for a fence
65 * @tiling: tiling mode
66 * @stride: tiling stride
68 * Return the required global GTT size for a fence (view of a tiled object),
69 * taking into account potential fence register mapping.
71 u32 i915_gem_fence_size(struct drm_i915_private *i915,
72 u32 size, unsigned int tiling, unsigned int stride)
78 if (tiling == I915_TILING_NONE)
83 if (INTEL_GEN(i915) >= 4) {
84 stride *= i915_gem_tile_height(tiling);
85 GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
86 return roundup(size, stride);
89 /* Previous chips need a power-of-two fence region when tiling */
91 ggtt_size = 1024*1024;
95 while (ggtt_size < size)
102 * i915_gem_fence_alignment - required global GTT alignment for a fence
105 * @tiling: tiling mode
106 * @stride: tiling stride
108 * Return the required global GTT alignment for a fence (a view of a tiled
109 * object), taking into account potential fence register mapping.
111 u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
112 unsigned int tiling, unsigned int stride)
117 * Minimum alignment is 4k (GTT page size), but might be greater
118 * if a fence register is needed for the object.
120 if (tiling == I915_TILING_NONE)
121 return I915_GTT_MIN_ALIGNMENT;
123 if (INTEL_GEN(i915) >= 4)
124 return I965_FENCE_PAGE;
127 * Previous chips need to be aligned to the size of the smallest
128 * fence register that can contain the object.
130 return i915_gem_fence_size(i915, size, tiling, stride);
133 /* Check pitch constriants for all chips & tiling formats */
135 i915_tiling_ok(struct drm_i915_gem_object *obj,
136 unsigned int tiling, unsigned int stride)
138 struct drm_i915_private *i915 = to_i915(obj->base.dev);
139 unsigned int tile_width;
141 /* Linear is always fine */
142 if (tiling == I915_TILING_NONE)
145 if (tiling > I915_TILING_LAST)
148 /* check maximum stride & object size */
149 /* i965+ stores the end address of the gtt mapping in the fence
150 * reg, so dont bother to check the size */
151 if (INTEL_GEN(i915) >= 7) {
152 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
154 } else if (INTEL_GEN(i915) >= 4) {
155 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
161 if (!is_power_of_2(stride))
166 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
171 if (!stride || !IS_ALIGNED(stride, tile_width))
177 static bool i915_vma_fence_prepare(struct i915_vma *vma,
178 int tiling_mode, unsigned int stride)
180 struct drm_i915_private *i915 = vma->vm->i915;
183 if (!i915_vma_is_map_and_fenceable(vma))
186 size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
187 if (vma->node.size < size)
190 alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
191 if (!IS_ALIGNED(vma->node.start, alignment))
197 /* Make the current GTT allocation valid for the change in tiling. */
199 i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
200 int tiling_mode, unsigned int stride)
202 struct i915_vma *vma;
205 if (tiling_mode == I915_TILING_NONE)
208 list_for_each_entry(vma, &obj->vma_list, obj_link) {
209 if (!i915_vma_is_ggtt(vma))
212 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
215 ret = i915_vma_unbind(vma);
224 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
225 unsigned int tiling, unsigned int stride)
227 struct drm_i915_private *i915 = to_i915(obj->base.dev);
228 struct i915_vma *vma;
231 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
232 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
234 GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
235 GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
236 lockdep_assert_held(&i915->drm.struct_mutex);
238 if ((tiling | stride) == obj->tiling_and_stride)
241 if (i915_gem_object_is_framebuffer(obj))
244 /* We need to rebind the object if its current allocation
245 * no longer meets the alignment restrictions for its new
246 * tiling mode. Otherwise we can just leave it alone, but
247 * need to ensure that any fence register is updated before
248 * the next fenced (either through the GTT or by the BLT unit
249 * on older GPUs) access.
251 * After updating the tiling parameters, we then flag whether
252 * we need to update an associated fence register. Note this
253 * has to also include the unfenced register the GPU uses
254 * whilst executing a fenced command for an untiled object.
257 err = i915_gem_object_fence_prepare(obj, tiling, stride);
261 i915_gem_object_lock(obj);
262 if (i915_gem_object_is_framebuffer(obj)) {
263 i915_gem_object_unlock(obj);
267 /* If the memory has unknown (i.e. varying) swizzling, we pin the
268 * pages to prevent them being swapped out and causing corruption
269 * due to the change in swizzling.
271 mutex_lock(&obj->mm.lock);
273 obj->mm.madv == I915_MADV_WILLNEED &&
274 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
275 if (tiling == I915_TILING_NONE) {
276 GEM_BUG_ON(!obj->mm.quirked);
277 __i915_gem_object_unpin_pages(obj);
278 obj->mm.quirked = false;
280 if (!i915_gem_object_is_tiled(obj)) {
281 GEM_BUG_ON(obj->mm.quirked);
282 __i915_gem_object_pin_pages(obj);
283 obj->mm.quirked = true;
286 mutex_unlock(&obj->mm.lock);
288 list_for_each_entry(vma, &obj->vma_list, obj_link) {
289 if (!i915_vma_is_ggtt(vma))
293 i915_gem_fence_size(i915, vma->size, tiling, stride);
294 vma->fence_alignment =
295 i915_gem_fence_alignment(i915,
296 vma->size, tiling, stride);
299 vma->fence->dirty = true;
302 obj->tiling_and_stride = tiling | stride;
303 i915_gem_object_unlock(obj);
305 /* Force the fence to be reacquired for GTT access */
306 i915_gem_release_mmap(obj);
308 /* Try to preallocate memory required to save swizzling on put-pages */
309 if (i915_gem_object_needs_bit17_swizzle(obj)) {
311 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
312 sizeof(long), GFP_KERNEL);
323 * i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
325 * @data: data pointer for the ioctl
326 * @file: DRM file for the ioctl call
328 * Sets the tiling mode of an object, returning the required swizzling of
329 * bit 6 of addresses in the object.
331 * Called by the user via ioctl.
334 * Zero on success, negative errno on failure.
337 i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
338 struct drm_file *file)
340 struct drm_i915_gem_set_tiling *args = data;
341 struct drm_i915_gem_object *obj;
344 obj = i915_gem_object_lookup(file, args->handle);
348 if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
353 if (args->tiling_mode == I915_TILING_NONE) {
354 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
357 if (args->tiling_mode == I915_TILING_X)
358 args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
360 args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
362 /* Hide bit 17 swizzling from the user. This prevents old Mesa
363 * from aborting the application on sw fallbacks to bit 17,
364 * and we use the pread/pwrite bit17 paths to swizzle for it.
365 * If there was a user that was relying on the swizzle
366 * information for drm_intel_bo_map()ed reads/writes this would
367 * break it, but we don't have any of those.
369 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
370 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
371 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
372 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
374 /* If we can't handle the swizzling, make it untiled. */
375 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
376 args->tiling_mode = I915_TILING_NONE;
377 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
382 err = mutex_lock_interruptible(&dev->struct_mutex);
386 err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
387 mutex_unlock(&dev->struct_mutex);
389 /* We have to maintain this existing ABI... */
390 args->stride = i915_gem_object_get_stride(obj);
391 args->tiling_mode = i915_gem_object_get_tiling(obj);
394 i915_gem_object_put(obj);
399 * i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
401 * @data: data pointer for the ioctl
402 * @file: DRM file for the ioctl call
404 * Returns the current tiling mode and required bit 6 swizzling for the object.
406 * Called by the user via ioctl.
409 * Zero on success, negative errno on failure.
412 i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
413 struct drm_file *file)
415 struct drm_i915_gem_get_tiling *args = data;
416 struct drm_i915_private *dev_priv = to_i915(dev);
417 struct drm_i915_gem_object *obj;
421 obj = i915_gem_object_lookup_rcu(file, args->handle);
424 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
431 switch (args->tiling_mode) {
433 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
436 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
439 case I915_TILING_NONE:
440 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
444 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
445 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
446 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
448 args->phys_swizzle_mode = args->swizzle_mode;
449 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
450 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
451 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
452 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;