drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include "i915_drv.h"
  32
  33 static const char *yesno(int v)
  34 {
  35         return v ? "yes" : "no";
  36 }
  37
  38 static const char *ring_str(int ring)
  39 {
  40         switch (ring) {
  41         case RCS: return "render";
  42         case VCS: return "bsd";
  43         case BCS: return "blt";
  44         case VECS: return "vebox";
  45         default: return "";
  46         }
  47 }
  48
  49 static const char *pin_flag(int pinned)
  50 {
  51         if (pinned > 0)
  52                 return " P";
  53         else if (pinned < 0)
  54                 return " p";
  55         else
  56                 return "";
  57 }
  58
  59 static const char *tiling_flag(int tiling)
  60 {
  61         switch (tiling) {
  62         default:
  63         case I915_TILING_NONE: return "";
  64         case I915_TILING_X: return " X";
  65         case I915_TILING_Y: return " Y";
  66         }
  67 }
  68
  69 static const char *dirty_flag(int dirty)
  70 {
  71         return dirty ? " dirty" : "";
  72 }
  73
  74 static const char *purgeable_flag(int purgeable)
  75 {
  76         return purgeable ? " purgeable" : "";
  77 }
  78
  79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  80 {
  81
  82         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  83                 e->err = -ENOSPC;
  84                 return false;
  85         }
  86
  87         if (e->bytes == e->size - 1 || e->err)
  88                 return false;
  89
  90         return true;
  91 }
  92
  93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  94                               unsigned len)
  95 {
  96         if (e->pos + len <= e->start) {
  97                 e->pos += len;
  98                 return false;
  99         }
 100
 101         /* First vsnprintf needs to fit in its entirety for memmove */
 102         if (len >= e->size) {
 103                 e->err = -EIO;
 104                 return false;
 105         }
 106
 107         return true;
 108 }
 109
 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 111                                  unsigned len)
 112 {
 113         /* If this is first printf in this window, adjust it so that
 114          * start position matches start of the buffer
 115          */
 116
 117         if (e->pos < e->start) {
 118                 const size_t off = e->start - e->pos;
 119
 120                 /* Should not happen but be paranoid */
 121                 if (off > len || e->bytes) {
 122                         e->err = -EIO;
 123                         return;
 124                 }
 125
 126                 memmove(e->buf, e->buf + off, len - off);
 127                 e->bytes = len - off;
 128                 e->pos = e->start;
 129                 return;
 130         }
 131
 132         e->bytes += len;
 133         e->pos += len;
 134 }
 135
 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 137                                const char *f, va_list args)
 138 {
 139         unsigned len;
 140
 141         if (!__i915_error_ok(e))
 142                 return;
 143
 144         /* Seek the first printf which is hits start position */
 145         if (e->pos < e->start) {
 146                 va_list tmp;
 147
 148                 va_copy(tmp, args);
 149                 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
 150                         return;
 151         }
 152
 153         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 154         if (len >= e->size - e->bytes)
 155                 len = e->size - e->bytes - 1;
 156
 157         __i915_error_advance(e, len);
 158 }
 159
 160 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 161                             const char *str)
 162 {
 163         unsigned len;
 164
 165         if (!__i915_error_ok(e))
 166                 return;
 167
 168         len = strlen(str);
 169
 170         /* Seek the first printf which is hits start position */
 171         if (e->pos < e->start) {
 172                 if (!__i915_error_seek(e, len))
 173                         return;
 174         }
 175
 176         if (len >= e->size - e->bytes)
 177                 len = e->size - e->bytes - 1;
 178         memcpy(e->buf + e->bytes, str, len);
 179
 180         __i915_error_advance(e, len);
 181 }
 182
 183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 184 #define err_puts(e, s) i915_error_puts(e, s)
 185
 186 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 187                                 const char *name,
 188                                 struct drm_i915_error_buffer *err,
 189                                 int count)
 190 {
 191         err_printf(m, "%s [%d]:\n", name, count);
 192
 193         while (count--) {
 194                 err_printf(m, "  %08x %8u %02x %02x %x %x",
 195                            err->gtt_offset,
 196                            err->size,
 197                            err->read_domains,
 198                            err->write_domain,
 199                            err->rseqno, err->wseqno);
 200                 err_puts(m, pin_flag(err->pinned));
 201                 err_puts(m, tiling_flag(err->tiling));
 202                 err_puts(m, dirty_flag(err->dirty));
 203                 err_puts(m, purgeable_flag(err->purgeable));
 204                 err_puts(m, err->ring != -1 ? " " : "");
 205                 err_puts(m, ring_str(err->ring));
 206                 err_puts(m, i915_cache_level_str(err->cache_level));
 207
 208                 if (err->name)
 209                         err_printf(m, " (name: %d)", err->name);
 210                 if (err->fence_reg != I915_FENCE_REG_NONE)
 211                         err_printf(m, " (fence: %d)", err->fence_reg);
 212
 213                 err_puts(m, "\n");
 214                 err++;
 215         }
 216 }
 217
 218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
 219 {
 220         switch (a) {
 221         case HANGCHECK_IDLE:
 222                 return "idle";
 223         case HANGCHECK_WAIT:
 224                 return "wait";
 225         case HANGCHECK_ACTIVE:
 226                 return "active";
 227         case HANGCHECK_KICK:
 228                 return "kick";
 229         case HANGCHECK_HUNG:
 230                 return "hung";
 231         }
 232
 233         return "unknown";
 234 }
 235
 236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
 237                                   struct drm_device *dev,
 238                                   struct drm_i915_error_ring *ring)
 239 {
 240         if (!ring->valid)
 241                 return;
 242
 243         err_printf(m, "  HEAD: 0x%08x\n", ring->head);
 244         err_printf(m, "  TAIL: 0x%08x\n", ring->tail);
 245         err_printf(m, "  CTL: 0x%08x\n", ring->ctl);
 246         err_printf(m, "  HWS: 0x%08x\n", ring->hws);
 247         err_printf(m, "  ACTHD: 0x%08x\n", ring->acthd);
 248         err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
 249         err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
 250         err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
 251         if (INTEL_INFO(dev)->gen >= 4) {
 252                 err_printf(m, "  BBADDR: 0x%08llx\n", ring->bbaddr);
 253                 err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
 254                 err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
 255         }
 256         err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
 257         err_printf(m, "  FADDR: 0x%08x\n", ring->faddr);
 258         if (INTEL_INFO(dev)->gen >= 6) {
 259                 err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
 260                 err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
 261                 err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 262                            ring->semaphore_mboxes[0],
 263                            ring->semaphore_seqno[0]);
 264                 err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 265                            ring->semaphore_mboxes[1],
 266                            ring->semaphore_seqno[1]);
 267                 if (HAS_VEBOX(dev)) {
 268                         err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 269                                    ring->semaphore_mboxes[2],
 270                                    ring->semaphore_seqno[2]);
 271                 }
 272         }
 273         err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
 274         err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
 275         err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
 276         err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
 277         err_printf(m, "  hangcheck: %s [%d]\n",
 278                    hangcheck_action_to_str(ring->hangcheck_action),
 279                    ring->hangcheck_score);
 280 }
 281
 282 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 283 {
 284         va_list args;
 285
 286         va_start(args, f);
 287         i915_error_vprintf(e, f, args);
 288         va_end(args);
 289 }
 290
 291 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 292                             const struct i915_error_state_file_priv *error_priv)
 293 {
 294         struct drm_device *dev = error_priv->dev;
 295         drm_i915_private_t *dev_priv = dev->dev_private;
 296         struct drm_i915_error_state *error = error_priv->error;
 297         int i, j, page, offset, elt;
 298
 299         if (!error) {
 300                 err_printf(m, "no error state collected\n");
 301                 goto out;
 302         }
 303
 304         err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 305                    error->time.tv_usec);
 306         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 307         err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 308         err_printf(m, "EIR: 0x%08x\n", error->eir);
 309         err_printf(m, "IER: 0x%08x\n", error->ier);
 310         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 311         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 312         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 313         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 314         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 315
 316         for (i = 0; i < dev_priv->num_fence_regs; i++)
 317                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 318
 319         for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
 320                 err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
 321                            error->extra_instdone[i]);
 322
 323         if (INTEL_INFO(dev)->gen >= 6) {
 324                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 325                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 326         }
 327
 328         if (INTEL_INFO(dev)->gen == 7)
 329                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 330
 331         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 332                 err_printf(m, "%s command stream:\n", ring_str(i));
 333                 i915_ring_error_state(m, dev, &error->ring[i]);
 334         }
 335
 336         if (error->active_bo)
 337                 print_error_buffers(m, "Active",
 338                                     error->active_bo[0],
 339                                     error->active_bo_count[0]);
 340
 341         if (error->pinned_bo)
 342                 print_error_buffers(m, "Pinned",
 343                                     error->pinned_bo[0],
 344                                     error->pinned_bo_count[0]);
 345
 346         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 347                 struct drm_i915_error_object *obj;
 348
 349                 if ((obj = error->ring[i].batchbuffer)) {
 350                         err_printf(m, "%s --- gtt_offset = 0x%08x\n",
 351                                    dev_priv->ring[i].name,
 352                                    obj->gtt_offset);
 353                         offset = 0;
 354                         for (page = 0; page < obj->page_count; page++) {
 355                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 356                                         err_printf(m, "%08x :  %08x\n", offset,
 357                                                    obj->pages[page][elt]);
 358                                         offset += 4;
 359                                 }
 360                         }
 361                 }
 362
 363                 if (error->ring[i].num_requests) {
 364                         err_printf(m, "%s --- %d requests\n",
 365                                    dev_priv->ring[i].name,
 366                                    error->ring[i].num_requests);
 367                         for (j = 0; j < error->ring[i].num_requests; j++) {
 368                                 err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 369                                            error->ring[i].requests[j].seqno,
 370                                            error->ring[i].requests[j].jiffies,
 371                                            error->ring[i].requests[j].tail);
 372                         }
 373                 }
 374
 375                 if ((obj = error->ring[i].ringbuffer)) {
 376                         err_printf(m, "%s --- ringbuffer = 0x%08x\n",
 377                                    dev_priv->ring[i].name,
 378                                    obj->gtt_offset);
 379                         offset = 0;
 380                         for (page = 0; page < obj->page_count; page++) {
 381                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 382                                         err_printf(m, "%08x :  %08x\n",
 383                                                    offset,
 384                                                    obj->pages[page][elt]);
 385                                         offset += 4;
 386                                 }
 387                         }
 388                 }
 389
 390                 if ((obj = error->ring[i].hws_page)) {
 391                         err_printf(m, "%s --- HW Status = 0x%08x\n",
 392                                    dev_priv->ring[i].name,
 393                                    obj->gtt_offset);
 394                         offset = 0;
 395                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 396                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 397                                            offset,
 398                                            obj->pages[0][elt],
 399                                            obj->pages[0][elt+1],
 400                                            obj->pages[0][elt+2],
 401                                            obj->pages[0][elt+3]);
 402                                         offset += 16;
 403                         }
 404                 }
 405
 406                 if ((obj = error->ring[i].ctx)) {
 407                         err_printf(m, "%s --- HW Context = 0x%08x\n",
 408                                    dev_priv->ring[i].name,
 409                                    obj->gtt_offset);
 410                         offset = 0;
 411                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 412                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 413                                            offset,
 414                                            obj->pages[0][elt],
 415                                            obj->pages[0][elt+1],
 416                                            obj->pages[0][elt+2],
 417                                            obj->pages[0][elt+3]);
 418                                         offset += 16;
 419                         }
 420                 }
 421         }
 422
 423         if (error->overlay)
 424                 intel_overlay_print_error_state(m, error->overlay);
 425
 426         if (error->display)
 427                 intel_display_print_error_state(m, dev, error->display);
 428
 429 out:
 430         if (m->bytes == 0 && m->err)
 431                 return m->err;
 432
 433         return 0;
 434 }
 435
 436 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 437                               size_t count, loff_t pos)
 438 {
 439         memset(ebuf, 0, sizeof(*ebuf));
 440
 441         /* We need to have enough room to store any i915_error_state printf
 442          * so that we can move it to start position.
 443          */
 444         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 445         ebuf->buf = kmalloc(ebuf->size,
 446                                 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
 447
 448         if (ebuf->buf == NULL) {
 449                 ebuf->size = PAGE_SIZE;
 450                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 451         }
 452
 453         if (ebuf->buf == NULL) {
 454                 ebuf->size = 128;
 455                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 456         }
 457
 458         if (ebuf->buf == NULL)
 459                 return -ENOMEM;
 460
 461         ebuf->start = pos;
 462
 463         return 0;
 464 }
 465
 466 static void i915_error_object_free(struct drm_i915_error_object *obj)
 467 {
 468         int page;
 469
 470         if (obj == NULL)
 471                 return;
 472
 473         for (page = 0; page < obj->page_count; page++)
 474                 kfree(obj->pages[page]);
 475
 476         kfree(obj);
 477 }
 478
 479 static void i915_error_state_free(struct kref *error_ref)
 480 {
 481         struct drm_i915_error_state *error = container_of(error_ref,
 482                                                           typeof(*error), ref);
 483         int i;
 484
 485         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 486                 i915_error_object_free(error->ring[i].batchbuffer);
 487                 i915_error_object_free(error->ring[i].ringbuffer);
 488                 i915_error_object_free(error->ring[i].hws_page);
 489                 i915_error_object_free(error->ring[i].ctx);
 490                 kfree(error->ring[i].requests);
 491         }
 492
 493         kfree(error->active_bo);
 494         kfree(error->overlay);
 495         kfree(error->display);
 496         kfree(error);
 497 }
 498
 499 static struct drm_i915_error_object *
 500 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
 501                                struct drm_i915_gem_object *src,
 502                                struct i915_address_space *vm,
 503                                const int num_pages)
 504 {
 505         struct drm_i915_error_object *dst;
 506         int i;
 507         u32 reloc_offset;
 508
 509         if (src == NULL || src->pages == NULL)
 510                 return NULL;
 511
 512         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 513         if (dst == NULL)
 514                 return NULL;
 515
 516         reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
 517         for (i = 0; i < num_pages; i++) {
 518                 unsigned long flags;
 519                 void *d;
 520
 521                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 522                 if (d == NULL)
 523                         goto unwind;
 524
 525                 local_irq_save(flags);
 526                 if (reloc_offset < dev_priv->gtt.mappable_end &&
 527                     src->has_global_gtt_mapping &&
 528                     i915_is_ggtt(vm)) {
 529                         void __iomem *s;
 530
 531                         /* Simply ignore tiling or any overlapping fence.
 532                          * It's part of the error state, and this hopefully
 533                          * captures what the GPU read.
 534                          */
 535
 536                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 537                                                      reloc_offset);
 538                         memcpy_fromio(d, s, PAGE_SIZE);
 539                         io_mapping_unmap_atomic(s);
 540                 } else if (src->stolen) {
 541                         unsigned long offset;
 542
 543                         offset = dev_priv->mm.stolen_base;
 544                         offset += src->stolen->start;
 545                         offset += i << PAGE_SHIFT;
 546
 547                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
 548                 } else {
 549                         struct page *page;
 550                         void *s;
 551
 552                         page = i915_gem_object_get_page(src, i);
 553
 554                         drm_clflush_pages(&page, 1);
 555
 556                         s = kmap_atomic(page);
 557                         memcpy(d, s, PAGE_SIZE);
 558                         kunmap_atomic(s);
 559
 560                         drm_clflush_pages(&page, 1);
 561                 }
 562                 local_irq_restore(flags);
 563
 564                 dst->pages[i] = d;
 565
 566                 reloc_offset += PAGE_SIZE;
 567         }
 568         dst->page_count = num_pages;
 569
 570         return dst;
 571
 572 unwind:
 573         while (i--)
 574                 kfree(dst->pages[i]);
 575         kfree(dst);
 576         return NULL;
 577 }
 578 #define i915_error_object_create(dev_priv, src, vm) \
 579         i915_error_object_create_sized((dev_priv), (src), (vm), \
 580                                        (src)->base.size>>PAGE_SHIFT)
 581
 582 #define i915_error_ggtt_object_create(dev_priv, src) \
 583         i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
 584                                        (src)->base.size>>PAGE_SHIFT)
 585
 586 static void capture_bo(struct drm_i915_error_buffer *err,
 587                        struct drm_i915_gem_object *obj)
 588 {
 589         err->size = obj->base.size;
 590         err->name = obj->base.name;
 591         err->rseqno = obj->last_read_seqno;
 592         err->wseqno = obj->last_write_seqno;
 593         err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
 594         err->read_domains = obj->base.read_domains;
 595         err->write_domain = obj->base.write_domain;
 596         err->fence_reg = obj->fence_reg;
 597         err->pinned = 0;
 598         if (i915_gem_obj_is_pinned(obj))
 599                 err->pinned = 1;
 600         if (obj->user_pin_count > 0)
 601                 err->pinned = -1;
 602         err->tiling = obj->tiling_mode;
 603         err->dirty = obj->dirty;
 604         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 605         err->ring = obj->ring ? obj->ring->id : -1;
 606         err->cache_level = obj->cache_level;
 607 }
 608
 609 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 610                              int count, struct list_head *head)
 611 {
 612         struct i915_vma *vma;
 613         int i = 0;
 614
 615         list_for_each_entry(vma, head, mm_list) {
 616                 capture_bo(err++, vma->obj);
 617                 if (++i == count)
 618                         break;
 619         }
 620
 621         return i;
 622 }
 623
 624 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 625                              int count, struct list_head *head)
 626 {
 627         struct drm_i915_gem_object *obj;
 628         int i = 0;
 629
 630         list_for_each_entry(obj, head, global_list) {
 631                 if (!i915_gem_obj_is_pinned(obj))
 632                         continue;
 633
 634                 capture_bo(err++, obj);
 635                 if (++i == count)
 636                         break;
 637         }
 638
 639         return i;
 640 }
 641
 642 static void i915_gem_record_fences(struct drm_device *dev,
 643                                    struct drm_i915_error_state *error)
 644 {
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         int i;
 647
 648         /* Fences */
 649         switch (INTEL_INFO(dev)->gen) {
 650         case 8:
 651         case 7:
 652         case 6:
 653                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 654                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 655                 break;
 656         case 5:
 657         case 4:
 658                 for (i = 0; i < 16; i++)
 659                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 660                 break;
 661         case 3:
 662                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 663                         for (i = 0; i < 8; i++)
 664                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 665         case 2:
 666                 for (i = 0; i < 8; i++)
 667                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 668                 break;
 669
 670         default:
 671                 BUG();
 672         }
 673 }
 674
 675 /* This assumes all batchbuffers are executed from the PPGTT. It might have to
 676  * change in the future. */
 677 static bool is_active_vm(struct i915_address_space *vm,
 678                          struct intel_ring_buffer *ring)
 679 {
 680         struct drm_device *dev = vm->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         struct i915_hw_ppgtt *ppgtt;
 683
 684         if (INTEL_INFO(dev)->gen < 7)
 685                 return i915_is_ggtt(vm);
 686
 687         /* FIXME: This ignores that the global gtt vm is also on this list. */
 688         ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
 689
 690         if (INTEL_INFO(dev)->gen >= 8) {
 691                 u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32;
 692                 pdp0 |=  I915_READ(GEN8_RING_PDP_LDW(ring, 0));
 693                 return pdp0 == ppgtt->pd_dma_addr[0];
 694         } else {
 695                 u32 pp_db;
 696                 pp_db = I915_READ(RING_PP_DIR_BASE(ring));
 697                 return (pp_db >> 10) == ppgtt->pd_offset;
 698         }
 699 }
 700
 701 static struct drm_i915_error_object *
 702 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 703                              struct intel_ring_buffer *ring)
 704 {
 705         struct i915_address_space *vm;
 706         struct i915_vma *vma;
 707         struct drm_i915_gem_object *obj;
 708         bool found_active = false;
 709         u32 seqno;
 710
 711         if (!ring->get_seqno)
 712                 return NULL;
 713
 714         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
 715                 u32 acthd = I915_READ(ACTHD);
 716
 717                 if (WARN_ON(ring->id != RCS))
 718                         return NULL;
 719
 720                 obj = ring->scratch.obj;
 721                 if (obj != NULL &&
 722                     acthd >= i915_gem_obj_ggtt_offset(obj) &&
 723                     acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
 724                         return i915_error_ggtt_object_create(dev_priv, obj);
 725         }
 726
 727         seqno = ring->get_seqno(ring, false);
 728         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
 729                 if (!is_active_vm(vm, ring))
 730                         continue;
 731
 732                 found_active = true;
 733
 734                 list_for_each_entry(vma, &vm->active_list, mm_list) {
 735                         obj = vma->obj;
 736                         if (obj->ring != ring)
 737                                 continue;
 738
 739                         if (i915_seqno_passed(seqno, obj->last_read_seqno))
 740                                 continue;
 741
 742                         if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 743                                 continue;
 744
 745                         /* We need to copy these to an anonymous buffer as the simplest
 746                          * method to avoid being overwritten by userspace.
 747                          */
 748                         return i915_error_object_create(dev_priv, obj, vm);
 749                 }
 750         }
 751
 752         WARN_ON(!found_active);
 753         return NULL;
 754 }
 755
 756 static void i915_record_ring_state(struct drm_device *dev,
 757                                    struct intel_ring_buffer *ring,
 758                                    struct drm_i915_error_ring *ering)
 759 {
 760         struct drm_i915_private *dev_priv = dev->dev_private;
 761
 762         if (INTEL_INFO(dev)->gen >= 6) {
 763                 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
 764                 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 765                 ering->semaphore_mboxes[0]
 766                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 767                 ering->semaphore_mboxes[1]
 768                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 769                 ering->semaphore_seqno[0] = ring->sync_seqno[0];
 770                 ering->semaphore_seqno[1] = ring->sync_seqno[1];
 771         }
 772
 773         if (HAS_VEBOX(dev)) {
 774                 ering->semaphore_mboxes[2] =
 775                         I915_READ(RING_SYNC_2(ring->mmio_base));
 776                 ering->semaphore_seqno[2] = ring->sync_seqno[2];
 777         }
 778
 779         if (INTEL_INFO(dev)->gen >= 4) {
 780                 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
 781                 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
 782                 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
 783                 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
 784                 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
 785                 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
 786                 if (INTEL_INFO(dev)->gen >= 8)
 787                         ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
 788                 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
 789         } else {
 790                 ering->faddr = I915_READ(DMA_FADD_I8XX);
 791                 ering->ipeir = I915_READ(IPEIR);
 792                 ering->ipehr = I915_READ(IPEHR);
 793                 ering->instdone = I915_READ(INSTDONE);
 794         }
 795
 796         ering->waiting = waitqueue_active(&ring->irq_queue);
 797         ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
 798         ering->seqno = ring->get_seqno(ring, false);
 799         ering->acthd = intel_ring_get_active_head(ring);
 800         ering->head = I915_READ_HEAD(ring);
 801         ering->tail = I915_READ_TAIL(ring);
 802         ering->ctl = I915_READ_CTL(ring);
 803
 804         if (I915_NEED_GFX_HWS(dev)) {
 805                 int mmio;
 806
 807                 if (IS_GEN7(dev)) {
 808                         switch (ring->id) {
 809                         default:
 810                         case RCS:
 811                                 mmio = RENDER_HWS_PGA_GEN7;
 812                                 break;
 813                         case BCS:
 814                                 mmio = BLT_HWS_PGA_GEN7;
 815                                 break;
 816                         case VCS:
 817                                 mmio = BSD_HWS_PGA_GEN7;
 818                                 break;
 819                         case VECS:
 820                                 mmio = VEBOX_HWS_PGA_GEN7;
 821                                 break;
 822                         }
 823                 } else if (IS_GEN6(ring->dev)) {
 824                         mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 825                 } else {
 826                         /* XXX: gen8 returns to sanity */
 827                         mmio = RING_HWS_PGA(ring->mmio_base);
 828                 }
 829
 830                 ering->hws = I915_READ(mmio);
 831         }
 832
 833         ering->cpu_ring_head = ring->head;
 834         ering->cpu_ring_tail = ring->tail;
 835
 836         ering->hangcheck_score = ring->hangcheck.score;
 837         ering->hangcheck_action = ring->hangcheck.action;
 838 }
 839
 840
 841 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
 842                                            struct drm_i915_error_state *error,
 843                                            struct drm_i915_error_ring *ering)
 844 {
 845         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 846         struct drm_i915_gem_object *obj;
 847
 848         /* Currently render ring is the only HW context user */
 849         if (ring->id != RCS || !error->ccid)
 850                 return;
 851
 852         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 853                 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
 854                         ering->ctx = i915_error_object_create_sized(dev_priv,
 855                                                                     obj,
 856                                                                     &dev_priv->gtt.base,
 857                                                                     1);
 858                         break;
 859                 }
 860         }
 861 }
 862
 863 static void i915_gem_record_rings(struct drm_device *dev,
 864                                   struct drm_i915_error_state *error)
 865 {
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         struct drm_i915_gem_request *request;
 868         int i, count;
 869
 870         for (i = 0; i < I915_NUM_RINGS; i++) {
 871                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
 872
 873                 if (ring->dev == NULL)
 874                         continue;
 875
 876                 error->ring[i].valid = true;
 877
 878                 i915_record_ring_state(dev, ring, &error->ring[i]);
 879
 880                 error->ring[i].batchbuffer =
 881                         i915_error_first_batchbuffer(dev_priv, ring);
 882
 883                 error->ring[i].ringbuffer =
 884                         i915_error_ggtt_object_create(dev_priv, ring->obj);
 885
 886                 if (ring->status_page.obj)
 887                         error->ring[i].hws_page =
 888                                 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
 889
 890                 i915_gem_record_active_context(ring, error, &error->ring[i]);
 891
 892                 count = 0;
 893                 list_for_each_entry(request, &ring->request_list, list)
 894                         count++;
 895
 896                 error->ring[i].num_requests = count;
 897                 error->ring[i].requests =
 898                         kcalloc(count, sizeof(*error->ring[i].requests),
 899                                 GFP_ATOMIC);
 900                 if (error->ring[i].requests == NULL) {
 901                         error->ring[i].num_requests = 0;
 902                         continue;
 903                 }
 904
 905                 count = 0;
 906                 list_for_each_entry(request, &ring->request_list, list) {
 907                         struct drm_i915_error_request *erq;
 908
 909                         erq = &error->ring[i].requests[count++];
 910                         erq->seqno = request->seqno;
 911                         erq->jiffies = request->emitted_jiffies;
 912                         erq->tail = request->tail;
 913                 }
 914         }
 915 }
 916
 917 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
 918  * VM.
 919  */
 920 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
 921                                 struct drm_i915_error_state *error,
 922                                 struct i915_address_space *vm,
 923                                 const int ndx)
 924 {
 925         struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
 926         struct drm_i915_gem_object *obj;
 927         struct i915_vma *vma;
 928         int i;
 929
 930         i = 0;
 931         list_for_each_entry(vma, &vm->active_list, mm_list)
 932                 i++;
 933         error->active_bo_count[ndx] = i;
 934         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 935                 if (i915_gem_obj_is_pinned(obj))
 936                         i++;
 937         error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
 938
 939         if (i) {
 940                 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
 941                 if (active_bo)
 942                         pinned_bo = active_bo + error->active_bo_count[ndx];
 943         }
 944
 945         if (active_bo)
 946                 error->active_bo_count[ndx] =
 947                         capture_active_bo(active_bo,
 948                                           error->active_bo_count[ndx],
 949                                           &vm->active_list);
 950
 951         if (pinned_bo)
 952                 error->pinned_bo_count[ndx] =
 953                         capture_pinned_bo(pinned_bo,
 954                                           error->pinned_bo_count[ndx],
 955                                           &dev_priv->mm.bound_list);
 956         error->active_bo[ndx] = active_bo;
 957         error->pinned_bo[ndx] = pinned_bo;
 958 }
 959
 960 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
 961                                      struct drm_i915_error_state *error)
 962 {
 963         struct i915_address_space *vm;
 964         int cnt = 0, i = 0;
 965
 966         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
 967                 cnt++;
 968
 969         error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
 970         error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
 971         error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
 972                                          GFP_ATOMIC);
 973         error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
 974                                          GFP_ATOMIC);
 975
 976         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
 977                 i915_gem_capture_vm(dev_priv, error, vm, i++);
 978 }
 979
 980 /* Capture all registers which don't fit into another category. */
 981 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 982                                    struct drm_i915_error_state *error)
 983 {
 984         struct drm_device *dev = dev_priv->dev;
 985         int pipe;
 986
 987         /* General organization
 988          * 1. Registers specific to a single generation
 989          * 2. Registers which belong to multiple generations
 990          * 3. Feature specific registers.
 991          * 4. Everything else
 992          * Please try to follow the order.
 993          */
 994
 995         /* 1: Registers specific to a single generation */
 996         if (IS_VALLEYVIEW(dev)) {
 997                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
 998                 error->forcewake = I915_READ(FORCEWAKE_VLV);
 999         }
1000
1001         if (IS_GEN7(dev))
1002                 error->err_int = I915_READ(GEN7_ERR_INT);
1003
1004         if (IS_GEN6(dev))
1005                 error->forcewake = I915_READ(FORCEWAKE);
1006
1007         if (IS_GEN2(dev))
1008                 error->ier = I915_READ16(IER);
1009
1010         /* 2: Registers which belong to multiple generations */
1011         if (INTEL_INFO(dev)->gen >= 7)
1012                 error->forcewake = I915_READ(FORCEWAKE_MT);
1013
1014         if (INTEL_INFO(dev)->gen >= 6) {
1015                 error->derrmr = I915_READ(DERRMR);
1016                 error->error = I915_READ(ERROR_GEN6);
1017                 error->done_reg = I915_READ(DONE_REG);
1018         }
1019
1020         /* 3: Feature specific registers */
1021         if (HAS_HW_CONTEXTS(dev))
1022                 error->ccid = I915_READ(CCID);
1023
1024         if (HAS_PCH_SPLIT(dev))
1025                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1026         else {
1027                 error->ier = I915_READ(IER);
1028                 for_each_pipe(pipe)
1029                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1030         }
1031
1032         /* 4: Everything else */
1033         error->eir = I915_READ(EIR);
1034         error->pgtbl_er = I915_READ(PGTBL_ER);
1035
1036         i915_get_extra_instdone(dev, error->extra_instdone);
1037 }
1038
1039 /**
1040  * i915_capture_error_state - capture an error record for later analysis
1041  * @dev: drm device
1042  *
1043  * Should be called when an error is detected (either a hang or an error
1044  * interrupt) to capture error state from the time of the error.  Fills
1045  * out a structure which becomes available in debugfs for user level tools
1046  * to pick up.
1047  */
1048 void i915_capture_error_state(struct drm_device *dev)
1049 {
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         struct drm_i915_error_state *error;
1052         unsigned long flags;
1053
1054         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1055         error = dev_priv->gpu_error.first_error;
1056         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1057         if (error)
1058                 return;
1059
1060         /* Account for pipe specific data like PIPE*STAT */
1061         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1062         if (!error) {
1063                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1064                 return;
1065         }
1066
1067         DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1068                  dev->primary->index);
1069         DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1070         DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1071         DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1072         DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1073
1074         kref_init(&error->ref);
1075
1076         i915_capture_reg_state(dev_priv, error);
1077         i915_gem_capture_buffers(dev_priv, error);
1078         i915_gem_record_fences(dev, error);
1079         i915_gem_record_rings(dev, error);
1080
1081         do_gettimeofday(&error->time);
1082
1083         error->overlay = intel_overlay_capture_error_state(dev);
1084         error->display = intel_display_capture_error_state(dev);
1085
1086         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1087         if (dev_priv->gpu_error.first_error == NULL) {
1088                 dev_priv->gpu_error.first_error = error;
1089                 error = NULL;
1090         }
1091         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1092
1093         if (error)
1094                 i915_error_state_free(&error->ref);
1095 }
1096
1097 void i915_error_state_get(struct drm_device *dev,
1098                           struct i915_error_state_file_priv *error_priv)
1099 {
1100         struct drm_i915_private *dev_priv = dev->dev_private;
1101         unsigned long flags;
1102
1103         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1104         error_priv->error = dev_priv->gpu_error.first_error;
1105         if (error_priv->error)
1106                 kref_get(&error_priv->error->ref);
1107         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1108
1109 }
1110
1111 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1112 {
1113         if (error_priv->error)
1114                 kref_put(&error_priv->error->ref, i915_error_state_free);
1115 }
1116
1117 void i915_destroy_error_state(struct drm_device *dev)
1118 {
1119         struct drm_i915_private *dev_priv = dev->dev_private;
1120         struct drm_i915_error_state *error;
1121         unsigned long flags;
1122
1123         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1124         error = dev_priv->gpu_error.first_error;
1125         dev_priv->gpu_error.first_error = NULL;
1126         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1127
1128         if (error)
1129                 kref_put(&error->ref, i915_error_state_free);
1130 }
1131
1132 const char *i915_cache_level_str(int type)
1133 {
1134         switch (type) {
1135         case I915_CACHE_NONE: return " uncached";
1136         case I915_CACHE_LLC: return " snooped or LLC";
1137         case I915_CACHE_L3_LLC: return " L3+LLC";
1138         case I915_CACHE_WT: return " WT";
1139         default: return "";
1140         }
1141 }
1142
1143 /* NB: please notice the memset */
1144 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1145 {
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1148
1149         switch (INTEL_INFO(dev)->gen) {
1150         case 2:
1151         case 3:
1152                 instdone[0] = I915_READ(INSTDONE);
1153                 break;
1154         case 4:
1155         case 5:
1156         case 6:
1157                 instdone[0] = I915_READ(INSTDONE_I965);
1158                 instdone[1] = I915_READ(INSTDONE1);
1159                 break;
1160         default:
1161                 WARN_ONCE(1, "Unsupported platform\n");
1162         case 7:
1163         case 8:
1164                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1165                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1166                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1167                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1168                 break;
1169         }
1170 }