2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <generated/utsrelease.h>
31 #include <linux/stop_machine.h>
32 #include <linux/zlib.h>
35 static const char *engine_str(int engine)
38 case RCS: return "render";
39 case VCS: return "bsd";
40 case BCS: return "blt";
41 case VECS: return "vebox";
42 case VCS2: return "bsd2";
47 static const char *tiling_flag(int tiling)
51 case I915_TILING_NONE: return "";
52 case I915_TILING_X: return " X";
53 case I915_TILING_Y: return " Y";
57 static const char *dirty_flag(int dirty)
59 return dirty ? " dirty" : "";
62 static const char *purgeable_flag(int purgeable)
64 return purgeable ? " purgeable" : "";
67 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
70 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
75 if (e->bytes == e->size - 1 || e->err)
81 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
84 if (e->pos + len <= e->start) {
89 /* First vsnprintf needs to fit in its entirety for memmove */
98 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
101 /* If this is first printf in this window, adjust it so that
102 * start position matches start of the buffer
105 if (e->pos < e->start) {
106 const size_t off = e->start - e->pos;
108 /* Should not happen but be paranoid */
109 if (off > len || e->bytes) {
114 memmove(e->buf, e->buf + off, len - off);
115 e->bytes = len - off;
124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
125 const char *f, va_list args)
129 if (!__i915_error_ok(e))
132 /* Seek the first printf which is hits start position */
133 if (e->pos < e->start) {
137 len = vsnprintf(NULL, 0, f, tmp);
140 if (!__i915_error_seek(e, len))
144 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
145 if (len >= e->size - e->bytes)
146 len = e->size - e->bytes - 1;
148 __i915_error_advance(e, len);
151 static void i915_error_puts(struct drm_i915_error_state_buf *e,
156 if (!__i915_error_ok(e))
161 /* Seek the first printf which is hits start position */
162 if (e->pos < e->start) {
163 if (!__i915_error_seek(e, len))
167 if (len >= e->size - e->bytes)
168 len = e->size - e->bytes - 1;
169 memcpy(e->buf + e->bytes, str, len);
171 __i915_error_advance(e, len);
174 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
175 #define err_puts(e, s) i915_error_puts(e, s)
177 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
179 static bool compress_init(struct z_stream_s *zstream)
181 memset(zstream, 0, sizeof(*zstream));
184 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
185 GFP_ATOMIC | __GFP_NOWARN);
186 if (!zstream->workspace)
189 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
190 kfree(zstream->workspace);
197 static int compress_page(struct z_stream_s *zstream,
199 struct drm_i915_error_object *dst)
201 zstream->next_in = src;
202 zstream->avail_in = PAGE_SIZE;
205 if (zstream->avail_out == 0) {
208 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
212 dst->pages[dst->page_count++] = (void *)page;
214 zstream->next_out = (void *)page;
215 zstream->avail_out = PAGE_SIZE;
218 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
220 } while (zstream->avail_in);
222 /* Fallback to uncompressed if we increase size? */
223 if (0 && zstream->total_out > zstream->total_in)
229 static void compress_fini(struct z_stream_s *zstream,
230 struct drm_i915_error_object *dst)
233 zlib_deflate(zstream, Z_FINISH);
234 dst->unused = zstream->avail_out;
237 zlib_deflateEnd(zstream);
238 kfree(zstream->workspace);
241 static void err_compression_marker(struct drm_i915_error_state_buf *m)
248 static bool compress_init(struct z_stream_s *zstream)
253 static int compress_page(struct z_stream_s *zstream,
255 struct drm_i915_error_object *dst)
259 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
263 dst->pages[dst->page_count++] =
264 memcpy((void *)page, src, PAGE_SIZE);
269 static void compress_fini(struct z_stream_s *zstream,
270 struct drm_i915_error_object *dst)
274 static void err_compression_marker(struct drm_i915_error_state_buf *m)
281 static void print_error_buffers(struct drm_i915_error_state_buf *m,
283 struct drm_i915_error_buffer *err,
288 err_printf(m, "%s [%d]:\n", name, count);
291 err_printf(m, " %08x_%08x %8u %02x %02x [ ",
292 upper_32_bits(err->gtt_offset),
293 lower_32_bits(err->gtt_offset),
297 for (i = 0; i < I915_NUM_ENGINES; i++)
298 err_printf(m, "%02x ", err->rseqno[i]);
300 err_printf(m, "] %02x", err->wseqno);
301 err_puts(m, tiling_flag(err->tiling));
302 err_puts(m, dirty_flag(err->dirty));
303 err_puts(m, purgeable_flag(err->purgeable));
304 err_puts(m, err->userptr ? " userptr" : "");
305 err_puts(m, err->engine != -1 ? " " : "");
306 err_puts(m, engine_str(err->engine));
307 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
310 err_printf(m, " (name: %d)", err->name);
311 if (err->fence_reg != I915_FENCE_REG_NONE)
312 err_printf(m, " (fence: %d)", err->fence_reg);
319 static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
326 case HANGCHECK_ACTIVE:
337 static void error_print_instdone(struct drm_i915_error_state_buf *m,
338 struct drm_i915_error_engine *ee)
343 err_printf(m, " INSTDONE: 0x%08x\n",
344 ee->instdone.instdone);
346 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
349 err_printf(m, " SC_INSTDONE: 0x%08x\n",
350 ee->instdone.slice_common);
352 if (INTEL_GEN(m->i915) <= 6)
355 for_each_instdone_slice_subslice(m->i915, slice, subslice)
356 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
358 ee->instdone.sampler[slice][subslice]);
360 for_each_instdone_slice_subslice(m->i915, slice, subslice)
361 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
363 ee->instdone.row[slice][subslice]);
366 static void error_print_request(struct drm_i915_error_state_buf *m,
368 struct drm_i915_error_request *erq)
373 err_printf(m, "%s pid %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
375 erq->context, erq->seqno,
376 jiffies_to_msecs(jiffies - erq->jiffies),
377 erq->head, erq->tail);
380 static void error_print_engine(struct drm_i915_error_state_buf *m,
381 struct drm_i915_error_engine *ee)
383 err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
384 err_printf(m, " START: 0x%08x\n", ee->start);
385 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
386 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
387 ee->tail, ee->rq_post, ee->rq_tail);
388 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
389 err_printf(m, " MODE: 0x%08x\n", ee->mode);
390 err_printf(m, " HWS: 0x%08x\n", ee->hws);
391 err_printf(m, " ACTHD: 0x%08x %08x\n",
392 (u32)(ee->acthd>>32), (u32)ee->acthd);
393 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
394 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
396 error_print_instdone(m, ee);
398 if (ee->batchbuffer) {
399 u64 start = ee->batchbuffer->gtt_offset;
400 u64 end = start + ee->batchbuffer->gtt_size;
402 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
403 upper_32_bits(start), lower_32_bits(start),
404 upper_32_bits(end), lower_32_bits(end));
406 if (INTEL_GEN(m->i915) >= 4) {
407 err_printf(m, " BBADDR: 0x%08x_%08x\n",
408 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
409 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
410 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
412 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
413 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
414 lower_32_bits(ee->faddr));
415 if (INTEL_GEN(m->i915) >= 6) {
416 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
417 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
418 err_printf(m, " SYNC_0: 0x%08x\n",
419 ee->semaphore_mboxes[0]);
420 err_printf(m, " SYNC_1: 0x%08x\n",
421 ee->semaphore_mboxes[1]);
422 if (HAS_VEBOX(m->i915))
423 err_printf(m, " SYNC_2: 0x%08x\n",
424 ee->semaphore_mboxes[2]);
426 if (USES_PPGTT(m->i915)) {
427 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
429 if (INTEL_GEN(m->i915) >= 8) {
431 for (i = 0; i < 4; i++)
432 err_printf(m, " PDP%d: 0x%016llx\n",
433 i, ee->vm_info.pdp[i]);
435 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
436 ee->vm_info.pp_dir_base);
439 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
440 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
441 err_printf(m, " waiting: %s\n", yesno(ee->waiting));
442 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
443 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
444 err_printf(m, " hangcheck: %s [%d]\n",
445 hangcheck_action_to_str(ee->hangcheck_action),
446 ee->hangcheck_score);
447 error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
448 error_print_request(m, " ELSP[1]: ", &ee->execlist[1]);
451 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
456 i915_error_vprintf(e, f, args);
461 ascii85_encode_len(int len)
463 return DIV_ROUND_UP(len, 4);
467 ascii85_encode(u32 in, char *out)
476 out[i] = '!' + in % 85;
483 static void print_error_obj(struct drm_i915_error_state_buf *m,
484 struct intel_engine_cs *engine,
486 struct drm_i915_error_object *obj)
495 err_printf(m, "%s --- %s = 0x%08x %08x\n",
496 engine ? engine->name : "global", name,
497 upper_32_bits(obj->gtt_offset),
498 lower_32_bits(obj->gtt_offset));
501 err_compression_marker(m);
502 for (page = 0; page < obj->page_count; page++) {
506 if (page == obj->page_count - 1)
508 len = ascii85_encode_len(len);
510 for (i = 0; i < len; i++) {
511 if (ascii85_encode(obj->pages[page][i], out))
520 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
521 const struct intel_device_info *info)
523 #define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
524 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
528 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
529 const struct i915_error_state_file_priv *error_priv)
531 struct drm_device *dev = error_priv->dev;
532 struct drm_i915_private *dev_priv = to_i915(dev);
533 struct pci_dev *pdev = dev_priv->drm.pdev;
534 struct drm_i915_error_state *error = error_priv->error;
535 struct drm_i915_error_object *obj;
536 int max_hangcheck_score;
540 err_printf(m, "no error state collected\n");
544 err_printf(m, "%s\n", error->error_msg);
545 err_printf(m, "Kernel: " UTS_RELEASE "\n");
546 err_printf(m, "Time: %ld s %ld us\n",
547 error->time.tv_sec, error->time.tv_usec);
548 err_printf(m, "Boottime: %ld s %ld us\n",
549 error->boottime.tv_sec, error->boottime.tv_usec);
550 err_printf(m, "Uptime: %ld s %ld us\n",
551 error->uptime.tv_sec, error->uptime.tv_usec);
552 err_print_capabilities(m, &error->device_info);
553 max_hangcheck_score = 0;
554 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
555 if (error->engine[i].hangcheck_score > max_hangcheck_score)
556 max_hangcheck_score = error->engine[i].hangcheck_score;
558 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
559 if (error->engine[i].hangcheck_score == max_hangcheck_score &&
560 error->engine[i].pid != -1) {
561 err_printf(m, "Active process (on ring %s): %s [%d]\n",
563 error->engine[i].comm,
564 error->engine[i].pid);
567 err_printf(m, "Reset count: %u\n", error->reset_count);
568 err_printf(m, "Suspend count: %u\n", error->suspend_count);
569 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
570 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
571 err_printf(m, "PCI Subsystem: %04x:%04x\n",
572 pdev->subsystem_vendor,
573 pdev->subsystem_device);
574 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
577 struct intel_csr *csr = &dev_priv->csr;
579 err_printf(m, "DMC loaded: %s\n",
580 yesno(csr->dmc_payload != NULL));
581 err_printf(m, "DMC fw version: %d.%d\n",
582 CSR_VERSION_MAJOR(csr->version),
583 CSR_VERSION_MINOR(csr->version));
586 err_printf(m, "EIR: 0x%08x\n", error->eir);
587 err_printf(m, "IER: 0x%08x\n", error->ier);
588 if (INTEL_INFO(dev)->gen >= 8) {
589 for (i = 0; i < 4; i++)
590 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
592 } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
593 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
594 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
595 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
596 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
597 err_printf(m, "CCID: 0x%08x\n", error->ccid);
598 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
600 for (i = 0; i < dev_priv->num_fence_regs; i++)
601 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
603 if (INTEL_INFO(dev)->gen >= 6) {
604 err_printf(m, "ERROR: 0x%08x\n", error->error);
606 if (INTEL_INFO(dev)->gen >= 8)
607 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
608 error->fault_data1, error->fault_data0);
610 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
613 if (IS_GEN7(dev_priv))
614 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
616 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
617 if (error->engine[i].engine_id != -1)
618 error_print_engine(m, &error->engine[i]);
621 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
625 if (!error->active_vm[i])
628 len = scnprintf(buf, sizeof(buf), "Active (");
629 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
630 if (error->engine[j].vm != error->active_vm[i])
633 len += scnprintf(buf + len, sizeof(buf), "%s%s",
635 dev_priv->engine[j]->name);
638 scnprintf(buf + len, sizeof(buf), ")");
639 print_error_buffers(m, buf,
641 error->active_bo_count[i]);
644 print_error_buffers(m, "Pinned (global)",
646 error->pinned_bo_count);
648 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
649 struct drm_i915_error_engine *ee = &error->engine[i];
651 obj = ee->batchbuffer;
653 err_puts(m, dev_priv->engine[i]->name);
655 err_printf(m, " (submitted by %s [%d])",
658 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
659 upper_32_bits(obj->gtt_offset),
660 lower_32_bits(obj->gtt_offset));
661 print_error_obj(m, dev_priv->engine[i], NULL, obj);
664 if (ee->num_requests) {
665 err_printf(m, "%s --- %d requests\n",
666 dev_priv->engine[i]->name,
668 for (j = 0; j < ee->num_requests; j++)
669 error_print_request(m, " ", &ee->requests[j]);
672 if (IS_ERR(ee->waiters)) {
673 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
674 dev_priv->engine[i]->name);
675 } else if (ee->num_waiters) {
676 err_printf(m, "%s --- %d waiters\n",
677 dev_priv->engine[i]->name,
679 for (j = 0; j < ee->num_waiters; j++) {
680 err_printf(m, " seqno 0x%08x for %s [%d]\n",
681 ee->waiters[j].seqno,
687 print_error_obj(m, dev_priv->engine[i],
688 "ringbuffer", ee->ringbuffer);
690 print_error_obj(m, dev_priv->engine[i],
691 "HW Status", ee->hws_page);
693 print_error_obj(m, dev_priv->engine[i],
694 "HW context", ee->ctx);
696 print_error_obj(m, dev_priv->engine[i],
697 "WA context", ee->wa_ctx);
699 print_error_obj(m, dev_priv->engine[i],
700 "WA batchbuffer", ee->wa_batchbuffer);
703 print_error_obj(m, NULL, "Semaphores", error->semaphore);
705 print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
708 intel_overlay_print_error_state(m, error->overlay);
711 intel_display_print_error_state(m, dev, error->display);
714 if (m->bytes == 0 && m->err)
720 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
721 struct drm_i915_private *i915,
722 size_t count, loff_t pos)
724 memset(ebuf, 0, sizeof(*ebuf));
727 /* We need to have enough room to store any i915_error_state printf
728 * so that we can move it to start position.
730 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
731 ebuf->buf = kmalloc(ebuf->size,
732 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
734 if (ebuf->buf == NULL) {
735 ebuf->size = PAGE_SIZE;
736 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
739 if (ebuf->buf == NULL) {
741 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
744 if (ebuf->buf == NULL)
752 static void i915_error_object_free(struct drm_i915_error_object *obj)
759 for (page = 0; page < obj->page_count; page++)
760 free_page((unsigned long)obj->pages[page]);
765 static void i915_error_state_free(struct kref *error_ref)
767 struct drm_i915_error_state *error = container_of(error_ref,
768 typeof(*error), ref);
771 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
772 struct drm_i915_error_engine *ee = &error->engine[i];
774 i915_error_object_free(ee->batchbuffer);
775 i915_error_object_free(ee->wa_batchbuffer);
776 i915_error_object_free(ee->ringbuffer);
777 i915_error_object_free(ee->hws_page);
778 i915_error_object_free(ee->ctx);
779 i915_error_object_free(ee->wa_ctx);
782 if (!IS_ERR_OR_NULL(ee->waiters))
786 i915_error_object_free(error->semaphore);
787 i915_error_object_free(error->guc_log);
789 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
790 kfree(error->active_bo[i]);
791 kfree(error->pinned_bo);
793 kfree(error->overlay);
794 kfree(error->display);
798 static struct drm_i915_error_object *
799 i915_error_object_create(struct drm_i915_private *i915,
800 struct i915_vma *vma)
802 struct i915_ggtt *ggtt = &i915->ggtt;
803 const u64 slot = ggtt->error_capture.start;
804 struct drm_i915_error_object *dst;
805 struct z_stream_s zstream;
806 unsigned long num_pages;
807 struct sgt_iter iter;
813 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
814 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
815 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
816 GFP_ATOMIC | __GFP_NOWARN);
820 dst->gtt_offset = vma->node.start;
821 dst->gtt_size = vma->node.size;
825 if (!compress_init(&zstream)) {
830 for_each_sgt_dma(dma, iter, vma->pages) {
834 ggtt->base.insert_page(&ggtt->base, dma, slot,
837 s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
838 ret = compress_page(&zstream, (void __force *)s, dst);
839 io_mapping_unmap_atomic(s);
847 while (dst->page_count--)
848 free_page((unsigned long)dst->pages[dst->page_count]);
853 compress_fini(&zstream, dst);
854 ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
858 /* The error capture is special as tries to run underneath the normal
859 * locking rules - so we use the raw version of the i915_gem_active lookup.
861 static inline uint32_t
862 __active_get_seqno(struct i915_gem_active *active)
864 return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
868 __active_get_engine_id(struct i915_gem_active *active)
870 struct intel_engine_cs *engine;
872 engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
873 return engine ? engine->id : -1;
876 static void capture_bo(struct drm_i915_error_buffer *err,
877 struct i915_vma *vma)
879 struct drm_i915_gem_object *obj = vma->obj;
882 err->size = obj->base.size;
883 err->name = obj->base.name;
885 for (i = 0; i < I915_NUM_ENGINES; i++)
886 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
887 err->wseqno = __active_get_seqno(&vma->last_write);
888 err->engine = __active_get_engine_id(&vma->last_write);
890 err->gtt_offset = vma->node.start;
891 err->read_domains = obj->base.read_domains;
892 err->write_domain = obj->base.write_domain;
893 err->fence_reg = vma->fence ? vma->fence->id : -1;
894 err->tiling = i915_gem_object_get_tiling(obj);
895 err->dirty = obj->mm.dirty;
896 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
897 err->userptr = obj->userptr.mm != NULL;
898 err->cache_level = obj->cache_level;
901 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
902 int count, struct list_head *head,
905 struct i915_vma *vma;
908 list_for_each_entry(vma, head, vm_link) {
909 if (pinned_only && !i915_vma_is_pinned(vma))
912 capture_bo(err++, vma);
920 /* Generate a semi-unique error code. The code is not meant to have meaning, The
921 * code's only purpose is to try to prevent false duplicated bug reports by
922 * grossly estimating a GPU error state.
924 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
925 * the hang if we could strip the GTT offset information from it.
927 * It's only a small step better than a random number in its current form.
929 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
930 struct drm_i915_error_state *error,
933 uint32_t error_code = 0;
936 /* IPEHR would be an ideal way to detect errors, as it's the gross
937 * measure of "the command that hung." However, has some very common
938 * synchronization commands which almost always appear in the case
939 * strictly a client bug. Use instdone to differentiate those some.
941 for (i = 0; i < I915_NUM_ENGINES; i++) {
942 if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
946 return error->engine[i].ipehr ^
947 error->engine[i].instdone.instdone;
954 static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
955 struct drm_i915_error_state *error)
959 if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
960 for (i = 0; i < dev_priv->num_fence_regs; i++)
961 error->fence[i] = I915_READ(FENCE_REG(i));
962 } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
963 for (i = 0; i < dev_priv->num_fence_regs; i++)
964 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
965 } else if (INTEL_GEN(dev_priv) >= 6) {
966 for (i = 0; i < dev_priv->num_fence_regs; i++)
967 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
972 gen8_engine_sync_index(struct intel_engine_cs *engine,
973 struct intel_engine_cs *other)
978 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
979 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
980 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
981 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
982 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
985 idx = (other - engine) - 1;
987 idx += I915_NUM_ENGINES;
992 static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
993 struct intel_engine_cs *engine,
994 struct drm_i915_error_engine *ee)
996 struct drm_i915_private *dev_priv = engine->i915;
997 struct intel_engine_cs *to;
998 enum intel_engine_id id;
1000 if (!error->semaphore)
1003 for_each_engine(to, dev_priv, id) {
1012 (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
1013 tmp = error->semaphore->pages[0];
1014 idx = gen8_engine_sync_index(engine, to);
1016 ee->semaphore_mboxes[idx] = tmp[signal_offset];
1020 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1021 struct drm_i915_error_engine *ee)
1023 struct drm_i915_private *dev_priv = engine->i915;
1025 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1026 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1027 if (HAS_VEBOX(dev_priv))
1028 ee->semaphore_mboxes[2] =
1029 I915_READ(RING_SYNC_2(engine->mmio_base));
1032 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1033 struct drm_i915_error_engine *ee)
1035 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1036 struct drm_i915_error_waiter *waiter;
1040 ee->num_waiters = 0;
1043 if (RB_EMPTY_ROOT(&b->waiters))
1046 if (!spin_trylock_irq(&b->lock)) {
1047 ee->waiters = ERR_PTR(-EDEADLK);
1052 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1054 spin_unlock_irq(&b->lock);
1058 waiter = kmalloc_array(count,
1059 sizeof(struct drm_i915_error_waiter),
1064 if (!spin_trylock_irq(&b->lock)) {
1066 ee->waiters = ERR_PTR(-EDEADLK);
1070 ee->waiters = waiter;
1071 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1072 struct intel_wait *w = container_of(rb, typeof(*w), node);
1074 strcpy(waiter->comm, w->tsk->comm);
1075 waiter->pid = w->tsk->pid;
1076 waiter->seqno = w->seqno;
1079 if (++ee->num_waiters == count)
1082 spin_unlock_irq(&b->lock);
1085 static void error_record_engine_registers(struct drm_i915_error_state *error,
1086 struct intel_engine_cs *engine,
1087 struct drm_i915_error_engine *ee)
1089 struct drm_i915_private *dev_priv = engine->i915;
1091 if (INTEL_GEN(dev_priv) >= 6) {
1092 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1093 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1094 if (INTEL_GEN(dev_priv) >= 8)
1095 gen8_record_semaphore_state(error, engine, ee);
1097 gen6_record_semaphore_state(engine, ee);
1100 if (INTEL_GEN(dev_priv) >= 4) {
1101 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1102 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1103 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1104 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1105 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1106 if (INTEL_GEN(dev_priv) >= 8) {
1107 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1108 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1110 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1112 ee->faddr = I915_READ(DMA_FADD_I8XX);
1113 ee->ipeir = I915_READ(IPEIR);
1114 ee->ipehr = I915_READ(IPEHR);
1117 intel_engine_get_instdone(engine, &ee->instdone);
1119 ee->waiting = intel_engine_has_waiter(engine);
1120 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1121 ee->acthd = intel_engine_get_active_head(engine);
1122 ee->seqno = intel_engine_get_seqno(engine);
1123 ee->last_seqno = engine->timeline->last_submitted_seqno;
1124 ee->start = I915_READ_START(engine);
1125 ee->head = I915_READ_HEAD(engine);
1126 ee->tail = I915_READ_TAIL(engine);
1127 ee->ctl = I915_READ_CTL(engine);
1128 if (INTEL_GEN(dev_priv) > 2)
1129 ee->mode = I915_READ_MODE(engine);
1131 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1134 if (IS_GEN7(dev_priv)) {
1135 switch (engine->id) {
1138 mmio = RENDER_HWS_PGA_GEN7;
1141 mmio = BLT_HWS_PGA_GEN7;
1144 mmio = BSD_HWS_PGA_GEN7;
1147 mmio = VEBOX_HWS_PGA_GEN7;
1150 } else if (IS_GEN6(engine->i915)) {
1151 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1153 /* XXX: gen8 returns to sanity */
1154 mmio = RING_HWS_PGA(engine->mmio_base);
1157 ee->hws = I915_READ(mmio);
1160 ee->hangcheck_score = engine->hangcheck.score;
1161 ee->hangcheck_action = engine->hangcheck.action;
1163 if (USES_PPGTT(dev_priv)) {
1166 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1168 if (IS_GEN6(dev_priv))
1169 ee->vm_info.pp_dir_base =
1170 I915_READ(RING_PP_DIR_BASE_READ(engine));
1171 else if (IS_GEN7(dev_priv))
1172 ee->vm_info.pp_dir_base =
1173 I915_READ(RING_PP_DIR_BASE(engine));
1174 else if (INTEL_GEN(dev_priv) >= 8)
1175 for (i = 0; i < 4; i++) {
1176 ee->vm_info.pdp[i] =
1177 I915_READ(GEN8_RING_PDP_UDW(engine, i));
1178 ee->vm_info.pdp[i] <<= 32;
1179 ee->vm_info.pdp[i] |=
1180 I915_READ(GEN8_RING_PDP_LDW(engine, i));
1185 static void record_request(struct drm_i915_gem_request *request,
1186 struct drm_i915_error_request *erq)
1188 erq->context = request->ctx->hw_id;
1189 erq->seqno = request->global_seqno;
1190 erq->jiffies = request->emitted_jiffies;
1191 erq->head = request->head;
1192 erq->tail = request->tail;
1195 erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1199 static void engine_record_requests(struct intel_engine_cs *engine,
1200 struct drm_i915_gem_request *first,
1201 struct drm_i915_error_engine *ee)
1203 struct drm_i915_gem_request *request;
1208 list_for_each_entry_from(request, &engine->timeline->requests, link)
1213 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1217 ee->num_requests = count;
1221 list_for_each_entry_from(request, &engine->timeline->requests, link) {
1222 if (count >= ee->num_requests) {
1224 * If the ring request list was changed in
1225 * between the point where the error request
1226 * list was created and dimensioned and this
1227 * point then just exit early to avoid crashes.
1229 * We don't need to communicate that the
1230 * request list changed state during error
1231 * state capture and that the error state is
1232 * slightly incorrect as a consequence since we
1233 * are typically only interested in the request
1234 * list state at the point of error state
1235 * capture, not in any changes happening during
1241 record_request(request, &ee->requests[count++]);
1243 ee->num_requests = count;
1246 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1247 struct drm_i915_error_engine *ee)
1251 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
1252 if (engine->execlist_port[n].request)
1253 record_request(engine->execlist_port[n].request,
1257 static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1258 struct drm_i915_error_state *error)
1260 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1264 i915_error_object_create(dev_priv, dev_priv->semaphore);
1266 for (i = 0; i < I915_NUM_ENGINES; i++) {
1267 struct intel_engine_cs *engine = dev_priv->engine[i];
1268 struct drm_i915_error_engine *ee = &error->engine[i];
1269 struct drm_i915_gem_request *request;
1279 error_record_engine_registers(error, engine, ee);
1280 error_record_engine_waiters(engine, ee);
1281 error_record_engine_execlists(engine, ee);
1283 request = i915_gem_find_active_request(engine);
1285 struct intel_ring *ring;
1288 ee->vm = request->ctx->ppgtt ?
1289 &request->ctx->ppgtt->base : &ggtt->base;
1291 /* We need to copy these to an anonymous buffer
1292 * as the simplest method to avoid being overwritten
1296 i915_error_object_create(dev_priv,
1299 if (HAS_BROKEN_CS_TLB(dev_priv))
1300 ee->wa_batchbuffer =
1301 i915_error_object_create(dev_priv,
1305 i915_error_object_create(dev_priv,
1306 request->ctx->engine[i].state);
1308 pid = request->ctx->pid;
1310 struct task_struct *task;
1313 task = pid_task(pid, PIDTYPE_PID);
1315 strcpy(ee->comm, task->comm);
1316 ee->pid = task->pid;
1322 request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
1324 ee->rq_head = request->head;
1325 ee->rq_post = request->postfix;
1326 ee->rq_tail = request->tail;
1328 ring = request->ring;
1329 ee->cpu_ring_head = ring->head;
1330 ee->cpu_ring_tail = ring->tail;
1332 i915_error_object_create(dev_priv, ring->vma);
1334 engine_record_requests(engine, request, ee);
1338 i915_error_object_create(dev_priv,
1339 engine->status_page.vma);
1342 i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1346 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1347 struct drm_i915_error_state *error,
1348 struct i915_address_space *vm,
1351 struct drm_i915_error_buffer *active_bo;
1352 struct i915_vma *vma;
1356 list_for_each_entry(vma, &vm->active_list, vm_link)
1361 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1363 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1367 error->active_vm[idx] = vm;
1368 error->active_bo[idx] = active_bo;
1369 error->active_bo_count[idx] = count;
1372 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1373 struct drm_i915_error_state *error)
1377 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1378 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1379 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1381 /* Scan each engine looking for unique active contexts/vm */
1382 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1383 struct drm_i915_error_engine *ee = &error->engine[i];
1390 for (j = 0; j < i && !found; j++)
1391 found = error->engine[j].vm == ee->vm;
1393 i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1397 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1398 struct drm_i915_error_state *error)
1400 struct i915_address_space *vm = &dev_priv->ggtt.base;
1401 struct drm_i915_error_buffer *bo;
1402 struct i915_vma *vma;
1403 int count_inactive, count_active;
1406 list_for_each_entry(vma, &vm->active_list, vm_link)
1410 list_for_each_entry(vma, &vm->inactive_list, vm_link)
1414 if (count_inactive + count_active)
1415 bo = kcalloc(count_inactive + count_active,
1416 sizeof(*bo), GFP_ATOMIC);
1420 count_inactive = capture_error_bo(bo, count_inactive,
1421 &vm->active_list, true);
1422 count_active = capture_error_bo(bo + count_inactive, count_active,
1423 &vm->inactive_list, true);
1424 error->pinned_bo_count = count_inactive + count_active;
1425 error->pinned_bo = bo;
1428 static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
1429 struct drm_i915_error_state *error)
1431 /* Capturing log buf contents won't be useful if logging was disabled */
1432 if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
1435 error->guc_log = i915_error_object_create(dev_priv,
1436 dev_priv->guc.log.vma);
1439 /* Capture all registers which don't fit into another category. */
1440 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1441 struct drm_i915_error_state *error)
1443 struct drm_device *dev = &dev_priv->drm;
1446 /* General organization
1447 * 1. Registers specific to a single generation
1448 * 2. Registers which belong to multiple generations
1449 * 3. Feature specific registers.
1450 * 4. Everything else
1451 * Please try to follow the order.
1454 /* 1: Registers specific to a single generation */
1455 if (IS_VALLEYVIEW(dev_priv)) {
1456 error->gtier[0] = I915_READ(GTIER);
1457 error->ier = I915_READ(VLV_IER);
1458 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1461 if (IS_GEN7(dev_priv))
1462 error->err_int = I915_READ(GEN7_ERR_INT);
1464 if (INTEL_INFO(dev)->gen >= 8) {
1465 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1466 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1469 if (IS_GEN6(dev_priv)) {
1470 error->forcewake = I915_READ_FW(FORCEWAKE);
1471 error->gab_ctl = I915_READ(GAB_CTL);
1472 error->gfx_mode = I915_READ(GFX_MODE);
1475 /* 2: Registers which belong to multiple generations */
1476 if (INTEL_INFO(dev)->gen >= 7)
1477 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1479 if (INTEL_INFO(dev)->gen >= 6) {
1480 error->derrmr = I915_READ(DERRMR);
1481 error->error = I915_READ(ERROR_GEN6);
1482 error->done_reg = I915_READ(DONE_REG);
1485 /* 3: Feature specific registers */
1486 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1487 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1488 error->gac_eco = I915_READ(GAC_ECO_BITS);
1491 /* 4: Everything else */
1492 if (HAS_HW_CONTEXTS(dev))
1493 error->ccid = I915_READ(CCID);
1495 if (INTEL_INFO(dev)->gen >= 8) {
1496 error->ier = I915_READ(GEN8_DE_MISC_IER);
1497 for (i = 0; i < 4; i++)
1498 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1499 } else if (HAS_PCH_SPLIT(dev_priv)) {
1500 error->ier = I915_READ(DEIER);
1501 error->gtier[0] = I915_READ(GTIER);
1502 } else if (IS_GEN2(dev_priv)) {
1503 error->ier = I915_READ16(IER);
1504 } else if (!IS_VALLEYVIEW(dev_priv)) {
1505 error->ier = I915_READ(IER);
1507 error->eir = I915_READ(EIR);
1508 error->pgtbl_er = I915_READ(PGTBL_ER);
1511 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1512 struct drm_i915_error_state *error,
1514 const char *error_msg)
1517 int engine_id = -1, len;
1519 ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1521 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1522 "GPU HANG: ecode %d:%d:0x%08x",
1523 INTEL_GEN(dev_priv), engine_id, ecode);
1525 if (engine_id != -1 && error->engine[engine_id].pid != -1)
1526 len += scnprintf(error->error_msg + len,
1527 sizeof(error->error_msg) - len,
1529 error->engine[engine_id].comm,
1530 error->engine[engine_id].pid);
1532 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1533 ", reason: %s, action: %s",
1535 engine_mask ? "reset" : "continue");
1538 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1539 struct drm_i915_error_state *error)
1542 #ifdef CONFIG_INTEL_IOMMU
1543 error->iommu = intel_iommu_gfx_mapped;
1545 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1546 error->suspend_count = dev_priv->suspend_count;
1548 memcpy(&error->device_info,
1549 INTEL_INFO(dev_priv),
1550 sizeof(error->device_info));
1553 static int capture(void *data)
1555 struct drm_i915_error_state *error = data;
1557 i915_capture_gen_state(error->i915, error);
1558 i915_capture_reg_state(error->i915, error);
1559 i915_gem_record_fences(error->i915, error);
1560 i915_gem_record_rings(error->i915, error);
1561 i915_capture_active_buffers(error->i915, error);
1562 i915_capture_pinned_buffers(error->i915, error);
1563 i915_gem_capture_guc_log_buffer(error->i915, error);
1565 do_gettimeofday(&error->time);
1566 error->boottime = ktime_to_timeval(ktime_get_boottime());
1568 ktime_to_timeval(ktime_sub(ktime_get(),
1569 error->i915->gt.last_init_time));
1571 error->overlay = intel_overlay_capture_error_state(error->i915);
1572 error->display = intel_display_capture_error_state(error->i915);
1577 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1580 * i915_capture_error_state - capture an error record for later analysis
1583 * Should be called when an error is detected (either a hang or an error
1584 * interrupt) to capture error state from the time of the error. Fills
1585 * out a structure which becomes available in debugfs for user level tools
1588 void i915_capture_error_state(struct drm_i915_private *dev_priv,
1590 const char *error_msg)
1593 struct drm_i915_error_state *error;
1594 unsigned long flags;
1596 if (!i915.error_capture)
1599 if (READ_ONCE(dev_priv->gpu_error.first_error))
1602 /* Account for pipe specific data like PIPE*STAT */
1603 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1605 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1609 kref_init(&error->ref);
1610 error->i915 = dev_priv;
1612 stop_machine(capture, error, NULL);
1614 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1615 DRM_INFO("%s\n", error->error_msg);
1617 if (!error->simulated) {
1618 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1619 if (!dev_priv->gpu_error.first_error) {
1620 dev_priv->gpu_error.first_error = error;
1623 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1627 i915_error_state_free(&error->ref);
1632 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1633 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1634 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1635 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1636 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1637 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1638 dev_priv->drm.primary->index);
1643 void i915_error_state_get(struct drm_device *dev,
1644 struct i915_error_state_file_priv *error_priv)
1646 struct drm_i915_private *dev_priv = to_i915(dev);
1648 spin_lock_irq(&dev_priv->gpu_error.lock);
1649 error_priv->error = dev_priv->gpu_error.first_error;
1650 if (error_priv->error)
1651 kref_get(&error_priv->error->ref);
1652 spin_unlock_irq(&dev_priv->gpu_error.lock);
1655 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1657 if (error_priv->error)
1658 kref_put(&error_priv->error->ref, i915_error_state_free);
1661 void i915_destroy_error_state(struct drm_device *dev)
1663 struct drm_i915_private *dev_priv = to_i915(dev);
1664 struct drm_i915_error_state *error;
1666 spin_lock_irq(&dev_priv->gpu_error.lock);
1667 error = dev_priv->gpu_error.first_error;
1668 dev_priv->gpu_error.first_error = NULL;
1669 spin_unlock_irq(&dev_priv->gpu_error.lock);
1672 kref_put(&error->ref, i915_error_state_free);