drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include "i915_drv.h"
  32
  33 static const char *yesno(int v)
  34 {
  35         return v ? "yes" : "no";
  36 }
  37
  38 static const char *ring_str(int ring)
  39 {
  40         switch (ring) {
  41         case RCS: return "render";
  42         case VCS: return "bsd";
  43         case BCS: return "blt";
  44         case VECS: return "vebox";
  45         default: return "";
  46         }
  47 }
  48
  49 static const char *pin_flag(int pinned)
  50 {
  51         if (pinned > 0)
  52                 return " P";
  53         else if (pinned < 0)
  54                 return " p";
  55         else
  56                 return "";
  57 }
  58
  59 static const char *tiling_flag(int tiling)
  60 {
  61         switch (tiling) {
  62         default:
  63         case I915_TILING_NONE: return "";
  64         case I915_TILING_X: return " X";
  65         case I915_TILING_Y: return " Y";
  66         }
  67 }
  68
  69 static const char *dirty_flag(int dirty)
  70 {
  71         return dirty ? " dirty" : "";
  72 }
  73
  74 static const char *purgeable_flag(int purgeable)
  75 {
  76         return purgeable ? " purgeable" : "";
  77 }
  78
  79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  80 {
  81
  82         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  83                 e->err = -ENOSPC;
  84                 return false;
  85         }
  86
  87         if (e->bytes == e->size - 1 || e->err)
  88                 return false;
  89
  90         return true;
  91 }
  92
  93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  94                               unsigned len)
  95 {
  96         if (e->pos + len <= e->start) {
  97                 e->pos += len;
  98                 return false;
  99         }
 100
 101         /* First vsnprintf needs to fit in its entirety for memmove */
 102         if (len >= e->size) {
 103                 e->err = -EIO;
 104                 return false;
 105         }
 106
 107         return true;
 108 }
 109
 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 111                                  unsigned len)
 112 {
 113         /* If this is first printf in this window, adjust it so that
 114          * start position matches start of the buffer
 115          */
 116
 117         if (e->pos < e->start) {
 118                 const size_t off = e->start - e->pos;
 119
 120                 /* Should not happen but be paranoid */
 121                 if (off > len || e->bytes) {
 122                         e->err = -EIO;
 123                         return;
 124                 }
 125
 126                 memmove(e->buf, e->buf + off, len - off);
 127                 e->bytes = len - off;
 128                 e->pos = e->start;
 129                 return;
 130         }
 131
 132         e->bytes += len;
 133         e->pos += len;
 134 }
 135
 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 137                                const char *f, va_list args)
 138 {
 139         unsigned len;
 140
 141         if (!__i915_error_ok(e))
 142                 return;
 143
 144         /* Seek the first printf which is hits start position */
 145         if (e->pos < e->start) {
 146                 va_list tmp;
 147
 148                 va_copy(tmp, args);
 149                 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
 150                         return;
 151         }
 152
 153         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 154         if (len >= e->size - e->bytes)
 155                 len = e->size - e->bytes - 1;
 156
 157         __i915_error_advance(e, len);
 158 }
 159
 160 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 161                             const char *str)
 162 {
 163         unsigned len;
 164
 165         if (!__i915_error_ok(e))
 166                 return;
 167
 168         len = strlen(str);
 169
 170         /* Seek the first printf which is hits start position */
 171         if (e->pos < e->start) {
 172                 if (!__i915_error_seek(e, len))
 173                         return;
 174         }
 175
 176         if (len >= e->size - e->bytes)
 177                 len = e->size - e->bytes - 1;
 178         memcpy(e->buf + e->bytes, str, len);
 179
 180         __i915_error_advance(e, len);
 181 }
 182
 183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 184 #define err_puts(e, s) i915_error_puts(e, s)
 185
 186 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 187                                 const char *name,
 188                                 struct drm_i915_error_buffer *err,
 189                                 int count)
 190 {
 191         err_printf(m, "%s [%d]:\n", name, count);
 192
 193         while (count--) {
 194                 err_printf(m, "  %08x %8u %02x %02x %x %x",
 195                            err->gtt_offset,
 196                            err->size,
 197                            err->read_domains,
 198                            err->write_domain,
 199                            err->rseqno, err->wseqno);
 200                 err_puts(m, pin_flag(err->pinned));
 201                 err_puts(m, tiling_flag(err->tiling));
 202                 err_puts(m, dirty_flag(err->dirty));
 203                 err_puts(m, purgeable_flag(err->purgeable));
 204                 err_puts(m, err->ring != -1 ? " " : "");
 205                 err_puts(m, ring_str(err->ring));
 206                 err_puts(m, i915_cache_level_str(err->cache_level));
 207
 208                 if (err->name)
 209                         err_printf(m, " (name: %d)", err->name);
 210                 if (err->fence_reg != I915_FENCE_REG_NONE)
 211                         err_printf(m, " (fence: %d)", err->fence_reg);
 212
 213                 err_puts(m, "\n");
 214                 err++;
 215         }
 216 }
 217
 218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
 219 {
 220         switch (a) {
 221         case HANGCHECK_IDLE:
 222                 return "idle";
 223         case HANGCHECK_WAIT:
 224                 return "wait";
 225         case HANGCHECK_ACTIVE:
 226                 return "active";
 227         case HANGCHECK_KICK:
 228                 return "kick";
 229         case HANGCHECK_HUNG:
 230                 return "hung";
 231         }
 232
 233         return "unknown";
 234 }
 235
 236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
 237                                   struct drm_device *dev,
 238                                   struct drm_i915_error_ring *ring)
 239 {
 240         if (!ring->valid)
 241                 return;
 242
 243         err_printf(m, "  HEAD: 0x%08x\n", ring->head);
 244         err_printf(m, "  TAIL: 0x%08x\n", ring->tail);
 245         err_printf(m, "  CTL: 0x%08x\n", ring->ctl);
 246         err_printf(m, "  HWS: 0x%08x\n", ring->hws);
 247         err_printf(m, "  ACTHD: 0x%08x\n", ring->acthd);
 248         err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
 249         err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
 250         err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
 251         if (INTEL_INFO(dev)->gen >= 4) {
 252                 err_printf(m, "  BBADDR: 0x%08llx\n", ring->bbaddr);
 253                 err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
 254                 err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
 255         }
 256         err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
 257         err_printf(m, "  FADDR: 0x%08x\n", ring->faddr);
 258         if (INTEL_INFO(dev)->gen >= 6) {
 259                 err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
 260                 err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
 261                 err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 262                            ring->semaphore_mboxes[0],
 263                            ring->semaphore_seqno[0]);
 264                 err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 265                            ring->semaphore_mboxes[1],
 266                            ring->semaphore_seqno[1]);
 267                 if (HAS_VEBOX(dev)) {
 268                         err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 269                                    ring->semaphore_mboxes[2],
 270                                    ring->semaphore_seqno[2]);
 271                 }
 272         }
 273         if (USES_PPGTT(dev)) {
 274                 err_printf(m, "  GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
 275
 276                 if (INTEL_INFO(dev)->gen >= 8) {
 277                         int i;
 278                         for (i = 0; i < 4; i++)
 279                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 280                                            i, ring->vm_info.pdp[i]);
 281                 } else {
 282                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 283                                    ring->vm_info.pp_dir_base);
 284                 }
 285         }
 286         err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
 287         err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
 288         err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
 289         err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
 290         err_printf(m, "  hangcheck: %s [%d]\n",
 291                    hangcheck_action_to_str(ring->hangcheck_action),
 292                    ring->hangcheck_score);
 293 }
 294
 295 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 296 {
 297         va_list args;
 298
 299         va_start(args, f);
 300         i915_error_vprintf(e, f, args);
 301         va_end(args);
 302 }
 303
 304 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 305                             const struct i915_error_state_file_priv *error_priv)
 306 {
 307         struct drm_device *dev = error_priv->dev;
 308         drm_i915_private_t *dev_priv = dev->dev_private;
 309         struct drm_i915_error_state *error = error_priv->error;
 310         int i, j, page, offset, elt;
 311
 312         if (!error) {
 313                 err_printf(m, "no error state collected\n");
 314                 goto out;
 315         }
 316
 317         err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 318                    error->time.tv_usec);
 319         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 320         err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 321         err_printf(m, "EIR: 0x%08x\n", error->eir);
 322         err_printf(m, "IER: 0x%08x\n", error->ier);
 323         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 324         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 325         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 326         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 327         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 328
 329         for (i = 0; i < dev_priv->num_fence_regs; i++)
 330                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 331
 332         for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
 333                 err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
 334                            error->extra_instdone[i]);
 335
 336         if (INTEL_INFO(dev)->gen >= 6) {
 337                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 338                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 339         }
 340
 341         if (INTEL_INFO(dev)->gen == 7)
 342                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 343
 344         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 345                 err_printf(m, "%s command stream:\n", ring_str(i));
 346                 i915_ring_error_state(m, dev, &error->ring[i]);
 347         }
 348
 349         if (error->active_bo)
 350                 print_error_buffers(m, "Active",
 351                                     error->active_bo[0],
 352                                     error->active_bo_count[0]);
 353
 354         if (error->pinned_bo)
 355                 print_error_buffers(m, "Pinned",
 356                                     error->pinned_bo[0],
 357                                     error->pinned_bo_count[0]);
 358
 359         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 360                 struct drm_i915_error_object *obj;
 361
 362                 if ((obj = error->ring[i].batchbuffer)) {
 363                         err_printf(m, "%s --- gtt_offset = 0x%08x\n",
 364                                    dev_priv->ring[i].name,
 365                                    obj->gtt_offset);
 366                         offset = 0;
 367                         for (page = 0; page < obj->page_count; page++) {
 368                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 369                                         err_printf(m, "%08x :  %08x\n", offset,
 370                                                    obj->pages[page][elt]);
 371                                         offset += 4;
 372                                 }
 373                         }
 374                 }
 375
 376                 if (error->ring[i].num_requests) {
 377                         err_printf(m, "%s --- %d requests\n",
 378                                    dev_priv->ring[i].name,
 379                                    error->ring[i].num_requests);
 380                         for (j = 0; j < error->ring[i].num_requests; j++) {
 381                                 err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 382                                            error->ring[i].requests[j].seqno,
 383                                            error->ring[i].requests[j].jiffies,
 384                                            error->ring[i].requests[j].tail);
 385                         }
 386                 }
 387
 388                 if ((obj = error->ring[i].ringbuffer)) {
 389                         err_printf(m, "%s --- ringbuffer = 0x%08x\n",
 390                                    dev_priv->ring[i].name,
 391                                    obj->gtt_offset);
 392                         offset = 0;
 393                         for (page = 0; page < obj->page_count; page++) {
 394                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 395                                         err_printf(m, "%08x :  %08x\n",
 396                                                    offset,
 397                                                    obj->pages[page][elt]);
 398                                         offset += 4;
 399                                 }
 400                         }
 401                 }
 402
 403                 if ((obj = error->ring[i].hws_page)) {
 404                         err_printf(m, "%s --- HW Status = 0x%08x\n",
 405                                    dev_priv->ring[i].name,
 406                                    obj->gtt_offset);
 407                         offset = 0;
 408                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 409                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 410                                            offset,
 411                                            obj->pages[0][elt],
 412                                            obj->pages[0][elt+1],
 413                                            obj->pages[0][elt+2],
 414                                            obj->pages[0][elt+3]);
 415                                         offset += 16;
 416                         }
 417                 }
 418
 419                 if ((obj = error->ring[i].ctx)) {
 420                         err_printf(m, "%s --- HW Context = 0x%08x\n",
 421                                    dev_priv->ring[i].name,
 422                                    obj->gtt_offset);
 423                         offset = 0;
 424                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 425                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 426                                            offset,
 427                                            obj->pages[0][elt],
 428                                            obj->pages[0][elt+1],
 429                                            obj->pages[0][elt+2],
 430                                            obj->pages[0][elt+3]);
 431                                         offset += 16;
 432                         }
 433                 }
 434         }
 435
 436         if (error->overlay)
 437                 intel_overlay_print_error_state(m, error->overlay);
 438
 439         if (error->display)
 440                 intel_display_print_error_state(m, dev, error->display);
 441
 442 out:
 443         if (m->bytes == 0 && m->err)
 444                 return m->err;
 445
 446         return 0;
 447 }
 448
 449 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 450                               size_t count, loff_t pos)
 451 {
 452         memset(ebuf, 0, sizeof(*ebuf));
 453
 454         /* We need to have enough room to store any i915_error_state printf
 455          * so that we can move it to start position.
 456          */
 457         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 458         ebuf->buf = kmalloc(ebuf->size,
 459                                 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
 460
 461         if (ebuf->buf == NULL) {
 462                 ebuf->size = PAGE_SIZE;
 463                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 464         }
 465
 466         if (ebuf->buf == NULL) {
 467                 ebuf->size = 128;
 468                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 469         }
 470
 471         if (ebuf->buf == NULL)
 472                 return -ENOMEM;
 473
 474         ebuf->start = pos;
 475
 476         return 0;
 477 }
 478
 479 static void i915_error_object_free(struct drm_i915_error_object *obj)
 480 {
 481         int page;
 482
 483         if (obj == NULL)
 484                 return;
 485
 486         for (page = 0; page < obj->page_count; page++)
 487                 kfree(obj->pages[page]);
 488
 489         kfree(obj);
 490 }
 491
 492 static void i915_error_state_free(struct kref *error_ref)
 493 {
 494         struct drm_i915_error_state *error = container_of(error_ref,
 495                                                           typeof(*error), ref);
 496         int i;
 497
 498         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 499                 i915_error_object_free(error->ring[i].batchbuffer);
 500                 i915_error_object_free(error->ring[i].ringbuffer);
 501                 i915_error_object_free(error->ring[i].hws_page);
 502                 i915_error_object_free(error->ring[i].ctx);
 503                 kfree(error->ring[i].requests);
 504         }
 505
 506         kfree(error->active_bo);
 507         kfree(error->overlay);
 508         kfree(error->display);
 509         kfree(error);
 510 }
 511
 512 static struct drm_i915_error_object *
 513 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
 514                                struct drm_i915_gem_object *src,
 515                                struct i915_address_space *vm,
 516                                const int num_pages)
 517 {
 518         struct drm_i915_error_object *dst;
 519         int i;
 520         u32 reloc_offset;
 521
 522         if (src == NULL || src->pages == NULL)
 523                 return NULL;
 524
 525         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 526         if (dst == NULL)
 527                 return NULL;
 528
 529         reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
 530         for (i = 0; i < num_pages; i++) {
 531                 unsigned long flags;
 532                 void *d;
 533
 534                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 535                 if (d == NULL)
 536                         goto unwind;
 537
 538                 local_irq_save(flags);
 539                 if (src->cache_level == I915_CACHE_NONE &&
 540                     reloc_offset < dev_priv->gtt.mappable_end &&
 541                     src->has_global_gtt_mapping &&
 542                     i915_is_ggtt(vm)) {
 543                         void __iomem *s;
 544
 545                         /* Simply ignore tiling or any overlapping fence.
 546                          * It's part of the error state, and this hopefully
 547                          * captures what the GPU read.
 548                          */
 549
 550                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 551                                                      reloc_offset);
 552                         memcpy_fromio(d, s, PAGE_SIZE);
 553                         io_mapping_unmap_atomic(s);
 554                 } else if (src->stolen) {
 555                         unsigned long offset;
 556
 557                         offset = dev_priv->mm.stolen_base;
 558                         offset += src->stolen->start;
 559                         offset += i << PAGE_SHIFT;
 560
 561                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
 562                 } else {
 563                         struct page *page;
 564                         void *s;
 565
 566                         page = i915_gem_object_get_page(src, i);
 567
 568                         drm_clflush_pages(&page, 1);
 569
 570                         s = kmap_atomic(page);
 571                         memcpy(d, s, PAGE_SIZE);
 572                         kunmap_atomic(s);
 573
 574                         drm_clflush_pages(&page, 1);
 575                 }
 576                 local_irq_restore(flags);
 577
 578                 dst->pages[i] = d;
 579
 580                 reloc_offset += PAGE_SIZE;
 581         }
 582         dst->page_count = num_pages;
 583
 584         return dst;
 585
 586 unwind:
 587         while (i--)
 588                 kfree(dst->pages[i]);
 589         kfree(dst);
 590         return NULL;
 591 }
 592 #define i915_error_object_create(dev_priv, src, vm) \
 593         i915_error_object_create_sized((dev_priv), (src), (vm), \
 594                                        (src)->base.size>>PAGE_SHIFT)
 595
 596 #define i915_error_ggtt_object_create(dev_priv, src) \
 597         i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
 598                                        (src)->base.size>>PAGE_SHIFT)
 599
 600 static void capture_bo(struct drm_i915_error_buffer *err,
 601                        struct drm_i915_gem_object *obj)
 602 {
 603         err->size = obj->base.size;
 604         err->name = obj->base.name;
 605         err->rseqno = obj->last_read_seqno;
 606         err->wseqno = obj->last_write_seqno;
 607         err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
 608         err->read_domains = obj->base.read_domains;
 609         err->write_domain = obj->base.write_domain;
 610         err->fence_reg = obj->fence_reg;
 611         err->pinned = 0;
 612         if (i915_gem_obj_is_pinned(obj))
 613                 err->pinned = 1;
 614         if (obj->user_pin_count > 0)
 615                 err->pinned = -1;
 616         err->tiling = obj->tiling_mode;
 617         err->dirty = obj->dirty;
 618         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 619         err->ring = obj->ring ? obj->ring->id : -1;
 620         err->cache_level = obj->cache_level;
 621 }
 622
 623 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 624                              int count, struct list_head *head)
 625 {
 626         struct i915_vma *vma;
 627         int i = 0;
 628
 629         list_for_each_entry(vma, head, mm_list) {
 630                 capture_bo(err++, vma->obj);
 631                 if (++i == count)
 632                         break;
 633         }
 634
 635         return i;
 636 }
 637
 638 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 639                              int count, struct list_head *head)
 640 {
 641         struct drm_i915_gem_object *obj;
 642         int i = 0;
 643
 644         list_for_each_entry(obj, head, global_list) {
 645                 if (!i915_gem_obj_is_pinned(obj))
 646                         continue;
 647
 648                 capture_bo(err++, obj);
 649                 if (++i == count)
 650                         break;
 651         }
 652
 653         return i;
 654 }
 655
 656 static void i915_gem_record_fences(struct drm_device *dev,
 657                                    struct drm_i915_error_state *error)
 658 {
 659         struct drm_i915_private *dev_priv = dev->dev_private;
 660         int i;
 661
 662         /* Fences */
 663         switch (INTEL_INFO(dev)->gen) {
 664         case 8:
 665         case 7:
 666         case 6:
 667                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 668                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 669                 break;
 670         case 5:
 671         case 4:
 672                 for (i = 0; i < 16; i++)
 673                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 674                 break;
 675         case 3:
 676                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 677                         for (i = 0; i < 8; i++)
 678                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 679         case 2:
 680                 for (i = 0; i < 8; i++)
 681                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 682                 break;
 683
 684         default:
 685                 BUG();
 686         }
 687 }
 688
 689 /* This assumes all batchbuffers are executed from the PPGTT. It might have to
 690  * change in the future. */
 691 static bool is_active_vm(struct i915_address_space *vm,
 692                          struct intel_ring_buffer *ring)
 693 {
 694         struct drm_device *dev = vm->dev;
 695         struct drm_i915_private *dev_priv = dev->dev_private;
 696         struct i915_hw_ppgtt *ppgtt;
 697
 698         if (INTEL_INFO(dev)->gen < 7)
 699                 return i915_is_ggtt(vm);
 700
 701         /* FIXME: This ignores that the global gtt vm is also on this list. */
 702         ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
 703
 704         if (INTEL_INFO(dev)->gen >= 8) {
 705                 u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32;
 706                 pdp0 |=  I915_READ(GEN8_RING_PDP_LDW(ring, 0));
 707                 return pdp0 == ppgtt->pd_dma_addr[0];
 708         } else {
 709                 u32 pp_db;
 710                 pp_db = I915_READ(RING_PP_DIR_BASE(ring));
 711                 return (pp_db >> 10) == ppgtt->pd_offset;
 712         }
 713 }
 714
 715 static struct drm_i915_error_object *
 716 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 717                              struct intel_ring_buffer *ring)
 718 {
 719         struct i915_address_space *vm;
 720         struct i915_vma *vma;
 721         struct drm_i915_gem_object *obj;
 722         bool found_active = false;
 723         u32 seqno;
 724
 725         if (!ring->get_seqno)
 726                 return NULL;
 727
 728         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
 729                 u32 acthd = I915_READ(ACTHD);
 730
 731                 if (WARN_ON(ring->id != RCS))
 732                         return NULL;
 733
 734                 obj = ring->scratch.obj;
 735                 if (obj != NULL &&
 736                     acthd >= i915_gem_obj_ggtt_offset(obj) &&
 737                     acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
 738                         return i915_error_ggtt_object_create(dev_priv, obj);
 739         }
 740
 741         seqno = ring->get_seqno(ring, false);
 742         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
 743                 if (!is_active_vm(vm, ring))
 744                         continue;
 745
 746                 found_active = true;
 747
 748                 list_for_each_entry(vma, &vm->active_list, mm_list) {
 749                         obj = vma->obj;
 750                         if (obj->ring != ring)
 751                                 continue;
 752
 753                         if (i915_seqno_passed(seqno, obj->last_read_seqno))
 754                                 continue;
 755
 756                         if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 757                                 continue;
 758
 759                         /* We need to copy these to an anonymous buffer as the simplest
 760                          * method to avoid being overwritten by userspace.
 761                          */
 762                         return i915_error_object_create(dev_priv, obj, vm);
 763                 }
 764         }
 765
 766         WARN_ON(!found_active);
 767         return NULL;
 768 }
 769
 770 static void i915_record_ring_state(struct drm_device *dev,
 771                                    struct intel_ring_buffer *ring,
 772                                    struct drm_i915_error_ring *ering)
 773 {
 774         struct drm_i915_private *dev_priv = dev->dev_private;
 775
 776         if (INTEL_INFO(dev)->gen >= 6) {
 777                 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
 778                 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 779                 ering->semaphore_mboxes[0]
 780                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 781                 ering->semaphore_mboxes[1]
 782                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 783                 ering->semaphore_seqno[0] = ring->sync_seqno[0];
 784                 ering->semaphore_seqno[1] = ring->sync_seqno[1];
 785         }
 786
 787         if (HAS_VEBOX(dev)) {
 788                 ering->semaphore_mboxes[2] =
 789                         I915_READ(RING_SYNC_2(ring->mmio_base));
 790                 ering->semaphore_seqno[2] = ring->sync_seqno[2];
 791         }
 792
 793         if (INTEL_INFO(dev)->gen >= 4) {
 794                 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
 795                 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
 796                 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
 797                 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
 798                 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
 799                 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
 800                 if (INTEL_INFO(dev)->gen >= 8)
 801                         ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
 802                 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
 803         } else {
 804                 ering->faddr = I915_READ(DMA_FADD_I8XX);
 805                 ering->ipeir = I915_READ(IPEIR);
 806                 ering->ipehr = I915_READ(IPEHR);
 807                 ering->instdone = I915_READ(INSTDONE);
 808         }
 809
 810         ering->waiting = waitqueue_active(&ring->irq_queue);
 811         ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
 812         ering->seqno = ring->get_seqno(ring, false);
 813         ering->acthd = intel_ring_get_active_head(ring);
 814         ering->head = I915_READ_HEAD(ring);
 815         ering->tail = I915_READ_TAIL(ring);
 816         ering->ctl = I915_READ_CTL(ring);
 817
 818         if (I915_NEED_GFX_HWS(dev)) {
 819                 int mmio;
 820
 821                 if (IS_GEN7(dev)) {
 822                         switch (ring->id) {
 823                         default:
 824                         case RCS:
 825                                 mmio = RENDER_HWS_PGA_GEN7;
 826                                 break;
 827                         case BCS:
 828                                 mmio = BLT_HWS_PGA_GEN7;
 829                                 break;
 830                         case VCS:
 831                                 mmio = BSD_HWS_PGA_GEN7;
 832                                 break;
 833                         case VECS:
 834                                 mmio = VEBOX_HWS_PGA_GEN7;
 835                                 break;
 836                         }
 837                 } else if (IS_GEN6(ring->dev)) {
 838                         mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 839                 } else {
 840                         /* XXX: gen8 returns to sanity */
 841                         mmio = RING_HWS_PGA(ring->mmio_base);
 842                 }
 843
 844                 ering->hws = I915_READ(mmio);
 845         }
 846
 847         ering->cpu_ring_head = ring->head;
 848         ering->cpu_ring_tail = ring->tail;
 849
 850         ering->hangcheck_score = ring->hangcheck.score;
 851         ering->hangcheck_action = ring->hangcheck.action;
 852
 853         if (USES_PPGTT(dev)) {
 854                 int i;
 855
 856                 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
 857
 858                 switch (INTEL_INFO(dev)->gen) {
 859                 case 8:
 860                         for (i = 0; i < 4; i++) {
 861                                 ering->vm_info.pdp[i] =
 862                                         I915_READ(GEN8_RING_PDP_UDW(ring, i));
 863                                 ering->vm_info.pdp[i] <<= 32;
 864                                 ering->vm_info.pdp[i] |=
 865                                         I915_READ(GEN8_RING_PDP_LDW(ring, i));
 866                         }
 867                         break;
 868                 case 7:
 869                         ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring);
 870                         break;
 871                 case 6:
 872                         ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring);
 873                         break;
 874                 }
 875         }
 876 }
 877
 878
 879 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
 880                                            struct drm_i915_error_state *error,
 881                                            struct drm_i915_error_ring *ering)
 882 {
 883         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 884         struct drm_i915_gem_object *obj;
 885
 886         /* Currently render ring is the only HW context user */
 887         if (ring->id != RCS || !error->ccid)
 888                 return;
 889
 890         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 891                 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
 892                         ering->ctx = i915_error_object_create_sized(dev_priv,
 893                                                                     obj,
 894                                                                     &dev_priv->gtt.base,
 895                                                                     1);
 896                         break;
 897                 }
 898         }
 899 }
 900
 901 static void i915_gem_record_rings(struct drm_device *dev,
 902                                   struct drm_i915_error_state *error)
 903 {
 904         struct drm_i915_private *dev_priv = dev->dev_private;
 905         struct drm_i915_gem_request *request;
 906         int i, count;
 907
 908         for (i = 0; i < I915_NUM_RINGS; i++) {
 909                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
 910
 911                 if (ring->dev == NULL)
 912                         continue;
 913
 914                 error->ring[i].valid = true;
 915
 916                 i915_record_ring_state(dev, ring, &error->ring[i]);
 917
 918                 error->ring[i].batchbuffer =
 919                         i915_error_first_batchbuffer(dev_priv, ring);
 920
 921                 error->ring[i].ringbuffer =
 922                         i915_error_ggtt_object_create(dev_priv, ring->obj);
 923
 924                 if (ring->status_page.obj)
 925                         error->ring[i].hws_page =
 926                                 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
 927
 928                 i915_gem_record_active_context(ring, error, &error->ring[i]);
 929
 930                 count = 0;
 931                 list_for_each_entry(request, &ring->request_list, list)
 932                         count++;
 933
 934                 error->ring[i].num_requests = count;
 935                 error->ring[i].requests =
 936                         kcalloc(count, sizeof(*error->ring[i].requests),
 937                                 GFP_ATOMIC);
 938                 if (error->ring[i].requests == NULL) {
 939                         error->ring[i].num_requests = 0;
 940                         continue;
 941                 }
 942
 943                 count = 0;
 944                 list_for_each_entry(request, &ring->request_list, list) {
 945                         struct drm_i915_error_request *erq;
 946
 947                         erq = &error->ring[i].requests[count++];
 948                         erq->seqno = request->seqno;
 949                         erq->jiffies = request->emitted_jiffies;
 950                         erq->tail = request->tail;
 951                 }
 952         }
 953 }
 954
 955 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
 956  * VM.
 957  */
 958 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
 959                                 struct drm_i915_error_state *error,
 960                                 struct i915_address_space *vm,
 961                                 const int ndx)
 962 {
 963         struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
 964         struct drm_i915_gem_object *obj;
 965         struct i915_vma *vma;
 966         int i;
 967
 968         i = 0;
 969         list_for_each_entry(vma, &vm->active_list, mm_list)
 970                 i++;
 971         error->active_bo_count[ndx] = i;
 972         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 973                 if (i915_gem_obj_is_pinned(obj))
 974                         i++;
 975         error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
 976
 977         if (i) {
 978                 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
 979                 if (active_bo)
 980                         pinned_bo = active_bo + error->active_bo_count[ndx];
 981         }
 982
 983         if (active_bo)
 984                 error->active_bo_count[ndx] =
 985                         capture_active_bo(active_bo,
 986                                           error->active_bo_count[ndx],
 987                                           &vm->active_list);
 988
 989         if (pinned_bo)
 990                 error->pinned_bo_count[ndx] =
 991                         capture_pinned_bo(pinned_bo,
 992                                           error->pinned_bo_count[ndx],
 993                                           &dev_priv->mm.bound_list);
 994         error->active_bo[ndx] = active_bo;
 995         error->pinned_bo[ndx] = pinned_bo;
 996 }
 997
 998 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
 999                                      struct drm_i915_error_state *error)
1000 {
1001         struct i915_address_space *vm;
1002         int cnt = 0, i = 0;
1003
1004         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1005                 cnt++;
1006
1007         error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1008         error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1009         error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1010                                          GFP_ATOMIC);
1011         error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1012                                          GFP_ATOMIC);
1013
1014         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1015                 i915_gem_capture_vm(dev_priv, error, vm, i++);
1016 }
1017
1018 /* Capture all registers which don't fit into another category. */
1019 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1020                                    struct drm_i915_error_state *error)
1021 {
1022         struct drm_device *dev = dev_priv->dev;
1023         int pipe;
1024
1025         /* General organization
1026          * 1. Registers specific to a single generation
1027          * 2. Registers which belong to multiple generations
1028          * 3. Feature specific registers.
1029          * 4. Everything else
1030          * Please try to follow the order.
1031          */
1032
1033         /* 1: Registers specific to a single generation */
1034         if (IS_VALLEYVIEW(dev)) {
1035                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1036                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1037         }
1038
1039         if (IS_GEN7(dev))
1040                 error->err_int = I915_READ(GEN7_ERR_INT);
1041
1042         if (IS_GEN6(dev)) {
1043                 error->forcewake = I915_READ(FORCEWAKE);
1044                 error->gab_ctl = I915_READ(GAB_CTL);
1045                 error->gfx_mode = I915_READ(GFX_MODE);
1046         }
1047
1048         if (IS_GEN2(dev))
1049                 error->ier = I915_READ16(IER);
1050
1051         /* 2: Registers which belong to multiple generations */
1052         if (INTEL_INFO(dev)->gen >= 7)
1053                 error->forcewake = I915_READ(FORCEWAKE_MT);
1054
1055         if (INTEL_INFO(dev)->gen >= 6) {
1056                 error->derrmr = I915_READ(DERRMR);
1057                 error->error = I915_READ(ERROR_GEN6);
1058                 error->done_reg = I915_READ(DONE_REG);
1059         }
1060
1061         /* 3: Feature specific registers */
1062         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1063                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1064                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1065         }
1066
1067         /* 4: Everything else */
1068         if (HAS_HW_CONTEXTS(dev))
1069                 error->ccid = I915_READ(CCID);
1070
1071         if (HAS_PCH_SPLIT(dev))
1072                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1073         else {
1074                 error->ier = I915_READ(IER);
1075                 for_each_pipe(pipe)
1076                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1077         }
1078
1079         /* 4: Everything else */
1080         error->eir = I915_READ(EIR);
1081         error->pgtbl_er = I915_READ(PGTBL_ER);
1082
1083         i915_get_extra_instdone(dev, error->extra_instdone);
1084 }
1085
1086 /**
1087  * i915_capture_error_state - capture an error record for later analysis
1088  * @dev: drm device
1089  *
1090  * Should be called when an error is detected (either a hang or an error
1091  * interrupt) to capture error state from the time of the error.  Fills
1092  * out a structure which becomes available in debugfs for user level tools
1093  * to pick up.
1094  */
1095 void i915_capture_error_state(struct drm_device *dev)
1096 {
1097         static bool warned;
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         struct drm_i915_error_state *error;
1100         unsigned long flags;
1101
1102         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1103         error = dev_priv->gpu_error.first_error;
1104         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1105         if (error)
1106                 return;
1107
1108         /* Account for pipe specific data like PIPE*STAT */
1109         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1110         if (!error) {
1111                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1112                 return;
1113         }
1114
1115         DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1116                  dev->primary->index);
1117         if (!warned) {
1118                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1119                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1120                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1121                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1122                 warned = true;
1123         }
1124
1125         kref_init(&error->ref);
1126
1127         i915_capture_reg_state(dev_priv, error);
1128         i915_gem_capture_buffers(dev_priv, error);
1129         i915_gem_record_fences(dev, error);
1130         i915_gem_record_rings(dev, error);
1131
1132         do_gettimeofday(&error->time);
1133
1134         error->overlay = intel_overlay_capture_error_state(dev);
1135         error->display = intel_display_capture_error_state(dev);
1136
1137         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1138         if (dev_priv->gpu_error.first_error == NULL) {
1139                 dev_priv->gpu_error.first_error = error;
1140                 error = NULL;
1141         }
1142         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1143
1144         if (error)
1145                 i915_error_state_free(&error->ref);
1146 }
1147
1148 void i915_error_state_get(struct drm_device *dev,
1149                           struct i915_error_state_file_priv *error_priv)
1150 {
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         unsigned long flags;
1153
1154         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1155         error_priv->error = dev_priv->gpu_error.first_error;
1156         if (error_priv->error)
1157                 kref_get(&error_priv->error->ref);
1158         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1159
1160 }
1161
1162 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1163 {
1164         if (error_priv->error)
1165                 kref_put(&error_priv->error->ref, i915_error_state_free);
1166 }
1167
1168 void i915_destroy_error_state(struct drm_device *dev)
1169 {
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct drm_i915_error_state *error;
1172         unsigned long flags;
1173
1174         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1175         error = dev_priv->gpu_error.first_error;
1176         dev_priv->gpu_error.first_error = NULL;
1177         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1178
1179         if (error)
1180                 kref_put(&error->ref, i915_error_state_free);
1181 }
1182
1183 const char *i915_cache_level_str(int type)
1184 {
1185         switch (type) {
1186         case I915_CACHE_NONE: return " uncached";
1187         case I915_CACHE_LLC: return " snooped or LLC";
1188         case I915_CACHE_L3_LLC: return " L3+LLC";
1189         case I915_CACHE_WT: return " WT";
1190         default: return "";
1191         }
1192 }
1193
1194 /* NB: please notice the memset */
1195 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1196 {
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1199
1200         switch (INTEL_INFO(dev)->gen) {
1201         case 2:
1202         case 3:
1203                 instdone[0] = I915_READ(INSTDONE);
1204                 break;
1205         case 4:
1206         case 5:
1207         case 6:
1208                 instdone[0] = I915_READ(INSTDONE_I965);
1209                 instdone[1] = I915_READ(INSTDONE1);
1210                 break;
1211         default:
1212                 WARN_ONCE(1, "Unsupported platform\n");
1213         case 7:
1214         case 8:
1215                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1216                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1217                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1218                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1219                 break;
1220         }
1221 }