drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include <linux/stop_machine.h>
  32 #include <linux/zlib.h>
  33 #include "i915_drv.h"
  34
  35 static const char *engine_str(int engine)
  36 {
  37         switch (engine) {
  38         case RCS: return "render";
  39         case VCS: return "bsd";
  40         case BCS: return "blt";
  41         case VECS: return "vebox";
  42         case VCS2: return "bsd2";
  43         default: return "";
  44         }
  45 }
  46
  47 static const char *tiling_flag(int tiling)
  48 {
  49         switch (tiling) {
  50         default:
  51         case I915_TILING_NONE: return "";
  52         case I915_TILING_X: return " X";
  53         case I915_TILING_Y: return " Y";
  54         }
  55 }
  56
  57 static const char *dirty_flag(int dirty)
  58 {
  59         return dirty ? " dirty" : "";
  60 }
  61
  62 static const char *purgeable_flag(int purgeable)
  63 {
  64         return purgeable ? " purgeable" : "";
  65 }
  66
  67 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  68 {
  69
  70         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  71                 e->err = -ENOSPC;
  72                 return false;
  73         }
  74
  75         if (e->bytes == e->size - 1 || e->err)
  76                 return false;
  77
  78         return true;
  79 }
  80
  81 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  82                               unsigned len)
  83 {
  84         if (e->pos + len <= e->start) {
  85                 e->pos += len;
  86                 return false;
  87         }
  88
  89         /* First vsnprintf needs to fit in its entirety for memmove */
  90         if (len >= e->size) {
  91                 e->err = -EIO;
  92                 return false;
  93         }
  94
  95         return true;
  96 }
  97
  98 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
  99                                  unsigned len)
 100 {
 101         /* If this is first printf in this window, adjust it so that
 102          * start position matches start of the buffer
 103          */
 104
 105         if (e->pos < e->start) {
 106                 const size_t off = e->start - e->pos;
 107
 108                 /* Should not happen but be paranoid */
 109                 if (off > len || e->bytes) {
 110                         e->err = -EIO;
 111                         return;
 112                 }
 113
 114                 memmove(e->buf, e->buf + off, len - off);
 115                 e->bytes = len - off;
 116                 e->pos = e->start;
 117                 return;
 118         }
 119
 120         e->bytes += len;
 121         e->pos += len;
 122 }
 123
 124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 125                                const char *f, va_list args)
 126 {
 127         unsigned len;
 128
 129         if (!__i915_error_ok(e))
 130                 return;
 131
 132         /* Seek the first printf which is hits start position */
 133         if (e->pos < e->start) {
 134                 va_list tmp;
 135
 136                 va_copy(tmp, args);
 137                 len = vsnprintf(NULL, 0, f, tmp);
 138                 va_end(tmp);
 139
 140                 if (!__i915_error_seek(e, len))
 141                         return;
 142         }
 143
 144         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 145         if (len >= e->size - e->bytes)
 146                 len = e->size - e->bytes - 1;
 147
 148         __i915_error_advance(e, len);
 149 }
 150
 151 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 152                             const char *str)
 153 {
 154         unsigned len;
 155
 156         if (!__i915_error_ok(e))
 157                 return;
 158
 159         len = strlen(str);
 160
 161         /* Seek the first printf which is hits start position */
 162         if (e->pos < e->start) {
 163                 if (!__i915_error_seek(e, len))
 164                         return;
 165         }
 166
 167         if (len >= e->size - e->bytes)
 168                 len = e->size - e->bytes - 1;
 169         memcpy(e->buf + e->bytes, str, len);
 170
 171         __i915_error_advance(e, len);
 172 }
 173
 174 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 175 #define err_puts(e, s) i915_error_puts(e, s)
 176
 177 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 178
 179 static bool compress_init(struct z_stream_s *zstream)
 180 {
 181         memset(zstream, 0, sizeof(*zstream));
 182
 183         zstream->workspace =
 184                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 185                         GFP_ATOMIC | __GFP_NOWARN);
 186         if (!zstream->workspace)
 187                 return false;
 188
 189         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 190                 kfree(zstream->workspace);
 191                 return false;
 192         }
 193
 194         return true;
 195 }
 196
 197 static int compress_page(struct z_stream_s *zstream,
 198                          void *src,
 199                          struct drm_i915_error_object *dst)
 200 {
 201         zstream->next_in = src;
 202         zstream->avail_in = PAGE_SIZE;
 203
 204         do {
 205                 if (zstream->avail_out == 0) {
 206                         unsigned long page;
 207
 208                         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 209                         if (!page)
 210                                 return -ENOMEM;
 211
 212                         dst->pages[dst->page_count++] = (void *)page;
 213
 214                         zstream->next_out = (void *)page;
 215                         zstream->avail_out = PAGE_SIZE;
 216                 }
 217
 218                 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
 219                         return -EIO;
 220         } while (zstream->avail_in);
 221
 222         /* Fallback to uncompressed if we increase size? */
 223         if (0 && zstream->total_out > zstream->total_in)
 224                 return -E2BIG;
 225
 226         return 0;
 227 }
 228
 229 static void compress_fini(struct z_stream_s *zstream,
 230                           struct drm_i915_error_object *dst)
 231 {
 232         if (dst) {
 233                 zlib_deflate(zstream, Z_FINISH);
 234                 dst->unused = zstream->avail_out;
 235         }
 236
 237         zlib_deflateEnd(zstream);
 238         kfree(zstream->workspace);
 239 }
 240
 241 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 242 {
 243         err_puts(m, ":");
 244 }
 245
 246 #else
 247
 248 static bool compress_init(struct z_stream_s *zstream)
 249 {
 250         return true;
 251 }
 252
 253 static int compress_page(struct z_stream_s *zstream,
 254                          void *src,
 255                          struct drm_i915_error_object *dst)
 256 {
 257         unsigned long page;
 258
 259         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 260         if (!page)
 261                 return -ENOMEM;
 262
 263         dst->pages[dst->page_count++] =
 264                 memcpy((void *)page, src, PAGE_SIZE);
 265
 266         return 0;
 267 }
 268
 269 static void compress_fini(struct z_stream_s *zstream,
 270                           struct drm_i915_error_object *dst)
 271 {
 272 }
 273
 274 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 275 {
 276         err_puts(m, "~");
 277 }
 278
 279 #endif
 280
 281 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 282                                 const char *name,
 283                                 struct drm_i915_error_buffer *err,
 284                                 int count)
 285 {
 286         int i;
 287
 288         err_printf(m, "%s [%d]:\n", name, count);
 289
 290         while (count--) {
 291                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 292                            upper_32_bits(err->gtt_offset),
 293                            lower_32_bits(err->gtt_offset),
 294                            err->size,
 295                            err->read_domains,
 296                            err->write_domain);
 297                 for (i = 0; i < I915_NUM_ENGINES; i++)
 298                         err_printf(m, "%02x ", err->rseqno[i]);
 299
 300                 err_printf(m, "] %02x", err->wseqno);
 301                 err_puts(m, tiling_flag(err->tiling));
 302                 err_puts(m, dirty_flag(err->dirty));
 303                 err_puts(m, purgeable_flag(err->purgeable));
 304                 err_puts(m, err->userptr ? " userptr" : "");
 305                 err_puts(m, err->engine != -1 ? " " : "");
 306                 err_puts(m, engine_str(err->engine));
 307                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 308
 309                 if (err->name)
 310                         err_printf(m, " (name: %d)", err->name);
 311                 if (err->fence_reg != I915_FENCE_REG_NONE)
 312                         err_printf(m, " (fence: %d)", err->fence_reg);
 313
 314                 err_puts(m, "\n");
 315                 err++;
 316         }
 317 }
 318
 319 static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
 320 {
 321         switch (a) {
 322         case HANGCHECK_IDLE:
 323                 return "idle";
 324         case HANGCHECK_WAIT:
 325                 return "wait";
 326         case HANGCHECK_ACTIVE:
 327                 return "active";
 328         case HANGCHECK_KICK:
 329                 return "kick";
 330         case HANGCHECK_HUNG:
 331                 return "hung";
 332         }
 333
 334         return "unknown";
 335 }
 336
 337 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 338                                  struct drm_i915_error_engine *ee)
 339 {
 340         int slice;
 341         int subslice;
 342
 343         err_printf(m, "  INSTDONE: 0x%08x\n",
 344                    ee->instdone.instdone);
 345
 346         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 347                 return;
 348
 349         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 350                    ee->instdone.slice_common);
 351
 352         if (INTEL_GEN(m->i915) <= 6)
 353                 return;
 354
 355         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 356                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 357                            slice, subslice,
 358                            ee->instdone.sampler[slice][subslice]);
 359
 360         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 361                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 362                            slice, subslice,
 363                            ee->instdone.row[slice][subslice]);
 364 }
 365
 366 static void error_print_request(struct drm_i915_error_state_buf *m,
 367                                 const char *prefix,
 368                                 struct drm_i915_error_request *erq)
 369 {
 370         if (!erq->seqno)
 371                 return;
 372
 373         err_printf(m, "%s pid %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
 374                    prefix, erq->pid,
 375                    erq->context, erq->seqno,
 376                    jiffies_to_msecs(jiffies - erq->jiffies),
 377                    erq->head, erq->tail);
 378 }
 379
 380 static void error_print_engine(struct drm_i915_error_state_buf *m,
 381                                struct drm_i915_error_engine *ee)
 382 {
 383         err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
 384         err_printf(m, "  START: 0x%08x\n", ee->start);
 385         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 386         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 387                    ee->tail, ee->rq_post, ee->rq_tail);
 388         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 389         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 390         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 391         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 392                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 393         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 394         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 395
 396         error_print_instdone(m, ee);
 397
 398         if (ee->batchbuffer) {
 399                 u64 start = ee->batchbuffer->gtt_offset;
 400                 u64 end = start + ee->batchbuffer->gtt_size;
 401
 402                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 403                            upper_32_bits(start), lower_32_bits(start),
 404                            upper_32_bits(end), lower_32_bits(end));
 405         }
 406         if (INTEL_GEN(m->i915) >= 4) {
 407                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 408                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 409                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 410                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 411         }
 412         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 413         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 414                    lower_32_bits(ee->faddr));
 415         if (INTEL_GEN(m->i915) >= 6) {
 416                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 417                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 418                 err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 419                            ee->semaphore_mboxes[0],
 420                            ee->semaphore_seqno[0]);
 421                 err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 422                            ee->semaphore_mboxes[1],
 423                            ee->semaphore_seqno[1]);
 424                 if (HAS_VEBOX(m->i915)) {
 425                         err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 426                                    ee->semaphore_mboxes[2],
 427                                    ee->semaphore_seqno[2]);
 428                 }
 429         }
 430         if (USES_PPGTT(m->i915)) {
 431                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 432
 433                 if (INTEL_GEN(m->i915) >= 8) {
 434                         int i;
 435                         for (i = 0; i < 4; i++)
 436                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 437                                            i, ee->vm_info.pdp[i]);
 438                 } else {
 439                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 440                                    ee->vm_info.pp_dir_base);
 441                 }
 442         }
 443         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 444         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 445         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 446         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 447         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 448         err_printf(m, "  hangcheck: %s [%d]\n",
 449                    hangcheck_action_to_str(ee->hangcheck_action),
 450                    ee->hangcheck_score);
 451         error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
 452         error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
 453 }
 454
 455 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 456 {
 457         va_list args;
 458
 459         va_start(args, f);
 460         i915_error_vprintf(e, f, args);
 461         va_end(args);
 462 }
 463
 464 static int
 465 ascii85_encode_len(int len)
 466 {
 467         return DIV_ROUND_UP(len, 4);
 468 }
 469
 470 static bool
 471 ascii85_encode(u32 in, char *out)
 472 {
 473         int i;
 474
 475         if (in == 0)
 476                 return false;
 477
 478         out[5] = '\0';
 479         for (i = 5; i--; ) {
 480                 out[i] = '!' + in % 85;
 481                 in /= 85;
 482         }
 483
 484         return true;
 485 }
 486
 487 static void print_error_obj(struct drm_i915_error_state_buf *m,
 488                             struct intel_engine_cs *engine,
 489                             const char *name,
 490                             struct drm_i915_error_object *obj)
 491 {
 492         char out[6];
 493         int page;
 494
 495         if (!obj)
 496                 return;
 497
 498         if (name) {
 499                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 500                            engine ? engine->name : "global", name,
 501                            upper_32_bits(obj->gtt_offset),
 502                            lower_32_bits(obj->gtt_offset));
 503         }
 504
 505         err_compression_marker(m);
 506         for (page = 0; page < obj->page_count; page++) {
 507                 int i, len;
 508
 509                 len = PAGE_SIZE;
 510                 if (page == obj->page_count - 1)
 511                         len -= obj->unused;
 512                 len = ascii85_encode_len(len);
 513
 514                 for (i = 0; i < len; i++) {
 515                         if (ascii85_encode(obj->pages[page][i], out))
 516                                 err_puts(m, out);
 517                         else
 518                                 err_puts(m, "z");
 519                 }
 520         }
 521         err_puts(m, "\n");
 522 }
 523
 524 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 525                                    const struct intel_device_info *info)
 526 {
 527 #define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
 528         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 529 #undef PRINT_FLAG
 530 }
 531
 532 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 533                             const struct i915_error_state_file_priv *error_priv)
 534 {
 535         struct drm_device *dev = error_priv->dev;
 536         struct drm_i915_private *dev_priv = to_i915(dev);
 537         struct pci_dev *pdev = dev_priv->drm.pdev;
 538         struct drm_i915_error_state *error = error_priv->error;
 539         struct drm_i915_error_object *obj;
 540         int max_hangcheck_score;
 541         int i, j;
 542
 543         if (!error) {
 544                 err_printf(m, "no error state collected\n");
 545                 goto out;
 546         }
 547
 548         err_printf(m, "%s\n", error->error_msg);
 549         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 550         err_printf(m, "Time: %ld s %ld us\n",
 551                    error->time.tv_sec, error->time.tv_usec);
 552         err_printf(m, "Boottime: %ld s %ld us\n",
 553                    error->boottime.tv_sec, error->boottime.tv_usec);
 554         err_printf(m, "Uptime: %ld s %ld us\n",
 555                    error->uptime.tv_sec, error->uptime.tv_usec);
 556         err_print_capabilities(m, &error->device_info);
 557         max_hangcheck_score = 0;
 558         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 559                 if (error->engine[i].hangcheck_score > max_hangcheck_score)
 560                         max_hangcheck_score = error->engine[i].hangcheck_score;
 561         }
 562         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 563                 if (error->engine[i].hangcheck_score == max_hangcheck_score &&
 564                     error->engine[i].pid != -1) {
 565                         err_printf(m, "Active process (on ring %s): %s [%d]\n",
 566                                    engine_str(i),
 567                                    error->engine[i].comm,
 568                                    error->engine[i].pid);
 569                 }
 570         }
 571         err_printf(m, "Reset count: %u\n", error->reset_count);
 572         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 573         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 574         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 575         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 576                    pdev->subsystem_vendor,
 577                    pdev->subsystem_device);
 578         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 579
 580         if (HAS_CSR(dev)) {
 581                 struct intel_csr *csr = &dev_priv->csr;
 582
 583                 err_printf(m, "DMC loaded: %s\n",
 584                            yesno(csr->dmc_payload != NULL));
 585                 err_printf(m, "DMC fw version: %d.%d\n",
 586                            CSR_VERSION_MAJOR(csr->version),
 587                            CSR_VERSION_MINOR(csr->version));
 588         }
 589
 590         err_printf(m, "EIR: 0x%08x\n", error->eir);
 591         err_printf(m, "IER: 0x%08x\n", error->ier);
 592         if (INTEL_INFO(dev)->gen >= 8) {
 593                 for (i = 0; i < 4; i++)
 594                         err_printf(m, "GTIER gt %d: 0x%08x\n", i,
 595                                    error->gtier[i]);
 596         } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
 597                 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
 598         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 599         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 600         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 601         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 602         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 603
 604         for (i = 0; i < dev_priv->num_fence_regs; i++)
 605                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 606
 607         if (INTEL_INFO(dev)->gen >= 6) {
 608                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 609
 610                 if (INTEL_INFO(dev)->gen >= 8)
 611                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 612                                    error->fault_data1, error->fault_data0);
 613
 614                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 615         }
 616
 617         if (IS_GEN7(dev_priv))
 618                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 619
 620         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 621                 if (error->engine[i].engine_id != -1)
 622                         error_print_engine(m, &error->engine[i]);
 623         }
 624
 625         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 626                 char buf[128];
 627                 int len, first = 1;
 628
 629                 if (!error->active_vm[i])
 630                         break;
 631
 632                 len = scnprintf(buf, sizeof(buf), "Active (");
 633                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 634                         if (error->engine[j].vm != error->active_vm[i])
 635                                 continue;
 636
 637                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 638                                          first ? "" : ", ",
 639                                          dev_priv->engine[j]->name);
 640                         first = 0;
 641                 }
 642                 scnprintf(buf + len, sizeof(buf), ")");
 643                 print_error_buffers(m, buf,
 644                                     error->active_bo[i],
 645                                     error->active_bo_count[i]);
 646         }
 647
 648         print_error_buffers(m, "Pinned (global)",
 649                             error->pinned_bo,
 650                             error->pinned_bo_count);
 651
 652         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 653                 struct drm_i915_error_engine *ee = &error->engine[i];
 654
 655                 obj = ee->batchbuffer;
 656                 if (obj) {
 657                         err_puts(m, dev_priv->engine[i]->name);
 658                         if (ee->pid != -1)
 659                                 err_printf(m, " (submitted by %s [%d])",
 660                                            ee->comm,
 661                                            ee->pid);
 662                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 663                                    upper_32_bits(obj->gtt_offset),
 664                                    lower_32_bits(obj->gtt_offset));
 665                         print_error_obj(m, dev_priv->engine[i], NULL, obj);
 666                 }
 667
 668                 if (ee->num_requests) {
 669                         err_printf(m, "%s --- %d requests\n",
 670                                    dev_priv->engine[i]->name,
 671                                    ee->num_requests);
 672                         for (j = 0; j < ee->num_requests; j++)
 673                                 error_print_request(m, " ", &ee->requests[j]);
 674                 }
 675
 676                 if (IS_ERR(ee->waiters)) {
 677                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 678                                    dev_priv->engine[i]->name);
 679                 } else if (ee->num_waiters) {
 680                         err_printf(m, "%s --- %d waiters\n",
 681                                    dev_priv->engine[i]->name,
 682                                    ee->num_waiters);
 683                         for (j = 0; j < ee->num_waiters; j++) {
 684                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 685                                            ee->waiters[j].seqno,
 686                                            ee->waiters[j].comm,
 687                                            ee->waiters[j].pid);
 688                         }
 689                 }
 690
 691                 print_error_obj(m, dev_priv->engine[i],
 692                                 "ringbuffer", ee->ringbuffer);
 693
 694                 print_error_obj(m, dev_priv->engine[i],
 695                                 "HW Status", ee->hws_page);
 696
 697                 print_error_obj(m, dev_priv->engine[i],
 698                                 "HW context", ee->ctx);
 699
 700                 print_error_obj(m, dev_priv->engine[i],
 701                                 "WA context", ee->wa_ctx);
 702
 703                 print_error_obj(m, dev_priv->engine[i],
 704                                 "WA batchbuffer", ee->wa_batchbuffer);
 705         }
 706
 707         print_error_obj(m, NULL, "Semaphores", error->semaphore);
 708
 709         print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
 710
 711         if (error->overlay)
 712                 intel_overlay_print_error_state(m, error->overlay);
 713
 714         if (error->display)
 715                 intel_display_print_error_state(m, dev, error->display);
 716
 717 out:
 718         if (m->bytes == 0 && m->err)
 719                 return m->err;
 720
 721         return 0;
 722 }
 723
 724 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 725                               struct drm_i915_private *i915,
 726                               size_t count, loff_t pos)
 727 {
 728         memset(ebuf, 0, sizeof(*ebuf));
 729         ebuf->i915 = i915;
 730
 731         /* We need to have enough room to store any i915_error_state printf
 732          * so that we can move it to start position.
 733          */
 734         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 735         ebuf->buf = kmalloc(ebuf->size,
 736                                 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
 737
 738         if (ebuf->buf == NULL) {
 739                 ebuf->size = PAGE_SIZE;
 740                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 741         }
 742
 743         if (ebuf->buf == NULL) {
 744                 ebuf->size = 128;
 745                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 746         }
 747
 748         if (ebuf->buf == NULL)
 749                 return -ENOMEM;
 750
 751         ebuf->start = pos;
 752
 753         return 0;
 754 }
 755
 756 static void i915_error_object_free(struct drm_i915_error_object *obj)
 757 {
 758         int page;
 759
 760         if (obj == NULL)
 761                 return;
 762
 763         for (page = 0; page < obj->page_count; page++)
 764                 free_page((unsigned long)obj->pages[page]);
 765
 766         kfree(obj);
 767 }
 768
 769 static void i915_error_state_free(struct kref *error_ref)
 770 {
 771         struct drm_i915_error_state *error = container_of(error_ref,
 772                                                           typeof(*error), ref);
 773         int i;
 774
 775         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 776                 struct drm_i915_error_engine *ee = &error->engine[i];
 777
 778                 i915_error_object_free(ee->batchbuffer);
 779                 i915_error_object_free(ee->wa_batchbuffer);
 780                 i915_error_object_free(ee->ringbuffer);
 781                 i915_error_object_free(ee->hws_page);
 782                 i915_error_object_free(ee->ctx);
 783                 i915_error_object_free(ee->wa_ctx);
 784
 785                 kfree(ee->requests);
 786                 if (!IS_ERR_OR_NULL(ee->waiters))
 787                         kfree(ee->waiters);
 788         }
 789
 790         i915_error_object_free(error->semaphore);
 791         i915_error_object_free(error->guc_log);
 792
 793         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
 794                 kfree(error->active_bo[i]);
 795         kfree(error->pinned_bo);
 796
 797         kfree(error->overlay);
 798         kfree(error->display);
 799         kfree(error);
 800 }
 801
 802 static struct drm_i915_error_object *
 803 i915_error_object_create(struct drm_i915_private *i915,
 804                          struct i915_vma *vma)
 805 {
 806         struct i915_ggtt *ggtt = &i915->ggtt;
 807         const u64 slot = ggtt->error_capture.start;
 808         struct drm_i915_error_object *dst;
 809         struct z_stream_s zstream;
 810         unsigned long num_pages;
 811         struct sgt_iter iter;
 812         dma_addr_t dma;
 813
 814         if (!vma)
 815                 return NULL;
 816
 817         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 818         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 819         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
 820                       GFP_ATOMIC | __GFP_NOWARN);
 821         if (!dst)
 822                 return NULL;
 823
 824         dst->gtt_offset = vma->node.start;
 825         dst->gtt_size = vma->node.size;
 826         dst->page_count = 0;
 827         dst->unused = 0;
 828
 829         if (!compress_init(&zstream)) {
 830                 kfree(dst);
 831                 return NULL;
 832         }
 833
 834         for_each_sgt_dma(dma, iter, vma->pages) {
 835                 void __iomem *s;
 836                 int ret;
 837
 838                 ggtt->base.insert_page(&ggtt->base, dma, slot,
 839                                        I915_CACHE_NONE, 0);
 840
 841                 s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
 842                 ret = compress_page(&zstream, (void  __force *)s, dst);
 843                 io_mapping_unmap_atomic(s);
 844
 845                 if (ret)
 846                         goto unwind;
 847         }
 848         goto out;
 849
 850 unwind:
 851         while (dst->page_count--)
 852                 free_page((unsigned long)dst->pages[dst->page_count]);
 853         kfree(dst);
 854         dst = NULL;
 855
 856 out:
 857         compress_fini(&zstream, dst);
 858         ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
 859         return dst;
 860 }
 861
 862 /* The error capture is special as tries to run underneath the normal
 863  * locking rules - so we use the raw version of the i915_gem_active lookup.
 864  */
 865 static inline uint32_t
 866 __active_get_seqno(struct i915_gem_active *active)
 867 {
 868         return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
 869 }
 870
 871 static inline int
 872 __active_get_engine_id(struct i915_gem_active *active)
 873 {
 874         struct intel_engine_cs *engine;
 875
 876         engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
 877         return engine ? engine->id : -1;
 878 }
 879
 880 static void capture_bo(struct drm_i915_error_buffer *err,
 881                        struct i915_vma *vma)
 882 {
 883         struct drm_i915_gem_object *obj = vma->obj;
 884         int i;
 885
 886         err->size = obj->base.size;
 887         err->name = obj->base.name;
 888
 889         for (i = 0; i < I915_NUM_ENGINES; i++)
 890                 err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
 891         err->wseqno = __active_get_seqno(&obj->last_write);
 892         err->engine = __active_get_engine_id(&obj->last_write);
 893
 894         err->gtt_offset = vma->node.start;
 895         err->read_domains = obj->base.read_domains;
 896         err->write_domain = obj->base.write_domain;
 897         err->fence_reg = vma->fence ? vma->fence->id : -1;
 898         err->tiling = i915_gem_object_get_tiling(obj);
 899         err->dirty = obj->dirty;
 900         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 901         err->userptr = obj->userptr.mm != NULL;
 902         err->cache_level = obj->cache_level;
 903 }
 904
 905 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
 906                             int count, struct list_head *head,
 907                             bool pinned_only)
 908 {
 909         struct i915_vma *vma;
 910         int i = 0;
 911
 912         list_for_each_entry(vma, head, vm_link) {
 913                 if (pinned_only && !i915_vma_is_pinned(vma))
 914                         continue;
 915
 916                 capture_bo(err++, vma);
 917                 if (++i == count)
 918                         break;
 919         }
 920
 921         return i;
 922 }
 923
 924 /* Generate a semi-unique error code. The code is not meant to have meaning, The
 925  * code's only purpose is to try to prevent false duplicated bug reports by
 926  * grossly estimating a GPU error state.
 927  *
 928  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 929  * the hang if we could strip the GTT offset information from it.
 930  *
 931  * It's only a small step better than a random number in its current form.
 932  */
 933 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
 934                                          struct drm_i915_error_state *error,
 935                                          int *engine_id)
 936 {
 937         uint32_t error_code = 0;
 938         int i;
 939
 940         /* IPEHR would be an ideal way to detect errors, as it's the gross
 941          * measure of "the command that hung." However, has some very common
 942          * synchronization commands which almost always appear in the case
 943          * strictly a client bug. Use instdone to differentiate those some.
 944          */
 945         for (i = 0; i < I915_NUM_ENGINES; i++) {
 946                 if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
 947                         if (engine_id)
 948                                 *engine_id = i;
 949
 950                         return error->engine[i].ipehr ^
 951                                error->engine[i].instdone.instdone;
 952                 }
 953         }
 954
 955         return error_code;
 956 }
 957
 958 static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
 959                                    struct drm_i915_error_state *error)
 960 {
 961         int i;
 962
 963         if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
 964                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 965                         error->fence[i] = I915_READ(FENCE_REG(i));
 966         } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
 967                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 968                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
 969         } else if (INTEL_GEN(dev_priv) >= 6) {
 970                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 971                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
 972         }
 973 }
 974
 975
 976 static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
 977                                         struct intel_engine_cs *engine,
 978                                         struct drm_i915_error_engine *ee)
 979 {
 980         struct drm_i915_private *dev_priv = engine->i915;
 981         struct intel_engine_cs *to;
 982         enum intel_engine_id id;
 983
 984         if (!error->semaphore)
 985                 return;
 986
 987         for_each_engine(to, dev_priv, id) {
 988                 int idx;
 989                 u16 signal_offset;
 990                 u32 *tmp;
 991
 992                 if (engine == to)
 993                         continue;
 994
 995                 signal_offset =
 996                         (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
 997                 tmp = error->semaphore->pages[0];
 998                 idx = intel_engine_sync_index(engine, to);
 999
1000                 ee->semaphore_mboxes[idx] = tmp[signal_offset];
1001                 ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
1002         }
1003 }
1004
1005 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1006                                         struct drm_i915_error_engine *ee)
1007 {
1008         struct drm_i915_private *dev_priv = engine->i915;
1009
1010         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1011         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1012         ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
1013         ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
1014
1015         if (HAS_VEBOX(dev_priv)) {
1016                 ee->semaphore_mboxes[2] =
1017                         I915_READ(RING_SYNC_2(engine->mmio_base));
1018                 ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
1019         }
1020 }
1021
1022 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1023                                         struct drm_i915_error_engine *ee)
1024 {
1025         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1026         struct drm_i915_error_waiter *waiter;
1027         struct rb_node *rb;
1028         int count;
1029
1030         ee->num_waiters = 0;
1031         ee->waiters = NULL;
1032
1033         if (RB_EMPTY_ROOT(&b->waiters))
1034                 return;
1035
1036         if (!spin_trylock(&b->lock)) {
1037                 ee->waiters = ERR_PTR(-EDEADLK);
1038                 return;
1039         }
1040
1041         count = 0;
1042         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1043                 count++;
1044         spin_unlock(&b->lock);
1045
1046         waiter = NULL;
1047         if (count)
1048                 waiter = kmalloc_array(count,
1049                                        sizeof(struct drm_i915_error_waiter),
1050                                        GFP_ATOMIC);
1051         if (!waiter)
1052                 return;
1053
1054         if (!spin_trylock(&b->lock)) {
1055                 kfree(waiter);
1056                 ee->waiters = ERR_PTR(-EDEADLK);
1057                 return;
1058         }
1059
1060         ee->waiters = waiter;
1061         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1062                 struct intel_wait *w = container_of(rb, typeof(*w), node);
1063
1064                 strcpy(waiter->comm, w->tsk->comm);
1065                 waiter->pid = w->tsk->pid;
1066                 waiter->seqno = w->seqno;
1067                 waiter++;
1068
1069                 if (++ee->num_waiters == count)
1070                         break;
1071         }
1072         spin_unlock(&b->lock);
1073 }
1074
1075 static void error_record_engine_registers(struct drm_i915_error_state *error,
1076                                           struct intel_engine_cs *engine,
1077                                           struct drm_i915_error_engine *ee)
1078 {
1079         struct drm_i915_private *dev_priv = engine->i915;
1080
1081         if (INTEL_GEN(dev_priv) >= 6) {
1082                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1083                 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1084                 if (INTEL_GEN(dev_priv) >= 8)
1085                         gen8_record_semaphore_state(error, engine, ee);
1086                 else
1087                         gen6_record_semaphore_state(engine, ee);
1088         }
1089
1090         if (INTEL_GEN(dev_priv) >= 4) {
1091                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1092                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1093                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1094                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1095                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1096                 if (INTEL_GEN(dev_priv) >= 8) {
1097                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1098                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1099                 }
1100                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1101         } else {
1102                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1103                 ee->ipeir = I915_READ(IPEIR);
1104                 ee->ipehr = I915_READ(IPEHR);
1105         }
1106
1107         intel_engine_get_instdone(engine, &ee->instdone);
1108
1109         ee->waiting = intel_engine_has_waiter(engine);
1110         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1111         ee->acthd = intel_engine_get_active_head(engine);
1112         ee->seqno = intel_engine_get_seqno(engine);
1113         ee->last_seqno = engine->last_submitted_seqno;
1114         ee->start = I915_READ_START(engine);
1115         ee->head = I915_READ_HEAD(engine);
1116         ee->tail = I915_READ_TAIL(engine);
1117         ee->ctl = I915_READ_CTL(engine);
1118         if (INTEL_GEN(dev_priv) > 2)
1119                 ee->mode = I915_READ_MODE(engine);
1120
1121         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1122                 i915_reg_t mmio;
1123
1124                 if (IS_GEN7(dev_priv)) {
1125                         switch (engine->id) {
1126                         default:
1127                         case RCS:
1128                                 mmio = RENDER_HWS_PGA_GEN7;
1129                                 break;
1130                         case BCS:
1131                                 mmio = BLT_HWS_PGA_GEN7;
1132                                 break;
1133                         case VCS:
1134                                 mmio = BSD_HWS_PGA_GEN7;
1135                                 break;
1136                         case VECS:
1137                                 mmio = VEBOX_HWS_PGA_GEN7;
1138                                 break;
1139                         }
1140                 } else if (IS_GEN6(engine->i915)) {
1141                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1142                 } else {
1143                         /* XXX: gen8 returns to sanity */
1144                         mmio = RING_HWS_PGA(engine->mmio_base);
1145                 }
1146
1147                 ee->hws = I915_READ(mmio);
1148         }
1149
1150         ee->hangcheck_score = engine->hangcheck.score;
1151         ee->hangcheck_action = engine->hangcheck.action;
1152
1153         if (USES_PPGTT(dev_priv)) {
1154                 int i;
1155
1156                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1157
1158                 if (IS_GEN6(dev_priv))
1159                         ee->vm_info.pp_dir_base =
1160                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1161                 else if (IS_GEN7(dev_priv))
1162                         ee->vm_info.pp_dir_base =
1163                                 I915_READ(RING_PP_DIR_BASE(engine));
1164                 else if (INTEL_GEN(dev_priv) >= 8)
1165                         for (i = 0; i < 4; i++) {
1166                                 ee->vm_info.pdp[i] =
1167                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1168                                 ee->vm_info.pdp[i] <<= 32;
1169                                 ee->vm_info.pdp[i] |=
1170                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1171                         }
1172         }
1173 }
1174
1175 static void record_request(struct drm_i915_gem_request *request,
1176                            struct drm_i915_error_request *erq)
1177 {
1178         erq->context = request->ctx->hw_id;
1179         erq->seqno = request->fence.seqno;
1180         erq->jiffies = request->emitted_jiffies;
1181         erq->head = request->head;
1182         erq->tail = request->tail;
1183
1184         rcu_read_lock();
1185         erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1186         rcu_read_unlock();
1187 }
1188
1189 static void engine_record_requests(struct intel_engine_cs *engine,
1190                                    struct drm_i915_gem_request *first,
1191                                    struct drm_i915_error_engine *ee)
1192 {
1193         struct drm_i915_gem_request *request;
1194         int count;
1195
1196         count = 0;
1197         request = first;
1198         list_for_each_entry_from(request, &engine->request_list, link)
1199                 count++;
1200         if (!count)
1201                 return;
1202
1203         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1204         if (!ee->requests)
1205                 return;
1206
1207         ee->num_requests = count;
1208
1209         count = 0;
1210         request = first;
1211         list_for_each_entry_from(request, &engine->request_list, link) {
1212                 if (count >= ee->num_requests) {
1213                         /*
1214                          * If the ring request list was changed in
1215                          * between the point where the error request
1216                          * list was created and dimensioned and this
1217                          * point then just exit early to avoid crashes.
1218                          *
1219                          * We don't need to communicate that the
1220                          * request list changed state during error
1221                          * state capture and that the error state is
1222                          * slightly incorrect as a consequence since we
1223                          * are typically only interested in the request
1224                          * list state at the point of error state
1225                          * capture, not in any changes happening during
1226                          * the capture.
1227                          */
1228                         break;
1229                 }
1230
1231                 record_request(request, &ee->requests[count++]);
1232         }
1233         ee->num_requests = count;
1234 }
1235
1236 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1237                                           struct drm_i915_error_engine *ee)
1238 {
1239         unsigned int n;
1240
1241         for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
1242                 if (engine->execlist_port[n].request)
1243                         record_request(engine->execlist_port[n].request,
1244                                        &ee->execlist[n]);
1245 }
1246
1247 static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1248                                   struct drm_i915_error_state *error)
1249 {
1250         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1251         int i;
1252
1253         error->semaphore =
1254                 i915_error_object_create(dev_priv, dev_priv->semaphore);
1255
1256         for (i = 0; i < I915_NUM_ENGINES; i++) {
1257                 struct intel_engine_cs *engine = dev_priv->engine[i];
1258                 struct drm_i915_error_engine *ee = &error->engine[i];
1259                 struct drm_i915_gem_request *request;
1260
1261                 ee->pid = -1;
1262                 ee->engine_id = -1;
1263
1264                 if (!engine)
1265                         continue;
1266
1267                 ee->engine_id = i;
1268
1269                 error_record_engine_registers(error, engine, ee);
1270                 error_record_engine_waiters(engine, ee);
1271                 error_record_engine_execlists(engine, ee);
1272
1273                 request = i915_gem_find_active_request(engine);
1274                 if (request) {
1275                         struct intel_ring *ring;
1276                         struct pid *pid;
1277
1278                         ee->vm = request->ctx->ppgtt ?
1279                                 &request->ctx->ppgtt->base : &ggtt->base;
1280
1281                         /* We need to copy these to an anonymous buffer
1282                          * as the simplest method to avoid being overwritten
1283                          * by userspace.
1284                          */
1285                         ee->batchbuffer =
1286                                 i915_error_object_create(dev_priv,
1287                                                          request->batch);
1288
1289                         if (HAS_BROKEN_CS_TLB(dev_priv))
1290                                 ee->wa_batchbuffer =
1291                                         i915_error_object_create(dev_priv,
1292                                                                  engine->scratch);
1293
1294                         ee->ctx =
1295                                 i915_error_object_create(dev_priv,
1296                                                          request->ctx->engine[i].state);
1297
1298                         pid = request->ctx->pid;
1299                         if (pid) {
1300                                 struct task_struct *task;
1301
1302                                 rcu_read_lock();
1303                                 task = pid_task(pid, PIDTYPE_PID);
1304                                 if (task) {
1305                                         strcpy(ee->comm, task->comm);
1306                                         ee->pid = task->pid;
1307                                 }
1308                                 rcu_read_unlock();
1309                         }
1310
1311                         error->simulated |=
1312                                 request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
1313
1314                         ee->rq_head = request->head;
1315                         ee->rq_post = request->postfix;
1316                         ee->rq_tail = request->tail;
1317
1318                         ring = request->ring;
1319                         ee->cpu_ring_head = ring->head;
1320                         ee->cpu_ring_tail = ring->tail;
1321                         ee->ringbuffer =
1322                                 i915_error_object_create(dev_priv, ring->vma);
1323
1324                         engine_record_requests(engine, request, ee);
1325                 }
1326
1327                 ee->hws_page =
1328                         i915_error_object_create(dev_priv,
1329                                                  engine->status_page.vma);
1330
1331                 ee->wa_ctx =
1332                         i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1333         }
1334 }
1335
1336 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1337                                 struct drm_i915_error_state *error,
1338                                 struct i915_address_space *vm,
1339                                 int idx)
1340 {
1341         struct drm_i915_error_buffer *active_bo;
1342         struct i915_vma *vma;
1343         int count;
1344
1345         count = 0;
1346         list_for_each_entry(vma, &vm->active_list, vm_link)
1347                 count++;
1348
1349         active_bo = NULL;
1350         if (count)
1351                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1352         if (active_bo)
1353                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1354         else
1355                 count = 0;
1356
1357         error->active_vm[idx] = vm;
1358         error->active_bo[idx] = active_bo;
1359         error->active_bo_count[idx] = count;
1360 }
1361
1362 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1363                                         struct drm_i915_error_state *error)
1364 {
1365         int cnt = 0, i, j;
1366
1367         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1368         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1369         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1370
1371         /* Scan each engine looking for unique active contexts/vm */
1372         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1373                 struct drm_i915_error_engine *ee = &error->engine[i];
1374                 bool found;
1375
1376                 if (!ee->vm)
1377                         continue;
1378
1379                 found = false;
1380                 for (j = 0; j < i && !found; j++)
1381                         found = error->engine[j].vm == ee->vm;
1382                 if (!found)
1383                         i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1384         }
1385 }
1386
1387 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1388                                         struct drm_i915_error_state *error)
1389 {
1390         struct i915_address_space *vm = &dev_priv->ggtt.base;
1391         struct drm_i915_error_buffer *bo;
1392         struct i915_vma *vma;
1393         int count_inactive, count_active;
1394
1395         count_inactive = 0;
1396         list_for_each_entry(vma, &vm->active_list, vm_link)
1397                 count_inactive++;
1398
1399         count_active = 0;
1400         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1401                 count_active++;
1402
1403         bo = NULL;
1404         if (count_inactive + count_active)
1405                 bo = kcalloc(count_inactive + count_active,
1406                              sizeof(*bo), GFP_ATOMIC);
1407         if (!bo)
1408                 return;
1409
1410         count_inactive = capture_error_bo(bo, count_inactive,
1411                                           &vm->active_list, true);
1412         count_active = capture_error_bo(bo + count_inactive, count_active,
1413                                         &vm->inactive_list, true);
1414         error->pinned_bo_count = count_inactive + count_active;
1415         error->pinned_bo = bo;
1416 }
1417
1418 static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
1419                                             struct drm_i915_error_state *error)
1420 {
1421         /* Capturing log buf contents won't be useful if logging was disabled */
1422         if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
1423                 return;
1424
1425         error->guc_log = i915_error_object_create(dev_priv,
1426                                                   dev_priv->guc.log.vma);
1427 }
1428
1429 /* Capture all registers which don't fit into another category. */
1430 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1431                                    struct drm_i915_error_state *error)
1432 {
1433         struct drm_device *dev = &dev_priv->drm;
1434         int i;
1435
1436         /* General organization
1437          * 1. Registers specific to a single generation
1438          * 2. Registers which belong to multiple generations
1439          * 3. Feature specific registers.
1440          * 4. Everything else
1441          * Please try to follow the order.
1442          */
1443
1444         /* 1: Registers specific to a single generation */
1445         if (IS_VALLEYVIEW(dev_priv)) {
1446                 error->gtier[0] = I915_READ(GTIER);
1447                 error->ier = I915_READ(VLV_IER);
1448                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1449         }
1450
1451         if (IS_GEN7(dev_priv))
1452                 error->err_int = I915_READ(GEN7_ERR_INT);
1453
1454         if (INTEL_INFO(dev)->gen >= 8) {
1455                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1456                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1457         }
1458
1459         if (IS_GEN6(dev_priv)) {
1460                 error->forcewake = I915_READ_FW(FORCEWAKE);
1461                 error->gab_ctl = I915_READ(GAB_CTL);
1462                 error->gfx_mode = I915_READ(GFX_MODE);
1463         }
1464
1465         /* 2: Registers which belong to multiple generations */
1466         if (INTEL_INFO(dev)->gen >= 7)
1467                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1468
1469         if (INTEL_INFO(dev)->gen >= 6) {
1470                 error->derrmr = I915_READ(DERRMR);
1471                 error->error = I915_READ(ERROR_GEN6);
1472                 error->done_reg = I915_READ(DONE_REG);
1473         }
1474
1475         /* 3: Feature specific registers */
1476         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1477                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1478                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1479         }
1480
1481         /* 4: Everything else */
1482         if (HAS_HW_CONTEXTS(dev))
1483                 error->ccid = I915_READ(CCID);
1484
1485         if (INTEL_INFO(dev)->gen >= 8) {
1486                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1487                 for (i = 0; i < 4; i++)
1488                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1489         } else if (HAS_PCH_SPLIT(dev_priv)) {
1490                 error->ier = I915_READ(DEIER);
1491                 error->gtier[0] = I915_READ(GTIER);
1492         } else if (IS_GEN2(dev_priv)) {
1493                 error->ier = I915_READ16(IER);
1494         } else if (!IS_VALLEYVIEW(dev_priv)) {
1495                 error->ier = I915_READ(IER);
1496         }
1497         error->eir = I915_READ(EIR);
1498         error->pgtbl_er = I915_READ(PGTBL_ER);
1499 }
1500
1501 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1502                                    struct drm_i915_error_state *error,
1503                                    u32 engine_mask,
1504                                    const char *error_msg)
1505 {
1506         u32 ecode;
1507         int engine_id = -1, len;
1508
1509         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1510
1511         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1512                         "GPU HANG: ecode %d:%d:0x%08x",
1513                         INTEL_GEN(dev_priv), engine_id, ecode);
1514
1515         if (engine_id != -1 && error->engine[engine_id].pid != -1)
1516                 len += scnprintf(error->error_msg + len,
1517                                  sizeof(error->error_msg) - len,
1518                                  ", in %s [%d]",
1519                                  error->engine[engine_id].comm,
1520                                  error->engine[engine_id].pid);
1521
1522         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1523                   ", reason: %s, action: %s",
1524                   error_msg,
1525                   engine_mask ? "reset" : "continue");
1526 }
1527
1528 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1529                                    struct drm_i915_error_state *error)
1530 {
1531         error->iommu = -1;
1532 #ifdef CONFIG_INTEL_IOMMU
1533         error->iommu = intel_iommu_gfx_mapped;
1534 #endif
1535         error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1536         error->suspend_count = dev_priv->suspend_count;
1537
1538         memcpy(&error->device_info,
1539                INTEL_INFO(dev_priv),
1540                sizeof(error->device_info));
1541 }
1542
1543 static int capture(void *data)
1544 {
1545         struct drm_i915_error_state *error = data;
1546
1547         i915_capture_gen_state(error->i915, error);
1548         i915_capture_reg_state(error->i915, error);
1549         i915_gem_record_fences(error->i915, error);
1550         i915_gem_record_rings(error->i915, error);
1551         i915_capture_active_buffers(error->i915, error);
1552         i915_capture_pinned_buffers(error->i915, error);
1553         i915_gem_capture_guc_log_buffer(error->i915, error);
1554
1555         do_gettimeofday(&error->time);
1556         error->boottime = ktime_to_timeval(ktime_get_boottime());
1557         error->uptime =
1558                 ktime_to_timeval(ktime_sub(ktime_get(),
1559                                            error->i915->gt.last_init_time));
1560
1561         error->overlay = intel_overlay_capture_error_state(error->i915);
1562         error->display = intel_display_capture_error_state(error->i915);
1563
1564         return 0;
1565 }
1566
1567 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1568
1569 /**
1570  * i915_capture_error_state - capture an error record for later analysis
1571  * @dev: drm device
1572  *
1573  * Should be called when an error is detected (either a hang or an error
1574  * interrupt) to capture error state from the time of the error.  Fills
1575  * out a structure which becomes available in debugfs for user level tools
1576  * to pick up.
1577  */
1578 void i915_capture_error_state(struct drm_i915_private *dev_priv,
1579                               u32 engine_mask,
1580                               const char *error_msg)
1581 {
1582         static bool warned;
1583         struct drm_i915_error_state *error;
1584         unsigned long flags;
1585
1586         if (!i915.error_capture)
1587                 return;
1588
1589         if (READ_ONCE(dev_priv->gpu_error.first_error))
1590                 return;
1591
1592         /* Account for pipe specific data like PIPE*STAT */
1593         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1594         if (!error) {
1595                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1596                 return;
1597         }
1598
1599         kref_init(&error->ref);
1600         error->i915 = dev_priv;
1601
1602         stop_machine(capture, error, NULL);
1603
1604         i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1605         DRM_INFO("%s\n", error->error_msg);
1606
1607         if (!error->simulated) {
1608                 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1609                 if (!dev_priv->gpu_error.first_error) {
1610                         dev_priv->gpu_error.first_error = error;
1611                         error = NULL;
1612                 }
1613                 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1614         }
1615
1616         if (error) {
1617                 i915_error_state_free(&error->ref);
1618                 return;
1619         }
1620
1621         if (!warned &&
1622             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1623                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1624                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1625                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1626                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1627                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1628                          dev_priv->drm.primary->index);
1629                 warned = true;
1630         }
1631 }
1632
1633 void i915_error_state_get(struct drm_device *dev,
1634                           struct i915_error_state_file_priv *error_priv)
1635 {
1636         struct drm_i915_private *dev_priv = to_i915(dev);
1637
1638         spin_lock_irq(&dev_priv->gpu_error.lock);
1639         error_priv->error = dev_priv->gpu_error.first_error;
1640         if (error_priv->error)
1641                 kref_get(&error_priv->error->ref);
1642         spin_unlock_irq(&dev_priv->gpu_error.lock);
1643 }
1644
1645 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1646 {
1647         if (error_priv->error)
1648                 kref_put(&error_priv->error->ref, i915_error_state_free);
1649 }
1650
1651 void i915_destroy_error_state(struct drm_device *dev)
1652 {
1653         struct drm_i915_private *dev_priv = to_i915(dev);
1654         struct drm_i915_error_state *error;
1655
1656         spin_lock_irq(&dev_priv->gpu_error.lock);
1657         error = dev_priv->gpu_error.first_error;
1658         dev_priv->gpu_error.first_error = NULL;
1659         spin_unlock_irq(&dev_priv->gpu_error.lock);
1660
1661         if (error)
1662                 kref_put(&error->ref, i915_error_state_free);
1663 }