2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
73 u32 val = I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val);
78 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
80 struct drm_i915_private *dev_priv = guc_to_i915(guc);
85 if (WARN_ON(len < 1 || len > 15))
88 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
90 dev_priv->guc.action_count += 1;
91 dev_priv->guc.action_cmd = data[0];
93 for (i = 0; i < len; i++)
94 I915_WRITE(SOFT_SCRATCH(i), data[i]);
96 POSTING_READ(SOFT_SCRATCH(i - 1));
98 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
100 /* No HOST2GUC command should take longer than 10ms */
101 ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
102 if (status != GUC2HOST_STATUS_SUCCESS) {
104 * Either the GuC explicitly returned an error (which
105 * we convert to -EIO here) or no response at all was
106 * received within the timeout limit (-ETIMEDOUT)
108 if (ret != -ETIMEDOUT)
111 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
112 "status=0x%08X response=0x%08X\n",
113 data[0], ret, status,
114 I915_READ(SOFT_SCRATCH(15)));
116 dev_priv->guc.action_fail += 1;
117 dev_priv->guc.action_err = ret;
119 dev_priv->guc.action_status = status;
121 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
127 * Tell the GuC to allocate or deallocate a specific doorbell
130 static int host2guc_allocate_doorbell(struct intel_guc *guc,
131 struct i915_guc_client *client)
135 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
136 data[1] = client->ctx_index;
138 return host2guc_action(guc, data, 2);
141 static int host2guc_release_doorbell(struct intel_guc *guc,
142 struct i915_guc_client *client)
146 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
147 data[1] = client->ctx_index;
149 return host2guc_action(guc, data, 2);
152 static int host2guc_sample_forcewake(struct intel_guc *guc,
153 struct i915_guc_client *client)
155 struct drm_i915_private *dev_priv = guc_to_i915(guc);
156 struct drm_device *dev = dev_priv->dev;
159 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
160 /* WaRsDisableCoarsePowerGating:skl,bxt */
161 if (!intel_enable_rc6(dev_priv->dev) ||
162 IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
163 (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||
164 (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
167 /* bit 0 and 1 are for Render and Media domain separately */
168 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
170 return host2guc_action(guc, data, ARRAY_SIZE(data));
174 * Initialise, update, or clear doorbell data shared with the GuC
176 * These functions modify shared data and so need access to the mapped
177 * client object which contains the page being used for the doorbell
180 static void guc_init_doorbell(struct intel_guc *guc,
181 struct i915_guc_client *client)
183 struct guc_doorbell_info *doorbell;
186 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
187 doorbell = base + client->doorbell_offset;
189 doorbell->db_status = 1;
190 doorbell->cookie = 0;
195 static int guc_ring_doorbell(struct i915_guc_client *gc)
197 struct guc_process_desc *desc;
198 union guc_doorbell_qw db_cmp, db_exc, db_ret;
199 union guc_doorbell_qw *db;
201 int attempt = 2, ret = -EAGAIN;
203 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
204 desc = base + gc->proc_desc_offset;
206 /* Update the tail so it is visible to GuC */
207 desc->tail = gc->wq_tail;
210 db_cmp.db_status = GUC_DOORBELL_ENABLED;
211 db_cmp.cookie = gc->cookie;
213 /* cookie to be updated */
214 db_exc.db_status = GUC_DOORBELL_ENABLED;
215 db_exc.cookie = gc->cookie + 1;
216 if (db_exc.cookie == 0)
219 /* pointer of current doorbell cacheline */
220 db = base + gc->doorbell_offset;
223 /* lets ring the doorbell */
224 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
225 db_cmp.value_qw, db_exc.value_qw);
227 /* if the exchange was successfully executed */
228 if (db_ret.value_qw == db_cmp.value_qw) {
229 /* db was successfully rung */
230 gc->cookie = db_exc.cookie;
235 /* XXX: doorbell was lost and need to acquire it again */
236 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
239 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
240 db_cmp.cookie, db_ret.cookie);
242 /* update the cookie to newly read cookie from GuC */
243 db_cmp.cookie = db_ret.cookie;
244 db_exc.cookie = db_ret.cookie + 1;
245 if (db_exc.cookie == 0)
253 static void guc_disable_doorbell(struct intel_guc *guc,
254 struct i915_guc_client *client)
256 struct drm_i915_private *dev_priv = guc_to_i915(guc);
257 struct guc_doorbell_info *doorbell;
259 i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id);
262 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
263 doorbell = base + client->doorbell_offset;
265 doorbell->db_status = 0;
269 I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID);
271 value = I915_READ(drbreg);
272 WARN_ON((value & GEN8_DRB_VALID) != 0);
274 I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0);
275 I915_WRITE(drbreg, 0);
277 /* XXX: wait for any interrupts */
278 /* XXX: wait for workqueue to drain */
282 * Select, assign and relase doorbell cachelines
284 * These functions track which doorbell cachelines are in use.
285 * The data they manipulate is protected by the host2guc lock.
288 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
290 const uint32_t cacheline_size = cache_line_size();
293 /* Doorbell uses a single cache line within a page */
294 offset = offset_in_page(guc->db_cacheline);
296 /* Moving to next cache line to reduce contention */
297 guc->db_cacheline += cacheline_size;
299 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
300 offset, guc->db_cacheline, cacheline_size);
305 static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority)
308 * The bitmap is split into two halves; the first half is used for
309 * normal priority contexts, the second half for high-priority ones.
310 * Note that logically higher priorities are numerically less than
311 * normal ones, so the test below means "is it high-priority?"
313 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
314 const uint16_t half = GUC_MAX_DOORBELLS / 2;
315 const uint16_t start = hi_pri ? half : 0;
316 const uint16_t end = start + half;
319 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
321 id = GUC_INVALID_DOORBELL_ID;
323 bitmap_set(guc->doorbell_bitmap, id, 1);
325 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
326 hi_pri ? "high" : "normal", id);
331 static void release_doorbell(struct intel_guc *guc, uint16_t id)
333 bitmap_clear(guc->doorbell_bitmap, id, 1);
337 * Initialise the process descriptor shared with the GuC firmware.
339 static void guc_init_proc_desc(struct intel_guc *guc,
340 struct i915_guc_client *client)
342 struct guc_process_desc *desc;
345 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
346 desc = base + client->proc_desc_offset;
348 memset(desc, 0, sizeof(*desc));
351 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
352 * space for ring3 clients (set them as in mmap_ioctl) or kernel
353 * space for kernel clients (map on demand instead? May make debug
354 * easier to have it mapped).
356 desc->wq_base_addr = 0;
357 desc->db_base_addr = 0;
359 desc->context_id = client->ctx_index;
360 desc->wq_size_bytes = client->wq_size;
361 desc->wq_status = WQ_STATUS_ACTIVE;
362 desc->priority = client->priority;
368 * Initialise/clear the context descriptor shared with the GuC firmware.
370 * This descriptor tells the GuC where (in GGTT space) to find the important
371 * data structures relating to this client (doorbell, process descriptor,
375 static void guc_init_ctx_desc(struct intel_guc *guc,
376 struct i915_guc_client *client)
378 struct intel_context *ctx = client->owner;
379 struct guc_context_desc desc;
383 memset(&desc, 0, sizeof(desc));
385 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
386 desc.context_id = client->ctx_index;
387 desc.priority = client->priority;
388 desc.db_id = client->doorbell_id;
390 for (i = 0; i < I915_NUM_RINGS; i++) {
391 struct guc_execlist_context *lrc = &desc.lrc[i];
392 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
393 struct intel_engine_cs *ring;
394 struct drm_i915_gem_object *obj;
397 /* TODO: We have a design issue to be solved here. Only when we
398 * receive the first batch, we know which engine is used by the
399 * user. But here GuC expects the lrc and ring to be pinned. It
400 * is not an issue for default context, which is the only one
401 * for now who owns a GuC client. But for future owner of GuC
402 * client, need to make sure lrc is pinned prior to enter here.
404 obj = ctx->engine[i].state;
406 break; /* XXX: continue? */
408 ring = ringbuf->ring;
409 ctx_desc = intel_lr_context_descriptor(ctx, ring);
410 lrc->context_desc = (u32)ctx_desc;
412 /* The state page is after PPHWSP */
413 lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
414 LRC_STATE_PN * PAGE_SIZE;
415 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
416 (ring->id << GUC_ELC_ENGINE_OFFSET);
420 lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
421 lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
422 lrc->ring_next_free_location = lrc->ring_begin;
423 lrc->ring_current_tail_pointer_value = 0;
425 desc.engines_used |= (1 << ring->id);
428 WARN_ON(desc.engines_used == 0);
431 * The CPU address is only needed at certain points, so kmap_atomic on
432 * demand instead of storing it in the ctx descriptor.
433 * XXX: May make debug easier to have it mapped
435 desc.db_trigger_cpu = 0;
436 desc.db_trigger_uk = client->doorbell_offset +
437 i915_gem_obj_ggtt_offset(client->client_obj);
438 desc.db_trigger_phy = client->doorbell_offset +
439 sg_dma_address(client->client_obj->pages->sgl);
441 desc.process_desc = client->proc_desc_offset +
442 i915_gem_obj_ggtt_offset(client->client_obj);
444 desc.wq_addr = client->wq_offset +
445 i915_gem_obj_ggtt_offset(client->client_obj);
447 desc.wq_size = client->wq_size;
450 * XXX: Take LRCs from an existing intel_context if this is not an
451 * IsKMDCreatedContext client
453 desc.desc_private = (uintptr_t)client;
455 /* Pool context is pinned already */
456 sg = guc->ctx_pool_obj->pages;
457 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
458 sizeof(desc) * client->ctx_index);
461 static void guc_fini_ctx_desc(struct intel_guc *guc,
462 struct i915_guc_client *client)
464 struct guc_context_desc desc;
467 memset(&desc, 0, sizeof(desc));
469 sg = guc->ctx_pool_obj->pages;
470 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
471 sizeof(desc) * client->ctx_index);
474 /* Get valid workqueue item and return it back to offset */
475 static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
477 struct guc_process_desc *desc;
479 u32 size = sizeof(struct guc_wq_item);
480 int ret = -ETIMEDOUT, timeout_counter = 200;
482 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
483 desc = base + gc->proc_desc_offset;
485 while (timeout_counter-- > 0) {
486 if (CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size) >= size) {
487 *offset = gc->wq_tail;
489 /* advance the tail for next workqueue item */
491 gc->wq_tail &= gc->wq_size - 1;
493 /* this will break the loop */
499 usleep_range(1000, 2000);
507 static int guc_add_workqueue_item(struct i915_guc_client *gc,
508 struct drm_i915_gem_request *rq)
510 enum intel_ring_id ring_id = rq->ring->id;
511 struct guc_wq_item *wqi;
513 u32 tail, wq_len, wq_off = 0;
516 ret = guc_get_workqueue_space(gc, &wq_off);
520 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
521 * should not have the case where structure wqi is across page, neither
522 * wrapped to the beginning. This simplifies the implementation below.
524 * XXX: if not the case, we need save data to a temp wqi and copy it to
525 * workqueue buffer dw by dw.
527 WARN_ON(sizeof(struct guc_wq_item) != 16);
530 /* wq starts from the page after doorbell / process_desc */
531 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj,
532 (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT));
533 wq_off &= PAGE_SIZE - 1;
534 wqi = (struct guc_wq_item *)((char *)base + wq_off);
536 /* len does not include the header */
537 wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
538 wqi->header = WQ_TYPE_INORDER |
539 (wq_len << WQ_LEN_SHIFT) |
540 (ring_id << WQ_TARGET_SHIFT) |
543 /* The GuC wants only the low-order word of the context descriptor */
544 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring);
546 /* The GuC firmware wants the tail index in QWords, not bytes */
547 tail = rq->ringbuf->tail >> 3;
548 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
549 wqi->fence_id = 0; /*XXX: what fence to be here */
556 #define CTX_RING_BUFFER_START 0x08
558 /* Update the ringbuffer pointer in a saved context image */
559 static void lr_context_update(struct drm_i915_gem_request *rq)
561 enum intel_ring_id ring_id = rq->ring->id;
562 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state;
563 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
568 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
569 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
571 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
572 reg_state = kmap_atomic(page);
574 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
576 kunmap_atomic(reg_state);
580 * i915_guc_submit() - Submit commands through GuC
581 * @client: the guc client where commands will go through
582 * @rq: request associated with the commands
584 * Return: 0 if succeed
586 int i915_guc_submit(struct i915_guc_client *client,
587 struct drm_i915_gem_request *rq)
589 struct intel_guc *guc = client->guc;
590 enum intel_ring_id ring_id = rq->ring->id;
593 /* Need this because of the deferred pin ctx and ring */
594 /* Shall we move this right after ring is pinned? */
595 lr_context_update(rq);
597 q_ret = guc_add_workqueue_item(client, rq);
599 b_ret = guc_ring_doorbell(client);
601 client->submissions[ring_id] += 1;
604 client->retcode = q_ret;
607 client->retcode = q_ret = b_ret;
611 guc->submissions[ring_id] += 1;
612 guc->last_seqno[ring_id] = rq->seqno;
618 * Everything below here is concerned with setup & teardown, and is
619 * therefore not part of the somewhat time-critical batch-submission
620 * path of i915_guc_submit() above.
624 * gem_allocate_guc_obj() - Allocate gem object for GuC usage
626 * @size: size of object
628 * This is a wrapper to create a gem obj. In order to use it inside GuC, the
629 * object needs to be pinned lifetime. Also we must pin it to gtt space other
630 * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
632 * Return: A drm_i915_gem_object if successful, otherwise NULL.
634 static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_i915_gem_object *obj;
640 obj = i915_gem_alloc_object(dev, size);
644 if (i915_gem_object_get_pages(obj)) {
645 drm_gem_object_unreference(&obj->base);
649 if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
650 PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
651 drm_gem_object_unreference(&obj->base);
655 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
656 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
662 * gem_release_guc_obj() - Release gem object allocated for GuC usage
663 * @obj: gem obj to be released
665 static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
670 if (i915_gem_obj_is_pinned(obj))
671 i915_gem_object_ggtt_unpin(obj);
673 drm_gem_object_unreference(&obj->base);
676 static void guc_client_free(struct drm_device *dev,
677 struct i915_guc_client *client)
679 struct drm_i915_private *dev_priv = dev->dev_private;
680 struct intel_guc *guc = &dev_priv->guc;
685 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) {
687 * First disable the doorbell, then tell the GuC we've
688 * finished with it, finally deallocate it in our bitmap
690 guc_disable_doorbell(guc, client);
691 host2guc_release_doorbell(guc, client);
692 release_doorbell(guc, client->doorbell_id);
696 * XXX: wait for any outstanding submissions before freeing memory.
697 * Be sure to drop any locks
700 gem_release_guc_obj(client->client_obj);
702 if (client->ctx_index != GUC_INVALID_CTX_ID) {
703 guc_fini_ctx_desc(guc, client);
704 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
711 * guc_client_alloc() - Allocate an i915_guc_client
713 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
714 * The kernel client to replace ExecList submission is created with
715 * NORMAL priority. Priority of a client for scheduler can be HIGH,
716 * while a preemption context can use CRITICAL.
717 * @ctx: the context that owns the client (we use the default render
720 * Return: An i915_guc_client object if success.
722 static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
724 struct intel_context *ctx)
726 struct i915_guc_client *client;
727 struct drm_i915_private *dev_priv = dev->dev_private;
728 struct intel_guc *guc = &dev_priv->guc;
729 struct drm_i915_gem_object *obj;
731 client = kzalloc(sizeof(*client), GFP_KERNEL);
735 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
736 client->priority = priority;
740 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
741 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
742 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
743 client->ctx_index = GUC_INVALID_CTX_ID;
747 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
748 obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE);
752 client->client_obj = obj;
753 client->wq_offset = GUC_DB_SIZE;
754 client->wq_size = GUC_WQ_SIZE;
756 client->doorbell_offset = select_doorbell_cacheline(guc);
759 * Since the doorbell only requires a single cacheline, we can save
760 * space by putting the application process descriptor in the same
761 * page. Use the half of the page that doesn't include the doorbell.
763 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
764 client->proc_desc_offset = 0;
766 client->proc_desc_offset = (GUC_DB_SIZE / 2);
768 client->doorbell_id = assign_doorbell(guc, client->priority);
769 if (client->doorbell_id == GUC_INVALID_DOORBELL_ID)
770 /* XXX: evict a doorbell instead */
773 guc_init_proc_desc(guc, client);
774 guc_init_ctx_desc(guc, client);
775 guc_init_doorbell(guc, client);
777 /* XXX: Any cache flushes needed? General domain mgmt calls? */
779 if (host2guc_allocate_doorbell(guc, client))
782 DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
783 priority, client, client->ctx_index, client->doorbell_id);
788 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
790 guc_client_free(dev, client);
794 static void guc_create_log(struct intel_guc *guc)
796 struct drm_i915_private *dev_priv = guc_to_i915(guc);
797 struct drm_i915_gem_object *obj;
798 unsigned long offset;
799 uint32_t size, flags;
801 if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
804 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
805 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
807 /* The first page is to save log buffer state. Allocate one
808 * extra page for others in case for overlap */
809 size = (1 + GUC_LOG_DPC_PAGES + 1 +
810 GUC_LOG_ISR_PAGES + 1 +
811 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
815 obj = gem_allocate_guc_obj(dev_priv->dev, size);
817 /* logging will be off */
818 i915.guc_log_level = -1;
825 /* each allocated unit is a page */
826 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
827 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
828 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
829 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
831 offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
832 guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
836 * Set up the memory resources to be shared with the GuC. At this point,
837 * we require just one object that can be mapped through the GGTT.
839 int i915_guc_submission_init(struct drm_device *dev)
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 const size_t ctxsize = sizeof(struct guc_context_desc);
843 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
844 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
845 struct intel_guc *guc = &dev_priv->guc;
847 if (!i915.enable_guc_submission)
848 return 0; /* not enabled */
850 if (guc->ctx_pool_obj)
851 return 0; /* already allocated */
853 guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize);
854 if (!guc->ctx_pool_obj)
857 ida_init(&guc->ctx_ids);
864 int i915_guc_submission_enable(struct drm_device *dev)
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 struct intel_guc *guc = &dev_priv->guc;
868 struct intel_context *ctx = dev_priv->ring[RCS].default_context;
869 struct i915_guc_client *client;
871 /* client for execbuf submission */
872 client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx);
874 DRM_ERROR("Failed to create execbuf guc_client\n");
878 guc->execbuf_client = client;
880 host2guc_sample_forcewake(guc, client);
885 void i915_guc_submission_disable(struct drm_device *dev)
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 struct intel_guc *guc = &dev_priv->guc;
890 guc_client_free(dev, guc->execbuf_client);
891 guc->execbuf_client = NULL;
894 void i915_guc_submission_fini(struct drm_device *dev)
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 struct intel_guc *guc = &dev_priv->guc;
899 gem_release_guc_obj(dev_priv->guc.log_obj);
902 if (guc->ctx_pool_obj)
903 ida_destroy(&guc->ctx_ids);
904 gem_release_guc_obj(guc->ctx_pool_obj);
905 guc->ctx_pool_obj = NULL;
909 * intel_guc_suspend() - notify GuC entering suspend state
912 int intel_guc_suspend(struct drm_device *dev)
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 struct intel_guc *guc = &dev_priv->guc;
916 struct intel_context *ctx;
919 if (!i915.enable_guc_submission)
922 ctx = dev_priv->ring[RCS].default_context;
924 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
925 /* any value greater than GUC_POWER_D0 */
926 data[1] = GUC_POWER_D1;
927 /* first page is shared data with GuC */
928 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
930 return host2guc_action(guc, data, ARRAY_SIZE(data));
935 * intel_guc_resume() - notify GuC resuming from suspend state
938 int intel_guc_resume(struct drm_device *dev)
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 struct intel_guc *guc = &dev_priv->guc;
942 struct intel_context *ctx;
945 if (!i915.enable_guc_submission)
948 ctx = dev_priv->ring[RCS].default_context;
950 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
951 data[1] = GUC_POWER_D0;
952 /* first page is shared data with GuC */
953 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
955 return host2guc_action(guc, data, ARRAY_SIZE(data));