2 * Copyright © 2014 Intel Corporation
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24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
26 #include <linux/debugfs.h>
27 #include <linux/relay.h>
32 * DOC: GuC-based command submission
35 * We use the term client to avoid confusion with contexts. A i915_guc_client is
36 * equivalent to GuC object guc_context_desc. This context descriptor is
37 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
38 * and workqueue for it. Also the process descriptor (guc_process_desc), which
39 * is mapped to client space. So the client can write Work Item then ring the
42 * To simplify the implementation, we allocate one gem object that contains all
43 * pages for doorbell, process descriptor and workqueue.
45 * The Scratch registers:
46 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
47 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
48 * triggers an interrupt on the GuC via another register write (0xC4C8).
49 * Firmware writes a success/fail code back to the action register after
50 * processes the request. The kernel driver polls waiting for this update and
52 * See intel_guc_send()
55 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
56 * mapped into process space.
59 * There are several types of work items that the host may place into a
60 * workqueue, each with its own requirements and limitations. Currently only
61 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
62 * represents in-order queue. The kernel driver packs ring tail pointer and an
63 * ELSP context descriptor dword into Work Item.
64 * See guc_wq_item_append()
69 * Tell the GuC to allocate or deallocate a specific doorbell
72 static int guc_allocate_doorbell(struct intel_guc *guc,
73 struct i915_guc_client *client)
76 INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
80 return intel_guc_send(guc, action, ARRAY_SIZE(action));
83 static int guc_release_doorbell(struct intel_guc *guc,
84 struct i915_guc_client *client)
87 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
91 return intel_guc_send(guc, action, ARRAY_SIZE(action));
95 * Initialise, update, or clear doorbell data shared with the GuC
97 * These functions modify shared data and so need access to the mapped
98 * client object which contains the page being used for the doorbell
101 static int guc_update_doorbell_id(struct intel_guc *guc,
102 struct i915_guc_client *client,
105 struct sg_table *sg = guc->ctx_pool_vma->pages;
106 void *doorbell_bitmap = guc->doorbell_bitmap;
107 struct guc_doorbell_info *doorbell;
108 struct guc_context_desc desc;
111 doorbell = client->vaddr + client->doorbell_offset;
113 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
114 test_bit(client->doorbell_id, doorbell_bitmap)) {
115 /* Deactivate the old doorbell */
116 doorbell->db_status = GUC_DOORBELL_DISABLED;
117 (void)guc_release_doorbell(guc, client);
118 __clear_bit(client->doorbell_id, doorbell_bitmap);
121 /* Update the GuC's idea of the doorbell ID */
122 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
123 sizeof(desc) * client->ctx_index);
124 if (len != sizeof(desc))
127 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
128 sizeof(desc) * client->ctx_index);
129 if (len != sizeof(desc))
132 client->doorbell_id = new_id;
133 if (new_id == GUC_INVALID_DOORBELL_ID)
136 /* Activate the new doorbell */
137 __set_bit(new_id, doorbell_bitmap);
138 doorbell->cookie = 0;
139 doorbell->db_status = GUC_DOORBELL_ENABLED;
140 return guc_allocate_doorbell(guc, client);
143 static int guc_init_doorbell(struct intel_guc *guc,
144 struct i915_guc_client *client,
147 return guc_update_doorbell_id(guc, client, db_id);
150 static void guc_disable_doorbell(struct intel_guc *guc,
151 struct i915_guc_client *client)
153 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
155 /* XXX: wait for any interrupts */
156 /* XXX: wait for workqueue to drain */
160 select_doorbell_register(struct intel_guc *guc, uint32_t priority)
163 * The bitmap tracks which doorbell registers are currently in use.
164 * It is split into two halves; the first half is used for normal
165 * priority contexts, the second half for high-priority ones.
166 * Note that logically higher priorities are numerically less than
167 * normal ones, so the test below means "is it high-priority?"
169 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
170 const uint16_t half = GUC_MAX_DOORBELLS / 2;
171 const uint16_t start = hi_pri ? half : 0;
172 const uint16_t end = start + half;
175 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
177 id = GUC_INVALID_DOORBELL_ID;
179 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
180 hi_pri ? "high" : "normal", id);
186 * Select, assign and relase doorbell cachelines
188 * These functions track which doorbell cachelines are in use.
189 * The data they manipulate is protected by the intel_guc_send lock.
192 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
194 const uint32_t cacheline_size = cache_line_size();
197 /* Doorbell uses a single cache line within a page */
198 offset = offset_in_page(guc->db_cacheline);
200 /* Moving to next cache line to reduce contention */
201 guc->db_cacheline += cacheline_size;
203 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
204 offset, guc->db_cacheline, cacheline_size);
210 * Initialise the process descriptor shared with the GuC firmware.
212 static void guc_proc_desc_init(struct intel_guc *guc,
213 struct i915_guc_client *client)
215 struct guc_process_desc *desc;
217 desc = client->vaddr + client->proc_desc_offset;
219 memset(desc, 0, sizeof(*desc));
222 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
223 * space for ring3 clients (set them as in mmap_ioctl) or kernel
224 * space for kernel clients (map on demand instead? May make debug
225 * easier to have it mapped).
227 desc->wq_base_addr = 0;
228 desc->db_base_addr = 0;
230 desc->context_id = client->ctx_index;
231 desc->wq_size_bytes = client->wq_size;
232 desc->wq_status = WQ_STATUS_ACTIVE;
233 desc->priority = client->priority;
237 * Initialise/clear the context descriptor shared with the GuC firmware.
239 * This descriptor tells the GuC where (in GGTT space) to find the important
240 * data structures relating to this client (doorbell, process descriptor,
244 static void guc_ctx_desc_init(struct intel_guc *guc,
245 struct i915_guc_client *client)
247 struct drm_i915_private *dev_priv = guc_to_i915(guc);
248 struct intel_engine_cs *engine;
249 struct i915_gem_context *ctx = client->owner;
250 struct guc_context_desc desc;
255 memset(&desc, 0, sizeof(desc));
257 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
258 desc.context_id = client->ctx_index;
259 desc.priority = client->priority;
260 desc.db_id = client->doorbell_id;
262 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
263 struct intel_context *ce = &ctx->engine[engine->id];
264 uint32_t guc_engine_id = engine->guc_id;
265 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
267 /* TODO: We have a design issue to be solved here. Only when we
268 * receive the first batch, we know which engine is used by the
269 * user. But here GuC expects the lrc and ring to be pinned. It
270 * is not an issue for default context, which is the only one
271 * for now who owns a GuC client. But for future owner of GuC
272 * client, need to make sure lrc is pinned prior to enter here.
275 break; /* XXX: continue? */
277 lrc->context_desc = lower_32_bits(ce->lrc_desc);
279 /* The state page is after PPHWSP */
281 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
282 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
283 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
285 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma);
286 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
287 lrc->ring_next_free_location = lrc->ring_begin;
288 lrc->ring_current_tail_pointer_value = 0;
290 desc.engines_used |= (1 << guc_engine_id);
293 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
294 client->engines, desc.engines_used);
295 WARN_ON(desc.engines_used == 0);
298 * The doorbell, process descriptor, and workqueue are all parts
299 * of the client object, which the GuC will reference via the GGTT
301 gfx_addr = i915_ggtt_offset(client->vma);
302 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
303 client->doorbell_offset;
304 desc.db_trigger_cpu =
305 (uintptr_t)client->vaddr + client->doorbell_offset;
306 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
307 desc.process_desc = gfx_addr + client->proc_desc_offset;
308 desc.wq_addr = gfx_addr + client->wq_offset;
309 desc.wq_size = client->wq_size;
312 * XXX: Take LRCs from an existing context if this is not an
313 * IsKMDCreatedContext client
315 desc.desc_private = (uintptr_t)client;
317 /* Pool context is pinned already */
318 sg = guc->ctx_pool_vma->pages;
319 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
320 sizeof(desc) * client->ctx_index);
323 static void guc_ctx_desc_fini(struct intel_guc *guc,
324 struct i915_guc_client *client)
326 struct guc_context_desc desc;
329 memset(&desc, 0, sizeof(desc));
331 sg = guc->ctx_pool_vma->pages;
332 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
333 sizeof(desc) * client->ctx_index);
337 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
338 * @request: request associated with the commands
340 * Return: 0 if space is available
341 * -EAGAIN if space is not currently available
343 * This function must be called (and must return 0) before a request
344 * is submitted to the GuC via i915_guc_submit() below. Once a result
345 * of 0 has been returned, it must be balanced by a corresponding
348 * Reservation allows the caller to determine in advance that space
349 * will be available for the next submission before committing resources
350 * to it, and helps avoid late failures with complicated recovery paths.
352 int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
354 const size_t wqi_size = sizeof(struct guc_wq_item);
355 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
356 struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset;
360 spin_lock(&gc->wq_lock);
361 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
362 freespace -= gc->wq_rsvd;
363 if (likely(freespace >= wqi_size)) {
364 gc->wq_rsvd += wqi_size;
370 spin_unlock(&gc->wq_lock);
375 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
377 const size_t wqi_size = sizeof(struct guc_wq_item);
378 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
380 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
382 spin_lock(&gc->wq_lock);
383 gc->wq_rsvd -= wqi_size;
384 spin_unlock(&gc->wq_lock);
387 /* Construct a Work Item and append it to the GuC's Work Queue */
388 static void guc_wq_item_append(struct i915_guc_client *gc,
389 struct drm_i915_gem_request *rq)
391 /* wqi_len is in DWords, and does not include the one-word header */
392 const size_t wqi_size = sizeof(struct guc_wq_item);
393 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
394 struct intel_engine_cs *engine = rq->engine;
395 struct guc_process_desc *desc;
396 struct guc_wq_item *wqi;
397 u32 freespace, tail, wq_off;
399 desc = gc->vaddr + gc->proc_desc_offset;
401 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
402 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
403 GEM_BUG_ON(freespace < wqi_size);
405 /* The GuC firmware wants the tail index in QWords, not bytes */
407 GEM_BUG_ON(tail & 7);
409 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
411 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
412 * should not have the case where structure wqi is across page, neither
413 * wrapped to the beginning. This simplifies the implementation below.
415 * XXX: if not the case, we need save data to a temp wqi and copy it to
416 * workqueue buffer dw by dw.
418 BUILD_BUG_ON(wqi_size != 16);
419 GEM_BUG_ON(gc->wq_rsvd < wqi_size);
421 /* postincrement WQ tail for next time */
422 wq_off = gc->wq_tail;
423 GEM_BUG_ON(wq_off & (wqi_size - 1));
424 gc->wq_tail += wqi_size;
425 gc->wq_tail &= gc->wq_size - 1;
426 gc->wq_rsvd -= wqi_size;
428 /* WQ starts from the page after doorbell / process_desc */
429 wqi = gc->vaddr + wq_off + GUC_DB_SIZE;
431 /* Now fill in the 4-word work queue item */
432 wqi->header = WQ_TYPE_INORDER |
433 (wqi_len << WQ_LEN_SHIFT) |
434 (engine->guc_id << WQ_TARGET_SHIFT) |
437 /* The GuC wants only the low-order word of the context descriptor */
438 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
440 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
441 wqi->fence_id = rq->global_seqno;
444 static int guc_ring_doorbell(struct i915_guc_client *gc)
446 struct guc_process_desc *desc;
447 union guc_doorbell_qw db_cmp, db_exc, db_ret;
448 union guc_doorbell_qw *db;
449 int attempt = 2, ret = -EAGAIN;
451 desc = gc->vaddr + gc->proc_desc_offset;
453 /* Update the tail so it is visible to GuC */
454 desc->tail = gc->wq_tail;
457 db_cmp.db_status = GUC_DOORBELL_ENABLED;
458 db_cmp.cookie = gc->cookie;
460 /* cookie to be updated */
461 db_exc.db_status = GUC_DOORBELL_ENABLED;
462 db_exc.cookie = gc->cookie + 1;
463 if (db_exc.cookie == 0)
466 /* pointer of current doorbell cacheline */
467 db = gc->vaddr + gc->doorbell_offset;
470 /* lets ring the doorbell */
471 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
472 db_cmp.value_qw, db_exc.value_qw);
474 /* if the exchange was successfully executed */
475 if (db_ret.value_qw == db_cmp.value_qw) {
476 /* db was successfully rung */
477 gc->cookie = db_exc.cookie;
482 /* XXX: doorbell was lost and need to acquire it again */
483 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
486 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
487 db_cmp.cookie, db_ret.cookie);
489 /* update the cookie to newly read cookie from GuC */
490 db_cmp.cookie = db_ret.cookie;
491 db_exc.cookie = db_ret.cookie + 1;
492 if (db_exc.cookie == 0)
500 * i915_guc_submit() - Submit commands through GuC
501 * @rq: request associated with the commands
503 * Return: 0 on success, otherwise an errno.
504 * (Note: nonzero really shouldn't happen!)
506 * The caller must have already called i915_guc_wq_reserve() above with
507 * a result of 0 (success), guaranteeing that there is space in the work
508 * queue for the new request, so enqueuing the item cannot fail.
510 * Bad Things Will Happen if the caller violates this protocol e.g. calls
511 * submit() when _reserve() says there's no space, or calls _submit()
512 * a different number of times from (successful) calls to _reserve().
514 * The only error here arises if the doorbell hardware isn't functioning
515 * as expected, which really shouln't happen.
517 static void i915_guc_submit(struct drm_i915_gem_request *rq)
519 struct drm_i915_private *dev_priv = rq->i915;
520 struct intel_engine_cs *engine = rq->engine;
521 unsigned int engine_id = engine->id;
522 struct intel_guc *guc = &rq->i915->guc;
523 struct i915_guc_client *client = guc->execbuf_client;
526 /* We keep the previous context alive until we retire the following
527 * request. This ensures that any the context object is still pinned
528 * for any residual writes the HW makes into it on the context switch
529 * into the next object following the breadcrumb. Otherwise, we may
530 * retire the context too early.
532 rq->previous_context = engine->last_context;
533 engine->last_context = rq->ctx;
535 i915_gem_request_submit(rq);
537 spin_lock(&client->wq_lock);
538 guc_wq_item_append(client, rq);
540 /* WA to flush out the pending GMADR writes to ring buffer. */
541 if (i915_vma_is_map_and_fenceable(rq->ring->vma))
542 POSTING_READ_FW(GUC_STATUS);
544 b_ret = guc_ring_doorbell(client);
546 client->submissions[engine_id] += 1;
547 client->retcode = b_ret;
551 guc->submissions[engine_id] += 1;
552 guc->last_seqno[engine_id] = rq->global_seqno;
553 spin_unlock(&client->wq_lock);
557 * Everything below here is concerned with setup & teardown, and is
558 * therefore not part of the somewhat time-critical batch-submission
559 * path of i915_guc_submit() above.
563 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
565 * @size: size of area to allocate (both virtual space and memory)
567 * This is a wrapper to create an object for use with the GuC. In order to
568 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
569 * both some backing storage and a range inside the Global GTT. We must pin
570 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
571 * range is reserved inside GuC.
573 * Return: A i915_vma if successful, otherwise an ERR_PTR.
575 static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
577 struct drm_i915_private *dev_priv = guc_to_i915(guc);
578 struct drm_i915_gem_object *obj;
579 struct i915_vma *vma;
582 obj = i915_gem_object_create(&dev_priv->drm, size);
584 return ERR_CAST(obj);
586 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
590 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
591 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
597 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
598 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
603 i915_gem_object_put(obj);
608 guc_client_free(struct drm_i915_private *dev_priv,
609 struct i915_guc_client *client)
611 struct intel_guc *guc = &dev_priv->guc;
617 * XXX: wait for any outstanding submissions before freeing memory.
618 * Be sure to drop any locks
623 * If we got as far as setting up a doorbell, make sure we
624 * shut it down before unmapping & deallocating the memory.
626 guc_disable_doorbell(guc, client);
628 i915_gem_object_unpin_map(client->vma->obj);
631 i915_vma_unpin_and_release(&client->vma);
633 if (client->ctx_index != GUC_INVALID_CTX_ID) {
634 guc_ctx_desc_fini(guc, client);
635 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
641 /* Check that a doorbell register is in the expected state */
642 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
644 struct drm_i915_private *dev_priv = guc_to_i915(guc);
645 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
646 uint32_t value = I915_READ(drbreg);
647 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
648 bool expected = test_bit(db_id, guc->doorbell_bitmap);
650 if (enabled == expected)
653 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
654 db_id, drbreg.reg, value,
655 expected ? "active" : "inactive");
661 * Borrow the first client to set up & tear down each unused doorbell
662 * in turn, to ensure that all doorbell h/w is (re)initialised.
664 static void guc_init_doorbell_hw(struct intel_guc *guc)
666 struct i915_guc_client *client = guc->execbuf_client;
670 /* Save client's original doorbell selection */
671 db_id = client->doorbell_id;
673 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
674 /* Skip if doorbell is OK */
675 if (guc_doorbell_check(guc, i))
678 err = guc_update_doorbell_id(guc, client, i);
680 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
684 /* Restore to original value */
685 err = guc_update_doorbell_id(guc, client, db_id);
687 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
690 /* Read back & verify all doorbell registers */
691 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
692 (void)guc_doorbell_check(guc, i);
696 * guc_client_alloc() - Allocate an i915_guc_client
697 * @dev_priv: driver private data structure
698 * @engines: The set of engines to enable for this client
699 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
700 * The kernel client to replace ExecList submission is created with
701 * NORMAL priority. Priority of a client for scheduler can be HIGH,
702 * while a preemption context can use CRITICAL.
703 * @ctx: the context that owns the client (we use the default render
706 * Return: An i915_guc_client object if success, else NULL.
708 static struct i915_guc_client *
709 guc_client_alloc(struct drm_i915_private *dev_priv,
712 struct i915_gem_context *ctx)
714 struct i915_guc_client *client;
715 struct intel_guc *guc = &dev_priv->guc;
716 struct i915_vma *vma;
720 client = kzalloc(sizeof(*client), GFP_KERNEL);
726 client->engines = engines;
727 client->priority = priority;
728 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
730 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
731 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
732 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
733 client->ctx_index = GUC_INVALID_CTX_ID;
737 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
738 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
742 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
745 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
749 client->vaddr = vaddr;
751 spin_lock_init(&client->wq_lock);
752 client->wq_offset = GUC_DB_SIZE;
753 client->wq_size = GUC_WQ_SIZE;
755 db_id = select_doorbell_register(guc, client->priority);
756 if (db_id == GUC_INVALID_DOORBELL_ID)
757 /* XXX: evict a doorbell instead? */
760 client->doorbell_offset = select_doorbell_cacheline(guc);
763 * Since the doorbell only requires a single cacheline, we can save
764 * space by putting the application process descriptor in the same
765 * page. Use the half of the page that doesn't include the doorbell.
767 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
768 client->proc_desc_offset = 0;
770 client->proc_desc_offset = (GUC_DB_SIZE / 2);
772 guc_proc_desc_init(guc, client);
773 guc_ctx_desc_init(guc, client);
774 if (guc_init_doorbell(guc, client, db_id))
777 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
778 priority, client, client->engines, client->ctx_index);
779 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
780 client->doorbell_id, client->doorbell_offset);
785 guc_client_free(dev_priv, client);
790 * Sub buffer switch callback. Called whenever relay has to switch to a new
791 * sub buffer, relay stays on the same sub buffer if 0 is returned.
793 static int subbuf_start_callback(struct rchan_buf *buf,
798 /* Use no-overwrite mode by default, where relay will stop accepting
799 * new data if there are no empty sub buffers left.
800 * There is no strict synchronization enforced by relay between Consumer
801 * and Producer. In overwrite mode, there is a possibility of getting
802 * inconsistent/garbled data, the producer could be writing on to the
803 * same sub buffer from which Consumer is reading. This can't be avoided
804 * unless Consumer is fast enough and can always run in tandem with
807 if (relay_buf_full(buf))
814 * file_create() callback. Creates relay file in debugfs.
816 static struct dentry *create_buf_file_callback(const char *filename,
817 struct dentry *parent,
819 struct rchan_buf *buf,
822 struct dentry *buf_file;
824 /* This to enable the use of a single buffer for the relay channel and
825 * correspondingly have a single file exposed to User, through which
826 * it can collect the logs in order without any post-processing.
827 * Need to set 'is_global' even if parent is NULL for early logging.
834 /* Not using the channel filename passed as an argument, since for each
835 * channel relay appends the corresponding CPU number to the filename
836 * passed in relay_open(). This should be fine as relay just needs a
837 * dentry of the file associated with the channel buffer and that file's
838 * name need not be same as the filename passed as an argument.
840 buf_file = debugfs_create_file("guc_log", mode,
841 parent, buf, &relay_file_operations);
846 * file_remove() default callback. Removes relay file in debugfs.
848 static int remove_buf_file_callback(struct dentry *dentry)
850 debugfs_remove(dentry);
854 /* relay channel callbacks */
855 static struct rchan_callbacks relay_callbacks = {
856 .subbuf_start = subbuf_start_callback,
857 .create_buf_file = create_buf_file_callback,
858 .remove_buf_file = remove_buf_file_callback,
861 static void guc_log_remove_relay_file(struct intel_guc *guc)
863 relay_close(guc->log.relay_chan);
866 static int guc_log_create_relay_channel(struct intel_guc *guc)
868 struct drm_i915_private *dev_priv = guc_to_i915(guc);
869 struct rchan *guc_log_relay_chan;
870 size_t n_subbufs, subbuf_size;
872 /* Keep the size of sub buffers same as shared log buffer */
873 subbuf_size = guc->log.vma->obj->base.size;
875 /* Store up to 8 snapshots, which is large enough to buffer sufficient
876 * boot time logs and provides enough leeway to User, in terms of
877 * latency, for consuming the logs from relay. Also doesn't take
878 * up too much memory.
882 guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
883 n_subbufs, &relay_callbacks, dev_priv);
884 if (!guc_log_relay_chan) {
885 DRM_ERROR("Couldn't create relay chan for GuC logging\n");
889 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
890 guc->log.relay_chan = guc_log_relay_chan;
894 static int guc_log_create_relay_file(struct intel_guc *guc)
896 struct drm_i915_private *dev_priv = guc_to_i915(guc);
897 struct dentry *log_dir;
900 /* For now create the log file in /sys/kernel/debug/dri/0 dir */
901 log_dir = dev_priv->drm.primary->debugfs_root;
903 /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
904 * not mounted and so can't create the relay file.
905 * The relay API seems to fit well with debugfs only, for availing relay
906 * there are 3 requirements which can be met for debugfs file only in a
907 * straightforward/clean manner :-
908 * i) Need the associated dentry pointer of the file, while opening the
910 * ii) Should be able to use 'relay_file_operations' fops for the file.
911 * iii) Set the 'i_private' field of file's inode to the pointer of
912 * relay channel buffer.
915 DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
919 ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir);
921 DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
928 static void guc_move_to_next_buf(struct intel_guc *guc)
930 /* Make sure the updates made in the sub buffer are visible when
931 * Consumer sees the following update to offset inside the sub buffer.
935 /* All data has been written, so now move the offset of sub buffer. */
936 relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size);
938 /* Switch to the next sub buffer */
939 relay_flush(guc->log.relay_chan);
942 static void *guc_get_write_buffer(struct intel_guc *guc)
944 if (!guc->log.relay_chan)
947 /* Just get the base address of a new sub buffer and copy data into it
948 * ourselves. NULL will be returned in no-overwrite mode, if all sub
949 * buffers are full. Could have used the relay_write() to indirectly
950 * copy the data, but that would have been bit convoluted, as we need to
951 * write to only certain locations inside a sub buffer which cannot be
952 * done without using relay_reserve() along with relay_write(). So its
953 * better to use relay_reserve() alone.
955 return relay_reserve(guc->log.relay_chan, 0);
959 guc_check_log_buf_overflow(struct intel_guc *guc,
960 enum guc_log_buffer_type type, unsigned int full_cnt)
962 unsigned int prev_full_cnt = guc->log.prev_overflow_count[type];
963 bool overflow = false;
965 if (full_cnt != prev_full_cnt) {
968 guc->log.prev_overflow_count[type] = full_cnt;
969 guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt;
971 if (full_cnt < prev_full_cnt) {
972 /* buffer_full_cnt is a 4 bit counter */
973 guc->log.total_overflow_count[type] += 16;
975 DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
981 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
984 case GUC_ISR_LOG_BUFFER:
985 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
986 case GUC_DPC_LOG_BUFFER:
987 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
988 case GUC_CRASH_DUMP_LOG_BUFFER:
989 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
997 static void guc_read_update_log_buffer(struct intel_guc *guc)
999 unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
1000 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
1001 struct guc_log_buffer_state log_buf_state_local;
1002 enum guc_log_buffer_type type;
1003 void *src_data, *dst_data;
1006 if (WARN_ON(!guc->log.buf_addr))
1009 /* Get the pointer to shared GuC log buffer */
1010 log_buf_state = src_data = guc->log.buf_addr;
1012 /* Get the pointer to local buffer to store the logs */
1013 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
1015 /* Actual logs are present from the 2nd page */
1016 src_data += PAGE_SIZE;
1017 dst_data += PAGE_SIZE;
1019 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
1020 /* Make a copy of the state structure, inside GuC log buffer
1021 * (which is uncached mapped), on the stack to avoid reading
1022 * from it multiple times.
1024 memcpy(&log_buf_state_local, log_buf_state,
1025 sizeof(struct guc_log_buffer_state));
1026 buffer_size = guc_get_log_buffer_size(type);
1027 read_offset = log_buf_state_local.read_ptr;
1028 write_offset = log_buf_state_local.sampled_write_ptr;
1029 full_cnt = log_buf_state_local.buffer_full_cnt;
1031 /* Bookkeeping stuff */
1032 guc->log.flush_count[type] += log_buf_state_local.flush_to_file;
1033 new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt);
1035 /* Update the state of shared log buffer */
1036 log_buf_state->read_ptr = write_offset;
1037 log_buf_state->flush_to_file = 0;
1040 if (unlikely(!log_buf_snapshot_state))
1043 /* First copy the state structure in snapshot buffer */
1044 memcpy(log_buf_snapshot_state, &log_buf_state_local,
1045 sizeof(struct guc_log_buffer_state));
1047 /* The write pointer could have been updated by GuC firmware,
1048 * after sending the flush interrupt to Host, for consistency
1049 * set write pointer value to same value of sampled_write_ptr
1050 * in the snapshot buffer.
1052 log_buf_snapshot_state->write_ptr = write_offset;
1053 log_buf_snapshot_state++;
1055 /* Now copy the actual logs. */
1056 if (unlikely(new_overflow)) {
1057 /* copy the whole buffer in case of overflow */
1059 write_offset = buffer_size;
1060 } else if (unlikely((read_offset > buffer_size) ||
1061 (write_offset > buffer_size))) {
1062 DRM_ERROR("invalid log buffer state\n");
1063 /* copy whole buffer as offsets are unreliable */
1065 write_offset = buffer_size;
1068 /* Just copy the newly written data */
1069 if (read_offset > write_offset) {
1070 i915_memcpy_from_wc(dst_data, src_data, write_offset);
1071 bytes_to_copy = buffer_size - read_offset;
1073 bytes_to_copy = write_offset - read_offset;
1075 i915_memcpy_from_wc(dst_data + read_offset,
1076 src_data + read_offset, bytes_to_copy);
1078 src_data += buffer_size;
1079 dst_data += buffer_size;
1082 if (log_buf_snapshot_state)
1083 guc_move_to_next_buf(guc);
1085 /* Used rate limited to avoid deluge of messages, logs might be
1086 * getting consumed by User at a slow rate.
1088 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
1089 guc->log.capture_miss_count++;
1093 static void guc_capture_logs_work(struct work_struct *work)
1095 struct drm_i915_private *dev_priv =
1096 container_of(work, struct drm_i915_private, guc.log.flush_work);
1098 i915_guc_capture_logs(dev_priv);
1101 static void guc_log_cleanup(struct intel_guc *guc)
1103 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1105 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1107 /* First disable the flush interrupt */
1108 gen9_disable_guc_interrupts(dev_priv);
1110 if (guc->log.flush_wq)
1111 destroy_workqueue(guc->log.flush_wq);
1113 guc->log.flush_wq = NULL;
1115 if (guc->log.relay_chan)
1116 guc_log_remove_relay_file(guc);
1118 guc->log.relay_chan = NULL;
1120 if (guc->log.buf_addr)
1121 i915_gem_object_unpin_map(guc->log.vma->obj);
1123 guc->log.buf_addr = NULL;
1126 static int guc_log_create_extras(struct intel_guc *guc)
1128 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1132 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1135 if (i915.guc_log_level < 0)
1138 if (!guc->log.buf_addr) {
1139 /* Create a WC (Uncached for read) vmalloc mapping of log
1140 * buffer pages, so that we can directly get the data
1141 * (up-to-date) from memory.
1143 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC);
1144 if (IS_ERR(vaddr)) {
1145 ret = PTR_ERR(vaddr);
1146 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
1150 guc->log.buf_addr = vaddr;
1153 if (!guc->log.relay_chan) {
1154 /* Create a relay channel, so that we have buffers for storing
1155 * the GuC firmware logs, the channel will be linked with a file
1156 * later on when debugfs is registered.
1158 ret = guc_log_create_relay_channel(guc);
1163 if (!guc->log.flush_wq) {
1164 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
1167 * GuC log buffer flush work item has to do register access to
1168 * send the ack to GuC and this work item, if not synced before
1169 * suspend, can potentially get executed after the GFX device is
1171 * By marking the WQ as freezable, we don't have to bother about
1172 * flushing of this work item from the suspend hooks, the pending
1173 * work item if any will be either executed before the suspend
1174 * or scheduled later on resume. This way the handling of work
1175 * item can be kept same between system suspend & rpm suspend.
1177 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
1178 WQ_HIGHPRI | WQ_FREEZABLE);
1179 if (guc->log.flush_wq == NULL) {
1180 DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
1188 static void guc_log_create(struct intel_guc *guc)
1190 struct i915_vma *vma;
1191 unsigned long offset;
1192 uint32_t size, flags;
1194 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
1195 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
1197 /* The first page is to save log buffer state. Allocate one
1198 * extra page for others in case for overlap */
1199 size = (1 + GUC_LOG_DPC_PAGES + 1 +
1200 GUC_LOG_ISR_PAGES + 1 +
1201 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
1205 /* We require SSE 4.1 for fast reads from the GuC log buffer and
1206 * it should be present on the chipsets supporting GuC based
1209 if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) {
1210 /* logging will not be enabled */
1211 i915.guc_log_level = -1;
1215 vma = guc_allocate_vma(guc, size);
1217 /* logging will be off */
1218 i915.guc_log_level = -1;
1224 if (guc_log_create_extras(guc)) {
1225 guc_log_cleanup(guc);
1226 i915_vma_unpin_and_release(&guc->log.vma);
1227 i915.guc_log_level = -1;
1232 /* each allocated unit is a page */
1233 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
1234 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
1235 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
1236 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
1238 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
1239 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
1242 static int guc_log_late_setup(struct intel_guc *guc)
1244 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1247 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1249 if (i915.guc_log_level < 0)
1252 /* If log_level was set as -1 at boot time, then setup needed to
1253 * handle log buffer flush interrupts would not have been done yet,
1256 ret = guc_log_create_extras(guc);
1260 ret = guc_log_create_relay_file(guc);
1266 guc_log_cleanup(guc);
1267 /* logging will remain off */
1268 i915.guc_log_level = -1;
1272 static void guc_policies_init(struct guc_policies *policies)
1274 struct guc_policy *policy;
1277 policies->dpc_promote_time = 500000;
1278 policies->max_num_work_items = POLICY_MAX_NUM_WI;
1280 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
1281 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
1282 policy = &policies->policy[p][i];
1284 policy->execution_quantum = 1000000;
1285 policy->preemption_time = 500000;
1286 policy->fault_time = 250000;
1287 policy->policy_flags = 0;
1291 policies->is_valid = 1;
1294 static void guc_addon_create(struct intel_guc *guc)
1296 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1297 struct i915_vma *vma;
1298 struct guc_ads *ads;
1299 struct guc_policies *policies;
1300 struct guc_mmio_reg_state *reg_state;
1301 struct intel_engine_cs *engine;
1302 enum intel_engine_id id;
1306 /* The ads obj includes the struct itself and buffers passed to GuC */
1307 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
1308 sizeof(struct guc_mmio_reg_state) +
1309 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
1313 vma = guc_allocate_vma(guc, PAGE_ALIGN(size));
1320 page = i915_vma_first_page(vma);
1324 * The GuC requires a "Golden Context" when it reinitialises
1325 * engines after a reset. Here we use the Render ring default
1326 * context, which must already exist and be pinned in the GGTT,
1327 * so its address won't change after we've told the GuC where
1330 engine = dev_priv->engine[RCS];
1331 ads->golden_context_lrca = engine->status_page.ggtt_offset;
1333 for_each_engine(engine, dev_priv, id)
1334 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
1336 /* GuC scheduling policies */
1337 policies = (void *)ads + sizeof(struct guc_ads);
1338 guc_policies_init(policies);
1340 ads->scheduler_policies =
1341 i915_ggtt_offset(vma) + sizeof(struct guc_ads);
1343 /* MMIO reg state */
1344 reg_state = (void *)policies + sizeof(struct guc_policies);
1346 for_each_engine(engine, dev_priv, id) {
1347 reg_state->mmio_white_list[engine->guc_id].mmio_start =
1348 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
1350 /* Nothing to be saved or restored for now. */
1351 reg_state->mmio_white_list[engine->guc_id].count = 0;
1354 ads->reg_state_addr = ads->scheduler_policies +
1355 sizeof(struct guc_policies);
1357 ads->reg_state_buffer = ads->reg_state_addr +
1358 sizeof(struct guc_mmio_reg_state);
1364 * Set up the memory resources to be shared with the GuC. At this point,
1365 * we require just one object that can be mapped through the GGTT.
1367 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
1369 const size_t ctxsize = sizeof(struct guc_context_desc);
1370 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
1371 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
1372 struct intel_guc *guc = &dev_priv->guc;
1373 struct i915_vma *vma;
1375 /* Wipe bitmap & delete client in case of reinitialisation */
1376 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
1377 i915_guc_submission_disable(dev_priv);
1379 if (!i915.enable_guc_submission)
1380 return 0; /* not enabled */
1382 if (guc->ctx_pool_vma)
1383 return 0; /* already allocated */
1385 vma = guc_allocate_vma(guc, gemsize);
1387 return PTR_ERR(vma);
1389 guc->ctx_pool_vma = vma;
1390 ida_init(&guc->ctx_ids);
1391 guc_log_create(guc);
1392 guc_addon_create(guc);
1397 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1399 struct intel_guc *guc = &dev_priv->guc;
1400 struct drm_i915_gem_request *request;
1401 struct i915_guc_client *client;
1402 struct intel_engine_cs *engine;
1403 enum intel_engine_id id;
1405 /* client for execbuf submission */
1406 client = guc_client_alloc(dev_priv,
1407 INTEL_INFO(dev_priv)->ring_mask,
1408 GUC_CTX_PRIORITY_KMD_NORMAL,
1409 dev_priv->kernel_context);
1411 DRM_ERROR("Failed to create normal GuC client!\n");
1415 guc->execbuf_client = client;
1416 intel_guc_sample_forcewake(guc);
1417 guc_init_doorbell_hw(guc);
1419 /* Take over from manual control of ELSP (execlists) */
1420 for_each_engine(engine, dev_priv, id) {
1421 engine->submit_request = i915_guc_submit;
1422 engine->schedule = NULL;
1424 /* Replay the current set of previously submitted requests */
1425 list_for_each_entry(request,
1426 &engine->timeline->requests, link) {
1427 client->wq_rsvd += sizeof(struct guc_wq_item);
1428 if (i915_sw_fence_done(&request->submit))
1429 i915_guc_submit(request);
1436 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1438 struct intel_guc *guc = &dev_priv->guc;
1440 if (!guc->execbuf_client)
1443 /* Revert back to manual ELSP submission */
1444 intel_execlists_enable_submission(dev_priv);
1446 guc_client_free(dev_priv, guc->execbuf_client);
1447 guc->execbuf_client = NULL;
1450 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1452 struct intel_guc *guc = &dev_priv->guc;
1454 i915_vma_unpin_and_release(&guc->ads_vma);
1455 i915_vma_unpin_and_release(&guc->log.vma);
1457 if (guc->ctx_pool_vma)
1458 ida_destroy(&guc->ctx_ids);
1459 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
1463 * intel_guc_suspend() - notify GuC entering suspend state
1466 int intel_guc_suspend(struct drm_device *dev)
1468 struct drm_i915_private *dev_priv = to_i915(dev);
1469 struct intel_guc *guc = &dev_priv->guc;
1470 struct i915_gem_context *ctx;
1473 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1476 gen9_disable_guc_interrupts(dev_priv);
1478 ctx = dev_priv->kernel_context;
1480 data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
1481 /* any value greater than GUC_POWER_D0 */
1482 data[1] = GUC_POWER_D1;
1483 /* first page is shared data with GuC */
1484 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1486 return intel_guc_send(guc, data, ARRAY_SIZE(data));
1491 * intel_guc_resume() - notify GuC resuming from suspend state
1494 int intel_guc_resume(struct drm_device *dev)
1496 struct drm_i915_private *dev_priv = to_i915(dev);
1497 struct intel_guc *guc = &dev_priv->guc;
1498 struct i915_gem_context *ctx;
1501 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1504 if (i915.guc_log_level >= 0)
1505 gen9_enable_guc_interrupts(dev_priv);
1507 ctx = dev_priv->kernel_context;
1509 data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
1510 data[1] = GUC_POWER_D0;
1511 /* first page is shared data with GuC */
1512 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1514 return intel_guc_send(guc, data, ARRAY_SIZE(data));
1517 void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
1519 guc_read_update_log_buffer(&dev_priv->guc);
1521 /* Generally device is expected to be active only at this
1522 * time, so get/put should be really quick.
1524 intel_runtime_pm_get(dev_priv);
1525 intel_guc_log_flush_complete(&dev_priv->guc);
1526 intel_runtime_pm_put(dev_priv);
1529 void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
1531 if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
1534 /* First disable the interrupts, will be renabled afterwards */
1535 gen9_disable_guc_interrupts(dev_priv);
1537 /* Before initiating the forceful flush, wait for any pending/ongoing
1538 * flush to complete otherwise forceful flush may not actually happen.
1540 flush_work(&dev_priv->guc.log.flush_work);
1542 /* Ask GuC to update the log buffer state */
1543 intel_guc_log_flush(&dev_priv->guc);
1545 /* GuC would have updated log buffer by now, so capture it */
1546 i915_guc_capture_logs(dev_priv);
1549 void i915_guc_unregister(struct drm_i915_private *dev_priv)
1551 if (!i915.enable_guc_submission)
1554 mutex_lock(&dev_priv->drm.struct_mutex);
1555 guc_log_cleanup(&dev_priv->guc);
1556 mutex_unlock(&dev_priv->drm.struct_mutex);
1559 void i915_guc_register(struct drm_i915_private *dev_priv)
1561 if (!i915.enable_guc_submission)
1564 mutex_lock(&dev_priv->drm.struct_mutex);
1565 guc_log_late_setup(&dev_priv->guc);
1566 mutex_unlock(&dev_priv->drm.struct_mutex);
1569 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
1571 union guc_log_control log_param;
1574 log_param.value = control_val;
1576 if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN ||
1577 log_param.verbosity > GUC_LOG_VERBOSITY_MAX)
1580 /* This combination doesn't make sense & won't have any effect */
1581 if (!log_param.logging_enabled && (i915.guc_log_level < 0))
1584 ret = intel_guc_log_control(&dev_priv->guc, log_param.value);
1586 DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
1590 i915.guc_log_level = log_param.verbosity;
1592 /* If log_level was set as -1 at boot time, then the relay channel file
1593 * wouldn't have been created by now and interrupts also would not have
1596 if (!dev_priv->guc.log.relay_chan) {
1597 ret = guc_log_late_setup(&dev_priv->guc);
1599 gen9_enable_guc_interrupts(dev_priv);
1600 } else if (!log_param.logging_enabled) {
1601 /* Once logging is disabled, GuC won't generate logs & send an
1602 * interrupt. But there could be some data in the log buffer
1603 * which is yet to be captured. So request GuC to update the log
1604 * buffer state and then collect the left over logs.
1606 i915_guc_flush_logs(dev_priv);
1608 /* As logging is disabled, update log level to reflect that */
1609 i915.guc_log_level = -1;
1611 /* In case interrupts were disabled, enable them now */
1612 gen9_enable_guc_interrupts(dev_priv);