2 * Copyright © 2014 Intel Corporation
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
26 #include <linux/debugfs.h>
27 #include <linux/relay.h>
29 #include "intel_guc.h"
32 * DOC: GuC-based command submission
35 * We use the term client to avoid confusion with contexts. A i915_guc_client is
36 * equivalent to GuC object guc_context_desc. This context descriptor is
37 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
38 * and workqueue for it. Also the process descriptor (guc_process_desc), which
39 * is mapped to client space. So the client can write Work Item then ring the
42 * To simplify the implementation, we allocate one gem object that contains all
43 * pages for doorbell, process descriptor and workqueue.
45 * The Scratch registers:
46 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
47 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
48 * triggers an interrupt on the GuC via another register write (0xC4C8).
49 * Firmware writes a success/fail code back to the action register after
50 * processes the request. The kernel driver polls waiting for this update and
52 * See host2guc_action()
55 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
56 * mapped into process space.
59 * There are several types of work items that the host may place into a
60 * workqueue, each with its own requirements and limitations. Currently only
61 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
62 * represents in-order queue. The kernel driver packs ring tail pointer and an
63 * ELSP context descriptor dword into Work Item.
64 * See guc_wq_item_append()
69 * Read GuC command/status register (SOFT_SCRATCH_0)
70 * Return true if it contains a response rather than a command
72 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
75 u32 val = I915_READ(SOFT_SCRATCH(0));
77 return GUC2HOST_IS_RESPONSE(val);
80 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
82 struct drm_i915_private *dev_priv = guc_to_i915(guc);
87 if (WARN_ON(len < 1 || len > 15))
90 mutex_lock(&guc->action_lock);
91 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
93 dev_priv->guc.action_count += 1;
94 dev_priv->guc.action_cmd = data[0];
96 for (i = 0; i < len; i++)
97 I915_WRITE(SOFT_SCRATCH(i), data[i]);
99 POSTING_READ(SOFT_SCRATCH(i - 1));
101 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
104 * Fast commands should complete in less than 10us, so sample quickly
105 * up to that length of time, then switch to a slower sleep-wait loop.
106 * No HOST2GUC command should ever take longer than 10ms.
108 ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
110 ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
111 if (status != GUC2HOST_STATUS_SUCCESS) {
113 * Either the GuC explicitly returned an error (which
114 * we convert to -EIO here) or no response at all was
115 * received within the timeout limit (-ETIMEDOUT)
117 if (ret != -ETIMEDOUT)
120 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
121 data[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
123 dev_priv->guc.action_fail += 1;
124 dev_priv->guc.action_err = ret;
126 dev_priv->guc.action_status = status;
128 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
129 mutex_unlock(&guc->action_lock);
135 * Tell the GuC to allocate or deallocate a specific doorbell
138 static int host2guc_allocate_doorbell(struct intel_guc *guc,
139 struct i915_guc_client *client)
143 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
144 data[1] = client->ctx_index;
146 return host2guc_action(guc, data, 2);
149 static int host2guc_release_doorbell(struct intel_guc *guc,
150 struct i915_guc_client *client)
154 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
155 data[1] = client->ctx_index;
157 return host2guc_action(guc, data, 2);
160 static int host2guc_sample_forcewake(struct intel_guc *guc,
161 struct i915_guc_client *client)
163 struct drm_i915_private *dev_priv = guc_to_i915(guc);
166 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
167 /* WaRsDisableCoarsePowerGating:skl,bxt */
168 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
171 /* bit 0 and 1 are for Render and Media domain separately */
172 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
174 return host2guc_action(guc, data, ARRAY_SIZE(data));
177 static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
181 data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
183 return host2guc_action(guc, data, 1);
186 static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
190 data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
193 return host2guc_action(guc, data, 2);
196 static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
200 data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING;
201 data[1] = control_val;
203 return host2guc_action(guc, data, 2);
207 * Initialise, update, or clear doorbell data shared with the GuC
209 * These functions modify shared data and so need access to the mapped
210 * client object which contains the page being used for the doorbell
213 static int guc_update_doorbell_id(struct intel_guc *guc,
214 struct i915_guc_client *client,
217 struct sg_table *sg = guc->ctx_pool_vma->pages;
218 void *doorbell_bitmap = guc->doorbell_bitmap;
219 struct guc_doorbell_info *doorbell;
220 struct guc_context_desc desc;
223 doorbell = client->client_base + client->doorbell_offset;
225 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
226 test_bit(client->doorbell_id, doorbell_bitmap)) {
227 /* Deactivate the old doorbell */
228 doorbell->db_status = GUC_DOORBELL_DISABLED;
229 (void)host2guc_release_doorbell(guc, client);
230 __clear_bit(client->doorbell_id, doorbell_bitmap);
233 /* Update the GuC's idea of the doorbell ID */
234 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
235 sizeof(desc) * client->ctx_index);
236 if (len != sizeof(desc))
239 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
240 sizeof(desc) * client->ctx_index);
241 if (len != sizeof(desc))
244 client->doorbell_id = new_id;
245 if (new_id == GUC_INVALID_DOORBELL_ID)
248 /* Activate the new doorbell */
249 __set_bit(new_id, doorbell_bitmap);
250 doorbell->cookie = 0;
251 doorbell->db_status = GUC_DOORBELL_ENABLED;
252 return host2guc_allocate_doorbell(guc, client);
255 static int guc_init_doorbell(struct intel_guc *guc,
256 struct i915_guc_client *client,
259 return guc_update_doorbell_id(guc, client, db_id);
262 static void guc_disable_doorbell(struct intel_guc *guc,
263 struct i915_guc_client *client)
265 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
267 /* XXX: wait for any interrupts */
268 /* XXX: wait for workqueue to drain */
272 select_doorbell_register(struct intel_guc *guc, uint32_t priority)
275 * The bitmap tracks which doorbell registers are currently in use.
276 * It is split into two halves; the first half is used for normal
277 * priority contexts, the second half for high-priority ones.
278 * Note that logically higher priorities are numerically less than
279 * normal ones, so the test below means "is it high-priority?"
281 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
282 const uint16_t half = GUC_MAX_DOORBELLS / 2;
283 const uint16_t start = hi_pri ? half : 0;
284 const uint16_t end = start + half;
287 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
289 id = GUC_INVALID_DOORBELL_ID;
291 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
292 hi_pri ? "high" : "normal", id);
298 * Select, assign and relase doorbell cachelines
300 * These functions track which doorbell cachelines are in use.
301 * The data they manipulate is protected by the host2guc lock.
304 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
306 const uint32_t cacheline_size = cache_line_size();
309 /* Doorbell uses a single cache line within a page */
310 offset = offset_in_page(guc->db_cacheline);
312 /* Moving to next cache line to reduce contention */
313 guc->db_cacheline += cacheline_size;
315 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
316 offset, guc->db_cacheline, cacheline_size);
322 * Initialise the process descriptor shared with the GuC firmware.
324 static void guc_proc_desc_init(struct intel_guc *guc,
325 struct i915_guc_client *client)
327 struct guc_process_desc *desc;
329 desc = client->client_base + client->proc_desc_offset;
331 memset(desc, 0, sizeof(*desc));
334 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
335 * space for ring3 clients (set them as in mmap_ioctl) or kernel
336 * space for kernel clients (map on demand instead? May make debug
337 * easier to have it mapped).
339 desc->wq_base_addr = 0;
340 desc->db_base_addr = 0;
342 desc->context_id = client->ctx_index;
343 desc->wq_size_bytes = client->wq_size;
344 desc->wq_status = WQ_STATUS_ACTIVE;
345 desc->priority = client->priority;
349 * Initialise/clear the context descriptor shared with the GuC firmware.
351 * This descriptor tells the GuC where (in GGTT space) to find the important
352 * data structures relating to this client (doorbell, process descriptor,
356 static void guc_ctx_desc_init(struct intel_guc *guc,
357 struct i915_guc_client *client)
359 struct drm_i915_private *dev_priv = guc_to_i915(guc);
360 struct intel_engine_cs *engine;
361 struct i915_gem_context *ctx = client->owner;
362 struct guc_context_desc desc;
367 memset(&desc, 0, sizeof(desc));
369 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
370 desc.context_id = client->ctx_index;
371 desc.priority = client->priority;
372 desc.db_id = client->doorbell_id;
374 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
375 struct intel_context *ce = &ctx->engine[engine->id];
376 uint32_t guc_engine_id = engine->guc_id;
377 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
379 /* TODO: We have a design issue to be solved here. Only when we
380 * receive the first batch, we know which engine is used by the
381 * user. But here GuC expects the lrc and ring to be pinned. It
382 * is not an issue for default context, which is the only one
383 * for now who owns a GuC client. But for future owner of GuC
384 * client, need to make sure lrc is pinned prior to enter here.
387 break; /* XXX: continue? */
389 lrc->context_desc = lower_32_bits(ce->lrc_desc);
391 /* The state page is after PPHWSP */
393 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
394 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
395 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
397 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma);
398 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
399 lrc->ring_next_free_location = lrc->ring_begin;
400 lrc->ring_current_tail_pointer_value = 0;
402 desc.engines_used |= (1 << guc_engine_id);
405 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
406 client->engines, desc.engines_used);
407 WARN_ON(desc.engines_used == 0);
410 * The doorbell, process descriptor, and workqueue are all parts
411 * of the client object, which the GuC will reference via the GGTT
413 gfx_addr = i915_ggtt_offset(client->vma);
414 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
415 client->doorbell_offset;
416 desc.db_trigger_cpu = (uintptr_t)client->client_base +
417 client->doorbell_offset;
418 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
419 desc.process_desc = gfx_addr + client->proc_desc_offset;
420 desc.wq_addr = gfx_addr + client->wq_offset;
421 desc.wq_size = client->wq_size;
424 * XXX: Take LRCs from an existing context if this is not an
425 * IsKMDCreatedContext client
427 desc.desc_private = (uintptr_t)client;
429 /* Pool context is pinned already */
430 sg = guc->ctx_pool_vma->pages;
431 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
432 sizeof(desc) * client->ctx_index);
435 static void guc_ctx_desc_fini(struct intel_guc *guc,
436 struct i915_guc_client *client)
438 struct guc_context_desc desc;
441 memset(&desc, 0, sizeof(desc));
443 sg = guc->ctx_pool_vma->pages;
444 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
445 sizeof(desc) * client->ctx_index);
449 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
450 * @request: request associated with the commands
452 * Return: 0 if space is available
453 * -EAGAIN if space is not currently available
455 * This function must be called (and must return 0) before a request
456 * is submitted to the GuC via i915_guc_submit() below. Once a result
457 * of 0 has been returned, it must be balanced by a corresponding
460 * Reservation allows the caller to determine in advance that space
461 * will be available for the next submission before committing resources
462 * to it, and helps avoid late failures with complicated recovery paths.
464 int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
466 const size_t wqi_size = sizeof(struct guc_wq_item);
467 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
468 struct guc_process_desc *desc = gc->client_base + gc->proc_desc_offset;
472 spin_lock(&gc->wq_lock);
473 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
474 freespace -= gc->wq_rsvd;
475 if (likely(freespace >= wqi_size)) {
476 gc->wq_rsvd += wqi_size;
482 spin_unlock(&gc->wq_lock);
487 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
489 const size_t wqi_size = sizeof(struct guc_wq_item);
490 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
492 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
494 spin_lock(&gc->wq_lock);
495 gc->wq_rsvd -= wqi_size;
496 spin_unlock(&gc->wq_lock);
499 /* Construct a Work Item and append it to the GuC's Work Queue */
500 static void guc_wq_item_append(struct i915_guc_client *gc,
501 struct drm_i915_gem_request *rq)
503 /* wqi_len is in DWords, and does not include the one-word header */
504 const size_t wqi_size = sizeof(struct guc_wq_item);
505 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
506 struct intel_engine_cs *engine = rq->engine;
507 struct guc_process_desc *desc;
508 struct guc_wq_item *wqi;
510 u32 freespace, tail, wq_off, wq_page;
512 desc = gc->client_base + gc->proc_desc_offset;
514 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
515 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
516 GEM_BUG_ON(freespace < wqi_size);
518 /* The GuC firmware wants the tail index in QWords, not bytes */
520 GEM_BUG_ON(tail & 7);
522 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
524 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
525 * should not have the case where structure wqi is across page, neither
526 * wrapped to the beginning. This simplifies the implementation below.
528 * XXX: if not the case, we need save data to a temp wqi and copy it to
529 * workqueue buffer dw by dw.
531 BUILD_BUG_ON(wqi_size != 16);
532 GEM_BUG_ON(gc->wq_rsvd < wqi_size);
534 /* postincrement WQ tail for next time */
535 wq_off = gc->wq_tail;
536 GEM_BUG_ON(wq_off & (wqi_size - 1));
537 gc->wq_tail += wqi_size;
538 gc->wq_tail &= gc->wq_size - 1;
539 gc->wq_rsvd -= wqi_size;
541 /* WQ starts from the page after doorbell / process_desc */
542 wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT;
543 wq_off &= PAGE_SIZE - 1;
544 base = kmap_atomic(i915_gem_object_get_page(gc->vma->obj, wq_page));
545 wqi = (struct guc_wq_item *)((char *)base + wq_off);
547 /* Now fill in the 4-word work queue item */
548 wqi->header = WQ_TYPE_INORDER |
549 (wqi_len << WQ_LEN_SHIFT) |
550 (engine->guc_id << WQ_TARGET_SHIFT) |
553 /* The GuC wants only the low-order word of the context descriptor */
554 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
556 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
557 wqi->fence_id = rq->fence.seqno;
562 static int guc_ring_doorbell(struct i915_guc_client *gc)
564 struct guc_process_desc *desc;
565 union guc_doorbell_qw db_cmp, db_exc, db_ret;
566 union guc_doorbell_qw *db;
567 int attempt = 2, ret = -EAGAIN;
569 desc = gc->client_base + gc->proc_desc_offset;
571 /* Update the tail so it is visible to GuC */
572 desc->tail = gc->wq_tail;
575 db_cmp.db_status = GUC_DOORBELL_ENABLED;
576 db_cmp.cookie = gc->cookie;
578 /* cookie to be updated */
579 db_exc.db_status = GUC_DOORBELL_ENABLED;
580 db_exc.cookie = gc->cookie + 1;
581 if (db_exc.cookie == 0)
584 /* pointer of current doorbell cacheline */
585 db = gc->client_base + gc->doorbell_offset;
588 /* lets ring the doorbell */
589 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
590 db_cmp.value_qw, db_exc.value_qw);
592 /* if the exchange was successfully executed */
593 if (db_ret.value_qw == db_cmp.value_qw) {
594 /* db was successfully rung */
595 gc->cookie = db_exc.cookie;
600 /* XXX: doorbell was lost and need to acquire it again */
601 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
604 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
605 db_cmp.cookie, db_ret.cookie);
607 /* update the cookie to newly read cookie from GuC */
608 db_cmp.cookie = db_ret.cookie;
609 db_exc.cookie = db_ret.cookie + 1;
610 if (db_exc.cookie == 0)
618 * i915_guc_submit() - Submit commands through GuC
619 * @rq: request associated with the commands
621 * Return: 0 on success, otherwise an errno.
622 * (Note: nonzero really shouldn't happen!)
624 * The caller must have already called i915_guc_wq_reserve() above with
625 * a result of 0 (success), guaranteeing that there is space in the work
626 * queue for the new request, so enqueuing the item cannot fail.
628 * Bad Things Will Happen if the caller violates this protocol e.g. calls
629 * submit() when _reserve() says there's no space, or calls _submit()
630 * a different number of times from (successful) calls to _reserve().
632 * The only error here arises if the doorbell hardware isn't functioning
633 * as expected, which really shouln't happen.
635 static void i915_guc_submit(struct drm_i915_gem_request *rq)
637 struct drm_i915_private *dev_priv = rq->i915;
638 unsigned int engine_id = rq->engine->id;
639 struct intel_guc *guc = &rq->i915->guc;
640 struct i915_guc_client *client = guc->execbuf_client;
643 spin_lock(&client->wq_lock);
644 guc_wq_item_append(client, rq);
646 /* WA to flush out the pending GMADR writes to ring buffer. */
647 if (i915_vma_is_map_and_fenceable(rq->ring->vma))
648 POSTING_READ_FW(GUC_STATUS);
650 b_ret = guc_ring_doorbell(client);
652 client->submissions[engine_id] += 1;
653 client->retcode = b_ret;
657 guc->submissions[engine_id] += 1;
658 guc->last_seqno[engine_id] = rq->fence.seqno;
659 spin_unlock(&client->wq_lock);
663 * Everything below here is concerned with setup & teardown, and is
664 * therefore not part of the somewhat time-critical batch-submission
665 * path of i915_guc_submit() above.
669 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
671 * @size: size of area to allocate (both virtual space and memory)
673 * This is a wrapper to create an object for use with the GuC. In order to
674 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
675 * both some backing storage and a range inside the Global GTT. We must pin
676 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
677 * range is reserved inside GuC.
679 * Return: A i915_vma if successful, otherwise an ERR_PTR.
681 static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
683 struct drm_i915_private *dev_priv = guc_to_i915(guc);
684 struct drm_i915_gem_object *obj;
685 struct i915_vma *vma;
688 obj = i915_gem_object_create(&dev_priv->drm, size);
690 return ERR_CAST(obj);
692 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
696 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
697 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
703 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
704 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
709 i915_gem_object_put(obj);
714 guc_client_free(struct drm_i915_private *dev_priv,
715 struct i915_guc_client *client)
717 struct intel_guc *guc = &dev_priv->guc;
723 * XXX: wait for any outstanding submissions before freeing memory.
724 * Be sure to drop any locks
727 if (client->client_base) {
729 * If we got as far as setting up a doorbell, make sure we
730 * shut it down before unmapping & deallocating the memory.
732 guc_disable_doorbell(guc, client);
734 kunmap(kmap_to_page(client->client_base));
737 i915_vma_unpin_and_release(&client->vma);
739 if (client->ctx_index != GUC_INVALID_CTX_ID) {
740 guc_ctx_desc_fini(guc, client);
741 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
747 /* Check that a doorbell register is in the expected state */
748 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
750 struct drm_i915_private *dev_priv = guc_to_i915(guc);
751 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
752 uint32_t value = I915_READ(drbreg);
753 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
754 bool expected = test_bit(db_id, guc->doorbell_bitmap);
756 if (enabled == expected)
759 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
760 db_id, drbreg.reg, value,
761 expected ? "active" : "inactive");
767 * Borrow the first client to set up & tear down each unused doorbell
768 * in turn, to ensure that all doorbell h/w is (re)initialised.
770 static void guc_init_doorbell_hw(struct intel_guc *guc)
772 struct i915_guc_client *client = guc->execbuf_client;
776 /* Save client's original doorbell selection */
777 db_id = client->doorbell_id;
779 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
780 /* Skip if doorbell is OK */
781 if (guc_doorbell_check(guc, i))
784 err = guc_update_doorbell_id(guc, client, i);
786 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
790 /* Restore to original value */
791 err = guc_update_doorbell_id(guc, client, db_id);
793 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
796 /* Read back & verify all doorbell registers */
797 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
798 (void)guc_doorbell_check(guc, i);
802 * guc_client_alloc() - Allocate an i915_guc_client
803 * @dev_priv: driver private data structure
804 * @engines: The set of engines to enable for this client
805 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
806 * The kernel client to replace ExecList submission is created with
807 * NORMAL priority. Priority of a client for scheduler can be HIGH,
808 * while a preemption context can use CRITICAL.
809 * @ctx: the context that owns the client (we use the default render
812 * Return: An i915_guc_client object if success, else NULL.
814 static struct i915_guc_client *
815 guc_client_alloc(struct drm_i915_private *dev_priv,
818 struct i915_gem_context *ctx)
820 struct i915_guc_client *client;
821 struct intel_guc *guc = &dev_priv->guc;
822 struct i915_vma *vma;
825 client = kzalloc(sizeof(*client), GFP_KERNEL);
831 client->engines = engines;
832 client->priority = priority;
833 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
835 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
836 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
837 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
838 client->ctx_index = GUC_INVALID_CTX_ID;
842 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
843 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
847 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
849 client->client_base = kmap(i915_vma_first_page(vma));
851 spin_lock_init(&client->wq_lock);
852 client->wq_offset = GUC_DB_SIZE;
853 client->wq_size = GUC_WQ_SIZE;
855 db_id = select_doorbell_register(guc, client->priority);
856 if (db_id == GUC_INVALID_DOORBELL_ID)
857 /* XXX: evict a doorbell instead? */
860 client->doorbell_offset = select_doorbell_cacheline(guc);
863 * Since the doorbell only requires a single cacheline, we can save
864 * space by putting the application process descriptor in the same
865 * page. Use the half of the page that doesn't include the doorbell.
867 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
868 client->proc_desc_offset = 0;
870 client->proc_desc_offset = (GUC_DB_SIZE / 2);
872 guc_proc_desc_init(guc, client);
873 guc_ctx_desc_init(guc, client);
874 if (guc_init_doorbell(guc, client, db_id))
877 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
878 priority, client, client->engines, client->ctx_index);
879 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
880 client->doorbell_id, client->doorbell_offset);
885 guc_client_free(dev_priv, client);
890 * Sub buffer switch callback. Called whenever relay has to switch to a new
891 * sub buffer, relay stays on the same sub buffer if 0 is returned.
893 static int subbuf_start_callback(struct rchan_buf *buf,
898 /* Use no-overwrite mode by default, where relay will stop accepting
899 * new data if there are no empty sub buffers left.
900 * There is no strict synchronization enforced by relay between Consumer
901 * and Producer. In overwrite mode, there is a possibility of getting
902 * inconsistent/garbled data, the producer could be writing on to the
903 * same sub buffer from which Consumer is reading. This can't be avoided
904 * unless Consumer is fast enough and can always run in tandem with
907 if (relay_buf_full(buf))
914 * file_create() callback. Creates relay file in debugfs.
916 static struct dentry *create_buf_file_callback(const char *filename,
917 struct dentry *parent,
919 struct rchan_buf *buf,
922 struct dentry *buf_file;
924 /* This to enable the use of a single buffer for the relay channel and
925 * correspondingly have a single file exposed to User, through which
926 * it can collect the logs in order without any post-processing.
927 * Need to set 'is_global' even if parent is NULL for early logging.
934 /* Not using the channel filename passed as an argument, since for each
935 * channel relay appends the corresponding CPU number to the filename
936 * passed in relay_open(). This should be fine as relay just needs a
937 * dentry of the file associated with the channel buffer and that file's
938 * name need not be same as the filename passed as an argument.
940 buf_file = debugfs_create_file("guc_log", mode,
941 parent, buf, &relay_file_operations);
946 * file_remove() default callback. Removes relay file in debugfs.
948 static int remove_buf_file_callback(struct dentry *dentry)
950 debugfs_remove(dentry);
954 /* relay channel callbacks */
955 static struct rchan_callbacks relay_callbacks = {
956 .subbuf_start = subbuf_start_callback,
957 .create_buf_file = create_buf_file_callback,
958 .remove_buf_file = remove_buf_file_callback,
961 static void guc_log_remove_relay_file(struct intel_guc *guc)
963 relay_close(guc->log.relay_chan);
966 static int guc_log_create_relay_channel(struct intel_guc *guc)
968 struct drm_i915_private *dev_priv = guc_to_i915(guc);
969 struct rchan *guc_log_relay_chan;
970 size_t n_subbufs, subbuf_size;
972 /* Keep the size of sub buffers same as shared log buffer */
973 subbuf_size = guc->log.vma->obj->base.size;
975 /* Store up to 8 snapshots, which is large enough to buffer sufficient
976 * boot time logs and provides enough leeway to User, in terms of
977 * latency, for consuming the logs from relay. Also doesn't take
978 * up too much memory.
982 guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
983 n_subbufs, &relay_callbacks, dev_priv);
984 if (!guc_log_relay_chan) {
985 DRM_ERROR("Couldn't create relay chan for GuC logging\n");
989 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
990 guc->log.relay_chan = guc_log_relay_chan;
994 static int guc_log_create_relay_file(struct intel_guc *guc)
996 struct drm_i915_private *dev_priv = guc_to_i915(guc);
997 struct dentry *log_dir;
1000 /* For now create the log file in /sys/kernel/debug/dri/0 dir */
1001 log_dir = dev_priv->drm.primary->debugfs_root;
1003 /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
1004 * not mounted and so can't create the relay file.
1005 * The relay API seems to fit well with debugfs only, for availing relay
1006 * there are 3 requirements which can be met for debugfs file only in a
1007 * straightforward/clean manner :-
1008 * i) Need the associated dentry pointer of the file, while opening the
1010 * ii) Should be able to use 'relay_file_operations' fops for the file.
1011 * iii) Set the 'i_private' field of file's inode to the pointer of
1012 * relay channel buffer.
1015 DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
1019 ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir);
1021 DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
1028 static void guc_move_to_next_buf(struct intel_guc *guc)
1030 /* Make sure the updates made in the sub buffer are visible when
1031 * Consumer sees the following update to offset inside the sub buffer.
1035 /* All data has been written, so now move the offset of sub buffer. */
1036 relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size);
1038 /* Switch to the next sub buffer */
1039 relay_flush(guc->log.relay_chan);
1042 static void *guc_get_write_buffer(struct intel_guc *guc)
1044 if (!guc->log.relay_chan)
1047 /* Just get the base address of a new sub buffer and copy data into it
1048 * ourselves. NULL will be returned in no-overwrite mode, if all sub
1049 * buffers are full. Could have used the relay_write() to indirectly
1050 * copy the data, but that would have been bit convoluted, as we need to
1051 * write to only certain locations inside a sub buffer which cannot be
1052 * done without using relay_reserve() along with relay_write(). So its
1053 * better to use relay_reserve() alone.
1055 return relay_reserve(guc->log.relay_chan, 0);
1059 guc_check_log_buf_overflow(struct intel_guc *guc,
1060 enum guc_log_buffer_type type, unsigned int full_cnt)
1062 unsigned int prev_full_cnt = guc->log.prev_overflow_count[type];
1063 bool overflow = false;
1065 if (full_cnt != prev_full_cnt) {
1068 guc->log.prev_overflow_count[type] = full_cnt;
1069 guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt;
1071 if (full_cnt < prev_full_cnt) {
1072 /* buffer_full_cnt is a 4 bit counter */
1073 guc->log.total_overflow_count[type] += 16;
1075 DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
1081 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
1084 case GUC_ISR_LOG_BUFFER:
1085 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
1086 case GUC_DPC_LOG_BUFFER:
1087 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
1088 case GUC_CRASH_DUMP_LOG_BUFFER:
1089 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
1097 static void guc_read_update_log_buffer(struct intel_guc *guc)
1099 unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
1100 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
1101 struct guc_log_buffer_state log_buf_state_local;
1102 enum guc_log_buffer_type type;
1103 void *src_data, *dst_data;
1106 if (WARN_ON(!guc->log.buf_addr))
1109 /* Get the pointer to shared GuC log buffer */
1110 log_buf_state = src_data = guc->log.buf_addr;
1112 /* Get the pointer to local buffer to store the logs */
1113 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
1115 /* Actual logs are present from the 2nd page */
1116 src_data += PAGE_SIZE;
1117 dst_data += PAGE_SIZE;
1119 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
1120 /* Make a copy of the state structure, inside GuC log buffer
1121 * (which is uncached mapped), on the stack to avoid reading
1122 * from it multiple times.
1124 memcpy(&log_buf_state_local, log_buf_state,
1125 sizeof(struct guc_log_buffer_state));
1126 buffer_size = guc_get_log_buffer_size(type);
1127 read_offset = log_buf_state_local.read_ptr;
1128 write_offset = log_buf_state_local.sampled_write_ptr;
1129 full_cnt = log_buf_state_local.buffer_full_cnt;
1131 /* Bookkeeping stuff */
1132 guc->log.flush_count[type] += log_buf_state_local.flush_to_file;
1133 new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt);
1135 /* Update the state of shared log buffer */
1136 log_buf_state->read_ptr = write_offset;
1137 log_buf_state->flush_to_file = 0;
1140 if (unlikely(!log_buf_snapshot_state))
1143 /* First copy the state structure in snapshot buffer */
1144 memcpy(log_buf_snapshot_state, &log_buf_state_local,
1145 sizeof(struct guc_log_buffer_state));
1147 /* The write pointer could have been updated by GuC firmware,
1148 * after sending the flush interrupt to Host, for consistency
1149 * set write pointer value to same value of sampled_write_ptr
1150 * in the snapshot buffer.
1152 log_buf_snapshot_state->write_ptr = write_offset;
1153 log_buf_snapshot_state++;
1155 /* Now copy the actual logs. */
1156 if (unlikely(new_overflow)) {
1157 /* copy the whole buffer in case of overflow */
1159 write_offset = buffer_size;
1160 } else if (unlikely((read_offset > buffer_size) ||
1161 (write_offset > buffer_size))) {
1162 DRM_ERROR("invalid log buffer state\n");
1163 /* copy whole buffer as offsets are unreliable */
1165 write_offset = buffer_size;
1168 /* Just copy the newly written data */
1169 if (read_offset > write_offset) {
1170 i915_memcpy_from_wc(dst_data, src_data, write_offset);
1171 bytes_to_copy = buffer_size - read_offset;
1173 bytes_to_copy = write_offset - read_offset;
1175 i915_memcpy_from_wc(dst_data + read_offset,
1176 src_data + read_offset, bytes_to_copy);
1178 src_data += buffer_size;
1179 dst_data += buffer_size;
1182 if (log_buf_snapshot_state)
1183 guc_move_to_next_buf(guc);
1185 /* Used rate limited to avoid deluge of messages, logs might be
1186 * getting consumed by User at a slow rate.
1188 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
1189 guc->log.capture_miss_count++;
1193 static void guc_capture_logs_work(struct work_struct *work)
1195 struct drm_i915_private *dev_priv =
1196 container_of(work, struct drm_i915_private, guc.log.flush_work);
1198 i915_guc_capture_logs(dev_priv);
1201 static void guc_log_cleanup(struct intel_guc *guc)
1203 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1205 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1207 /* First disable the flush interrupt */
1208 gen9_disable_guc_interrupts(dev_priv);
1210 if (guc->log.flush_wq)
1211 destroy_workqueue(guc->log.flush_wq);
1213 guc->log.flush_wq = NULL;
1215 if (guc->log.relay_chan)
1216 guc_log_remove_relay_file(guc);
1218 guc->log.relay_chan = NULL;
1220 if (guc->log.buf_addr)
1221 i915_gem_object_unpin_map(guc->log.vma->obj);
1223 guc->log.buf_addr = NULL;
1226 static int guc_log_create_extras(struct intel_guc *guc)
1228 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1232 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1235 if (i915.guc_log_level < 0)
1238 if (!guc->log.buf_addr) {
1239 /* Create a WC (Uncached for read) vmalloc mapping of log
1240 * buffer pages, so that we can directly get the data
1241 * (up-to-date) from memory.
1243 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC);
1244 if (IS_ERR(vaddr)) {
1245 ret = PTR_ERR(vaddr);
1246 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
1250 guc->log.buf_addr = vaddr;
1253 if (!guc->log.relay_chan) {
1254 /* Create a relay channel, so that we have buffers for storing
1255 * the GuC firmware logs, the channel will be linked with a file
1256 * later on when debugfs is registered.
1258 ret = guc_log_create_relay_channel(guc);
1263 if (!guc->log.flush_wq) {
1264 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
1267 * GuC log buffer flush work item has to do register access to
1268 * send the ack to GuC and this work item, if not synced before
1269 * suspend, can potentially get executed after the GFX device is
1271 * By marking the WQ as freezable, we don't have to bother about
1272 * flushing of this work item from the suspend hooks, the pending
1273 * work item if any will be either executed before the suspend
1274 * or scheduled later on resume. This way the handling of work
1275 * item can be kept same between system suspend & rpm suspend.
1277 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
1278 WQ_HIGHPRI | WQ_FREEZABLE);
1279 if (guc->log.flush_wq == NULL) {
1280 DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
1288 static void guc_log_create(struct intel_guc *guc)
1290 struct i915_vma *vma;
1291 unsigned long offset;
1292 uint32_t size, flags;
1294 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
1295 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
1297 /* The first page is to save log buffer state. Allocate one
1298 * extra page for others in case for overlap */
1299 size = (1 + GUC_LOG_DPC_PAGES + 1 +
1300 GUC_LOG_ISR_PAGES + 1 +
1301 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
1305 /* We require SSE 4.1 for fast reads from the GuC log buffer and
1306 * it should be present on the chipsets supporting GuC based
1309 if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) {
1310 /* logging will not be enabled */
1311 i915.guc_log_level = -1;
1315 vma = guc_allocate_vma(guc, size);
1317 /* logging will be off */
1318 i915.guc_log_level = -1;
1324 if (guc_log_create_extras(guc)) {
1325 guc_log_cleanup(guc);
1326 i915_vma_unpin_and_release(&guc->log.vma);
1327 i915.guc_log_level = -1;
1332 /* each allocated unit is a page */
1333 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
1334 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
1335 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
1336 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
1338 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
1339 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
1342 static int guc_log_late_setup(struct intel_guc *guc)
1344 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1347 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1349 if (i915.guc_log_level < 0)
1352 /* If log_level was set as -1 at boot time, then setup needed to
1353 * handle log buffer flush interrupts would not have been done yet,
1356 ret = guc_log_create_extras(guc);
1360 ret = guc_log_create_relay_file(guc);
1366 guc_log_cleanup(guc);
1367 /* logging will remain off */
1368 i915.guc_log_level = -1;
1372 static void guc_policies_init(struct guc_policies *policies)
1374 struct guc_policy *policy;
1377 policies->dpc_promote_time = 500000;
1378 policies->max_num_work_items = POLICY_MAX_NUM_WI;
1380 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
1381 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
1382 policy = &policies->policy[p][i];
1384 policy->execution_quantum = 1000000;
1385 policy->preemption_time = 500000;
1386 policy->fault_time = 250000;
1387 policy->policy_flags = 0;
1391 policies->is_valid = 1;
1394 static void guc_addon_create(struct intel_guc *guc)
1396 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1397 struct i915_vma *vma;
1398 struct guc_ads *ads;
1399 struct guc_policies *policies;
1400 struct guc_mmio_reg_state *reg_state;
1401 struct intel_engine_cs *engine;
1402 enum intel_engine_id id;
1406 /* The ads obj includes the struct itself and buffers passed to GuC */
1407 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
1408 sizeof(struct guc_mmio_reg_state) +
1409 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
1413 vma = guc_allocate_vma(guc, PAGE_ALIGN(size));
1420 page = i915_vma_first_page(vma);
1424 * The GuC requires a "Golden Context" when it reinitialises
1425 * engines after a reset. Here we use the Render ring default
1426 * context, which must already exist and be pinned in the GGTT,
1427 * so its address won't change after we've told the GuC where
1430 engine = dev_priv->engine[RCS];
1431 ads->golden_context_lrca = engine->status_page.ggtt_offset;
1433 for_each_engine(engine, dev_priv, id)
1434 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
1436 /* GuC scheduling policies */
1437 policies = (void *)ads + sizeof(struct guc_ads);
1438 guc_policies_init(policies);
1440 ads->scheduler_policies =
1441 i915_ggtt_offset(vma) + sizeof(struct guc_ads);
1443 /* MMIO reg state */
1444 reg_state = (void *)policies + sizeof(struct guc_policies);
1446 for_each_engine(engine, dev_priv, id) {
1447 reg_state->mmio_white_list[engine->guc_id].mmio_start =
1448 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
1450 /* Nothing to be saved or restored for now. */
1451 reg_state->mmio_white_list[engine->guc_id].count = 0;
1454 ads->reg_state_addr = ads->scheduler_policies +
1455 sizeof(struct guc_policies);
1457 ads->reg_state_buffer = ads->reg_state_addr +
1458 sizeof(struct guc_mmio_reg_state);
1464 * Set up the memory resources to be shared with the GuC. At this point,
1465 * we require just one object that can be mapped through the GGTT.
1467 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
1469 const size_t ctxsize = sizeof(struct guc_context_desc);
1470 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
1471 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
1472 struct intel_guc *guc = &dev_priv->guc;
1473 struct i915_vma *vma;
1475 /* Wipe bitmap & delete client in case of reinitialisation */
1476 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
1477 i915_guc_submission_disable(dev_priv);
1479 if (!i915.enable_guc_submission)
1480 return 0; /* not enabled */
1482 if (guc->ctx_pool_vma)
1483 return 0; /* already allocated */
1485 vma = guc_allocate_vma(guc, gemsize);
1487 return PTR_ERR(vma);
1489 guc->ctx_pool_vma = vma;
1490 ida_init(&guc->ctx_ids);
1491 mutex_init(&guc->action_lock);
1492 guc_log_create(guc);
1493 guc_addon_create(guc);
1498 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1500 struct intel_guc *guc = &dev_priv->guc;
1501 struct drm_i915_gem_request *request;
1502 struct i915_guc_client *client;
1503 struct intel_engine_cs *engine;
1504 enum intel_engine_id id;
1506 /* client for execbuf submission */
1507 client = guc_client_alloc(dev_priv,
1508 INTEL_INFO(dev_priv)->ring_mask,
1509 GUC_CTX_PRIORITY_KMD_NORMAL,
1510 dev_priv->kernel_context);
1512 DRM_ERROR("Failed to create normal GuC client!\n");
1516 guc->execbuf_client = client;
1517 host2guc_sample_forcewake(guc, client);
1518 guc_init_doorbell_hw(guc);
1520 /* Take over from manual control of ELSP (execlists) */
1521 for_each_engine(engine, dev_priv, id) {
1522 engine->submit_request = i915_guc_submit;
1524 /* Replay the current set of previously submitted requests */
1525 list_for_each_entry(request, &engine->request_list, link) {
1526 client->wq_rsvd += sizeof(struct guc_wq_item);
1527 if (i915_sw_fence_done(&request->submit))
1528 i915_guc_submit(request);
1535 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1537 struct intel_guc *guc = &dev_priv->guc;
1539 if (!guc->execbuf_client)
1542 /* Revert back to manual ELSP submission */
1543 intel_execlists_enable_submission(dev_priv);
1545 guc_client_free(dev_priv, guc->execbuf_client);
1546 guc->execbuf_client = NULL;
1549 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1551 struct intel_guc *guc = &dev_priv->guc;
1553 i915_vma_unpin_and_release(&guc->ads_vma);
1554 i915_vma_unpin_and_release(&guc->log.vma);
1556 if (guc->ctx_pool_vma)
1557 ida_destroy(&guc->ctx_ids);
1558 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
1562 * intel_guc_suspend() - notify GuC entering suspend state
1565 int intel_guc_suspend(struct drm_device *dev)
1567 struct drm_i915_private *dev_priv = to_i915(dev);
1568 struct intel_guc *guc = &dev_priv->guc;
1569 struct i915_gem_context *ctx;
1572 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1575 gen9_disable_guc_interrupts(dev_priv);
1577 ctx = dev_priv->kernel_context;
1579 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
1580 /* any value greater than GUC_POWER_D0 */
1581 data[1] = GUC_POWER_D1;
1582 /* first page is shared data with GuC */
1583 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1585 return host2guc_action(guc, data, ARRAY_SIZE(data));
1590 * intel_guc_resume() - notify GuC resuming from suspend state
1593 int intel_guc_resume(struct drm_device *dev)
1595 struct drm_i915_private *dev_priv = to_i915(dev);
1596 struct intel_guc *guc = &dev_priv->guc;
1597 struct i915_gem_context *ctx;
1600 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1603 if (i915.guc_log_level >= 0)
1604 gen9_enable_guc_interrupts(dev_priv);
1606 ctx = dev_priv->kernel_context;
1608 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
1609 data[1] = GUC_POWER_D0;
1610 /* first page is shared data with GuC */
1611 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1613 return host2guc_action(guc, data, ARRAY_SIZE(data));
1616 void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
1618 guc_read_update_log_buffer(&dev_priv->guc);
1620 /* Generally device is expected to be active only at this
1621 * time, so get/put should be really quick.
1623 intel_runtime_pm_get(dev_priv);
1624 host2guc_logbuffer_flush_complete(&dev_priv->guc);
1625 intel_runtime_pm_put(dev_priv);
1628 void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
1630 if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
1633 /* First disable the interrupts, will be renabled afterwards */
1634 gen9_disable_guc_interrupts(dev_priv);
1636 /* Before initiating the forceful flush, wait for any pending/ongoing
1637 * flush to complete otherwise forceful flush may not actually happen.
1639 flush_work(&dev_priv->guc.log.flush_work);
1641 /* Ask GuC to update the log buffer state */
1642 host2guc_force_logbuffer_flush(&dev_priv->guc);
1644 /* GuC would have updated log buffer by now, so capture it */
1645 i915_guc_capture_logs(dev_priv);
1648 void i915_guc_unregister(struct drm_i915_private *dev_priv)
1650 if (!i915.enable_guc_submission)
1653 mutex_lock(&dev_priv->drm.struct_mutex);
1654 guc_log_cleanup(&dev_priv->guc);
1655 mutex_unlock(&dev_priv->drm.struct_mutex);
1658 void i915_guc_register(struct drm_i915_private *dev_priv)
1660 if (!i915.enable_guc_submission)
1663 mutex_lock(&dev_priv->drm.struct_mutex);
1664 guc_log_late_setup(&dev_priv->guc);
1665 mutex_unlock(&dev_priv->drm.struct_mutex);
1668 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
1670 union guc_log_control log_param;
1673 log_param.value = control_val;
1675 if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN ||
1676 log_param.verbosity > GUC_LOG_VERBOSITY_MAX)
1679 /* This combination doesn't make sense & won't have any effect */
1680 if (!log_param.logging_enabled && (i915.guc_log_level < 0))
1683 ret = host2guc_logging_control(&dev_priv->guc, log_param.value);
1685 DRM_DEBUG_DRIVER("host2guc action failed %d\n", ret);
1689 i915.guc_log_level = log_param.verbosity;
1691 /* If log_level was set as -1 at boot time, then the relay channel file
1692 * wouldn't have been created by now and interrupts also would not have
1695 if (!dev_priv->guc.log.relay_chan) {
1696 ret = guc_log_late_setup(&dev_priv->guc);
1698 gen9_enable_guc_interrupts(dev_priv);
1699 } else if (!log_param.logging_enabled) {
1700 /* Once logging is disabled, GuC won't generate logs & send an
1701 * interrupt. But there could be some data in the log buffer
1702 * which is yet to be captured. So request GuC to update the log
1703 * buffer state and then collect the left over logs.
1705 i915_guc_flush_logs(dev_priv);
1707 /* As logging is disabled, update log level to reflect that */
1708 i915.guc_log_level = -1;
1710 /* In case interrupts were disabled, enable them now */
1711 gen9_enable_guc_interrupts(dev_priv);