2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_wq_item_append()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
73 u32 val = I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val);
78 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
80 struct drm_i915_private *dev_priv = guc_to_i915(guc);
85 if (WARN_ON(len < 1 || len > 15))
88 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
90 dev_priv->guc.action_count += 1;
91 dev_priv->guc.action_cmd = data[0];
93 for (i = 0; i < len; i++)
94 I915_WRITE(SOFT_SCRATCH(i), data[i]);
96 POSTING_READ(SOFT_SCRATCH(i - 1));
98 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
101 * Fast commands should complete in less than 10us, so sample quickly
102 * up to that length of time, then switch to a slower sleep-wait loop.
103 * No HOST2GUC command should ever take longer than 10ms.
105 ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
107 ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
108 if (status != GUC2HOST_STATUS_SUCCESS) {
110 * Either the GuC explicitly returned an error (which
111 * we convert to -EIO here) or no response at all was
112 * received within the timeout limit (-ETIMEDOUT)
114 if (ret != -ETIMEDOUT)
117 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
118 data[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
120 dev_priv->guc.action_fail += 1;
121 dev_priv->guc.action_err = ret;
123 dev_priv->guc.action_status = status;
125 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
131 * Tell the GuC to allocate or deallocate a specific doorbell
134 static int host2guc_allocate_doorbell(struct intel_guc *guc,
135 struct i915_guc_client *client)
139 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
140 data[1] = client->ctx_index;
142 return host2guc_action(guc, data, 2);
145 static int host2guc_release_doorbell(struct intel_guc *guc,
146 struct i915_guc_client *client)
150 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
151 data[1] = client->ctx_index;
153 return host2guc_action(guc, data, 2);
156 static int host2guc_sample_forcewake(struct intel_guc *guc,
157 struct i915_guc_client *client)
159 struct drm_i915_private *dev_priv = guc_to_i915(guc);
162 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
163 /* WaRsDisableCoarsePowerGating:skl,bxt */
164 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
167 /* bit 0 and 1 are for Render and Media domain separately */
168 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
170 return host2guc_action(guc, data, ARRAY_SIZE(data));
173 static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
177 data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
179 return host2guc_action(guc, data, 1);
183 * Initialise, update, or clear doorbell data shared with the GuC
185 * These functions modify shared data and so need access to the mapped
186 * client object which contains the page being used for the doorbell
189 static int guc_update_doorbell_id(struct intel_guc *guc,
190 struct i915_guc_client *client,
193 struct sg_table *sg = guc->ctx_pool_vma->pages;
194 void *doorbell_bitmap = guc->doorbell_bitmap;
195 struct guc_doorbell_info *doorbell;
196 struct guc_context_desc desc;
199 doorbell = client->client_base + client->doorbell_offset;
201 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
202 test_bit(client->doorbell_id, doorbell_bitmap)) {
203 /* Deactivate the old doorbell */
204 doorbell->db_status = GUC_DOORBELL_DISABLED;
205 (void)host2guc_release_doorbell(guc, client);
206 __clear_bit(client->doorbell_id, doorbell_bitmap);
209 /* Update the GuC's idea of the doorbell ID */
210 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
211 sizeof(desc) * client->ctx_index);
212 if (len != sizeof(desc))
215 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
216 sizeof(desc) * client->ctx_index);
217 if (len != sizeof(desc))
220 client->doorbell_id = new_id;
221 if (new_id == GUC_INVALID_DOORBELL_ID)
224 /* Activate the new doorbell */
225 __set_bit(new_id, doorbell_bitmap);
226 doorbell->cookie = 0;
227 doorbell->db_status = GUC_DOORBELL_ENABLED;
228 return host2guc_allocate_doorbell(guc, client);
231 static int guc_init_doorbell(struct intel_guc *guc,
232 struct i915_guc_client *client,
235 return guc_update_doorbell_id(guc, client, db_id);
238 static void guc_disable_doorbell(struct intel_guc *guc,
239 struct i915_guc_client *client)
241 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
243 /* XXX: wait for any interrupts */
244 /* XXX: wait for workqueue to drain */
248 select_doorbell_register(struct intel_guc *guc, uint32_t priority)
251 * The bitmap tracks which doorbell registers are currently in use.
252 * It is split into two halves; the first half is used for normal
253 * priority contexts, the second half for high-priority ones.
254 * Note that logically higher priorities are numerically less than
255 * normal ones, so the test below means "is it high-priority?"
257 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
258 const uint16_t half = GUC_MAX_DOORBELLS / 2;
259 const uint16_t start = hi_pri ? half : 0;
260 const uint16_t end = start + half;
263 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
265 id = GUC_INVALID_DOORBELL_ID;
267 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
268 hi_pri ? "high" : "normal", id);
274 * Select, assign and relase doorbell cachelines
276 * These functions track which doorbell cachelines are in use.
277 * The data they manipulate is protected by the host2guc lock.
280 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
282 const uint32_t cacheline_size = cache_line_size();
285 /* Doorbell uses a single cache line within a page */
286 offset = offset_in_page(guc->db_cacheline);
288 /* Moving to next cache line to reduce contention */
289 guc->db_cacheline += cacheline_size;
291 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
292 offset, guc->db_cacheline, cacheline_size);
298 * Initialise the process descriptor shared with the GuC firmware.
300 static void guc_proc_desc_init(struct intel_guc *guc,
301 struct i915_guc_client *client)
303 struct guc_process_desc *desc;
305 desc = client->client_base + client->proc_desc_offset;
307 memset(desc, 0, sizeof(*desc));
310 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
311 * space for ring3 clients (set them as in mmap_ioctl) or kernel
312 * space for kernel clients (map on demand instead? May make debug
313 * easier to have it mapped).
315 desc->wq_base_addr = 0;
316 desc->db_base_addr = 0;
318 desc->context_id = client->ctx_index;
319 desc->wq_size_bytes = client->wq_size;
320 desc->wq_status = WQ_STATUS_ACTIVE;
321 desc->priority = client->priority;
325 * Initialise/clear the context descriptor shared with the GuC firmware.
327 * This descriptor tells the GuC where (in GGTT space) to find the important
328 * data structures relating to this client (doorbell, process descriptor,
332 static void guc_ctx_desc_init(struct intel_guc *guc,
333 struct i915_guc_client *client)
335 struct drm_i915_private *dev_priv = guc_to_i915(guc);
336 struct intel_engine_cs *engine;
337 struct i915_gem_context *ctx = client->owner;
338 struct guc_context_desc desc;
343 memset(&desc, 0, sizeof(desc));
345 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
346 desc.context_id = client->ctx_index;
347 desc.priority = client->priority;
348 desc.db_id = client->doorbell_id;
350 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
351 struct intel_context *ce = &ctx->engine[engine->id];
352 uint32_t guc_engine_id = engine->guc_id;
353 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
355 /* TODO: We have a design issue to be solved here. Only when we
356 * receive the first batch, we know which engine is used by the
357 * user. But here GuC expects the lrc and ring to be pinned. It
358 * is not an issue for default context, which is the only one
359 * for now who owns a GuC client. But for future owner of GuC
360 * client, need to make sure lrc is pinned prior to enter here.
363 break; /* XXX: continue? */
365 lrc->context_desc = lower_32_bits(ce->lrc_desc);
367 /* The state page is after PPHWSP */
369 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
370 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
371 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
373 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma);
374 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
375 lrc->ring_next_free_location = lrc->ring_begin;
376 lrc->ring_current_tail_pointer_value = 0;
378 desc.engines_used |= (1 << guc_engine_id);
381 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
382 client->engines, desc.engines_used);
383 WARN_ON(desc.engines_used == 0);
386 * The doorbell, process descriptor, and workqueue are all parts
387 * of the client object, which the GuC will reference via the GGTT
389 gfx_addr = i915_ggtt_offset(client->vma);
390 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
391 client->doorbell_offset;
392 desc.db_trigger_cpu = (uintptr_t)client->client_base +
393 client->doorbell_offset;
394 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
395 desc.process_desc = gfx_addr + client->proc_desc_offset;
396 desc.wq_addr = gfx_addr + client->wq_offset;
397 desc.wq_size = client->wq_size;
400 * XXX: Take LRCs from an existing context if this is not an
401 * IsKMDCreatedContext client
403 desc.desc_private = (uintptr_t)client;
405 /* Pool context is pinned already */
406 sg = guc->ctx_pool_vma->pages;
407 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
408 sizeof(desc) * client->ctx_index);
411 static void guc_ctx_desc_fini(struct intel_guc *guc,
412 struct i915_guc_client *client)
414 struct guc_context_desc desc;
417 memset(&desc, 0, sizeof(desc));
419 sg = guc->ctx_pool_vma->pages;
420 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
421 sizeof(desc) * client->ctx_index);
425 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
426 * @request: request associated with the commands
428 * Return: 0 if space is available
429 * -EAGAIN if space is not currently available
431 * This function must be called (and must return 0) before a request
432 * is submitted to the GuC via i915_guc_submit() below. Once a result
433 * of 0 has been returned, it must be balanced by a corresponding
436 * Reservation allows the caller to determine in advance that space
437 * will be available for the next submission before committing resources
438 * to it, and helps avoid late failures with complicated recovery paths.
440 int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
442 const size_t wqi_size = sizeof(struct guc_wq_item);
443 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
444 struct guc_process_desc *desc = gc->client_base + gc->proc_desc_offset;
448 spin_lock(&gc->wq_lock);
449 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
450 freespace -= gc->wq_rsvd;
451 if (likely(freespace >= wqi_size)) {
452 gc->wq_rsvd += wqi_size;
458 spin_unlock(&gc->wq_lock);
463 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
465 const size_t wqi_size = sizeof(struct guc_wq_item);
466 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
468 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
470 spin_lock(&gc->wq_lock);
471 gc->wq_rsvd -= wqi_size;
472 spin_unlock(&gc->wq_lock);
475 /* Construct a Work Item and append it to the GuC's Work Queue */
476 static void guc_wq_item_append(struct i915_guc_client *gc,
477 struct drm_i915_gem_request *rq)
479 /* wqi_len is in DWords, and does not include the one-word header */
480 const size_t wqi_size = sizeof(struct guc_wq_item);
481 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
482 struct intel_engine_cs *engine = rq->engine;
483 struct guc_process_desc *desc;
484 struct guc_wq_item *wqi;
486 u32 freespace, tail, wq_off, wq_page;
488 desc = gc->client_base + gc->proc_desc_offset;
490 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
491 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
492 GEM_BUG_ON(freespace < wqi_size);
494 /* The GuC firmware wants the tail index in QWords, not bytes */
496 GEM_BUG_ON(tail & 7);
498 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
500 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
501 * should not have the case where structure wqi is across page, neither
502 * wrapped to the beginning. This simplifies the implementation below.
504 * XXX: if not the case, we need save data to a temp wqi and copy it to
505 * workqueue buffer dw by dw.
507 BUILD_BUG_ON(wqi_size != 16);
508 GEM_BUG_ON(gc->wq_rsvd < wqi_size);
510 /* postincrement WQ tail for next time */
511 wq_off = gc->wq_tail;
512 GEM_BUG_ON(wq_off & (wqi_size - 1));
513 gc->wq_tail += wqi_size;
514 gc->wq_tail &= gc->wq_size - 1;
515 gc->wq_rsvd -= wqi_size;
517 /* WQ starts from the page after doorbell / process_desc */
518 wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT;
519 wq_off &= PAGE_SIZE - 1;
520 base = kmap_atomic(i915_gem_object_get_page(gc->vma->obj, wq_page));
521 wqi = (struct guc_wq_item *)((char *)base + wq_off);
523 /* Now fill in the 4-word work queue item */
524 wqi->header = WQ_TYPE_INORDER |
525 (wqi_len << WQ_LEN_SHIFT) |
526 (engine->guc_id << WQ_TARGET_SHIFT) |
529 /* The GuC wants only the low-order word of the context descriptor */
530 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
532 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
533 wqi->fence_id = rq->fence.seqno;
538 static int guc_ring_doorbell(struct i915_guc_client *gc)
540 struct guc_process_desc *desc;
541 union guc_doorbell_qw db_cmp, db_exc, db_ret;
542 union guc_doorbell_qw *db;
543 int attempt = 2, ret = -EAGAIN;
545 desc = gc->client_base + gc->proc_desc_offset;
547 /* Update the tail so it is visible to GuC */
548 desc->tail = gc->wq_tail;
551 db_cmp.db_status = GUC_DOORBELL_ENABLED;
552 db_cmp.cookie = gc->cookie;
554 /* cookie to be updated */
555 db_exc.db_status = GUC_DOORBELL_ENABLED;
556 db_exc.cookie = gc->cookie + 1;
557 if (db_exc.cookie == 0)
560 /* pointer of current doorbell cacheline */
561 db = gc->client_base + gc->doorbell_offset;
564 /* lets ring the doorbell */
565 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
566 db_cmp.value_qw, db_exc.value_qw);
568 /* if the exchange was successfully executed */
569 if (db_ret.value_qw == db_cmp.value_qw) {
570 /* db was successfully rung */
571 gc->cookie = db_exc.cookie;
576 /* XXX: doorbell was lost and need to acquire it again */
577 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
580 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
581 db_cmp.cookie, db_ret.cookie);
583 /* update the cookie to newly read cookie from GuC */
584 db_cmp.cookie = db_ret.cookie;
585 db_exc.cookie = db_ret.cookie + 1;
586 if (db_exc.cookie == 0)
594 * i915_guc_submit() - Submit commands through GuC
595 * @rq: request associated with the commands
597 * Return: 0 on success, otherwise an errno.
598 * (Note: nonzero really shouldn't happen!)
600 * The caller must have already called i915_guc_wq_reserve() above with
601 * a result of 0 (success), guaranteeing that there is space in the work
602 * queue for the new request, so enqueuing the item cannot fail.
604 * Bad Things Will Happen if the caller violates this protocol e.g. calls
605 * submit() when _reserve() says there's no space, or calls _submit()
606 * a different number of times from (successful) calls to _reserve().
608 * The only error here arises if the doorbell hardware isn't functioning
609 * as expected, which really shouln't happen.
611 static void i915_guc_submit(struct drm_i915_gem_request *rq)
613 unsigned int engine_id = rq->engine->id;
614 struct intel_guc *guc = &rq->i915->guc;
615 struct i915_guc_client *client = guc->execbuf_client;
618 spin_lock(&client->wq_lock);
619 guc_wq_item_append(client, rq);
620 b_ret = guc_ring_doorbell(client);
622 client->submissions[engine_id] += 1;
623 client->retcode = b_ret;
627 guc->submissions[engine_id] += 1;
628 guc->last_seqno[engine_id] = rq->fence.seqno;
629 spin_unlock(&client->wq_lock);
633 * Everything below here is concerned with setup & teardown, and is
634 * therefore not part of the somewhat time-critical batch-submission
635 * path of i915_guc_submit() above.
639 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
641 * @size: size of area to allocate (both virtual space and memory)
643 * This is a wrapper to create an object for use with the GuC. In order to
644 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
645 * both some backing storage and a range inside the Global GTT. We must pin
646 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
647 * range is reserved inside GuC.
649 * Return: A i915_vma if successful, otherwise an ERR_PTR.
651 static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
653 struct drm_i915_private *dev_priv = guc_to_i915(guc);
654 struct drm_i915_gem_object *obj;
655 struct i915_vma *vma;
658 obj = i915_gem_object_create(&dev_priv->drm, size);
660 return ERR_CAST(obj);
662 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
666 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
667 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
673 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
674 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
679 i915_gem_object_put(obj);
684 guc_client_free(struct drm_i915_private *dev_priv,
685 struct i915_guc_client *client)
687 struct intel_guc *guc = &dev_priv->guc;
693 * XXX: wait for any outstanding submissions before freeing memory.
694 * Be sure to drop any locks
697 if (client->client_base) {
699 * If we got as far as setting up a doorbell, make sure we
700 * shut it down before unmapping & deallocating the memory.
702 guc_disable_doorbell(guc, client);
704 kunmap(kmap_to_page(client->client_base));
707 i915_vma_unpin_and_release(&client->vma);
709 if (client->ctx_index != GUC_INVALID_CTX_ID) {
710 guc_ctx_desc_fini(guc, client);
711 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
717 /* Check that a doorbell register is in the expected state */
718 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
720 struct drm_i915_private *dev_priv = guc_to_i915(guc);
721 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
722 uint32_t value = I915_READ(drbreg);
723 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
724 bool expected = test_bit(db_id, guc->doorbell_bitmap);
726 if (enabled == expected)
729 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
730 db_id, drbreg.reg, value,
731 expected ? "active" : "inactive");
737 * Borrow the first client to set up & tear down each unused doorbell
738 * in turn, to ensure that all doorbell h/w is (re)initialised.
740 static void guc_init_doorbell_hw(struct intel_guc *guc)
742 struct i915_guc_client *client = guc->execbuf_client;
746 /* Save client's original doorbell selection */
747 db_id = client->doorbell_id;
749 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
750 /* Skip if doorbell is OK */
751 if (guc_doorbell_check(guc, i))
754 err = guc_update_doorbell_id(guc, client, i);
756 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
760 /* Restore to original value */
761 err = guc_update_doorbell_id(guc, client, db_id);
763 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
766 /* Read back & verify all doorbell registers */
767 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
768 (void)guc_doorbell_check(guc, i);
772 * guc_client_alloc() - Allocate an i915_guc_client
773 * @dev_priv: driver private data structure
774 * @engines: The set of engines to enable for this client
775 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
776 * The kernel client to replace ExecList submission is created with
777 * NORMAL priority. Priority of a client for scheduler can be HIGH,
778 * while a preemption context can use CRITICAL.
779 * @ctx: the context that owns the client (we use the default render
782 * Return: An i915_guc_client object if success, else NULL.
784 static struct i915_guc_client *
785 guc_client_alloc(struct drm_i915_private *dev_priv,
788 struct i915_gem_context *ctx)
790 struct i915_guc_client *client;
791 struct intel_guc *guc = &dev_priv->guc;
792 struct i915_vma *vma;
795 client = kzalloc(sizeof(*client), GFP_KERNEL);
801 client->engines = engines;
802 client->priority = priority;
803 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
805 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
806 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
807 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
808 client->ctx_index = GUC_INVALID_CTX_ID;
812 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
813 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
817 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
819 client->client_base = kmap(i915_vma_first_page(vma));
821 spin_lock_init(&client->wq_lock);
822 client->wq_offset = GUC_DB_SIZE;
823 client->wq_size = GUC_WQ_SIZE;
825 db_id = select_doorbell_register(guc, client->priority);
826 if (db_id == GUC_INVALID_DOORBELL_ID)
827 /* XXX: evict a doorbell instead? */
830 client->doorbell_offset = select_doorbell_cacheline(guc);
833 * Since the doorbell only requires a single cacheline, we can save
834 * space by putting the application process descriptor in the same
835 * page. Use the half of the page that doesn't include the doorbell.
837 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
838 client->proc_desc_offset = 0;
840 client->proc_desc_offset = (GUC_DB_SIZE / 2);
842 guc_proc_desc_init(guc, client);
843 guc_ctx_desc_init(guc, client);
844 if (guc_init_doorbell(guc, client, db_id))
847 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
848 priority, client, client->engines, client->ctx_index);
849 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
850 client->doorbell_id, client->doorbell_offset);
855 guc_client_free(dev_priv, client);
859 static void guc_move_to_next_buf(struct intel_guc *guc)
863 static void *guc_get_write_buffer(struct intel_guc *guc)
868 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
871 case GUC_ISR_LOG_BUFFER:
872 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
873 case GUC_DPC_LOG_BUFFER:
874 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
875 case GUC_CRASH_DUMP_LOG_BUFFER:
876 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
884 static void guc_read_update_log_buffer(struct intel_guc *guc)
886 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
887 struct guc_log_buffer_state log_buf_state_local;
888 unsigned int buffer_size, write_offset;
889 enum guc_log_buffer_type type;
890 void *src_data, *dst_data;
892 if (WARN_ON(!guc->log.buf_addr))
895 /* Get the pointer to shared GuC log buffer */
896 log_buf_state = src_data = guc->log.buf_addr;
898 /* Get the pointer to local buffer to store the logs */
899 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
901 /* Actual logs are present from the 2nd page */
902 src_data += PAGE_SIZE;
903 dst_data += PAGE_SIZE;
905 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
906 /* Make a copy of the state structure, inside GuC log buffer
907 * (which is uncached mapped), on the stack to avoid reading
908 * from it multiple times.
910 memcpy(&log_buf_state_local, log_buf_state,
911 sizeof(struct guc_log_buffer_state));
912 buffer_size = guc_get_log_buffer_size(type);
913 write_offset = log_buf_state_local.sampled_write_ptr;
915 /* Update the state of shared log buffer */
916 log_buf_state->read_ptr = write_offset;
917 log_buf_state->flush_to_file = 0;
920 if (unlikely(!log_buf_snapshot_state))
923 /* First copy the state structure in snapshot buffer */
924 memcpy(log_buf_snapshot_state, &log_buf_state_local,
925 sizeof(struct guc_log_buffer_state));
927 /* The write pointer could have been updated by GuC firmware,
928 * after sending the flush interrupt to Host, for consistency
929 * set write pointer value to same value of sampled_write_ptr
930 * in the snapshot buffer.
932 log_buf_snapshot_state->write_ptr = write_offset;
933 log_buf_snapshot_state++;
935 /* Now copy the actual logs. */
936 memcpy(dst_data, src_data, buffer_size);
938 src_data += buffer_size;
939 dst_data += buffer_size;
941 /* FIXME: invalidate/flush for log buffer needed */
944 if (log_buf_snapshot_state)
945 guc_move_to_next_buf(guc);
948 static void guc_capture_logs_work(struct work_struct *work)
950 struct drm_i915_private *dev_priv =
951 container_of(work, struct drm_i915_private, guc.log.flush_work);
953 i915_guc_capture_logs(dev_priv);
956 static void guc_log_cleanup(struct intel_guc *guc)
958 struct drm_i915_private *dev_priv = guc_to_i915(guc);
960 lockdep_assert_held(&dev_priv->drm.struct_mutex);
962 /* First disable the flush interrupt */
963 gen9_disable_guc_interrupts(dev_priv);
965 if (guc->log.flush_wq)
966 destroy_workqueue(guc->log.flush_wq);
968 guc->log.flush_wq = NULL;
970 if (guc->log.buf_addr)
971 i915_gem_object_unpin_map(guc->log.vma->obj);
973 guc->log.buf_addr = NULL;
976 static int guc_log_create_extras(struct intel_guc *guc)
978 struct drm_i915_private *dev_priv = guc_to_i915(guc);
982 lockdep_assert_held(&dev_priv->drm.struct_mutex);
985 if (i915.guc_log_level < 0)
988 if (!guc->log.buf_addr) {
989 /* Create a vmalloc mapping of log buffer pages */
990 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WB);
992 ret = PTR_ERR(vaddr);
993 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
997 guc->log.buf_addr = vaddr;
1000 if (!guc->log.flush_wq) {
1001 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
1003 /* Need a dedicated wq to process log buffer flush interrupts
1004 * from GuC without much delay so as to avoid any loss of logs.
1006 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log", WQ_HIGHPRI);
1007 if (guc->log.flush_wq == NULL) {
1008 DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
1016 static void guc_log_create(struct intel_guc *guc)
1018 struct i915_vma *vma;
1019 unsigned long offset;
1020 uint32_t size, flags;
1022 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
1023 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
1025 /* The first page is to save log buffer state. Allocate one
1026 * extra page for others in case for overlap */
1027 size = (1 + GUC_LOG_DPC_PAGES + 1 +
1028 GUC_LOG_ISR_PAGES + 1 +
1029 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
1033 vma = guc_allocate_vma(guc, size);
1035 /* logging will be off */
1036 i915.guc_log_level = -1;
1042 if (guc_log_create_extras(guc)) {
1043 guc_log_cleanup(guc);
1044 i915_vma_unpin_and_release(&guc->log.vma);
1045 i915.guc_log_level = -1;
1050 /* each allocated unit is a page */
1051 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
1052 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
1053 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
1054 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
1056 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
1057 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
1060 static void guc_policies_init(struct guc_policies *policies)
1062 struct guc_policy *policy;
1065 policies->dpc_promote_time = 500000;
1066 policies->max_num_work_items = POLICY_MAX_NUM_WI;
1068 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
1069 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
1070 policy = &policies->policy[p][i];
1072 policy->execution_quantum = 1000000;
1073 policy->preemption_time = 500000;
1074 policy->fault_time = 250000;
1075 policy->policy_flags = 0;
1079 policies->is_valid = 1;
1082 static void guc_addon_create(struct intel_guc *guc)
1084 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1085 struct i915_vma *vma;
1086 struct guc_ads *ads;
1087 struct guc_policies *policies;
1088 struct guc_mmio_reg_state *reg_state;
1089 struct intel_engine_cs *engine;
1090 enum intel_engine_id id;
1094 /* The ads obj includes the struct itself and buffers passed to GuC */
1095 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
1096 sizeof(struct guc_mmio_reg_state) +
1097 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
1101 vma = guc_allocate_vma(guc, PAGE_ALIGN(size));
1108 page = i915_vma_first_page(vma);
1112 * The GuC requires a "Golden Context" when it reinitialises
1113 * engines after a reset. Here we use the Render ring default
1114 * context, which must already exist and be pinned in the GGTT,
1115 * so its address won't change after we've told the GuC where
1118 engine = dev_priv->engine[RCS];
1119 ads->golden_context_lrca = engine->status_page.ggtt_offset;
1121 for_each_engine(engine, dev_priv, id)
1122 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
1124 /* GuC scheduling policies */
1125 policies = (void *)ads + sizeof(struct guc_ads);
1126 guc_policies_init(policies);
1128 ads->scheduler_policies =
1129 i915_ggtt_offset(vma) + sizeof(struct guc_ads);
1131 /* MMIO reg state */
1132 reg_state = (void *)policies + sizeof(struct guc_policies);
1134 for_each_engine(engine, dev_priv, id) {
1135 reg_state->mmio_white_list[engine->guc_id].mmio_start =
1136 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
1138 /* Nothing to be saved or restored for now. */
1139 reg_state->mmio_white_list[engine->guc_id].count = 0;
1142 ads->reg_state_addr = ads->scheduler_policies +
1143 sizeof(struct guc_policies);
1145 ads->reg_state_buffer = ads->reg_state_addr +
1146 sizeof(struct guc_mmio_reg_state);
1152 * Set up the memory resources to be shared with the GuC. At this point,
1153 * we require just one object that can be mapped through the GGTT.
1155 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
1157 const size_t ctxsize = sizeof(struct guc_context_desc);
1158 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
1159 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
1160 struct intel_guc *guc = &dev_priv->guc;
1161 struct i915_vma *vma;
1163 /* Wipe bitmap & delete client in case of reinitialisation */
1164 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
1165 i915_guc_submission_disable(dev_priv);
1167 if (!i915.enable_guc_submission)
1168 return 0; /* not enabled */
1170 if (guc->ctx_pool_vma)
1171 return 0; /* already allocated */
1173 vma = guc_allocate_vma(guc, gemsize);
1175 return PTR_ERR(vma);
1177 guc->ctx_pool_vma = vma;
1178 ida_init(&guc->ctx_ids);
1179 guc_log_create(guc);
1180 guc_addon_create(guc);
1185 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1187 struct intel_guc *guc = &dev_priv->guc;
1188 struct drm_i915_gem_request *request;
1189 struct i915_guc_client *client;
1190 struct intel_engine_cs *engine;
1191 enum intel_engine_id id;
1193 /* client for execbuf submission */
1194 client = guc_client_alloc(dev_priv,
1195 INTEL_INFO(dev_priv)->ring_mask,
1196 GUC_CTX_PRIORITY_KMD_NORMAL,
1197 dev_priv->kernel_context);
1199 DRM_ERROR("Failed to create normal GuC client!\n");
1203 guc->execbuf_client = client;
1204 host2guc_sample_forcewake(guc, client);
1205 guc_init_doorbell_hw(guc);
1207 /* Take over from manual control of ELSP (execlists) */
1208 for_each_engine(engine, dev_priv, id) {
1209 engine->submit_request = i915_guc_submit;
1211 /* Replay the current set of previously submitted requests */
1212 list_for_each_entry(request, &engine->request_list, link) {
1213 client->wq_rsvd += sizeof(struct guc_wq_item);
1214 if (i915_sw_fence_done(&request->submit))
1215 i915_guc_submit(request);
1222 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1224 struct intel_guc *guc = &dev_priv->guc;
1226 if (!guc->execbuf_client)
1229 /* Revert back to manual ELSP submission */
1230 intel_execlists_enable_submission(dev_priv);
1232 guc_client_free(dev_priv, guc->execbuf_client);
1233 guc->execbuf_client = NULL;
1236 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1238 struct intel_guc *guc = &dev_priv->guc;
1240 i915_vma_unpin_and_release(&guc->ads_vma);
1241 guc_log_cleanup(guc);
1242 i915_vma_unpin_and_release(&guc->log.vma);
1244 if (guc->ctx_pool_vma)
1245 ida_destroy(&guc->ctx_ids);
1246 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
1250 * intel_guc_suspend() - notify GuC entering suspend state
1253 int intel_guc_suspend(struct drm_device *dev)
1255 struct drm_i915_private *dev_priv = to_i915(dev);
1256 struct intel_guc *guc = &dev_priv->guc;
1257 struct i915_gem_context *ctx;
1260 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1263 gen9_disable_guc_interrupts(dev_priv);
1265 ctx = dev_priv->kernel_context;
1267 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
1268 /* any value greater than GUC_POWER_D0 */
1269 data[1] = GUC_POWER_D1;
1270 /* first page is shared data with GuC */
1271 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1273 return host2guc_action(guc, data, ARRAY_SIZE(data));
1278 * intel_guc_resume() - notify GuC resuming from suspend state
1281 int intel_guc_resume(struct drm_device *dev)
1283 struct drm_i915_private *dev_priv = to_i915(dev);
1284 struct intel_guc *guc = &dev_priv->guc;
1285 struct i915_gem_context *ctx;
1288 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1291 if (i915.guc_log_level >= 0)
1292 gen9_enable_guc_interrupts(dev_priv);
1294 ctx = dev_priv->kernel_context;
1296 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
1297 data[1] = GUC_POWER_D0;
1298 /* first page is shared data with GuC */
1299 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1301 return host2guc_action(guc, data, ARRAY_SIZE(data));
1304 void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
1306 guc_read_update_log_buffer(&dev_priv->guc);
1308 /* Generally device is expected to be active only at this
1309 * time, so get/put should be really quick.
1311 intel_runtime_pm_get(dev_priv);
1312 host2guc_logbuffer_flush_complete(&dev_priv->guc);
1313 intel_runtime_pm_put(dev_priv);