2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
26 #include <linux/debugfs.h>
27 #include <linux/relay.h>
29 #include "intel_guc.h"
32 * DOC: GuC-based command submission
35 * We use the term client to avoid confusion with contexts. A i915_guc_client is
36 * equivalent to GuC object guc_context_desc. This context descriptor is
37 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
38 * and workqueue for it. Also the process descriptor (guc_process_desc), which
39 * is mapped to client space. So the client can write Work Item then ring the
42 * To simplify the implementation, we allocate one gem object that contains all
43 * pages for doorbell, process descriptor and workqueue.
45 * The Scratch registers:
46 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
47 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
48 * triggers an interrupt on the GuC via another register write (0xC4C8).
49 * Firmware writes a success/fail code back to the action register after
50 * processes the request. The kernel driver polls waiting for this update and
52 * See host2guc_action()
55 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
56 * mapped into process space.
59 * There are several types of work items that the host may place into a
60 * workqueue, each with its own requirements and limitations. Currently only
61 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
62 * represents in-order queue. The kernel driver packs ring tail pointer and an
63 * ELSP context descriptor dword into Work Item.
64 * See guc_wq_item_append()
69 * Read GuC command/status register (SOFT_SCRATCH_0)
70 * Return true if it contains a response rather than a command
72 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
75 u32 val = I915_READ(SOFT_SCRATCH(0));
77 return GUC2HOST_IS_RESPONSE(val);
80 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
82 struct drm_i915_private *dev_priv = guc_to_i915(guc);
87 if (WARN_ON(len < 1 || len > 15))
90 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
92 dev_priv->guc.action_count += 1;
93 dev_priv->guc.action_cmd = data[0];
95 for (i = 0; i < len; i++)
96 I915_WRITE(SOFT_SCRATCH(i), data[i]);
98 POSTING_READ(SOFT_SCRATCH(i - 1));
100 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
103 * Fast commands should complete in less than 10us, so sample quickly
104 * up to that length of time, then switch to a slower sleep-wait loop.
105 * No HOST2GUC command should ever take longer than 10ms.
107 ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
109 ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
110 if (status != GUC2HOST_STATUS_SUCCESS) {
112 * Either the GuC explicitly returned an error (which
113 * we convert to -EIO here) or no response at all was
114 * received within the timeout limit (-ETIMEDOUT)
116 if (ret != -ETIMEDOUT)
119 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
120 data[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
122 dev_priv->guc.action_fail += 1;
123 dev_priv->guc.action_err = ret;
125 dev_priv->guc.action_status = status;
127 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
133 * Tell the GuC to allocate or deallocate a specific doorbell
136 static int host2guc_allocate_doorbell(struct intel_guc *guc,
137 struct i915_guc_client *client)
141 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
142 data[1] = client->ctx_index;
144 return host2guc_action(guc, data, 2);
147 static int host2guc_release_doorbell(struct intel_guc *guc,
148 struct i915_guc_client *client)
152 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
153 data[1] = client->ctx_index;
155 return host2guc_action(guc, data, 2);
158 static int host2guc_sample_forcewake(struct intel_guc *guc,
159 struct i915_guc_client *client)
161 struct drm_i915_private *dev_priv = guc_to_i915(guc);
164 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
165 /* WaRsDisableCoarsePowerGating:skl,bxt */
166 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
169 /* bit 0 and 1 are for Render and Media domain separately */
170 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
172 return host2guc_action(guc, data, ARRAY_SIZE(data));
175 static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
179 data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
181 return host2guc_action(guc, data, 1);
185 * Initialise, update, or clear doorbell data shared with the GuC
187 * These functions modify shared data and so need access to the mapped
188 * client object which contains the page being used for the doorbell
191 static int guc_update_doorbell_id(struct intel_guc *guc,
192 struct i915_guc_client *client,
195 struct sg_table *sg = guc->ctx_pool_vma->pages;
196 void *doorbell_bitmap = guc->doorbell_bitmap;
197 struct guc_doorbell_info *doorbell;
198 struct guc_context_desc desc;
201 doorbell = client->client_base + client->doorbell_offset;
203 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
204 test_bit(client->doorbell_id, doorbell_bitmap)) {
205 /* Deactivate the old doorbell */
206 doorbell->db_status = GUC_DOORBELL_DISABLED;
207 (void)host2guc_release_doorbell(guc, client);
208 __clear_bit(client->doorbell_id, doorbell_bitmap);
211 /* Update the GuC's idea of the doorbell ID */
212 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
213 sizeof(desc) * client->ctx_index);
214 if (len != sizeof(desc))
217 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
218 sizeof(desc) * client->ctx_index);
219 if (len != sizeof(desc))
222 client->doorbell_id = new_id;
223 if (new_id == GUC_INVALID_DOORBELL_ID)
226 /* Activate the new doorbell */
227 __set_bit(new_id, doorbell_bitmap);
228 doorbell->cookie = 0;
229 doorbell->db_status = GUC_DOORBELL_ENABLED;
230 return host2guc_allocate_doorbell(guc, client);
233 static int guc_init_doorbell(struct intel_guc *guc,
234 struct i915_guc_client *client,
237 return guc_update_doorbell_id(guc, client, db_id);
240 static void guc_disable_doorbell(struct intel_guc *guc,
241 struct i915_guc_client *client)
243 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
245 /* XXX: wait for any interrupts */
246 /* XXX: wait for workqueue to drain */
250 select_doorbell_register(struct intel_guc *guc, uint32_t priority)
253 * The bitmap tracks which doorbell registers are currently in use.
254 * It is split into two halves; the first half is used for normal
255 * priority contexts, the second half for high-priority ones.
256 * Note that logically higher priorities are numerically less than
257 * normal ones, so the test below means "is it high-priority?"
259 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
260 const uint16_t half = GUC_MAX_DOORBELLS / 2;
261 const uint16_t start = hi_pri ? half : 0;
262 const uint16_t end = start + half;
265 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
267 id = GUC_INVALID_DOORBELL_ID;
269 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
270 hi_pri ? "high" : "normal", id);
276 * Select, assign and relase doorbell cachelines
278 * These functions track which doorbell cachelines are in use.
279 * The data they manipulate is protected by the host2guc lock.
282 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
284 const uint32_t cacheline_size = cache_line_size();
287 /* Doorbell uses a single cache line within a page */
288 offset = offset_in_page(guc->db_cacheline);
290 /* Moving to next cache line to reduce contention */
291 guc->db_cacheline += cacheline_size;
293 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
294 offset, guc->db_cacheline, cacheline_size);
300 * Initialise the process descriptor shared with the GuC firmware.
302 static void guc_proc_desc_init(struct intel_guc *guc,
303 struct i915_guc_client *client)
305 struct guc_process_desc *desc;
307 desc = client->client_base + client->proc_desc_offset;
309 memset(desc, 0, sizeof(*desc));
312 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
313 * space for ring3 clients (set them as in mmap_ioctl) or kernel
314 * space for kernel clients (map on demand instead? May make debug
315 * easier to have it mapped).
317 desc->wq_base_addr = 0;
318 desc->db_base_addr = 0;
320 desc->context_id = client->ctx_index;
321 desc->wq_size_bytes = client->wq_size;
322 desc->wq_status = WQ_STATUS_ACTIVE;
323 desc->priority = client->priority;
327 * Initialise/clear the context descriptor shared with the GuC firmware.
329 * This descriptor tells the GuC where (in GGTT space) to find the important
330 * data structures relating to this client (doorbell, process descriptor,
334 static void guc_ctx_desc_init(struct intel_guc *guc,
335 struct i915_guc_client *client)
337 struct drm_i915_private *dev_priv = guc_to_i915(guc);
338 struct intel_engine_cs *engine;
339 struct i915_gem_context *ctx = client->owner;
340 struct guc_context_desc desc;
345 memset(&desc, 0, sizeof(desc));
347 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
348 desc.context_id = client->ctx_index;
349 desc.priority = client->priority;
350 desc.db_id = client->doorbell_id;
352 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
353 struct intel_context *ce = &ctx->engine[engine->id];
354 uint32_t guc_engine_id = engine->guc_id;
355 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
357 /* TODO: We have a design issue to be solved here. Only when we
358 * receive the first batch, we know which engine is used by the
359 * user. But here GuC expects the lrc and ring to be pinned. It
360 * is not an issue for default context, which is the only one
361 * for now who owns a GuC client. But for future owner of GuC
362 * client, need to make sure lrc is pinned prior to enter here.
365 break; /* XXX: continue? */
367 lrc->context_desc = lower_32_bits(ce->lrc_desc);
369 /* The state page is after PPHWSP */
371 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
372 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
373 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
375 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma);
376 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
377 lrc->ring_next_free_location = lrc->ring_begin;
378 lrc->ring_current_tail_pointer_value = 0;
380 desc.engines_used |= (1 << guc_engine_id);
383 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
384 client->engines, desc.engines_used);
385 WARN_ON(desc.engines_used == 0);
388 * The doorbell, process descriptor, and workqueue are all parts
389 * of the client object, which the GuC will reference via the GGTT
391 gfx_addr = i915_ggtt_offset(client->vma);
392 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
393 client->doorbell_offset;
394 desc.db_trigger_cpu = (uintptr_t)client->client_base +
395 client->doorbell_offset;
396 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
397 desc.process_desc = gfx_addr + client->proc_desc_offset;
398 desc.wq_addr = gfx_addr + client->wq_offset;
399 desc.wq_size = client->wq_size;
402 * XXX: Take LRCs from an existing context if this is not an
403 * IsKMDCreatedContext client
405 desc.desc_private = (uintptr_t)client;
407 /* Pool context is pinned already */
408 sg = guc->ctx_pool_vma->pages;
409 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
410 sizeof(desc) * client->ctx_index);
413 static void guc_ctx_desc_fini(struct intel_guc *guc,
414 struct i915_guc_client *client)
416 struct guc_context_desc desc;
419 memset(&desc, 0, sizeof(desc));
421 sg = guc->ctx_pool_vma->pages;
422 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
423 sizeof(desc) * client->ctx_index);
427 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
428 * @request: request associated with the commands
430 * Return: 0 if space is available
431 * -EAGAIN if space is not currently available
433 * This function must be called (and must return 0) before a request
434 * is submitted to the GuC via i915_guc_submit() below. Once a result
435 * of 0 has been returned, it must be balanced by a corresponding
438 * Reservation allows the caller to determine in advance that space
439 * will be available for the next submission before committing resources
440 * to it, and helps avoid late failures with complicated recovery paths.
442 int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
444 const size_t wqi_size = sizeof(struct guc_wq_item);
445 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
446 struct guc_process_desc *desc = gc->client_base + gc->proc_desc_offset;
450 spin_lock(&gc->wq_lock);
451 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
452 freespace -= gc->wq_rsvd;
453 if (likely(freespace >= wqi_size)) {
454 gc->wq_rsvd += wqi_size;
460 spin_unlock(&gc->wq_lock);
465 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
467 const size_t wqi_size = sizeof(struct guc_wq_item);
468 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
470 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
472 spin_lock(&gc->wq_lock);
473 gc->wq_rsvd -= wqi_size;
474 spin_unlock(&gc->wq_lock);
477 /* Construct a Work Item and append it to the GuC's Work Queue */
478 static void guc_wq_item_append(struct i915_guc_client *gc,
479 struct drm_i915_gem_request *rq)
481 /* wqi_len is in DWords, and does not include the one-word header */
482 const size_t wqi_size = sizeof(struct guc_wq_item);
483 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
484 struct intel_engine_cs *engine = rq->engine;
485 struct guc_process_desc *desc;
486 struct guc_wq_item *wqi;
488 u32 freespace, tail, wq_off, wq_page;
490 desc = gc->client_base + gc->proc_desc_offset;
492 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
493 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
494 GEM_BUG_ON(freespace < wqi_size);
496 /* The GuC firmware wants the tail index in QWords, not bytes */
498 GEM_BUG_ON(tail & 7);
500 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
502 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
503 * should not have the case where structure wqi is across page, neither
504 * wrapped to the beginning. This simplifies the implementation below.
506 * XXX: if not the case, we need save data to a temp wqi and copy it to
507 * workqueue buffer dw by dw.
509 BUILD_BUG_ON(wqi_size != 16);
510 GEM_BUG_ON(gc->wq_rsvd < wqi_size);
512 /* postincrement WQ tail for next time */
513 wq_off = gc->wq_tail;
514 GEM_BUG_ON(wq_off & (wqi_size - 1));
515 gc->wq_tail += wqi_size;
516 gc->wq_tail &= gc->wq_size - 1;
517 gc->wq_rsvd -= wqi_size;
519 /* WQ starts from the page after doorbell / process_desc */
520 wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT;
521 wq_off &= PAGE_SIZE - 1;
522 base = kmap_atomic(i915_gem_object_get_page(gc->vma->obj, wq_page));
523 wqi = (struct guc_wq_item *)((char *)base + wq_off);
525 /* Now fill in the 4-word work queue item */
526 wqi->header = WQ_TYPE_INORDER |
527 (wqi_len << WQ_LEN_SHIFT) |
528 (engine->guc_id << WQ_TARGET_SHIFT) |
531 /* The GuC wants only the low-order word of the context descriptor */
532 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
534 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
535 wqi->fence_id = rq->fence.seqno;
540 static int guc_ring_doorbell(struct i915_guc_client *gc)
542 struct guc_process_desc *desc;
543 union guc_doorbell_qw db_cmp, db_exc, db_ret;
544 union guc_doorbell_qw *db;
545 int attempt = 2, ret = -EAGAIN;
547 desc = gc->client_base + gc->proc_desc_offset;
549 /* Update the tail so it is visible to GuC */
550 desc->tail = gc->wq_tail;
553 db_cmp.db_status = GUC_DOORBELL_ENABLED;
554 db_cmp.cookie = gc->cookie;
556 /* cookie to be updated */
557 db_exc.db_status = GUC_DOORBELL_ENABLED;
558 db_exc.cookie = gc->cookie + 1;
559 if (db_exc.cookie == 0)
562 /* pointer of current doorbell cacheline */
563 db = gc->client_base + gc->doorbell_offset;
566 /* lets ring the doorbell */
567 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
568 db_cmp.value_qw, db_exc.value_qw);
570 /* if the exchange was successfully executed */
571 if (db_ret.value_qw == db_cmp.value_qw) {
572 /* db was successfully rung */
573 gc->cookie = db_exc.cookie;
578 /* XXX: doorbell was lost and need to acquire it again */
579 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
582 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
583 db_cmp.cookie, db_ret.cookie);
585 /* update the cookie to newly read cookie from GuC */
586 db_cmp.cookie = db_ret.cookie;
587 db_exc.cookie = db_ret.cookie + 1;
588 if (db_exc.cookie == 0)
596 * i915_guc_submit() - Submit commands through GuC
597 * @rq: request associated with the commands
599 * Return: 0 on success, otherwise an errno.
600 * (Note: nonzero really shouldn't happen!)
602 * The caller must have already called i915_guc_wq_reserve() above with
603 * a result of 0 (success), guaranteeing that there is space in the work
604 * queue for the new request, so enqueuing the item cannot fail.
606 * Bad Things Will Happen if the caller violates this protocol e.g. calls
607 * submit() when _reserve() says there's no space, or calls _submit()
608 * a different number of times from (successful) calls to _reserve().
610 * The only error here arises if the doorbell hardware isn't functioning
611 * as expected, which really shouln't happen.
613 static void i915_guc_submit(struct drm_i915_gem_request *rq)
615 unsigned int engine_id = rq->engine->id;
616 struct intel_guc *guc = &rq->i915->guc;
617 struct i915_guc_client *client = guc->execbuf_client;
620 spin_lock(&client->wq_lock);
621 guc_wq_item_append(client, rq);
622 b_ret = guc_ring_doorbell(client);
624 client->submissions[engine_id] += 1;
625 client->retcode = b_ret;
629 guc->submissions[engine_id] += 1;
630 guc->last_seqno[engine_id] = rq->fence.seqno;
631 spin_unlock(&client->wq_lock);
635 * Everything below here is concerned with setup & teardown, and is
636 * therefore not part of the somewhat time-critical batch-submission
637 * path of i915_guc_submit() above.
641 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
643 * @size: size of area to allocate (both virtual space and memory)
645 * This is a wrapper to create an object for use with the GuC. In order to
646 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
647 * both some backing storage and a range inside the Global GTT. We must pin
648 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
649 * range is reserved inside GuC.
651 * Return: A i915_vma if successful, otherwise an ERR_PTR.
653 static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
655 struct drm_i915_private *dev_priv = guc_to_i915(guc);
656 struct drm_i915_gem_object *obj;
657 struct i915_vma *vma;
660 obj = i915_gem_object_create(&dev_priv->drm, size);
662 return ERR_CAST(obj);
664 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
668 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
669 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
675 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
676 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
681 i915_gem_object_put(obj);
686 guc_client_free(struct drm_i915_private *dev_priv,
687 struct i915_guc_client *client)
689 struct intel_guc *guc = &dev_priv->guc;
695 * XXX: wait for any outstanding submissions before freeing memory.
696 * Be sure to drop any locks
699 if (client->client_base) {
701 * If we got as far as setting up a doorbell, make sure we
702 * shut it down before unmapping & deallocating the memory.
704 guc_disable_doorbell(guc, client);
706 kunmap(kmap_to_page(client->client_base));
709 i915_vma_unpin_and_release(&client->vma);
711 if (client->ctx_index != GUC_INVALID_CTX_ID) {
712 guc_ctx_desc_fini(guc, client);
713 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
719 /* Check that a doorbell register is in the expected state */
720 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
722 struct drm_i915_private *dev_priv = guc_to_i915(guc);
723 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
724 uint32_t value = I915_READ(drbreg);
725 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
726 bool expected = test_bit(db_id, guc->doorbell_bitmap);
728 if (enabled == expected)
731 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
732 db_id, drbreg.reg, value,
733 expected ? "active" : "inactive");
739 * Borrow the first client to set up & tear down each unused doorbell
740 * in turn, to ensure that all doorbell h/w is (re)initialised.
742 static void guc_init_doorbell_hw(struct intel_guc *guc)
744 struct i915_guc_client *client = guc->execbuf_client;
748 /* Save client's original doorbell selection */
749 db_id = client->doorbell_id;
751 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
752 /* Skip if doorbell is OK */
753 if (guc_doorbell_check(guc, i))
756 err = guc_update_doorbell_id(guc, client, i);
758 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
762 /* Restore to original value */
763 err = guc_update_doorbell_id(guc, client, db_id);
765 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
768 /* Read back & verify all doorbell registers */
769 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
770 (void)guc_doorbell_check(guc, i);
774 * guc_client_alloc() - Allocate an i915_guc_client
775 * @dev_priv: driver private data structure
776 * @engines: The set of engines to enable for this client
777 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
778 * The kernel client to replace ExecList submission is created with
779 * NORMAL priority. Priority of a client for scheduler can be HIGH,
780 * while a preemption context can use CRITICAL.
781 * @ctx: the context that owns the client (we use the default render
784 * Return: An i915_guc_client object if success, else NULL.
786 static struct i915_guc_client *
787 guc_client_alloc(struct drm_i915_private *dev_priv,
790 struct i915_gem_context *ctx)
792 struct i915_guc_client *client;
793 struct intel_guc *guc = &dev_priv->guc;
794 struct i915_vma *vma;
797 client = kzalloc(sizeof(*client), GFP_KERNEL);
803 client->engines = engines;
804 client->priority = priority;
805 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
807 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
808 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
809 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
810 client->ctx_index = GUC_INVALID_CTX_ID;
814 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
815 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
819 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
821 client->client_base = kmap(i915_vma_first_page(vma));
823 spin_lock_init(&client->wq_lock);
824 client->wq_offset = GUC_DB_SIZE;
825 client->wq_size = GUC_WQ_SIZE;
827 db_id = select_doorbell_register(guc, client->priority);
828 if (db_id == GUC_INVALID_DOORBELL_ID)
829 /* XXX: evict a doorbell instead? */
832 client->doorbell_offset = select_doorbell_cacheline(guc);
835 * Since the doorbell only requires a single cacheline, we can save
836 * space by putting the application process descriptor in the same
837 * page. Use the half of the page that doesn't include the doorbell.
839 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
840 client->proc_desc_offset = 0;
842 client->proc_desc_offset = (GUC_DB_SIZE / 2);
844 guc_proc_desc_init(guc, client);
845 guc_ctx_desc_init(guc, client);
846 if (guc_init_doorbell(guc, client, db_id))
849 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
850 priority, client, client->engines, client->ctx_index);
851 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
852 client->doorbell_id, client->doorbell_offset);
857 guc_client_free(dev_priv, client);
862 * Sub buffer switch callback. Called whenever relay has to switch to a new
863 * sub buffer, relay stays on the same sub buffer if 0 is returned.
865 static int subbuf_start_callback(struct rchan_buf *buf,
870 /* Use no-overwrite mode by default, where relay will stop accepting
871 * new data if there are no empty sub buffers left.
872 * There is no strict synchronization enforced by relay between Consumer
873 * and Producer. In overwrite mode, there is a possibility of getting
874 * inconsistent/garbled data, the producer could be writing on to the
875 * same sub buffer from which Consumer is reading. This can't be avoided
876 * unless Consumer is fast enough and can always run in tandem with
879 if (relay_buf_full(buf))
886 * file_create() callback. Creates relay file in debugfs.
888 static struct dentry *create_buf_file_callback(const char *filename,
889 struct dentry *parent,
891 struct rchan_buf *buf,
894 struct dentry *buf_file;
899 /* This to enable the use of a single buffer for the relay channel and
900 * correspondingly have a single file exposed to User, through which
901 * it can collect the logs in order without any post-processing.
905 /* Not using the channel filename passed as an argument, since for each
906 * channel relay appends the corresponding CPU number to the filename
907 * passed in relay_open(). This should be fine as relay just needs a
908 * dentry of the file associated with the channel buffer and that file's
909 * name need not be same as the filename passed as an argument.
911 buf_file = debugfs_create_file("guc_log", mode,
912 parent, buf, &relay_file_operations);
917 * file_remove() default callback. Removes relay file in debugfs.
919 static int remove_buf_file_callback(struct dentry *dentry)
921 debugfs_remove(dentry);
925 /* relay channel callbacks */
926 static struct rchan_callbacks relay_callbacks = {
927 .subbuf_start = subbuf_start_callback,
928 .create_buf_file = create_buf_file_callback,
929 .remove_buf_file = remove_buf_file_callback,
932 static void guc_log_remove_relay_file(struct intel_guc *guc)
934 relay_close(guc->log.relay_chan);
937 static int guc_log_create_relay_file(struct intel_guc *guc)
939 struct drm_i915_private *dev_priv = guc_to_i915(guc);
940 struct rchan *guc_log_relay_chan;
941 struct dentry *log_dir;
942 size_t n_subbufs, subbuf_size;
944 /* For now create the log file in /sys/kernel/debug/dri/0 dir */
945 log_dir = dev_priv->drm.primary->debugfs_root;
947 /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
948 * not mounted and so can't create the relay file.
949 * The relay API seems to fit well with debugfs only, for availing relay
950 * there are 3 requirements which can be met for debugfs file only in a
951 * straightforward/clean manner :-
952 * i) Need the associated dentry pointer of the file, while opening the
954 * ii) Should be able to use 'relay_file_operations' fops for the file.
955 * iii) Set the 'i_private' field of file's inode to the pointer of
956 * relay channel buffer.
959 DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
963 /* Keep the size of sub buffers same as shared log buffer */
964 subbuf_size = guc->log.vma->obj->base.size;
966 /* Store up to 8 snapshots, which is large enough to buffer sufficient
967 * boot time logs and provides enough leeway to User, in terms of
968 * latency, for consuming the logs from relay. Also doesn't take
969 * up too much memory.
973 guc_log_relay_chan = relay_open("guc_log", log_dir, subbuf_size,
974 n_subbufs, &relay_callbacks, dev_priv);
975 if (!guc_log_relay_chan) {
976 DRM_ERROR("Couldn't create relay chan for GuC logging\n");
980 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
981 /* FIXME: Cover the update under a lock ? */
982 guc->log.relay_chan = guc_log_relay_chan;
986 static void guc_move_to_next_buf(struct intel_guc *guc)
988 /* Make sure the updates made in the sub buffer are visible when
989 * Consumer sees the following update to offset inside the sub buffer.
993 /* All data has been written, so now move the offset of sub buffer. */
994 relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size);
996 /* Switch to the next sub buffer */
997 relay_flush(guc->log.relay_chan);
1000 static void *guc_get_write_buffer(struct intel_guc *guc)
1002 /* FIXME: Cover the check under a lock ? */
1003 if (!guc->log.relay_chan)
1006 /* Just get the base address of a new sub buffer and copy data into it
1007 * ourselves. NULL will be returned in no-overwrite mode, if all sub
1008 * buffers are full. Could have used the relay_write() to indirectly
1009 * copy the data, but that would have been bit convoluted, as we need to
1010 * write to only certain locations inside a sub buffer which cannot be
1011 * done without using relay_reserve() along with relay_write(). So its
1012 * better to use relay_reserve() alone.
1014 return relay_reserve(guc->log.relay_chan, 0);
1017 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
1020 case GUC_ISR_LOG_BUFFER:
1021 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
1022 case GUC_DPC_LOG_BUFFER:
1023 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
1024 case GUC_CRASH_DUMP_LOG_BUFFER:
1025 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
1033 static void guc_read_update_log_buffer(struct intel_guc *guc)
1035 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
1036 struct guc_log_buffer_state log_buf_state_local;
1037 unsigned int buffer_size, write_offset;
1038 enum guc_log_buffer_type type;
1039 void *src_data, *dst_data;
1041 if (WARN_ON(!guc->log.buf_addr))
1044 /* Get the pointer to shared GuC log buffer */
1045 log_buf_state = src_data = guc->log.buf_addr;
1047 /* Get the pointer to local buffer to store the logs */
1048 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
1050 /* Actual logs are present from the 2nd page */
1051 src_data += PAGE_SIZE;
1052 dst_data += PAGE_SIZE;
1054 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
1055 /* Make a copy of the state structure, inside GuC log buffer
1056 * (which is uncached mapped), on the stack to avoid reading
1057 * from it multiple times.
1059 memcpy(&log_buf_state_local, log_buf_state,
1060 sizeof(struct guc_log_buffer_state));
1061 buffer_size = guc_get_log_buffer_size(type);
1062 write_offset = log_buf_state_local.sampled_write_ptr;
1064 /* Update the state of shared log buffer */
1065 log_buf_state->read_ptr = write_offset;
1066 log_buf_state->flush_to_file = 0;
1069 if (unlikely(!log_buf_snapshot_state))
1072 /* First copy the state structure in snapshot buffer */
1073 memcpy(log_buf_snapshot_state, &log_buf_state_local,
1074 sizeof(struct guc_log_buffer_state));
1076 /* The write pointer could have been updated by GuC firmware,
1077 * after sending the flush interrupt to Host, for consistency
1078 * set write pointer value to same value of sampled_write_ptr
1079 * in the snapshot buffer.
1081 log_buf_snapshot_state->write_ptr = write_offset;
1082 log_buf_snapshot_state++;
1084 /* Now copy the actual logs. */
1085 memcpy(dst_data, src_data, buffer_size);
1087 src_data += buffer_size;
1088 dst_data += buffer_size;
1090 /* FIXME: invalidate/flush for log buffer needed */
1093 if (log_buf_snapshot_state)
1094 guc_move_to_next_buf(guc);
1096 /* Used rate limited to avoid deluge of messages, logs might be
1097 * getting consumed by User at a slow rate.
1099 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
1103 static void guc_capture_logs_work(struct work_struct *work)
1105 struct drm_i915_private *dev_priv =
1106 container_of(work, struct drm_i915_private, guc.log.flush_work);
1108 i915_guc_capture_logs(dev_priv);
1111 static void guc_log_cleanup(struct intel_guc *guc)
1113 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1115 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1117 /* First disable the flush interrupt */
1118 gen9_disable_guc_interrupts(dev_priv);
1120 if (guc->log.flush_wq)
1121 destroy_workqueue(guc->log.flush_wq);
1123 guc->log.flush_wq = NULL;
1125 if (guc->log.relay_chan)
1126 guc_log_remove_relay_file(guc);
1128 guc->log.relay_chan = NULL;
1130 if (guc->log.buf_addr)
1131 i915_gem_object_unpin_map(guc->log.vma->obj);
1133 guc->log.buf_addr = NULL;
1136 static int guc_log_create_extras(struct intel_guc *guc)
1138 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1142 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1145 if (i915.guc_log_level < 0)
1148 if (!guc->log.buf_addr) {
1149 /* Create a vmalloc mapping of log buffer pages */
1150 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WB);
1151 if (IS_ERR(vaddr)) {
1152 ret = PTR_ERR(vaddr);
1153 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
1157 guc->log.buf_addr = vaddr;
1160 if (!guc->log.flush_wq) {
1161 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
1163 /* Need a dedicated wq to process log buffer flush interrupts
1164 * from GuC without much delay so as to avoid any loss of logs.
1166 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log", WQ_HIGHPRI);
1167 if (guc->log.flush_wq == NULL) {
1168 DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
1176 static void guc_log_create(struct intel_guc *guc)
1178 struct i915_vma *vma;
1179 unsigned long offset;
1180 uint32_t size, flags;
1182 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
1183 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
1185 /* The first page is to save log buffer state. Allocate one
1186 * extra page for others in case for overlap */
1187 size = (1 + GUC_LOG_DPC_PAGES + 1 +
1188 GUC_LOG_ISR_PAGES + 1 +
1189 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
1193 vma = guc_allocate_vma(guc, size);
1195 /* logging will be off */
1196 i915.guc_log_level = -1;
1202 if (guc_log_create_extras(guc)) {
1203 guc_log_cleanup(guc);
1204 i915_vma_unpin_and_release(&guc->log.vma);
1205 i915.guc_log_level = -1;
1210 /* each allocated unit is a page */
1211 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
1212 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
1213 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
1214 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
1216 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
1217 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
1220 static int guc_log_late_setup(struct intel_guc *guc)
1222 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1225 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1227 if (i915.guc_log_level < 0)
1230 /* If log_level was set as -1 at boot time, then setup needed to
1231 * handle log buffer flush interrupts would not have been done yet,
1234 ret = guc_log_create_extras(guc);
1238 ret = guc_log_create_relay_file(guc);
1244 guc_log_cleanup(guc);
1245 /* logging will remain off */
1246 i915.guc_log_level = -1;
1250 static void guc_policies_init(struct guc_policies *policies)
1252 struct guc_policy *policy;
1255 policies->dpc_promote_time = 500000;
1256 policies->max_num_work_items = POLICY_MAX_NUM_WI;
1258 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
1259 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
1260 policy = &policies->policy[p][i];
1262 policy->execution_quantum = 1000000;
1263 policy->preemption_time = 500000;
1264 policy->fault_time = 250000;
1265 policy->policy_flags = 0;
1269 policies->is_valid = 1;
1272 static void guc_addon_create(struct intel_guc *guc)
1274 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1275 struct i915_vma *vma;
1276 struct guc_ads *ads;
1277 struct guc_policies *policies;
1278 struct guc_mmio_reg_state *reg_state;
1279 struct intel_engine_cs *engine;
1280 enum intel_engine_id id;
1284 /* The ads obj includes the struct itself and buffers passed to GuC */
1285 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
1286 sizeof(struct guc_mmio_reg_state) +
1287 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
1291 vma = guc_allocate_vma(guc, PAGE_ALIGN(size));
1298 page = i915_vma_first_page(vma);
1302 * The GuC requires a "Golden Context" when it reinitialises
1303 * engines after a reset. Here we use the Render ring default
1304 * context, which must already exist and be pinned in the GGTT,
1305 * so its address won't change after we've told the GuC where
1308 engine = dev_priv->engine[RCS];
1309 ads->golden_context_lrca = engine->status_page.ggtt_offset;
1311 for_each_engine(engine, dev_priv, id)
1312 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
1314 /* GuC scheduling policies */
1315 policies = (void *)ads + sizeof(struct guc_ads);
1316 guc_policies_init(policies);
1318 ads->scheduler_policies =
1319 i915_ggtt_offset(vma) + sizeof(struct guc_ads);
1321 /* MMIO reg state */
1322 reg_state = (void *)policies + sizeof(struct guc_policies);
1324 for_each_engine(engine, dev_priv, id) {
1325 reg_state->mmio_white_list[engine->guc_id].mmio_start =
1326 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
1328 /* Nothing to be saved or restored for now. */
1329 reg_state->mmio_white_list[engine->guc_id].count = 0;
1332 ads->reg_state_addr = ads->scheduler_policies +
1333 sizeof(struct guc_policies);
1335 ads->reg_state_buffer = ads->reg_state_addr +
1336 sizeof(struct guc_mmio_reg_state);
1342 * Set up the memory resources to be shared with the GuC. At this point,
1343 * we require just one object that can be mapped through the GGTT.
1345 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
1347 const size_t ctxsize = sizeof(struct guc_context_desc);
1348 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
1349 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
1350 struct intel_guc *guc = &dev_priv->guc;
1351 struct i915_vma *vma;
1353 /* Wipe bitmap & delete client in case of reinitialisation */
1354 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
1355 i915_guc_submission_disable(dev_priv);
1357 if (!i915.enable_guc_submission)
1358 return 0; /* not enabled */
1360 if (guc->ctx_pool_vma)
1361 return 0; /* already allocated */
1363 vma = guc_allocate_vma(guc, gemsize);
1365 return PTR_ERR(vma);
1367 guc->ctx_pool_vma = vma;
1368 ida_init(&guc->ctx_ids);
1369 guc_log_create(guc);
1370 guc_addon_create(guc);
1375 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1377 struct intel_guc *guc = &dev_priv->guc;
1378 struct drm_i915_gem_request *request;
1379 struct i915_guc_client *client;
1380 struct intel_engine_cs *engine;
1381 enum intel_engine_id id;
1383 /* client for execbuf submission */
1384 client = guc_client_alloc(dev_priv,
1385 INTEL_INFO(dev_priv)->ring_mask,
1386 GUC_CTX_PRIORITY_KMD_NORMAL,
1387 dev_priv->kernel_context);
1389 DRM_ERROR("Failed to create normal GuC client!\n");
1393 guc->execbuf_client = client;
1394 host2guc_sample_forcewake(guc, client);
1395 guc_init_doorbell_hw(guc);
1397 /* Take over from manual control of ELSP (execlists) */
1398 for_each_engine(engine, dev_priv, id) {
1399 engine->submit_request = i915_guc_submit;
1401 /* Replay the current set of previously submitted requests */
1402 list_for_each_entry(request, &engine->request_list, link) {
1403 client->wq_rsvd += sizeof(struct guc_wq_item);
1404 if (i915_sw_fence_done(&request->submit))
1405 i915_guc_submit(request);
1412 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1414 struct intel_guc *guc = &dev_priv->guc;
1416 if (!guc->execbuf_client)
1419 /* Revert back to manual ELSP submission */
1420 intel_execlists_enable_submission(dev_priv);
1422 guc_client_free(dev_priv, guc->execbuf_client);
1423 guc->execbuf_client = NULL;
1426 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1428 struct intel_guc *guc = &dev_priv->guc;
1430 i915_vma_unpin_and_release(&guc->ads_vma);
1431 i915_vma_unpin_and_release(&guc->log.vma);
1433 if (guc->ctx_pool_vma)
1434 ida_destroy(&guc->ctx_ids);
1435 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
1439 * intel_guc_suspend() - notify GuC entering suspend state
1442 int intel_guc_suspend(struct drm_device *dev)
1444 struct drm_i915_private *dev_priv = to_i915(dev);
1445 struct intel_guc *guc = &dev_priv->guc;
1446 struct i915_gem_context *ctx;
1449 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1452 gen9_disable_guc_interrupts(dev_priv);
1454 ctx = dev_priv->kernel_context;
1456 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
1457 /* any value greater than GUC_POWER_D0 */
1458 data[1] = GUC_POWER_D1;
1459 /* first page is shared data with GuC */
1460 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1462 return host2guc_action(guc, data, ARRAY_SIZE(data));
1467 * intel_guc_resume() - notify GuC resuming from suspend state
1470 int intel_guc_resume(struct drm_device *dev)
1472 struct drm_i915_private *dev_priv = to_i915(dev);
1473 struct intel_guc *guc = &dev_priv->guc;
1474 struct i915_gem_context *ctx;
1477 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1480 if (i915.guc_log_level >= 0)
1481 gen9_enable_guc_interrupts(dev_priv);
1483 ctx = dev_priv->kernel_context;
1485 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
1486 data[1] = GUC_POWER_D0;
1487 /* first page is shared data with GuC */
1488 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1490 return host2guc_action(guc, data, ARRAY_SIZE(data));
1493 void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
1495 guc_read_update_log_buffer(&dev_priv->guc);
1497 /* Generally device is expected to be active only at this
1498 * time, so get/put should be really quick.
1500 intel_runtime_pm_get(dev_priv);
1501 host2guc_logbuffer_flush_complete(&dev_priv->guc);
1502 intel_runtime_pm_put(dev_priv);
1505 void i915_guc_unregister(struct drm_i915_private *dev_priv)
1507 if (!i915.enable_guc_submission)
1510 mutex_lock(&dev_priv->drm.struct_mutex);
1511 guc_log_cleanup(&dev_priv->guc);
1512 mutex_unlock(&dev_priv->drm.struct_mutex);
1515 void i915_guc_register(struct drm_i915_private *dev_priv)
1517 if (!i915.enable_guc_submission)
1520 mutex_lock(&dev_priv->drm.struct_mutex);
1521 guc_log_late_setup(&dev_priv->guc);
1522 mutex_unlock(&dev_priv->drm.struct_mutex);