drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         assert_spin_locked(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         assert_spin_locked(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         assert_spin_locked(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         assert_spin_locked(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         assert_spin_locked(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         assert_spin_locked(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         assert_spin_locked(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 393 {
 394         return (mask & ~dev_priv->rps.pm_intr_keep);
 395 }
 396
 397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 398 {
 399         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 400                 return;
 401
 402         spin_lock_irq(&dev_priv->irq_lock);
 403         dev_priv->rps.interrupts_enabled = false;
 404
 405         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 406
 407         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 408
 409         spin_unlock_irq(&dev_priv->irq_lock);
 410         synchronize_irq(dev_priv->drm.irq);
 411
 412         /* Now that we will not be generating any more work, flush any
 413          * outsanding tasks. As we are called on the RPS idle path,
 414          * we will reset the GPU to minimum frequencies, so the current
 415          * state of the worker can be discarded.
 416          */
 417         cancel_work_sync(&dev_priv->rps.work);
 418         gen6_reset_rps_interrupts(dev_priv);
 419 }
 420
 421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 422 {
 423         spin_lock_irq(&dev_priv->irq_lock);
 424         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 425         spin_unlock_irq(&dev_priv->irq_lock);
 426 }
 427
 428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 429 {
 430         spin_lock_irq(&dev_priv->irq_lock);
 431         if (!dev_priv->guc.interrupts_enabled) {
 432                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 433                                        dev_priv->pm_guc_events);
 434                 dev_priv->guc.interrupts_enabled = true;
 435                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 436         }
 437         spin_unlock_irq(&dev_priv->irq_lock);
 438 }
 439
 440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 441 {
 442         spin_lock_irq(&dev_priv->irq_lock);
 443         dev_priv->guc.interrupts_enabled = false;
 444
 445         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 446
 447         spin_unlock_irq(&dev_priv->irq_lock);
 448         synchronize_irq(dev_priv->drm.irq);
 449
 450         gen9_reset_guc_interrupts(dev_priv);
 451 }
 452
 453 /**
 454  * bdw_update_port_irq - update DE port interrupt
 455  * @dev_priv: driver private
 456  * @interrupt_mask: mask of interrupt bits to update
 457  * @enabled_irq_mask: mask of interrupt bits to enable
 458  */
 459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 460                                 uint32_t interrupt_mask,
 461                                 uint32_t enabled_irq_mask)
 462 {
 463         uint32_t new_val;
 464         uint32_t old_val;
 465
 466         assert_spin_locked(&dev_priv->irq_lock);
 467
 468         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 469
 470         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 471                 return;
 472
 473         old_val = I915_READ(GEN8_DE_PORT_IMR);
 474
 475         new_val = old_val;
 476         new_val &= ~interrupt_mask;
 477         new_val |= (~enabled_irq_mask & interrupt_mask);
 478
 479         if (new_val != old_val) {
 480                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 481                 POSTING_READ(GEN8_DE_PORT_IMR);
 482         }
 483 }
 484
 485 /**
 486  * bdw_update_pipe_irq - update DE pipe interrupt
 487  * @dev_priv: driver private
 488  * @pipe: pipe whose interrupt to update
 489  * @interrupt_mask: mask of interrupt bits to update
 490  * @enabled_irq_mask: mask of interrupt bits to enable
 491  */
 492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 493                          enum pipe pipe,
 494                          uint32_t interrupt_mask,
 495                          uint32_t enabled_irq_mask)
 496 {
 497         uint32_t new_val;
 498
 499         assert_spin_locked(&dev_priv->irq_lock);
 500
 501         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 502
 503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 504                 return;
 505
 506         new_val = dev_priv->de_irq_mask[pipe];
 507         new_val &= ~interrupt_mask;
 508         new_val |= (~enabled_irq_mask & interrupt_mask);
 509
 510         if (new_val != dev_priv->de_irq_mask[pipe]) {
 511                 dev_priv->de_irq_mask[pipe] = new_val;
 512                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 513                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 514         }
 515 }
 516
 517 /**
 518  * ibx_display_interrupt_update - update SDEIMR
 519  * @dev_priv: driver private
 520  * @interrupt_mask: mask of interrupt bits to update
 521  * @enabled_irq_mask: mask of interrupt bits to enable
 522  */
 523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 524                                   uint32_t interrupt_mask,
 525                                   uint32_t enabled_irq_mask)
 526 {
 527         uint32_t sdeimr = I915_READ(SDEIMR);
 528         sdeimr &= ~interrupt_mask;
 529         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 530
 531         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 532
 533         assert_spin_locked(&dev_priv->irq_lock);
 534
 535         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 536                 return;
 537
 538         I915_WRITE(SDEIMR, sdeimr);
 539         POSTING_READ(SDEIMR);
 540 }
 541
 542 static void
 543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 544                        u32 enable_mask, u32 status_mask)
 545 {
 546         i915_reg_t reg = PIPESTAT(pipe);
 547         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 548
 549         assert_spin_locked(&dev_priv->irq_lock);
 550         WARN_ON(!intel_irqs_enabled(dev_priv));
 551
 552         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 553                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 554                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 555                       pipe_name(pipe), enable_mask, status_mask))
 556                 return;
 557
 558         if ((pipestat & enable_mask) == enable_mask)
 559                 return;
 560
 561         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 562
 563         /* Enable the interrupt, clear any pending status */
 564         pipestat |= enable_mask | status_mask;
 565         I915_WRITE(reg, pipestat);
 566         POSTING_READ(reg);
 567 }
 568
 569 static void
 570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 571                         u32 enable_mask, u32 status_mask)
 572 {
 573         i915_reg_t reg = PIPESTAT(pipe);
 574         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 575
 576         assert_spin_locked(&dev_priv->irq_lock);
 577         WARN_ON(!intel_irqs_enabled(dev_priv));
 578
 579         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 580                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 581                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 582                       pipe_name(pipe), enable_mask, status_mask))
 583                 return;
 584
 585         if ((pipestat & enable_mask) == 0)
 586                 return;
 587
 588         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 589
 590         pipestat &= ~enable_mask;
 591         I915_WRITE(reg, pipestat);
 592         POSTING_READ(reg);
 593 }
 594
 595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 596 {
 597         u32 enable_mask = status_mask << 16;
 598
 599         /*
 600          * On pipe A we don't support the PSR interrupt yet,
 601          * on pipe B and C the same bit MBZ.
 602          */
 603         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 604                 return 0;
 605         /*
 606          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 607          * A the same bit is for perf counters which we don't use either.
 608          */
 609         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 610                 return 0;
 611
 612         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 613                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 614                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 615         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 616                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 617         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 618                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 619
 620         return enable_mask;
 621 }
 622
 623 void
 624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 625                      u32 status_mask)
 626 {
 627         u32 enable_mask;
 628
 629         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 630                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 631                                                            status_mask);
 632         else
 633                 enable_mask = status_mask << 16;
 634         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 635 }
 636
 637 void
 638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 639                       u32 status_mask)
 640 {
 641         u32 enable_mask;
 642
 643         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 644                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 645                                                            status_mask);
 646         else
 647                 enable_mask = status_mask << 16;
 648         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 649 }
 650
 651 /**
 652  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 653  * @dev_priv: i915 device private
 654  */
 655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 656 {
 657         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 658                 return;
 659
 660         spin_lock_irq(&dev_priv->irq_lock);
 661
 662         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 663         if (INTEL_GEN(dev_priv) >= 4)
 664                 i915_enable_pipestat(dev_priv, PIPE_A,
 665                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 666
 667         spin_unlock_irq(&dev_priv->irq_lock);
 668 }
 669
 670 /*
 671  * This timing diagram depicts the video signal in and
 672  * around the vertical blanking period.
 673  *
 674  * Assumptions about the fictitious mode used in this example:
 675  *  vblank_start >= 3
 676  *  vsync_start = vblank_start + 1
 677  *  vsync_end = vblank_start + 2
 678  *  vtotal = vblank_start + 3
 679  *
 680  *           start of vblank:
 681  *           latch double buffered registers
 682  *           increment frame counter (ctg+)
 683  *           generate start of vblank interrupt (gen4+)
 684  *           |
 685  *           |          frame start:
 686  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 687  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 688  *           |          |
 689  *           |          |  start of vsync:
 690  *           |          |  generate vsync interrupt
 691  *           |          |  |
 692  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 693  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 694  * ----va---> <-----------------vb--------------------> <--------va-------------
 695  *       |          |       <----vs----->                     |
 696  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 697  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 698  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 699  *       |          |                                         |
 700  *       last visible pixel                                   first visible pixel
 701  *                  |                                         increment frame counter (gen3/4)
 702  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 703  *
 704  * x  = horizontal active
 705  * _  = horizontal blanking
 706  * hs = horizontal sync
 707  * va = vertical active
 708  * vb = vertical blanking
 709  * vs = vertical sync
 710  * vbs = vblank_start (number)
 711  *
 712  * Summary:
 713  * - most events happen at the start of horizontal sync
 714  * - frame start happens at the start of horizontal blank, 1-4 lines
 715  *   (depending on PIPECONF settings) after the start of vblank
 716  * - gen3/4 pixel and frame counter are synchronized with the start
 717  *   of horizontal active on the first line of vertical active
 718  */
 719
 720 /* Called from drm generic code, passed a 'crtc', which
 721  * we use as a pipe index
 722  */
 723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 724 {
 725         struct drm_i915_private *dev_priv = to_i915(dev);
 726         i915_reg_t high_frame, low_frame;
 727         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 728         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 729                                                                 pipe);
 730         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 731
 732         htotal = mode->crtc_htotal;
 733         hsync_start = mode->crtc_hsync_start;
 734         vbl_start = mode->crtc_vblank_start;
 735         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 736                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 737
 738         /* Convert to pixel count */
 739         vbl_start *= htotal;
 740
 741         /* Start of vblank event occurs at start of hsync */
 742         vbl_start -= htotal - hsync_start;
 743
 744         high_frame = PIPEFRAME(pipe);
 745         low_frame = PIPEFRAMEPIXEL(pipe);
 746
 747         /*
 748          * High & low register fields aren't synchronized, so make sure
 749          * we get a low value that's stable across two reads of the high
 750          * register.
 751          */
 752         do {
 753                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 754                 low   = I915_READ(low_frame);
 755                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 756         } while (high1 != high2);
 757
 758         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 759         pixel = low & PIPE_PIXEL_MASK;
 760         low >>= PIPE_FRAME_LOW_SHIFT;
 761
 762         /*
 763          * The frame counter increments at beginning of active.
 764          * Cook up a vblank counter by also checking the pixel
 765          * counter against vblank start.
 766          */
 767         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 768 }
 769
 770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773
 774         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 775 }
 776
 777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         struct drm_i915_private *dev_priv = to_i915(dev);
 782         const struct drm_display_mode *mode = &crtc->base.hwmode;
 783         enum pipe pipe = crtc->pipe;
 784         int position, vtotal;
 785
 786         vtotal = mode->crtc_vtotal;
 787         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 788                 vtotal /= 2;
 789
 790         if (IS_GEN2(dev_priv))
 791                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 792         else
 793                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 794
 795         /*
 796          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 797          * read it just before the start of vblank.  So try it again
 798          * so we don't accidentally end up spanning a vblank frame
 799          * increment, causing the pipe_update_end() code to squak at us.
 800          *
 801          * The nature of this problem means we can't simply check the ISR
 802          * bit and return the vblank start value; nor can we use the scanline
 803          * debug register in the transcoder as it appears to have the same
 804          * problem.  We may need to extend this to include other platforms,
 805          * but so far testing only shows the problem on HSW.
 806          */
 807         if (HAS_DDI(dev_priv) && !position) {
 808                 int i, temp;
 809
 810                 for (i = 0; i < 100; i++) {
 811                         udelay(1);
 812                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 813                                 DSL_LINEMASK_GEN3;
 814                         if (temp != position) {
 815                                 position = temp;
 816                                 break;
 817                         }
 818                 }
 819         }
 820
 821         /*
 822          * See update_scanline_offset() for the details on the
 823          * scanline_offset adjustment.
 824          */
 825         return (position + crtc->scanline_offset) % vtotal;
 826 }
 827
 828 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 829                                     unsigned int flags, int *vpos, int *hpos,
 830                                     ktime_t *stime, ktime_t *etime,
 831                                     const struct drm_display_mode *mode)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(dev);
 834         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 835                                                                 pipe);
 836         int position;
 837         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 838         bool in_vbl = true;
 839         int ret = 0;
 840         unsigned long irqflags;
 841
 842         if (WARN_ON(!mode->crtc_clock)) {
 843                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 844                                  "pipe %c\n", pipe_name(pipe));
 845                 return 0;
 846         }
 847
 848         htotal = mode->crtc_htotal;
 849         hsync_start = mode->crtc_hsync_start;
 850         vtotal = mode->crtc_vtotal;
 851         vbl_start = mode->crtc_vblank_start;
 852         vbl_end = mode->crtc_vblank_end;
 853
 854         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 855                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 856                 vbl_end /= 2;
 857                 vtotal /= 2;
 858         }
 859
 860         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 861
 862         /*
 863          * Lock uncore.lock, as we will do multiple timing critical raw
 864          * register reads, potentially with preemption disabled, so the
 865          * following code must not block on uncore.lock.
 866          */
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 870
 871         /* Get optional system timestamp before query. */
 872         if (stime)
 873                 *stime = ktime_get();
 874
 875         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 876                 /* No obvious pixelcount register. Only query vertical
 877                  * scanout position from Display scan line register.
 878                  */
 879                 position = __intel_get_crtc_scanline(intel_crtc);
 880         } else {
 881                 /* Have access to pixelcount since start of frame.
 882                  * We can split this into vertical and horizontal
 883                  * scanout position.
 884                  */
 885                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 886
 887                 /* convert to pixel counts */
 888                 vbl_start *= htotal;
 889                 vbl_end *= htotal;
 890                 vtotal *= htotal;
 891
 892                 /*
 893                  * In interlaced modes, the pixel counter counts all pixels,
 894                  * so one field will have htotal more pixels. In order to avoid
 895                  * the reported position from jumping backwards when the pixel
 896                  * counter is beyond the length of the shorter field, just
 897                  * clamp the position the length of the shorter field. This
 898                  * matches how the scanline counter based position works since
 899                  * the scanline counter doesn't count the two half lines.
 900                  */
 901                 if (position >= vtotal)
 902                         position = vtotal - 1;
 903
 904                 /*
 905                  * Start of vblank interrupt is triggered at start of hsync,
 906                  * just prior to the first active line of vblank. However we
 907                  * consider lines to start at the leading edge of horizontal
 908                  * active. So, should we get here before we've crossed into
 909                  * the horizontal active of the first line in vblank, we would
 910                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 911                  * always add htotal-hsync_start to the current pixel position.
 912                  */
 913                 position = (position + htotal - hsync_start) % vtotal;
 914         }
 915
 916         /* Get optional system timestamp after query. */
 917         if (etime)
 918                 *etime = ktime_get();
 919
 920         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 921
 922         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 923
 924         in_vbl = position >= vbl_start && position < vbl_end;
 925
 926         /*
 927          * While in vblank, position will be negative
 928          * counting up towards 0 at vbl_end. And outside
 929          * vblank, position will be positive counting
 930          * up since vbl_end.
 931          */
 932         if (position >= vbl_start)
 933                 position -= vbl_end;
 934         else
 935                 position += vtotal - vbl_end;
 936
 937         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 938                 *vpos = position;
 939                 *hpos = 0;
 940         } else {
 941                 *vpos = position / htotal;
 942                 *hpos = position - (*vpos * htotal);
 943         }
 944
 945         /* In vblank? */
 946         if (in_vbl)
 947                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 948
 949         return ret;
 950 }
 951
 952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 953 {
 954         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 955         unsigned long irqflags;
 956         int position;
 957
 958         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 959         position = __intel_get_crtc_scanline(crtc);
 960         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 961
 962         return position;
 963 }
 964
 965 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 966                               int *max_error,
 967                               struct timeval *vblank_time,
 968                               unsigned flags)
 969 {
 970         struct drm_i915_private *dev_priv = to_i915(dev);
 971         struct intel_crtc *crtc;
 972
 973         if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
 974                 DRM_ERROR("Invalid crtc %u\n", pipe);
 975                 return -EINVAL;
 976         }
 977
 978         /* Get drm_crtc to timestamp: */
 979         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 980         if (crtc == NULL) {
 981                 DRM_ERROR("Invalid crtc %u\n", pipe);
 982                 return -EINVAL;
 983         }
 984
 985         if (!crtc->base.hwmode.crtc_clock) {
 986                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 987                 return -EBUSY;
 988         }
 989
 990         /* Helper routine in DRM core does all the work: */
 991         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 992                                                      vblank_time, flags,
 993                                                      &crtc->base.hwmode);
 994 }
 995
 996 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 997 {
 998         u32 busy_up, busy_down, max_avg, min_avg;
 999         u8 new_delay;
1000
1001         spin_lock(&mchdev_lock);
1002
1003         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1004
1005         new_delay = dev_priv->ips.cur_delay;
1006
1007         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1008         busy_up = I915_READ(RCPREVBSYTUPAVG);
1009         busy_down = I915_READ(RCPREVBSYTDNAVG);
1010         max_avg = I915_READ(RCBMAXAVG);
1011         min_avg = I915_READ(RCBMINAVG);
1012
1013         /* Handle RCS change request from hw */
1014         if (busy_up > max_avg) {
1015                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1016                         new_delay = dev_priv->ips.cur_delay - 1;
1017                 if (new_delay < dev_priv->ips.max_delay)
1018                         new_delay = dev_priv->ips.max_delay;
1019         } else if (busy_down < min_avg) {
1020                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1021                         new_delay = dev_priv->ips.cur_delay + 1;
1022                 if (new_delay > dev_priv->ips.min_delay)
1023                         new_delay = dev_priv->ips.min_delay;
1024         }
1025
1026         if (ironlake_set_drps(dev_priv, new_delay))
1027                 dev_priv->ips.cur_delay = new_delay;
1028
1029         spin_unlock(&mchdev_lock);
1030
1031         return;
1032 }
1033
1034 static void notify_ring(struct intel_engine_cs *engine)
1035 {
1036         set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1037         if (intel_engine_wakeup(engine))
1038                 trace_i915_gem_request_notify(engine);
1039 }
1040
1041 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1042                         struct intel_rps_ei *ei)
1043 {
1044         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1045         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1046         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1047 }
1048
1049 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1050                          const struct intel_rps_ei *old,
1051                          const struct intel_rps_ei *now,
1052                          int threshold)
1053 {
1054         u64 time, c0;
1055         unsigned int mul = 100;
1056
1057         if (old->cz_clock == 0)
1058                 return false;
1059
1060         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1061                 mul <<= 8;
1062
1063         time = now->cz_clock - old->cz_clock;
1064         time *= threshold * dev_priv->czclk_freq;
1065
1066         /* Workload can be split between render + media, e.g. SwapBuffers
1067          * being blitted in X after being rendered in mesa. To account for
1068          * this we need to combine both engines into our activity counter.
1069          */
1070         c0 = now->render_c0 - old->render_c0;
1071         c0 += now->media_c0 - old->media_c0;
1072         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1073
1074         return c0 >= time;
1075 }
1076
1077 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1078 {
1079         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1080         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1081 }
1082
1083 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1084 {
1085         struct intel_rps_ei now;
1086         u32 events = 0;
1087
1088         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1089                 return 0;
1090
1091         vlv_c0_read(dev_priv, &now);
1092         if (now.cz_clock == 0)
1093                 return 0;
1094
1095         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1096                 if (!vlv_c0_above(dev_priv,
1097                                   &dev_priv->rps.down_ei, &now,
1098                                   dev_priv->rps.down_threshold))
1099                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1100                 dev_priv->rps.down_ei = now;
1101         }
1102
1103         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1104                 if (vlv_c0_above(dev_priv,
1105                                  &dev_priv->rps.up_ei, &now,
1106                                  dev_priv->rps.up_threshold))
1107                         events |= GEN6_PM_RP_UP_THRESHOLD;
1108                 dev_priv->rps.up_ei = now;
1109         }
1110
1111         return events;
1112 }
1113
1114 static bool any_waiters(struct drm_i915_private *dev_priv)
1115 {
1116         struct intel_engine_cs *engine;
1117         enum intel_engine_id id;
1118
1119         for_each_engine(engine, dev_priv, id)
1120                 if (intel_engine_has_waiter(engine))
1121                         return true;
1122
1123         return false;
1124 }
1125
1126 static void gen6_pm_rps_work(struct work_struct *work)
1127 {
1128         struct drm_i915_private *dev_priv =
1129                 container_of(work, struct drm_i915_private, rps.work);
1130         bool client_boost;
1131         int new_delay, adj, min, max;
1132         u32 pm_iir;
1133
1134         spin_lock_irq(&dev_priv->irq_lock);
1135         /* Speed up work cancelation during disabling rps interrupts. */
1136         if (!dev_priv->rps.interrupts_enabled) {
1137                 spin_unlock_irq(&dev_priv->irq_lock);
1138                 return;
1139         }
1140
1141         pm_iir = dev_priv->rps.pm_iir;
1142         dev_priv->rps.pm_iir = 0;
1143         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1144         gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1145         client_boost = dev_priv->rps.client_boost;
1146         dev_priv->rps.client_boost = false;
1147         spin_unlock_irq(&dev_priv->irq_lock);
1148
1149         /* Make sure we didn't queue anything we're not going to process. */
1150         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1151
1152         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1153                 return;
1154
1155         mutex_lock(&dev_priv->rps.hw_lock);
1156
1157         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1158
1159         adj = dev_priv->rps.last_adj;
1160         new_delay = dev_priv->rps.cur_freq;
1161         min = dev_priv->rps.min_freq_softlimit;
1162         max = dev_priv->rps.max_freq_softlimit;
1163         if (client_boost || any_waiters(dev_priv))
1164                 max = dev_priv->rps.max_freq;
1165         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1166                 new_delay = dev_priv->rps.boost_freq;
1167                 adj = 0;
1168         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1169                 if (adj > 0)
1170                         adj *= 2;
1171                 else /* CHV needs even encode values */
1172                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1173
1174                 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1175                         adj = 0;
1176                 /*
1177                  * For better performance, jump directly
1178                  * to RPe if we're below it.
1179                  */
1180                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1181                         new_delay = dev_priv->rps.efficient_freq;
1182                         adj = 0;
1183                 }
1184         } else if (client_boost || any_waiters(dev_priv)) {
1185                 adj = 0;
1186         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1187                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1188                         new_delay = dev_priv->rps.efficient_freq;
1189                 else
1190                         new_delay = dev_priv->rps.min_freq_softlimit;
1191                 adj = 0;
1192         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1193                 if (adj < 0)
1194                         adj *= 2;
1195                 else /* CHV needs even encode values */
1196                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1197
1198                 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1199                         adj = 0;
1200         } else { /* unknown event */
1201                 adj = 0;
1202         }
1203
1204         dev_priv->rps.last_adj = adj;
1205
1206         /* sysfs frequency interfaces may have snuck in while servicing the
1207          * interrupt
1208          */
1209         new_delay += adj;
1210         new_delay = clamp_t(int, new_delay, min, max);
1211
1212         if (intel_set_rps(dev_priv, new_delay)) {
1213                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1214                 dev_priv->rps.last_adj = 0;
1215         }
1216
1217         mutex_unlock(&dev_priv->rps.hw_lock);
1218 }
1219
1220
1221 /**
1222  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1223  * occurred.
1224  * @work: workqueue struct
1225  *
1226  * Doesn't actually do anything except notify userspace. As a consequence of
1227  * this event, userspace should try to remap the bad rows since statistically
1228  * it is likely the same row is more likely to go bad again.
1229  */
1230 static void ivybridge_parity_work(struct work_struct *work)
1231 {
1232         struct drm_i915_private *dev_priv =
1233                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1234         u32 error_status, row, bank, subbank;
1235         char *parity_event[6];
1236         uint32_t misccpctl;
1237         uint8_t slice = 0;
1238
1239         /* We must turn off DOP level clock gating to access the L3 registers.
1240          * In order to prevent a get/put style interface, acquire struct mutex
1241          * any time we access those registers.
1242          */
1243         mutex_lock(&dev_priv->drm.struct_mutex);
1244
1245         /* If we've screwed up tracking, just let the interrupt fire again */
1246         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1247                 goto out;
1248
1249         misccpctl = I915_READ(GEN7_MISCCPCTL);
1250         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1251         POSTING_READ(GEN7_MISCCPCTL);
1252
1253         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1254                 i915_reg_t reg;
1255
1256                 slice--;
1257                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1258                         break;
1259
1260                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1261
1262                 reg = GEN7_L3CDERRST1(slice);
1263
1264                 error_status = I915_READ(reg);
1265                 row = GEN7_PARITY_ERROR_ROW(error_status);
1266                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1267                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1268
1269                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1270                 POSTING_READ(reg);
1271
1272                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1273                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1274                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1275                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1276                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1277                 parity_event[5] = NULL;
1278
1279                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1280                                    KOBJ_CHANGE, parity_event);
1281
1282                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1283                           slice, row, bank, subbank);
1284
1285                 kfree(parity_event[4]);
1286                 kfree(parity_event[3]);
1287                 kfree(parity_event[2]);
1288                 kfree(parity_event[1]);
1289         }
1290
1291         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1292
1293 out:
1294         WARN_ON(dev_priv->l3_parity.which_slice);
1295         spin_lock_irq(&dev_priv->irq_lock);
1296         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1297         spin_unlock_irq(&dev_priv->irq_lock);
1298
1299         mutex_unlock(&dev_priv->drm.struct_mutex);
1300 }
1301
1302 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1303                                                u32 iir)
1304 {
1305         if (!HAS_L3_DPF(dev_priv))
1306                 return;
1307
1308         spin_lock(&dev_priv->irq_lock);
1309         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1310         spin_unlock(&dev_priv->irq_lock);
1311
1312         iir &= GT_PARITY_ERROR(dev_priv);
1313         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1314                 dev_priv->l3_parity.which_slice |= 1 << 1;
1315
1316         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1317                 dev_priv->l3_parity.which_slice |= 1 << 0;
1318
1319         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1320 }
1321
1322 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1323                                u32 gt_iir)
1324 {
1325         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1326                 notify_ring(dev_priv->engine[RCS]);
1327         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1328                 notify_ring(dev_priv->engine[VCS]);
1329 }
1330
1331 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1332                                u32 gt_iir)
1333 {
1334         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1335                 notify_ring(dev_priv->engine[RCS]);
1336         if (gt_iir & GT_BSD_USER_INTERRUPT)
1337                 notify_ring(dev_priv->engine[VCS]);
1338         if (gt_iir & GT_BLT_USER_INTERRUPT)
1339                 notify_ring(dev_priv->engine[BCS]);
1340
1341         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1342                       GT_BSD_CS_ERROR_INTERRUPT |
1343                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1344                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1345
1346         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1347                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1348 }
1349
1350 static __always_inline void
1351 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1352 {
1353         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1354                 notify_ring(engine);
1355
1356         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1357                 set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1358                 tasklet_hi_schedule(&engine->irq_tasklet);
1359         }
1360 }
1361
1362 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1363                                    u32 master_ctl,
1364                                    u32 gt_iir[4])
1365 {
1366         irqreturn_t ret = IRQ_NONE;
1367
1368         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1369                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1370                 if (gt_iir[0]) {
1371                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1372                         ret = IRQ_HANDLED;
1373                 } else
1374                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1375         }
1376
1377         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1378                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1379                 if (gt_iir[1]) {
1380                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1381                         ret = IRQ_HANDLED;
1382                 } else
1383                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1384         }
1385
1386         if (master_ctl & GEN8_GT_VECS_IRQ) {
1387                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1388                 if (gt_iir[3]) {
1389                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1390                         ret = IRQ_HANDLED;
1391                 } else
1392                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1393         }
1394
1395         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1396                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1397                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1398                                  dev_priv->pm_guc_events)) {
1399                         I915_WRITE_FW(GEN8_GT_IIR(2),
1400                                       gt_iir[2] & (dev_priv->pm_rps_events |
1401                                                    dev_priv->pm_guc_events));
1402                         ret = IRQ_HANDLED;
1403                 } else
1404                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1405         }
1406
1407         return ret;
1408 }
1409
1410 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1411                                 u32 gt_iir[4])
1412 {
1413         if (gt_iir[0]) {
1414                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1415                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1416                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1417                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1418         }
1419
1420         if (gt_iir[1]) {
1421                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1422                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1423                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1424                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1425         }
1426
1427         if (gt_iir[3])
1428                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1429                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1430
1431         if (gt_iir[2] & dev_priv->pm_rps_events)
1432                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1433
1434         if (gt_iir[2] & dev_priv->pm_guc_events)
1435                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1436 }
1437
1438 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1439 {
1440         switch (port) {
1441         case PORT_A:
1442                 return val & PORTA_HOTPLUG_LONG_DETECT;
1443         case PORT_B:
1444                 return val & PORTB_HOTPLUG_LONG_DETECT;
1445         case PORT_C:
1446                 return val & PORTC_HOTPLUG_LONG_DETECT;
1447         default:
1448                 return false;
1449         }
1450 }
1451
1452 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1453 {
1454         switch (port) {
1455         case PORT_E:
1456                 return val & PORTE_HOTPLUG_LONG_DETECT;
1457         default:
1458                 return false;
1459         }
1460 }
1461
1462 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1463 {
1464         switch (port) {
1465         case PORT_A:
1466                 return val & PORTA_HOTPLUG_LONG_DETECT;
1467         case PORT_B:
1468                 return val & PORTB_HOTPLUG_LONG_DETECT;
1469         case PORT_C:
1470                 return val & PORTC_HOTPLUG_LONG_DETECT;
1471         case PORT_D:
1472                 return val & PORTD_HOTPLUG_LONG_DETECT;
1473         default:
1474                 return false;
1475         }
1476 }
1477
1478 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1479 {
1480         switch (port) {
1481         case PORT_A:
1482                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1483         default:
1484                 return false;
1485         }
1486 }
1487
1488 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1489 {
1490         switch (port) {
1491         case PORT_B:
1492                 return val & PORTB_HOTPLUG_LONG_DETECT;
1493         case PORT_C:
1494                 return val & PORTC_HOTPLUG_LONG_DETECT;
1495         case PORT_D:
1496                 return val & PORTD_HOTPLUG_LONG_DETECT;
1497         default:
1498                 return false;
1499         }
1500 }
1501
1502 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1503 {
1504         switch (port) {
1505         case PORT_B:
1506                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1507         case PORT_C:
1508                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1509         case PORT_D:
1510                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1511         default:
1512                 return false;
1513         }
1514 }
1515
1516 /*
1517  * Get a bit mask of pins that have triggered, and which ones may be long.
1518  * This can be called multiple times with the same masks to accumulate
1519  * hotplug detection results from several registers.
1520  *
1521  * Note that the caller is expected to zero out the masks initially.
1522  */
1523 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1524                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1525                              const u32 hpd[HPD_NUM_PINS],
1526                              bool long_pulse_detect(enum port port, u32 val))
1527 {
1528         enum port port;
1529         int i;
1530
1531         for_each_hpd_pin(i) {
1532                 if ((hpd[i] & hotplug_trigger) == 0)
1533                         continue;
1534
1535                 *pin_mask |= BIT(i);
1536
1537                 if (!intel_hpd_pin_to_port(i, &port))
1538                         continue;
1539
1540                 if (long_pulse_detect(port, dig_hotplug_reg))
1541                         *long_mask |= BIT(i);
1542         }
1543
1544         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1545                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1546
1547 }
1548
1549 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1550 {
1551         wake_up_all(&dev_priv->gmbus_wait_queue);
1552 }
1553
1554 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1555 {
1556         wake_up_all(&dev_priv->gmbus_wait_queue);
1557 }
1558
1559 #if defined(CONFIG_DEBUG_FS)
1560 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1561                                          enum pipe pipe,
1562                                          uint32_t crc0, uint32_t crc1,
1563                                          uint32_t crc2, uint32_t crc3,
1564                                          uint32_t crc4)
1565 {
1566         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1567         struct intel_pipe_crc_entry *entry;
1568         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1569         struct drm_driver *driver = dev_priv->drm.driver;
1570         uint32_t crcs[5];
1571         int head, tail;
1572
1573         spin_lock(&pipe_crc->lock);
1574         if (pipe_crc->source) {
1575                 if (!pipe_crc->entries) {
1576                         spin_unlock(&pipe_crc->lock);
1577                         DRM_DEBUG_KMS("spurious interrupt\n");
1578                         return;
1579                 }
1580
1581                 head = pipe_crc->head;
1582                 tail = pipe_crc->tail;
1583
1584                 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1585                         spin_unlock(&pipe_crc->lock);
1586                         DRM_ERROR("CRC buffer overflowing\n");
1587                         return;
1588                 }
1589
1590                 entry = &pipe_crc->entries[head];
1591
1592                 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1593                 entry->crc[0] = crc0;
1594                 entry->crc[1] = crc1;
1595                 entry->crc[2] = crc2;
1596                 entry->crc[3] = crc3;
1597                 entry->crc[4] = crc4;
1598
1599                 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1600                 pipe_crc->head = head;
1601
1602                 spin_unlock(&pipe_crc->lock);
1603
1604                 wake_up_interruptible(&pipe_crc->wq);
1605         } else {
1606                 /*
1607                  * For some not yet identified reason, the first CRC is
1608                  * bonkers. So let's just wait for the next vblank and read
1609                  * out the buggy result.
1610                  *
1611                  * On CHV sometimes the second CRC is bonkers as well, so
1612                  * don't trust that one either.
1613                  */
1614                 if (pipe_crc->skipped == 0 ||
1615                     (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1616                         pipe_crc->skipped++;
1617                         spin_unlock(&pipe_crc->lock);
1618                         return;
1619                 }
1620                 spin_unlock(&pipe_crc->lock);
1621                 crcs[0] = crc0;
1622                 crcs[1] = crc1;
1623                 crcs[2] = crc2;
1624                 crcs[3] = crc3;
1625                 crcs[4] = crc4;
1626                 drm_crtc_add_crc_entry(&crtc->base, true,
1627                                        drm_accurate_vblank_count(&crtc->base),
1628                                        crcs);
1629         }
1630 }
1631 #else
1632 static inline void
1633 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1634                              enum pipe pipe,
1635                              uint32_t crc0, uint32_t crc1,
1636                              uint32_t crc2, uint32_t crc3,
1637                              uint32_t crc4) {}
1638 #endif
1639
1640
1641 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1642                                      enum pipe pipe)
1643 {
1644         display_pipe_crc_irq_handler(dev_priv, pipe,
1645                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1646                                      0, 0, 0, 0);
1647 }
1648
1649 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1650                                      enum pipe pipe)
1651 {
1652         display_pipe_crc_irq_handler(dev_priv, pipe,
1653                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1654                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1655                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1656                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1657                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1658 }
1659
1660 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1661                                       enum pipe pipe)
1662 {
1663         uint32_t res1, res2;
1664
1665         if (INTEL_GEN(dev_priv) >= 3)
1666                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1667         else
1668                 res1 = 0;
1669
1670         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1671                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1672         else
1673                 res2 = 0;
1674
1675         display_pipe_crc_irq_handler(dev_priv, pipe,
1676                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1677                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1678                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1679                                      res1, res2);
1680 }
1681
1682 /* The RPS events need forcewake, so we add them to a work queue and mask their
1683  * IMR bits until the work is done. Other interrupts can be processed without
1684  * the work queue. */
1685 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1686 {
1687         if (pm_iir & dev_priv->pm_rps_events) {
1688                 spin_lock(&dev_priv->irq_lock);
1689                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1690                 if (dev_priv->rps.interrupts_enabled) {
1691                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1692                         schedule_work(&dev_priv->rps.work);
1693                 }
1694                 spin_unlock(&dev_priv->irq_lock);
1695         }
1696
1697         if (INTEL_INFO(dev_priv)->gen >= 8)
1698                 return;
1699
1700         if (HAS_VEBOX(dev_priv)) {
1701                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1702                         notify_ring(dev_priv->engine[VECS]);
1703
1704                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1705                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1706         }
1707 }
1708
1709 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1710 {
1711         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1712                 /* Sample the log buffer flush related bits & clear them out now
1713                  * itself from the message identity register to minimize the
1714                  * probability of losing a flush interrupt, when there are back
1715                  * to back flush interrupts.
1716                  * There can be a new flush interrupt, for different log buffer
1717                  * type (like for ISR), whilst Host is handling one (for DPC).
1718                  * Since same bit is used in message register for ISR & DPC, it
1719                  * could happen that GuC sets the bit for 2nd interrupt but Host
1720                  * clears out the bit on handling the 1st interrupt.
1721                  */
1722                 u32 msg, flush;
1723
1724                 msg = I915_READ(SOFT_SCRATCH(15));
1725                 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1726                                INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1727                 if (flush) {
1728                         /* Clear the message bits that are handled */
1729                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1730
1731                         /* Handle flush interrupt in bottom half */
1732                         queue_work(dev_priv->guc.log.flush_wq,
1733                                    &dev_priv->guc.log.flush_work);
1734
1735                         dev_priv->guc.log.flush_interrupt_count++;
1736                 } else {
1737                         /* Not clearing of unhandled event bits won't result in
1738                          * re-triggering of the interrupt.
1739                          */
1740                 }
1741         }
1742 }
1743
1744 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1745                                      enum pipe pipe)
1746 {
1747         bool ret;
1748
1749         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1750         if (ret)
1751                 intel_finish_page_flip_mmio(dev_priv, pipe);
1752
1753         return ret;
1754 }
1755
1756 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1757                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1758 {
1759         int pipe;
1760
1761         spin_lock(&dev_priv->irq_lock);
1762
1763         if (!dev_priv->display_irqs_enabled) {
1764                 spin_unlock(&dev_priv->irq_lock);
1765                 return;
1766         }
1767
1768         for_each_pipe(dev_priv, pipe) {
1769                 i915_reg_t reg;
1770                 u32 mask, iir_bit = 0;
1771
1772                 /*
1773                  * PIPESTAT bits get signalled even when the interrupt is
1774                  * disabled with the mask bits, and some of the status bits do
1775                  * not generate interrupts at all (like the underrun bit). Hence
1776                  * we need to be careful that we only handle what we want to
1777                  * handle.
1778                  */
1779
1780                 /* fifo underruns are filterered in the underrun handler. */
1781                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1782
1783                 switch (pipe) {
1784                 case PIPE_A:
1785                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1786                         break;
1787                 case PIPE_B:
1788                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1789                         break;
1790                 case PIPE_C:
1791                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1792                         break;
1793                 }
1794                 if (iir & iir_bit)
1795                         mask |= dev_priv->pipestat_irq_mask[pipe];
1796
1797                 if (!mask)
1798                         continue;
1799
1800                 reg = PIPESTAT(pipe);
1801                 mask |= PIPESTAT_INT_ENABLE_MASK;
1802                 pipe_stats[pipe] = I915_READ(reg) & mask;
1803
1804                 /*
1805                  * Clear the PIPE*STAT regs before the IIR
1806                  */
1807                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1808                                         PIPESTAT_INT_STATUS_MASK))
1809                         I915_WRITE(reg, pipe_stats[pipe]);
1810         }
1811         spin_unlock(&dev_priv->irq_lock);
1812 }
1813
1814 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1815                                             u32 pipe_stats[I915_MAX_PIPES])
1816 {
1817         enum pipe pipe;
1818
1819         for_each_pipe(dev_priv, pipe) {
1820                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1821                     intel_pipe_handle_vblank(dev_priv, pipe))
1822                         intel_check_page_flip(dev_priv, pipe);
1823
1824                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1825                         intel_finish_page_flip_cs(dev_priv, pipe);
1826
1827                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1828                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1829
1830                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1831                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1832         }
1833
1834         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1835                 gmbus_irq_handler(dev_priv);
1836 }
1837
1838 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1839 {
1840         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1841
1842         if (hotplug_status)
1843                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1844
1845         return hotplug_status;
1846 }
1847
1848 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1849                                  u32 hotplug_status)
1850 {
1851         u32 pin_mask = 0, long_mask = 0;
1852
1853         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1854             IS_CHERRYVIEW(dev_priv)) {
1855                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1856
1857                 if (hotplug_trigger) {
1858                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1859                                            hotplug_trigger, hpd_status_g4x,
1860                                            i9xx_port_hotplug_long_detect);
1861
1862                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1863                 }
1864
1865                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1866                         dp_aux_irq_handler(dev_priv);
1867         } else {
1868                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1869
1870                 if (hotplug_trigger) {
1871                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1872                                            hotplug_trigger, hpd_status_i915,
1873                                            i9xx_port_hotplug_long_detect);
1874                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1875                 }
1876         }
1877 }
1878
1879 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1880 {
1881         struct drm_device *dev = arg;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         irqreturn_t ret = IRQ_NONE;
1884
1885         if (!intel_irqs_enabled(dev_priv))
1886                 return IRQ_NONE;
1887
1888         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1889         disable_rpm_wakeref_asserts(dev_priv);
1890
1891         do {
1892                 u32 iir, gt_iir, pm_iir;
1893                 u32 pipe_stats[I915_MAX_PIPES] = {};
1894                 u32 hotplug_status = 0;
1895                 u32 ier = 0;
1896
1897                 gt_iir = I915_READ(GTIIR);
1898                 pm_iir = I915_READ(GEN6_PMIIR);
1899                 iir = I915_READ(VLV_IIR);
1900
1901                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1902                         break;
1903
1904                 ret = IRQ_HANDLED;
1905
1906                 /*
1907                  * Theory on interrupt generation, based on empirical evidence:
1908                  *
1909                  * x = ((VLV_IIR & VLV_IER) ||
1910                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1911                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1912                  *
1913                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1914                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1915                  * guarantee the CPU interrupt will be raised again even if we
1916                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1917                  * bits this time around.
1918                  */
1919                 I915_WRITE(VLV_MASTER_IER, 0);
1920                 ier = I915_READ(VLV_IER);
1921                 I915_WRITE(VLV_IER, 0);
1922
1923                 if (gt_iir)
1924                         I915_WRITE(GTIIR, gt_iir);
1925                 if (pm_iir)
1926                         I915_WRITE(GEN6_PMIIR, pm_iir);
1927
1928                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1929                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1930
1931                 /* Call regardless, as some status bits might not be
1932                  * signalled in iir */
1933                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1934
1935                 /*
1936                  * VLV_IIR is single buffered, and reflects the level
1937                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1938                  */
1939                 if (iir)
1940                         I915_WRITE(VLV_IIR, iir);
1941
1942                 I915_WRITE(VLV_IER, ier);
1943                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1944                 POSTING_READ(VLV_MASTER_IER);
1945
1946                 if (gt_iir)
1947                         snb_gt_irq_handler(dev_priv, gt_iir);
1948                 if (pm_iir)
1949                         gen6_rps_irq_handler(dev_priv, pm_iir);
1950
1951                 if (hotplug_status)
1952                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1953
1954                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1955         } while (0);
1956
1957         enable_rpm_wakeref_asserts(dev_priv);
1958
1959         return ret;
1960 }
1961
1962 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1963 {
1964         struct drm_device *dev = arg;
1965         struct drm_i915_private *dev_priv = to_i915(dev);
1966         irqreturn_t ret = IRQ_NONE;
1967
1968         if (!intel_irqs_enabled(dev_priv))
1969                 return IRQ_NONE;
1970
1971         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1972         disable_rpm_wakeref_asserts(dev_priv);
1973
1974         do {
1975                 u32 master_ctl, iir;
1976                 u32 gt_iir[4] = {};
1977                 u32 pipe_stats[I915_MAX_PIPES] = {};
1978                 u32 hotplug_status = 0;
1979                 u32 ier = 0;
1980
1981                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1982                 iir = I915_READ(VLV_IIR);
1983
1984                 if (master_ctl == 0 && iir == 0)
1985                         break;
1986
1987                 ret = IRQ_HANDLED;
1988
1989                 /*
1990                  * Theory on interrupt generation, based on empirical evidence:
1991                  *
1992                  * x = ((VLV_IIR & VLV_IER) ||
1993                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1994                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1995                  *
1996                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1997                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1998                  * guarantee the CPU interrupt will be raised again even if we
1999                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2000                  * bits this time around.
2001                  */
2002                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2003                 ier = I915_READ(VLV_IER);
2004                 I915_WRITE(VLV_IER, 0);
2005
2006                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2007
2008                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2009                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2010
2011                 /* Call regardless, as some status bits might not be
2012                  * signalled in iir */
2013                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2014
2015                 /*
2016                  * VLV_IIR is single buffered, and reflects the level
2017                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2018                  */
2019                 if (iir)
2020                         I915_WRITE(VLV_IIR, iir);
2021
2022                 I915_WRITE(VLV_IER, ier);
2023                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2024                 POSTING_READ(GEN8_MASTER_IRQ);
2025
2026                 gen8_gt_irq_handler(dev_priv, gt_iir);
2027
2028                 if (hotplug_status)
2029                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2030
2031                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2032         } while (0);
2033
2034         enable_rpm_wakeref_asserts(dev_priv);
2035
2036         return ret;
2037 }
2038
2039 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2040                                 u32 hotplug_trigger,
2041                                 const u32 hpd[HPD_NUM_PINS])
2042 {
2043         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2044
2045         /*
2046          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2047          * unless we touch the hotplug register, even if hotplug_trigger is
2048          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2049          * errors.
2050          */
2051         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2052         if (!hotplug_trigger) {
2053                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2054                         PORTD_HOTPLUG_STATUS_MASK |
2055                         PORTC_HOTPLUG_STATUS_MASK |
2056                         PORTB_HOTPLUG_STATUS_MASK;
2057                 dig_hotplug_reg &= ~mask;
2058         }
2059
2060         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2061         if (!hotplug_trigger)
2062                 return;
2063
2064         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2065                            dig_hotplug_reg, hpd,
2066                            pch_port_hotplug_long_detect);
2067
2068         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2069 }
2070
2071 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2072 {
2073         int pipe;
2074         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2075
2076         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2077
2078         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2079                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2080                                SDE_AUDIO_POWER_SHIFT);
2081                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2082                                  port_name(port));
2083         }
2084
2085         if (pch_iir & SDE_AUX_MASK)
2086                 dp_aux_irq_handler(dev_priv);
2087
2088         if (pch_iir & SDE_GMBUS)
2089                 gmbus_irq_handler(dev_priv);
2090
2091         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2092                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2093
2094         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2095                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2096
2097         if (pch_iir & SDE_POISON)
2098                 DRM_ERROR("PCH poison interrupt\n");
2099
2100         if (pch_iir & SDE_FDI_MASK)
2101                 for_each_pipe(dev_priv, pipe)
2102                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2103                                          pipe_name(pipe),
2104                                          I915_READ(FDI_RX_IIR(pipe)));
2105
2106         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2107                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2108
2109         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2110                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2111
2112         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2113                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2114
2115         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2116                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2117 }
2118
2119 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2120 {
2121         u32 err_int = I915_READ(GEN7_ERR_INT);
2122         enum pipe pipe;
2123
2124         if (err_int & ERR_INT_POISON)
2125                 DRM_ERROR("Poison interrupt\n");
2126
2127         for_each_pipe(dev_priv, pipe) {
2128                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2129                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2130
2131                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2132                         if (IS_IVYBRIDGE(dev_priv))
2133                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2134                         else
2135                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2136                 }
2137         }
2138
2139         I915_WRITE(GEN7_ERR_INT, err_int);
2140 }
2141
2142 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2143 {
2144         u32 serr_int = I915_READ(SERR_INT);
2145
2146         if (serr_int & SERR_INT_POISON)
2147                 DRM_ERROR("PCH poison interrupt\n");
2148
2149         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2150                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2151
2152         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2153                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2154
2155         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2156                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2157
2158         I915_WRITE(SERR_INT, serr_int);
2159 }
2160
2161 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2162 {
2163         int pipe;
2164         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2165
2166         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2167
2168         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2169                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2170                                SDE_AUDIO_POWER_SHIFT_CPT);
2171                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2172                                  port_name(port));
2173         }
2174
2175         if (pch_iir & SDE_AUX_MASK_CPT)
2176                 dp_aux_irq_handler(dev_priv);
2177
2178         if (pch_iir & SDE_GMBUS_CPT)
2179                 gmbus_irq_handler(dev_priv);
2180
2181         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2182                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2183
2184         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2185                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2186
2187         if (pch_iir & SDE_FDI_MASK_CPT)
2188                 for_each_pipe(dev_priv, pipe)
2189                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2190                                          pipe_name(pipe),
2191                                          I915_READ(FDI_RX_IIR(pipe)));
2192
2193         if (pch_iir & SDE_ERROR_CPT)
2194                 cpt_serr_int_handler(dev_priv);
2195 }
2196
2197 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2198 {
2199         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2200                 ~SDE_PORTE_HOTPLUG_SPT;
2201         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2202         u32 pin_mask = 0, long_mask = 0;
2203
2204         if (hotplug_trigger) {
2205                 u32 dig_hotplug_reg;
2206
2207                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2208                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2209
2210                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2211                                    dig_hotplug_reg, hpd_spt,
2212                                    spt_port_hotplug_long_detect);
2213         }
2214
2215         if (hotplug2_trigger) {
2216                 u32 dig_hotplug_reg;
2217
2218                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2219                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2220
2221                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2222                                    dig_hotplug_reg, hpd_spt,
2223                                    spt_port_hotplug2_long_detect);
2224         }
2225
2226         if (pin_mask)
2227                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2228
2229         if (pch_iir & SDE_GMBUS_CPT)
2230                 gmbus_irq_handler(dev_priv);
2231 }
2232
2233 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2234                                 u32 hotplug_trigger,
2235                                 const u32 hpd[HPD_NUM_PINS])
2236 {
2237         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2238
2239         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2240         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2241
2242         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2243                            dig_hotplug_reg, hpd,
2244                            ilk_port_hotplug_long_detect);
2245
2246         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2247 }
2248
2249 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2250                                     u32 de_iir)
2251 {
2252         enum pipe pipe;
2253         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2254
2255         if (hotplug_trigger)
2256                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2257
2258         if (de_iir & DE_AUX_CHANNEL_A)
2259                 dp_aux_irq_handler(dev_priv);
2260
2261         if (de_iir & DE_GSE)
2262                 intel_opregion_asle_intr(dev_priv);
2263
2264         if (de_iir & DE_POISON)
2265                 DRM_ERROR("Poison interrupt\n");
2266
2267         for_each_pipe(dev_priv, pipe) {
2268                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2269                     intel_pipe_handle_vblank(dev_priv, pipe))
2270                         intel_check_page_flip(dev_priv, pipe);
2271
2272                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2273                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2274
2275                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2276                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2277
2278                 /* plane/pipes map 1:1 on ilk+ */
2279                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2280                         intel_finish_page_flip_cs(dev_priv, pipe);
2281         }
2282
2283         /* check event from PCH */
2284         if (de_iir & DE_PCH_EVENT) {
2285                 u32 pch_iir = I915_READ(SDEIIR);
2286
2287                 if (HAS_PCH_CPT(dev_priv))
2288                         cpt_irq_handler(dev_priv, pch_iir);
2289                 else
2290                         ibx_irq_handler(dev_priv, pch_iir);
2291
2292                 /* should clear PCH hotplug event before clear CPU irq */
2293                 I915_WRITE(SDEIIR, pch_iir);
2294         }
2295
2296         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2297                 ironlake_rps_change_irq_handler(dev_priv);
2298 }
2299
2300 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2301                                     u32 de_iir)
2302 {
2303         enum pipe pipe;
2304         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2305
2306         if (hotplug_trigger)
2307                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2308
2309         if (de_iir & DE_ERR_INT_IVB)
2310                 ivb_err_int_handler(dev_priv);
2311
2312         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2313                 dp_aux_irq_handler(dev_priv);
2314
2315         if (de_iir & DE_GSE_IVB)
2316                 intel_opregion_asle_intr(dev_priv);
2317
2318         for_each_pipe(dev_priv, pipe) {
2319                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2320                     intel_pipe_handle_vblank(dev_priv, pipe))
2321                         intel_check_page_flip(dev_priv, pipe);
2322
2323                 /* plane/pipes map 1:1 on ilk+ */
2324                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2325                         intel_finish_page_flip_cs(dev_priv, pipe);
2326         }
2327
2328         /* check event from PCH */
2329         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2330                 u32 pch_iir = I915_READ(SDEIIR);
2331
2332                 cpt_irq_handler(dev_priv, pch_iir);
2333
2334                 /* clear PCH hotplug event before clear CPU irq */
2335                 I915_WRITE(SDEIIR, pch_iir);
2336         }
2337 }
2338
2339 /*
2340  * To handle irqs with the minimum potential races with fresh interrupts, we:
2341  * 1 - Disable Master Interrupt Control.
2342  * 2 - Find the source(s) of the interrupt.
2343  * 3 - Clear the Interrupt Identity bits (IIR).
2344  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2345  * 5 - Re-enable Master Interrupt Control.
2346  */
2347 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2348 {
2349         struct drm_device *dev = arg;
2350         struct drm_i915_private *dev_priv = to_i915(dev);
2351         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2352         irqreturn_t ret = IRQ_NONE;
2353
2354         if (!intel_irqs_enabled(dev_priv))
2355                 return IRQ_NONE;
2356
2357         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2358         disable_rpm_wakeref_asserts(dev_priv);
2359
2360         /* disable master interrupt before clearing iir  */
2361         de_ier = I915_READ(DEIER);
2362         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2363         POSTING_READ(DEIER);
2364
2365         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2366          * interrupts will will be stored on its back queue, and then we'll be
2367          * able to process them after we restore SDEIER (as soon as we restore
2368          * it, we'll get an interrupt if SDEIIR still has something to process
2369          * due to its back queue). */
2370         if (!HAS_PCH_NOP(dev_priv)) {
2371                 sde_ier = I915_READ(SDEIER);
2372                 I915_WRITE(SDEIER, 0);
2373                 POSTING_READ(SDEIER);
2374         }
2375
2376         /* Find, clear, then process each source of interrupt */
2377
2378         gt_iir = I915_READ(GTIIR);
2379         if (gt_iir) {
2380                 I915_WRITE(GTIIR, gt_iir);
2381                 ret = IRQ_HANDLED;
2382                 if (INTEL_GEN(dev_priv) >= 6)
2383                         snb_gt_irq_handler(dev_priv, gt_iir);
2384                 else
2385                         ilk_gt_irq_handler(dev_priv, gt_iir);
2386         }
2387
2388         de_iir = I915_READ(DEIIR);
2389         if (de_iir) {
2390                 I915_WRITE(DEIIR, de_iir);
2391                 ret = IRQ_HANDLED;
2392                 if (INTEL_GEN(dev_priv) >= 7)
2393                         ivb_display_irq_handler(dev_priv, de_iir);
2394                 else
2395                         ilk_display_irq_handler(dev_priv, de_iir);
2396         }
2397
2398         if (INTEL_GEN(dev_priv) >= 6) {
2399                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2400                 if (pm_iir) {
2401                         I915_WRITE(GEN6_PMIIR, pm_iir);
2402                         ret = IRQ_HANDLED;
2403                         gen6_rps_irq_handler(dev_priv, pm_iir);
2404                 }
2405         }
2406
2407         I915_WRITE(DEIER, de_ier);
2408         POSTING_READ(DEIER);
2409         if (!HAS_PCH_NOP(dev_priv)) {
2410                 I915_WRITE(SDEIER, sde_ier);
2411                 POSTING_READ(SDEIER);
2412         }
2413
2414         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2415         enable_rpm_wakeref_asserts(dev_priv);
2416
2417         return ret;
2418 }
2419
2420 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2421                                 u32 hotplug_trigger,
2422                                 const u32 hpd[HPD_NUM_PINS])
2423 {
2424         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2425
2426         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2427         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2428
2429         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2430                            dig_hotplug_reg, hpd,
2431                            bxt_port_hotplug_long_detect);
2432
2433         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2434 }
2435
2436 static irqreturn_t
2437 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2438 {
2439         irqreturn_t ret = IRQ_NONE;
2440         u32 iir;
2441         enum pipe pipe;
2442
2443         if (master_ctl & GEN8_DE_MISC_IRQ) {
2444                 iir = I915_READ(GEN8_DE_MISC_IIR);
2445                 if (iir) {
2446                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2447                         ret = IRQ_HANDLED;
2448                         if (iir & GEN8_DE_MISC_GSE)
2449                                 intel_opregion_asle_intr(dev_priv);
2450                         else
2451                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2452                 }
2453                 else
2454                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2455         }
2456
2457         if (master_ctl & GEN8_DE_PORT_IRQ) {
2458                 iir = I915_READ(GEN8_DE_PORT_IIR);
2459                 if (iir) {
2460                         u32 tmp_mask;
2461                         bool found = false;
2462
2463                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2464                         ret = IRQ_HANDLED;
2465
2466                         tmp_mask = GEN8_AUX_CHANNEL_A;
2467                         if (INTEL_INFO(dev_priv)->gen >= 9)
2468                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2469                                             GEN9_AUX_CHANNEL_C |
2470                                             GEN9_AUX_CHANNEL_D;
2471
2472                         if (iir & tmp_mask) {
2473                                 dp_aux_irq_handler(dev_priv);
2474                                 found = true;
2475                         }
2476
2477                         if (IS_GEN9_LP(dev_priv)) {
2478                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2479                                 if (tmp_mask) {
2480                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2481                                                             hpd_bxt);
2482                                         found = true;
2483                                 }
2484                         } else if (IS_BROADWELL(dev_priv)) {
2485                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2486                                 if (tmp_mask) {
2487                                         ilk_hpd_irq_handler(dev_priv,
2488                                                             tmp_mask, hpd_bdw);
2489                                         found = true;
2490                                 }
2491                         }
2492
2493                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2494                                 gmbus_irq_handler(dev_priv);
2495                                 found = true;
2496                         }
2497
2498                         if (!found)
2499                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2500                 }
2501                 else
2502                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2503         }
2504
2505         for_each_pipe(dev_priv, pipe) {
2506                 u32 flip_done, fault_errors;
2507
2508                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2509                         continue;
2510
2511                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2512                 if (!iir) {
2513                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2514                         continue;
2515                 }
2516
2517                 ret = IRQ_HANDLED;
2518                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2519
2520                 if (iir & GEN8_PIPE_VBLANK &&
2521                     intel_pipe_handle_vblank(dev_priv, pipe))
2522                         intel_check_page_flip(dev_priv, pipe);
2523
2524                 flip_done = iir;
2525                 if (INTEL_INFO(dev_priv)->gen >= 9)
2526                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2527                 else
2528                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2529
2530                 if (flip_done)
2531                         intel_finish_page_flip_cs(dev_priv, pipe);
2532
2533                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2534                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2535
2536                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2537                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2538
2539                 fault_errors = iir;
2540                 if (INTEL_INFO(dev_priv)->gen >= 9)
2541                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2542                 else
2543                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2544
2545                 if (fault_errors)
2546                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2547                                   pipe_name(pipe),
2548                                   fault_errors);
2549         }
2550
2551         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2552             master_ctl & GEN8_DE_PCH_IRQ) {
2553                 /*
2554                  * FIXME(BDW): Assume for now that the new interrupt handling
2555                  * scheme also closed the SDE interrupt handling race we've seen
2556                  * on older pch-split platforms. But this needs testing.
2557                  */
2558                 iir = I915_READ(SDEIIR);
2559                 if (iir) {
2560                         I915_WRITE(SDEIIR, iir);
2561                         ret = IRQ_HANDLED;
2562
2563                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2564                                 spt_irq_handler(dev_priv, iir);
2565                         else
2566                                 cpt_irq_handler(dev_priv, iir);
2567                 } else {
2568                         /*
2569                          * Like on previous PCH there seems to be something
2570                          * fishy going on with forwarding PCH interrupts.
2571                          */
2572                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2573                 }
2574         }
2575
2576         return ret;
2577 }
2578
2579 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2580 {
2581         struct drm_device *dev = arg;
2582         struct drm_i915_private *dev_priv = to_i915(dev);
2583         u32 master_ctl;
2584         u32 gt_iir[4] = {};
2585         irqreturn_t ret;
2586
2587         if (!intel_irqs_enabled(dev_priv))
2588                 return IRQ_NONE;
2589
2590         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2591         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2592         if (!master_ctl)
2593                 return IRQ_NONE;
2594
2595         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2596
2597         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2598         disable_rpm_wakeref_asserts(dev_priv);
2599
2600         /* Find, clear, then process each source of interrupt */
2601         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2602         gen8_gt_irq_handler(dev_priv, gt_iir);
2603         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2604
2605         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2606         POSTING_READ_FW(GEN8_MASTER_IRQ);
2607
2608         enable_rpm_wakeref_asserts(dev_priv);
2609
2610         return ret;
2611 }
2612
2613 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2614 {
2615         /*
2616          * Notify all waiters for GPU completion events that reset state has
2617          * been changed, and that they need to restart their wait after
2618          * checking for potential errors (and bail out to drop locks if there is
2619          * a gpu reset pending so that i915_error_work_func can acquire them).
2620          */
2621
2622         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2623         wake_up_all(&dev_priv->gpu_error.wait_queue);
2624
2625         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2626         wake_up_all(&dev_priv->pending_flip_queue);
2627 }
2628
2629 /**
2630  * i915_reset_and_wakeup - do process context error handling work
2631  * @dev_priv: i915 device private
2632  *
2633  * Fire an error uevent so userspace can see that a hang or error
2634  * was detected.
2635  */
2636 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2637 {
2638         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2639         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2640         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2641         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2642
2643         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2644
2645         DRM_DEBUG_DRIVER("resetting chip\n");
2646         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2647
2648         /*
2649          * In most cases it's guaranteed that we get here with an RPM
2650          * reference held, for example because there is a pending GPU
2651          * request that won't finish until the reset is done. This
2652          * isn't the case at least when we get here by doing a
2653          * simulated reset via debugs, so get an RPM reference.
2654          */
2655         intel_runtime_pm_get(dev_priv);
2656         intel_prepare_reset(dev_priv);
2657
2658         do {
2659                 /*
2660                  * All state reset _must_ be completed before we update the
2661                  * reset counter, for otherwise waiters might miss the reset
2662                  * pending state and not properly drop locks, resulting in
2663                  * deadlocks with the reset work.
2664                  */
2665                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2666                         i915_reset(dev_priv);
2667                         mutex_unlock(&dev_priv->drm.struct_mutex);
2668                 }
2669
2670                 /* We need to wait for anyone holding the lock to wakeup */
2671         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2672                                      I915_RESET_IN_PROGRESS,
2673                                      TASK_UNINTERRUPTIBLE,
2674                                      HZ));
2675
2676         intel_finish_reset(dev_priv);
2677         intel_runtime_pm_put(dev_priv);
2678
2679         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2680                 kobject_uevent_env(kobj,
2681                                    KOBJ_CHANGE, reset_done_event);
2682
2683         /*
2684          * Note: The wake_up also serves as a memory barrier so that
2685          * waiters see the updated value of the dev_priv->gpu_error.
2686          */
2687         wake_up_all(&dev_priv->gpu_error.reset_queue);
2688 }
2689
2690 static inline void
2691 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2692                         struct intel_instdone *instdone)
2693 {
2694         int slice;
2695         int subslice;
2696
2697         pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
2698
2699         if (INTEL_GEN(dev_priv) <= 3)
2700                 return;
2701
2702         pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2703
2704         if (INTEL_GEN(dev_priv) <= 6)
2705                 return;
2706
2707         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2708                 pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2709                        slice, subslice, instdone->sampler[slice][subslice]);
2710
2711         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2712                 pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
2713                        slice, subslice, instdone->row[slice][subslice]);
2714 }
2715
2716 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2717 {
2718         u32 eir;
2719
2720         if (!IS_GEN2(dev_priv))
2721                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2722
2723         if (INTEL_GEN(dev_priv) < 4)
2724                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2725         else
2726                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2727
2728         I915_WRITE(EIR, I915_READ(EIR));
2729         eir = I915_READ(EIR);
2730         if (eir) {
2731                 /*
2732                  * some errors might have become stuck,
2733                  * mask them.
2734                  */
2735                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2736                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2737                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2738         }
2739 }
2740
2741 /**
2742  * i915_handle_error - handle a gpu error
2743  * @dev_priv: i915 device private
2744  * @engine_mask: mask representing engines that are hung
2745  * @fmt: Error message format string
2746  *
2747  * Do some basic checking of register state at error time and
2748  * dump it to the syslog.  Also call i915_capture_error_state() to make
2749  * sure we get a record and make it available in debugfs.  Fire a uevent
2750  * so userspace knows something bad happened (should trigger collection
2751  * of a ring dump etc.).
2752  */
2753 void i915_handle_error(struct drm_i915_private *dev_priv,
2754                        u32 engine_mask,
2755                        const char *fmt, ...)
2756 {
2757         va_list args;
2758         char error_msg[80];
2759
2760         va_start(args, fmt);
2761         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2762         va_end(args);
2763
2764         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2765         i915_clear_error_registers(dev_priv);
2766
2767         if (!engine_mask)
2768                 return;
2769
2770         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2771                              &dev_priv->gpu_error.flags))
2772                 return;
2773
2774         /*
2775          * Wakeup waiting processes so that the reset function
2776          * i915_reset_and_wakeup doesn't deadlock trying to grab
2777          * various locks. By bumping the reset counter first, the woken
2778          * processes will see a reset in progress and back off,
2779          * releasing their locks and then wait for the reset completion.
2780          * We must do this for _all_ gpu waiters that might hold locks
2781          * that the reset work needs to acquire.
2782          *
2783          * Note: The wake_up also provides a memory barrier to ensure that the
2784          * waiters see the updated value of the reset flags.
2785          */
2786         i915_error_wake_up(dev_priv);
2787
2788         i915_reset_and_wakeup(dev_priv);
2789 }
2790
2791 /* Called from drm generic code, passed 'crtc' which
2792  * we use as a pipe index
2793  */
2794 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2795 {
2796         struct drm_i915_private *dev_priv = to_i915(dev);
2797         unsigned long irqflags;
2798
2799         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2800         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2801         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2802
2803         return 0;
2804 }
2805
2806 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2807 {
2808         struct drm_i915_private *dev_priv = to_i915(dev);
2809         unsigned long irqflags;
2810
2811         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2812         i915_enable_pipestat(dev_priv, pipe,
2813                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2814         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2815
2816         return 0;
2817 }
2818
2819 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2820 {
2821         struct drm_i915_private *dev_priv = to_i915(dev);
2822         unsigned long irqflags;
2823         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2824                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2825
2826         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2827         ilk_enable_display_irq(dev_priv, bit);
2828         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2829
2830         return 0;
2831 }
2832
2833 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2834 {
2835         struct drm_i915_private *dev_priv = to_i915(dev);
2836         unsigned long irqflags;
2837
2838         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2839         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2840         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2841
2842         return 0;
2843 }
2844
2845 /* Called from drm generic code, passed 'crtc' which
2846  * we use as a pipe index
2847  */
2848 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2849 {
2850         struct drm_i915_private *dev_priv = to_i915(dev);
2851         unsigned long irqflags;
2852
2853         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2854         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2855         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2856 }
2857
2858 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2859 {
2860         struct drm_i915_private *dev_priv = to_i915(dev);
2861         unsigned long irqflags;
2862
2863         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2864         i915_disable_pipestat(dev_priv, pipe,
2865                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2866         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2867 }
2868
2869 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2870 {
2871         struct drm_i915_private *dev_priv = to_i915(dev);
2872         unsigned long irqflags;
2873         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2874                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2875
2876         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2877         ilk_disable_display_irq(dev_priv, bit);
2878         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2879 }
2880
2881 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2882 {
2883         struct drm_i915_private *dev_priv = to_i915(dev);
2884         unsigned long irqflags;
2885
2886         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2887         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2888         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2889 }
2890
2891 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2892 {
2893         if (HAS_PCH_NOP(dev_priv))
2894                 return;
2895
2896         GEN5_IRQ_RESET(SDE);
2897
2898         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2899                 I915_WRITE(SERR_INT, 0xffffffff);
2900 }
2901
2902 /*
2903  * SDEIER is also touched by the interrupt handler to work around missed PCH
2904  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2905  * instead we unconditionally enable all PCH interrupt sources here, but then
2906  * only unmask them as needed with SDEIMR.
2907  *
2908  * This function needs to be called before interrupts are enabled.
2909  */
2910 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2911 {
2912         struct drm_i915_private *dev_priv = to_i915(dev);
2913
2914         if (HAS_PCH_NOP(dev_priv))
2915                 return;
2916
2917         WARN_ON(I915_READ(SDEIER) != 0);
2918         I915_WRITE(SDEIER, 0xffffffff);
2919         POSTING_READ(SDEIER);
2920 }
2921
2922 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2923 {
2924         GEN5_IRQ_RESET(GT);
2925         if (INTEL_GEN(dev_priv) >= 6)
2926                 GEN5_IRQ_RESET(GEN6_PM);
2927 }
2928
2929 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2930 {
2931         enum pipe pipe;
2932
2933         if (IS_CHERRYVIEW(dev_priv))
2934                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2935         else
2936                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2937
2938         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2939         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2940
2941         for_each_pipe(dev_priv, pipe) {
2942                 I915_WRITE(PIPESTAT(pipe),
2943                            PIPE_FIFO_UNDERRUN_STATUS |
2944                            PIPESTAT_INT_STATUS_MASK);
2945                 dev_priv->pipestat_irq_mask[pipe] = 0;
2946         }
2947
2948         GEN5_IRQ_RESET(VLV_);
2949         dev_priv->irq_mask = ~0;
2950 }
2951
2952 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2953 {
2954         u32 pipestat_mask;
2955         u32 enable_mask;
2956         enum pipe pipe;
2957
2958         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2959                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2960
2961         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2962         for_each_pipe(dev_priv, pipe)
2963                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2964
2965         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2966                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2967                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2968         if (IS_CHERRYVIEW(dev_priv))
2969                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2970
2971         WARN_ON(dev_priv->irq_mask != ~0);
2972
2973         dev_priv->irq_mask = ~enable_mask;
2974
2975         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
2976 }
2977
2978 /* drm_dma.h hooks
2979 */
2980 static void ironlake_irq_reset(struct drm_device *dev)
2981 {
2982         struct drm_i915_private *dev_priv = to_i915(dev);
2983
2984         I915_WRITE(HWSTAM, 0xffffffff);
2985
2986         GEN5_IRQ_RESET(DE);
2987         if (IS_GEN7(dev_priv))
2988                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2989
2990         gen5_gt_irq_reset(dev_priv);
2991
2992         ibx_irq_reset(dev_priv);
2993 }
2994
2995 static void valleyview_irq_preinstall(struct drm_device *dev)
2996 {
2997         struct drm_i915_private *dev_priv = to_i915(dev);
2998
2999         I915_WRITE(VLV_MASTER_IER, 0);
3000         POSTING_READ(VLV_MASTER_IER);
3001
3002         gen5_gt_irq_reset(dev_priv);
3003
3004         spin_lock_irq(&dev_priv->irq_lock);
3005         if (dev_priv->display_irqs_enabled)
3006                 vlv_display_irq_reset(dev_priv);
3007         spin_unlock_irq(&dev_priv->irq_lock);
3008 }
3009
3010 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3011 {
3012         GEN8_IRQ_RESET_NDX(GT, 0);
3013         GEN8_IRQ_RESET_NDX(GT, 1);
3014         GEN8_IRQ_RESET_NDX(GT, 2);
3015         GEN8_IRQ_RESET_NDX(GT, 3);
3016 }
3017
3018 static void gen8_irq_reset(struct drm_device *dev)
3019 {
3020         struct drm_i915_private *dev_priv = to_i915(dev);
3021         int pipe;
3022
3023         I915_WRITE(GEN8_MASTER_IRQ, 0);
3024         POSTING_READ(GEN8_MASTER_IRQ);
3025
3026         gen8_gt_irq_reset(dev_priv);
3027
3028         for_each_pipe(dev_priv, pipe)
3029                 if (intel_display_power_is_enabled(dev_priv,
3030                                                    POWER_DOMAIN_PIPE(pipe)))
3031                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3032
3033         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3034         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3035         GEN5_IRQ_RESET(GEN8_PCU_);
3036
3037         if (HAS_PCH_SPLIT(dev_priv))
3038                 ibx_irq_reset(dev_priv);
3039 }
3040
3041 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3042                                      unsigned int pipe_mask)
3043 {
3044         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3045         enum pipe pipe;
3046
3047         spin_lock_irq(&dev_priv->irq_lock);
3048         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3049                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3050                                   dev_priv->de_irq_mask[pipe],
3051                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3052         spin_unlock_irq(&dev_priv->irq_lock);
3053 }
3054
3055 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3056                                      unsigned int pipe_mask)
3057 {
3058         enum pipe pipe;
3059
3060         spin_lock_irq(&dev_priv->irq_lock);
3061         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3062                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3063         spin_unlock_irq(&dev_priv->irq_lock);
3064
3065         /* make sure we're done processing display irqs */
3066         synchronize_irq(dev_priv->drm.irq);
3067 }
3068
3069 static void cherryview_irq_preinstall(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = to_i915(dev);
3072
3073         I915_WRITE(GEN8_MASTER_IRQ, 0);
3074         POSTING_READ(GEN8_MASTER_IRQ);
3075
3076         gen8_gt_irq_reset(dev_priv);
3077
3078         GEN5_IRQ_RESET(GEN8_PCU_);
3079
3080         spin_lock_irq(&dev_priv->irq_lock);
3081         if (dev_priv->display_irqs_enabled)
3082                 vlv_display_irq_reset(dev_priv);
3083         spin_unlock_irq(&dev_priv->irq_lock);
3084 }
3085
3086 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3087                                   const u32 hpd[HPD_NUM_PINS])
3088 {
3089         struct intel_encoder *encoder;
3090         u32 enabled_irqs = 0;
3091
3092         for_each_intel_encoder(&dev_priv->drm, encoder)
3093                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3094                         enabled_irqs |= hpd[encoder->hpd_pin];
3095
3096         return enabled_irqs;
3097 }
3098
3099 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3100 {
3101         u32 hotplug_irqs, hotplug, enabled_irqs;
3102
3103         if (HAS_PCH_IBX(dev_priv)) {
3104                 hotplug_irqs = SDE_HOTPLUG_MASK;
3105                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3106         } else {
3107                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3108                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3109         }
3110
3111         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3112
3113         /*
3114          * Enable digital hotplug on the PCH, and configure the DP short pulse
3115          * duration to 2ms (which is the minimum in the Display Port spec).
3116          * The pulse duration bits are reserved on LPT+.
3117          */
3118         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3119         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3120         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3121         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3122         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3123         /*
3124          * When CPU and PCH are on the same package, port A
3125          * HPD must be enabled in both north and south.
3126          */
3127         if (HAS_PCH_LPT_LP(dev_priv))
3128                 hotplug |= PORTA_HOTPLUG_ENABLE;
3129         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3130 }
3131
3132 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3133 {
3134         u32 hotplug_irqs, hotplug, enabled_irqs;
3135
3136         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3137         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3138
3139         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3140
3141         /* Enable digital hotplug on the PCH */
3142         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3143         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3144                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3145         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3146
3147         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3148         hotplug |= PORTE_HOTPLUG_ENABLE;
3149         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3150 }
3151
3152 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3153 {
3154         u32 hotplug_irqs, hotplug, enabled_irqs;
3155
3156         if (INTEL_GEN(dev_priv) >= 8) {
3157                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3158                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3159
3160                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3161         } else if (INTEL_GEN(dev_priv) >= 7) {
3162                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3163                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3164
3165                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3166         } else {
3167                 hotplug_irqs = DE_DP_A_HOTPLUG;
3168                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3169
3170                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3171         }
3172
3173         /*
3174          * Enable digital hotplug on the CPU, and configure the DP short pulse
3175          * duration to 2ms (which is the minimum in the Display Port spec)
3176          * The pulse duration bits are reserved on HSW+.
3177          */
3178         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3179         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3180         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3181         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3182
3183         ibx_hpd_irq_setup(dev_priv);
3184 }
3185
3186 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3187 {
3188         u32 hotplug_irqs, hotplug, enabled_irqs;
3189
3190         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3191         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3192
3193         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3194
3195         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3196         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3197                 PORTA_HOTPLUG_ENABLE;
3198
3199         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3200                       hotplug, enabled_irqs);
3201         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3202
3203         /*
3204          * For BXT invert bit has to be set based on AOB design
3205          * for HPD detection logic, update it based on VBT fields.
3206          */
3207
3208         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3209             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3210                 hotplug |= BXT_DDIA_HPD_INVERT;
3211         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3212             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3213                 hotplug |= BXT_DDIB_HPD_INVERT;
3214         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3215             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3216                 hotplug |= BXT_DDIC_HPD_INVERT;
3217
3218         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3219 }
3220
3221 static void ibx_irq_postinstall(struct drm_device *dev)
3222 {
3223         struct drm_i915_private *dev_priv = to_i915(dev);
3224         u32 mask;
3225
3226         if (HAS_PCH_NOP(dev_priv))
3227                 return;
3228
3229         if (HAS_PCH_IBX(dev_priv))
3230                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3231         else
3232                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3233
3234         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3235         I915_WRITE(SDEIMR, ~mask);
3236 }
3237
3238 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3239 {
3240         struct drm_i915_private *dev_priv = to_i915(dev);
3241         u32 pm_irqs, gt_irqs;
3242
3243         pm_irqs = gt_irqs = 0;
3244
3245         dev_priv->gt_irq_mask = ~0;
3246         if (HAS_L3_DPF(dev_priv)) {
3247                 /* L3 parity interrupt is always unmasked. */
3248                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3249                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3250         }
3251
3252         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3253         if (IS_GEN5(dev_priv)) {
3254                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3255         } else {
3256                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3257         }
3258
3259         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3260
3261         if (INTEL_GEN(dev_priv) >= 6) {
3262                 /*
3263                  * RPS interrupts will get enabled/disabled on demand when RPS
3264                  * itself is enabled/disabled.
3265                  */
3266                 if (HAS_VEBOX(dev_priv)) {
3267                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3268                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3269                 }
3270
3271                 dev_priv->pm_imr = 0xffffffff;
3272                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3273         }
3274 }
3275
3276 static int ironlake_irq_postinstall(struct drm_device *dev)
3277 {
3278         struct drm_i915_private *dev_priv = to_i915(dev);
3279         u32 display_mask, extra_mask;
3280
3281         if (INTEL_GEN(dev_priv) >= 7) {
3282                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3283                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3284                                 DE_PLANEB_FLIP_DONE_IVB |
3285                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3286                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3287                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3288                               DE_DP_A_HOTPLUG_IVB);
3289         } else {
3290                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3291                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3292                                 DE_AUX_CHANNEL_A |
3293                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3294                                 DE_POISON);
3295                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3296                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3297                               DE_DP_A_HOTPLUG);
3298         }
3299
3300         dev_priv->irq_mask = ~display_mask;
3301
3302         I915_WRITE(HWSTAM, 0xeffe);
3303
3304         ibx_irq_pre_postinstall(dev);
3305
3306         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3307
3308         gen5_gt_irq_postinstall(dev);
3309
3310         ibx_irq_postinstall(dev);
3311
3312         if (IS_IRONLAKE_M(dev_priv)) {
3313                 /* Enable PCU event interrupts
3314                  *
3315                  * spinlocking not required here for correctness since interrupt
3316                  * setup is guaranteed to run in single-threaded context. But we
3317                  * need it to make the assert_spin_locked happy. */
3318                 spin_lock_irq(&dev_priv->irq_lock);
3319                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3320                 spin_unlock_irq(&dev_priv->irq_lock);
3321         }
3322
3323         return 0;
3324 }
3325
3326 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3327 {
3328         assert_spin_locked(&dev_priv->irq_lock);
3329
3330         if (dev_priv->display_irqs_enabled)
3331                 return;
3332
3333         dev_priv->display_irqs_enabled = true;
3334
3335         if (intel_irqs_enabled(dev_priv)) {
3336                 vlv_display_irq_reset(dev_priv);
3337                 vlv_display_irq_postinstall(dev_priv);
3338         }
3339 }
3340
3341 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3342 {
3343         assert_spin_locked(&dev_priv->irq_lock);
3344
3345         if (!dev_priv->display_irqs_enabled)
3346                 return;
3347
3348         dev_priv->display_irqs_enabled = false;
3349
3350         if (intel_irqs_enabled(dev_priv))
3351                 vlv_display_irq_reset(dev_priv);
3352 }
3353
3354
3355 static int valleyview_irq_postinstall(struct drm_device *dev)
3356 {
3357         struct drm_i915_private *dev_priv = to_i915(dev);
3358
3359         gen5_gt_irq_postinstall(dev);
3360
3361         spin_lock_irq(&dev_priv->irq_lock);
3362         if (dev_priv->display_irqs_enabled)
3363                 vlv_display_irq_postinstall(dev_priv);
3364         spin_unlock_irq(&dev_priv->irq_lock);
3365
3366         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3367         POSTING_READ(VLV_MASTER_IER);
3368
3369         return 0;
3370 }
3371
3372 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3373 {
3374         /* These are interrupts we'll toggle with the ring mask register */
3375         uint32_t gt_interrupts[] = {
3376                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3377                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3378                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3379                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3380                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3381                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3382                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3383                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3384                 0,
3385                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3386                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3387                 };
3388
3389         if (HAS_L3_DPF(dev_priv))
3390                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3391
3392         dev_priv->pm_ier = 0x0;
3393         dev_priv->pm_imr = ~dev_priv->pm_ier;
3394         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3395         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3396         /*
3397          * RPS interrupts will get enabled/disabled on demand when RPS itself
3398          * is enabled/disabled. Same wil be the case for GuC interrupts.
3399          */
3400         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3401         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3402 }
3403
3404 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3405 {
3406         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3407         uint32_t de_pipe_enables;
3408         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3409         u32 de_port_enables;
3410         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3411         enum pipe pipe;
3412
3413         if (INTEL_INFO(dev_priv)->gen >= 9) {
3414                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3415                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3416                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3417                                   GEN9_AUX_CHANNEL_D;
3418                 if (IS_GEN9_LP(dev_priv))
3419                         de_port_masked |= BXT_DE_PORT_GMBUS;
3420         } else {
3421                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3422                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3423         }
3424
3425         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3426                                            GEN8_PIPE_FIFO_UNDERRUN;
3427
3428         de_port_enables = de_port_masked;
3429         if (IS_GEN9_LP(dev_priv))
3430                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3431         else if (IS_BROADWELL(dev_priv))
3432                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3433
3434         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3435         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3436         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3437
3438         for_each_pipe(dev_priv, pipe)
3439                 if (intel_display_power_is_enabled(dev_priv,
3440                                 POWER_DOMAIN_PIPE(pipe)))
3441                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3442                                           dev_priv->de_irq_mask[pipe],
3443                                           de_pipe_enables);
3444
3445         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3446         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3447 }
3448
3449 static int gen8_irq_postinstall(struct drm_device *dev)
3450 {
3451         struct drm_i915_private *dev_priv = to_i915(dev);
3452
3453         if (HAS_PCH_SPLIT(dev_priv))
3454                 ibx_irq_pre_postinstall(dev);
3455
3456         gen8_gt_irq_postinstall(dev_priv);
3457         gen8_de_irq_postinstall(dev_priv);
3458
3459         if (HAS_PCH_SPLIT(dev_priv))
3460                 ibx_irq_postinstall(dev);
3461
3462         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3463         POSTING_READ(GEN8_MASTER_IRQ);
3464
3465         return 0;
3466 }
3467
3468 static int cherryview_irq_postinstall(struct drm_device *dev)
3469 {
3470         struct drm_i915_private *dev_priv = to_i915(dev);
3471
3472         gen8_gt_irq_postinstall(dev_priv);
3473
3474         spin_lock_irq(&dev_priv->irq_lock);
3475         if (dev_priv->display_irqs_enabled)
3476                 vlv_display_irq_postinstall(dev_priv);
3477         spin_unlock_irq(&dev_priv->irq_lock);
3478
3479         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3480         POSTING_READ(GEN8_MASTER_IRQ);
3481
3482         return 0;
3483 }
3484
3485 static void gen8_irq_uninstall(struct drm_device *dev)
3486 {
3487         struct drm_i915_private *dev_priv = to_i915(dev);
3488
3489         if (!dev_priv)
3490                 return;
3491
3492         gen8_irq_reset(dev);
3493 }
3494
3495 static void valleyview_irq_uninstall(struct drm_device *dev)
3496 {
3497         struct drm_i915_private *dev_priv = to_i915(dev);
3498
3499         if (!dev_priv)
3500                 return;
3501
3502         I915_WRITE(VLV_MASTER_IER, 0);
3503         POSTING_READ(VLV_MASTER_IER);
3504
3505         gen5_gt_irq_reset(dev_priv);
3506
3507         I915_WRITE(HWSTAM, 0xffffffff);
3508
3509         spin_lock_irq(&dev_priv->irq_lock);
3510         if (dev_priv->display_irqs_enabled)
3511                 vlv_display_irq_reset(dev_priv);
3512         spin_unlock_irq(&dev_priv->irq_lock);
3513 }
3514
3515 static void cherryview_irq_uninstall(struct drm_device *dev)
3516 {
3517         struct drm_i915_private *dev_priv = to_i915(dev);
3518
3519         if (!dev_priv)
3520                 return;
3521
3522         I915_WRITE(GEN8_MASTER_IRQ, 0);
3523         POSTING_READ(GEN8_MASTER_IRQ);
3524
3525         gen8_gt_irq_reset(dev_priv);
3526
3527         GEN5_IRQ_RESET(GEN8_PCU_);
3528
3529         spin_lock_irq(&dev_priv->irq_lock);
3530         if (dev_priv->display_irqs_enabled)
3531                 vlv_display_irq_reset(dev_priv);
3532         spin_unlock_irq(&dev_priv->irq_lock);
3533 }
3534
3535 static void ironlake_irq_uninstall(struct drm_device *dev)
3536 {
3537         struct drm_i915_private *dev_priv = to_i915(dev);
3538
3539         if (!dev_priv)
3540                 return;
3541
3542         ironlake_irq_reset(dev);
3543 }
3544
3545 static void i8xx_irq_preinstall(struct drm_device * dev)
3546 {
3547         struct drm_i915_private *dev_priv = to_i915(dev);
3548         int pipe;
3549
3550         for_each_pipe(dev_priv, pipe)
3551                 I915_WRITE(PIPESTAT(pipe), 0);
3552         I915_WRITE16(IMR, 0xffff);
3553         I915_WRITE16(IER, 0x0);
3554         POSTING_READ16(IER);
3555 }
3556
3557 static int i8xx_irq_postinstall(struct drm_device *dev)
3558 {
3559         struct drm_i915_private *dev_priv = to_i915(dev);
3560
3561         I915_WRITE16(EMR,
3562                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3563
3564         /* Unmask the interrupts that we always want on. */
3565         dev_priv->irq_mask =
3566                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3567                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3568                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3569                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3570         I915_WRITE16(IMR, dev_priv->irq_mask);
3571
3572         I915_WRITE16(IER,
3573                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3574                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3575                      I915_USER_INTERRUPT);
3576         POSTING_READ16(IER);
3577
3578         /* Interrupt setup is already guaranteed to be single-threaded, this is
3579          * just to make the assert_spin_locked check happy. */
3580         spin_lock_irq(&dev_priv->irq_lock);
3581         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3582         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3583         spin_unlock_irq(&dev_priv->irq_lock);
3584
3585         return 0;
3586 }
3587
3588 /*
3589  * Returns true when a page flip has completed.
3590  */
3591 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3592                                int plane, int pipe, u32 iir)
3593 {
3594         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3595
3596         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3597                 return false;
3598
3599         if ((iir & flip_pending) == 0)
3600                 goto check_page_flip;
3601
3602         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3603          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3604          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3605          * the flip is completed (no longer pending). Since this doesn't raise
3606          * an interrupt per se, we watch for the change at vblank.
3607          */
3608         if (I915_READ16(ISR) & flip_pending)
3609                 goto check_page_flip;
3610
3611         intel_finish_page_flip_cs(dev_priv, pipe);
3612         return true;
3613
3614 check_page_flip:
3615         intel_check_page_flip(dev_priv, pipe);
3616         return false;
3617 }
3618
3619 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3620 {
3621         struct drm_device *dev = arg;
3622         struct drm_i915_private *dev_priv = to_i915(dev);
3623         u16 iir, new_iir;
3624         u32 pipe_stats[2];
3625         int pipe;
3626         u16 flip_mask =
3627                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3628                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3629         irqreturn_t ret;
3630
3631         if (!intel_irqs_enabled(dev_priv))
3632                 return IRQ_NONE;
3633
3634         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3635         disable_rpm_wakeref_asserts(dev_priv);
3636
3637         ret = IRQ_NONE;
3638         iir = I915_READ16(IIR);
3639         if (iir == 0)
3640                 goto out;
3641
3642         while (iir & ~flip_mask) {
3643                 /* Can't rely on pipestat interrupt bit in iir as it might
3644                  * have been cleared after the pipestat interrupt was received.
3645                  * It doesn't set the bit in iir again, but it still produces
3646                  * interrupts (for non-MSI).
3647                  */
3648                 spin_lock(&dev_priv->irq_lock);
3649                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3650                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3651
3652                 for_each_pipe(dev_priv, pipe) {
3653                         i915_reg_t reg = PIPESTAT(pipe);
3654                         pipe_stats[pipe] = I915_READ(reg);
3655
3656                         /*
3657                          * Clear the PIPE*STAT regs before the IIR
3658                          */
3659                         if (pipe_stats[pipe] & 0x8000ffff)
3660                                 I915_WRITE(reg, pipe_stats[pipe]);
3661                 }
3662                 spin_unlock(&dev_priv->irq_lock);
3663
3664                 I915_WRITE16(IIR, iir & ~flip_mask);
3665                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3666
3667                 if (iir & I915_USER_INTERRUPT)
3668                         notify_ring(dev_priv->engine[RCS]);
3669
3670                 for_each_pipe(dev_priv, pipe) {
3671                         int plane = pipe;
3672                         if (HAS_FBC(dev_priv))
3673                                 plane = !plane;
3674
3675                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3676                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3677                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3678
3679                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3680                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3681
3682                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3683                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3684                                                                     pipe);
3685                 }
3686
3687                 iir = new_iir;
3688         }
3689         ret = IRQ_HANDLED;
3690
3691 out:
3692         enable_rpm_wakeref_asserts(dev_priv);
3693
3694         return ret;
3695 }
3696
3697 static void i8xx_irq_uninstall(struct drm_device * dev)
3698 {
3699         struct drm_i915_private *dev_priv = to_i915(dev);
3700         int pipe;
3701
3702         for_each_pipe(dev_priv, pipe) {
3703                 /* Clear enable bits; then clear status bits */
3704                 I915_WRITE(PIPESTAT(pipe), 0);
3705                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3706         }
3707         I915_WRITE16(IMR, 0xffff);
3708         I915_WRITE16(IER, 0x0);
3709         I915_WRITE16(IIR, I915_READ16(IIR));
3710 }
3711
3712 static void i915_irq_preinstall(struct drm_device * dev)
3713 {
3714         struct drm_i915_private *dev_priv = to_i915(dev);
3715         int pipe;
3716
3717         if (I915_HAS_HOTPLUG(dev_priv)) {
3718                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3719                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3720         }
3721
3722         I915_WRITE16(HWSTAM, 0xeffe);
3723         for_each_pipe(dev_priv, pipe)
3724                 I915_WRITE(PIPESTAT(pipe), 0);
3725         I915_WRITE(IMR, 0xffffffff);
3726         I915_WRITE(IER, 0x0);
3727         POSTING_READ(IER);
3728 }
3729
3730 static int i915_irq_postinstall(struct drm_device *dev)
3731 {
3732         struct drm_i915_private *dev_priv = to_i915(dev);
3733         u32 enable_mask;
3734
3735         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3736
3737         /* Unmask the interrupts that we always want on. */
3738         dev_priv->irq_mask =
3739                 ~(I915_ASLE_INTERRUPT |
3740                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3741                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3742                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3743                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3744
3745         enable_mask =
3746                 I915_ASLE_INTERRUPT |
3747                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3748                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3749                 I915_USER_INTERRUPT;
3750
3751         if (I915_HAS_HOTPLUG(dev_priv)) {
3752                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3753                 POSTING_READ(PORT_HOTPLUG_EN);
3754
3755                 /* Enable in IER... */
3756                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3757                 /* and unmask in IMR */
3758                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3759         }
3760
3761         I915_WRITE(IMR, dev_priv->irq_mask);
3762         I915_WRITE(IER, enable_mask);
3763         POSTING_READ(IER);
3764
3765         i915_enable_asle_pipestat(dev_priv);
3766
3767         /* Interrupt setup is already guaranteed to be single-threaded, this is
3768          * just to make the assert_spin_locked check happy. */
3769         spin_lock_irq(&dev_priv->irq_lock);
3770         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3771         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3772         spin_unlock_irq(&dev_priv->irq_lock);
3773
3774         return 0;
3775 }
3776
3777 /*
3778  * Returns true when a page flip has completed.
3779  */
3780 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3781                                int plane, int pipe, u32 iir)
3782 {
3783         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3784
3785         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3786                 return false;
3787
3788         if ((iir & flip_pending) == 0)
3789                 goto check_page_flip;
3790
3791         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3792          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3793          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3794          * the flip is completed (no longer pending). Since this doesn't raise
3795          * an interrupt per se, we watch for the change at vblank.
3796          */
3797         if (I915_READ(ISR) & flip_pending)
3798                 goto check_page_flip;
3799
3800         intel_finish_page_flip_cs(dev_priv, pipe);
3801         return true;
3802
3803 check_page_flip:
3804         intel_check_page_flip(dev_priv, pipe);
3805         return false;
3806 }
3807
3808 static irqreturn_t i915_irq_handler(int irq, void *arg)
3809 {
3810         struct drm_device *dev = arg;
3811         struct drm_i915_private *dev_priv = to_i915(dev);
3812         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3813         u32 flip_mask =
3814                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3815                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3816         int pipe, ret = IRQ_NONE;
3817
3818         if (!intel_irqs_enabled(dev_priv))
3819                 return IRQ_NONE;
3820
3821         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3822         disable_rpm_wakeref_asserts(dev_priv);
3823
3824         iir = I915_READ(IIR);
3825         do {
3826                 bool irq_received = (iir & ~flip_mask) != 0;
3827                 bool blc_event = false;
3828
3829                 /* Can't rely on pipestat interrupt bit in iir as it might
3830                  * have been cleared after the pipestat interrupt was received.
3831                  * It doesn't set the bit in iir again, but it still produces
3832                  * interrupts (for non-MSI).
3833                  */
3834                 spin_lock(&dev_priv->irq_lock);
3835                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3836                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3837
3838                 for_each_pipe(dev_priv, pipe) {
3839                         i915_reg_t reg = PIPESTAT(pipe);
3840                         pipe_stats[pipe] = I915_READ(reg);
3841
3842                         /* Clear the PIPE*STAT regs before the IIR */
3843                         if (pipe_stats[pipe] & 0x8000ffff) {
3844                                 I915_WRITE(reg, pipe_stats[pipe]);
3845                                 irq_received = true;
3846                         }
3847                 }
3848                 spin_unlock(&dev_priv->irq_lock);
3849
3850                 if (!irq_received)
3851                         break;
3852
3853                 /* Consume port.  Then clear IIR or we'll miss events */
3854                 if (I915_HAS_HOTPLUG(dev_priv) &&
3855                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3856                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3857                         if (hotplug_status)
3858                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3859                 }
3860
3861                 I915_WRITE(IIR, iir & ~flip_mask);
3862                 new_iir = I915_READ(IIR); /* Flush posted writes */
3863
3864                 if (iir & I915_USER_INTERRUPT)
3865                         notify_ring(dev_priv->engine[RCS]);
3866
3867                 for_each_pipe(dev_priv, pipe) {
3868                         int plane = pipe;
3869                         if (HAS_FBC(dev_priv))
3870                                 plane = !plane;
3871
3872                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3873                             i915_handle_vblank(dev_priv, plane, pipe, iir))
3874                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3875
3876                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3877                                 blc_event = true;
3878
3879                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3880                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3881
3882                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3883                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3884                                                                     pipe);
3885                 }
3886
3887                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3888                         intel_opregion_asle_intr(dev_priv);
3889
3890                 /* With MSI, interrupts are only generated when iir
3891                  * transitions from zero to nonzero.  If another bit got
3892                  * set while we were handling the existing iir bits, then
3893                  * we would never get another interrupt.
3894                  *
3895                  * This is fine on non-MSI as well, as if we hit this path
3896                  * we avoid exiting the interrupt handler only to generate
3897                  * another one.
3898                  *
3899                  * Note that for MSI this could cause a stray interrupt report
3900                  * if an interrupt landed in the time between writing IIR and
3901                  * the posting read.  This should be rare enough to never
3902                  * trigger the 99% of 100,000 interrupts test for disabling
3903                  * stray interrupts.
3904                  */
3905                 ret = IRQ_HANDLED;
3906                 iir = new_iir;
3907         } while (iir & ~flip_mask);
3908
3909         enable_rpm_wakeref_asserts(dev_priv);
3910
3911         return ret;
3912 }
3913
3914 static void i915_irq_uninstall(struct drm_device * dev)
3915 {
3916         struct drm_i915_private *dev_priv = to_i915(dev);
3917         int pipe;
3918
3919         if (I915_HAS_HOTPLUG(dev_priv)) {
3920                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3921                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3922         }
3923
3924         I915_WRITE16(HWSTAM, 0xffff);
3925         for_each_pipe(dev_priv, pipe) {
3926                 /* Clear enable bits; then clear status bits */
3927                 I915_WRITE(PIPESTAT(pipe), 0);
3928                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3929         }
3930         I915_WRITE(IMR, 0xffffffff);
3931         I915_WRITE(IER, 0x0);
3932
3933         I915_WRITE(IIR, I915_READ(IIR));
3934 }
3935
3936 static void i965_irq_preinstall(struct drm_device * dev)
3937 {
3938         struct drm_i915_private *dev_priv = to_i915(dev);
3939         int pipe;
3940
3941         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3942         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3943
3944         I915_WRITE(HWSTAM, 0xeffe);
3945         for_each_pipe(dev_priv, pipe)
3946                 I915_WRITE(PIPESTAT(pipe), 0);
3947         I915_WRITE(IMR, 0xffffffff);
3948         I915_WRITE(IER, 0x0);
3949         POSTING_READ(IER);
3950 }
3951
3952 static int i965_irq_postinstall(struct drm_device *dev)
3953 {
3954         struct drm_i915_private *dev_priv = to_i915(dev);
3955         u32 enable_mask;
3956         u32 error_mask;
3957
3958         /* Unmask the interrupts that we always want on. */
3959         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3960                                I915_DISPLAY_PORT_INTERRUPT |
3961                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3962                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3963                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3964                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3965                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3966
3967         enable_mask = ~dev_priv->irq_mask;
3968         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3969                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3970         enable_mask |= I915_USER_INTERRUPT;
3971
3972         if (IS_G4X(dev_priv))
3973                 enable_mask |= I915_BSD_USER_INTERRUPT;
3974
3975         /* Interrupt setup is already guaranteed to be single-threaded, this is
3976          * just to make the assert_spin_locked check happy. */
3977         spin_lock_irq(&dev_priv->irq_lock);
3978         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3979         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3980         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3981         spin_unlock_irq(&dev_priv->irq_lock);
3982
3983         /*
3984          * Enable some error detection, note the instruction error mask
3985          * bit is reserved, so we leave it masked.
3986          */
3987         if (IS_G4X(dev_priv)) {
3988                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3989                                GM45_ERROR_MEM_PRIV |
3990                                GM45_ERROR_CP_PRIV |
3991                                I915_ERROR_MEMORY_REFRESH);
3992         } else {
3993                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3994                                I915_ERROR_MEMORY_REFRESH);
3995         }
3996         I915_WRITE(EMR, error_mask);
3997
3998         I915_WRITE(IMR, dev_priv->irq_mask);
3999         I915_WRITE(IER, enable_mask);
4000         POSTING_READ(IER);
4001
4002         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4003         POSTING_READ(PORT_HOTPLUG_EN);
4004
4005         i915_enable_asle_pipestat(dev_priv);
4006
4007         return 0;
4008 }
4009
4010 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4011 {
4012         u32 hotplug_en;
4013
4014         assert_spin_locked(&dev_priv->irq_lock);
4015
4016         /* Note HDMI and DP share hotplug bits */
4017         /* enable bits are the same for all generations */
4018         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4019         /* Programming the CRT detection parameters tends
4020            to generate a spurious hotplug event about three
4021            seconds later.  So just do it once.
4022         */
4023         if (IS_G4X(dev_priv))
4024                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4025         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4026
4027         /* Ignore TV since it's buggy */
4028         i915_hotplug_interrupt_update_locked(dev_priv,
4029                                              HOTPLUG_INT_EN_MASK |
4030                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4031                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4032                                              hotplug_en);
4033 }
4034
4035 static irqreturn_t i965_irq_handler(int irq, void *arg)
4036 {
4037         struct drm_device *dev = arg;
4038         struct drm_i915_private *dev_priv = to_i915(dev);
4039         u32 iir, new_iir;
4040         u32 pipe_stats[I915_MAX_PIPES];
4041         int ret = IRQ_NONE, pipe;
4042         u32 flip_mask =
4043                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4044                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4045
4046         if (!intel_irqs_enabled(dev_priv))
4047                 return IRQ_NONE;
4048
4049         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4050         disable_rpm_wakeref_asserts(dev_priv);
4051
4052         iir = I915_READ(IIR);
4053
4054         for (;;) {
4055                 bool irq_received = (iir & ~flip_mask) != 0;
4056                 bool blc_event = false;
4057
4058                 /* Can't rely on pipestat interrupt bit in iir as it might
4059                  * have been cleared after the pipestat interrupt was received.
4060                  * It doesn't set the bit in iir again, but it still produces
4061                  * interrupts (for non-MSI).
4062                  */
4063                 spin_lock(&dev_priv->irq_lock);
4064                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4065                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4066
4067                 for_each_pipe(dev_priv, pipe) {
4068                         i915_reg_t reg = PIPESTAT(pipe);
4069                         pipe_stats[pipe] = I915_READ(reg);
4070
4071                         /*
4072                          * Clear the PIPE*STAT regs before the IIR
4073                          */
4074                         if (pipe_stats[pipe] & 0x8000ffff) {
4075                                 I915_WRITE(reg, pipe_stats[pipe]);
4076                                 irq_received = true;
4077                         }
4078                 }
4079                 spin_unlock(&dev_priv->irq_lock);
4080
4081                 if (!irq_received)
4082                         break;
4083
4084                 ret = IRQ_HANDLED;
4085
4086                 /* Consume port.  Then clear IIR or we'll miss events */
4087                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4088                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4089                         if (hotplug_status)
4090                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4091                 }
4092
4093                 I915_WRITE(IIR, iir & ~flip_mask);
4094                 new_iir = I915_READ(IIR); /* Flush posted writes */
4095
4096                 if (iir & I915_USER_INTERRUPT)
4097                         notify_ring(dev_priv->engine[RCS]);
4098                 if (iir & I915_BSD_USER_INTERRUPT)
4099                         notify_ring(dev_priv->engine[VCS]);
4100
4101                 for_each_pipe(dev_priv, pipe) {
4102                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4103                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4104                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4105
4106                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4107                                 blc_event = true;
4108
4109                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4110                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4111
4112                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4113                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4114                 }
4115
4116                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4117                         intel_opregion_asle_intr(dev_priv);
4118
4119                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4120                         gmbus_irq_handler(dev_priv);
4121
4122                 /* With MSI, interrupts are only generated when iir
4123                  * transitions from zero to nonzero.  If another bit got
4124                  * set while we were handling the existing iir bits, then
4125                  * we would never get another interrupt.
4126                  *
4127                  * This is fine on non-MSI as well, as if we hit this path
4128                  * we avoid exiting the interrupt handler only to generate
4129                  * another one.
4130                  *
4131                  * Note that for MSI this could cause a stray interrupt report
4132                  * if an interrupt landed in the time between writing IIR and
4133                  * the posting read.  This should be rare enough to never
4134                  * trigger the 99% of 100,000 interrupts test for disabling
4135                  * stray interrupts.
4136                  */
4137                 iir = new_iir;
4138         }
4139
4140         enable_rpm_wakeref_asserts(dev_priv);
4141
4142         return ret;
4143 }
4144
4145 static void i965_irq_uninstall(struct drm_device * dev)
4146 {
4147         struct drm_i915_private *dev_priv = to_i915(dev);
4148         int pipe;
4149
4150         if (!dev_priv)
4151                 return;
4152
4153         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4154         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4155
4156         I915_WRITE(HWSTAM, 0xffffffff);
4157         for_each_pipe(dev_priv, pipe)
4158                 I915_WRITE(PIPESTAT(pipe), 0);
4159         I915_WRITE(IMR, 0xffffffff);
4160         I915_WRITE(IER, 0x0);
4161
4162         for_each_pipe(dev_priv, pipe)
4163                 I915_WRITE(PIPESTAT(pipe),
4164                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4165         I915_WRITE(IIR, I915_READ(IIR));
4166 }
4167
4168 /**
4169  * intel_irq_init - initializes irq support
4170  * @dev_priv: i915 device instance
4171  *
4172  * This function initializes all the irq support including work items, timers
4173  * and all the vtables. It does not setup the interrupt itself though.
4174  */
4175 void intel_irq_init(struct drm_i915_private *dev_priv)
4176 {
4177         struct drm_device *dev = &dev_priv->drm;
4178
4179         intel_hpd_init_work(dev_priv);
4180
4181         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4182         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4183
4184         if (HAS_GUC_SCHED(dev_priv))
4185                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4186
4187         /* Let's track the enabled rps events */
4188         if (IS_VALLEYVIEW(dev_priv))
4189                 /* WaGsvRC0ResidencyMethod:vlv */
4190                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4191         else
4192                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4193
4194         dev_priv->rps.pm_intr_keep = 0;
4195
4196         /*
4197          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4198          * if GEN6_PM_UP_EI_EXPIRED is masked.
4199          *
4200          * TODO: verify if this can be reproduced on VLV,CHV.
4201          */
4202         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4203                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4204
4205         if (INTEL_INFO(dev_priv)->gen >= 8)
4206                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4207
4208         if (IS_GEN2(dev_priv)) {
4209                 /* Gen2 doesn't have a hardware frame counter */
4210                 dev->max_vblank_count = 0;
4211                 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4212         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4213                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4214                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4215         } else {
4216                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4217                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4218         }
4219
4220         /*
4221          * Opt out of the vblank disable timer on everything except gen2.
4222          * Gen2 doesn't have a hardware frame counter and so depends on
4223          * vblank interrupts to produce sane vblank seuquence numbers.
4224          */
4225         if (!IS_GEN2(dev_priv))
4226                 dev->vblank_disable_immediate = true;
4227
4228         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4229         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4230
4231         if (IS_CHERRYVIEW(dev_priv)) {
4232                 dev->driver->irq_handler = cherryview_irq_handler;
4233                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4234                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4235                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4236                 dev->driver->enable_vblank = i965_enable_vblank;
4237                 dev->driver->disable_vblank = i965_disable_vblank;
4238                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4239         } else if (IS_VALLEYVIEW(dev_priv)) {
4240                 dev->driver->irq_handler = valleyview_irq_handler;
4241                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4242                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4243                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4244                 dev->driver->enable_vblank = i965_enable_vblank;
4245                 dev->driver->disable_vblank = i965_disable_vblank;
4246                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4247         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4248                 dev->driver->irq_handler = gen8_irq_handler;
4249                 dev->driver->irq_preinstall = gen8_irq_reset;
4250                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4251                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4252                 dev->driver->enable_vblank = gen8_enable_vblank;
4253                 dev->driver->disable_vblank = gen8_disable_vblank;
4254                 if (IS_GEN9_LP(dev_priv))
4255                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4256                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4257                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4258                 else
4259                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4260         } else if (HAS_PCH_SPLIT(dev_priv)) {
4261                 dev->driver->irq_handler = ironlake_irq_handler;
4262                 dev->driver->irq_preinstall = ironlake_irq_reset;
4263                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4264                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4265                 dev->driver->enable_vblank = ironlake_enable_vblank;
4266                 dev->driver->disable_vblank = ironlake_disable_vblank;
4267                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4268         } else {
4269                 if (IS_GEN2(dev_priv)) {
4270                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4271                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4272                         dev->driver->irq_handler = i8xx_irq_handler;
4273                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4274                         dev->driver->enable_vblank = i8xx_enable_vblank;
4275                         dev->driver->disable_vblank = i8xx_disable_vblank;
4276                 } else if (IS_GEN3(dev_priv)) {
4277                         dev->driver->irq_preinstall = i915_irq_preinstall;
4278                         dev->driver->irq_postinstall = i915_irq_postinstall;
4279                         dev->driver->irq_uninstall = i915_irq_uninstall;
4280                         dev->driver->irq_handler = i915_irq_handler;
4281                         dev->driver->enable_vblank = i8xx_enable_vblank;
4282                         dev->driver->disable_vblank = i8xx_disable_vblank;
4283                 } else {
4284                         dev->driver->irq_preinstall = i965_irq_preinstall;
4285                         dev->driver->irq_postinstall = i965_irq_postinstall;
4286                         dev->driver->irq_uninstall = i965_irq_uninstall;
4287                         dev->driver->irq_handler = i965_irq_handler;
4288                         dev->driver->enable_vblank = i965_enable_vblank;
4289                         dev->driver->disable_vblank = i965_disable_vblank;
4290                 }
4291                 if (I915_HAS_HOTPLUG(dev_priv))
4292                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4293         }
4294 }
4295
4296 /**
4297  * intel_irq_install - enables the hardware interrupt
4298  * @dev_priv: i915 device instance
4299  *
4300  * This function enables the hardware interrupt handling, but leaves the hotplug
4301  * handling still disabled. It is called after intel_irq_init().
4302  *
4303  * In the driver load and resume code we need working interrupts in a few places
4304  * but don't want to deal with the hassle of concurrent probe and hotplug
4305  * workers. Hence the split into this two-stage approach.
4306  */
4307 int intel_irq_install(struct drm_i915_private *dev_priv)
4308 {
4309         /*
4310          * We enable some interrupt sources in our postinstall hooks, so mark
4311          * interrupts as enabled _before_ actually enabling them to avoid
4312          * special cases in our ordering checks.
4313          */
4314         dev_priv->pm.irqs_enabled = true;
4315
4316         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4317 }
4318
4319 /**
4320  * intel_irq_uninstall - finilizes all irq handling
4321  * @dev_priv: i915 device instance
4322  *
4323  * This stops interrupt and hotplug handling and unregisters and frees all
4324  * resources acquired in the init functions.
4325  */
4326 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4327 {
4328         drm_irq_uninstall(&dev_priv->drm);
4329         intel_hpd_cancel_work(dev_priv);
4330         dev_priv->pm.irqs_enabled = false;
4331 }
4332
4333 /**
4334  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4335  * @dev_priv: i915 device instance
4336  *
4337  * This function is used to disable interrupts at runtime, both in the runtime
4338  * pm and the system suspend/resume code.
4339  */
4340 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4341 {
4342         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4343         dev_priv->pm.irqs_enabled = false;
4344         synchronize_irq(dev_priv->drm.irq);
4345 }
4346
4347 /**
4348  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4349  * @dev_priv: i915 device instance
4350  *
4351  * This function is used to enable interrupts at runtime, both in the runtime
4352  * pm and the system suspend/resume code.
4353  */
4354 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4355 {
4356         dev_priv->pm.irqs_enabled = true;
4357         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4358         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4359 }