drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262         POSTING_READ(GTIMR);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         spin_lock_irq(&dev_priv->irq_lock);
 354
 355         WARN_ON(dev_priv->rps.pm_iir);
 356         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 357         dev_priv->rps.interrupts_enabled = true;
 358         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 359                                 dev_priv->pm_rps_events);
 360         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 361
 362         spin_unlock_irq(&dev_priv->irq_lock);
 363 }
 364
 365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 366 {
 367         /*
 368          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 369          * if GEN6_PM_UP_EI_EXPIRED is masked.
 370          *
 371          * TODO: verify if this can be reproduced on VLV,CHV.
 372          */
 373         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 374                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 375
 376         if (INTEL_INFO(dev_priv)->gen >= 8)
 377                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 378
 379         return mask;
 380 }
 381
 382 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 383 {
 384         spin_lock_irq(&dev_priv->irq_lock);
 385         dev_priv->rps.interrupts_enabled = false;
 386         spin_unlock_irq(&dev_priv->irq_lock);
 387
 388         cancel_work_sync(&dev_priv->rps.work);
 389
 390         spin_lock_irq(&dev_priv->irq_lock);
 391
 392         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 393
 394         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 395         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 396                                 ~dev_priv->pm_rps_events);
 397
 398         spin_unlock_irq(&dev_priv->irq_lock);
 399
 400         synchronize_irq(dev_priv->dev->irq);
 401 }
 402
 403 /**
 404  * bdw_update_port_irq - update DE port interrupt
 405  * @dev_priv: driver private
 406  * @interrupt_mask: mask of interrupt bits to update
 407  * @enabled_irq_mask: mask of interrupt bits to enable
 408  */
 409 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 410                                 uint32_t interrupt_mask,
 411                                 uint32_t enabled_irq_mask)
 412 {
 413         uint32_t new_val;
 414         uint32_t old_val;
 415
 416         assert_spin_locked(&dev_priv->irq_lock);
 417
 418         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 419
 420         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 421                 return;
 422
 423         old_val = I915_READ(GEN8_DE_PORT_IMR);
 424
 425         new_val = old_val;
 426         new_val &= ~interrupt_mask;
 427         new_val |= (~enabled_irq_mask & interrupt_mask);
 428
 429         if (new_val != old_val) {
 430                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 431                 POSTING_READ(GEN8_DE_PORT_IMR);
 432         }
 433 }
 434
 435 /**
 436  * bdw_update_pipe_irq - update DE pipe interrupt
 437  * @dev_priv: driver private
 438  * @pipe: pipe whose interrupt to update
 439  * @interrupt_mask: mask of interrupt bits to update
 440  * @enabled_irq_mask: mask of interrupt bits to enable
 441  */
 442 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 443                          enum pipe pipe,
 444                          uint32_t interrupt_mask,
 445                          uint32_t enabled_irq_mask)
 446 {
 447         uint32_t new_val;
 448
 449         assert_spin_locked(&dev_priv->irq_lock);
 450
 451         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 452
 453         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 454                 return;
 455
 456         new_val = dev_priv->de_irq_mask[pipe];
 457         new_val &= ~interrupt_mask;
 458         new_val |= (~enabled_irq_mask & interrupt_mask);
 459
 460         if (new_val != dev_priv->de_irq_mask[pipe]) {
 461                 dev_priv->de_irq_mask[pipe] = new_val;
 462                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 463                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 464         }
 465 }
 466
 467 /**
 468  * ibx_display_interrupt_update - update SDEIMR
 469  * @dev_priv: driver private
 470  * @interrupt_mask: mask of interrupt bits to update
 471  * @enabled_irq_mask: mask of interrupt bits to enable
 472  */
 473 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 474                                   uint32_t interrupt_mask,
 475                                   uint32_t enabled_irq_mask)
 476 {
 477         uint32_t sdeimr = I915_READ(SDEIMR);
 478         sdeimr &= ~interrupt_mask;
 479         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 480
 481         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 482
 483         assert_spin_locked(&dev_priv->irq_lock);
 484
 485         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 486                 return;
 487
 488         I915_WRITE(SDEIMR, sdeimr);
 489         POSTING_READ(SDEIMR);
 490 }
 491
 492 static void
 493 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 494                        u32 enable_mask, u32 status_mask)
 495 {
 496         i915_reg_t reg = PIPESTAT(pipe);
 497         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 498
 499         assert_spin_locked(&dev_priv->irq_lock);
 500         WARN_ON(!intel_irqs_enabled(dev_priv));
 501
 502         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 503                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 504                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 505                       pipe_name(pipe), enable_mask, status_mask))
 506                 return;
 507
 508         if ((pipestat & enable_mask) == enable_mask)
 509                 return;
 510
 511         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 512
 513         /* Enable the interrupt, clear any pending status */
 514         pipestat |= enable_mask | status_mask;
 515         I915_WRITE(reg, pipestat);
 516         POSTING_READ(reg);
 517 }
 518
 519 static void
 520 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 521                         u32 enable_mask, u32 status_mask)
 522 {
 523         i915_reg_t reg = PIPESTAT(pipe);
 524         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 525
 526         assert_spin_locked(&dev_priv->irq_lock);
 527         WARN_ON(!intel_irqs_enabled(dev_priv));
 528
 529         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 530                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 531                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 532                       pipe_name(pipe), enable_mask, status_mask))
 533                 return;
 534
 535         if ((pipestat & enable_mask) == 0)
 536                 return;
 537
 538         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 539
 540         pipestat &= ~enable_mask;
 541         I915_WRITE(reg, pipestat);
 542         POSTING_READ(reg);
 543 }
 544
 545 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 546 {
 547         u32 enable_mask = status_mask << 16;
 548
 549         /*
 550          * On pipe A we don't support the PSR interrupt yet,
 551          * on pipe B and C the same bit MBZ.
 552          */
 553         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 554                 return 0;
 555         /*
 556          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 557          * A the same bit is for perf counters which we don't use either.
 558          */
 559         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 560                 return 0;
 561
 562         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 563                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 564                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 565         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 566                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 567         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 568                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 569
 570         return enable_mask;
 571 }
 572
 573 void
 574 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 575                      u32 status_mask)
 576 {
 577         u32 enable_mask;
 578
 579         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 580                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 581                                                            status_mask);
 582         else
 583                 enable_mask = status_mask << 16;
 584         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 585 }
 586
 587 void
 588 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 589                       u32 status_mask)
 590 {
 591         u32 enable_mask;
 592
 593         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 594                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 595                                                            status_mask);
 596         else
 597                 enable_mask = status_mask << 16;
 598         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 599 }
 600
 601 /**
 602  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 603  * @dev: drm device
 604  */
 605 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 606 {
 607         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 608                 return;
 609
 610         spin_lock_irq(&dev_priv->irq_lock);
 611
 612         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 613         if (INTEL_GEN(dev_priv) >= 4)
 614                 i915_enable_pipestat(dev_priv, PIPE_A,
 615                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 616
 617         spin_unlock_irq(&dev_priv->irq_lock);
 618 }
 619
 620 /*
 621  * This timing diagram depicts the video signal in and
 622  * around the vertical blanking period.
 623  *
 624  * Assumptions about the fictitious mode used in this example:
 625  *  vblank_start >= 3
 626  *  vsync_start = vblank_start + 1
 627  *  vsync_end = vblank_start + 2
 628  *  vtotal = vblank_start + 3
 629  *
 630  *           start of vblank:
 631  *           latch double buffered registers
 632  *           increment frame counter (ctg+)
 633  *           generate start of vblank interrupt (gen4+)
 634  *           |
 635  *           |          frame start:
 636  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 637  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 638  *           |          |
 639  *           |          |  start of vsync:
 640  *           |          |  generate vsync interrupt
 641  *           |          |  |
 642  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 643  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 644  * ----va---> <-----------------vb--------------------> <--------va-------------
 645  *       |          |       <----vs----->                     |
 646  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 647  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 648  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 649  *       |          |                                         |
 650  *       last visible pixel                                   first visible pixel
 651  *                  |                                         increment frame counter (gen3/4)
 652  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 653  *
 654  * x  = horizontal active
 655  * _  = horizontal blanking
 656  * hs = horizontal sync
 657  * va = vertical active
 658  * vb = vertical blanking
 659  * vs = vertical sync
 660  * vbs = vblank_start (number)
 661  *
 662  * Summary:
 663  * - most events happen at the start of horizontal sync
 664  * - frame start happens at the start of horizontal blank, 1-4 lines
 665  *   (depending on PIPECONF settings) after the start of vblank
 666  * - gen3/4 pixel and frame counter are synchronized with the start
 667  *   of horizontal active on the first line of vertical active
 668  */
 669
 670 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 671 {
 672         /* Gen2 doesn't have a hardware frame counter */
 673         return 0;
 674 }
 675
 676 /* Called from drm generic code, passed a 'crtc', which
 677  * we use as a pipe index
 678  */
 679 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 680 {
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         i915_reg_t high_frame, low_frame;
 683         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 684         struct intel_crtc *intel_crtc =
 685                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 686         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 687
 688         htotal = mode->crtc_htotal;
 689         hsync_start = mode->crtc_hsync_start;
 690         vbl_start = mode->crtc_vblank_start;
 691         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 692                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 693
 694         /* Convert to pixel count */
 695         vbl_start *= htotal;
 696
 697         /* Start of vblank event occurs at start of hsync */
 698         vbl_start -= htotal - hsync_start;
 699
 700         high_frame = PIPEFRAME(pipe);
 701         low_frame = PIPEFRAMEPIXEL(pipe);
 702
 703         /*
 704          * High & low register fields aren't synchronized, so make sure
 705          * we get a low value that's stable across two reads of the high
 706          * register.
 707          */
 708         do {
 709                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 710                 low   = I915_READ(low_frame);
 711                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 712         } while (high1 != high2);
 713
 714         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 715         pixel = low & PIPE_PIXEL_MASK;
 716         low >>= PIPE_FRAME_LOW_SHIFT;
 717
 718         /*
 719          * The frame counter increments at beginning of active.
 720          * Cook up a vblank counter by also checking the pixel
 721          * counter against vblank start.
 722          */
 723         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 724 }
 725
 726 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729
 730         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 731 }
 732
 733 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 734 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 735 {
 736         struct drm_device *dev = crtc->base.dev;
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738         const struct drm_display_mode *mode = &crtc->base.hwmode;
 739         enum pipe pipe = crtc->pipe;
 740         int position, vtotal;
 741
 742         vtotal = mode->crtc_vtotal;
 743         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 744                 vtotal /= 2;
 745
 746         if (IS_GEN2(dev_priv))
 747                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 748         else
 749                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 750
 751         /*
 752          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 753          * read it just before the start of vblank.  So try it again
 754          * so we don't accidentally end up spanning a vblank frame
 755          * increment, causing the pipe_update_end() code to squak at us.
 756          *
 757          * The nature of this problem means we can't simply check the ISR
 758          * bit and return the vblank start value; nor can we use the scanline
 759          * debug register in the transcoder as it appears to have the same
 760          * problem.  We may need to extend this to include other platforms,
 761          * but so far testing only shows the problem on HSW.
 762          */
 763         if (HAS_DDI(dev_priv) && !position) {
 764                 int i, temp;
 765
 766                 for (i = 0; i < 100; i++) {
 767                         udelay(1);
 768                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 769                                 DSL_LINEMASK_GEN3;
 770                         if (temp != position) {
 771                                 position = temp;
 772                                 break;
 773                         }
 774                 }
 775         }
 776
 777         /*
 778          * See update_scanline_offset() for the details on the
 779          * scanline_offset adjustment.
 780          */
 781         return (position + crtc->scanline_offset) % vtotal;
 782 }
 783
 784 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 785                                     unsigned int flags, int *vpos, int *hpos,
 786                                     ktime_t *stime, ktime_t *etime,
 787                                     const struct drm_display_mode *mode)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 792         int position;
 793         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 794         bool in_vbl = true;
 795         int ret = 0;
 796         unsigned long irqflags;
 797
 798         if (WARN_ON(!mode->crtc_clock)) {
 799                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 800                                  "pipe %c\n", pipe_name(pipe));
 801                 return 0;
 802         }
 803
 804         htotal = mode->crtc_htotal;
 805         hsync_start = mode->crtc_hsync_start;
 806         vtotal = mode->crtc_vtotal;
 807         vbl_start = mode->crtc_vblank_start;
 808         vbl_end = mode->crtc_vblank_end;
 809
 810         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 811                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 812                 vbl_end /= 2;
 813                 vtotal /= 2;
 814         }
 815
 816         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 817
 818         /*
 819          * Lock uncore.lock, as we will do multiple timing critical raw
 820          * register reads, potentially with preemption disabled, so the
 821          * following code must not block on uncore.lock.
 822          */
 823         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 824
 825         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 826
 827         /* Get optional system timestamp before query. */
 828         if (stime)
 829                 *stime = ktime_get();
 830
 831         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 832                 /* No obvious pixelcount register. Only query vertical
 833                  * scanout position from Display scan line register.
 834                  */
 835                 position = __intel_get_crtc_scanline(intel_crtc);
 836         } else {
 837                 /* Have access to pixelcount since start of frame.
 838                  * We can split this into vertical and horizontal
 839                  * scanout position.
 840                  */
 841                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 842
 843                 /* convert to pixel counts */
 844                 vbl_start *= htotal;
 845                 vbl_end *= htotal;
 846                 vtotal *= htotal;
 847
 848                 /*
 849                  * In interlaced modes, the pixel counter counts all pixels,
 850                  * so one field will have htotal more pixels. In order to avoid
 851                  * the reported position from jumping backwards when the pixel
 852                  * counter is beyond the length of the shorter field, just
 853                  * clamp the position the length of the shorter field. This
 854                  * matches how the scanline counter based position works since
 855                  * the scanline counter doesn't count the two half lines.
 856                  */
 857                 if (position >= vtotal)
 858                         position = vtotal - 1;
 859
 860                 /*
 861                  * Start of vblank interrupt is triggered at start of hsync,
 862                  * just prior to the first active line of vblank. However we
 863                  * consider lines to start at the leading edge of horizontal
 864                  * active. So, should we get here before we've crossed into
 865                  * the horizontal active of the first line in vblank, we would
 866                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 867                  * always add htotal-hsync_start to the current pixel position.
 868                  */
 869                 position = (position + htotal - hsync_start) % vtotal;
 870         }
 871
 872         /* Get optional system timestamp after query. */
 873         if (etime)
 874                 *etime = ktime_get();
 875
 876         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 877
 878         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 879
 880         in_vbl = position >= vbl_start && position < vbl_end;
 881
 882         /*
 883          * While in vblank, position will be negative
 884          * counting up towards 0 at vbl_end. And outside
 885          * vblank, position will be positive counting
 886          * up since vbl_end.
 887          */
 888         if (position >= vbl_start)
 889                 position -= vbl_end;
 890         else
 891                 position += vtotal - vbl_end;
 892
 893         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 894                 *vpos = position;
 895                 *hpos = 0;
 896         } else {
 897                 *vpos = position / htotal;
 898                 *hpos = position - (*vpos * htotal);
 899         }
 900
 901         /* In vblank? */
 902         if (in_vbl)
 903                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 904
 905         return ret;
 906 }
 907
 908 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 909 {
 910         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 911         unsigned long irqflags;
 912         int position;
 913
 914         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 915         position = __intel_get_crtc_scanline(crtc);
 916         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 917
 918         return position;
 919 }
 920
 921 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 922                               int *max_error,
 923                               struct timeval *vblank_time,
 924                               unsigned flags)
 925 {
 926         struct drm_crtc *crtc;
 927
 928         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 929                 DRM_ERROR("Invalid crtc %u\n", pipe);
 930                 return -EINVAL;
 931         }
 932
 933         /* Get drm_crtc to timestamp: */
 934         crtc = intel_get_crtc_for_pipe(dev, pipe);
 935         if (crtc == NULL) {
 936                 DRM_ERROR("Invalid crtc %u\n", pipe);
 937                 return -EINVAL;
 938         }
 939
 940         if (!crtc->hwmode.crtc_clock) {
 941                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 942                 return -EBUSY;
 943         }
 944
 945         /* Helper routine in DRM core does all the work: */
 946         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 947                                                      vblank_time, flags,
 948                                                      &crtc->hwmode);
 949 }
 950
 951 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 952 {
 953         u32 busy_up, busy_down, max_avg, min_avg;
 954         u8 new_delay;
 955
 956         spin_lock(&mchdev_lock);
 957
 958         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 959
 960         new_delay = dev_priv->ips.cur_delay;
 961
 962         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 963         busy_up = I915_READ(RCPREVBSYTUPAVG);
 964         busy_down = I915_READ(RCPREVBSYTDNAVG);
 965         max_avg = I915_READ(RCBMAXAVG);
 966         min_avg = I915_READ(RCBMINAVG);
 967
 968         /* Handle RCS change request from hw */
 969         if (busy_up > max_avg) {
 970                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 971                         new_delay = dev_priv->ips.cur_delay - 1;
 972                 if (new_delay < dev_priv->ips.max_delay)
 973                         new_delay = dev_priv->ips.max_delay;
 974         } else if (busy_down < min_avg) {
 975                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 976                         new_delay = dev_priv->ips.cur_delay + 1;
 977                 if (new_delay > dev_priv->ips.min_delay)
 978                         new_delay = dev_priv->ips.min_delay;
 979         }
 980
 981         if (ironlake_set_drps(dev_priv, new_delay))
 982                 dev_priv->ips.cur_delay = new_delay;
 983
 984         spin_unlock(&mchdev_lock);
 985
 986         return;
 987 }
 988
 989 static void notify_ring(struct intel_engine_cs *engine)
 990 {
 991         if (!intel_engine_initialized(engine))
 992                 return;
 993
 994         trace_i915_gem_request_notify(engine);
 995         engine->user_interrupts++;
 996
 997         wake_up_all(&engine->irq_queue);
 998 }
 999
1000 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1001                         struct intel_rps_ei *ei)
1002 {
1003         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1004         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1005         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1006 }
1007
1008 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1009                          const struct intel_rps_ei *old,
1010                          const struct intel_rps_ei *now,
1011                          int threshold)
1012 {
1013         u64 time, c0;
1014         unsigned int mul = 100;
1015
1016         if (old->cz_clock == 0)
1017                 return false;
1018
1019         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1020                 mul <<= 8;
1021
1022         time = now->cz_clock - old->cz_clock;
1023         time *= threshold * dev_priv->czclk_freq;
1024
1025         /* Workload can be split between render + media, e.g. SwapBuffers
1026          * being blitted in X after being rendered in mesa. To account for
1027          * this we need to combine both engines into our activity counter.
1028          */
1029         c0 = now->render_c0 - old->render_c0;
1030         c0 += now->media_c0 - old->media_c0;
1031         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1032
1033         return c0 >= time;
1034 }
1035
1036 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1037 {
1038         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1039         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1040 }
1041
1042 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1043 {
1044         struct intel_rps_ei now;
1045         u32 events = 0;
1046
1047         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1048                 return 0;
1049
1050         vlv_c0_read(dev_priv, &now);
1051         if (now.cz_clock == 0)
1052                 return 0;
1053
1054         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1055                 if (!vlv_c0_above(dev_priv,
1056                                   &dev_priv->rps.down_ei, &now,
1057                                   dev_priv->rps.down_threshold))
1058                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1059                 dev_priv->rps.down_ei = now;
1060         }
1061
1062         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1063                 if (vlv_c0_above(dev_priv,
1064                                  &dev_priv->rps.up_ei, &now,
1065                                  dev_priv->rps.up_threshold))
1066                         events |= GEN6_PM_RP_UP_THRESHOLD;
1067                 dev_priv->rps.up_ei = now;
1068         }
1069
1070         return events;
1071 }
1072
1073 static bool any_waiters(struct drm_i915_private *dev_priv)
1074 {
1075         struct intel_engine_cs *engine;
1076
1077         for_each_engine(engine, dev_priv)
1078                 if (engine->irq_refcount)
1079                         return true;
1080
1081         return false;
1082 }
1083
1084 static void gen6_pm_rps_work(struct work_struct *work)
1085 {
1086         struct drm_i915_private *dev_priv =
1087                 container_of(work, struct drm_i915_private, rps.work);
1088         bool client_boost;
1089         int new_delay, adj, min, max;
1090         u32 pm_iir;
1091
1092         spin_lock_irq(&dev_priv->irq_lock);
1093         /* Speed up work cancelation during disabling rps interrupts. */
1094         if (!dev_priv->rps.interrupts_enabled) {
1095                 spin_unlock_irq(&dev_priv->irq_lock);
1096                 return;
1097         }
1098
1099         /*
1100          * The RPS work is synced during runtime suspend, we don't require a
1101          * wakeref. TODO: instead of disabling the asserts make sure that we
1102          * always hold an RPM reference while the work is running.
1103          */
1104         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1105
1106         pm_iir = dev_priv->rps.pm_iir;
1107         dev_priv->rps.pm_iir = 0;
1108         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1109         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1110         client_boost = dev_priv->rps.client_boost;
1111         dev_priv->rps.client_boost = false;
1112         spin_unlock_irq(&dev_priv->irq_lock);
1113
1114         /* Make sure we didn't queue anything we're not going to process. */
1115         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1116
1117         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1118                 goto out;
1119
1120         mutex_lock(&dev_priv->rps.hw_lock);
1121
1122         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1123
1124         adj = dev_priv->rps.last_adj;
1125         new_delay = dev_priv->rps.cur_freq;
1126         min = dev_priv->rps.min_freq_softlimit;
1127         max = dev_priv->rps.max_freq_softlimit;
1128
1129         if (client_boost) {
1130                 new_delay = dev_priv->rps.max_freq_softlimit;
1131                 adj = 0;
1132         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1133                 if (adj > 0)
1134                         adj *= 2;
1135                 else /* CHV needs even encode values */
1136                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1137                 /*
1138                  * For better performance, jump directly
1139                  * to RPe if we're below it.
1140                  */
1141                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1142                         new_delay = dev_priv->rps.efficient_freq;
1143                         adj = 0;
1144                 }
1145         } else if (any_waiters(dev_priv)) {
1146                 adj = 0;
1147         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1148                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1149                         new_delay = dev_priv->rps.efficient_freq;
1150                 else
1151                         new_delay = dev_priv->rps.min_freq_softlimit;
1152                 adj = 0;
1153         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1154                 if (adj < 0)
1155                         adj *= 2;
1156                 else /* CHV needs even encode values */
1157                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1158         } else { /* unknown event */
1159                 adj = 0;
1160         }
1161
1162         dev_priv->rps.last_adj = adj;
1163
1164         /* sysfs frequency interfaces may have snuck in while servicing the
1165          * interrupt
1166          */
1167         new_delay += adj;
1168         new_delay = clamp_t(int, new_delay, min, max);
1169
1170         intel_set_rps(dev_priv, new_delay);
1171
1172         mutex_unlock(&dev_priv->rps.hw_lock);
1173 out:
1174         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1175 }
1176
1177
1178 /**
1179  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1180  * occurred.
1181  * @work: workqueue struct
1182  *
1183  * Doesn't actually do anything except notify userspace. As a consequence of
1184  * this event, userspace should try to remap the bad rows since statistically
1185  * it is likely the same row is more likely to go bad again.
1186  */
1187 static void ivybridge_parity_work(struct work_struct *work)
1188 {
1189         struct drm_i915_private *dev_priv =
1190                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1191         u32 error_status, row, bank, subbank;
1192         char *parity_event[6];
1193         uint32_t misccpctl;
1194         uint8_t slice = 0;
1195
1196         /* We must turn off DOP level clock gating to access the L3 registers.
1197          * In order to prevent a get/put style interface, acquire struct mutex
1198          * any time we access those registers.
1199          */
1200         mutex_lock(&dev_priv->dev->struct_mutex);
1201
1202         /* If we've screwed up tracking, just let the interrupt fire again */
1203         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1204                 goto out;
1205
1206         misccpctl = I915_READ(GEN7_MISCCPCTL);
1207         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1208         POSTING_READ(GEN7_MISCCPCTL);
1209
1210         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1211                 i915_reg_t reg;
1212
1213                 slice--;
1214                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1215                         break;
1216
1217                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1218
1219                 reg = GEN7_L3CDERRST1(slice);
1220
1221                 error_status = I915_READ(reg);
1222                 row = GEN7_PARITY_ERROR_ROW(error_status);
1223                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1224                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1225
1226                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1227                 POSTING_READ(reg);
1228
1229                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1230                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1231                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1232                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1233                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1234                 parity_event[5] = NULL;
1235
1236                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1237                                    KOBJ_CHANGE, parity_event);
1238
1239                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1240                           slice, row, bank, subbank);
1241
1242                 kfree(parity_event[4]);
1243                 kfree(parity_event[3]);
1244                 kfree(parity_event[2]);
1245                 kfree(parity_event[1]);
1246         }
1247
1248         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1249
1250 out:
1251         WARN_ON(dev_priv->l3_parity.which_slice);
1252         spin_lock_irq(&dev_priv->irq_lock);
1253         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1254         spin_unlock_irq(&dev_priv->irq_lock);
1255
1256         mutex_unlock(&dev_priv->dev->struct_mutex);
1257 }
1258
1259 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1260                                                u32 iir)
1261 {
1262         if (!HAS_L3_DPF(dev_priv))
1263                 return;
1264
1265         spin_lock(&dev_priv->irq_lock);
1266         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1267         spin_unlock(&dev_priv->irq_lock);
1268
1269         iir &= GT_PARITY_ERROR(dev_priv);
1270         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1271                 dev_priv->l3_parity.which_slice |= 1 << 1;
1272
1273         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1274                 dev_priv->l3_parity.which_slice |= 1 << 0;
1275
1276         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1277 }
1278
1279 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1280                                u32 gt_iir)
1281 {
1282         if (gt_iir &
1283             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1284                 notify_ring(&dev_priv->engine[RCS]);
1285         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1286                 notify_ring(&dev_priv->engine[VCS]);
1287 }
1288
1289 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1290                                u32 gt_iir)
1291 {
1292
1293         if (gt_iir &
1294             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1295                 notify_ring(&dev_priv->engine[RCS]);
1296         if (gt_iir & GT_BSD_USER_INTERRUPT)
1297                 notify_ring(&dev_priv->engine[VCS]);
1298         if (gt_iir & GT_BLT_USER_INTERRUPT)
1299                 notify_ring(&dev_priv->engine[BCS]);
1300
1301         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1302                       GT_BSD_CS_ERROR_INTERRUPT |
1303                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1304                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1305
1306         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1307                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1308 }
1309
1310 static __always_inline void
1311 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1312 {
1313         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1314                 notify_ring(engine);
1315         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1316                 tasklet_schedule(&engine->irq_tasklet);
1317 }
1318
1319 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1320                                    u32 master_ctl,
1321                                    u32 gt_iir[4])
1322 {
1323         irqreturn_t ret = IRQ_NONE;
1324
1325         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1326                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1327                 if (gt_iir[0]) {
1328                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1329                         ret = IRQ_HANDLED;
1330                 } else
1331                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1332         }
1333
1334         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1335                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1336                 if (gt_iir[1]) {
1337                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1338                         ret = IRQ_HANDLED;
1339                 } else
1340                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1341         }
1342
1343         if (master_ctl & GEN8_GT_VECS_IRQ) {
1344                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1345                 if (gt_iir[3]) {
1346                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1347                         ret = IRQ_HANDLED;
1348                 } else
1349                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1350         }
1351
1352         if (master_ctl & GEN8_GT_PM_IRQ) {
1353                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1354                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1355                         I915_WRITE_FW(GEN8_GT_IIR(2),
1356                                       gt_iir[2] & dev_priv->pm_rps_events);
1357                         ret = IRQ_HANDLED;
1358                 } else
1359                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1360         }
1361
1362         return ret;
1363 }
1364
1365 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1366                                 u32 gt_iir[4])
1367 {
1368         if (gt_iir[0]) {
1369                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1370                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1371                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1372                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1373         }
1374
1375         if (gt_iir[1]) {
1376                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1377                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1378                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1379                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1380         }
1381
1382         if (gt_iir[3])
1383                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1384                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1385
1386         if (gt_iir[2] & dev_priv->pm_rps_events)
1387                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1388 }
1389
1390 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1391 {
1392         switch (port) {
1393         case PORT_A:
1394                 return val & PORTA_HOTPLUG_LONG_DETECT;
1395         case PORT_B:
1396                 return val & PORTB_HOTPLUG_LONG_DETECT;
1397         case PORT_C:
1398                 return val & PORTC_HOTPLUG_LONG_DETECT;
1399         default:
1400                 return false;
1401         }
1402 }
1403
1404 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1405 {
1406         switch (port) {
1407         case PORT_E:
1408                 return val & PORTE_HOTPLUG_LONG_DETECT;
1409         default:
1410                 return false;
1411         }
1412 }
1413
1414 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1415 {
1416         switch (port) {
1417         case PORT_A:
1418                 return val & PORTA_HOTPLUG_LONG_DETECT;
1419         case PORT_B:
1420                 return val & PORTB_HOTPLUG_LONG_DETECT;
1421         case PORT_C:
1422                 return val & PORTC_HOTPLUG_LONG_DETECT;
1423         case PORT_D:
1424                 return val & PORTD_HOTPLUG_LONG_DETECT;
1425         default:
1426                 return false;
1427         }
1428 }
1429
1430 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1431 {
1432         switch (port) {
1433         case PORT_A:
1434                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1435         default:
1436                 return false;
1437         }
1438 }
1439
1440 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1441 {
1442         switch (port) {
1443         case PORT_B:
1444                 return val & PORTB_HOTPLUG_LONG_DETECT;
1445         case PORT_C:
1446                 return val & PORTC_HOTPLUG_LONG_DETECT;
1447         case PORT_D:
1448                 return val & PORTD_HOTPLUG_LONG_DETECT;
1449         default:
1450                 return false;
1451         }
1452 }
1453
1454 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1455 {
1456         switch (port) {
1457         case PORT_B:
1458                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1459         case PORT_C:
1460                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1461         case PORT_D:
1462                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1463         default:
1464                 return false;
1465         }
1466 }
1467
1468 /*
1469  * Get a bit mask of pins that have triggered, and which ones may be long.
1470  * This can be called multiple times with the same masks to accumulate
1471  * hotplug detection results from several registers.
1472  *
1473  * Note that the caller is expected to zero out the masks initially.
1474  */
1475 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1476                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1477                              const u32 hpd[HPD_NUM_PINS],
1478                              bool long_pulse_detect(enum port port, u32 val))
1479 {
1480         enum port port;
1481         int i;
1482
1483         for_each_hpd_pin(i) {
1484                 if ((hpd[i] & hotplug_trigger) == 0)
1485                         continue;
1486
1487                 *pin_mask |= BIT(i);
1488
1489                 if (!intel_hpd_pin_to_port(i, &port))
1490                         continue;
1491
1492                 if (long_pulse_detect(port, dig_hotplug_reg))
1493                         *long_mask |= BIT(i);
1494         }
1495
1496         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1497                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1498
1499 }
1500
1501 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1502 {
1503         wake_up_all(&dev_priv->gmbus_wait_queue);
1504 }
1505
1506 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1507 {
1508         wake_up_all(&dev_priv->gmbus_wait_queue);
1509 }
1510
1511 #if defined(CONFIG_DEBUG_FS)
1512 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1513                                          enum pipe pipe,
1514                                          uint32_t crc0, uint32_t crc1,
1515                                          uint32_t crc2, uint32_t crc3,
1516                                          uint32_t crc4)
1517 {
1518         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1519         struct intel_pipe_crc_entry *entry;
1520         int head, tail;
1521
1522         spin_lock(&pipe_crc->lock);
1523
1524         if (!pipe_crc->entries) {
1525                 spin_unlock(&pipe_crc->lock);
1526                 DRM_DEBUG_KMS("spurious interrupt\n");
1527                 return;
1528         }
1529
1530         head = pipe_crc->head;
1531         tail = pipe_crc->tail;
1532
1533         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1534                 spin_unlock(&pipe_crc->lock);
1535                 DRM_ERROR("CRC buffer overflowing\n");
1536                 return;
1537         }
1538
1539         entry = &pipe_crc->entries[head];
1540
1541         entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1542                                                                  pipe);
1543         entry->crc[0] = crc0;
1544         entry->crc[1] = crc1;
1545         entry->crc[2] = crc2;
1546         entry->crc[3] = crc3;
1547         entry->crc[4] = crc4;
1548
1549         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1550         pipe_crc->head = head;
1551
1552         spin_unlock(&pipe_crc->lock);
1553
1554         wake_up_interruptible(&pipe_crc->wq);
1555 }
1556 #else
1557 static inline void
1558 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1559                              enum pipe pipe,
1560                              uint32_t crc0, uint32_t crc1,
1561                              uint32_t crc2, uint32_t crc3,
1562                              uint32_t crc4) {}
1563 #endif
1564
1565
1566 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1567                                      enum pipe pipe)
1568 {
1569         display_pipe_crc_irq_handler(dev_priv, pipe,
1570                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1571                                      0, 0, 0, 0);
1572 }
1573
1574 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1575                                      enum pipe pipe)
1576 {
1577         display_pipe_crc_irq_handler(dev_priv, pipe,
1578                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1579                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1580                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1581                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1582                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1583 }
1584
1585 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1586                                       enum pipe pipe)
1587 {
1588         uint32_t res1, res2;
1589
1590         if (INTEL_GEN(dev_priv) >= 3)
1591                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1592         else
1593                 res1 = 0;
1594
1595         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1596                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1597         else
1598                 res2 = 0;
1599
1600         display_pipe_crc_irq_handler(dev_priv, pipe,
1601                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1602                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1603                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1604                                      res1, res2);
1605 }
1606
1607 /* The RPS events need forcewake, so we add them to a work queue and mask their
1608  * IMR bits until the work is done. Other interrupts can be processed without
1609  * the work queue. */
1610 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1611 {
1612         if (pm_iir & dev_priv->pm_rps_events) {
1613                 spin_lock(&dev_priv->irq_lock);
1614                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1615                 if (dev_priv->rps.interrupts_enabled) {
1616                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1617                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1618                 }
1619                 spin_unlock(&dev_priv->irq_lock);
1620         }
1621
1622         if (INTEL_INFO(dev_priv)->gen >= 8)
1623                 return;
1624
1625         if (HAS_VEBOX(dev_priv)) {
1626                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1627                         notify_ring(&dev_priv->engine[VECS]);
1628
1629                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1630                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1631         }
1632 }
1633
1634 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1635                                      enum pipe pipe)
1636 {
1637         return drm_handle_vblank(dev_priv->dev, pipe);
1638 }
1639
1640 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1641                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1642 {
1643         int pipe;
1644
1645         spin_lock(&dev_priv->irq_lock);
1646
1647         if (!dev_priv->display_irqs_enabled) {
1648                 spin_unlock(&dev_priv->irq_lock);
1649                 return;
1650         }
1651
1652         for_each_pipe(dev_priv, pipe) {
1653                 i915_reg_t reg;
1654                 u32 mask, iir_bit = 0;
1655
1656                 /*
1657                  * PIPESTAT bits get signalled even when the interrupt is
1658                  * disabled with the mask bits, and some of the status bits do
1659                  * not generate interrupts at all (like the underrun bit). Hence
1660                  * we need to be careful that we only handle what we want to
1661                  * handle.
1662                  */
1663
1664                 /* fifo underruns are filterered in the underrun handler. */
1665                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1666
1667                 switch (pipe) {
1668                 case PIPE_A:
1669                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1670                         break;
1671                 case PIPE_B:
1672                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1673                         break;
1674                 case PIPE_C:
1675                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1676                         break;
1677                 }
1678                 if (iir & iir_bit)
1679                         mask |= dev_priv->pipestat_irq_mask[pipe];
1680
1681                 if (!mask)
1682                         continue;
1683
1684                 reg = PIPESTAT(pipe);
1685                 mask |= PIPESTAT_INT_ENABLE_MASK;
1686                 pipe_stats[pipe] = I915_READ(reg) & mask;
1687
1688                 /*
1689                  * Clear the PIPE*STAT regs before the IIR
1690                  */
1691                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1692                                         PIPESTAT_INT_STATUS_MASK))
1693                         I915_WRITE(reg, pipe_stats[pipe]);
1694         }
1695         spin_unlock(&dev_priv->irq_lock);
1696 }
1697
1698 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1699                                             u32 pipe_stats[I915_MAX_PIPES])
1700 {
1701         enum pipe pipe;
1702
1703         for_each_pipe(dev_priv, pipe) {
1704                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1705                     intel_pipe_handle_vblank(dev_priv, pipe))
1706                         intel_check_page_flip(dev_priv, pipe);
1707
1708                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1709                         intel_finish_page_flip(dev_priv, pipe);
1710
1711                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1712                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1713
1714                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1715                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1716         }
1717
1718         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1719                 gmbus_irq_handler(dev_priv);
1720 }
1721
1722 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1723 {
1724         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1725
1726         if (hotplug_status)
1727                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1728
1729         return hotplug_status;
1730 }
1731
1732 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1733                                  u32 hotplug_status)
1734 {
1735         u32 pin_mask = 0, long_mask = 0;
1736
1737         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1738             IS_CHERRYVIEW(dev_priv)) {
1739                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1740
1741                 if (hotplug_trigger) {
1742                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1743                                            hotplug_trigger, hpd_status_g4x,
1744                                            i9xx_port_hotplug_long_detect);
1745
1746                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1747                 }
1748
1749                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1750                         dp_aux_irq_handler(dev_priv);
1751         } else {
1752                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1753
1754                 if (hotplug_trigger) {
1755                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1756                                            hotplug_trigger, hpd_status_i915,
1757                                            i9xx_port_hotplug_long_detect);
1758                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1759                 }
1760         }
1761 }
1762
1763 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1764 {
1765         struct drm_device *dev = arg;
1766         struct drm_i915_private *dev_priv = dev->dev_private;
1767         irqreturn_t ret = IRQ_NONE;
1768
1769         if (!intel_irqs_enabled(dev_priv))
1770                 return IRQ_NONE;
1771
1772         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1773         disable_rpm_wakeref_asserts(dev_priv);
1774
1775         do {
1776                 u32 iir, gt_iir, pm_iir;
1777                 u32 pipe_stats[I915_MAX_PIPES] = {};
1778                 u32 hotplug_status = 0;
1779                 u32 ier = 0;
1780
1781                 gt_iir = I915_READ(GTIIR);
1782                 pm_iir = I915_READ(GEN6_PMIIR);
1783                 iir = I915_READ(VLV_IIR);
1784
1785                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1786                         break;
1787
1788                 ret = IRQ_HANDLED;
1789
1790                 /*
1791                  * Theory on interrupt generation, based on empirical evidence:
1792                  *
1793                  * x = ((VLV_IIR & VLV_IER) ||
1794                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1795                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1796                  *
1797                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1798                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1799                  * guarantee the CPU interrupt will be raised again even if we
1800                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1801                  * bits this time around.
1802                  */
1803                 I915_WRITE(VLV_MASTER_IER, 0);
1804                 ier = I915_READ(VLV_IER);
1805                 I915_WRITE(VLV_IER, 0);
1806
1807                 if (gt_iir)
1808                         I915_WRITE(GTIIR, gt_iir);
1809                 if (pm_iir)
1810                         I915_WRITE(GEN6_PMIIR, pm_iir);
1811
1812                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1813                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1814
1815                 /* Call regardless, as some status bits might not be
1816                  * signalled in iir */
1817                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1818
1819                 /*
1820                  * VLV_IIR is single buffered, and reflects the level
1821                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1822                  */
1823                 if (iir)
1824                         I915_WRITE(VLV_IIR, iir);
1825
1826                 I915_WRITE(VLV_IER, ier);
1827                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1828                 POSTING_READ(VLV_MASTER_IER);
1829
1830                 if (gt_iir)
1831                         snb_gt_irq_handler(dev_priv, gt_iir);
1832                 if (pm_iir)
1833                         gen6_rps_irq_handler(dev_priv, pm_iir);
1834
1835                 if (hotplug_status)
1836                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1837
1838                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1839         } while (0);
1840
1841         enable_rpm_wakeref_asserts(dev_priv);
1842
1843         return ret;
1844 }
1845
1846 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1847 {
1848         struct drm_device *dev = arg;
1849         struct drm_i915_private *dev_priv = dev->dev_private;
1850         irqreturn_t ret = IRQ_NONE;
1851
1852         if (!intel_irqs_enabled(dev_priv))
1853                 return IRQ_NONE;
1854
1855         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1856         disable_rpm_wakeref_asserts(dev_priv);
1857
1858         do {
1859                 u32 master_ctl, iir;
1860                 u32 gt_iir[4] = {};
1861                 u32 pipe_stats[I915_MAX_PIPES] = {};
1862                 u32 hotplug_status = 0;
1863                 u32 ier = 0;
1864
1865                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1866                 iir = I915_READ(VLV_IIR);
1867
1868                 if (master_ctl == 0 && iir == 0)
1869                         break;
1870
1871                 ret = IRQ_HANDLED;
1872
1873                 /*
1874                  * Theory on interrupt generation, based on empirical evidence:
1875                  *
1876                  * x = ((VLV_IIR & VLV_IER) ||
1877                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1878                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1879                  *
1880                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1881                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1882                  * guarantee the CPU interrupt will be raised again even if we
1883                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1884                  * bits this time around.
1885                  */
1886                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1887                 ier = I915_READ(VLV_IER);
1888                 I915_WRITE(VLV_IER, 0);
1889
1890                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1891
1892                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1893                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1894
1895                 /* Call regardless, as some status bits might not be
1896                  * signalled in iir */
1897                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1898
1899                 /*
1900                  * VLV_IIR is single buffered, and reflects the level
1901                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1902                  */
1903                 if (iir)
1904                         I915_WRITE(VLV_IIR, iir);
1905
1906                 I915_WRITE(VLV_IER, ier);
1907                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1908                 POSTING_READ(GEN8_MASTER_IRQ);
1909
1910                 gen8_gt_irq_handler(dev_priv, gt_iir);
1911
1912                 if (hotplug_status)
1913                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1914
1915                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1916         } while (0);
1917
1918         enable_rpm_wakeref_asserts(dev_priv);
1919
1920         return ret;
1921 }
1922
1923 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1924                                 u32 hotplug_trigger,
1925                                 const u32 hpd[HPD_NUM_PINS])
1926 {
1927         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1928
1929         /*
1930          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1931          * unless we touch the hotplug register, even if hotplug_trigger is
1932          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1933          * errors.
1934          */
1935         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1936         if (!hotplug_trigger) {
1937                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1938                         PORTD_HOTPLUG_STATUS_MASK |
1939                         PORTC_HOTPLUG_STATUS_MASK |
1940                         PORTB_HOTPLUG_STATUS_MASK;
1941                 dig_hotplug_reg &= ~mask;
1942         }
1943
1944         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1945         if (!hotplug_trigger)
1946                 return;
1947
1948         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1949                            dig_hotplug_reg, hpd,
1950                            pch_port_hotplug_long_detect);
1951
1952         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1953 }
1954
1955 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1956 {
1957         int pipe;
1958         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1959
1960         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1961
1962         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1963                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1964                                SDE_AUDIO_POWER_SHIFT);
1965                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1966                                  port_name(port));
1967         }
1968
1969         if (pch_iir & SDE_AUX_MASK)
1970                 dp_aux_irq_handler(dev_priv);
1971
1972         if (pch_iir & SDE_GMBUS)
1973                 gmbus_irq_handler(dev_priv);
1974
1975         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1976                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1977
1978         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1979                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1980
1981         if (pch_iir & SDE_POISON)
1982                 DRM_ERROR("PCH poison interrupt\n");
1983
1984         if (pch_iir & SDE_FDI_MASK)
1985                 for_each_pipe(dev_priv, pipe)
1986                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1987                                          pipe_name(pipe),
1988                                          I915_READ(FDI_RX_IIR(pipe)));
1989
1990         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1991                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1992
1993         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1994                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1995
1996         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1997                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1998
1999         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2000                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2001 }
2002
2003 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2004 {
2005         u32 err_int = I915_READ(GEN7_ERR_INT);
2006         enum pipe pipe;
2007
2008         if (err_int & ERR_INT_POISON)
2009                 DRM_ERROR("Poison interrupt\n");
2010
2011         for_each_pipe(dev_priv, pipe) {
2012                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2013                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2014
2015                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2016                         if (IS_IVYBRIDGE(dev_priv))
2017                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2018                         else
2019                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2020                 }
2021         }
2022
2023         I915_WRITE(GEN7_ERR_INT, err_int);
2024 }
2025
2026 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2027 {
2028         u32 serr_int = I915_READ(SERR_INT);
2029
2030         if (serr_int & SERR_INT_POISON)
2031                 DRM_ERROR("PCH poison interrupt\n");
2032
2033         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2034                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2035
2036         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2037                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2038
2039         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2040                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2041
2042         I915_WRITE(SERR_INT, serr_int);
2043 }
2044
2045 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2046 {
2047         int pipe;
2048         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2049
2050         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2051
2052         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2053                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2054                                SDE_AUDIO_POWER_SHIFT_CPT);
2055                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2056                                  port_name(port));
2057         }
2058
2059         if (pch_iir & SDE_AUX_MASK_CPT)
2060                 dp_aux_irq_handler(dev_priv);
2061
2062         if (pch_iir & SDE_GMBUS_CPT)
2063                 gmbus_irq_handler(dev_priv);
2064
2065         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2066                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2067
2068         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2069                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2070
2071         if (pch_iir & SDE_FDI_MASK_CPT)
2072                 for_each_pipe(dev_priv, pipe)
2073                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2074                                          pipe_name(pipe),
2075                                          I915_READ(FDI_RX_IIR(pipe)));
2076
2077         if (pch_iir & SDE_ERROR_CPT)
2078                 cpt_serr_int_handler(dev_priv);
2079 }
2080
2081 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2082 {
2083         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2084                 ~SDE_PORTE_HOTPLUG_SPT;
2085         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2086         u32 pin_mask = 0, long_mask = 0;
2087
2088         if (hotplug_trigger) {
2089                 u32 dig_hotplug_reg;
2090
2091                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2092                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2093
2094                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2095                                    dig_hotplug_reg, hpd_spt,
2096                                    spt_port_hotplug_long_detect);
2097         }
2098
2099         if (hotplug2_trigger) {
2100                 u32 dig_hotplug_reg;
2101
2102                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2103                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2104
2105                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2106                                    dig_hotplug_reg, hpd_spt,
2107                                    spt_port_hotplug2_long_detect);
2108         }
2109
2110         if (pin_mask)
2111                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2112
2113         if (pch_iir & SDE_GMBUS_CPT)
2114                 gmbus_irq_handler(dev_priv);
2115 }
2116
2117 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2118                                 u32 hotplug_trigger,
2119                                 const u32 hpd[HPD_NUM_PINS])
2120 {
2121         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2122
2123         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2124         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2125
2126         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2127                            dig_hotplug_reg, hpd,
2128                            ilk_port_hotplug_long_detect);
2129
2130         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2131 }
2132
2133 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2134                                     u32 de_iir)
2135 {
2136         enum pipe pipe;
2137         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2138
2139         if (hotplug_trigger)
2140                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2141
2142         if (de_iir & DE_AUX_CHANNEL_A)
2143                 dp_aux_irq_handler(dev_priv);
2144
2145         if (de_iir & DE_GSE)
2146                 intel_opregion_asle_intr(dev_priv);
2147
2148         if (de_iir & DE_POISON)
2149                 DRM_ERROR("Poison interrupt\n");
2150
2151         for_each_pipe(dev_priv, pipe) {
2152                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2153                     intel_pipe_handle_vblank(dev_priv, pipe))
2154                         intel_check_page_flip(dev_priv, pipe);
2155
2156                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2157                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2158
2159                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2160                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2161
2162                 /* plane/pipes map 1:1 on ilk+ */
2163                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2164                         intel_finish_page_flip(dev_priv, pipe);
2165         }
2166
2167         /* check event from PCH */
2168         if (de_iir & DE_PCH_EVENT) {
2169                 u32 pch_iir = I915_READ(SDEIIR);
2170
2171                 if (HAS_PCH_CPT(dev_priv))
2172                         cpt_irq_handler(dev_priv, pch_iir);
2173                 else
2174                         ibx_irq_handler(dev_priv, pch_iir);
2175
2176                 /* should clear PCH hotplug event before clear CPU irq */
2177                 I915_WRITE(SDEIIR, pch_iir);
2178         }
2179
2180         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2181                 ironlake_rps_change_irq_handler(dev_priv);
2182 }
2183
2184 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2185                                     u32 de_iir)
2186 {
2187         enum pipe pipe;
2188         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2189
2190         if (hotplug_trigger)
2191                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2192
2193         if (de_iir & DE_ERR_INT_IVB)
2194                 ivb_err_int_handler(dev_priv);
2195
2196         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2197                 dp_aux_irq_handler(dev_priv);
2198
2199         if (de_iir & DE_GSE_IVB)
2200                 intel_opregion_asle_intr(dev_priv);
2201
2202         for_each_pipe(dev_priv, pipe) {
2203                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2204                     intel_pipe_handle_vblank(dev_priv, pipe))
2205                         intel_check_page_flip(dev_priv, pipe);
2206
2207                 /* plane/pipes map 1:1 on ilk+ */
2208                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2209                         intel_finish_page_flip(dev_priv, pipe);
2210         }
2211
2212         /* check event from PCH */
2213         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2214                 u32 pch_iir = I915_READ(SDEIIR);
2215
2216                 cpt_irq_handler(dev_priv, pch_iir);
2217
2218                 /* clear PCH hotplug event before clear CPU irq */
2219                 I915_WRITE(SDEIIR, pch_iir);
2220         }
2221 }
2222
2223 /*
2224  * To handle irqs with the minimum potential races with fresh interrupts, we:
2225  * 1 - Disable Master Interrupt Control.
2226  * 2 - Find the source(s) of the interrupt.
2227  * 3 - Clear the Interrupt Identity bits (IIR).
2228  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2229  * 5 - Re-enable Master Interrupt Control.
2230  */
2231 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2232 {
2233         struct drm_device *dev = arg;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2236         irqreturn_t ret = IRQ_NONE;
2237
2238         if (!intel_irqs_enabled(dev_priv))
2239                 return IRQ_NONE;
2240
2241         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2242         disable_rpm_wakeref_asserts(dev_priv);
2243
2244         /* disable master interrupt before clearing iir  */
2245         de_ier = I915_READ(DEIER);
2246         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2247         POSTING_READ(DEIER);
2248
2249         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2250          * interrupts will will be stored on its back queue, and then we'll be
2251          * able to process them after we restore SDEIER (as soon as we restore
2252          * it, we'll get an interrupt if SDEIIR still has something to process
2253          * due to its back queue). */
2254         if (!HAS_PCH_NOP(dev_priv)) {
2255                 sde_ier = I915_READ(SDEIER);
2256                 I915_WRITE(SDEIER, 0);
2257                 POSTING_READ(SDEIER);
2258         }
2259
2260         /* Find, clear, then process each source of interrupt */
2261
2262         gt_iir = I915_READ(GTIIR);
2263         if (gt_iir) {
2264                 I915_WRITE(GTIIR, gt_iir);
2265                 ret = IRQ_HANDLED;
2266                 if (INTEL_GEN(dev_priv) >= 6)
2267                         snb_gt_irq_handler(dev_priv, gt_iir);
2268                 else
2269                         ilk_gt_irq_handler(dev_priv, gt_iir);
2270         }
2271
2272         de_iir = I915_READ(DEIIR);
2273         if (de_iir) {
2274                 I915_WRITE(DEIIR, de_iir);
2275                 ret = IRQ_HANDLED;
2276                 if (INTEL_GEN(dev_priv) >= 7)
2277                         ivb_display_irq_handler(dev_priv, de_iir);
2278                 else
2279                         ilk_display_irq_handler(dev_priv, de_iir);
2280         }
2281
2282         if (INTEL_GEN(dev_priv) >= 6) {
2283                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2284                 if (pm_iir) {
2285                         I915_WRITE(GEN6_PMIIR, pm_iir);
2286                         ret = IRQ_HANDLED;
2287                         gen6_rps_irq_handler(dev_priv, pm_iir);
2288                 }
2289         }
2290
2291         I915_WRITE(DEIER, de_ier);
2292         POSTING_READ(DEIER);
2293         if (!HAS_PCH_NOP(dev_priv)) {
2294                 I915_WRITE(SDEIER, sde_ier);
2295                 POSTING_READ(SDEIER);
2296         }
2297
2298         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2299         enable_rpm_wakeref_asserts(dev_priv);
2300
2301         return ret;
2302 }
2303
2304 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2305                                 u32 hotplug_trigger,
2306                                 const u32 hpd[HPD_NUM_PINS])
2307 {
2308         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2309
2310         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2311         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2312
2313         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2314                            dig_hotplug_reg, hpd,
2315                            bxt_port_hotplug_long_detect);
2316
2317         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2318 }
2319
2320 static irqreturn_t
2321 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2322 {
2323         irqreturn_t ret = IRQ_NONE;
2324         u32 iir;
2325         enum pipe pipe;
2326
2327         if (master_ctl & GEN8_DE_MISC_IRQ) {
2328                 iir = I915_READ(GEN8_DE_MISC_IIR);
2329                 if (iir) {
2330                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2331                         ret = IRQ_HANDLED;
2332                         if (iir & GEN8_DE_MISC_GSE)
2333                                 intel_opregion_asle_intr(dev_priv);
2334                         else
2335                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2336                 }
2337                 else
2338                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2339         }
2340
2341         if (master_ctl & GEN8_DE_PORT_IRQ) {
2342                 iir = I915_READ(GEN8_DE_PORT_IIR);
2343                 if (iir) {
2344                         u32 tmp_mask;
2345                         bool found = false;
2346
2347                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2348                         ret = IRQ_HANDLED;
2349
2350                         tmp_mask = GEN8_AUX_CHANNEL_A;
2351                         if (INTEL_INFO(dev_priv)->gen >= 9)
2352                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2353                                             GEN9_AUX_CHANNEL_C |
2354                                             GEN9_AUX_CHANNEL_D;
2355
2356                         if (iir & tmp_mask) {
2357                                 dp_aux_irq_handler(dev_priv);
2358                                 found = true;
2359                         }
2360
2361                         if (IS_BROXTON(dev_priv)) {
2362                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2363                                 if (tmp_mask) {
2364                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2365                                                             hpd_bxt);
2366                                         found = true;
2367                                 }
2368                         } else if (IS_BROADWELL(dev_priv)) {
2369                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2370                                 if (tmp_mask) {
2371                                         ilk_hpd_irq_handler(dev_priv,
2372                                                             tmp_mask, hpd_bdw);
2373                                         found = true;
2374                                 }
2375                         }
2376
2377                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2378                                 gmbus_irq_handler(dev_priv);
2379                                 found = true;
2380                         }
2381
2382                         if (!found)
2383                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2384                 }
2385                 else
2386                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2387         }
2388
2389         for_each_pipe(dev_priv, pipe) {
2390                 u32 flip_done, fault_errors;
2391
2392                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2393                         continue;
2394
2395                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2396                 if (!iir) {
2397                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2398                         continue;
2399                 }
2400
2401                 ret = IRQ_HANDLED;
2402                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2403
2404                 if (iir & GEN8_PIPE_VBLANK &&
2405                     intel_pipe_handle_vblank(dev_priv, pipe))
2406                         intel_check_page_flip(dev_priv, pipe);
2407
2408                 flip_done = iir;
2409                 if (INTEL_INFO(dev_priv)->gen >= 9)
2410                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2411                 else
2412                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2413
2414                 if (flip_done)
2415                         intel_finish_page_flip(dev_priv, pipe);
2416
2417                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2418                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2419
2420                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2421                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2422
2423                 fault_errors = iir;
2424                 if (INTEL_INFO(dev_priv)->gen >= 9)
2425                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2426                 else
2427                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2428
2429                 if (fault_errors)
2430                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2431                                   pipe_name(pipe),
2432                                   fault_errors);
2433         }
2434
2435         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2436             master_ctl & GEN8_DE_PCH_IRQ) {
2437                 /*
2438                  * FIXME(BDW): Assume for now that the new interrupt handling
2439                  * scheme also closed the SDE interrupt handling race we've seen
2440                  * on older pch-split platforms. But this needs testing.
2441                  */
2442                 iir = I915_READ(SDEIIR);
2443                 if (iir) {
2444                         I915_WRITE(SDEIIR, iir);
2445                         ret = IRQ_HANDLED;
2446
2447                         if (HAS_PCH_SPT(dev_priv))
2448                                 spt_irq_handler(dev_priv, iir);
2449                         else
2450                                 cpt_irq_handler(dev_priv, iir);
2451                 } else {
2452                         /*
2453                          * Like on previous PCH there seems to be something
2454                          * fishy going on with forwarding PCH interrupts.
2455                          */
2456                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2457                 }
2458         }
2459
2460         return ret;
2461 }
2462
2463 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2464 {
2465         struct drm_device *dev = arg;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         u32 master_ctl;
2468         u32 gt_iir[4] = {};
2469         irqreturn_t ret;
2470
2471         if (!intel_irqs_enabled(dev_priv))
2472                 return IRQ_NONE;
2473
2474         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2475         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2476         if (!master_ctl)
2477                 return IRQ_NONE;
2478
2479         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2480
2481         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2482         disable_rpm_wakeref_asserts(dev_priv);
2483
2484         /* Find, clear, then process each source of interrupt */
2485         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2486         gen8_gt_irq_handler(dev_priv, gt_iir);
2487         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2488
2489         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2490         POSTING_READ_FW(GEN8_MASTER_IRQ);
2491
2492         enable_rpm_wakeref_asserts(dev_priv);
2493
2494         return ret;
2495 }
2496
2497 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2498                                bool reset_completed)
2499 {
2500         struct intel_engine_cs *engine;
2501
2502         /*
2503          * Notify all waiters for GPU completion events that reset state has
2504          * been changed, and that they need to restart their wait after
2505          * checking for potential errors (and bail out to drop locks if there is
2506          * a gpu reset pending so that i915_error_work_func can acquire them).
2507          */
2508
2509         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2510         for_each_engine(engine, dev_priv)
2511                 wake_up_all(&engine->irq_queue);
2512
2513         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2514         wake_up_all(&dev_priv->pending_flip_queue);
2515
2516         /*
2517          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2518          * reset state is cleared.
2519          */
2520         if (reset_completed)
2521                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2522 }
2523
2524 /**
2525  * i915_reset_and_wakeup - do process context error handling work
2526  * @dev: drm device
2527  *
2528  * Fire an error uevent so userspace can see that a hang or error
2529  * was detected.
2530  */
2531 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2532 {
2533         struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2534         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2535         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2536         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2537         int ret;
2538
2539         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2540
2541         /*
2542          * Note that there's only one work item which does gpu resets, so we
2543          * need not worry about concurrent gpu resets potentially incrementing
2544          * error->reset_counter twice. We only need to take care of another
2545          * racing irq/hangcheck declaring the gpu dead for a second time. A
2546          * quick check for that is good enough: schedule_work ensures the
2547          * correct ordering between hang detection and this work item, and since
2548          * the reset in-progress bit is only ever set by code outside of this
2549          * work we don't need to worry about any other races.
2550          */
2551         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2552                 DRM_DEBUG_DRIVER("resetting chip\n");
2553                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2554
2555                 /*
2556                  * In most cases it's guaranteed that we get here with an RPM
2557                  * reference held, for example because there is a pending GPU
2558                  * request that won't finish until the reset is done. This
2559                  * isn't the case at least when we get here by doing a
2560                  * simulated reset via debugs, so get an RPM reference.
2561                  */
2562                 intel_runtime_pm_get(dev_priv);
2563
2564                 intel_prepare_reset(dev_priv);
2565
2566                 /*
2567                  * All state reset _must_ be completed before we update the
2568                  * reset counter, for otherwise waiters might miss the reset
2569                  * pending state and not properly drop locks, resulting in
2570                  * deadlocks with the reset work.
2571                  */
2572                 ret = i915_reset(dev_priv);
2573
2574                 intel_finish_reset(dev_priv);
2575
2576                 intel_runtime_pm_put(dev_priv);
2577
2578                 if (ret == 0)
2579                         kobject_uevent_env(kobj,
2580                                            KOBJ_CHANGE, reset_done_event);
2581
2582                 /*
2583                  * Note: The wake_up also serves as a memory barrier so that
2584                  * waiters see the update value of the reset counter atomic_t.
2585                  */
2586                 i915_error_wake_up(dev_priv, true);
2587         }
2588 }
2589
2590 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2591 {
2592         uint32_t instdone[I915_NUM_INSTDONE_REG];
2593         u32 eir = I915_READ(EIR);
2594         int pipe, i;
2595
2596         if (!eir)
2597                 return;
2598
2599         pr_err("render error detected, EIR: 0x%08x\n", eir);
2600
2601         i915_get_extra_instdone(dev_priv, instdone);
2602
2603         if (IS_G4X(dev_priv)) {
2604                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2605                         u32 ipeir = I915_READ(IPEIR_I965);
2606
2607                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2608                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2609                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2610                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2611                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2612                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2613                         I915_WRITE(IPEIR_I965, ipeir);
2614                         POSTING_READ(IPEIR_I965);
2615                 }
2616                 if (eir & GM45_ERROR_PAGE_TABLE) {
2617                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2618                         pr_err("page table error\n");
2619                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2620                         I915_WRITE(PGTBL_ER, pgtbl_err);
2621                         POSTING_READ(PGTBL_ER);
2622                 }
2623         }
2624
2625         if (!IS_GEN2(dev_priv)) {
2626                 if (eir & I915_ERROR_PAGE_TABLE) {
2627                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2628                         pr_err("page table error\n");
2629                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2630                         I915_WRITE(PGTBL_ER, pgtbl_err);
2631                         POSTING_READ(PGTBL_ER);
2632                 }
2633         }
2634
2635         if (eir & I915_ERROR_MEMORY_REFRESH) {
2636                 pr_err("memory refresh error:\n");
2637                 for_each_pipe(dev_priv, pipe)
2638                         pr_err("pipe %c stat: 0x%08x\n",
2639                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2640                 /* pipestat has already been acked */
2641         }
2642         if (eir & I915_ERROR_INSTRUCTION) {
2643                 pr_err("instruction error\n");
2644                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2645                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2646                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2647                 if (INTEL_GEN(dev_priv) < 4) {
2648                         u32 ipeir = I915_READ(IPEIR);
2649
2650                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2651                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2652                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2653                         I915_WRITE(IPEIR, ipeir);
2654                         POSTING_READ(IPEIR);
2655                 } else {
2656                         u32 ipeir = I915_READ(IPEIR_I965);
2657
2658                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2659                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2660                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2661                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2662                         I915_WRITE(IPEIR_I965, ipeir);
2663                         POSTING_READ(IPEIR_I965);
2664                 }
2665         }
2666
2667         I915_WRITE(EIR, eir);
2668         POSTING_READ(EIR);
2669         eir = I915_READ(EIR);
2670         if (eir) {
2671                 /*
2672                  * some errors might have become stuck,
2673                  * mask them.
2674                  */
2675                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2676                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2677                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2678         }
2679 }
2680
2681 /**
2682  * i915_handle_error - handle a gpu error
2683  * @dev: drm device
2684  * @engine_mask: mask representing engines that are hung
2685  * Do some basic checking of register state at error time and
2686  * dump it to the syslog.  Also call i915_capture_error_state() to make
2687  * sure we get a record and make it available in debugfs.  Fire a uevent
2688  * so userspace knows something bad happened (should trigger collection
2689  * of a ring dump etc.).
2690  */
2691 void i915_handle_error(struct drm_i915_private *dev_priv,
2692                        u32 engine_mask,
2693                        const char *fmt, ...)
2694 {
2695         va_list args;
2696         char error_msg[80];
2697
2698         va_start(args, fmt);
2699         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2700         va_end(args);
2701
2702         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2703         i915_report_and_clear_eir(dev_priv);
2704
2705         if (engine_mask) {
2706                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2707                                 &dev_priv->gpu_error.reset_counter);
2708
2709                 /*
2710                  * Wakeup waiting processes so that the reset function
2711                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2712                  * various locks. By bumping the reset counter first, the woken
2713                  * processes will see a reset in progress and back off,
2714                  * releasing their locks and then wait for the reset completion.
2715                  * We must do this for _all_ gpu waiters that might hold locks
2716                  * that the reset work needs to acquire.
2717                  *
2718                  * Note: The wake_up serves as the required memory barrier to
2719                  * ensure that the waiters see the updated value of the reset
2720                  * counter atomic_t.
2721                  */
2722                 i915_error_wake_up(dev_priv, false);
2723         }
2724
2725         i915_reset_and_wakeup(dev_priv);
2726 }
2727
2728 /* Called from drm generic code, passed 'crtc' which
2729  * we use as a pipe index
2730  */
2731 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2732 {
2733         struct drm_i915_private *dev_priv = dev->dev_private;
2734         unsigned long irqflags;
2735
2736         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2737         if (INTEL_INFO(dev)->gen >= 4)
2738                 i915_enable_pipestat(dev_priv, pipe,
2739                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2740         else
2741                 i915_enable_pipestat(dev_priv, pipe,
2742                                      PIPE_VBLANK_INTERRUPT_STATUS);
2743         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2744
2745         return 0;
2746 }
2747
2748 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2749 {
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751         unsigned long irqflags;
2752         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2753                                                      DE_PIPE_VBLANK(pipe);
2754
2755         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2756         ilk_enable_display_irq(dev_priv, bit);
2757         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2758
2759         return 0;
2760 }
2761
2762 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         unsigned long irqflags;
2766
2767         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2768         i915_enable_pipestat(dev_priv, pipe,
2769                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2770         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2771
2772         return 0;
2773 }
2774
2775 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2776 {
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778         unsigned long irqflags;
2779
2780         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2781         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2782         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2783
2784         return 0;
2785 }
2786
2787 /* Called from drm generic code, passed 'crtc' which
2788  * we use as a pipe index
2789  */
2790 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2791 {
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         unsigned long irqflags;
2794
2795         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2796         i915_disable_pipestat(dev_priv, pipe,
2797                               PIPE_VBLANK_INTERRUPT_STATUS |
2798                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2799         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2800 }
2801
2802 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2803 {
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         unsigned long irqflags;
2806         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2807                                                      DE_PIPE_VBLANK(pipe);
2808
2809         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2810         ilk_disable_display_irq(dev_priv, bit);
2811         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2812 }
2813
2814 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2815 {
2816         struct drm_i915_private *dev_priv = dev->dev_private;
2817         unsigned long irqflags;
2818
2819         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2820         i915_disable_pipestat(dev_priv, pipe,
2821                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2822         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2823 }
2824
2825 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         unsigned long irqflags;
2829
2830         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2831         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2832         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2833 }
2834
2835 static bool
2836 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2837 {
2838         return i915_seqno_passed(seqno,
2839                                  READ_ONCE(engine->last_submitted_seqno));
2840 }
2841
2842 static bool
2843 ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
2844 {
2845         if (INTEL_GEN(dev_priv) >= 8) {
2846                 return (ipehr >> 23) == 0x1c;
2847         } else {
2848                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2849                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2850                                  MI_SEMAPHORE_REGISTER);
2851         }
2852 }
2853
2854 static struct intel_engine_cs *
2855 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2856                                  u64 offset)
2857 {
2858         struct drm_i915_private *dev_priv = engine->i915;
2859         struct intel_engine_cs *signaller;
2860
2861         if (INTEL_GEN(dev_priv) >= 8) {
2862                 for_each_engine(signaller, dev_priv) {
2863                         if (engine == signaller)
2864                                 continue;
2865
2866                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2867                                 return signaller;
2868                 }
2869         } else {
2870                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2871
2872                 for_each_engine(signaller, dev_priv) {
2873                         if(engine == signaller)
2874                                 continue;
2875
2876                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2877                                 return signaller;
2878                 }
2879         }
2880
2881         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2882                   engine->id, ipehr, offset);
2883
2884         return NULL;
2885 }
2886
2887 static struct intel_engine_cs *
2888 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2889 {
2890         struct drm_i915_private *dev_priv = engine->i915;
2891         u32 cmd, ipehr, head;
2892         u64 offset = 0;
2893         int i, backwards;
2894
2895         /*
2896          * This function does not support execlist mode - any attempt to
2897          * proceed further into this function will result in a kernel panic
2898          * when dereferencing ring->buffer, which is not set up in execlist
2899          * mode.
2900          *
2901          * The correct way of doing it would be to derive the currently
2902          * executing ring buffer from the current context, which is derived
2903          * from the currently running request. Unfortunately, to get the
2904          * current request we would have to grab the struct_mutex before doing
2905          * anything else, which would be ill-advised since some other thread
2906          * might have grabbed it already and managed to hang itself, causing
2907          * the hang checker to deadlock.
2908          *
2909          * Therefore, this function does not support execlist mode in its
2910          * current form. Just return NULL and move on.
2911          */
2912         if (engine->buffer == NULL)
2913                 return NULL;
2914
2915         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2916         if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
2917                 return NULL;
2918
2919         /*
2920          * HEAD is likely pointing to the dword after the actual command,
2921          * so scan backwards until we find the MBOX. But limit it to just 3
2922          * or 4 dwords depending on the semaphore wait command size.
2923          * Note that we don't care about ACTHD here since that might
2924          * point at at batch, and semaphores are always emitted into the
2925          * ringbuffer itself.
2926          */
2927         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2928         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2929
2930         for (i = backwards; i; --i) {
2931                 /*
2932                  * Be paranoid and presume the hw has gone off into the wild -
2933                  * our ring is smaller than what the hardware (and hence
2934                  * HEAD_ADDR) allows. Also handles wrap-around.
2935                  */
2936                 head &= engine->buffer->size - 1;
2937
2938                 /* This here seems to blow up */
2939                 cmd = ioread32(engine->buffer->virtual_start + head);
2940                 if (cmd == ipehr)
2941                         break;
2942
2943                 head -= 4;
2944         }
2945
2946         if (!i)
2947                 return NULL;
2948
2949         *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2950         if (INTEL_GEN(dev_priv) >= 8) {
2951                 offset = ioread32(engine->buffer->virtual_start + head + 12);
2952                 offset <<= 32;
2953                 offset = ioread32(engine->buffer->virtual_start + head + 8);
2954         }
2955         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2956 }
2957
2958 static int semaphore_passed(struct intel_engine_cs *engine)
2959 {
2960         struct drm_i915_private *dev_priv = engine->i915;
2961         struct intel_engine_cs *signaller;
2962         u32 seqno;
2963
2964         engine->hangcheck.deadlock++;
2965
2966         signaller = semaphore_waits_for(engine, &seqno);
2967         if (signaller == NULL)
2968                 return -1;
2969
2970         /* Prevent pathological recursion due to driver bugs */
2971         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2972                 return -1;
2973
2974         if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
2975                 return 1;
2976
2977         /* cursory check for an unkickable deadlock */
2978         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2979             semaphore_passed(signaller) < 0)
2980                 return -1;
2981
2982         return 0;
2983 }
2984
2985 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2986 {
2987         struct intel_engine_cs *engine;
2988
2989         for_each_engine(engine, dev_priv)
2990                 engine->hangcheck.deadlock = 0;
2991 }
2992
2993 static bool subunits_stuck(struct intel_engine_cs *engine)
2994 {
2995         u32 instdone[I915_NUM_INSTDONE_REG];
2996         bool stuck;
2997         int i;
2998
2999         if (engine->id != RCS)
3000                 return true;
3001
3002         i915_get_extra_instdone(engine->i915, instdone);
3003
3004         /* There might be unstable subunit states even when
3005          * actual head is not moving. Filter out the unstable ones by
3006          * accumulating the undone -> done transitions and only
3007          * consider those as progress.
3008          */
3009         stuck = true;
3010         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
3011                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
3012
3013                 if (tmp != engine->hangcheck.instdone[i])
3014                         stuck = false;
3015
3016                 engine->hangcheck.instdone[i] |= tmp;
3017         }
3018
3019         return stuck;
3020 }
3021
3022 static enum intel_ring_hangcheck_action
3023 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3024 {
3025         if (acthd != engine->hangcheck.acthd) {
3026
3027                 /* Clear subunit states on head movement */
3028                 memset(engine->hangcheck.instdone, 0,
3029                        sizeof(engine->hangcheck.instdone));
3030
3031                 return HANGCHECK_ACTIVE;
3032         }
3033
3034         if (!subunits_stuck(engine))
3035                 return HANGCHECK_ACTIVE;
3036
3037         return HANGCHECK_HUNG;
3038 }
3039
3040 static enum intel_ring_hangcheck_action
3041 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3042 {
3043         struct drm_i915_private *dev_priv = engine->i915;
3044         enum intel_ring_hangcheck_action ha;
3045         u32 tmp;
3046
3047         ha = head_stuck(engine, acthd);
3048         if (ha != HANGCHECK_HUNG)
3049                 return ha;
3050
3051         if (IS_GEN2(dev_priv))
3052                 return HANGCHECK_HUNG;
3053
3054         /* Is the chip hanging on a WAIT_FOR_EVENT?
3055          * If so we can simply poke the RB_WAIT bit
3056          * and break the hang. This should work on
3057          * all but the second generation chipsets.
3058          */
3059         tmp = I915_READ_CTL(engine);
3060         if (tmp & RING_WAIT) {
3061                 i915_handle_error(dev_priv, 0,
3062                                   "Kicking stuck wait on %s",
3063                                   engine->name);
3064                 I915_WRITE_CTL(engine, tmp);
3065                 return HANGCHECK_KICK;
3066         }
3067
3068         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3069                 switch (semaphore_passed(engine)) {
3070                 default:
3071                         return HANGCHECK_HUNG;
3072                 case 1:
3073                         i915_handle_error(dev_priv, 0,
3074                                           "Kicking stuck semaphore on %s",
3075                                           engine->name);
3076                         I915_WRITE_CTL(engine, tmp);
3077                         return HANGCHECK_KICK;
3078                 case 0:
3079                         return HANGCHECK_WAIT;
3080                 }
3081         }
3082
3083         return HANGCHECK_HUNG;
3084 }
3085
3086 static unsigned kick_waiters(struct intel_engine_cs *engine)
3087 {
3088         struct drm_i915_private *i915 = engine->i915;
3089         unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3090
3091         if (engine->hangcheck.user_interrupts == user_interrupts &&
3092             !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3093                 if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine)))
3094                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3095                                   engine->name);
3096                 else
3097                         DRM_INFO("Fake missed irq on %s\n",
3098                                  engine->name);
3099                 wake_up_all(&engine->irq_queue);
3100         }
3101
3102         return user_interrupts;
3103 }
3104 /*
3105  * This is called when the chip hasn't reported back with completed
3106  * batchbuffers in a long time. We keep track per ring seqno progress and
3107  * if there are no progress, hangcheck score for that ring is increased.
3108  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3109  * we kick the ring. If we see no progress on three subsequent calls
3110  * we assume chip is wedged and try to fix it by resetting the chip.
3111  */
3112 static void i915_hangcheck_elapsed(struct work_struct *work)
3113 {
3114         struct drm_i915_private *dev_priv =
3115                 container_of(work, typeof(*dev_priv),
3116                              gpu_error.hangcheck_work.work);
3117         struct intel_engine_cs *engine;
3118         enum intel_engine_id id;
3119         int busy_count = 0, rings_hung = 0;
3120         bool stuck[I915_NUM_ENGINES] = { 0 };
3121 #define BUSY 1
3122 #define KICK 5
3123 #define HUNG 20
3124 #define ACTIVE_DECAY 15
3125
3126         if (!i915.enable_hangcheck)
3127                 return;
3128
3129         /*
3130          * The hangcheck work is synced during runtime suspend, we don't
3131          * require a wakeref. TODO: instead of disabling the asserts make
3132          * sure that we hold a reference when this work is running.
3133          */
3134         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3135
3136         /* As enabling the GPU requires fairly extensive mmio access,
3137          * periodically arm the mmio checker to see if we are triggering
3138          * any invalid access.
3139          */
3140         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3141
3142         for_each_engine_id(engine, dev_priv, id) {
3143                 u64 acthd;
3144                 u32 seqno;
3145                 unsigned user_interrupts;
3146                 bool busy = true;
3147
3148                 semaphore_clear_deadlocks(dev_priv);
3149
3150                 /* We don't strictly need an irq-barrier here, as we are not
3151                  * serving an interrupt request, be paranoid in case the
3152                  * barrier has side-effects (such as preventing a broken
3153                  * cacheline snoop) and so be sure that we can see the seqno
3154                  * advance. If the seqno should stick, due to a stale
3155                  * cacheline, we would erroneously declare the GPU hung.
3156                  */
3157                 if (engine->irq_seqno_barrier)
3158                         engine->irq_seqno_barrier(engine);
3159
3160                 acthd = intel_ring_get_active_head(engine);
3161                 seqno = engine->get_seqno(engine);
3162
3163                 /* Reset stuck interrupts between batch advances */
3164                 user_interrupts = 0;
3165
3166                 if (engine->hangcheck.seqno == seqno) {
3167                         if (ring_idle(engine, seqno)) {
3168                                 engine->hangcheck.action = HANGCHECK_IDLE;
3169                                 if (waitqueue_active(&engine->irq_queue)) {
3170                                         /* Safeguard against driver failure */
3171                                         user_interrupts = kick_waiters(engine);
3172                                         engine->hangcheck.score += BUSY;
3173                                 } else
3174                                         busy = false;
3175                         } else {
3176                                 /* We always increment the hangcheck score
3177                                  * if the ring is busy and still processing
3178                                  * the same request, so that no single request
3179                                  * can run indefinitely (such as a chain of
3180                                  * batches). The only time we do not increment
3181                                  * the hangcheck score on this ring, if this
3182                                  * ring is in a legitimate wait for another
3183                                  * ring. In that case the waiting ring is a
3184                                  * victim and we want to be sure we catch the
3185                                  * right culprit. Then every time we do kick
3186                                  * the ring, add a small increment to the
3187                                  * score so that we can catch a batch that is
3188                                  * being repeatedly kicked and so responsible
3189                                  * for stalling the machine.
3190                                  */
3191                                 engine->hangcheck.action = ring_stuck(engine,
3192                                                                       acthd);
3193
3194                                 switch (engine->hangcheck.action) {
3195                                 case HANGCHECK_IDLE:
3196                                 case HANGCHECK_WAIT:
3197                                         break;
3198                                 case HANGCHECK_ACTIVE:
3199                                         engine->hangcheck.score += BUSY;
3200                                         break;
3201                                 case HANGCHECK_KICK:
3202                                         engine->hangcheck.score += KICK;
3203                                         break;
3204                                 case HANGCHECK_HUNG:
3205                                         engine->hangcheck.score += HUNG;
3206                                         stuck[id] = true;
3207                                         break;
3208                                 }
3209                         }
3210                 } else {
3211                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3212
3213                         /* Gradually reduce the count so that we catch DoS
3214                          * attempts across multiple batches.
3215                          */
3216                         if (engine->hangcheck.score > 0)
3217                                 engine->hangcheck.score -= ACTIVE_DECAY;
3218                         if (engine->hangcheck.score < 0)
3219                                 engine->hangcheck.score = 0;
3220
3221                         /* Clear head and subunit states on seqno movement */
3222                         acthd = 0;
3223
3224                         memset(engine->hangcheck.instdone, 0,
3225                                sizeof(engine->hangcheck.instdone));
3226                 }
3227
3228                 engine->hangcheck.seqno = seqno;
3229                 engine->hangcheck.acthd = acthd;
3230                 engine->hangcheck.user_interrupts = user_interrupts;
3231                 busy_count += busy;
3232         }
3233
3234         for_each_engine_id(engine, dev_priv, id) {
3235                 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3236                         DRM_INFO("%s on %s\n",
3237                                  stuck[id] ? "stuck" : "no progress",
3238                                  engine->name);
3239                         rings_hung |= intel_engine_flag(engine);
3240                 }
3241         }
3242
3243         if (rings_hung) {
3244                 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3245                 goto out;
3246         }
3247
3248         if (busy_count)
3249                 /* Reset timer case chip hangs without another request
3250                  * being added */
3251                 i915_queue_hangcheck(dev_priv);
3252
3253 out:
3254         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3255 }
3256
3257 void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3258 {
3259         struct i915_gpu_error *e = &dev_priv->gpu_error;
3260
3261         if (!i915.enable_hangcheck)
3262                 return;
3263
3264         /* Don't continually defer the hangcheck so that it is always run at
3265          * least once after work has been scheduled on any ring. Otherwise,
3266          * we will ignore a hung ring if a second ring is kept busy.
3267          */
3268
3269         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3270                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3271 }
3272
3273 static void ibx_irq_reset(struct drm_device *dev)
3274 {
3275         struct drm_i915_private *dev_priv = dev->dev_private;
3276
3277         if (HAS_PCH_NOP(dev))
3278                 return;
3279
3280         GEN5_IRQ_RESET(SDE);
3281
3282         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3283                 I915_WRITE(SERR_INT, 0xffffffff);
3284 }
3285
3286 /*
3287  * SDEIER is also touched by the interrupt handler to work around missed PCH
3288  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3289  * instead we unconditionally enable all PCH interrupt sources here, but then
3290  * only unmask them as needed with SDEIMR.
3291  *
3292  * This function needs to be called before interrupts are enabled.
3293  */
3294 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3295 {
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297
3298         if (HAS_PCH_NOP(dev))
3299                 return;
3300
3301         WARN_ON(I915_READ(SDEIER) != 0);
3302         I915_WRITE(SDEIER, 0xffffffff);
3303         POSTING_READ(SDEIER);
3304 }
3305
3306 static void gen5_gt_irq_reset(struct drm_device *dev)
3307 {
3308         struct drm_i915_private *dev_priv = dev->dev_private;
3309
3310         GEN5_IRQ_RESET(GT);
3311         if (INTEL_INFO(dev)->gen >= 6)
3312                 GEN5_IRQ_RESET(GEN6_PM);
3313 }
3314
3315 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3316 {
3317         enum pipe pipe;
3318
3319         if (IS_CHERRYVIEW(dev_priv))
3320                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3321         else
3322                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3323
3324         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3325         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3326
3327         for_each_pipe(dev_priv, pipe) {
3328                 I915_WRITE(PIPESTAT(pipe),
3329                            PIPE_FIFO_UNDERRUN_STATUS |
3330                            PIPESTAT_INT_STATUS_MASK);
3331                 dev_priv->pipestat_irq_mask[pipe] = 0;
3332         }
3333
3334         GEN5_IRQ_RESET(VLV_);
3335         dev_priv->irq_mask = ~0;
3336 }
3337
3338 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3339 {
3340         u32 pipestat_mask;
3341         u32 enable_mask;
3342         enum pipe pipe;
3343
3344         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3345                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3346
3347         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3348         for_each_pipe(dev_priv, pipe)
3349                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3350
3351         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3352                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3353                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3354         if (IS_CHERRYVIEW(dev_priv))
3355                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3356
3357         WARN_ON(dev_priv->irq_mask != ~0);
3358
3359         dev_priv->irq_mask = ~enable_mask;
3360
3361         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3362 }
3363
3364 /* drm_dma.h hooks
3365 */
3366 static void ironlake_irq_reset(struct drm_device *dev)
3367 {
3368         struct drm_i915_private *dev_priv = dev->dev_private;
3369
3370         I915_WRITE(HWSTAM, 0xffffffff);
3371
3372         GEN5_IRQ_RESET(DE);
3373         if (IS_GEN7(dev))
3374                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3375
3376         gen5_gt_irq_reset(dev);
3377
3378         ibx_irq_reset(dev);
3379 }
3380
3381 static void valleyview_irq_preinstall(struct drm_device *dev)
3382 {
3383         struct drm_i915_private *dev_priv = dev->dev_private;
3384
3385         I915_WRITE(VLV_MASTER_IER, 0);
3386         POSTING_READ(VLV_MASTER_IER);
3387
3388         gen5_gt_irq_reset(dev);
3389
3390         spin_lock_irq(&dev_priv->irq_lock);
3391         if (dev_priv->display_irqs_enabled)
3392                 vlv_display_irq_reset(dev_priv);
3393         spin_unlock_irq(&dev_priv->irq_lock);
3394 }
3395
3396 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3397 {
3398         GEN8_IRQ_RESET_NDX(GT, 0);
3399         GEN8_IRQ_RESET_NDX(GT, 1);
3400         GEN8_IRQ_RESET_NDX(GT, 2);
3401         GEN8_IRQ_RESET_NDX(GT, 3);
3402 }
3403
3404 static void gen8_irq_reset(struct drm_device *dev)
3405 {
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407         int pipe;
3408
3409         I915_WRITE(GEN8_MASTER_IRQ, 0);
3410         POSTING_READ(GEN8_MASTER_IRQ);
3411
3412         gen8_gt_irq_reset(dev_priv);
3413
3414         for_each_pipe(dev_priv, pipe)
3415                 if (intel_display_power_is_enabled(dev_priv,
3416                                                    POWER_DOMAIN_PIPE(pipe)))
3417                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3418
3419         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3420         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3421         GEN5_IRQ_RESET(GEN8_PCU_);
3422
3423         if (HAS_PCH_SPLIT(dev))
3424                 ibx_irq_reset(dev);
3425 }
3426
3427 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3428                                      unsigned int pipe_mask)
3429 {
3430         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3431         enum pipe pipe;
3432
3433         spin_lock_irq(&dev_priv->irq_lock);
3434         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3435                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3436                                   dev_priv->de_irq_mask[pipe],
3437                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3438         spin_unlock_irq(&dev_priv->irq_lock);
3439 }
3440
3441 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3442                                      unsigned int pipe_mask)
3443 {
3444         enum pipe pipe;
3445
3446         spin_lock_irq(&dev_priv->irq_lock);
3447         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3448                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3449         spin_unlock_irq(&dev_priv->irq_lock);
3450
3451         /* make sure we're done processing display irqs */
3452         synchronize_irq(dev_priv->dev->irq);
3453 }
3454
3455 static void cherryview_irq_preinstall(struct drm_device *dev)
3456 {
3457         struct drm_i915_private *dev_priv = dev->dev_private;
3458
3459         I915_WRITE(GEN8_MASTER_IRQ, 0);
3460         POSTING_READ(GEN8_MASTER_IRQ);
3461
3462         gen8_gt_irq_reset(dev_priv);
3463
3464         GEN5_IRQ_RESET(GEN8_PCU_);
3465
3466         spin_lock_irq(&dev_priv->irq_lock);
3467         if (dev_priv->display_irqs_enabled)
3468                 vlv_display_irq_reset(dev_priv);
3469         spin_unlock_irq(&dev_priv->irq_lock);
3470 }
3471
3472 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3473                                   const u32 hpd[HPD_NUM_PINS])
3474 {
3475         struct intel_encoder *encoder;
3476         u32 enabled_irqs = 0;
3477
3478         for_each_intel_encoder(dev_priv->dev, encoder)
3479                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3480                         enabled_irqs |= hpd[encoder->hpd_pin];
3481
3482         return enabled_irqs;
3483 }
3484
3485 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3486 {
3487         u32 hotplug_irqs, hotplug, enabled_irqs;
3488
3489         if (HAS_PCH_IBX(dev_priv)) {
3490                 hotplug_irqs = SDE_HOTPLUG_MASK;
3491                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3492         } else {
3493                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3494                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3495         }
3496
3497         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3498
3499         /*
3500          * Enable digital hotplug on the PCH, and configure the DP short pulse
3501          * duration to 2ms (which is the minimum in the Display Port spec).
3502          * The pulse duration bits are reserved on LPT+.
3503          */
3504         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3505         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3506         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3507         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3508         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3509         /*
3510          * When CPU and PCH are on the same package, port A
3511          * HPD must be enabled in both north and south.
3512          */
3513         if (HAS_PCH_LPT_LP(dev_priv))
3514                 hotplug |= PORTA_HOTPLUG_ENABLE;
3515         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3516 }
3517
3518 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3519 {
3520         u32 hotplug_irqs, hotplug, enabled_irqs;
3521
3522         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3523         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3524
3525         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3526
3527         /* Enable digital hotplug on the PCH */
3528         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3529         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3530                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3531         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3532
3533         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3534         hotplug |= PORTE_HOTPLUG_ENABLE;
3535         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3536 }
3537
3538 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3539 {
3540         u32 hotplug_irqs, hotplug, enabled_irqs;
3541
3542         if (INTEL_GEN(dev_priv) >= 8) {
3543                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3544                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3545
3546                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3547         } else if (INTEL_GEN(dev_priv) >= 7) {
3548                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3549                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3550
3551                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3552         } else {
3553                 hotplug_irqs = DE_DP_A_HOTPLUG;
3554                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3555
3556                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3557         }
3558
3559         /*
3560          * Enable digital hotplug on the CPU, and configure the DP short pulse
3561          * duration to 2ms (which is the minimum in the Display Port spec)
3562          * The pulse duration bits are reserved on HSW+.
3563          */
3564         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3565         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3566         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3567         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3568
3569         ibx_hpd_irq_setup(dev_priv);
3570 }
3571
3572 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3573 {
3574         u32 hotplug_irqs, hotplug, enabled_irqs;
3575
3576         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3577         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3578
3579         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3580
3581         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3582         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3583                 PORTA_HOTPLUG_ENABLE;
3584
3585         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3586                       hotplug, enabled_irqs);
3587         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3588
3589         /*
3590          * For BXT invert bit has to be set based on AOB design
3591          * for HPD detection logic, update it based on VBT fields.
3592          */
3593
3594         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3595             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3596                 hotplug |= BXT_DDIA_HPD_INVERT;
3597         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3598             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3599                 hotplug |= BXT_DDIB_HPD_INVERT;
3600         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3601             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3602                 hotplug |= BXT_DDIC_HPD_INVERT;
3603
3604         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3605 }
3606
3607 static void ibx_irq_postinstall(struct drm_device *dev)
3608 {
3609         struct drm_i915_private *dev_priv = dev->dev_private;
3610         u32 mask;
3611
3612         if (HAS_PCH_NOP(dev))
3613                 return;
3614
3615         if (HAS_PCH_IBX(dev))
3616                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3617         else
3618                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3619
3620         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3621         I915_WRITE(SDEIMR, ~mask);
3622 }
3623
3624 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3625 {
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         u32 pm_irqs, gt_irqs;
3628
3629         pm_irqs = gt_irqs = 0;
3630
3631         dev_priv->gt_irq_mask = ~0;
3632         if (HAS_L3_DPF(dev)) {
3633                 /* L3 parity interrupt is always unmasked. */
3634                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3635                 gt_irqs |= GT_PARITY_ERROR(dev);
3636         }
3637
3638         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3639         if (IS_GEN5(dev)) {
3640                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3641                            ILK_BSD_USER_INTERRUPT;
3642         } else {
3643                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3644         }
3645
3646         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3647
3648         if (INTEL_INFO(dev)->gen >= 6) {
3649                 /*
3650                  * RPS interrupts will get enabled/disabled on demand when RPS
3651                  * itself is enabled/disabled.
3652                  */
3653                 if (HAS_VEBOX(dev))
3654                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3655
3656                 dev_priv->pm_irq_mask = 0xffffffff;
3657                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3658         }
3659 }
3660
3661 static int ironlake_irq_postinstall(struct drm_device *dev)
3662 {
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         u32 display_mask, extra_mask;
3665
3666         if (INTEL_INFO(dev)->gen >= 7) {
3667                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3668                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3669                                 DE_PLANEB_FLIP_DONE_IVB |
3670                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3671                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3672                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3673                               DE_DP_A_HOTPLUG_IVB);
3674         } else {
3675                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3676                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3677                                 DE_AUX_CHANNEL_A |
3678                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3679                                 DE_POISON);
3680                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3681                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3682                               DE_DP_A_HOTPLUG);
3683         }
3684
3685         dev_priv->irq_mask = ~display_mask;
3686
3687         I915_WRITE(HWSTAM, 0xeffe);
3688
3689         ibx_irq_pre_postinstall(dev);
3690
3691         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3692
3693         gen5_gt_irq_postinstall(dev);
3694
3695         ibx_irq_postinstall(dev);
3696
3697         if (IS_IRONLAKE_M(dev)) {
3698                 /* Enable PCU event interrupts
3699                  *
3700                  * spinlocking not required here for correctness since interrupt
3701                  * setup is guaranteed to run in single-threaded context. But we
3702                  * need it to make the assert_spin_locked happy. */
3703                 spin_lock_irq(&dev_priv->irq_lock);
3704                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3705                 spin_unlock_irq(&dev_priv->irq_lock);
3706         }
3707
3708         return 0;
3709 }
3710
3711 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3712 {
3713         assert_spin_locked(&dev_priv->irq_lock);
3714
3715         if (dev_priv->display_irqs_enabled)
3716                 return;
3717
3718         dev_priv->display_irqs_enabled = true;
3719
3720         if (intel_irqs_enabled(dev_priv)) {
3721                 vlv_display_irq_reset(dev_priv);
3722                 vlv_display_irq_postinstall(dev_priv);
3723         }
3724 }
3725
3726 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3727 {
3728         assert_spin_locked(&dev_priv->irq_lock);
3729
3730         if (!dev_priv->display_irqs_enabled)
3731                 return;
3732
3733         dev_priv->display_irqs_enabled = false;
3734
3735         if (intel_irqs_enabled(dev_priv))
3736                 vlv_display_irq_reset(dev_priv);
3737 }
3738
3739
3740 static int valleyview_irq_postinstall(struct drm_device *dev)
3741 {
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743
3744         gen5_gt_irq_postinstall(dev);
3745
3746         spin_lock_irq(&dev_priv->irq_lock);
3747         if (dev_priv->display_irqs_enabled)
3748                 vlv_display_irq_postinstall(dev_priv);
3749         spin_unlock_irq(&dev_priv->irq_lock);
3750
3751         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3752         POSTING_READ(VLV_MASTER_IER);
3753
3754         return 0;
3755 }
3756
3757 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3758 {
3759         /* These are interrupts we'll toggle with the ring mask register */
3760         uint32_t gt_interrupts[] = {
3761                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3762                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3763                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3764                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3765                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3766                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3767                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3768                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3769                 0,
3770                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3771                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3772                 };
3773
3774         if (HAS_L3_DPF(dev_priv))
3775                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3776
3777         dev_priv->pm_irq_mask = 0xffffffff;
3778         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3779         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3780         /*
3781          * RPS interrupts will get enabled/disabled on demand when RPS itself
3782          * is enabled/disabled.
3783          */
3784         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3785         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3786 }
3787
3788 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3789 {
3790         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3791         uint32_t de_pipe_enables;
3792         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3793         u32 de_port_enables;
3794         enum pipe pipe;
3795
3796         if (INTEL_INFO(dev_priv)->gen >= 9) {
3797                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3798                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3799                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3800                                   GEN9_AUX_CHANNEL_D;
3801                 if (IS_BROXTON(dev_priv))
3802                         de_port_masked |= BXT_DE_PORT_GMBUS;
3803         } else {
3804                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3805                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3806         }
3807
3808         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3809                                            GEN8_PIPE_FIFO_UNDERRUN;
3810
3811         de_port_enables = de_port_masked;
3812         if (IS_BROXTON(dev_priv))
3813                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3814         else if (IS_BROADWELL(dev_priv))
3815                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3816
3817         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3818         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3819         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3820
3821         for_each_pipe(dev_priv, pipe)
3822                 if (intel_display_power_is_enabled(dev_priv,
3823                                 POWER_DOMAIN_PIPE(pipe)))
3824                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3825                                           dev_priv->de_irq_mask[pipe],
3826                                           de_pipe_enables);
3827
3828         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3829 }
3830
3831 static int gen8_irq_postinstall(struct drm_device *dev)
3832 {
3833         struct drm_i915_private *dev_priv = dev->dev_private;
3834
3835         if (HAS_PCH_SPLIT(dev))
3836                 ibx_irq_pre_postinstall(dev);
3837
3838         gen8_gt_irq_postinstall(dev_priv);
3839         gen8_de_irq_postinstall(dev_priv);
3840
3841         if (HAS_PCH_SPLIT(dev))
3842                 ibx_irq_postinstall(dev);
3843
3844         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3845         POSTING_READ(GEN8_MASTER_IRQ);
3846
3847         return 0;
3848 }
3849
3850 static int cherryview_irq_postinstall(struct drm_device *dev)
3851 {
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853
3854         gen8_gt_irq_postinstall(dev_priv);
3855
3856         spin_lock_irq(&dev_priv->irq_lock);
3857         if (dev_priv->display_irqs_enabled)
3858                 vlv_display_irq_postinstall(dev_priv);
3859         spin_unlock_irq(&dev_priv->irq_lock);
3860
3861         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3862         POSTING_READ(GEN8_MASTER_IRQ);
3863
3864         return 0;
3865 }
3866
3867 static void gen8_irq_uninstall(struct drm_device *dev)
3868 {
3869         struct drm_i915_private *dev_priv = dev->dev_private;
3870
3871         if (!dev_priv)
3872                 return;
3873
3874         gen8_irq_reset(dev);
3875 }
3876
3877 static void valleyview_irq_uninstall(struct drm_device *dev)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881         if (!dev_priv)
3882                 return;
3883
3884         I915_WRITE(VLV_MASTER_IER, 0);
3885         POSTING_READ(VLV_MASTER_IER);
3886
3887         gen5_gt_irq_reset(dev);
3888
3889         I915_WRITE(HWSTAM, 0xffffffff);
3890
3891         spin_lock_irq(&dev_priv->irq_lock);
3892         if (dev_priv->display_irqs_enabled)
3893                 vlv_display_irq_reset(dev_priv);
3894         spin_unlock_irq(&dev_priv->irq_lock);
3895 }
3896
3897 static void cherryview_irq_uninstall(struct drm_device *dev)
3898 {
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900
3901         if (!dev_priv)
3902                 return;
3903
3904         I915_WRITE(GEN8_MASTER_IRQ, 0);
3905         POSTING_READ(GEN8_MASTER_IRQ);
3906
3907         gen8_gt_irq_reset(dev_priv);
3908
3909         GEN5_IRQ_RESET(GEN8_PCU_);
3910
3911         spin_lock_irq(&dev_priv->irq_lock);
3912         if (dev_priv->display_irqs_enabled)
3913                 vlv_display_irq_reset(dev_priv);
3914         spin_unlock_irq(&dev_priv->irq_lock);
3915 }
3916
3917 static void ironlake_irq_uninstall(struct drm_device *dev)
3918 {
3919         struct drm_i915_private *dev_priv = dev->dev_private;
3920
3921         if (!dev_priv)
3922                 return;
3923
3924         ironlake_irq_reset(dev);
3925 }
3926
3927 static void i8xx_irq_preinstall(struct drm_device * dev)
3928 {
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         int pipe;
3931
3932         for_each_pipe(dev_priv, pipe)
3933                 I915_WRITE(PIPESTAT(pipe), 0);
3934         I915_WRITE16(IMR, 0xffff);
3935         I915_WRITE16(IER, 0x0);
3936         POSTING_READ16(IER);
3937 }
3938
3939 static int i8xx_irq_postinstall(struct drm_device *dev)
3940 {
3941         struct drm_i915_private *dev_priv = dev->dev_private;
3942
3943         I915_WRITE16(EMR,
3944                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3945
3946         /* Unmask the interrupts that we always want on. */
3947         dev_priv->irq_mask =
3948                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3949                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3950                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3951                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3952         I915_WRITE16(IMR, dev_priv->irq_mask);
3953
3954         I915_WRITE16(IER,
3955                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3956                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3957                      I915_USER_INTERRUPT);
3958         POSTING_READ16(IER);
3959
3960         /* Interrupt setup is already guaranteed to be single-threaded, this is
3961          * just to make the assert_spin_locked check happy. */
3962         spin_lock_irq(&dev_priv->irq_lock);
3963         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3964         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3965         spin_unlock_irq(&dev_priv->irq_lock);
3966
3967         return 0;
3968 }
3969
3970 /*
3971  * Returns true when a page flip has completed.
3972  */
3973 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3974                                int plane, int pipe, u32 iir)
3975 {
3976         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3977
3978         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3979                 return false;
3980
3981         if ((iir & flip_pending) == 0)
3982                 goto check_page_flip;
3983
3984         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3985          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3986          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3987          * the flip is completed (no longer pending). Since this doesn't raise
3988          * an interrupt per se, we watch for the change at vblank.
3989          */
3990         if (I915_READ16(ISR) & flip_pending)
3991                 goto check_page_flip;
3992
3993         intel_finish_page_flip(dev_priv, pipe);
3994         return true;
3995
3996 check_page_flip:
3997         intel_check_page_flip(dev_priv, pipe);
3998         return false;
3999 }
4000
4001 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4002 {
4003         struct drm_device *dev = arg;
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         u16 iir, new_iir;
4006         u32 pipe_stats[2];
4007         int pipe;
4008         u16 flip_mask =
4009                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4010                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4011         irqreturn_t ret;
4012
4013         if (!intel_irqs_enabled(dev_priv))
4014                 return IRQ_NONE;
4015
4016         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4017         disable_rpm_wakeref_asserts(dev_priv);
4018
4019         ret = IRQ_NONE;
4020         iir = I915_READ16(IIR);
4021         if (iir == 0)
4022                 goto out;
4023
4024         while (iir & ~flip_mask) {
4025                 /* Can't rely on pipestat interrupt bit in iir as it might
4026                  * have been cleared after the pipestat interrupt was received.
4027                  * It doesn't set the bit in iir again, but it still produces
4028                  * interrupts (for non-MSI).
4029                  */
4030                 spin_lock(&dev_priv->irq_lock);
4031                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4032                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4033
4034                 for_each_pipe(dev_priv, pipe) {
4035                         i915_reg_t reg = PIPESTAT(pipe);
4036                         pipe_stats[pipe] = I915_READ(reg);
4037
4038                         /*
4039                          * Clear the PIPE*STAT regs before the IIR
4040                          */
4041                         if (pipe_stats[pipe] & 0x8000ffff)
4042                                 I915_WRITE(reg, pipe_stats[pipe]);
4043                 }
4044                 spin_unlock(&dev_priv->irq_lock);
4045
4046                 I915_WRITE16(IIR, iir & ~flip_mask);
4047                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4048
4049                 if (iir & I915_USER_INTERRUPT)
4050                         notify_ring(&dev_priv->engine[RCS]);
4051
4052                 for_each_pipe(dev_priv, pipe) {
4053                         int plane = pipe;
4054                         if (HAS_FBC(dev_priv))
4055                                 plane = !plane;
4056
4057                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4058                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4059                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4060
4061                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4062                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4063
4064                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4065                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4066                                                                     pipe);
4067                 }
4068
4069                 iir = new_iir;
4070         }
4071         ret = IRQ_HANDLED;
4072
4073 out:
4074         enable_rpm_wakeref_asserts(dev_priv);
4075
4076         return ret;
4077 }
4078
4079 static void i8xx_irq_uninstall(struct drm_device * dev)
4080 {
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         int pipe;
4083
4084         for_each_pipe(dev_priv, pipe) {
4085                 /* Clear enable bits; then clear status bits */
4086                 I915_WRITE(PIPESTAT(pipe), 0);
4087                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4088         }
4089         I915_WRITE16(IMR, 0xffff);
4090         I915_WRITE16(IER, 0x0);
4091         I915_WRITE16(IIR, I915_READ16(IIR));
4092 }
4093
4094 static void i915_irq_preinstall(struct drm_device * dev)
4095 {
4096         struct drm_i915_private *dev_priv = dev->dev_private;
4097         int pipe;
4098
4099         if (I915_HAS_HOTPLUG(dev)) {
4100                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4101                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4102         }
4103
4104         I915_WRITE16(HWSTAM, 0xeffe);
4105         for_each_pipe(dev_priv, pipe)
4106                 I915_WRITE(PIPESTAT(pipe), 0);
4107         I915_WRITE(IMR, 0xffffffff);
4108         I915_WRITE(IER, 0x0);
4109         POSTING_READ(IER);
4110 }
4111
4112 static int i915_irq_postinstall(struct drm_device *dev)
4113 {
4114         struct drm_i915_private *dev_priv = dev->dev_private;
4115         u32 enable_mask;
4116
4117         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4118
4119         /* Unmask the interrupts that we always want on. */
4120         dev_priv->irq_mask =
4121                 ~(I915_ASLE_INTERRUPT |
4122                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4123                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4124                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4125                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4126
4127         enable_mask =
4128                 I915_ASLE_INTERRUPT |
4129                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4130                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4131                 I915_USER_INTERRUPT;
4132
4133         if (I915_HAS_HOTPLUG(dev)) {
4134                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4135                 POSTING_READ(PORT_HOTPLUG_EN);
4136
4137                 /* Enable in IER... */
4138                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4139                 /* and unmask in IMR */
4140                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4141         }
4142
4143         I915_WRITE(IMR, dev_priv->irq_mask);
4144         I915_WRITE(IER, enable_mask);
4145         POSTING_READ(IER);
4146
4147         i915_enable_asle_pipestat(dev_priv);
4148
4149         /* Interrupt setup is already guaranteed to be single-threaded, this is
4150          * just to make the assert_spin_locked check happy. */
4151         spin_lock_irq(&dev_priv->irq_lock);
4152         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4153         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4154         spin_unlock_irq(&dev_priv->irq_lock);
4155
4156         return 0;
4157 }
4158
4159 /*
4160  * Returns true when a page flip has completed.
4161  */
4162 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4163                                int plane, int pipe, u32 iir)
4164 {
4165         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4166
4167         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4168                 return false;
4169
4170         if ((iir & flip_pending) == 0)
4171                 goto check_page_flip;
4172
4173         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4174          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4175          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4176          * the flip is completed (no longer pending). Since this doesn't raise
4177          * an interrupt per se, we watch for the change at vblank.
4178          */
4179         if (I915_READ(ISR) & flip_pending)
4180                 goto check_page_flip;
4181
4182         intel_finish_page_flip(dev_priv, pipe);
4183         return true;
4184
4185 check_page_flip:
4186         intel_check_page_flip(dev_priv, pipe);
4187         return false;
4188 }
4189
4190 static irqreturn_t i915_irq_handler(int irq, void *arg)
4191 {
4192         struct drm_device *dev = arg;
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4195         u32 flip_mask =
4196                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4197                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4198         int pipe, ret = IRQ_NONE;
4199
4200         if (!intel_irqs_enabled(dev_priv))
4201                 return IRQ_NONE;
4202
4203         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4204         disable_rpm_wakeref_asserts(dev_priv);
4205
4206         iir = I915_READ(IIR);
4207         do {
4208                 bool irq_received = (iir & ~flip_mask) != 0;
4209                 bool blc_event = false;
4210
4211                 /* Can't rely on pipestat interrupt bit in iir as it might
4212                  * have been cleared after the pipestat interrupt was received.
4213                  * It doesn't set the bit in iir again, but it still produces
4214                  * interrupts (for non-MSI).
4215                  */
4216                 spin_lock(&dev_priv->irq_lock);
4217                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4218                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4219
4220                 for_each_pipe(dev_priv, pipe) {
4221                         i915_reg_t reg = PIPESTAT(pipe);
4222                         pipe_stats[pipe] = I915_READ(reg);
4223
4224                         /* Clear the PIPE*STAT regs before the IIR */
4225                         if (pipe_stats[pipe] & 0x8000ffff) {
4226                                 I915_WRITE(reg, pipe_stats[pipe]);
4227                                 irq_received = true;
4228                         }
4229                 }
4230                 spin_unlock(&dev_priv->irq_lock);
4231
4232                 if (!irq_received)
4233                         break;
4234
4235                 /* Consume port.  Then clear IIR or we'll miss events */
4236                 if (I915_HAS_HOTPLUG(dev_priv) &&
4237                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4238                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4239                         if (hotplug_status)
4240                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4241                 }
4242
4243                 I915_WRITE(IIR, iir & ~flip_mask);
4244                 new_iir = I915_READ(IIR); /* Flush posted writes */
4245
4246                 if (iir & I915_USER_INTERRUPT)
4247                         notify_ring(&dev_priv->engine[RCS]);
4248
4249                 for_each_pipe(dev_priv, pipe) {
4250                         int plane = pipe;
4251                         if (HAS_FBC(dev_priv))
4252                                 plane = !plane;
4253
4254                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4255                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4256                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4257
4258                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4259                                 blc_event = true;
4260
4261                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4262                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4263
4264                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4265                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4266                                                                     pipe);
4267                 }
4268
4269                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4270                         intel_opregion_asle_intr(dev_priv);
4271
4272                 /* With MSI, interrupts are only generated when iir
4273                  * transitions from zero to nonzero.  If another bit got
4274                  * set while we were handling the existing iir bits, then
4275                  * we would never get another interrupt.
4276                  *
4277                  * This is fine on non-MSI as well, as if we hit this path
4278                  * we avoid exiting the interrupt handler only to generate
4279                  * another one.
4280                  *
4281                  * Note that for MSI this could cause a stray interrupt report
4282                  * if an interrupt landed in the time between writing IIR and
4283                  * the posting read.  This should be rare enough to never
4284                  * trigger the 99% of 100,000 interrupts test for disabling
4285                  * stray interrupts.
4286                  */
4287                 ret = IRQ_HANDLED;
4288                 iir = new_iir;
4289         } while (iir & ~flip_mask);
4290
4291         enable_rpm_wakeref_asserts(dev_priv);
4292
4293         return ret;
4294 }
4295
4296 static void i915_irq_uninstall(struct drm_device * dev)
4297 {
4298         struct drm_i915_private *dev_priv = dev->dev_private;
4299         int pipe;
4300
4301         if (I915_HAS_HOTPLUG(dev)) {
4302                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4303                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4304         }
4305
4306         I915_WRITE16(HWSTAM, 0xffff);
4307         for_each_pipe(dev_priv, pipe) {
4308                 /* Clear enable bits; then clear status bits */
4309                 I915_WRITE(PIPESTAT(pipe), 0);
4310                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4311         }
4312         I915_WRITE(IMR, 0xffffffff);
4313         I915_WRITE(IER, 0x0);
4314
4315         I915_WRITE(IIR, I915_READ(IIR));
4316 }
4317
4318 static void i965_irq_preinstall(struct drm_device * dev)
4319 {
4320         struct drm_i915_private *dev_priv = dev->dev_private;
4321         int pipe;
4322
4323         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4324         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4325
4326         I915_WRITE(HWSTAM, 0xeffe);
4327         for_each_pipe(dev_priv, pipe)
4328                 I915_WRITE(PIPESTAT(pipe), 0);
4329         I915_WRITE(IMR, 0xffffffff);
4330         I915_WRITE(IER, 0x0);
4331         POSTING_READ(IER);
4332 }
4333
4334 static int i965_irq_postinstall(struct drm_device *dev)
4335 {
4336         struct drm_i915_private *dev_priv = dev->dev_private;
4337         u32 enable_mask;
4338         u32 error_mask;
4339
4340         /* Unmask the interrupts that we always want on. */
4341         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4342                                I915_DISPLAY_PORT_INTERRUPT |
4343                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4344                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4345                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4346                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4347                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4348
4349         enable_mask = ~dev_priv->irq_mask;
4350         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4351                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4352         enable_mask |= I915_USER_INTERRUPT;
4353
4354         if (IS_G4X(dev_priv))
4355                 enable_mask |= I915_BSD_USER_INTERRUPT;
4356
4357         /* Interrupt setup is already guaranteed to be single-threaded, this is
4358          * just to make the assert_spin_locked check happy. */
4359         spin_lock_irq(&dev_priv->irq_lock);
4360         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4361         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4362         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4363         spin_unlock_irq(&dev_priv->irq_lock);
4364
4365         /*
4366          * Enable some error detection, note the instruction error mask
4367          * bit is reserved, so we leave it masked.
4368          */
4369         if (IS_G4X(dev_priv)) {
4370                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4371                                GM45_ERROR_MEM_PRIV |
4372                                GM45_ERROR_CP_PRIV |
4373                                I915_ERROR_MEMORY_REFRESH);
4374         } else {
4375                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4376                                I915_ERROR_MEMORY_REFRESH);
4377         }
4378         I915_WRITE(EMR, error_mask);
4379
4380         I915_WRITE(IMR, dev_priv->irq_mask);
4381         I915_WRITE(IER, enable_mask);
4382         POSTING_READ(IER);
4383
4384         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4385         POSTING_READ(PORT_HOTPLUG_EN);
4386
4387         i915_enable_asle_pipestat(dev_priv);
4388
4389         return 0;
4390 }
4391
4392 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4393 {
4394         u32 hotplug_en;
4395
4396         assert_spin_locked(&dev_priv->irq_lock);
4397
4398         /* Note HDMI and DP share hotplug bits */
4399         /* enable bits are the same for all generations */
4400         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4401         /* Programming the CRT detection parameters tends
4402            to generate a spurious hotplug event about three
4403            seconds later.  So just do it once.
4404         */
4405         if (IS_G4X(dev_priv))
4406                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4407         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4408
4409         /* Ignore TV since it's buggy */
4410         i915_hotplug_interrupt_update_locked(dev_priv,
4411                                              HOTPLUG_INT_EN_MASK |
4412                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4413                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4414                                              hotplug_en);
4415 }
4416
4417 static irqreturn_t i965_irq_handler(int irq, void *arg)
4418 {
4419         struct drm_device *dev = arg;
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421         u32 iir, new_iir;
4422         u32 pipe_stats[I915_MAX_PIPES];
4423         int ret = IRQ_NONE, pipe;
4424         u32 flip_mask =
4425                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4426                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4427
4428         if (!intel_irqs_enabled(dev_priv))
4429                 return IRQ_NONE;
4430
4431         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4432         disable_rpm_wakeref_asserts(dev_priv);
4433
4434         iir = I915_READ(IIR);
4435
4436         for (;;) {
4437                 bool irq_received = (iir & ~flip_mask) != 0;
4438                 bool blc_event = false;
4439
4440                 /* Can't rely on pipestat interrupt bit in iir as it might
4441                  * have been cleared after the pipestat interrupt was received.
4442                  * It doesn't set the bit in iir again, but it still produces
4443                  * interrupts (for non-MSI).
4444                  */
4445                 spin_lock(&dev_priv->irq_lock);
4446                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4447                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4448
4449                 for_each_pipe(dev_priv, pipe) {
4450                         i915_reg_t reg = PIPESTAT(pipe);
4451                         pipe_stats[pipe] = I915_READ(reg);
4452
4453                         /*
4454                          * Clear the PIPE*STAT regs before the IIR
4455                          */
4456                         if (pipe_stats[pipe] & 0x8000ffff) {
4457                                 I915_WRITE(reg, pipe_stats[pipe]);
4458                                 irq_received = true;
4459                         }
4460                 }
4461                 spin_unlock(&dev_priv->irq_lock);
4462
4463                 if (!irq_received)
4464                         break;
4465
4466                 ret = IRQ_HANDLED;
4467
4468                 /* Consume port.  Then clear IIR or we'll miss events */
4469                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4470                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4471                         if (hotplug_status)
4472                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4473                 }
4474
4475                 I915_WRITE(IIR, iir & ~flip_mask);
4476                 new_iir = I915_READ(IIR); /* Flush posted writes */
4477
4478                 if (iir & I915_USER_INTERRUPT)
4479                         notify_ring(&dev_priv->engine[RCS]);
4480                 if (iir & I915_BSD_USER_INTERRUPT)
4481                         notify_ring(&dev_priv->engine[VCS]);
4482
4483                 for_each_pipe(dev_priv, pipe) {
4484                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4485                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4486                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4487
4488                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4489                                 blc_event = true;
4490
4491                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4492                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4493
4494                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4495                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4496                 }
4497
4498                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4499                         intel_opregion_asle_intr(dev_priv);
4500
4501                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4502                         gmbus_irq_handler(dev_priv);
4503
4504                 /* With MSI, interrupts are only generated when iir
4505                  * transitions from zero to nonzero.  If another bit got
4506                  * set while we were handling the existing iir bits, then
4507                  * we would never get another interrupt.
4508                  *
4509                  * This is fine on non-MSI as well, as if we hit this path
4510                  * we avoid exiting the interrupt handler only to generate
4511                  * another one.
4512                  *
4513                  * Note that for MSI this could cause a stray interrupt report
4514                  * if an interrupt landed in the time between writing IIR and
4515                  * the posting read.  This should be rare enough to never
4516                  * trigger the 99% of 100,000 interrupts test for disabling
4517                  * stray interrupts.
4518                  */
4519                 iir = new_iir;
4520         }
4521
4522         enable_rpm_wakeref_asserts(dev_priv);
4523
4524         return ret;
4525 }
4526
4527 static void i965_irq_uninstall(struct drm_device * dev)
4528 {
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         int pipe;
4531
4532         if (!dev_priv)
4533                 return;
4534
4535         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4536         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4537
4538         I915_WRITE(HWSTAM, 0xffffffff);
4539         for_each_pipe(dev_priv, pipe)
4540                 I915_WRITE(PIPESTAT(pipe), 0);
4541         I915_WRITE(IMR, 0xffffffff);
4542         I915_WRITE(IER, 0x0);
4543
4544         for_each_pipe(dev_priv, pipe)
4545                 I915_WRITE(PIPESTAT(pipe),
4546                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4547         I915_WRITE(IIR, I915_READ(IIR));
4548 }
4549
4550 /**
4551  * intel_irq_init - initializes irq support
4552  * @dev_priv: i915 device instance
4553  *
4554  * This function initializes all the irq support including work items, timers
4555  * and all the vtables. It does not setup the interrupt itself though.
4556  */
4557 void intel_irq_init(struct drm_i915_private *dev_priv)
4558 {
4559         struct drm_device *dev = dev_priv->dev;
4560
4561         intel_hpd_init_work(dev_priv);
4562
4563         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4564         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4565
4566         /* Let's track the enabled rps events */
4567         if (IS_VALLEYVIEW(dev_priv))
4568                 /* WaGsvRC0ResidencyMethod:vlv */
4569                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4570         else
4571                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4572
4573         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4574                           i915_hangcheck_elapsed);
4575
4576         if (IS_GEN2(dev_priv)) {
4577                 dev->max_vblank_count = 0;
4578                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4579         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4580                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4581                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4582         } else {
4583                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4584                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4585         }
4586
4587         /*
4588          * Opt out of the vblank disable timer on everything except gen2.
4589          * Gen2 doesn't have a hardware frame counter and so depends on
4590          * vblank interrupts to produce sane vblank seuquence numbers.
4591          */
4592         if (!IS_GEN2(dev_priv))
4593                 dev->vblank_disable_immediate = true;
4594
4595         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4596         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4597
4598         if (IS_CHERRYVIEW(dev_priv)) {
4599                 dev->driver->irq_handler = cherryview_irq_handler;
4600                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4601                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4602                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4603                 dev->driver->enable_vblank = valleyview_enable_vblank;
4604                 dev->driver->disable_vblank = valleyview_disable_vblank;
4605                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4606         } else if (IS_VALLEYVIEW(dev_priv)) {
4607                 dev->driver->irq_handler = valleyview_irq_handler;
4608                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4609                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4610                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4611                 dev->driver->enable_vblank = valleyview_enable_vblank;
4612                 dev->driver->disable_vblank = valleyview_disable_vblank;
4613                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4614         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4615                 dev->driver->irq_handler = gen8_irq_handler;
4616                 dev->driver->irq_preinstall = gen8_irq_reset;
4617                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4618                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4619                 dev->driver->enable_vblank = gen8_enable_vblank;
4620                 dev->driver->disable_vblank = gen8_disable_vblank;
4621                 if (IS_BROXTON(dev))
4622                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4623                 else if (HAS_PCH_SPT(dev))
4624                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4625                 else
4626                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4627         } else if (HAS_PCH_SPLIT(dev)) {
4628                 dev->driver->irq_handler = ironlake_irq_handler;
4629                 dev->driver->irq_preinstall = ironlake_irq_reset;
4630                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4631                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4632                 dev->driver->enable_vblank = ironlake_enable_vblank;
4633                 dev->driver->disable_vblank = ironlake_disable_vblank;
4634                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4635         } else {
4636                 if (IS_GEN2(dev_priv)) {
4637                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4638                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4639                         dev->driver->irq_handler = i8xx_irq_handler;
4640                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4641                 } else if (IS_GEN3(dev_priv)) {
4642                         dev->driver->irq_preinstall = i915_irq_preinstall;
4643                         dev->driver->irq_postinstall = i915_irq_postinstall;
4644                         dev->driver->irq_uninstall = i915_irq_uninstall;
4645                         dev->driver->irq_handler = i915_irq_handler;
4646                 } else {
4647                         dev->driver->irq_preinstall = i965_irq_preinstall;
4648                         dev->driver->irq_postinstall = i965_irq_postinstall;
4649                         dev->driver->irq_uninstall = i965_irq_uninstall;
4650                         dev->driver->irq_handler = i965_irq_handler;
4651                 }
4652                 if (I915_HAS_HOTPLUG(dev_priv))
4653                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4654                 dev->driver->enable_vblank = i915_enable_vblank;
4655                 dev->driver->disable_vblank = i915_disable_vblank;
4656         }
4657 }
4658
4659 /**
4660  * intel_irq_install - enables the hardware interrupt
4661  * @dev_priv: i915 device instance
4662  *
4663  * This function enables the hardware interrupt handling, but leaves the hotplug
4664  * handling still disabled. It is called after intel_irq_init().
4665  *
4666  * In the driver load and resume code we need working interrupts in a few places
4667  * but don't want to deal with the hassle of concurrent probe and hotplug
4668  * workers. Hence the split into this two-stage approach.
4669  */
4670 int intel_irq_install(struct drm_i915_private *dev_priv)
4671 {
4672         /*
4673          * We enable some interrupt sources in our postinstall hooks, so mark
4674          * interrupts as enabled _before_ actually enabling them to avoid
4675          * special cases in our ordering checks.
4676          */
4677         dev_priv->pm.irqs_enabled = true;
4678
4679         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4680 }
4681
4682 /**
4683  * intel_irq_uninstall - finilizes all irq handling
4684  * @dev_priv: i915 device instance
4685  *
4686  * This stops interrupt and hotplug handling and unregisters and frees all
4687  * resources acquired in the init functions.
4688  */
4689 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4690 {
4691         drm_irq_uninstall(dev_priv->dev);
4692         intel_hpd_cancel_work(dev_priv);
4693         dev_priv->pm.irqs_enabled = false;
4694 }
4695
4696 /**
4697  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4698  * @dev_priv: i915 device instance
4699  *
4700  * This function is used to disable interrupts at runtime, both in the runtime
4701  * pm and the system suspend/resume code.
4702  */
4703 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4704 {
4705         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4706         dev_priv->pm.irqs_enabled = false;
4707         synchronize_irq(dev_priv->dev->irq);
4708 }
4709
4710 /**
4711  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4712  * @dev_priv: i915 device instance
4713  *
4714  * This function is used to enable interrupts at runtime, both in the runtime
4715  * pm and the system suspend/resume code.
4716  */
4717 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4718 {
4719         dev_priv->pm.irqs_enabled = true;
4720         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4721         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4722 }