drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 /* For display hotplug interrupt */
  40 static void
  41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  42 {
  43         if ((dev_priv->irq_mask & mask) != 0) {
  44                 dev_priv->irq_mask &= ~mask;
  45                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  46                 POSTING_READ(DEIMR);
  47         }
  48 }
  49
  50 static inline void
  51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  52 {
  53         if ((dev_priv->irq_mask & mask) != mask) {
  54                 dev_priv->irq_mask |= mask;
  55                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  56                 POSTING_READ(DEIMR);
  57         }
  58 }
  59
  60 void
  61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  62 {
  63         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  64                 u32 reg = PIPESTAT(pipe);
  65
  66                 dev_priv->pipestat[pipe] |= mask;
  67                 /* Enable the interrupt, clear any pending status */
  68                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  69                 POSTING_READ(reg);
  70         }
  71 }
  72
  73 void
  74 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  75 {
  76         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  77                 u32 reg = PIPESTAT(pipe);
  78
  79                 dev_priv->pipestat[pipe] &= ~mask;
  80                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  81                 POSTING_READ(reg);
  82         }
  83 }
  84
  85 /**
  86  * intel_enable_asle - enable ASLE interrupt for OpRegion
  87  */
  88 void intel_enable_asle(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         unsigned long irqflags;
  92
  93         /* FIXME: opregion/asle for VLV */
  94         if (IS_VALLEYVIEW(dev))
  95                 return;
  96
  97         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  98
  99         if (HAS_PCH_SPLIT(dev))
 100                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 101         else {
 102                 i915_enable_pipestat(dev_priv, 1,
 103                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 104                 if (INTEL_INFO(dev)->gen >= 4)
 105                         i915_enable_pipestat(dev_priv, 0,
 106                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 107         }
 108
 109         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 110 }
 111
 112 /**
 113  * i915_pipe_enabled - check if a pipe is enabled
 114  * @dev: DRM device
 115  * @pipe: pipe to check
 116  *
 117  * Reading certain registers when the pipe is disabled can hang the chip.
 118  * Use this routine to make sure the PLL is running and the pipe is active
 119  * before reading such registers if unsure.
 120  */
 121 static int
 122 i915_pipe_enabled(struct drm_device *dev, int pipe)
 123 {
 124         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 126                                                                       pipe);
 127
 128         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 129 }
 130
 131 /* Called from drm generic code, passed a 'crtc', which
 132  * we use as a pipe index
 133  */
 134 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 135 {
 136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 137         unsigned long high_frame;
 138         unsigned long low_frame;
 139         u32 high1, high2, low;
 140
 141         if (!i915_pipe_enabled(dev, pipe)) {
 142                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 143                                 "pipe %c\n", pipe_name(pipe));
 144                 return 0;
 145         }
 146
 147         high_frame = PIPEFRAME(pipe);
 148         low_frame = PIPEFRAMEPIXEL(pipe);
 149
 150         /*
 151          * High & low register fields aren't synchronized, so make sure
 152          * we get a low value that's stable across two reads of the high
 153          * register.
 154          */
 155         do {
 156                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 158                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 159         } while (high1 != high2);
 160
 161         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 162         low >>= PIPE_FRAME_LOW_SHIFT;
 163         return (high1 << 8) | low;
 164 }
 165
 166 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169         int reg = PIPE_FRMCOUNT_GM45(pipe);
 170
 171         if (!i915_pipe_enabled(dev, pipe)) {
 172                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 173                                  "pipe %c\n", pipe_name(pipe));
 174                 return 0;
 175         }
 176
 177         return I915_READ(reg);
 178 }
 179
 180 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 181                              int *vpos, int *hpos)
 182 {
 183         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 184         u32 vbl = 0, position = 0;
 185         int vbl_start, vbl_end, htotal, vtotal;
 186         bool in_vbl = true;
 187         int ret = 0;
 188         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 189                                                                       pipe);
 190
 191         if (!i915_pipe_enabled(dev, pipe)) {
 192                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 193                                  "pipe %c\n", pipe_name(pipe));
 194                 return 0;
 195         }
 196
 197         /* Get vtotal. */
 198         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 199
 200         if (INTEL_INFO(dev)->gen >= 4) {
 201                 /* No obvious pixelcount register. Only query vertical
 202                  * scanout position from Display scan line register.
 203                  */
 204                 position = I915_READ(PIPEDSL(pipe));
 205
 206                 /* Decode into vertical scanout position. Don't have
 207                  * horizontal scanout position.
 208                  */
 209                 *vpos = position & 0x1fff;
 210                 *hpos = 0;
 211         } else {
 212                 /* Have access to pixelcount since start of frame.
 213                  * We can split this into vertical and horizontal
 214                  * scanout position.
 215                  */
 216                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 217
 218                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 219                 *vpos = position / htotal;
 220                 *hpos = position - (*vpos * htotal);
 221         }
 222
 223         /* Query vblank area. */
 224         vbl = I915_READ(VBLANK(cpu_transcoder));
 225
 226         /* Test position against vblank region. */
 227         vbl_start = vbl & 0x1fff;
 228         vbl_end = (vbl >> 16) & 0x1fff;
 229
 230         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 231                 in_vbl = false;
 232
 233         /* Inside "upper part" of vblank area? Apply corrective offset: */
 234         if (in_vbl && (*vpos >= vbl_start))
 235                 *vpos = *vpos - vtotal;
 236
 237         /* Readouts valid? */
 238         if (vbl > 0)
 239                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 240
 241         /* In vblank? */
 242         if (in_vbl)
 243                 ret |= DRM_SCANOUTPOS_INVBL;
 244
 245         return ret;
 246 }
 247
 248 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 249                               int *max_error,
 250                               struct timeval *vblank_time,
 251                               unsigned flags)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct drm_crtc *crtc;
 255
 256         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 257                 DRM_ERROR("Invalid crtc %d\n", pipe);
 258                 return -EINVAL;
 259         }
 260
 261         /* Get drm_crtc to timestamp: */
 262         crtc = intel_get_crtc_for_pipe(dev, pipe);
 263         if (crtc == NULL) {
 264                 DRM_ERROR("Invalid crtc %d\n", pipe);
 265                 return -EINVAL;
 266         }
 267
 268         if (!crtc->enabled) {
 269                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 270                 return -EBUSY;
 271         }
 272
 273         /* Helper routine in DRM core does all the work: */
 274         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 275                                                      vblank_time, flags,
 276                                                      crtc);
 277 }
 278
 279 /*
 280  * Handle hotplug events outside the interrupt handler proper.
 281  */
 282 static void i915_hotplug_work_func(struct work_struct *work)
 283 {
 284         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 285                                                     hotplug_work);
 286         struct drm_device *dev = dev_priv->dev;
 287         struct drm_mode_config *mode_config = &dev->mode_config;
 288         struct intel_encoder *encoder;
 289
 290         /* HPD irq before everything is fully set up. */
 291         if (!dev_priv->enable_hotplug_processing)
 292                 return;
 293
 294         mutex_lock(&mode_config->mutex);
 295         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 296
 297         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 298                 if (encoder->hot_plug)
 299                         encoder->hot_plug(encoder);
 300
 301         mutex_unlock(&mode_config->mutex);
 302
 303         /* Just fire off a uevent and let userspace tell us what to do */
 304         drm_helper_hpd_irq_event(dev);
 305 }
 306
 307 /* defined intel_pm.c */
 308 extern spinlock_t mchdev_lock;
 309
 310 static void ironlake_handle_rps_change(struct drm_device *dev)
 311 {
 312         drm_i915_private_t *dev_priv = dev->dev_private;
 313         u32 busy_up, busy_down, max_avg, min_avg;
 314         u8 new_delay;
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&mchdev_lock, flags);
 318
 319         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 320
 321         new_delay = dev_priv->ips.cur_delay;
 322
 323         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 324         busy_up = I915_READ(RCPREVBSYTUPAVG);
 325         busy_down = I915_READ(RCPREVBSYTDNAVG);
 326         max_avg = I915_READ(RCBMAXAVG);
 327         min_avg = I915_READ(RCBMINAVG);
 328
 329         /* Handle RCS change request from hw */
 330         if (busy_up > max_avg) {
 331                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 332                         new_delay = dev_priv->ips.cur_delay - 1;
 333                 if (new_delay < dev_priv->ips.max_delay)
 334                         new_delay = dev_priv->ips.max_delay;
 335         } else if (busy_down < min_avg) {
 336                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 337                         new_delay = dev_priv->ips.cur_delay + 1;
 338                 if (new_delay > dev_priv->ips.min_delay)
 339                         new_delay = dev_priv->ips.min_delay;
 340         }
 341
 342         if (ironlake_set_drps(dev, new_delay))
 343                 dev_priv->ips.cur_delay = new_delay;
 344
 345         spin_unlock_irqrestore(&mchdev_lock, flags);
 346
 347         return;
 348 }
 349
 350 static void notify_ring(struct drm_device *dev,
 351                         struct intel_ring_buffer *ring)
 352 {
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354
 355         if (ring->obj == NULL)
 356                 return;
 357
 358         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 359
 360         wake_up_all(&ring->irq_queue);
 361         if (i915_enable_hangcheck) {
 362                 dev_priv->hangcheck_count = 0;
 363                 mod_timer(&dev_priv->hangcheck_timer,
 364                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 365         }
 366 }
 367
 368 static void gen6_pm_rps_work(struct work_struct *work)
 369 {
 370         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 371                                                     rps.work);
 372         u32 pm_iir, pm_imr;
 373         u8 new_delay;
 374
 375         spin_lock_irq(&dev_priv->rps.lock);
 376         pm_iir = dev_priv->rps.pm_iir;
 377         dev_priv->rps.pm_iir = 0;
 378         pm_imr = I915_READ(GEN6_PMIMR);
 379         I915_WRITE(GEN6_PMIMR, 0);
 380         spin_unlock_irq(&dev_priv->rps.lock);
 381
 382         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 383                 return;
 384
 385         mutex_lock(&dev_priv->rps.hw_lock);
 386
 387         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 388                 new_delay = dev_priv->rps.cur_delay + 1;
 389         else
 390                 new_delay = dev_priv->rps.cur_delay - 1;
 391
 392         /* sysfs frequency interfaces may have snuck in while servicing the
 393          * interrupt
 394          */
 395         if (!(new_delay > dev_priv->rps.max_delay ||
 396               new_delay < dev_priv->rps.min_delay)) {
 397                 gen6_set_rps(dev_priv->dev, new_delay);
 398         }
 399
 400         mutex_unlock(&dev_priv->rps.hw_lock);
 401 }
 402
 403
 404 /**
 405  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 406  * occurred.
 407  * @work: workqueue struct
 408  *
 409  * Doesn't actually do anything except notify userspace. As a consequence of
 410  * this event, userspace should try to remap the bad rows since statistically
 411  * it is likely the same row is more likely to go bad again.
 412  */
 413 static void ivybridge_parity_work(struct work_struct *work)
 414 {
 415         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 416                                                     l3_parity.error_work);
 417         u32 error_status, row, bank, subbank;
 418         char *parity_event[5];
 419         uint32_t misccpctl;
 420         unsigned long flags;
 421
 422         /* We must turn off DOP level clock gating to access the L3 registers.
 423          * In order to prevent a get/put style interface, acquire struct mutex
 424          * any time we access those registers.
 425          */
 426         mutex_lock(&dev_priv->dev->struct_mutex);
 427
 428         misccpctl = I915_READ(GEN7_MISCCPCTL);
 429         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 430         POSTING_READ(GEN7_MISCCPCTL);
 431
 432         error_status = I915_READ(GEN7_L3CDERRST1);
 433         row = GEN7_PARITY_ERROR_ROW(error_status);
 434         bank = GEN7_PARITY_ERROR_BANK(error_status);
 435         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 436
 437         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 438                                     GEN7_L3CDERRST1_ENABLE);
 439         POSTING_READ(GEN7_L3CDERRST1);
 440
 441         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 442
 443         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 444         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 445         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 446         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 447
 448         mutex_unlock(&dev_priv->dev->struct_mutex);
 449
 450         parity_event[0] = "L3_PARITY_ERROR=1";
 451         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 452         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 453         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 454         parity_event[4] = NULL;
 455
 456         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 457                            KOBJ_CHANGE, parity_event);
 458
 459         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 460                   row, bank, subbank);
 461
 462         kfree(parity_event[3]);
 463         kfree(parity_event[2]);
 464         kfree(parity_event[1]);
 465 }
 466
 467 static void ivybridge_handle_parity_error(struct drm_device *dev)
 468 {
 469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 470         unsigned long flags;
 471
 472         if (!HAS_L3_GPU_CACHE(dev))
 473                 return;
 474
 475         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 476         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 477         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 478         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 479
 480         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 481 }
 482
 483 static void snb_gt_irq_handler(struct drm_device *dev,
 484                                struct drm_i915_private *dev_priv,
 485                                u32 gt_iir)
 486 {
 487
 488         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 489                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 490                 notify_ring(dev, &dev_priv->ring[RCS]);
 491         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 492                 notify_ring(dev, &dev_priv->ring[VCS]);
 493         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 494                 notify_ring(dev, &dev_priv->ring[BCS]);
 495
 496         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 497                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 498                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 499                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 500                 i915_handle_error(dev, false);
 501         }
 502
 503         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 504                 ivybridge_handle_parity_error(dev);
 505 }
 506
 507 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 508                                 u32 pm_iir)
 509 {
 510         unsigned long flags;
 511
 512         /*
 513          * IIR bits should never already be set because IMR should
 514          * prevent an interrupt from being shown in IIR. The warning
 515          * displays a case where we've unsafely cleared
 516          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 517          * type is not a problem, it displays a problem in the logic.
 518          *
 519          * The mask bit in IMR is cleared by dev_priv->rps.work.
 520          */
 521
 522         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 523         dev_priv->rps.pm_iir |= pm_iir;
 524         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 525         POSTING_READ(GEN6_PMIMR);
 526         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 527
 528         queue_work(dev_priv->wq, &dev_priv->rps.work);
 529 }
 530
 531 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 532 {
 533         struct drm_device *dev = (struct drm_device *) arg;
 534         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 535         u32 iir, gt_iir, pm_iir;
 536         irqreturn_t ret = IRQ_NONE;
 537         unsigned long irqflags;
 538         int pipe;
 539         u32 pipe_stats[I915_MAX_PIPES];
 540         bool blc_event;
 541
 542         atomic_inc(&dev_priv->irq_received);
 543
 544         while (true) {
 545                 iir = I915_READ(VLV_IIR);
 546                 gt_iir = I915_READ(GTIIR);
 547                 pm_iir = I915_READ(GEN6_PMIIR);
 548
 549                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 550                         goto out;
 551
 552                 ret = IRQ_HANDLED;
 553
 554                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 555
 556                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 557                 for_each_pipe(pipe) {
 558                         int reg = PIPESTAT(pipe);
 559                         pipe_stats[pipe] = I915_READ(reg);
 560
 561                         /*
 562                          * Clear the PIPE*STAT regs before the IIR
 563                          */
 564                         if (pipe_stats[pipe] & 0x8000ffff) {
 565                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 566                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 567                                                          pipe_name(pipe));
 568                                 I915_WRITE(reg, pipe_stats[pipe]);
 569                         }
 570                 }
 571                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 572
 573                 for_each_pipe(pipe) {
 574                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 575                                 drm_handle_vblank(dev, pipe);
 576
 577                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 578                                 intel_prepare_page_flip(dev, pipe);
 579                                 intel_finish_page_flip(dev, pipe);
 580                         }
 581                 }
 582
 583                 /* Consume port.  Then clear IIR or we'll miss events */
 584                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 585                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 586
 587                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 588                                          hotplug_status);
 589                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 590                                 queue_work(dev_priv->wq,
 591                                            &dev_priv->hotplug_work);
 592
 593                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 594                         I915_READ(PORT_HOTPLUG_STAT);
 595                 }
 596
 597                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 598                         blc_event = true;
 599
 600                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 601                         gen6_queue_rps_work(dev_priv, pm_iir);
 602
 603                 I915_WRITE(GTIIR, gt_iir);
 604                 I915_WRITE(GEN6_PMIIR, pm_iir);
 605                 I915_WRITE(VLV_IIR, iir);
 606         }
 607
 608 out:
 609         return ret;
 610 }
 611
 612 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 613 {
 614         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 615         int pipe;
 616
 617         if (pch_iir & SDE_HOTPLUG_MASK)
 618                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 619
 620         if (pch_iir & SDE_AUDIO_POWER_MASK)
 621                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 622                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 623                                  SDE_AUDIO_POWER_SHIFT);
 624
 625         if (pch_iir & SDE_GMBUS)
 626                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 627
 628         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 629                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 630
 631         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 632                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 633
 634         if (pch_iir & SDE_POISON)
 635                 DRM_ERROR("PCH poison interrupt\n");
 636
 637         if (pch_iir & SDE_FDI_MASK)
 638                 for_each_pipe(pipe)
 639                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 640                                          pipe_name(pipe),
 641                                          I915_READ(FDI_RX_IIR(pipe)));
 642
 643         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 644                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 645
 646         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 647                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 648
 649         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 650                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 651         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 652                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 653 }
 654
 655 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 656 {
 657         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 658         int pipe;
 659
 660         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 661                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 662
 663         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 664                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 665                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 666                                  SDE_AUDIO_POWER_SHIFT_CPT);
 667
 668         if (pch_iir & SDE_AUX_MASK_CPT)
 669                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 670
 671         if (pch_iir & SDE_GMBUS_CPT)
 672                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 673
 674         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 675                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 676
 677         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 678                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 679
 680         if (pch_iir & SDE_FDI_MASK_CPT)
 681                 for_each_pipe(pipe)
 682                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 683                                          pipe_name(pipe),
 684                                          I915_READ(FDI_RX_IIR(pipe)));
 685 }
 686
 687 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 688 {
 689         struct drm_device *dev = (struct drm_device *) arg;
 690         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 691         u32 de_iir, gt_iir, de_ier, pm_iir;
 692         irqreturn_t ret = IRQ_NONE;
 693         int i;
 694
 695         atomic_inc(&dev_priv->irq_received);
 696
 697         /* disable master interrupt before clearing iir  */
 698         de_ier = I915_READ(DEIER);
 699         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 700
 701         gt_iir = I915_READ(GTIIR);
 702         if (gt_iir) {
 703                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 704                 I915_WRITE(GTIIR, gt_iir);
 705                 ret = IRQ_HANDLED;
 706         }
 707
 708         de_iir = I915_READ(DEIIR);
 709         if (de_iir) {
 710                 if (de_iir & DE_GSE_IVB)
 711                         intel_opregion_gse_intr(dev);
 712
 713                 for (i = 0; i < 3; i++) {
 714                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 715                                 drm_handle_vblank(dev, i);
 716                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 717                                 intel_prepare_page_flip(dev, i);
 718                                 intel_finish_page_flip_plane(dev, i);
 719                         }
 720                 }
 721
 722                 /* check event from PCH */
 723                 if (de_iir & DE_PCH_EVENT_IVB) {
 724                         u32 pch_iir = I915_READ(SDEIIR);
 725
 726                         cpt_irq_handler(dev, pch_iir);
 727
 728                         /* clear PCH hotplug event before clear CPU irq */
 729                         I915_WRITE(SDEIIR, pch_iir);
 730                 }
 731
 732                 I915_WRITE(DEIIR, de_iir);
 733                 ret = IRQ_HANDLED;
 734         }
 735
 736         pm_iir = I915_READ(GEN6_PMIIR);
 737         if (pm_iir) {
 738                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 739                         gen6_queue_rps_work(dev_priv, pm_iir);
 740                 I915_WRITE(GEN6_PMIIR, pm_iir);
 741                 ret = IRQ_HANDLED;
 742         }
 743
 744         I915_WRITE(DEIER, de_ier);
 745         POSTING_READ(DEIER);
 746
 747         return ret;
 748 }
 749
 750 static void ilk_gt_irq_handler(struct drm_device *dev,
 751                                struct drm_i915_private *dev_priv,
 752                                u32 gt_iir)
 753 {
 754         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 755                 notify_ring(dev, &dev_priv->ring[RCS]);
 756         if (gt_iir & GT_BSD_USER_INTERRUPT)
 757                 notify_ring(dev, &dev_priv->ring[VCS]);
 758 }
 759
 760 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 761 {
 762         struct drm_device *dev = (struct drm_device *) arg;
 763         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 764         int ret = IRQ_NONE;
 765         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 766
 767         atomic_inc(&dev_priv->irq_received);
 768
 769         /* disable master interrupt before clearing iir  */
 770         de_ier = I915_READ(DEIER);
 771         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 772         POSTING_READ(DEIER);
 773
 774         de_iir = I915_READ(DEIIR);
 775         gt_iir = I915_READ(GTIIR);
 776         pch_iir = I915_READ(SDEIIR);
 777         pm_iir = I915_READ(GEN6_PMIIR);
 778
 779         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 780             (!IS_GEN6(dev) || pm_iir == 0))
 781                 goto done;
 782
 783         ret = IRQ_HANDLED;
 784
 785         if (IS_GEN5(dev))
 786                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 787         else
 788                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 789
 790         if (de_iir & DE_GSE)
 791                 intel_opregion_gse_intr(dev);
 792
 793         if (de_iir & DE_PIPEA_VBLANK)
 794                 drm_handle_vblank(dev, 0);
 795
 796         if (de_iir & DE_PIPEB_VBLANK)
 797                 drm_handle_vblank(dev, 1);
 798
 799         if (de_iir & DE_PLANEA_FLIP_DONE) {
 800                 intel_prepare_page_flip(dev, 0);
 801                 intel_finish_page_flip_plane(dev, 0);
 802         }
 803
 804         if (de_iir & DE_PLANEB_FLIP_DONE) {
 805                 intel_prepare_page_flip(dev, 1);
 806                 intel_finish_page_flip_plane(dev, 1);
 807         }
 808
 809         /* check event from PCH */
 810         if (de_iir & DE_PCH_EVENT) {
 811                 if (HAS_PCH_CPT(dev))
 812                         cpt_irq_handler(dev, pch_iir);
 813                 else
 814                         ibx_irq_handler(dev, pch_iir);
 815         }
 816
 817         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 818                 ironlake_handle_rps_change(dev);
 819
 820         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 821                 gen6_queue_rps_work(dev_priv, pm_iir);
 822
 823         /* should clear PCH hotplug event before clear CPU irq */
 824         I915_WRITE(SDEIIR, pch_iir);
 825         I915_WRITE(GTIIR, gt_iir);
 826         I915_WRITE(DEIIR, de_iir);
 827         I915_WRITE(GEN6_PMIIR, pm_iir);
 828
 829 done:
 830         I915_WRITE(DEIER, de_ier);
 831         POSTING_READ(DEIER);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * i915_error_work_func - do process context error handling work
 838  * @work: work struct
 839  *
 840  * Fire an error uevent so userspace can see that a hang or error
 841  * was detected.
 842  */
 843 static void i915_error_work_func(struct work_struct *work)
 844 {
 845         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 846                                                     error_work);
 847         struct drm_device *dev = dev_priv->dev;
 848         char *error_event[] = { "ERROR=1", NULL };
 849         char *reset_event[] = { "RESET=1", NULL };
 850         char *reset_done_event[] = { "ERROR=0", NULL };
 851
 852         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 853
 854         if (atomic_read(&dev_priv->mm.wedged)) {
 855                 DRM_DEBUG_DRIVER("resetting chip\n");
 856                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 857                 if (!i915_reset(dev)) {
 858                         atomic_set(&dev_priv->mm.wedged, 0);
 859                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 860                 }
 861                 complete_all(&dev_priv->error_completion);
 862         }
 863 }
 864
 865 /* NB: please notice the memset */
 866 static void i915_get_extra_instdone(struct drm_device *dev,
 867                                     uint32_t *instdone)
 868 {
 869         struct drm_i915_private *dev_priv = dev->dev_private;
 870         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 871
 872         switch(INTEL_INFO(dev)->gen) {
 873         case 2:
 874         case 3:
 875                 instdone[0] = I915_READ(INSTDONE);
 876                 break;
 877         case 4:
 878         case 5:
 879         case 6:
 880                 instdone[0] = I915_READ(INSTDONE_I965);
 881                 instdone[1] = I915_READ(INSTDONE1);
 882                 break;
 883         default:
 884                 WARN_ONCE(1, "Unsupported platform\n");
 885         case 7:
 886                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 887                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 888                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 889                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 890                 break;
 891         }
 892 }
 893
 894 #ifdef CONFIG_DEBUG_FS
 895 static struct drm_i915_error_object *
 896 i915_error_object_create(struct drm_i915_private *dev_priv,
 897                          struct drm_i915_gem_object *src)
 898 {
 899         struct drm_i915_error_object *dst;
 900         int i, count;
 901         u32 reloc_offset;
 902
 903         if (src == NULL || src->pages == NULL)
 904                 return NULL;
 905
 906         count = src->base.size / PAGE_SIZE;
 907
 908         dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 909         if (dst == NULL)
 910                 return NULL;
 911
 912         reloc_offset = src->gtt_offset;
 913         for (i = 0; i < count; i++) {
 914                 unsigned long flags;
 915                 void *d;
 916
 917                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 918                 if (d == NULL)
 919                         goto unwind;
 920
 921                 local_irq_save(flags);
 922                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 923                     src->has_global_gtt_mapping) {
 924                         void __iomem *s;
 925
 926                         /* Simply ignore tiling or any overlapping fence.
 927                          * It's part of the error state, and this hopefully
 928                          * captures what the GPU read.
 929                          */
 930
 931                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 932                                                      reloc_offset);
 933                         memcpy_fromio(d, s, PAGE_SIZE);
 934                         io_mapping_unmap_atomic(s);
 935                 } else {
 936                         struct page *page;
 937                         void *s;
 938
 939                         page = i915_gem_object_get_page(src, i);
 940
 941                         drm_clflush_pages(&page, 1);
 942
 943                         s = kmap_atomic(page);
 944                         memcpy(d, s, PAGE_SIZE);
 945                         kunmap_atomic(s);
 946
 947                         drm_clflush_pages(&page, 1);
 948                 }
 949                 local_irq_restore(flags);
 950
 951                 dst->pages[i] = d;
 952
 953                 reloc_offset += PAGE_SIZE;
 954         }
 955         dst->page_count = count;
 956         dst->gtt_offset = src->gtt_offset;
 957
 958         return dst;
 959
 960 unwind:
 961         while (i--)
 962                 kfree(dst->pages[i]);
 963         kfree(dst);
 964         return NULL;
 965 }
 966
 967 static void
 968 i915_error_object_free(struct drm_i915_error_object *obj)
 969 {
 970         int page;
 971
 972         if (obj == NULL)
 973                 return;
 974
 975         for (page = 0; page < obj->page_count; page++)
 976                 kfree(obj->pages[page]);
 977
 978         kfree(obj);
 979 }
 980
 981 void
 982 i915_error_state_free(struct kref *error_ref)
 983 {
 984         struct drm_i915_error_state *error = container_of(error_ref,
 985                                                           typeof(*error), ref);
 986         int i;
 987
 988         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 989                 i915_error_object_free(error->ring[i].batchbuffer);
 990                 i915_error_object_free(error->ring[i].ringbuffer);
 991                 kfree(error->ring[i].requests);
 992         }
 993
 994         kfree(error->active_bo);
 995         kfree(error->overlay);
 996         kfree(error);
 997 }
 998 static void capture_bo(struct drm_i915_error_buffer *err,
 999                        struct drm_i915_gem_object *obj)
1000 {
1001         err->size = obj->base.size;
1002         err->name = obj->base.name;
1003         err->rseqno = obj->last_read_seqno;
1004         err->wseqno = obj->last_write_seqno;
1005         err->gtt_offset = obj->gtt_offset;
1006         err->read_domains = obj->base.read_domains;
1007         err->write_domain = obj->base.write_domain;
1008         err->fence_reg = obj->fence_reg;
1009         err->pinned = 0;
1010         if (obj->pin_count > 0)
1011                 err->pinned = 1;
1012         if (obj->user_pin_count > 0)
1013                 err->pinned = -1;
1014         err->tiling = obj->tiling_mode;
1015         err->dirty = obj->dirty;
1016         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1017         err->ring = obj->ring ? obj->ring->id : -1;
1018         err->cache_level = obj->cache_level;
1019 }
1020
1021 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1022                              int count, struct list_head *head)
1023 {
1024         struct drm_i915_gem_object *obj;
1025         int i = 0;
1026
1027         list_for_each_entry(obj, head, mm_list) {
1028                 capture_bo(err++, obj);
1029                 if (++i == count)
1030                         break;
1031         }
1032
1033         return i;
1034 }
1035
1036 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1037                              int count, struct list_head *head)
1038 {
1039         struct drm_i915_gem_object *obj;
1040         int i = 0;
1041
1042         list_for_each_entry(obj, head, gtt_list) {
1043                 if (obj->pin_count == 0)
1044                         continue;
1045
1046                 capture_bo(err++, obj);
1047                 if (++i == count)
1048                         break;
1049         }
1050
1051         return i;
1052 }
1053
1054 static void i915_gem_record_fences(struct drm_device *dev,
1055                                    struct drm_i915_error_state *error)
1056 {
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         int i;
1059
1060         /* Fences */
1061         switch (INTEL_INFO(dev)->gen) {
1062         case 7:
1063         case 6:
1064                 for (i = 0; i < 16; i++)
1065                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1066                 break;
1067         case 5:
1068         case 4:
1069                 for (i = 0; i < 16; i++)
1070                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1071                 break;
1072         case 3:
1073                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1074                         for (i = 0; i < 8; i++)
1075                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1076         case 2:
1077                 for (i = 0; i < 8; i++)
1078                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1079                 break;
1080
1081         }
1082 }
1083
1084 static struct drm_i915_error_object *
1085 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1086                              struct intel_ring_buffer *ring)
1087 {
1088         struct drm_i915_gem_object *obj;
1089         u32 seqno;
1090
1091         if (!ring->get_seqno)
1092                 return NULL;
1093
1094         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1095                 u32 acthd = I915_READ(ACTHD);
1096
1097                 if (WARN_ON(ring->id != RCS))
1098                         return NULL;
1099
1100                 obj = ring->private;
1101                 if (acthd >= obj->gtt_offset &&
1102                     acthd < obj->gtt_offset + obj->base.size)
1103                         return i915_error_object_create(dev_priv, obj);
1104         }
1105
1106         seqno = ring->get_seqno(ring, false);
1107         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1108                 if (obj->ring != ring)
1109                         continue;
1110
1111                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1112                         continue;
1113
1114                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1115                         continue;
1116
1117                 /* We need to copy these to an anonymous buffer as the simplest
1118                  * method to avoid being overwritten by userspace.
1119                  */
1120                 return i915_error_object_create(dev_priv, obj);
1121         }
1122
1123         return NULL;
1124 }
1125
1126 static void i915_record_ring_state(struct drm_device *dev,
1127                                    struct drm_i915_error_state *error,
1128                                    struct intel_ring_buffer *ring)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         if (INTEL_INFO(dev)->gen >= 6) {
1133                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1134                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1135                 error->semaphore_mboxes[ring->id][0]
1136                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1137                 error->semaphore_mboxes[ring->id][1]
1138                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1139                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1140                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1141         }
1142
1143         if (INTEL_INFO(dev)->gen >= 4) {
1144                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1145                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1146                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1147                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1148                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1149                 if (ring->id == RCS)
1150                         error->bbaddr = I915_READ64(BB_ADDR);
1151         } else {
1152                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1153                 error->ipeir[ring->id] = I915_READ(IPEIR);
1154                 error->ipehr[ring->id] = I915_READ(IPEHR);
1155                 error->instdone[ring->id] = I915_READ(INSTDONE);
1156         }
1157
1158         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1159         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1160         error->seqno[ring->id] = ring->get_seqno(ring, false);
1161         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1162         error->head[ring->id] = I915_READ_HEAD(ring);
1163         error->tail[ring->id] = I915_READ_TAIL(ring);
1164         error->ctl[ring->id] = I915_READ_CTL(ring);
1165
1166         error->cpu_ring_head[ring->id] = ring->head;
1167         error->cpu_ring_tail[ring->id] = ring->tail;
1168 }
1169
1170 static void i915_gem_record_rings(struct drm_device *dev,
1171                                   struct drm_i915_error_state *error)
1172 {
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         struct intel_ring_buffer *ring;
1175         struct drm_i915_gem_request *request;
1176         int i, count;
1177
1178         for_each_ring(ring, dev_priv, i) {
1179                 i915_record_ring_state(dev, error, ring);
1180
1181                 error->ring[i].batchbuffer =
1182                         i915_error_first_batchbuffer(dev_priv, ring);
1183
1184                 error->ring[i].ringbuffer =
1185                         i915_error_object_create(dev_priv, ring->obj);
1186
1187                 count = 0;
1188                 list_for_each_entry(request, &ring->request_list, list)
1189                         count++;
1190
1191                 error->ring[i].num_requests = count;
1192                 error->ring[i].requests =
1193                         kmalloc(count*sizeof(struct drm_i915_error_request),
1194                                 GFP_ATOMIC);
1195                 if (error->ring[i].requests == NULL) {
1196                         error->ring[i].num_requests = 0;
1197                         continue;
1198                 }
1199
1200                 count = 0;
1201                 list_for_each_entry(request, &ring->request_list, list) {
1202                         struct drm_i915_error_request *erq;
1203
1204                         erq = &error->ring[i].requests[count++];
1205                         erq->seqno = request->seqno;
1206                         erq->jiffies = request->emitted_jiffies;
1207                         erq->tail = request->tail;
1208                 }
1209         }
1210 }
1211
1212 /**
1213  * i915_capture_error_state - capture an error record for later analysis
1214  * @dev: drm device
1215  *
1216  * Should be called when an error is detected (either a hang or an error
1217  * interrupt) to capture error state from the time of the error.  Fills
1218  * out a structure which becomes available in debugfs for user level tools
1219  * to pick up.
1220  */
1221 static void i915_capture_error_state(struct drm_device *dev)
1222 {
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         struct drm_i915_gem_object *obj;
1225         struct drm_i915_error_state *error;
1226         unsigned long flags;
1227         int i, pipe;
1228
1229         spin_lock_irqsave(&dev_priv->error_lock, flags);
1230         error = dev_priv->first_error;
1231         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1232         if (error)
1233                 return;
1234
1235         /* Account for pipe specific data like PIPE*STAT */
1236         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1237         if (!error) {
1238                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1239                 return;
1240         }
1241
1242         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1243                  dev->primary->index);
1244
1245         kref_init(&error->ref);
1246         error->eir = I915_READ(EIR);
1247         error->pgtbl_er = I915_READ(PGTBL_ER);
1248         error->ccid = I915_READ(CCID);
1249
1250         if (HAS_PCH_SPLIT(dev))
1251                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1252         else if (IS_VALLEYVIEW(dev))
1253                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1254         else if (IS_GEN2(dev))
1255                 error->ier = I915_READ16(IER);
1256         else
1257                 error->ier = I915_READ(IER);
1258
1259         if (INTEL_INFO(dev)->gen >= 6)
1260                 error->derrmr = I915_READ(DERRMR);
1261
1262         if (IS_VALLEYVIEW(dev))
1263                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1264         else if (INTEL_INFO(dev)->gen >= 7)
1265                 error->forcewake = I915_READ(FORCEWAKE_MT);
1266         else if (INTEL_INFO(dev)->gen == 6)
1267                 error->forcewake = I915_READ(FORCEWAKE);
1268
1269         for_each_pipe(pipe)
1270                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1271
1272         if (INTEL_INFO(dev)->gen >= 6) {
1273                 error->error = I915_READ(ERROR_GEN6);
1274                 error->done_reg = I915_READ(DONE_REG);
1275         }
1276
1277         if (INTEL_INFO(dev)->gen == 7)
1278                 error->err_int = I915_READ(GEN7_ERR_INT);
1279
1280         i915_get_extra_instdone(dev, error->extra_instdone);
1281
1282         i915_gem_record_fences(dev, error);
1283         i915_gem_record_rings(dev, error);
1284
1285         /* Record buffers on the active and pinned lists. */
1286         error->active_bo = NULL;
1287         error->pinned_bo = NULL;
1288
1289         i = 0;
1290         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1291                 i++;
1292         error->active_bo_count = i;
1293         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1294                 if (obj->pin_count)
1295                         i++;
1296         error->pinned_bo_count = i - error->active_bo_count;
1297
1298         error->active_bo = NULL;
1299         error->pinned_bo = NULL;
1300         if (i) {
1301                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1302                                            GFP_ATOMIC);
1303                 if (error->active_bo)
1304                         error->pinned_bo =
1305                                 error->active_bo + error->active_bo_count;
1306         }
1307
1308         if (error->active_bo)
1309                 error->active_bo_count =
1310                         capture_active_bo(error->active_bo,
1311                                           error->active_bo_count,
1312                                           &dev_priv->mm.active_list);
1313
1314         if (error->pinned_bo)
1315                 error->pinned_bo_count =
1316                         capture_pinned_bo(error->pinned_bo,
1317                                           error->pinned_bo_count,
1318                                           &dev_priv->mm.bound_list);
1319
1320         do_gettimeofday(&error->time);
1321
1322         error->overlay = intel_overlay_capture_error_state(dev);
1323         error->display = intel_display_capture_error_state(dev);
1324
1325         spin_lock_irqsave(&dev_priv->error_lock, flags);
1326         if (dev_priv->first_error == NULL) {
1327                 dev_priv->first_error = error;
1328                 error = NULL;
1329         }
1330         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1331
1332         if (error)
1333                 i915_error_state_free(&error->ref);
1334 }
1335
1336 void i915_destroy_error_state(struct drm_device *dev)
1337 {
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         struct drm_i915_error_state *error;
1340         unsigned long flags;
1341
1342         spin_lock_irqsave(&dev_priv->error_lock, flags);
1343         error = dev_priv->first_error;
1344         dev_priv->first_error = NULL;
1345         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1346
1347         if (error)
1348                 kref_put(&error->ref, i915_error_state_free);
1349 }
1350 #else
1351 #define i915_capture_error_state(x)
1352 #endif
1353
1354 static void i915_report_and_clear_eir(struct drm_device *dev)
1355 {
1356         struct drm_i915_private *dev_priv = dev->dev_private;
1357         uint32_t instdone[I915_NUM_INSTDONE_REG];
1358         u32 eir = I915_READ(EIR);
1359         int pipe, i;
1360
1361         if (!eir)
1362                 return;
1363
1364         pr_err("render error detected, EIR: 0x%08x\n", eir);
1365
1366         i915_get_extra_instdone(dev, instdone);
1367
1368         if (IS_G4X(dev)) {
1369                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1370                         u32 ipeir = I915_READ(IPEIR_I965);
1371
1372                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1373                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1374                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1375                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1376                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1377                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1378                         I915_WRITE(IPEIR_I965, ipeir);
1379                         POSTING_READ(IPEIR_I965);
1380                 }
1381                 if (eir & GM45_ERROR_PAGE_TABLE) {
1382                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1383                         pr_err("page table error\n");
1384                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1385                         I915_WRITE(PGTBL_ER, pgtbl_err);
1386                         POSTING_READ(PGTBL_ER);
1387                 }
1388         }
1389
1390         if (!IS_GEN2(dev)) {
1391                 if (eir & I915_ERROR_PAGE_TABLE) {
1392                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1393                         pr_err("page table error\n");
1394                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1395                         I915_WRITE(PGTBL_ER, pgtbl_err);
1396                         POSTING_READ(PGTBL_ER);
1397                 }
1398         }
1399
1400         if (eir & I915_ERROR_MEMORY_REFRESH) {
1401                 pr_err("memory refresh error:\n");
1402                 for_each_pipe(pipe)
1403                         pr_err("pipe %c stat: 0x%08x\n",
1404                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1405                 /* pipestat has already been acked */
1406         }
1407         if (eir & I915_ERROR_INSTRUCTION) {
1408                 pr_err("instruction error\n");
1409                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1410                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1411                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1412                 if (INTEL_INFO(dev)->gen < 4) {
1413                         u32 ipeir = I915_READ(IPEIR);
1414
1415                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1416                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1417                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1418                         I915_WRITE(IPEIR, ipeir);
1419                         POSTING_READ(IPEIR);
1420                 } else {
1421                         u32 ipeir = I915_READ(IPEIR_I965);
1422
1423                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1424                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1425                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1426                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1427                         I915_WRITE(IPEIR_I965, ipeir);
1428                         POSTING_READ(IPEIR_I965);
1429                 }
1430         }
1431
1432         I915_WRITE(EIR, eir);
1433         POSTING_READ(EIR);
1434         eir = I915_READ(EIR);
1435         if (eir) {
1436                 /*
1437                  * some errors might have become stuck,
1438                  * mask them.
1439                  */
1440                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1441                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1442                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1443         }
1444 }
1445
1446 /**
1447  * i915_handle_error - handle an error interrupt
1448  * @dev: drm device
1449  *
1450  * Do some basic checking of regsiter state at error interrupt time and
1451  * dump it to the syslog.  Also call i915_capture_error_state() to make
1452  * sure we get a record and make it available in debugfs.  Fire a uevent
1453  * so userspace knows something bad happened (should trigger collection
1454  * of a ring dump etc.).
1455  */
1456 void i915_handle_error(struct drm_device *dev, bool wedged)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459         struct intel_ring_buffer *ring;
1460         int i;
1461
1462         i915_capture_error_state(dev);
1463         i915_report_and_clear_eir(dev);
1464
1465         if (wedged) {
1466                 INIT_COMPLETION(dev_priv->error_completion);
1467                 atomic_set(&dev_priv->mm.wedged, 1);
1468
1469                 /*
1470                  * Wakeup waiting processes so they don't hang
1471                  */
1472                 for_each_ring(ring, dev_priv, i)
1473                         wake_up_all(&ring->irq_queue);
1474         }
1475
1476         queue_work(dev_priv->wq, &dev_priv->error_work);
1477 }
1478
1479 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1480 {
1481         drm_i915_private_t *dev_priv = dev->dev_private;
1482         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1484         struct drm_i915_gem_object *obj;
1485         struct intel_unpin_work *work;
1486         unsigned long flags;
1487         bool stall_detected;
1488
1489         /* Ignore early vblank irqs */
1490         if (intel_crtc == NULL)
1491                 return;
1492
1493         spin_lock_irqsave(&dev->event_lock, flags);
1494         work = intel_crtc->unpin_work;
1495
1496         if (work == NULL ||
1497             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1498             !work->enable_stall_check) {
1499                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1500                 spin_unlock_irqrestore(&dev->event_lock, flags);
1501                 return;
1502         }
1503
1504         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1505         obj = work->pending_flip_obj;
1506         if (INTEL_INFO(dev)->gen >= 4) {
1507                 int dspsurf = DSPSURF(intel_crtc->plane);
1508                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1509                                         obj->gtt_offset;
1510         } else {
1511                 int dspaddr = DSPADDR(intel_crtc->plane);
1512                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1513                                                         crtc->y * crtc->fb->pitches[0] +
1514                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1515         }
1516
1517         spin_unlock_irqrestore(&dev->event_lock, flags);
1518
1519         if (stall_detected) {
1520                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1521                 intel_prepare_page_flip(dev, intel_crtc->plane);
1522         }
1523 }
1524
1525 /* Called from drm generic code, passed 'crtc' which
1526  * we use as a pipe index
1527  */
1528 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1529 {
1530         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1531         unsigned long irqflags;
1532
1533         if (!i915_pipe_enabled(dev, pipe))
1534                 return -EINVAL;
1535
1536         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1537         if (INTEL_INFO(dev)->gen >= 4)
1538                 i915_enable_pipestat(dev_priv, pipe,
1539                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1540         else
1541                 i915_enable_pipestat(dev_priv, pipe,
1542                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1543
1544         /* maintain vblank delivery even in deep C-states */
1545         if (dev_priv->info->gen == 3)
1546                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1547         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1548
1549         return 0;
1550 }
1551
1552 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1553 {
1554         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1555         unsigned long irqflags;
1556
1557         if (!i915_pipe_enabled(dev, pipe))
1558                 return -EINVAL;
1559
1560         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1561         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1562                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1563         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1564
1565         return 0;
1566 }
1567
1568 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1569 {
1570         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1571         unsigned long irqflags;
1572
1573         if (!i915_pipe_enabled(dev, pipe))
1574                 return -EINVAL;
1575
1576         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1577         ironlake_enable_display_irq(dev_priv,
1578                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1579         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1580
1581         return 0;
1582 }
1583
1584 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1585 {
1586         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1587         unsigned long irqflags;
1588         u32 imr;
1589
1590         if (!i915_pipe_enabled(dev, pipe))
1591                 return -EINVAL;
1592
1593         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1594         imr = I915_READ(VLV_IMR);
1595         if (pipe == 0)
1596                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1597         else
1598                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1599         I915_WRITE(VLV_IMR, imr);
1600         i915_enable_pipestat(dev_priv, pipe,
1601                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1602         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1603
1604         return 0;
1605 }
1606
1607 /* Called from drm generic code, passed 'crtc' which
1608  * we use as a pipe index
1609  */
1610 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1611 {
1612         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1613         unsigned long irqflags;
1614
1615         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1616         if (dev_priv->info->gen == 3)
1617                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1618
1619         i915_disable_pipestat(dev_priv, pipe,
1620                               PIPE_VBLANK_INTERRUPT_ENABLE |
1621                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1622         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1623 }
1624
1625 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1626 {
1627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1628         unsigned long irqflags;
1629
1630         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1631         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1632                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1633         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1634 }
1635
1636 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1637 {
1638         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1639         unsigned long irqflags;
1640
1641         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1642         ironlake_disable_display_irq(dev_priv,
1643                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1644         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1645 }
1646
1647 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1648 {
1649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1650         unsigned long irqflags;
1651         u32 imr;
1652
1653         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1654         i915_disable_pipestat(dev_priv, pipe,
1655                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1656         imr = I915_READ(VLV_IMR);
1657         if (pipe == 0)
1658                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1659         else
1660                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1661         I915_WRITE(VLV_IMR, imr);
1662         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1663 }
1664
1665 static u32
1666 ring_last_seqno(struct intel_ring_buffer *ring)
1667 {
1668         return list_entry(ring->request_list.prev,
1669                           struct drm_i915_gem_request, list)->seqno;
1670 }
1671
1672 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1673 {
1674         if (list_empty(&ring->request_list) ||
1675             i915_seqno_passed(ring->get_seqno(ring, false),
1676                               ring_last_seqno(ring))) {
1677                 /* Issue a wake-up to catch stuck h/w. */
1678                 if (waitqueue_active(&ring->irq_queue)) {
1679                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1680                                   ring->name);
1681                         wake_up_all(&ring->irq_queue);
1682                         *err = true;
1683                 }
1684                 return true;
1685         }
1686         return false;
1687 }
1688
1689 static bool kick_ring(struct intel_ring_buffer *ring)
1690 {
1691         struct drm_device *dev = ring->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         u32 tmp = I915_READ_CTL(ring);
1694         if (tmp & RING_WAIT) {
1695                 DRM_ERROR("Kicking stuck wait on %s\n",
1696                           ring->name);
1697                 I915_WRITE_CTL(ring, tmp);
1698                 return true;
1699         }
1700         return false;
1701 }
1702
1703 static bool i915_hangcheck_hung(struct drm_device *dev)
1704 {
1705         drm_i915_private_t *dev_priv = dev->dev_private;
1706
1707         if (dev_priv->hangcheck_count++ > 1) {
1708                 bool hung = true;
1709
1710                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1711                 i915_handle_error(dev, true);
1712
1713                 if (!IS_GEN2(dev)) {
1714                         struct intel_ring_buffer *ring;
1715                         int i;
1716
1717                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1718                          * If so we can simply poke the RB_WAIT bit
1719                          * and break the hang. This should work on
1720                          * all but the second generation chipsets.
1721                          */
1722                         for_each_ring(ring, dev_priv, i)
1723                                 hung &= !kick_ring(ring);
1724                 }
1725
1726                 return hung;
1727         }
1728
1729         return false;
1730 }
1731
1732 /**
1733  * This is called when the chip hasn't reported back with completed
1734  * batchbuffers in a long time. The first time this is called we simply record
1735  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1736  * again, we assume the chip is wedged and try to fix it.
1737  */
1738 void i915_hangcheck_elapsed(unsigned long data)
1739 {
1740         struct drm_device *dev = (struct drm_device *)data;
1741         drm_i915_private_t *dev_priv = dev->dev_private;
1742         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1743         struct intel_ring_buffer *ring;
1744         bool err = false, idle;
1745         int i;
1746
1747         if (!i915_enable_hangcheck)
1748                 return;
1749
1750         memset(acthd, 0, sizeof(acthd));
1751         idle = true;
1752         for_each_ring(ring, dev_priv, i) {
1753             idle &= i915_hangcheck_ring_idle(ring, &err);
1754             acthd[i] = intel_ring_get_active_head(ring);
1755         }
1756
1757         /* If all work is done then ACTHD clearly hasn't advanced. */
1758         if (idle) {
1759                 if (err) {
1760                         if (i915_hangcheck_hung(dev))
1761                                 return;
1762
1763                         goto repeat;
1764                 }
1765
1766                 dev_priv->hangcheck_count = 0;
1767                 return;
1768         }
1769
1770         i915_get_extra_instdone(dev, instdone);
1771         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1772             memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
1773                 if (i915_hangcheck_hung(dev))
1774                         return;
1775         } else {
1776                 dev_priv->hangcheck_count = 0;
1777
1778                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1779                 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
1780         }
1781
1782 repeat:
1783         /* Reset timer case chip hangs without another request being added */
1784         mod_timer(&dev_priv->hangcheck_timer,
1785                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1786 }
1787
1788 /* drm_dma.h hooks
1789 */
1790 static void ironlake_irq_preinstall(struct drm_device *dev)
1791 {
1792         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1793
1794         atomic_set(&dev_priv->irq_received, 0);
1795
1796         I915_WRITE(HWSTAM, 0xeffe);
1797
1798         /* XXX hotplug from PCH */
1799
1800         I915_WRITE(DEIMR, 0xffffffff);
1801         I915_WRITE(DEIER, 0x0);
1802         POSTING_READ(DEIER);
1803
1804         /* and GT */
1805         I915_WRITE(GTIMR, 0xffffffff);
1806         I915_WRITE(GTIER, 0x0);
1807         POSTING_READ(GTIER);
1808
1809         /* south display irq */
1810         I915_WRITE(SDEIMR, 0xffffffff);
1811         I915_WRITE(SDEIER, 0x0);
1812         POSTING_READ(SDEIER);
1813 }
1814
1815 static void valleyview_irq_preinstall(struct drm_device *dev)
1816 {
1817         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1818         int pipe;
1819
1820         atomic_set(&dev_priv->irq_received, 0);
1821
1822         /* VLV magic */
1823         I915_WRITE(VLV_IMR, 0);
1824         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1825         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1826         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1827
1828         /* and GT */
1829         I915_WRITE(GTIIR, I915_READ(GTIIR));
1830         I915_WRITE(GTIIR, I915_READ(GTIIR));
1831         I915_WRITE(GTIMR, 0xffffffff);
1832         I915_WRITE(GTIER, 0x0);
1833         POSTING_READ(GTIER);
1834
1835         I915_WRITE(DPINVGTT, 0xff);
1836
1837         I915_WRITE(PORT_HOTPLUG_EN, 0);
1838         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1839         for_each_pipe(pipe)
1840                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1841         I915_WRITE(VLV_IIR, 0xffffffff);
1842         I915_WRITE(VLV_IMR, 0xffffffff);
1843         I915_WRITE(VLV_IER, 0x0);
1844         POSTING_READ(VLV_IER);
1845 }
1846
1847 /*
1848  * Enable digital hotplug on the PCH, and configure the DP short pulse
1849  * duration to 2ms (which is the minimum in the Display Port spec)
1850  *
1851  * This register is the same on all known PCH chips.
1852  */
1853
1854 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1855 {
1856         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1857         u32     hotplug;
1858
1859         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1860         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1861         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1862         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1863         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1864         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1865 }
1866
1867 static int ironlake_irq_postinstall(struct drm_device *dev)
1868 {
1869         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1870         /* enable kind of interrupts always enabled */
1871         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1872                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1873         u32 render_irqs;
1874         u32 hotplug_mask;
1875
1876         dev_priv->irq_mask = ~display_mask;
1877
1878         /* should always can generate irq */
1879         I915_WRITE(DEIIR, I915_READ(DEIIR));
1880         I915_WRITE(DEIMR, dev_priv->irq_mask);
1881         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1882         POSTING_READ(DEIER);
1883
1884         dev_priv->gt_irq_mask = ~0;
1885
1886         I915_WRITE(GTIIR, I915_READ(GTIIR));
1887         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1888
1889         if (IS_GEN6(dev))
1890                 render_irqs =
1891                         GT_USER_INTERRUPT |
1892                         GEN6_BSD_USER_INTERRUPT |
1893                         GEN6_BLITTER_USER_INTERRUPT;
1894         else
1895                 render_irqs =
1896                         GT_USER_INTERRUPT |
1897                         GT_PIPE_NOTIFY |
1898                         GT_BSD_USER_INTERRUPT;
1899         I915_WRITE(GTIER, render_irqs);
1900         POSTING_READ(GTIER);
1901
1902         if (HAS_PCH_CPT(dev)) {
1903                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1904                                 SDE_PORTB_HOTPLUG_CPT |
1905                                 SDE_PORTC_HOTPLUG_CPT |
1906                                 SDE_PORTD_HOTPLUG_CPT);
1907         } else {
1908                 hotplug_mask = (SDE_CRT_HOTPLUG |
1909                                 SDE_PORTB_HOTPLUG |
1910                                 SDE_PORTC_HOTPLUG |
1911                                 SDE_PORTD_HOTPLUG |
1912                                 SDE_AUX_MASK);
1913         }
1914
1915         dev_priv->pch_irq_mask = ~hotplug_mask;
1916
1917         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1918         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1919         I915_WRITE(SDEIER, hotplug_mask);
1920         POSTING_READ(SDEIER);
1921
1922         ironlake_enable_pch_hotplug(dev);
1923
1924         if (IS_IRONLAKE_M(dev)) {
1925                 /* Clear & enable PCU event interrupts */
1926                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1927                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1928                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1929         }
1930
1931         return 0;
1932 }
1933
1934 static int ivybridge_irq_postinstall(struct drm_device *dev)
1935 {
1936         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1937         /* enable kind of interrupts always enabled */
1938         u32 display_mask =
1939                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1940                 DE_PLANEC_FLIP_DONE_IVB |
1941                 DE_PLANEB_FLIP_DONE_IVB |
1942                 DE_PLANEA_FLIP_DONE_IVB;
1943         u32 render_irqs;
1944         u32 hotplug_mask;
1945
1946         dev_priv->irq_mask = ~display_mask;
1947
1948         /* should always can generate irq */
1949         I915_WRITE(DEIIR, I915_READ(DEIIR));
1950         I915_WRITE(DEIMR, dev_priv->irq_mask);
1951         I915_WRITE(DEIER,
1952                    display_mask |
1953                    DE_PIPEC_VBLANK_IVB |
1954                    DE_PIPEB_VBLANK_IVB |
1955                    DE_PIPEA_VBLANK_IVB);
1956         POSTING_READ(DEIER);
1957
1958         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1959
1960         I915_WRITE(GTIIR, I915_READ(GTIIR));
1961         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1962
1963         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1964                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1965         I915_WRITE(GTIER, render_irqs);
1966         POSTING_READ(GTIER);
1967
1968         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1969                         SDE_PORTB_HOTPLUG_CPT |
1970                         SDE_PORTC_HOTPLUG_CPT |
1971                         SDE_PORTD_HOTPLUG_CPT);
1972         dev_priv->pch_irq_mask = ~hotplug_mask;
1973
1974         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1975         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1976         I915_WRITE(SDEIER, hotplug_mask);
1977         POSTING_READ(SDEIER);
1978
1979         ironlake_enable_pch_hotplug(dev);
1980
1981         return 0;
1982 }
1983
1984 static int valleyview_irq_postinstall(struct drm_device *dev)
1985 {
1986         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1987         u32 enable_mask;
1988         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1989         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1990         u32 render_irqs;
1991         u16 msid;
1992
1993         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1994         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1995                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1996                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1997                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1998
1999         /*
2000          *Leave vblank interrupts masked initially.  enable/disable will
2001          * toggle them based on usage.
2002          */
2003         dev_priv->irq_mask = (~enable_mask) |
2004                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2005                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2006
2007         dev_priv->pipestat[0] = 0;
2008         dev_priv->pipestat[1] = 0;
2009
2010         /* Hack for broken MSIs on VLV */
2011         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2012         pci_read_config_word(dev->pdev, 0x98, &msid);
2013         msid &= 0xff; /* mask out delivery bits */
2014         msid |= (1<<14);
2015         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2016
2017         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2018         I915_WRITE(VLV_IER, enable_mask);
2019         I915_WRITE(VLV_IIR, 0xffffffff);
2020         I915_WRITE(PIPESTAT(0), 0xffff);
2021         I915_WRITE(PIPESTAT(1), 0xffff);
2022         POSTING_READ(VLV_IER);
2023
2024         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2025         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2026
2027         I915_WRITE(VLV_IIR, 0xffffffff);
2028         I915_WRITE(VLV_IIR, 0xffffffff);
2029
2030         I915_WRITE(GTIIR, I915_READ(GTIIR));
2031         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2032
2033         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2034                 GEN6_BLITTER_USER_INTERRUPT;
2035         I915_WRITE(GTIER, render_irqs);
2036         POSTING_READ(GTIER);
2037
2038         /* ack & enable invalid PTE error interrupts */
2039 #if 0 /* FIXME: add support to irq handler for checking these bits */
2040         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2041         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2042 #endif
2043
2044         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2045         /* Note HDMI and DP share bits */
2046         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2047                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2048         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2049                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2050         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2051                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2052         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2053                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2054         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2055                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2056         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2057                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2058                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2059         }
2060
2061         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2062
2063         return 0;
2064 }
2065
2066 static void valleyview_irq_uninstall(struct drm_device *dev)
2067 {
2068         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2069         int pipe;
2070
2071         if (!dev_priv)
2072                 return;
2073
2074         for_each_pipe(pipe)
2075                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2076
2077         I915_WRITE(HWSTAM, 0xffffffff);
2078         I915_WRITE(PORT_HOTPLUG_EN, 0);
2079         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2080         for_each_pipe(pipe)
2081                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2082         I915_WRITE(VLV_IIR, 0xffffffff);
2083         I915_WRITE(VLV_IMR, 0xffffffff);
2084         I915_WRITE(VLV_IER, 0x0);
2085         POSTING_READ(VLV_IER);
2086 }
2087
2088 static void ironlake_irq_uninstall(struct drm_device *dev)
2089 {
2090         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2091
2092         if (!dev_priv)
2093                 return;
2094
2095         I915_WRITE(HWSTAM, 0xffffffff);
2096
2097         I915_WRITE(DEIMR, 0xffffffff);
2098         I915_WRITE(DEIER, 0x0);
2099         I915_WRITE(DEIIR, I915_READ(DEIIR));
2100
2101         I915_WRITE(GTIMR, 0xffffffff);
2102         I915_WRITE(GTIER, 0x0);
2103         I915_WRITE(GTIIR, I915_READ(GTIIR));
2104
2105         I915_WRITE(SDEIMR, 0xffffffff);
2106         I915_WRITE(SDEIER, 0x0);
2107         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2108 }
2109
2110 static void i8xx_irq_preinstall(struct drm_device * dev)
2111 {
2112         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2113         int pipe;
2114
2115         atomic_set(&dev_priv->irq_received, 0);
2116
2117         for_each_pipe(pipe)
2118                 I915_WRITE(PIPESTAT(pipe), 0);
2119         I915_WRITE16(IMR, 0xffff);
2120         I915_WRITE16(IER, 0x0);
2121         POSTING_READ16(IER);
2122 }
2123
2124 static int i8xx_irq_postinstall(struct drm_device *dev)
2125 {
2126         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2127
2128         dev_priv->pipestat[0] = 0;
2129         dev_priv->pipestat[1] = 0;
2130
2131         I915_WRITE16(EMR,
2132                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2133
2134         /* Unmask the interrupts that we always want on. */
2135         dev_priv->irq_mask =
2136                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2137                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2138                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2139                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2140                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2141         I915_WRITE16(IMR, dev_priv->irq_mask);
2142
2143         I915_WRITE16(IER,
2144                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2145                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2146                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2147                      I915_USER_INTERRUPT);
2148         POSTING_READ16(IER);
2149
2150         return 0;
2151 }
2152
2153 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2154 {
2155         struct drm_device *dev = (struct drm_device *) arg;
2156         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2157         u16 iir, new_iir;
2158         u32 pipe_stats[2];
2159         unsigned long irqflags;
2160         int irq_received;
2161         int pipe;
2162         u16 flip_mask =
2163                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2164                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2165
2166         atomic_inc(&dev_priv->irq_received);
2167
2168         iir = I915_READ16(IIR);
2169         if (iir == 0)
2170                 return IRQ_NONE;
2171
2172         while (iir & ~flip_mask) {
2173                 /* Can't rely on pipestat interrupt bit in iir as it might
2174                  * have been cleared after the pipestat interrupt was received.
2175                  * It doesn't set the bit in iir again, but it still produces
2176                  * interrupts (for non-MSI).
2177                  */
2178                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2179                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2180                         i915_handle_error(dev, false);
2181
2182                 for_each_pipe(pipe) {
2183                         int reg = PIPESTAT(pipe);
2184                         pipe_stats[pipe] = I915_READ(reg);
2185
2186                         /*
2187                          * Clear the PIPE*STAT regs before the IIR
2188                          */
2189                         if (pipe_stats[pipe] & 0x8000ffff) {
2190                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2191                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2192                                                          pipe_name(pipe));
2193                                 I915_WRITE(reg, pipe_stats[pipe]);
2194                                 irq_received = 1;
2195                         }
2196                 }
2197                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2198
2199                 I915_WRITE16(IIR, iir & ~flip_mask);
2200                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2201
2202                 i915_update_dri1_breadcrumb(dev);
2203
2204                 if (iir & I915_USER_INTERRUPT)
2205                         notify_ring(dev, &dev_priv->ring[RCS]);
2206
2207                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2208                     drm_handle_vblank(dev, 0)) {
2209                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2210                                 intel_prepare_page_flip(dev, 0);
2211                                 intel_finish_page_flip(dev, 0);
2212                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2213                         }
2214                 }
2215
2216                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2217                     drm_handle_vblank(dev, 1)) {
2218                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2219                                 intel_prepare_page_flip(dev, 1);
2220                                 intel_finish_page_flip(dev, 1);
2221                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2222                         }
2223                 }
2224
2225                 iir = new_iir;
2226         }
2227
2228         return IRQ_HANDLED;
2229 }
2230
2231 static void i8xx_irq_uninstall(struct drm_device * dev)
2232 {
2233         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2234         int pipe;
2235
2236         for_each_pipe(pipe) {
2237                 /* Clear enable bits; then clear status bits */
2238                 I915_WRITE(PIPESTAT(pipe), 0);
2239                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2240         }
2241         I915_WRITE16(IMR, 0xffff);
2242         I915_WRITE16(IER, 0x0);
2243         I915_WRITE16(IIR, I915_READ16(IIR));
2244 }
2245
2246 static void i915_irq_preinstall(struct drm_device * dev)
2247 {
2248         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2249         int pipe;
2250
2251         atomic_set(&dev_priv->irq_received, 0);
2252
2253         if (I915_HAS_HOTPLUG(dev)) {
2254                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2255                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2256         }
2257
2258         I915_WRITE16(HWSTAM, 0xeffe);
2259         for_each_pipe(pipe)
2260                 I915_WRITE(PIPESTAT(pipe), 0);
2261         I915_WRITE(IMR, 0xffffffff);
2262         I915_WRITE(IER, 0x0);
2263         POSTING_READ(IER);
2264 }
2265
2266 static int i915_irq_postinstall(struct drm_device *dev)
2267 {
2268         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2269         u32 enable_mask;
2270
2271         dev_priv->pipestat[0] = 0;
2272         dev_priv->pipestat[1] = 0;
2273
2274         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2275
2276         /* Unmask the interrupts that we always want on. */
2277         dev_priv->irq_mask =
2278                 ~(I915_ASLE_INTERRUPT |
2279                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2280                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2281                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2282                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2283                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2284
2285         enable_mask =
2286                 I915_ASLE_INTERRUPT |
2287                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2288                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2289                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2290                 I915_USER_INTERRUPT;
2291
2292         if (I915_HAS_HOTPLUG(dev)) {
2293                 /* Enable in IER... */
2294                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2295                 /* and unmask in IMR */
2296                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2297         }
2298
2299         I915_WRITE(IMR, dev_priv->irq_mask);
2300         I915_WRITE(IER, enable_mask);
2301         POSTING_READ(IER);
2302
2303         if (I915_HAS_HOTPLUG(dev)) {
2304                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2305
2306                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2307                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2308                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2309                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2310                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2311                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2312                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2313                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2314                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2315                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2316                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2317                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2318                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2319                 }
2320
2321                 /* Ignore TV since it's buggy */
2322
2323                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2324         }
2325
2326         intel_opregion_enable_asle(dev);
2327
2328         return 0;
2329 }
2330
2331 static irqreturn_t i915_irq_handler(int irq, void *arg)
2332 {
2333         struct drm_device *dev = (struct drm_device *) arg;
2334         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2335         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2336         unsigned long irqflags;
2337         u32 flip_mask =
2338                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2339                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2340         u32 flip[2] = {
2341                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2342                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2343         };
2344         int pipe, ret = IRQ_NONE;
2345
2346         atomic_inc(&dev_priv->irq_received);
2347
2348         iir = I915_READ(IIR);
2349         do {
2350                 bool irq_received = (iir & ~flip_mask) != 0;
2351                 bool blc_event = false;
2352
2353                 /* Can't rely on pipestat interrupt bit in iir as it might
2354                  * have been cleared after the pipestat interrupt was received.
2355                  * It doesn't set the bit in iir again, but it still produces
2356                  * interrupts (for non-MSI).
2357                  */
2358                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2359                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2360                         i915_handle_error(dev, false);
2361
2362                 for_each_pipe(pipe) {
2363                         int reg = PIPESTAT(pipe);
2364                         pipe_stats[pipe] = I915_READ(reg);
2365
2366                         /* Clear the PIPE*STAT regs before the IIR */
2367                         if (pipe_stats[pipe] & 0x8000ffff) {
2368                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2369                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2370                                                          pipe_name(pipe));
2371                                 I915_WRITE(reg, pipe_stats[pipe]);
2372                                 irq_received = true;
2373                         }
2374                 }
2375                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2376
2377                 if (!irq_received)
2378                         break;
2379
2380                 /* Consume port.  Then clear IIR or we'll miss events */
2381                 if ((I915_HAS_HOTPLUG(dev)) &&
2382                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2383                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2384
2385                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2386                                   hotplug_status);
2387                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2388                                 queue_work(dev_priv->wq,
2389                                            &dev_priv->hotplug_work);
2390
2391                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2392                         POSTING_READ(PORT_HOTPLUG_STAT);
2393                 }
2394
2395                 I915_WRITE(IIR, iir & ~flip_mask);
2396                 new_iir = I915_READ(IIR); /* Flush posted writes */
2397
2398                 if (iir & I915_USER_INTERRUPT)
2399                         notify_ring(dev, &dev_priv->ring[RCS]);
2400
2401                 for_each_pipe(pipe) {
2402                         int plane = pipe;
2403                         if (IS_MOBILE(dev))
2404                                 plane = !plane;
2405                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2406                             drm_handle_vblank(dev, pipe)) {
2407                                 if (iir & flip[plane]) {
2408                                         intel_prepare_page_flip(dev, plane);
2409                                         intel_finish_page_flip(dev, pipe);
2410                                         flip_mask &= ~flip[plane];
2411                                 }
2412                         }
2413
2414                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2415                                 blc_event = true;
2416                 }
2417
2418                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2419                         intel_opregion_asle_intr(dev);
2420
2421                 /* With MSI, interrupts are only generated when iir
2422                  * transitions from zero to nonzero.  If another bit got
2423                  * set while we were handling the existing iir bits, then
2424                  * we would never get another interrupt.
2425                  *
2426                  * This is fine on non-MSI as well, as if we hit this path
2427                  * we avoid exiting the interrupt handler only to generate
2428                  * another one.
2429                  *
2430                  * Note that for MSI this could cause a stray interrupt report
2431                  * if an interrupt landed in the time between writing IIR and
2432                  * the posting read.  This should be rare enough to never
2433                  * trigger the 99% of 100,000 interrupts test for disabling
2434                  * stray interrupts.
2435                  */
2436                 ret = IRQ_HANDLED;
2437                 iir = new_iir;
2438         } while (iir & ~flip_mask);
2439
2440         i915_update_dri1_breadcrumb(dev);
2441
2442         return ret;
2443 }
2444
2445 static void i915_irq_uninstall(struct drm_device * dev)
2446 {
2447         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2448         int pipe;
2449
2450         if (I915_HAS_HOTPLUG(dev)) {
2451                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2452                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2453         }
2454
2455         I915_WRITE16(HWSTAM, 0xffff);
2456         for_each_pipe(pipe) {
2457                 /* Clear enable bits; then clear status bits */
2458                 I915_WRITE(PIPESTAT(pipe), 0);
2459                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2460         }
2461         I915_WRITE(IMR, 0xffffffff);
2462         I915_WRITE(IER, 0x0);
2463
2464         I915_WRITE(IIR, I915_READ(IIR));
2465 }
2466
2467 static void i965_irq_preinstall(struct drm_device * dev)
2468 {
2469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470         int pipe;
2471
2472         atomic_set(&dev_priv->irq_received, 0);
2473
2474         I915_WRITE(PORT_HOTPLUG_EN, 0);
2475         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2476
2477         I915_WRITE(HWSTAM, 0xeffe);
2478         for_each_pipe(pipe)
2479                 I915_WRITE(PIPESTAT(pipe), 0);
2480         I915_WRITE(IMR, 0xffffffff);
2481         I915_WRITE(IER, 0x0);
2482         POSTING_READ(IER);
2483 }
2484
2485 static int i965_irq_postinstall(struct drm_device *dev)
2486 {
2487         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2488         u32 hotplug_en;
2489         u32 enable_mask;
2490         u32 error_mask;
2491
2492         /* Unmask the interrupts that we always want on. */
2493         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2494                                I915_DISPLAY_PORT_INTERRUPT |
2495                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2496                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2497                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2498                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2499                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2500
2501         enable_mask = ~dev_priv->irq_mask;
2502         enable_mask |= I915_USER_INTERRUPT;
2503
2504         if (IS_G4X(dev))
2505                 enable_mask |= I915_BSD_USER_INTERRUPT;
2506
2507         dev_priv->pipestat[0] = 0;
2508         dev_priv->pipestat[1] = 0;
2509
2510         /*
2511          * Enable some error detection, note the instruction error mask
2512          * bit is reserved, so we leave it masked.
2513          */
2514         if (IS_G4X(dev)) {
2515                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2516                                GM45_ERROR_MEM_PRIV |
2517                                GM45_ERROR_CP_PRIV |
2518                                I915_ERROR_MEMORY_REFRESH);
2519         } else {
2520                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2521                                I915_ERROR_MEMORY_REFRESH);
2522         }
2523         I915_WRITE(EMR, error_mask);
2524
2525         I915_WRITE(IMR, dev_priv->irq_mask);
2526         I915_WRITE(IER, enable_mask);
2527         POSTING_READ(IER);
2528
2529         /* Note HDMI and DP share hotplug bits */
2530         hotplug_en = 0;
2531         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2532                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2533         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2534                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2535         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2536                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2537         if (IS_G4X(dev)) {
2538                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2539                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2540                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2541                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2542         } else {
2543                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2544                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2545                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2546                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2547         }
2548         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2549                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2550
2551                 /* Programming the CRT detection parameters tends
2552                    to generate a spurious hotplug event about three
2553                    seconds later.  So just do it once.
2554                    */
2555                 if (IS_G4X(dev))
2556                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2557                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2558         }
2559
2560         /* Ignore TV since it's buggy */
2561
2562         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2563
2564         intel_opregion_enable_asle(dev);
2565
2566         return 0;
2567 }
2568
2569 static irqreturn_t i965_irq_handler(int irq, void *arg)
2570 {
2571         struct drm_device *dev = (struct drm_device *) arg;
2572         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2573         u32 iir, new_iir;
2574         u32 pipe_stats[I915_MAX_PIPES];
2575         unsigned long irqflags;
2576         int irq_received;
2577         int ret = IRQ_NONE, pipe;
2578
2579         atomic_inc(&dev_priv->irq_received);
2580
2581         iir = I915_READ(IIR);
2582
2583         for (;;) {
2584                 bool blc_event = false;
2585
2586                 irq_received = iir != 0;
2587
2588                 /* Can't rely on pipestat interrupt bit in iir as it might
2589                  * have been cleared after the pipestat interrupt was received.
2590                  * It doesn't set the bit in iir again, but it still produces
2591                  * interrupts (for non-MSI).
2592                  */
2593                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2594                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2595                         i915_handle_error(dev, false);
2596
2597                 for_each_pipe(pipe) {
2598                         int reg = PIPESTAT(pipe);
2599                         pipe_stats[pipe] = I915_READ(reg);
2600
2601                         /*
2602                          * Clear the PIPE*STAT regs before the IIR
2603                          */
2604                         if (pipe_stats[pipe] & 0x8000ffff) {
2605                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2606                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2607                                                          pipe_name(pipe));
2608                                 I915_WRITE(reg, pipe_stats[pipe]);
2609                                 irq_received = 1;
2610                         }
2611                 }
2612                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2613
2614                 if (!irq_received)
2615                         break;
2616
2617                 ret = IRQ_HANDLED;
2618
2619                 /* Consume port.  Then clear IIR or we'll miss events */
2620                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2621                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2622
2623                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2624                                   hotplug_status);
2625                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2626                                 queue_work(dev_priv->wq,
2627                                            &dev_priv->hotplug_work);
2628
2629                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2630                         I915_READ(PORT_HOTPLUG_STAT);
2631                 }
2632
2633                 I915_WRITE(IIR, iir);
2634                 new_iir = I915_READ(IIR); /* Flush posted writes */
2635
2636                 if (iir & I915_USER_INTERRUPT)
2637                         notify_ring(dev, &dev_priv->ring[RCS]);
2638                 if (iir & I915_BSD_USER_INTERRUPT)
2639                         notify_ring(dev, &dev_priv->ring[VCS]);
2640
2641                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2642                         intel_prepare_page_flip(dev, 0);
2643
2644                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2645                         intel_prepare_page_flip(dev, 1);
2646
2647                 for_each_pipe(pipe) {
2648                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2649                             drm_handle_vblank(dev, pipe)) {
2650                                 i915_pageflip_stall_check(dev, pipe);
2651                                 intel_finish_page_flip(dev, pipe);
2652                         }
2653
2654                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2655                                 blc_event = true;
2656                 }
2657
2658
2659                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2660                         intel_opregion_asle_intr(dev);
2661
2662                 /* With MSI, interrupts are only generated when iir
2663                  * transitions from zero to nonzero.  If another bit got
2664                  * set while we were handling the existing iir bits, then
2665                  * we would never get another interrupt.
2666                  *
2667                  * This is fine on non-MSI as well, as if we hit this path
2668                  * we avoid exiting the interrupt handler only to generate
2669                  * another one.
2670                  *
2671                  * Note that for MSI this could cause a stray interrupt report
2672                  * if an interrupt landed in the time between writing IIR and
2673                  * the posting read.  This should be rare enough to never
2674                  * trigger the 99% of 100,000 interrupts test for disabling
2675                  * stray interrupts.
2676                  */
2677                 iir = new_iir;
2678         }
2679
2680         i915_update_dri1_breadcrumb(dev);
2681
2682         return ret;
2683 }
2684
2685 static void i965_irq_uninstall(struct drm_device * dev)
2686 {
2687         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2688         int pipe;
2689
2690         if (!dev_priv)
2691                 return;
2692
2693         I915_WRITE(PORT_HOTPLUG_EN, 0);
2694         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2695
2696         I915_WRITE(HWSTAM, 0xffffffff);
2697         for_each_pipe(pipe)
2698                 I915_WRITE(PIPESTAT(pipe), 0);
2699         I915_WRITE(IMR, 0xffffffff);
2700         I915_WRITE(IER, 0x0);
2701
2702         for_each_pipe(pipe)
2703                 I915_WRITE(PIPESTAT(pipe),
2704                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2705         I915_WRITE(IIR, I915_READ(IIR));
2706 }
2707
2708 void intel_irq_init(struct drm_device *dev)
2709 {
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711
2712         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2713         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2714         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2715         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2716
2717         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2718         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2719         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2720                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2721                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2722         }
2723
2724         if (drm_core_check_feature(dev, DRIVER_MODESET))
2725                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2726         else
2727                 dev->driver->get_vblank_timestamp = NULL;
2728         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2729
2730         if (IS_VALLEYVIEW(dev)) {
2731                 dev->driver->irq_handler = valleyview_irq_handler;
2732                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2733                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2734                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2735                 dev->driver->enable_vblank = valleyview_enable_vblank;
2736                 dev->driver->disable_vblank = valleyview_disable_vblank;
2737         } else if (IS_IVYBRIDGE(dev)) {
2738                 /* Share pre & uninstall handlers with ILK/SNB */
2739                 dev->driver->irq_handler = ivybridge_irq_handler;
2740                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2741                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2742                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2743                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2744                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2745         } else if (IS_HASWELL(dev)) {
2746                 /* Share interrupts handling with IVB */
2747                 dev->driver->irq_handler = ivybridge_irq_handler;
2748                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2749                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2750                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2751                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2752                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2753         } else if (HAS_PCH_SPLIT(dev)) {
2754                 dev->driver->irq_handler = ironlake_irq_handler;
2755                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2756                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2757                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2758                 dev->driver->enable_vblank = ironlake_enable_vblank;
2759                 dev->driver->disable_vblank = ironlake_disable_vblank;
2760         } else {
2761                 if (INTEL_INFO(dev)->gen == 2) {
2762                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2763                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2764                         dev->driver->irq_handler = i8xx_irq_handler;
2765                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2766                 } else if (INTEL_INFO(dev)->gen == 3) {
2767                         dev->driver->irq_preinstall = i915_irq_preinstall;
2768                         dev->driver->irq_postinstall = i915_irq_postinstall;
2769                         dev->driver->irq_uninstall = i915_irq_uninstall;
2770                         dev->driver->irq_handler = i915_irq_handler;
2771                 } else {
2772                         dev->driver->irq_preinstall = i965_irq_preinstall;
2773                         dev->driver->irq_postinstall = i965_irq_postinstall;
2774                         dev->driver->irq_uninstall = i965_irq_uninstall;
2775                         dev->driver->irq_handler = i965_irq_handler;
2776                 }
2777                 dev->driver->enable_vblank = i915_enable_vblank;
2778                 dev->driver->disable_vblank = i915_disable_vblank;
2779         }
2780 }