1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
34 #include "intel_drv.h"
36 #define MAX_NOPID ((u32)~0)
39 * Interrupts that are always left unmasked.
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
50 /** Interrupts that we mask and unmask at runtime. */
51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
59 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
63 igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
65 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
66 dev_priv->gt_irq_mask_reg &= ~mask;
67 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
68 (void) I915_READ(GTIMR);
73 igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
75 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
76 dev_priv->gt_irq_mask_reg |= mask;
77 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
78 (void) I915_READ(GTIMR);
82 /* For display hotplug interrupt */
84 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86 if ((dev_priv->irq_mask_reg & mask) != 0) {
87 dev_priv->irq_mask_reg &= ~mask;
88 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
89 (void) I915_READ(DEIMR);
94 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
96 if ((dev_priv->irq_mask_reg & mask) != mask) {
97 dev_priv->irq_mask_reg |= mask;
98 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
99 (void) I915_READ(DEIMR);
104 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
106 if ((dev_priv->irq_mask_reg & mask) != 0) {
107 dev_priv->irq_mask_reg &= ~mask;
108 I915_WRITE(IMR, dev_priv->irq_mask_reg);
109 (void) I915_READ(IMR);
114 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
116 if ((dev_priv->irq_mask_reg & mask) != mask) {
117 dev_priv->irq_mask_reg |= mask;
118 I915_WRITE(IMR, dev_priv->irq_mask_reg);
119 (void) I915_READ(IMR);
124 i915_pipestat(int pipe)
134 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
136 if ((dev_priv->pipestat[pipe] & mask) != mask) {
137 u32 reg = i915_pipestat(pipe);
139 dev_priv->pipestat[pipe] |= mask;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
142 (void) I915_READ(reg);
147 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
149 if ((dev_priv->pipestat[pipe] & mask) != 0) {
150 u32 reg = i915_pipestat(pipe);
152 dev_priv->pipestat[pipe] &= ~mask;
153 I915_WRITE(reg, dev_priv->pipestat[pipe]);
154 (void) I915_READ(reg);
159 * i915_pipe_enabled - check if a pipe is enabled
161 * @pipe: pipe to check
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
168 i915_pipe_enabled(struct drm_device *dev, int pipe)
170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
173 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
179 /* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
182 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
185 unsigned long high_frame;
186 unsigned long low_frame;
187 u32 high1, high2, low, count;
189 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
203 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
204 PIPE_FRAME_HIGH_SHIFT);
205 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
206 PIPE_FRAME_LOW_SHIFT);
207 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
208 PIPE_FRAME_HIGH_SHIFT);
209 } while (high1 != high2);
211 count = (high1 << 8) | low;
216 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
221 if (!i915_pipe_enabled(dev, pipe)) {
222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
226 return I915_READ(reg);
230 * Handle hotplug events outside the interrupt handler proper.
232 static void i915_hotplug_work_func(struct work_struct *work)
234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
236 struct drm_device *dev = dev_priv->dev;
237 struct drm_mode_config *mode_config = &dev->mode_config;
238 struct drm_connector *connector;
240 if (mode_config->num_connector) {
241 list_for_each_entry(connector, &mode_config->connector_list, head) {
242 struct intel_output *intel_output = to_intel_output(connector);
244 if (intel_output->hot_plug)
245 (*intel_output->hot_plug) (intel_output);
248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev);
252 irqreturn_t igdng_irq_handler(struct drm_device *dev)
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
257 u32 new_de_iir, new_gt_iir;
258 struct drm_i915_master_private *master_priv;
260 de_iir = I915_READ(DEIIR);
261 gt_iir = I915_READ(GTIIR);
264 if (de_iir == 0 && gt_iir == 0)
269 I915_WRITE(DEIIR, de_iir);
270 new_de_iir = I915_READ(DEIIR);
271 I915_WRITE(GTIIR, gt_iir);
272 new_gt_iir = I915_READ(GTIIR);
274 if (dev->primary->master) {
275 master_priv = dev->primary->master->driver_priv;
276 if (master_priv->sarea_priv)
277 master_priv->sarea_priv->last_dispatch =
278 READ_BREADCRUMB(dev_priv);
281 if (gt_iir & GT_USER_INTERRUPT) {
282 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
283 DRM_WAKEUP(&dev_priv->irq_queue);
294 * i915_error_work_func - do process context error handling work
297 * Fire an error uevent so userspace can see that a hang or error
300 static void i915_error_work_func(struct work_struct *work)
302 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
304 struct drm_device *dev = dev_priv->dev;
305 char *event_string = "ERROR=1";
306 char *envp[] = { event_string, NULL };
308 DRM_DEBUG("generating error event\n");
310 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
314 * i915_capture_error_state - capture an error record for later analysis
317 * Should be called when an error is detected (either a hang or an error
318 * interrupt) to capture error state from the time of the error. Fills
319 * out a structure which becomes available in debugfs for user level tools
322 static void i915_capture_error_state(struct drm_device *dev)
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 struct drm_i915_error_state *error;
328 spin_lock_irqsave(&dev_priv->error_lock, flags);
329 if (dev_priv->first_error)
332 error = kmalloc(sizeof(*error), GFP_ATOMIC);
334 DRM_DEBUG("out ot memory, not capturing error state\n");
338 error->eir = I915_READ(EIR);
339 error->pgtbl_er = I915_READ(PGTBL_ER);
340 error->pipeastat = I915_READ(PIPEASTAT);
341 error->pipebstat = I915_READ(PIPEBSTAT);
342 error->instpm = I915_READ(INSTPM);
343 if (!IS_I965G(dev)) {
344 error->ipeir = I915_READ(IPEIR);
345 error->ipehr = I915_READ(IPEHR);
346 error->instdone = I915_READ(INSTDONE);
347 error->acthd = I915_READ(ACTHD);
349 error->ipeir = I915_READ(IPEIR_I965);
350 error->ipehr = I915_READ(IPEHR_I965);
351 error->instdone = I915_READ(INSTDONE_I965);
352 error->instps = I915_READ(INSTPS);
353 error->instdone1 = I915_READ(INSTDONE1);
354 error->acthd = I915_READ(ACTHD_I965);
357 do_gettimeofday(&error->time);
359 dev_priv->first_error = error;
362 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
366 * i915_handle_error - handle an error interrupt
369 * Do some basic checking of regsiter state at error interrupt time and
370 * dump it to the syslog. Also call i915_capture_error_state() to make
371 * sure we get a record and make it available in debugfs. Fire a uevent
372 * so userspace knows something bad happened (should trigger collection
373 * of a ring dump etc.).
375 static void i915_handle_error(struct drm_device *dev)
377 struct drm_i915_private *dev_priv = dev->dev_private;
378 u32 eir = I915_READ(EIR);
379 u32 pipea_stats = I915_READ(PIPEASTAT);
380 u32 pipeb_stats = I915_READ(PIPEBSTAT);
382 i915_capture_error_state(dev);
384 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
388 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
389 u32 ipeir = I915_READ(IPEIR_I965);
391 printk(KERN_ERR " IPEIR: 0x%08x\n",
392 I915_READ(IPEIR_I965));
393 printk(KERN_ERR " IPEHR: 0x%08x\n",
394 I915_READ(IPEHR_I965));
395 printk(KERN_ERR " INSTDONE: 0x%08x\n",
396 I915_READ(INSTDONE_I965));
397 printk(KERN_ERR " INSTPS: 0x%08x\n",
399 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
400 I915_READ(INSTDONE1));
401 printk(KERN_ERR " ACTHD: 0x%08x\n",
402 I915_READ(ACTHD_I965));
403 I915_WRITE(IPEIR_I965, ipeir);
404 (void)I915_READ(IPEIR_I965);
406 if (eir & GM45_ERROR_PAGE_TABLE) {
407 u32 pgtbl_err = I915_READ(PGTBL_ER);
408 printk(KERN_ERR "page table error\n");
409 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
411 I915_WRITE(PGTBL_ER, pgtbl_err);
412 (void)I915_READ(PGTBL_ER);
417 if (eir & I915_ERROR_PAGE_TABLE) {
418 u32 pgtbl_err = I915_READ(PGTBL_ER);
419 printk(KERN_ERR "page table error\n");
420 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
422 I915_WRITE(PGTBL_ER, pgtbl_err);
423 (void)I915_READ(PGTBL_ER);
427 if (eir & I915_ERROR_MEMORY_REFRESH) {
428 printk(KERN_ERR "memory refresh error\n");
429 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
431 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
433 /* pipestat has already been acked */
435 if (eir & I915_ERROR_INSTRUCTION) {
436 printk(KERN_ERR "instruction error\n");
437 printk(KERN_ERR " INSTPM: 0x%08x\n",
439 if (!IS_I965G(dev)) {
440 u32 ipeir = I915_READ(IPEIR);
442 printk(KERN_ERR " IPEIR: 0x%08x\n",
444 printk(KERN_ERR " IPEHR: 0x%08x\n",
446 printk(KERN_ERR " INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE));
448 printk(KERN_ERR " ACTHD: 0x%08x\n",
450 I915_WRITE(IPEIR, ipeir);
451 (void)I915_READ(IPEIR);
453 u32 ipeir = I915_READ(IPEIR_I965);
455 printk(KERN_ERR " IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965));
457 printk(KERN_ERR " IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965));
459 printk(KERN_ERR " INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965));
461 printk(KERN_ERR " INSTPS: 0x%08x\n",
463 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1));
465 printk(KERN_ERR " ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965));
467 I915_WRITE(IPEIR_I965, ipeir);
468 (void)I915_READ(IPEIR_I965);
472 I915_WRITE(EIR, eir);
473 (void)I915_READ(EIR);
474 eir = I915_READ(EIR);
477 * some errors might have become stuck,
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
481 I915_WRITE(EMR, I915_READ(EMR) | eir);
482 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
485 queue_work(dev_priv->wq, &dev_priv->error_work);
488 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
490 struct drm_device *dev = (struct drm_device *) arg;
491 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
492 struct drm_i915_master_private *master_priv;
494 u32 pipea_stats, pipeb_stats;
498 unsigned long irqflags;
502 atomic_inc(&dev_priv->irq_received);
505 return igdng_irq_handler(dev);
507 iir = I915_READ(IIR);
510 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
511 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
513 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
514 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
518 irq_received = iir != 0;
520 /* Can't rely on pipestat interrupt bit in iir as it might
521 * have been cleared after the pipestat interrupt was received.
522 * It doesn't set the bit in iir again, but it still produces
523 * interrupts (for non-MSI).
525 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
526 pipea_stats = I915_READ(PIPEASTAT);
527 pipeb_stats = I915_READ(PIPEBSTAT);
529 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
530 i915_handle_error(dev);
533 * Clear the PIPE(A|B)STAT regs before the IIR
535 if (pipea_stats & 0x8000ffff) {
536 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
537 DRM_DEBUG("pipe a underrun\n");
538 I915_WRITE(PIPEASTAT, pipea_stats);
542 if (pipeb_stats & 0x8000ffff) {
543 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
544 DRM_DEBUG("pipe b underrun\n");
545 I915_WRITE(PIPEBSTAT, pipeb_stats);
548 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
555 /* Consume port. Then clear IIR or we'll miss events */
556 if ((I915_HAS_HOTPLUG(dev)) &&
557 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
558 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
560 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
562 if (hotplug_status & dev_priv->hotplug_supported_mask)
563 queue_work(dev_priv->wq,
564 &dev_priv->hotplug_work);
566 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
567 I915_READ(PORT_HOTPLUG_STAT);
569 /* EOS interrupts occurs */
571 (hotplug_status & CRT_EOS_INT_STATUS)) {
574 DRM_DEBUG("EOS interrupt occurs\n");
575 /* status is already cleared */
576 temp = I915_READ(ADPA);
577 temp &= ~ADPA_DAC_ENABLE;
578 I915_WRITE(ADPA, temp);
580 temp = I915_READ(PORT_HOTPLUG_EN);
581 temp &= ~CRT_EOS_INT_EN;
582 I915_WRITE(PORT_HOTPLUG_EN, temp);
584 temp = I915_READ(PORT_HOTPLUG_STAT);
585 if (temp & CRT_EOS_INT_STATUS)
586 I915_WRITE(PORT_HOTPLUG_STAT,
591 I915_WRITE(IIR, iir);
592 new_iir = I915_READ(IIR); /* Flush posted writes */
594 if (dev->primary->master) {
595 master_priv = dev->primary->master->driver_priv;
596 if (master_priv->sarea_priv)
597 master_priv->sarea_priv->last_dispatch =
598 READ_BREADCRUMB(dev_priv);
601 if (iir & I915_USER_INTERRUPT) {
602 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
603 DRM_WAKEUP(&dev_priv->irq_queue);
606 if (pipea_stats & vblank_status) {
608 drm_handle_vblank(dev, 0);
611 if (pipeb_stats & vblank_status) {
613 drm_handle_vblank(dev, 1);
616 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
617 (iir & I915_ASLE_INTERRUPT))
618 opregion_asle_intr(dev);
620 /* With MSI, interrupts are only generated when iir
621 * transitions from zero to nonzero. If another bit got
622 * set while we were handling the existing iir bits, then
623 * we would never get another interrupt.
625 * This is fine on non-MSI as well, as if we hit this path
626 * we avoid exiting the interrupt handler only to generate
629 * Note that for MSI this could cause a stray interrupt report
630 * if an interrupt landed in the time between writing IIR and
631 * the posting read. This should be rare enough to never
632 * trigger the 99% of 100,000 interrupts test for disabling
641 static int i915_emit_irq(struct drm_device * dev)
643 drm_i915_private_t *dev_priv = dev->dev_private;
644 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
647 i915_kernel_lost_context(dev);
652 if (dev_priv->counter > 0x7FFFFFFFUL)
653 dev_priv->counter = 1;
654 if (master_priv->sarea_priv)
655 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
658 OUT_RING(MI_STORE_DWORD_INDEX);
659 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
660 OUT_RING(dev_priv->counter);
661 OUT_RING(MI_USER_INTERRUPT);
664 return dev_priv->counter;
667 void i915_user_irq_get(struct drm_device *dev)
669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
670 unsigned long irqflags;
672 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
673 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
675 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
677 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
679 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
682 void i915_user_irq_put(struct drm_device *dev)
684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
685 unsigned long irqflags;
687 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
688 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
689 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
691 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
693 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
695 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
698 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
700 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
701 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
704 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
705 READ_BREADCRUMB(dev_priv));
707 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
708 if (master_priv->sarea_priv)
709 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
713 if (master_priv->sarea_priv)
714 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
716 i915_user_irq_get(dev);
717 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
718 READ_BREADCRUMB(dev_priv) >= irq_nr);
719 i915_user_irq_put(dev);
722 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
723 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
729 /* Needs the lock as it touches the ring.
731 int i915_irq_emit(struct drm_device *dev, void *data,
732 struct drm_file *file_priv)
734 drm_i915_private_t *dev_priv = dev->dev_private;
735 drm_i915_irq_emit_t *emit = data;
738 if (!dev_priv || !dev_priv->ring.virtual_start) {
739 DRM_ERROR("called with no initialization\n");
743 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
745 mutex_lock(&dev->struct_mutex);
746 result = i915_emit_irq(dev);
747 mutex_unlock(&dev->struct_mutex);
749 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
750 DRM_ERROR("copy_to_user\n");
757 /* Doesn't need the hardware lock.
759 int i915_irq_wait(struct drm_device *dev, void *data,
760 struct drm_file *file_priv)
762 drm_i915_private_t *dev_priv = dev->dev_private;
763 drm_i915_irq_wait_t *irqwait = data;
766 DRM_ERROR("called with no initialization\n");
770 return i915_wait_irq(dev, irqwait->irq_seq);
773 /* Called from drm generic code, passed 'crtc' which
774 * we use as a pipe index
776 int i915_enable_vblank(struct drm_device *dev, int pipe)
778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
779 unsigned long irqflags;
780 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
783 pipeconf = I915_READ(pipeconf_reg);
784 if (!(pipeconf & PIPEACONF_ENABLE))
790 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
792 i915_enable_pipestat(dev_priv, pipe,
793 PIPE_START_VBLANK_INTERRUPT_ENABLE);
795 i915_enable_pipestat(dev_priv, pipe,
796 PIPE_VBLANK_INTERRUPT_ENABLE);
797 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
801 /* Called from drm generic code, passed 'crtc' which
802 * we use as a pipe index
804 void i915_disable_vblank(struct drm_device *dev, int pipe)
806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
807 unsigned long irqflags;
812 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
813 i915_disable_pipestat(dev_priv, pipe,
814 PIPE_VBLANK_INTERRUPT_ENABLE |
815 PIPE_START_VBLANK_INTERRUPT_ENABLE);
816 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
819 void i915_enable_interrupt (struct drm_device *dev)
821 struct drm_i915_private *dev_priv = dev->dev_private;
824 opregion_enable_asle(dev);
825 dev_priv->irq_enabled = 1;
829 /* Set the vblank monitor pipe
831 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
832 struct drm_file *file_priv)
834 drm_i915_private_t *dev_priv = dev->dev_private;
837 DRM_ERROR("called with no initialization\n");
844 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
845 struct drm_file *file_priv)
847 drm_i915_private_t *dev_priv = dev->dev_private;
848 drm_i915_vblank_pipe_t *pipe = data;
851 DRM_ERROR("called with no initialization\n");
855 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
861 * Schedule buffer swap at given vertical blank.
863 int i915_vblank_swap(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
866 /* The delayed swap mechanism was fundamentally racy, and has been
867 * removed. The model was that the client requested a delayed flip/swap
868 * from the kernel, then waited for vblank before continuing to perform
869 * rendering. The problem was that the kernel might wake the client
870 * up before it dispatched the vblank swap (since the lock has to be
871 * held while touching the ringbuffer), in which case the client would
872 * clear and start the next frame before the swap occurred, and
873 * flicker would occur in addition to likely missing the vblank.
875 * In the absence of this ioctl, userland falls back to a correct path
876 * of waiting for a vblank, then dispatching the swap on its own.
877 * Context switching to userland and back is plenty fast enough for
878 * meeting the requirements of vblank swapping.
885 static void igdng_irq_preinstall(struct drm_device *dev)
887 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
889 I915_WRITE(HWSTAM, 0xeffe);
891 /* XXX hotplug from PCH */
893 I915_WRITE(DEIMR, 0xffffffff);
894 I915_WRITE(DEIER, 0x0);
895 (void) I915_READ(DEIER);
898 I915_WRITE(GTIMR, 0xffffffff);
899 I915_WRITE(GTIER, 0x0);
900 (void) I915_READ(GTIER);
903 static int igdng_irq_postinstall(struct drm_device *dev)
905 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
906 /* enable kind of interrupts always enabled */
907 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
908 u32 render_mask = GT_USER_INTERRUPT;
910 dev_priv->irq_mask_reg = ~display_mask;
911 dev_priv->de_irq_enable_reg = display_mask;
913 /* should always can generate irq */
914 I915_WRITE(DEIIR, I915_READ(DEIIR));
915 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
916 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
917 (void) I915_READ(DEIER);
919 /* user interrupt should be enabled, but masked initial */
920 dev_priv->gt_irq_mask_reg = 0xffffffff;
921 dev_priv->gt_irq_enable_reg = render_mask;
923 I915_WRITE(GTIIR, I915_READ(GTIIR));
924 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
925 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
926 (void) I915_READ(GTIER);
931 void i915_driver_irq_preinstall(struct drm_device * dev)
933 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
935 atomic_set(&dev_priv->irq_received, 0);
937 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
938 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
941 igdng_irq_preinstall(dev);
945 if (I915_HAS_HOTPLUG(dev)) {
946 I915_WRITE(PORT_HOTPLUG_EN, 0);
947 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
950 I915_WRITE(HWSTAM, 0xeffe);
951 I915_WRITE(PIPEASTAT, 0);
952 I915_WRITE(PIPEBSTAT, 0);
953 I915_WRITE(IMR, 0xffffffff);
954 I915_WRITE(IER, 0x0);
955 (void) I915_READ(IER);
958 int i915_driver_irq_postinstall(struct drm_device *dev)
960 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
961 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
964 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
966 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
969 return igdng_irq_postinstall(dev);
971 /* Unmask the interrupts that we always want on. */
972 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
974 dev_priv->pipestat[0] = 0;
975 dev_priv->pipestat[1] = 0;
977 if (I915_HAS_HOTPLUG(dev)) {
978 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
980 /* Leave other bits alone */
981 hotplug_en |= HOTPLUG_EN_MASK;
982 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
984 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
985 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
986 SDVOB_HOTPLUG_INT_STATUS;
988 dev_priv->hotplug_supported_mask |=
989 HDMIB_HOTPLUG_INT_STATUS |
990 HDMIC_HOTPLUG_INT_STATUS |
991 HDMID_HOTPLUG_INT_STATUS;
993 /* Enable in IER... */
994 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
995 /* and unmask in IMR */
996 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1000 * Enable some error detection, note the instruction error mask
1001 * bit is reserved, so we leave it masked.
1004 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1005 GM45_ERROR_MEM_PRIV |
1006 GM45_ERROR_CP_PRIV |
1007 I915_ERROR_MEMORY_REFRESH);
1009 error_mask = ~(I915_ERROR_PAGE_TABLE |
1010 I915_ERROR_MEMORY_REFRESH);
1012 I915_WRITE(EMR, error_mask);
1014 /* Disable pipe interrupt enables, clear pending pipe status */
1015 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1016 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1017 /* Clear pending interrupt status */
1018 I915_WRITE(IIR, I915_READ(IIR));
1020 I915_WRITE(IER, enable_mask);
1021 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1022 (void) I915_READ(IER);
1024 opregion_enable_asle(dev);
1029 static void igdng_irq_uninstall(struct drm_device *dev)
1031 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1032 I915_WRITE(HWSTAM, 0xffffffff);
1034 I915_WRITE(DEIMR, 0xffffffff);
1035 I915_WRITE(DEIER, 0x0);
1036 I915_WRITE(DEIIR, I915_READ(DEIIR));
1038 I915_WRITE(GTIMR, 0xffffffff);
1039 I915_WRITE(GTIER, 0x0);
1040 I915_WRITE(GTIIR, I915_READ(GTIIR));
1043 void i915_driver_irq_uninstall(struct drm_device * dev)
1045 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1050 dev_priv->vblank_pipe = 0;
1052 if (IS_IGDNG(dev)) {
1053 igdng_irq_uninstall(dev);
1057 if (I915_HAS_HOTPLUG(dev)) {
1058 I915_WRITE(PORT_HOTPLUG_EN, 0);
1059 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1062 I915_WRITE(HWSTAM, 0xffffffff);
1063 I915_WRITE(PIPEASTAT, 0);
1064 I915_WRITE(PIPEBSTAT, 0);
1065 I915_WRITE(IMR, 0xffffffff);
1066 I915_WRITE(IER, 0x0);
1068 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1069 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1070 I915_WRITE(IIR, I915_READ(IIR));