drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static void notify_ring(struct drm_device *dev,
 297                         struct intel_ring_buffer *ring)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         u32 seqno = ring->get_seqno(ring);
 301         ring->irq_seqno = seqno;
 302         trace_i915_gem_request_complete(dev, seqno);
 303         wake_up_all(&ring->irq_queue);
 304         dev_priv->hangcheck_count = 0;
 305         mod_timer(&dev_priv->hangcheck_timer,
 306                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 307 }
 308
 309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         int ret = IRQ_NONE;
 313         u32 de_iir, gt_iir, de_ier, pch_iir;
 314         u32 hotplug_mask;
 315         struct drm_i915_master_private *master_priv;
 316         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 317
 318         if (IS_GEN6(dev))
 319                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 320
 321         /* disable master interrupt before clearing iir  */
 322         de_ier = I915_READ(DEIER);
 323         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 324         (void)I915_READ(DEIER);
 325
 326         de_iir = I915_READ(DEIIR);
 327         gt_iir = I915_READ(GTIIR);
 328         pch_iir = I915_READ(SDEIIR);
 329
 330         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 331                 goto done;
 332
 333         if (HAS_PCH_CPT(dev))
 334                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 335         else
 336                 hotplug_mask = SDE_HOTPLUG_MASK;
 337
 338         ret = IRQ_HANDLED;
 339
 340         if (dev->primary->master) {
 341                 master_priv = dev->primary->master->driver_priv;
 342                 if (master_priv->sarea_priv)
 343                         master_priv->sarea_priv->last_dispatch =
 344                                 READ_BREADCRUMB(dev_priv);
 345         }
 346
 347         if (gt_iir & GT_PIPE_NOTIFY)
 348                 notify_ring(dev, &dev_priv->render_ring);
 349         if (gt_iir & bsd_usr_interrupt)
 350                 notify_ring(dev, &dev_priv->bsd_ring);
 351         if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
 352                 notify_ring(dev, &dev_priv->blt_ring);
 353
 354         if (de_iir & DE_GSE)
 355                 intel_opregion_gse_intr(dev);
 356
 357         if (de_iir & DE_PLANEA_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 0);
 359                 intel_finish_page_flip_plane(dev, 0);
 360         }
 361
 362         if (de_iir & DE_PLANEB_FLIP_DONE) {
 363                 intel_prepare_page_flip(dev, 1);
 364                 intel_finish_page_flip_plane(dev, 1);
 365         }
 366
 367         if (de_iir & DE_PIPEA_VBLANK)
 368                 drm_handle_vblank(dev, 0);
 369
 370         if (de_iir & DE_PIPEB_VBLANK)
 371                 drm_handle_vblank(dev, 1);
 372
 373         /* check event from PCH */
 374         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 375                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 376
 377         if (de_iir & DE_PCU_EVENT) {
 378                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 379                 i915_handle_rps_change(dev);
 380         }
 381
 382         /* should clear PCH hotplug event before clear CPU irq */
 383         I915_WRITE(SDEIIR, pch_iir);
 384         I915_WRITE(GTIIR, gt_iir);
 385         I915_WRITE(DEIIR, de_iir);
 386
 387 done:
 388         I915_WRITE(DEIER, de_ier);
 389         (void)I915_READ(DEIER);
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * i915_error_work_func - do process context error handling work
 396  * @work: work struct
 397  *
 398  * Fire an error uevent so userspace can see that a hang or error
 399  * was detected.
 400  */
 401 static void i915_error_work_func(struct work_struct *work)
 402 {
 403         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 404                                                     error_work);
 405         struct drm_device *dev = dev_priv->dev;
 406         char *error_event[] = { "ERROR=1", NULL };
 407         char *reset_event[] = { "RESET=1", NULL };
 408         char *reset_done_event[] = { "ERROR=0", NULL };
 409
 410         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 411
 412         if (atomic_read(&dev_priv->mm.wedged)) {
 413                 DRM_DEBUG_DRIVER("resetting chip\n");
 414                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 415                 if (!i915_reset(dev, GRDOM_RENDER)) {
 416                         atomic_set(&dev_priv->mm.wedged, 0);
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 418                 }
 419                 complete_all(&dev_priv->error_completion);
 420         }
 421 }
 422
 423 #ifdef CONFIG_DEBUG_FS
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         struct drm_i915_gem_object *src_priv;
 431         int page, page_count;
 432         u32 reloc_offset;
 433
 434         if (src == NULL)
 435                 return NULL;
 436
 437         src_priv = to_intel_bo(src);
 438         if (src_priv->pages == NULL)
 439                 return NULL;
 440
 441         page_count = src->size / PAGE_SIZE;
 442
 443         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 444         if (dst == NULL)
 445                 return NULL;
 446
 447         reloc_offset = src_priv->gtt_offset;
 448         for (page = 0; page < page_count; page++) {
 449                 unsigned long flags;
 450                 void __iomem *s;
 451                 void *d;
 452
 453                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 454                 if (d == NULL)
 455                         goto unwind;
 456
 457                 local_irq_save(flags);
 458                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 459                                              reloc_offset);
 460                 memcpy_fromio(d, s, PAGE_SIZE);
 461                 io_mapping_unmap_atomic(s);
 462                 local_irq_restore(flags);
 463
 464                 dst->pages[page] = d;
 465
 466                 reloc_offset += PAGE_SIZE;
 467         }
 468         dst->page_count = page_count;
 469         dst->gtt_offset = src_priv->gtt_offset;
 470
 471         return dst;
 472
 473 unwind:
 474         while (page--)
 475                 kfree(dst->pages[page]);
 476         kfree(dst);
 477         return NULL;
 478 }
 479
 480 static void
 481 i915_error_object_free(struct drm_i915_error_object *obj)
 482 {
 483         int page;
 484
 485         if (obj == NULL)
 486                 return;
 487
 488         for (page = 0; page < obj->page_count; page++)
 489                 kfree(obj->pages[page]);
 490
 491         kfree(obj);
 492 }
 493
 494 static void
 495 i915_error_state_free(struct drm_device *dev,
 496                       struct drm_i915_error_state *error)
 497 {
 498         i915_error_object_free(error->batchbuffer[0]);
 499         i915_error_object_free(error->batchbuffer[1]);
 500         i915_error_object_free(error->ringbuffer);
 501         kfree(error->active_bo);
 502         kfree(error->overlay);
 503         kfree(error);
 504 }
 505
 506 static u32
 507 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 508 {
 509         u32 cmd;
 510
 511         if (IS_I830(dev) || IS_845G(dev))
 512                 cmd = MI_BATCH_BUFFER;
 513         else if (INTEL_INFO(dev)->gen >= 4)
 514                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 515                        MI_BATCH_NON_SECURE_I965);
 516         else
 517                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 518
 519         return ring[0] == cmd ? ring[1] : 0;
 520 }
 521
 522 static u32
 523 i915_ringbuffer_last_batch(struct drm_device *dev)
 524 {
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         u32 head, bbaddr;
 527         u32 *ring;
 528
 529         /* Locate the current position in the ringbuffer and walk back
 530          * to find the most recently dispatched batch buffer.
 531          */
 532         bbaddr = 0;
 533         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 534         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 535
 536         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 537                 bbaddr = i915_get_bbaddr(dev, ring);
 538                 if (bbaddr)
 539                         break;
 540         }
 541
 542         if (bbaddr == 0) {
 543                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 544                                 + dev_priv->render_ring.size);
 545                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 546                         bbaddr = i915_get_bbaddr(dev, ring);
 547                         if (bbaddr)
 548                                 break;
 549                 }
 550         }
 551
 552         return bbaddr;
 553 }
 554
 555 /**
 556  * i915_capture_error_state - capture an error record for later analysis
 557  * @dev: drm device
 558  *
 559  * Should be called when an error is detected (either a hang or an error
 560  * interrupt) to capture error state from the time of the error.  Fills
 561  * out a structure which becomes available in debugfs for user level tools
 562  * to pick up.
 563  */
 564 static void i915_capture_error_state(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct drm_i915_gem_object *obj_priv;
 568         struct drm_i915_error_state *error;
 569         struct drm_gem_object *batchbuffer[2];
 570         unsigned long flags;
 571         u32 bbaddr;
 572         int count;
 573
 574         spin_lock_irqsave(&dev_priv->error_lock, flags);
 575         error = dev_priv->first_error;
 576         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 577         if (error)
 578                 return;
 579
 580         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 581         if (!error) {
 582                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 583                 return;
 584         }
 585
 586         DRM_DEBUG_DRIVER("generating error event\n");
 587
 588         error->seqno =
 589                 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
 590         error->eir = I915_READ(EIR);
 591         error->pgtbl_er = I915_READ(PGTBL_ER);
 592         error->pipeastat = I915_READ(PIPEASTAT);
 593         error->pipebstat = I915_READ(PIPEBSTAT);
 594         error->instpm = I915_READ(INSTPM);
 595         error->error = 0;
 596         if (INTEL_INFO(dev)->gen >= 6) {
 597                 error->error = I915_READ(ERROR_GEN6);
 598
 599                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 600                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 601                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 602                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 603                 error->bcs_seqno = 0;
 604                 if (dev_priv->blt_ring.get_seqno)
 605                         error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring);
 606
 607                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 608                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 609                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 610                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 611                 error->vcs_seqno = 0;
 612                 if (dev_priv->bsd_ring.get_seqno)
 613                         error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring);
 614         }
 615         if (INTEL_INFO(dev)->gen >= 4) {
 616                 error->ipeir = I915_READ(IPEIR_I965);
 617                 error->ipehr = I915_READ(IPEHR_I965);
 618                 error->instdone = I915_READ(INSTDONE_I965);
 619                 error->instps = I915_READ(INSTPS);
 620                 error->instdone1 = I915_READ(INSTDONE1);
 621                 error->acthd = I915_READ(ACTHD_I965);
 622                 error->bbaddr = I915_READ64(BB_ADDR);
 623         } else {
 624                 error->ipeir = I915_READ(IPEIR);
 625                 error->ipehr = I915_READ(IPEHR);
 626                 error->instdone = I915_READ(INSTDONE);
 627                 error->acthd = I915_READ(ACTHD);
 628                 error->bbaddr = 0;
 629         }
 630
 631         bbaddr = i915_ringbuffer_last_batch(dev);
 632
 633         /* Grab the current batchbuffer, most likely to have crashed. */
 634         batchbuffer[0] = NULL;
 635         batchbuffer[1] = NULL;
 636         count = 0;
 637         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 638                 struct drm_gem_object *obj = &obj_priv->base;
 639
 640                 if (batchbuffer[0] == NULL &&
 641                     bbaddr >= obj_priv->gtt_offset &&
 642                     bbaddr < obj_priv->gtt_offset + obj->size)
 643                         batchbuffer[0] = obj;
 644
 645                 if (batchbuffer[1] == NULL &&
 646                     error->acthd >= obj_priv->gtt_offset &&
 647                     error->acthd < obj_priv->gtt_offset + obj->size)
 648                         batchbuffer[1] = obj;
 649
 650                 count++;
 651         }
 652         /* Scan the other lists for completeness for those bizarre errors. */
 653         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 654                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
 655                         struct drm_gem_object *obj = &obj_priv->base;
 656
 657                         if (batchbuffer[0] == NULL &&
 658                             bbaddr >= obj_priv->gtt_offset &&
 659                             bbaddr < obj_priv->gtt_offset + obj->size)
 660                                 batchbuffer[0] = obj;
 661
 662                         if (batchbuffer[1] == NULL &&
 663                             error->acthd >= obj_priv->gtt_offset &&
 664                             error->acthd < obj_priv->gtt_offset + obj->size)
 665                                 batchbuffer[1] = obj;
 666
 667                         if (batchbuffer[0] && batchbuffer[1])
 668                                 break;
 669                 }
 670         }
 671         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 672                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
 673                         struct drm_gem_object *obj = &obj_priv->base;
 674
 675                         if (batchbuffer[0] == NULL &&
 676                             bbaddr >= obj_priv->gtt_offset &&
 677                             bbaddr < obj_priv->gtt_offset + obj->size)
 678                                 batchbuffer[0] = obj;
 679
 680                         if (batchbuffer[1] == NULL &&
 681                             error->acthd >= obj_priv->gtt_offset &&
 682                             error->acthd < obj_priv->gtt_offset + obj->size)
 683                                 batchbuffer[1] = obj;
 684
 685                         if (batchbuffer[0] && batchbuffer[1])
 686                                 break;
 687                 }
 688         }
 689
 690         /* We need to copy these to an anonymous buffer as the simplest
 691          * method to avoid being overwritten by userspace.
 692          */
 693         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 694         if (batchbuffer[1] != batchbuffer[0])
 695                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 696         else
 697                 error->batchbuffer[1] = NULL;
 698
 699         /* Record the ringbuffer */
 700         error->ringbuffer = i915_error_object_create(dev,
 701                         dev_priv->render_ring.gem_object);
 702
 703         /* Record buffers on the active list. */
 704         error->active_bo = NULL;
 705         error->active_bo_count = 0;
 706
 707         if (count)
 708                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 709                                            GFP_ATOMIC);
 710
 711         if (error->active_bo) {
 712                 int i = 0;
 713                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 714                         struct drm_gem_object *obj = &obj_priv->base;
 715
 716                         error->active_bo[i].size = obj->size;
 717                         error->active_bo[i].name = obj->name;
 718                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 719                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 720                         error->active_bo[i].read_domains = obj->read_domains;
 721                         error->active_bo[i].write_domain = obj->write_domain;
 722                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 723                         error->active_bo[i].pinned = 0;
 724                         if (obj_priv->pin_count > 0)
 725                                 error->active_bo[i].pinned = 1;
 726                         if (obj_priv->user_pin_count > 0)
 727                                 error->active_bo[i].pinned = -1;
 728                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 729                         error->active_bo[i].dirty = obj_priv->dirty;
 730                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 731
 732                         if (++i == count)
 733                                 break;
 734                 }
 735                 error->active_bo_count = i;
 736         }
 737
 738         do_gettimeofday(&error->time);
 739
 740         error->overlay = intel_overlay_capture_error_state(dev);
 741
 742         spin_lock_irqsave(&dev_priv->error_lock, flags);
 743         if (dev_priv->first_error == NULL) {
 744                 dev_priv->first_error = error;
 745                 error = NULL;
 746         }
 747         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 748
 749         if (error)
 750                 i915_error_state_free(dev, error);
 751 }
 752
 753 void i915_destroy_error_state(struct drm_device *dev)
 754 {
 755         struct drm_i915_private *dev_priv = dev->dev_private;
 756         struct drm_i915_error_state *error;
 757
 758         spin_lock(&dev_priv->error_lock);
 759         error = dev_priv->first_error;
 760         dev_priv->first_error = NULL;
 761         spin_unlock(&dev_priv->error_lock);
 762
 763         if (error)
 764                 i915_error_state_free(dev, error);
 765 }
 766 #else
 767 #define i915_capture_error_state(x)
 768 #endif
 769
 770 static void i915_report_and_clear_eir(struct drm_device *dev)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         u32 eir = I915_READ(EIR);
 774
 775         if (!eir)
 776                 return;
 777
 778         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 779                eir);
 780
 781         if (IS_G4X(dev)) {
 782                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 783                         u32 ipeir = I915_READ(IPEIR_I965);
 784
 785                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 786                                I915_READ(IPEIR_I965));
 787                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 788                                I915_READ(IPEHR_I965));
 789                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 790                                I915_READ(INSTDONE_I965));
 791                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 792                                I915_READ(INSTPS));
 793                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 794                                I915_READ(INSTDONE1));
 795                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 796                                I915_READ(ACTHD_I965));
 797                         I915_WRITE(IPEIR_I965, ipeir);
 798                         (void)I915_READ(IPEIR_I965);
 799                 }
 800                 if (eir & GM45_ERROR_PAGE_TABLE) {
 801                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 802                         printk(KERN_ERR "page table error\n");
 803                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 804                                pgtbl_err);
 805                         I915_WRITE(PGTBL_ER, pgtbl_err);
 806                         (void)I915_READ(PGTBL_ER);
 807                 }
 808         }
 809
 810         if (!IS_GEN2(dev)) {
 811                 if (eir & I915_ERROR_PAGE_TABLE) {
 812                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 813                         printk(KERN_ERR "page table error\n");
 814                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 815                                pgtbl_err);
 816                         I915_WRITE(PGTBL_ER, pgtbl_err);
 817                         (void)I915_READ(PGTBL_ER);
 818                 }
 819         }
 820
 821         if (eir & I915_ERROR_MEMORY_REFRESH) {
 822                 u32 pipea_stats = I915_READ(PIPEASTAT);
 823                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 824
 825                 printk(KERN_ERR "memory refresh error\n");
 826                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 827                        pipea_stats);
 828                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 829                        pipeb_stats);
 830                 /* pipestat has already been acked */
 831         }
 832         if (eir & I915_ERROR_INSTRUCTION) {
 833                 printk(KERN_ERR "instruction error\n");
 834                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 835                        I915_READ(INSTPM));
 836                 if (INTEL_INFO(dev)->gen < 4) {
 837                         u32 ipeir = I915_READ(IPEIR);
 838
 839                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 840                                I915_READ(IPEIR));
 841                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 842                                I915_READ(IPEHR));
 843                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 844                                I915_READ(INSTDONE));
 845                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 846                                I915_READ(ACTHD));
 847                         I915_WRITE(IPEIR, ipeir);
 848                         (void)I915_READ(IPEIR);
 849                 } else {
 850                         u32 ipeir = I915_READ(IPEIR_I965);
 851
 852                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 853                                I915_READ(IPEIR_I965));
 854                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 855                                I915_READ(IPEHR_I965));
 856                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 857                                I915_READ(INSTDONE_I965));
 858                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 859                                I915_READ(INSTPS));
 860                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 861                                I915_READ(INSTDONE1));
 862                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 863                                I915_READ(ACTHD_I965));
 864                         I915_WRITE(IPEIR_I965, ipeir);
 865                         (void)I915_READ(IPEIR_I965);
 866                 }
 867         }
 868
 869         I915_WRITE(EIR, eir);
 870         (void)I915_READ(EIR);
 871         eir = I915_READ(EIR);
 872         if (eir) {
 873                 /*
 874                  * some errors might have become stuck,
 875                  * mask them.
 876                  */
 877                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 878                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 879                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 880         }
 881 }
 882
 883 /**
 884  * i915_handle_error - handle an error interrupt
 885  * @dev: drm device
 886  *
 887  * Do some basic checking of regsiter state at error interrupt time and
 888  * dump it to the syslog.  Also call i915_capture_error_state() to make
 889  * sure we get a record and make it available in debugfs.  Fire a uevent
 890  * so userspace knows something bad happened (should trigger collection
 891  * of a ring dump etc.).
 892  */
 893 static void i915_handle_error(struct drm_device *dev, bool wedged)
 894 {
 895         struct drm_i915_private *dev_priv = dev->dev_private;
 896
 897         i915_capture_error_state(dev);
 898         i915_report_and_clear_eir(dev);
 899
 900         if (wedged) {
 901                 INIT_COMPLETION(dev_priv->error_completion);
 902                 atomic_set(&dev_priv->mm.wedged, 1);
 903
 904                 /*
 905                  * Wakeup waiting processes so they don't hang
 906                  */
 907                 wake_up_all(&dev_priv->render_ring.irq_queue);
 908                 if (HAS_BSD(dev))
 909                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 910                 if (HAS_BLT(dev))
 911                         wake_up_all(&dev_priv->blt_ring.irq_queue);
 912         }
 913
 914         queue_work(dev_priv->wq, &dev_priv->error_work);
 915 }
 916
 917 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 918 {
 919         drm_i915_private_t *dev_priv = dev->dev_private;
 920         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 922         struct drm_i915_gem_object *obj_priv;
 923         struct intel_unpin_work *work;
 924         unsigned long flags;
 925         bool stall_detected;
 926
 927         /* Ignore early vblank irqs */
 928         if (intel_crtc == NULL)
 929                 return;
 930
 931         spin_lock_irqsave(&dev->event_lock, flags);
 932         work = intel_crtc->unpin_work;
 933
 934         if (work == NULL || work->pending || !work->enable_stall_check) {
 935                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 936                 spin_unlock_irqrestore(&dev->event_lock, flags);
 937                 return;
 938         }
 939
 940         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 941         obj_priv = to_intel_bo(work->pending_flip_obj);
 942         if (INTEL_INFO(dev)->gen >= 4) {
 943                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 944                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 945         } else {
 946                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 947                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 948                                                         crtc->y * crtc->fb->pitch +
 949                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 950         }
 951
 952         spin_unlock_irqrestore(&dev->event_lock, flags);
 953
 954         if (stall_detected) {
 955                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 956                 intel_prepare_page_flip(dev, intel_crtc->plane);
 957         }
 958 }
 959
 960 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 961 {
 962         struct drm_device *dev = (struct drm_device *) arg;
 963         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 964         struct drm_i915_master_private *master_priv;
 965         u32 iir, new_iir;
 966         u32 pipea_stats, pipeb_stats;
 967         u32 vblank_status;
 968         int vblank = 0;
 969         unsigned long irqflags;
 970         int irq_received;
 971         int ret = IRQ_NONE;
 972
 973         atomic_inc(&dev_priv->irq_received);
 974
 975         if (HAS_PCH_SPLIT(dev))
 976                 return ironlake_irq_handler(dev);
 977
 978         iir = I915_READ(IIR);
 979
 980         if (INTEL_INFO(dev)->gen >= 4)
 981                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 982         else
 983                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 984
 985         for (;;) {
 986                 irq_received = iir != 0;
 987
 988                 /* Can't rely on pipestat interrupt bit in iir as it might
 989                  * have been cleared after the pipestat interrupt was received.
 990                  * It doesn't set the bit in iir again, but it still produces
 991                  * interrupts (for non-MSI).
 992                  */
 993                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 994                 pipea_stats = I915_READ(PIPEASTAT);
 995                 pipeb_stats = I915_READ(PIPEBSTAT);
 996
 997                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 998                         i915_handle_error(dev, false);
 999
1000                 /*
1001                  * Clear the PIPE(A|B)STAT regs before the IIR
1002                  */
1003                 if (pipea_stats & 0x8000ffff) {
1004                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1005                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1006                         I915_WRITE(PIPEASTAT, pipea_stats);
1007                         irq_received = 1;
1008                 }
1009
1010                 if (pipeb_stats & 0x8000ffff) {
1011                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1012                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1013                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1014                         irq_received = 1;
1015                 }
1016                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1017
1018                 if (!irq_received)
1019                         break;
1020
1021                 ret = IRQ_HANDLED;
1022
1023                 /* Consume port.  Then clear IIR or we'll miss events */
1024                 if ((I915_HAS_HOTPLUG(dev)) &&
1025                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1026                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1027
1028                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1029                                   hotplug_status);
1030                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1031                                 queue_work(dev_priv->wq,
1032                                            &dev_priv->hotplug_work);
1033
1034                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1035                         I915_READ(PORT_HOTPLUG_STAT);
1036                 }
1037
1038                 I915_WRITE(IIR, iir);
1039                 new_iir = I915_READ(IIR); /* Flush posted writes */
1040
1041                 if (dev->primary->master) {
1042                         master_priv = dev->primary->master->driver_priv;
1043                         if (master_priv->sarea_priv)
1044                                 master_priv->sarea_priv->last_dispatch =
1045                                         READ_BREADCRUMB(dev_priv);
1046                 }
1047
1048                 if (iir & I915_USER_INTERRUPT)
1049                         notify_ring(dev, &dev_priv->render_ring);
1050                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1051                         notify_ring(dev, &dev_priv->bsd_ring);
1052
1053                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1054                         intel_prepare_page_flip(dev, 0);
1055                         if (dev_priv->flip_pending_is_done)
1056                                 intel_finish_page_flip_plane(dev, 0);
1057                 }
1058
1059                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1060                         intel_prepare_page_flip(dev, 1);
1061                         if (dev_priv->flip_pending_is_done)
1062                                 intel_finish_page_flip_plane(dev, 1);
1063                 }
1064
1065                 if (pipea_stats & vblank_status) {
1066                         vblank++;
1067                         drm_handle_vblank(dev, 0);
1068                         if (!dev_priv->flip_pending_is_done) {
1069                                 i915_pageflip_stall_check(dev, 0);
1070                                 intel_finish_page_flip(dev, 0);
1071                         }
1072                 }
1073
1074                 if (pipeb_stats & vblank_status) {
1075                         vblank++;
1076                         drm_handle_vblank(dev, 1);
1077                         if (!dev_priv->flip_pending_is_done) {
1078                                 i915_pageflip_stall_check(dev, 1);
1079                                 intel_finish_page_flip(dev, 1);
1080                         }
1081                 }
1082
1083                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1084                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1085                     (iir & I915_ASLE_INTERRUPT))
1086                         intel_opregion_asle_intr(dev);
1087
1088                 /* With MSI, interrupts are only generated when iir
1089                  * transitions from zero to nonzero.  If another bit got
1090                  * set while we were handling the existing iir bits, then
1091                  * we would never get another interrupt.
1092                  *
1093                  * This is fine on non-MSI as well, as if we hit this path
1094                  * we avoid exiting the interrupt handler only to generate
1095                  * another one.
1096                  *
1097                  * Note that for MSI this could cause a stray interrupt report
1098                  * if an interrupt landed in the time between writing IIR and
1099                  * the posting read.  This should be rare enough to never
1100                  * trigger the 99% of 100,000 interrupts test for disabling
1101                  * stray interrupts.
1102                  */
1103                 iir = new_iir;
1104         }
1105
1106         return ret;
1107 }
1108
1109 static int i915_emit_irq(struct drm_device * dev)
1110 {
1111         drm_i915_private_t *dev_priv = dev->dev_private;
1112         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1113
1114         i915_kernel_lost_context(dev);
1115
1116         DRM_DEBUG_DRIVER("\n");
1117
1118         dev_priv->counter++;
1119         if (dev_priv->counter > 0x7FFFFFFFUL)
1120                 dev_priv->counter = 1;
1121         if (master_priv->sarea_priv)
1122                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1123
1124         if (BEGIN_LP_RING(4) == 0) {
1125                 OUT_RING(MI_STORE_DWORD_INDEX);
1126                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1127                 OUT_RING(dev_priv->counter);
1128                 OUT_RING(MI_USER_INTERRUPT);
1129                 ADVANCE_LP_RING();
1130         }
1131
1132         return dev_priv->counter;
1133 }
1134
1135 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1136 {
1137         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1138         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1139
1140         if (dev_priv->trace_irq_seqno == 0)
1141                 render_ring->user_irq_get(render_ring);
1142
1143         dev_priv->trace_irq_seqno = seqno;
1144 }
1145
1146 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1147 {
1148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1150         int ret = 0;
1151         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1152
1153         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1154                   READ_BREADCRUMB(dev_priv));
1155
1156         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1157                 if (master_priv->sarea_priv)
1158                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1159                 return 0;
1160         }
1161
1162         if (master_priv->sarea_priv)
1163                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1164
1165         render_ring->user_irq_get(render_ring);
1166         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1167                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1168         render_ring->user_irq_put(render_ring);
1169
1170         if (ret == -EBUSY) {
1171                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1172                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1173         }
1174
1175         return ret;
1176 }
1177
1178 /* Needs the lock as it touches the ring.
1179  */
1180 int i915_irq_emit(struct drm_device *dev, void *data,
1181                          struct drm_file *file_priv)
1182 {
1183         drm_i915_private_t *dev_priv = dev->dev_private;
1184         drm_i915_irq_emit_t *emit = data;
1185         int result;
1186
1187         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1188                 DRM_ERROR("called with no initialization\n");
1189                 return -EINVAL;
1190         }
1191
1192         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1193
1194         mutex_lock(&dev->struct_mutex);
1195         result = i915_emit_irq(dev);
1196         mutex_unlock(&dev->struct_mutex);
1197
1198         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1199                 DRM_ERROR("copy_to_user\n");
1200                 return -EFAULT;
1201         }
1202
1203         return 0;
1204 }
1205
1206 /* Doesn't need the hardware lock.
1207  */
1208 int i915_irq_wait(struct drm_device *dev, void *data,
1209                          struct drm_file *file_priv)
1210 {
1211         drm_i915_private_t *dev_priv = dev->dev_private;
1212         drm_i915_irq_wait_t *irqwait = data;
1213
1214         if (!dev_priv) {
1215                 DRM_ERROR("called with no initialization\n");
1216                 return -EINVAL;
1217         }
1218
1219         return i915_wait_irq(dev, irqwait->irq_seq);
1220 }
1221
1222 /* Called from drm generic code, passed 'crtc' which
1223  * we use as a pipe index
1224  */
1225 int i915_enable_vblank(struct drm_device *dev, int pipe)
1226 {
1227         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1228         unsigned long irqflags;
1229
1230         if (!i915_pipe_enabled(dev, pipe))
1231                 return -EINVAL;
1232
1233         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1234         if (HAS_PCH_SPLIT(dev))
1235                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1236                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1237         else if (INTEL_INFO(dev)->gen >= 4)
1238                 i915_enable_pipestat(dev_priv, pipe,
1239                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1240         else
1241                 i915_enable_pipestat(dev_priv, pipe,
1242                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1243         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1244         return 0;
1245 }
1246
1247 /* Called from drm generic code, passed 'crtc' which
1248  * we use as a pipe index
1249  */
1250 void i915_disable_vblank(struct drm_device *dev, int pipe)
1251 {
1252         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1253         unsigned long irqflags;
1254
1255         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1256         if (HAS_PCH_SPLIT(dev))
1257                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1258                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1259         else
1260                 i915_disable_pipestat(dev_priv, pipe,
1261                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1262                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1263         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1264 }
1265
1266 void i915_enable_interrupt (struct drm_device *dev)
1267 {
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269
1270         if (!HAS_PCH_SPLIT(dev))
1271                 intel_opregion_enable_asle(dev);
1272         dev_priv->irq_enabled = 1;
1273 }
1274
1275
1276 /* Set the vblank monitor pipe
1277  */
1278 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1279                          struct drm_file *file_priv)
1280 {
1281         drm_i915_private_t *dev_priv = dev->dev_private;
1282
1283         if (!dev_priv) {
1284                 DRM_ERROR("called with no initialization\n");
1285                 return -EINVAL;
1286         }
1287
1288         return 0;
1289 }
1290
1291 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1292                          struct drm_file *file_priv)
1293 {
1294         drm_i915_private_t *dev_priv = dev->dev_private;
1295         drm_i915_vblank_pipe_t *pipe = data;
1296
1297         if (!dev_priv) {
1298                 DRM_ERROR("called with no initialization\n");
1299                 return -EINVAL;
1300         }
1301
1302         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1303
1304         return 0;
1305 }
1306
1307 /**
1308  * Schedule buffer swap at given vertical blank.
1309  */
1310 int i915_vblank_swap(struct drm_device *dev, void *data,
1311                      struct drm_file *file_priv)
1312 {
1313         /* The delayed swap mechanism was fundamentally racy, and has been
1314          * removed.  The model was that the client requested a delayed flip/swap
1315          * from the kernel, then waited for vblank before continuing to perform
1316          * rendering.  The problem was that the kernel might wake the client
1317          * up before it dispatched the vblank swap (since the lock has to be
1318          * held while touching the ringbuffer), in which case the client would
1319          * clear and start the next frame before the swap occurred, and
1320          * flicker would occur in addition to likely missing the vblank.
1321          *
1322          * In the absence of this ioctl, userland falls back to a correct path
1323          * of waiting for a vblank, then dispatching the swap on its own.
1324          * Context switching to userland and back is plenty fast enough for
1325          * meeting the requirements of vblank swapping.
1326          */
1327         return -EINVAL;
1328 }
1329
1330 static u32
1331 ring_last_seqno(struct intel_ring_buffer *ring)
1332 {
1333         return list_entry(ring->request_list.prev,
1334                           struct drm_i915_gem_request, list)->seqno;
1335 }
1336
1337 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1338 {
1339         if (list_empty(&ring->request_list) ||
1340             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1341                 /* Issue a wake-up to catch stuck h/w. */
1342                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1343                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1344                                   ring->name,
1345                                   ring->waiting_seqno,
1346                                   ring->get_seqno(ring));
1347                         wake_up_all(&ring->irq_queue);
1348                         *err = true;
1349                 }
1350                 return true;
1351         }
1352         return false;
1353 }
1354
1355 /**
1356  * This is called when the chip hasn't reported back with completed
1357  * batchbuffers in a long time. The first time this is called we simply record
1358  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1359  * again, we assume the chip is wedged and try to fix it.
1360  */
1361 void i915_hangcheck_elapsed(unsigned long data)
1362 {
1363         struct drm_device *dev = (struct drm_device *)data;
1364         drm_i915_private_t *dev_priv = dev->dev_private;
1365         uint32_t acthd, instdone, instdone1;
1366         bool err = false;
1367
1368         /* If all work is done then ACTHD clearly hasn't advanced. */
1369         if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1370             i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1371             i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1372                 dev_priv->hangcheck_count = 0;
1373                 if (err)
1374                         goto repeat;
1375                 return;
1376         }
1377
1378         if (INTEL_INFO(dev)->gen < 4) {
1379                 acthd = I915_READ(ACTHD);
1380                 instdone = I915_READ(INSTDONE);
1381                 instdone1 = 0;
1382         } else {
1383                 acthd = I915_READ(ACTHD_I965);
1384                 instdone = I915_READ(INSTDONE_I965);
1385                 instdone1 = I915_READ(INSTDONE1);
1386         }
1387
1388         if (dev_priv->last_acthd == acthd &&
1389             dev_priv->last_instdone == instdone &&
1390             dev_priv->last_instdone1 == instdone1) {
1391                 if (dev_priv->hangcheck_count++ > 1) {
1392                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1393
1394                         if (!IS_GEN2(dev)) {
1395                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1396                                  * If so we can simply poke the RB_WAIT bit
1397                                  * and break the hang. This should work on
1398                                  * all but the second generation chipsets.
1399                                  */
1400                                 u32 tmp = I915_READ(PRB0_CTL);
1401                                 if (tmp & RING_WAIT) {
1402                                         I915_WRITE(PRB0_CTL, tmp);
1403                                         POSTING_READ(PRB0_CTL);
1404                                         goto repeat;
1405                                 }
1406                         }
1407
1408                         i915_handle_error(dev, true);
1409                         return;
1410                 }
1411         } else {
1412                 dev_priv->hangcheck_count = 0;
1413
1414                 dev_priv->last_acthd = acthd;
1415                 dev_priv->last_instdone = instdone;
1416                 dev_priv->last_instdone1 = instdone1;
1417         }
1418
1419 repeat:
1420         /* Reset timer case chip hangs without another request being added */
1421         mod_timer(&dev_priv->hangcheck_timer,
1422                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1423 }
1424
1425 /* drm_dma.h hooks
1426 */
1427 static void ironlake_irq_preinstall(struct drm_device *dev)
1428 {
1429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1430
1431         I915_WRITE(HWSTAM, 0xeffe);
1432
1433         /* XXX hotplug from PCH */
1434
1435         I915_WRITE(DEIMR, 0xffffffff);
1436         I915_WRITE(DEIER, 0x0);
1437         (void) I915_READ(DEIER);
1438
1439         /* and GT */
1440         I915_WRITE(GTIMR, 0xffffffff);
1441         I915_WRITE(GTIER, 0x0);
1442         (void) I915_READ(GTIER);
1443
1444         /* south display irq */
1445         I915_WRITE(SDEIMR, 0xffffffff);
1446         I915_WRITE(SDEIER, 0x0);
1447         (void) I915_READ(SDEIER);
1448 }
1449
1450 static int ironlake_irq_postinstall(struct drm_device *dev)
1451 {
1452         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1453         /* enable kind of interrupts always enabled */
1454         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1455                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1456         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1457         u32 hotplug_mask;
1458
1459         dev_priv->irq_mask_reg = ~display_mask;
1460         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1461
1462         /* should always can generate irq */
1463         I915_WRITE(DEIIR, I915_READ(DEIIR));
1464         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1465         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1466         (void) I915_READ(DEIER);
1467
1468         if (IS_GEN6(dev)) {
1469                 render_mask =
1470                         GT_PIPE_NOTIFY |
1471                         GT_GEN6_BSD_USER_INTERRUPT |
1472                         GT_BLT_USER_INTERRUPT;
1473         }
1474
1475         dev_priv->gt_irq_mask_reg = ~render_mask;
1476         dev_priv->gt_irq_enable_reg = render_mask;
1477
1478         I915_WRITE(GTIIR, I915_READ(GTIIR));
1479         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1480         if (IS_GEN6(dev)) {
1481                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1482                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1483                 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1484         }
1485
1486         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1487         (void) I915_READ(GTIER);
1488
1489         if (HAS_PCH_CPT(dev)) {
1490                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1491                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1492         } else {
1493                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1494                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1495         }
1496
1497         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1498         dev_priv->pch_irq_enable_reg = hotplug_mask;
1499
1500         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1501         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1502         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1503         (void) I915_READ(SDEIER);
1504
1505         if (IS_IRONLAKE_M(dev)) {
1506                 /* Clear & enable PCU event interrupts */
1507                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1508                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1509                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1510         }
1511
1512         return 0;
1513 }
1514
1515 void i915_driver_irq_preinstall(struct drm_device * dev)
1516 {
1517         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1518
1519         atomic_set(&dev_priv->irq_received, 0);
1520
1521         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1522         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1523
1524         if (HAS_PCH_SPLIT(dev)) {
1525                 ironlake_irq_preinstall(dev);
1526                 return;
1527         }
1528
1529         if (I915_HAS_HOTPLUG(dev)) {
1530                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1531                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1532         }
1533
1534         I915_WRITE(HWSTAM, 0xeffe);
1535         I915_WRITE(PIPEASTAT, 0);
1536         I915_WRITE(PIPEBSTAT, 0);
1537         I915_WRITE(IMR, 0xffffffff);
1538         I915_WRITE(IER, 0x0);
1539         (void) I915_READ(IER);
1540 }
1541
1542 /*
1543  * Must be called after intel_modeset_init or hotplug interrupts won't be
1544  * enabled correctly.
1545  */
1546 int i915_driver_irq_postinstall(struct drm_device *dev)
1547 {
1548         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1549         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1550         u32 error_mask;
1551
1552         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1553         if (HAS_BSD(dev))
1554                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1555         if (HAS_BLT(dev))
1556                 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1557
1558         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1559
1560         if (HAS_PCH_SPLIT(dev))
1561                 return ironlake_irq_postinstall(dev);
1562
1563         /* Unmask the interrupts that we always want on. */
1564         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1565
1566         dev_priv->pipestat[0] = 0;
1567         dev_priv->pipestat[1] = 0;
1568
1569         if (I915_HAS_HOTPLUG(dev)) {
1570                 /* Enable in IER... */
1571                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1572                 /* and unmask in IMR */
1573                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1574         }
1575
1576         /*
1577          * Enable some error detection, note the instruction error mask
1578          * bit is reserved, so we leave it masked.
1579          */
1580         if (IS_G4X(dev)) {
1581                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1582                                GM45_ERROR_MEM_PRIV |
1583                                GM45_ERROR_CP_PRIV |
1584                                I915_ERROR_MEMORY_REFRESH);
1585         } else {
1586                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1587                                I915_ERROR_MEMORY_REFRESH);
1588         }
1589         I915_WRITE(EMR, error_mask);
1590
1591         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1592         I915_WRITE(IER, enable_mask);
1593         (void) I915_READ(IER);
1594
1595         if (I915_HAS_HOTPLUG(dev)) {
1596                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1597
1598                 /* Note HDMI and DP share bits */
1599                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1600                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1601                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1602                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1603                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1604                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1605                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1606                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1607                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1608                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1609                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1610                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1611
1612                         /* Programming the CRT detection parameters tends
1613                            to generate a spurious hotplug event about three
1614                            seconds later.  So just do it once.
1615                         */
1616                         if (IS_G4X(dev))
1617                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1618                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1619                 }
1620
1621                 /* Ignore TV since it's buggy */
1622
1623                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1624         }
1625
1626         intel_opregion_enable_asle(dev);
1627
1628         return 0;
1629 }
1630
1631 static void ironlake_irq_uninstall(struct drm_device *dev)
1632 {
1633         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1634         I915_WRITE(HWSTAM, 0xffffffff);
1635
1636         I915_WRITE(DEIMR, 0xffffffff);
1637         I915_WRITE(DEIER, 0x0);
1638         I915_WRITE(DEIIR, I915_READ(DEIIR));
1639
1640         I915_WRITE(GTIMR, 0xffffffff);
1641         I915_WRITE(GTIER, 0x0);
1642         I915_WRITE(GTIIR, I915_READ(GTIIR));
1643 }
1644
1645 void i915_driver_irq_uninstall(struct drm_device * dev)
1646 {
1647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1648
1649         if (!dev_priv)
1650                 return;
1651
1652         dev_priv->vblank_pipe = 0;
1653
1654         if (HAS_PCH_SPLIT(dev)) {
1655                 ironlake_irq_uninstall(dev);
1656                 return;
1657         }
1658
1659         if (I915_HAS_HOTPLUG(dev)) {
1660                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1661                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1662         }
1663
1664         I915_WRITE(HWSTAM, 0xffffffff);
1665         I915_WRITE(PIPEASTAT, 0);
1666         I915_WRITE(PIPEBSTAT, 0);
1667         I915_WRITE(IMR, 0xffffffff);
1668         I915_WRITE(IER, 0x0);
1669
1670         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1671         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1672         I915_WRITE(IIR, I915_READ(IIR));
1673 }