drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pm.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pm.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pm.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pm.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pm.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pm.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         u32 reg = PIPESTAT(pipe);
 239         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 240
 241         assert_spin_locked(&dev_priv->irq_lock);
 242
 243         I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                  enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 252                                           DE_PIPEB_FIFO_UNDERRUN;
 253
 254         if (enable)
 255                 ironlake_enable_display_irq(dev_priv, bit);
 256         else
 257                 ironlake_disable_display_irq(dev_priv, bit);
 258 }
 259
 260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 261                                                   enum pipe pipe, bool enable)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         if (enable) {
 265                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 266
 267                 if (!ivb_can_enable_err_int(dev))
 268                         return;
 269
 270                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 271         } else {
 272                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 273
 274                 /* Change the state _after_ we've read out the current one. */
 275                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 276
 277                 if (!was_enabled &&
 278                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 279                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 280                                       pipe_name(pipe));
 281                 }
 282         }
 283 }
 284
 285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 286                                                   enum pipe pipe, bool enable)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289
 290         assert_spin_locked(&dev_priv->irq_lock);
 291
 292         if (enable)
 293                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 294         else
 295                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 296         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 297         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 298 }
 299
 300 /**
 301  * ibx_display_interrupt_update - update SDEIMR
 302  * @dev_priv: driver private
 303  * @interrupt_mask: mask of interrupt bits to update
 304  * @enabled_irq_mask: mask of interrupt bits to enable
 305  */
 306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 307                                          uint32_t interrupt_mask,
 308                                          uint32_t enabled_irq_mask)
 309 {
 310         uint32_t sdeimr = I915_READ(SDEIMR);
 311         sdeimr &= ~interrupt_mask;
 312         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 313
 314         assert_spin_locked(&dev_priv->irq_lock);
 315
 316         if (dev_priv->pm.irqs_disabled &&
 317             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 318                 WARN(1, "IRQs disabled\n");
 319                 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
 320                 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
 321                                                  interrupt_mask);
 322                 return;
 323         }
 324
 325         I915_WRITE(SDEIMR, sdeimr);
 326         POSTING_READ(SDEIMR);
 327 }
 328 #define ibx_enable_display_interrupt(dev_priv, bits) \
 329         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 330 #define ibx_disable_display_interrupt(dev_priv, bits) \
 331         ibx_display_interrupt_update((dev_priv), (bits), 0)
 332
 333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 334                                             enum transcoder pch_transcoder,
 335                                             bool enable)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 339                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 340
 341         if (enable)
 342                 ibx_enable_display_interrupt(dev_priv, bit);
 343         else
 344                 ibx_disable_display_interrupt(dev_priv, bit);
 345 }
 346
 347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 348                                             enum transcoder pch_transcoder,
 349                                             bool enable)
 350 {
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352
 353         if (enable) {
 354                 I915_WRITE(SERR_INT,
 355                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 356
 357                 if (!cpt_can_enable_serr_int(dev))
 358                         return;
 359
 360                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 361         } else {
 362                 uint32_t tmp = I915_READ(SERR_INT);
 363                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 364
 365                 /* Change the state _after_ we've read out the current one. */
 366                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 367
 368                 if (!was_enabled &&
 369                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 370                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 371                                       transcoder_name(pch_transcoder));
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 378  * @dev: drm device
 379  * @pipe: pipe
 380  * @enable: true if we want to report FIFO underrun errors, false otherwise
 381  *
 382  * This function makes us disable or enable CPU fifo underruns for a specific
 383  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 384  * reporting for one pipe may also disable all the other CPU error interruts for
 385  * the other pipes, due to the fact that there's just one interrupt mask/enable
 386  * bit for all the pipes.
 387  *
 388  * Returns the previous state of underrun reporting.
 389  */
 390 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 391                                              enum pipe pipe, bool enable)
 392 {
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 396         bool ret;
 397
 398         assert_spin_locked(&dev_priv->irq_lock);
 399
 400         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 401
 402         if (enable == ret)
 403                 goto done;
 404
 405         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 406
 407         if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
 408                 i9xx_clear_fifo_underrun(dev, pipe);
 409         else if (IS_GEN5(dev) || IS_GEN6(dev))
 410                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 411         else if (IS_GEN7(dev))
 412                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 413         else if (IS_GEN8(dev))
 414                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 415
 416 done:
 417         return ret;
 418 }
 419
 420 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 421                                            enum pipe pipe, bool enable)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         unsigned long flags;
 425         bool ret;
 426
 427         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 428         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 429         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 430
 431         return ret;
 432 }
 433
 434 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 435                                                   enum pipe pipe)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 440
 441         return !intel_crtc->cpu_fifo_underrun_disabled;
 442 }
 443
 444 /**
 445  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 446  * @dev: drm device
 447  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 448  * @enable: true if we want to report FIFO underrun errors, false otherwise
 449  *
 450  * This function makes us disable or enable PCH fifo underruns for a specific
 451  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 452  * underrun reporting for one transcoder may also disable all the other PCH
 453  * error interruts for the other transcoders, due to the fact that there's just
 454  * one interrupt mask/enable bit for all the transcoders.
 455  *
 456  * Returns the previous state of underrun reporting.
 457  */
 458 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 459                                            enum transcoder pch_transcoder,
 460                                            bool enable)
 461 {
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 465         unsigned long flags;
 466         bool ret;
 467
 468         /*
 469          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 470          * has only one pch transcoder A that all pipes can use. To avoid racy
 471          * pch transcoder -> pipe lookups from interrupt code simply store the
 472          * underrun statistics in crtc A. Since we never expose this anywhere
 473          * nor use it outside of the fifo underrun code here using the "wrong"
 474          * crtc on LPT won't cause issues.
 475          */
 476
 477         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 478
 479         ret = !intel_crtc->pch_fifo_underrun_disabled;
 480
 481         if (enable == ret)
 482                 goto done;
 483
 484         intel_crtc->pch_fifo_underrun_disabled = !enable;
 485
 486         if (HAS_PCH_IBX(dev))
 487                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 488         else
 489                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 490
 491 done:
 492         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 493         return ret;
 494 }
 495
 496
 497 static void
 498 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 499                        u32 enable_mask, u32 status_mask)
 500 {
 501         u32 reg = PIPESTAT(pipe);
 502         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 503
 504         assert_spin_locked(&dev_priv->irq_lock);
 505
 506         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 507                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 508                 return;
 509
 510         if ((pipestat & enable_mask) == enable_mask)
 511                 return;
 512
 513         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 514
 515         /* Enable the interrupt, clear any pending status */
 516         pipestat |= enable_mask | status_mask;
 517         I915_WRITE(reg, pipestat);
 518         POSTING_READ(reg);
 519 }
 520
 521 static void
 522 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 523                         u32 enable_mask, u32 status_mask)
 524 {
 525         u32 reg = PIPESTAT(pipe);
 526         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 527
 528         assert_spin_locked(&dev_priv->irq_lock);
 529
 530         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 531                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 532                 return;
 533
 534         if ((pipestat & enable_mask) == 0)
 535                 return;
 536
 537         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 538
 539         pipestat &= ~enable_mask;
 540         I915_WRITE(reg, pipestat);
 541         POSTING_READ(reg);
 542 }
 543
 544 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 545 {
 546         u32 enable_mask = status_mask << 16;
 547
 548         /*
 549          * On pipe A we don't support the PSR interrupt yet, on pipe B the
 550          * same bit MBZ.
 551          */
 552         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 553                 return 0;
 554
 555         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 556                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 557                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 558         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 559                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 560         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 561                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 562
 563         return enable_mask;
 564 }
 565
 566 void
 567 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 568                      u32 status_mask)
 569 {
 570         u32 enable_mask;
 571
 572         if (IS_VALLEYVIEW(dev_priv->dev))
 573                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 574                                                            status_mask);
 575         else
 576                 enable_mask = status_mask << 16;
 577         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 578 }
 579
 580 void
 581 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 582                       u32 status_mask)
 583 {
 584         u32 enable_mask;
 585
 586         if (IS_VALLEYVIEW(dev_priv->dev))
 587                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 588                                                            status_mask);
 589         else
 590                 enable_mask = status_mask << 16;
 591         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 592 }
 593
 594 /**
 595  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 596  */
 597 static void i915_enable_asle_pipestat(struct drm_device *dev)
 598 {
 599         drm_i915_private_t *dev_priv = dev->dev_private;
 600         unsigned long irqflags;
 601
 602         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 603                 return;
 604
 605         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 606
 607         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 608         if (INTEL_INFO(dev)->gen >= 4)
 609                 i915_enable_pipestat(dev_priv, PIPE_A,
 610                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 611
 612         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 613 }
 614
 615 /**
 616  * i915_pipe_enabled - check if a pipe is enabled
 617  * @dev: DRM device
 618  * @pipe: pipe to check
 619  *
 620  * Reading certain registers when the pipe is disabled can hang the chip.
 621  * Use this routine to make sure the PLL is running and the pipe is active
 622  * before reading such registers if unsure.
 623  */
 624 static int
 625 i915_pipe_enabled(struct drm_device *dev, int pipe)
 626 {
 627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 628
 629         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 630                 /* Locking is horribly broken here, but whatever. */
 631                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 632                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 633
 634                 return intel_crtc->active;
 635         } else {
 636                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 637         }
 638 }
 639
 640 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 641 {
 642         /* Gen2 doesn't have a hardware frame counter */
 643         return 0;
 644 }
 645
 646 /* Called from drm generic code, passed a 'crtc', which
 647  * we use as a pipe index
 648  */
 649 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 650 {
 651         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 652         unsigned long high_frame;
 653         unsigned long low_frame;
 654         u32 high1, high2, low, pixel, vbl_start;
 655
 656         if (!i915_pipe_enabled(dev, pipe)) {
 657                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 658                                 "pipe %c\n", pipe_name(pipe));
 659                 return 0;
 660         }
 661
 662         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 663                 struct intel_crtc *intel_crtc =
 664                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 665                 const struct drm_display_mode *mode =
 666                         &intel_crtc->config.adjusted_mode;
 667
 668                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 669         } else {
 670                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 671                 u32 htotal;
 672
 673                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 674                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 675
 676                 vbl_start *= htotal;
 677         }
 678
 679         high_frame = PIPEFRAME(pipe);
 680         low_frame = PIPEFRAMEPIXEL(pipe);
 681
 682         /*
 683          * High & low register fields aren't synchronized, so make sure
 684          * we get a low value that's stable across two reads of the high
 685          * register.
 686          */
 687         do {
 688                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 689                 low   = I915_READ(low_frame);
 690                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 691         } while (high1 != high2);
 692
 693         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 694         pixel = low & PIPE_PIXEL_MASK;
 695         low >>= PIPE_FRAME_LOW_SHIFT;
 696
 697         /*
 698          * The frame counter increments at beginning of active.
 699          * Cook up a vblank counter by also checking the pixel
 700          * counter against vblank start.
 701          */
 702         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 703 }
 704
 705 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 706 {
 707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 708         int reg = PIPE_FRMCOUNT_GM45(pipe);
 709
 710         if (!i915_pipe_enabled(dev, pipe)) {
 711                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 712                                  "pipe %c\n", pipe_name(pipe));
 713                 return 0;
 714         }
 715
 716         return I915_READ(reg);
 717 }
 718
 719 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 720 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 721 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 722
 723 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 724 {
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         uint32_t status;
 727
 728         if (INTEL_INFO(dev)->gen < 7) {
 729                 status = pipe == PIPE_A ?
 730                         DE_PIPEA_VBLANK :
 731                         DE_PIPEB_VBLANK;
 732         } else {
 733                 switch (pipe) {
 734                 default:
 735                 case PIPE_A:
 736                         status = DE_PIPEA_VBLANK_IVB;
 737                         break;
 738                 case PIPE_B:
 739                         status = DE_PIPEB_VBLANK_IVB;
 740                         break;
 741                 case PIPE_C:
 742                         status = DE_PIPEC_VBLANK_IVB;
 743                         break;
 744                 }
 745         }
 746
 747         return __raw_i915_read32(dev_priv, DEISR) & status;
 748 }
 749
 750 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 751                                     unsigned int flags, int *vpos, int *hpos,
 752                                     ktime_t *stime, ktime_t *etime)
 753 {
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 758         int position;
 759         int vbl_start, vbl_end, htotal, vtotal;
 760         bool in_vbl = true;
 761         int ret = 0;
 762         unsigned long irqflags;
 763
 764         if (!intel_crtc->active) {
 765                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 766                                  "pipe %c\n", pipe_name(pipe));
 767                 return 0;
 768         }
 769
 770         htotal = mode->crtc_htotal;
 771         vtotal = mode->crtc_vtotal;
 772         vbl_start = mode->crtc_vblank_start;
 773         vbl_end = mode->crtc_vblank_end;
 774
 775         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 776                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 777                 vbl_end /= 2;
 778                 vtotal /= 2;
 779         }
 780
 781         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 782
 783         /*
 784          * Lock uncore.lock, as we will do multiple timing critical raw
 785          * register reads, potentially with preemption disabled, so the
 786          * following code must not block on uncore.lock.
 787          */
 788         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 789
 790         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 791
 792         /* Get optional system timestamp before query. */
 793         if (stime)
 794                 *stime = ktime_get();
 795
 796         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 797                 /* No obvious pixelcount register. Only query vertical
 798                  * scanout position from Display scan line register.
 799                  */
 800                 if (IS_GEN2(dev))
 801                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 802                 else
 803                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 804
 805                 if (HAS_PCH_SPLIT(dev)) {
 806                         /*
 807                          * The scanline counter increments at the leading edge
 808                          * of hsync, ie. it completely misses the active portion
 809                          * of the line. Fix up the counter at both edges of vblank
 810                          * to get a more accurate picture whether we're in vblank
 811                          * or not.
 812                          */
 813                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 814                         if ((in_vbl && position == vbl_start - 1) ||
 815                             (!in_vbl && position == vbl_end - 1))
 816                                 position = (position + 1) % vtotal;
 817                 } else {
 818                         /*
 819                          * ISR vblank status bits don't work the way we'd want
 820                          * them to work on non-PCH platforms (for
 821                          * ilk_pipe_in_vblank_locked()), and there doesn't
 822                          * appear any other way to determine if we're currently
 823                          * in vblank.
 824                          *
 825                          * Instead let's assume that we're already in vblank if
 826                          * we got called from the vblank interrupt and the
 827                          * scanline counter value indicates that we're on the
 828                          * line just prior to vblank start. This should result
 829                          * in the correct answer, unless the vblank interrupt
 830                          * delivery really got delayed for almost exactly one
 831                          * full frame/field.
 832                          */
 833                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 834                             position == vbl_start - 1) {
 835                                 position = (position + 1) % vtotal;
 836
 837                                 /* Signal this correction as "applied". */
 838                                 ret |= 0x8;
 839                         }
 840                 }
 841         } else {
 842                 /* Have access to pixelcount since start of frame.
 843                  * We can split this into vertical and horizontal
 844                  * scanout position.
 845                  */
 846                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 847
 848                 /* convert to pixel counts */
 849                 vbl_start *= htotal;
 850                 vbl_end *= htotal;
 851                 vtotal *= htotal;
 852         }
 853
 854         /* Get optional system timestamp after query. */
 855         if (etime)
 856                 *etime = ktime_get();
 857
 858         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 859
 860         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 861
 862         in_vbl = position >= vbl_start && position < vbl_end;
 863
 864         /*
 865          * While in vblank, position will be negative
 866          * counting up towards 0 at vbl_end. And outside
 867          * vblank, position will be positive counting
 868          * up since vbl_end.
 869          */
 870         if (position >= vbl_start)
 871                 position -= vbl_end;
 872         else
 873                 position += vtotal - vbl_end;
 874
 875         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 876                 *vpos = position;
 877                 *hpos = 0;
 878         } else {
 879                 *vpos = position / htotal;
 880                 *hpos = position - (*vpos * htotal);
 881         }
 882
 883         /* In vblank? */
 884         if (in_vbl)
 885                 ret |= DRM_SCANOUTPOS_INVBL;
 886
 887         return ret;
 888 }
 889
 890 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 891                               int *max_error,
 892                               struct timeval *vblank_time,
 893                               unsigned flags)
 894 {
 895         struct drm_crtc *crtc;
 896
 897         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 898                 DRM_ERROR("Invalid crtc %d\n", pipe);
 899                 return -EINVAL;
 900         }
 901
 902         /* Get drm_crtc to timestamp: */
 903         crtc = intel_get_crtc_for_pipe(dev, pipe);
 904         if (crtc == NULL) {
 905                 DRM_ERROR("Invalid crtc %d\n", pipe);
 906                 return -EINVAL;
 907         }
 908
 909         if (!crtc->enabled) {
 910                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 911                 return -EBUSY;
 912         }
 913
 914         /* Helper routine in DRM core does all the work: */
 915         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 916                                                      vblank_time, flags,
 917                                                      crtc,
 918                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 919 }
 920
 921 static bool intel_hpd_irq_event(struct drm_device *dev,
 922                                 struct drm_connector *connector)
 923 {
 924         enum drm_connector_status old_status;
 925
 926         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 927         old_status = connector->status;
 928
 929         connector->status = connector->funcs->detect(connector, false);
 930         if (old_status == connector->status)
 931                 return false;
 932
 933         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 934                       connector->base.id,
 935                       drm_get_connector_name(connector),
 936                       drm_get_connector_status_name(old_status),
 937                       drm_get_connector_status_name(connector->status));
 938
 939         return true;
 940 }
 941
 942 /*
 943  * Handle hotplug events outside the interrupt handler proper.
 944  */
 945 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 946
 947 static void i915_hotplug_work_func(struct work_struct *work)
 948 {
 949         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 950                                                     hotplug_work);
 951         struct drm_device *dev = dev_priv->dev;
 952         struct drm_mode_config *mode_config = &dev->mode_config;
 953         struct intel_connector *intel_connector;
 954         struct intel_encoder *intel_encoder;
 955         struct drm_connector *connector;
 956         unsigned long irqflags;
 957         bool hpd_disabled = false;
 958         bool changed = false;
 959         u32 hpd_event_bits;
 960
 961         /* HPD irq before everything is fully set up. */
 962         if (!dev_priv->enable_hotplug_processing)
 963                 return;
 964
 965         mutex_lock(&mode_config->mutex);
 966         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 967
 968         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 969
 970         hpd_event_bits = dev_priv->hpd_event_bits;
 971         dev_priv->hpd_event_bits = 0;
 972         list_for_each_entry(connector, &mode_config->connector_list, head) {
 973                 intel_connector = to_intel_connector(connector);
 974                 intel_encoder = intel_connector->encoder;
 975                 if (intel_encoder->hpd_pin > HPD_NONE &&
 976                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 977                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 978                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 979                                  "switching from hotplug detection to polling\n",
 980                                 drm_get_connector_name(connector));
 981                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 982                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 983                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 984                         hpd_disabled = true;
 985                 }
 986                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 987                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 988                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 989                 }
 990         }
 991          /* if there were no outputs to poll, poll was disabled,
 992           * therefore make sure it's enabled when disabling HPD on
 993           * some connectors */
 994         if (hpd_disabled) {
 995                 drm_kms_helper_poll_enable(dev);
 996                 mod_timer(&dev_priv->hotplug_reenable_timer,
 997                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 998         }
 999
1000         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1001
1002         list_for_each_entry(connector, &mode_config->connector_list, head) {
1003                 intel_connector = to_intel_connector(connector);
1004                 intel_encoder = intel_connector->encoder;
1005                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1006                         if (intel_encoder->hot_plug)
1007                                 intel_encoder->hot_plug(intel_encoder);
1008                         if (intel_hpd_irq_event(dev, connector))
1009                                 changed = true;
1010                 }
1011         }
1012         mutex_unlock(&mode_config->mutex);
1013
1014         if (changed)
1015                 drm_kms_helper_hotplug_event(dev);
1016 }
1017
1018 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1019 {
1020         del_timer_sync(&dev_priv->hotplug_reenable_timer);
1021 }
1022
1023 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1024 {
1025         drm_i915_private_t *dev_priv = dev->dev_private;
1026         u32 busy_up, busy_down, max_avg, min_avg;
1027         u8 new_delay;
1028
1029         spin_lock(&mchdev_lock);
1030
1031         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1032
1033         new_delay = dev_priv->ips.cur_delay;
1034
1035         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1036         busy_up = I915_READ(RCPREVBSYTUPAVG);
1037         busy_down = I915_READ(RCPREVBSYTDNAVG);
1038         max_avg = I915_READ(RCBMAXAVG);
1039         min_avg = I915_READ(RCBMINAVG);
1040
1041         /* Handle RCS change request from hw */
1042         if (busy_up > max_avg) {
1043                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1044                         new_delay = dev_priv->ips.cur_delay - 1;
1045                 if (new_delay < dev_priv->ips.max_delay)
1046                         new_delay = dev_priv->ips.max_delay;
1047         } else if (busy_down < min_avg) {
1048                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1049                         new_delay = dev_priv->ips.cur_delay + 1;
1050                 if (new_delay > dev_priv->ips.min_delay)
1051                         new_delay = dev_priv->ips.min_delay;
1052         }
1053
1054         if (ironlake_set_drps(dev, new_delay))
1055                 dev_priv->ips.cur_delay = new_delay;
1056
1057         spin_unlock(&mchdev_lock);
1058
1059         return;
1060 }
1061
1062 static void notify_ring(struct drm_device *dev,
1063                         struct intel_ring_buffer *ring)
1064 {
1065         if (ring->obj == NULL)
1066                 return;
1067
1068         trace_i915_gem_request_complete(ring);
1069
1070         wake_up_all(&ring->irq_queue);
1071         i915_queue_hangcheck(dev);
1072 }
1073
1074 void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1075                              u32 pm_iir, int new_delay)
1076 {
1077         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1078                 if (new_delay >= dev_priv->rps.max_freq_softlimit) {
1079                         /* Mask UP THRESHOLD Interrupts */
1080                         I915_WRITE(GEN6_PMINTRMSK,
1081                                    I915_READ(GEN6_PMINTRMSK) |
1082                                    GEN6_PM_RP_UP_THRESHOLD);
1083                         dev_priv->rps.rp_up_masked = true;
1084                 }
1085                 if (dev_priv->rps.rp_down_masked) {
1086                         /* UnMask DOWN THRESHOLD Interrupts */
1087                         I915_WRITE(GEN6_PMINTRMSK,
1088                                    I915_READ(GEN6_PMINTRMSK) &
1089                                    ~GEN6_PM_RP_DOWN_THRESHOLD);
1090                         dev_priv->rps.rp_down_masked = false;
1091                 }
1092         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1093                 if (new_delay <= dev_priv->rps.min_freq_softlimit) {
1094                         /* Mask DOWN THRESHOLD Interrupts */
1095                         I915_WRITE(GEN6_PMINTRMSK,
1096                                    I915_READ(GEN6_PMINTRMSK) |
1097                                    GEN6_PM_RP_DOWN_THRESHOLD);
1098                         dev_priv->rps.rp_down_masked = true;
1099                 }
1100
1101                 if (dev_priv->rps.rp_up_masked) {
1102                         /* UnMask UP THRESHOLD Interrupts */
1103                         I915_WRITE(GEN6_PMINTRMSK,
1104                                    I915_READ(GEN6_PMINTRMSK) &
1105                                    ~GEN6_PM_RP_UP_THRESHOLD);
1106                         dev_priv->rps.rp_up_masked = false;
1107                 }
1108         }
1109 }
1110
1111 static void gen6_pm_rps_work(struct work_struct *work)
1112 {
1113         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1114                                                     rps.work);
1115         u32 pm_iir;
1116         int new_delay, adj;
1117
1118         spin_lock_irq(&dev_priv->irq_lock);
1119         pm_iir = dev_priv->rps.pm_iir;
1120         dev_priv->rps.pm_iir = 0;
1121         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1122         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1123         spin_unlock_irq(&dev_priv->irq_lock);
1124
1125         /* Make sure we didn't queue anything we're not going to process. */
1126         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1127
1128         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1129                 return;
1130
1131         mutex_lock(&dev_priv->rps.hw_lock);
1132
1133         adj = dev_priv->rps.last_adj;
1134         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1135                 if (adj > 0)
1136                         adj *= 2;
1137                 else
1138                         adj = 1;
1139                 new_delay = dev_priv->rps.cur_freq + adj;
1140
1141                 /*
1142                  * For better performance, jump directly
1143                  * to RPe if we're below it.
1144                  */
1145                 if (new_delay < dev_priv->rps.efficient_freq)
1146                         new_delay = dev_priv->rps.efficient_freq;
1147         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1148                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1149                         new_delay = dev_priv->rps.efficient_freq;
1150                 else
1151                         new_delay = dev_priv->rps.min_freq_softlimit;
1152                 adj = 0;
1153         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1154                 if (adj < 0)
1155                         adj *= 2;
1156                 else
1157                         adj = -1;
1158                 new_delay = dev_priv->rps.cur_freq + adj;
1159         } else { /* unknown event */
1160                 new_delay = dev_priv->rps.cur_freq;
1161         }
1162
1163         /* sysfs frequency interfaces may have snuck in while servicing the
1164          * interrupt
1165          */
1166         new_delay = clamp_t(int, new_delay,
1167                             dev_priv->rps.min_freq_softlimit,
1168                             dev_priv->rps.max_freq_softlimit);
1169
1170         gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1171         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1172
1173         if (IS_VALLEYVIEW(dev_priv->dev))
1174                 valleyview_set_rps(dev_priv->dev, new_delay);
1175         else
1176                 gen6_set_rps(dev_priv->dev, new_delay);
1177
1178         mutex_unlock(&dev_priv->rps.hw_lock);
1179 }
1180
1181
1182 /**
1183  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1184  * occurred.
1185  * @work: workqueue struct
1186  *
1187  * Doesn't actually do anything except notify userspace. As a consequence of
1188  * this event, userspace should try to remap the bad rows since statistically
1189  * it is likely the same row is more likely to go bad again.
1190  */
1191 static void ivybridge_parity_work(struct work_struct *work)
1192 {
1193         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1194                                                     l3_parity.error_work);
1195         u32 error_status, row, bank, subbank;
1196         char *parity_event[6];
1197         uint32_t misccpctl;
1198         unsigned long flags;
1199         uint8_t slice = 0;
1200
1201         /* We must turn off DOP level clock gating to access the L3 registers.
1202          * In order to prevent a get/put style interface, acquire struct mutex
1203          * any time we access those registers.
1204          */
1205         mutex_lock(&dev_priv->dev->struct_mutex);
1206
1207         /* If we've screwed up tracking, just let the interrupt fire again */
1208         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1209                 goto out;
1210
1211         misccpctl = I915_READ(GEN7_MISCCPCTL);
1212         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1213         POSTING_READ(GEN7_MISCCPCTL);
1214
1215         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1216                 u32 reg;
1217
1218                 slice--;
1219                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1220                         break;
1221
1222                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1223
1224                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1225
1226                 error_status = I915_READ(reg);
1227                 row = GEN7_PARITY_ERROR_ROW(error_status);
1228                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1229                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1230
1231                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1232                 POSTING_READ(reg);
1233
1234                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1235                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1236                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1237                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1238                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1239                 parity_event[5] = NULL;
1240
1241                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1242                                    KOBJ_CHANGE, parity_event);
1243
1244                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1245                           slice, row, bank, subbank);
1246
1247                 kfree(parity_event[4]);
1248                 kfree(parity_event[3]);
1249                 kfree(parity_event[2]);
1250                 kfree(parity_event[1]);
1251         }
1252
1253         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1254
1255 out:
1256         WARN_ON(dev_priv->l3_parity.which_slice);
1257         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1258         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1259         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1260
1261         mutex_unlock(&dev_priv->dev->struct_mutex);
1262 }
1263
1264 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1265 {
1266         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1267
1268         if (!HAS_L3_DPF(dev))
1269                 return;
1270
1271         spin_lock(&dev_priv->irq_lock);
1272         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1273         spin_unlock(&dev_priv->irq_lock);
1274
1275         iir &= GT_PARITY_ERROR(dev);
1276         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1277                 dev_priv->l3_parity.which_slice |= 1 << 1;
1278
1279         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1280                 dev_priv->l3_parity.which_slice |= 1 << 0;
1281
1282         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1283 }
1284
1285 static void ilk_gt_irq_handler(struct drm_device *dev,
1286                                struct drm_i915_private *dev_priv,
1287                                u32 gt_iir)
1288 {
1289         if (gt_iir &
1290             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1291                 notify_ring(dev, &dev_priv->ring[RCS]);
1292         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1293                 notify_ring(dev, &dev_priv->ring[VCS]);
1294 }
1295
1296 static void snb_gt_irq_handler(struct drm_device *dev,
1297                                struct drm_i915_private *dev_priv,
1298                                u32 gt_iir)
1299 {
1300
1301         if (gt_iir &
1302             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1303                 notify_ring(dev, &dev_priv->ring[RCS]);
1304         if (gt_iir & GT_BSD_USER_INTERRUPT)
1305                 notify_ring(dev, &dev_priv->ring[VCS]);
1306         if (gt_iir & GT_BLT_USER_INTERRUPT)
1307                 notify_ring(dev, &dev_priv->ring[BCS]);
1308
1309         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1310                       GT_BSD_CS_ERROR_INTERRUPT |
1311                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1312                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1313                                   gt_iir);
1314         }
1315
1316         if (gt_iir & GT_PARITY_ERROR(dev))
1317                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1318 }
1319
1320 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1321                                        struct drm_i915_private *dev_priv,
1322                                        u32 master_ctl)
1323 {
1324         u32 rcs, bcs, vcs;
1325         uint32_t tmp = 0;
1326         irqreturn_t ret = IRQ_NONE;
1327
1328         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1329                 tmp = I915_READ(GEN8_GT_IIR(0));
1330                 if (tmp) {
1331                         ret = IRQ_HANDLED;
1332                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1333                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1334                         if (rcs & GT_RENDER_USER_INTERRUPT)
1335                                 notify_ring(dev, &dev_priv->ring[RCS]);
1336                         if (bcs & GT_RENDER_USER_INTERRUPT)
1337                                 notify_ring(dev, &dev_priv->ring[BCS]);
1338                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1339                 } else
1340                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1341         }
1342
1343         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1344                 tmp = I915_READ(GEN8_GT_IIR(1));
1345                 if (tmp) {
1346                         ret = IRQ_HANDLED;
1347                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1348                         if (vcs & GT_RENDER_USER_INTERRUPT)
1349                                 notify_ring(dev, &dev_priv->ring[VCS]);
1350                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1351                 } else
1352                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1353         }
1354
1355         if (master_ctl & GEN8_GT_VECS_IRQ) {
1356                 tmp = I915_READ(GEN8_GT_IIR(3));
1357                 if (tmp) {
1358                         ret = IRQ_HANDLED;
1359                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1360                         if (vcs & GT_RENDER_USER_INTERRUPT)
1361                                 notify_ring(dev, &dev_priv->ring[VECS]);
1362                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1363                 } else
1364                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1365         }
1366
1367         return ret;
1368 }
1369
1370 #define HPD_STORM_DETECT_PERIOD 1000
1371 #define HPD_STORM_THRESHOLD 5
1372
1373 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1374                                          u32 hotplug_trigger,
1375                                          const u32 *hpd)
1376 {
1377         drm_i915_private_t *dev_priv = dev->dev_private;
1378         int i;
1379         bool storm_detected = false;
1380
1381         if (!hotplug_trigger)
1382                 return;
1383
1384         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1385                           hotplug_trigger);
1386
1387         spin_lock(&dev_priv->irq_lock);
1388         for (i = 1; i < HPD_NUM_PINS; i++) {
1389
1390                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1391                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1392                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1393                           hotplug_trigger, i, hpd[i]);
1394
1395                 if (!(hpd[i] & hotplug_trigger) ||
1396                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1397                         continue;
1398
1399                 dev_priv->hpd_event_bits |= (1 << i);
1400                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1401                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1402                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1403                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1404                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1405                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1406                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1407                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1408                         dev_priv->hpd_event_bits &= ~(1 << i);
1409                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1410                         storm_detected = true;
1411                 } else {
1412                         dev_priv->hpd_stats[i].hpd_cnt++;
1413                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1414                                       dev_priv->hpd_stats[i].hpd_cnt);
1415                 }
1416         }
1417
1418         if (storm_detected)
1419                 dev_priv->display.hpd_irq_setup(dev);
1420         spin_unlock(&dev_priv->irq_lock);
1421
1422         /*
1423          * Our hotplug handler can grab modeset locks (by calling down into the
1424          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1425          * queue for otherwise the flush_work in the pageflip code will
1426          * deadlock.
1427          */
1428         schedule_work(&dev_priv->hotplug_work);
1429 }
1430
1431 static void gmbus_irq_handler(struct drm_device *dev)
1432 {
1433         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1434
1435         wake_up_all(&dev_priv->gmbus_wait_queue);
1436 }
1437
1438 static void dp_aux_irq_handler(struct drm_device *dev)
1439 {
1440         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1441
1442         wake_up_all(&dev_priv->gmbus_wait_queue);
1443 }
1444
1445 #if defined(CONFIG_DEBUG_FS)
1446 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1447                                          uint32_t crc0, uint32_t crc1,
1448                                          uint32_t crc2, uint32_t crc3,
1449                                          uint32_t crc4)
1450 {
1451         struct drm_i915_private *dev_priv = dev->dev_private;
1452         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1453         struct intel_pipe_crc_entry *entry;
1454         int head, tail;
1455
1456         spin_lock(&pipe_crc->lock);
1457
1458         if (!pipe_crc->entries) {
1459                 spin_unlock(&pipe_crc->lock);
1460                 DRM_ERROR("spurious interrupt\n");
1461                 return;
1462         }
1463
1464         head = pipe_crc->head;
1465         tail = pipe_crc->tail;
1466
1467         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1468                 spin_unlock(&pipe_crc->lock);
1469                 DRM_ERROR("CRC buffer overflowing\n");
1470                 return;
1471         }
1472
1473         entry = &pipe_crc->entries[head];
1474
1475         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1476         entry->crc[0] = crc0;
1477         entry->crc[1] = crc1;
1478         entry->crc[2] = crc2;
1479         entry->crc[3] = crc3;
1480         entry->crc[4] = crc4;
1481
1482         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1483         pipe_crc->head = head;
1484
1485         spin_unlock(&pipe_crc->lock);
1486
1487         wake_up_interruptible(&pipe_crc->wq);
1488 }
1489 #else
1490 static inline void
1491 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1492                              uint32_t crc0, uint32_t crc1,
1493                              uint32_t crc2, uint32_t crc3,
1494                              uint32_t crc4) {}
1495 #endif
1496
1497
1498 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1499 {
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501
1502         display_pipe_crc_irq_handler(dev, pipe,
1503                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1504                                      0, 0, 0, 0);
1505 }
1506
1507 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510
1511         display_pipe_crc_irq_handler(dev, pipe,
1512                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1513                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1514                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1515                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1516                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1517 }
1518
1519 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1520 {
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522         uint32_t res1, res2;
1523
1524         if (INTEL_INFO(dev)->gen >= 3)
1525                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1526         else
1527                 res1 = 0;
1528
1529         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1530                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1531         else
1532                 res2 = 0;
1533
1534         display_pipe_crc_irq_handler(dev, pipe,
1535                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1536                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1537                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1538                                      res1, res2);
1539 }
1540
1541 /* The RPS events need forcewake, so we add them to a work queue and mask their
1542  * IMR bits until the work is done. Other interrupts can be processed without
1543  * the work queue. */
1544 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1545 {
1546         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1547                 spin_lock(&dev_priv->irq_lock);
1548                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1549                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1550                 spin_unlock(&dev_priv->irq_lock);
1551
1552                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1553         }
1554
1555         if (HAS_VEBOX(dev_priv->dev)) {
1556                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1557                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1558
1559                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1560                         i915_handle_error(dev_priv->dev, false,
1561                                           "VEBOX CS error interrupt 0x%08x",
1562                                           pm_iir);
1563                 }
1564         }
1565 }
1566
1567 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1568 {
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         u32 pipe_stats[I915_MAX_PIPES] = { };
1571         int pipe;
1572
1573         spin_lock(&dev_priv->irq_lock);
1574         for_each_pipe(pipe) {
1575                 int reg;
1576                 u32 mask, iir_bit = 0;
1577
1578                 /*
1579                  * PIPESTAT bits get signalled even when the interrupt is
1580                  * disabled with the mask bits, and some of the status bits do
1581                  * not generate interrupts at all (like the underrun bit). Hence
1582                  * we need to be careful that we only handle what we want to
1583                  * handle.
1584                  */
1585                 mask = 0;
1586                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1587                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
1588
1589                 switch (pipe) {
1590                 case PIPE_A:
1591                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1592                         break;
1593                 case PIPE_B:
1594                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1595                         break;
1596                 }
1597                 if (iir & iir_bit)
1598                         mask |= dev_priv->pipestat_irq_mask[pipe];
1599
1600                 if (!mask)
1601                         continue;
1602
1603                 reg = PIPESTAT(pipe);
1604                 mask |= PIPESTAT_INT_ENABLE_MASK;
1605                 pipe_stats[pipe] = I915_READ(reg) & mask;
1606
1607                 /*
1608                  * Clear the PIPE*STAT regs before the IIR
1609                  */
1610                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1611                                         PIPESTAT_INT_STATUS_MASK))
1612                         I915_WRITE(reg, pipe_stats[pipe]);
1613         }
1614         spin_unlock(&dev_priv->irq_lock);
1615
1616         for_each_pipe(pipe) {
1617                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1618                         drm_handle_vblank(dev, pipe);
1619
1620                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1621                         intel_prepare_page_flip(dev, pipe);
1622                         intel_finish_page_flip(dev, pipe);
1623                 }
1624
1625                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1626                         i9xx_pipe_crc_irq_handler(dev, pipe);
1627
1628                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1629                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1630                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1631         }
1632
1633         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1634                 gmbus_irq_handler(dev);
1635 }
1636
1637 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1638 {
1639         struct drm_device *dev = (struct drm_device *) arg;
1640         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1641         u32 iir, gt_iir, pm_iir;
1642         irqreturn_t ret = IRQ_NONE;
1643
1644         while (true) {
1645                 iir = I915_READ(VLV_IIR);
1646                 gt_iir = I915_READ(GTIIR);
1647                 pm_iir = I915_READ(GEN6_PMIIR);
1648
1649                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1650                         goto out;
1651
1652                 ret = IRQ_HANDLED;
1653
1654                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1655
1656                 valleyview_pipestat_irq_handler(dev, iir);
1657
1658                 /* Consume port.  Then clear IIR or we'll miss events */
1659                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1660                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1661                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1662
1663                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1664
1665                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1666                                 dp_aux_irq_handler(dev);
1667
1668                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1669                         I915_READ(PORT_HOTPLUG_STAT);
1670                 }
1671
1672
1673                 if (pm_iir)
1674                         gen6_rps_irq_handler(dev_priv, pm_iir);
1675
1676                 I915_WRITE(GTIIR, gt_iir);
1677                 I915_WRITE(GEN6_PMIIR, pm_iir);
1678                 I915_WRITE(VLV_IIR, iir);
1679         }
1680
1681 out:
1682         return ret;
1683 }
1684
1685 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1686 {
1687         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1688         int pipe;
1689         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1690
1691         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1692
1693         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1694                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1695                                SDE_AUDIO_POWER_SHIFT);
1696                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1697                                  port_name(port));
1698         }
1699
1700         if (pch_iir & SDE_AUX_MASK)
1701                 dp_aux_irq_handler(dev);
1702
1703         if (pch_iir & SDE_GMBUS)
1704                 gmbus_irq_handler(dev);
1705
1706         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1707                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1708
1709         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1710                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1711
1712         if (pch_iir & SDE_POISON)
1713                 DRM_ERROR("PCH poison interrupt\n");
1714
1715         if (pch_iir & SDE_FDI_MASK)
1716                 for_each_pipe(pipe)
1717                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1718                                          pipe_name(pipe),
1719                                          I915_READ(FDI_RX_IIR(pipe)));
1720
1721         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1722                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1723
1724         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1725                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1726
1727         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1728                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1729                                                           false))
1730                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1731
1732         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1733                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1734                                                           false))
1735                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1736 }
1737
1738 static void ivb_err_int_handler(struct drm_device *dev)
1739 {
1740         struct drm_i915_private *dev_priv = dev->dev_private;
1741         u32 err_int = I915_READ(GEN7_ERR_INT);
1742         enum pipe pipe;
1743
1744         if (err_int & ERR_INT_POISON)
1745                 DRM_ERROR("Poison interrupt\n");
1746
1747         for_each_pipe(pipe) {
1748                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1749                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1750                                                                   false))
1751                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1752                                           pipe_name(pipe));
1753                 }
1754
1755                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1756                         if (IS_IVYBRIDGE(dev))
1757                                 ivb_pipe_crc_irq_handler(dev, pipe);
1758                         else
1759                                 hsw_pipe_crc_irq_handler(dev, pipe);
1760                 }
1761         }
1762
1763         I915_WRITE(GEN7_ERR_INT, err_int);
1764 }
1765
1766 static void cpt_serr_int_handler(struct drm_device *dev)
1767 {
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         u32 serr_int = I915_READ(SERR_INT);
1770
1771         if (serr_int & SERR_INT_POISON)
1772                 DRM_ERROR("PCH poison interrupt\n");
1773
1774         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1775                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1776                                                           false))
1777                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1778
1779         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1780                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1781                                                           false))
1782                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1783
1784         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1785                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1786                                                           false))
1787                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
1788
1789         I915_WRITE(SERR_INT, serr_int);
1790 }
1791
1792 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1793 {
1794         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795         int pipe;
1796         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1797
1798         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1799
1800         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1801                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1802                                SDE_AUDIO_POWER_SHIFT_CPT);
1803                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1804                                  port_name(port));
1805         }
1806
1807         if (pch_iir & SDE_AUX_MASK_CPT)
1808                 dp_aux_irq_handler(dev);
1809
1810         if (pch_iir & SDE_GMBUS_CPT)
1811                 gmbus_irq_handler(dev);
1812
1813         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1814                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1815
1816         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1817                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1818
1819         if (pch_iir & SDE_FDI_MASK_CPT)
1820                 for_each_pipe(pipe)
1821                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1822                                          pipe_name(pipe),
1823                                          I915_READ(FDI_RX_IIR(pipe)));
1824
1825         if (pch_iir & SDE_ERROR_CPT)
1826                 cpt_serr_int_handler(dev);
1827 }
1828
1829 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1830 {
1831         struct drm_i915_private *dev_priv = dev->dev_private;
1832         enum pipe pipe;
1833
1834         if (de_iir & DE_AUX_CHANNEL_A)
1835                 dp_aux_irq_handler(dev);
1836
1837         if (de_iir & DE_GSE)
1838                 intel_opregion_asle_intr(dev);
1839
1840         if (de_iir & DE_POISON)
1841                 DRM_ERROR("Poison interrupt\n");
1842
1843         for_each_pipe(pipe) {
1844                 if (de_iir & DE_PIPE_VBLANK(pipe))
1845                         drm_handle_vblank(dev, pipe);
1846
1847                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1848                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1849                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1850                                           pipe_name(pipe));
1851
1852                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1853                         i9xx_pipe_crc_irq_handler(dev, pipe);
1854
1855                 /* plane/pipes map 1:1 on ilk+ */
1856                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1857                         intel_prepare_page_flip(dev, pipe);
1858                         intel_finish_page_flip_plane(dev, pipe);
1859                 }
1860         }
1861
1862         /* check event from PCH */
1863         if (de_iir & DE_PCH_EVENT) {
1864                 u32 pch_iir = I915_READ(SDEIIR);
1865
1866                 if (HAS_PCH_CPT(dev))
1867                         cpt_irq_handler(dev, pch_iir);
1868                 else
1869                         ibx_irq_handler(dev, pch_iir);
1870
1871                 /* should clear PCH hotplug event before clear CPU irq */
1872                 I915_WRITE(SDEIIR, pch_iir);
1873         }
1874
1875         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1876                 ironlake_rps_change_irq_handler(dev);
1877 }
1878
1879 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1880 {
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         enum pipe pipe;
1883
1884         if (de_iir & DE_ERR_INT_IVB)
1885                 ivb_err_int_handler(dev);
1886
1887         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1888                 dp_aux_irq_handler(dev);
1889
1890         if (de_iir & DE_GSE_IVB)
1891                 intel_opregion_asle_intr(dev);
1892
1893         for_each_pipe(pipe) {
1894                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1895                         drm_handle_vblank(dev, pipe);
1896
1897                 /* plane/pipes map 1:1 on ilk+ */
1898                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1899                         intel_prepare_page_flip(dev, pipe);
1900                         intel_finish_page_flip_plane(dev, pipe);
1901                 }
1902         }
1903
1904         /* check event from PCH */
1905         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1906                 u32 pch_iir = I915_READ(SDEIIR);
1907
1908                 cpt_irq_handler(dev, pch_iir);
1909
1910                 /* clear PCH hotplug event before clear CPU irq */
1911                 I915_WRITE(SDEIIR, pch_iir);
1912         }
1913 }
1914
1915 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1916 {
1917         struct drm_device *dev = (struct drm_device *) arg;
1918         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1919         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1920         irqreturn_t ret = IRQ_NONE;
1921
1922         /* We get interrupts on unclaimed registers, so check for this before we
1923          * do any I915_{READ,WRITE}. */
1924         intel_uncore_check_errors(dev);
1925
1926         /* disable master interrupt before clearing iir  */
1927         de_ier = I915_READ(DEIER);
1928         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1929         POSTING_READ(DEIER);
1930
1931         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1932          * interrupts will will be stored on its back queue, and then we'll be
1933          * able to process them after we restore SDEIER (as soon as we restore
1934          * it, we'll get an interrupt if SDEIIR still has something to process
1935          * due to its back queue). */
1936         if (!HAS_PCH_NOP(dev)) {
1937                 sde_ier = I915_READ(SDEIER);
1938                 I915_WRITE(SDEIER, 0);
1939                 POSTING_READ(SDEIER);
1940         }
1941
1942         gt_iir = I915_READ(GTIIR);
1943         if (gt_iir) {
1944                 if (INTEL_INFO(dev)->gen >= 6)
1945                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1946                 else
1947                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1948                 I915_WRITE(GTIIR, gt_iir);
1949                 ret = IRQ_HANDLED;
1950         }
1951
1952         de_iir = I915_READ(DEIIR);
1953         if (de_iir) {
1954                 if (INTEL_INFO(dev)->gen >= 7)
1955                         ivb_display_irq_handler(dev, de_iir);
1956                 else
1957                         ilk_display_irq_handler(dev, de_iir);
1958                 I915_WRITE(DEIIR, de_iir);
1959                 ret = IRQ_HANDLED;
1960         }
1961
1962         if (INTEL_INFO(dev)->gen >= 6) {
1963                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1964                 if (pm_iir) {
1965                         gen6_rps_irq_handler(dev_priv, pm_iir);
1966                         I915_WRITE(GEN6_PMIIR, pm_iir);
1967                         ret = IRQ_HANDLED;
1968                 }
1969         }
1970
1971         I915_WRITE(DEIER, de_ier);
1972         POSTING_READ(DEIER);
1973         if (!HAS_PCH_NOP(dev)) {
1974                 I915_WRITE(SDEIER, sde_ier);
1975                 POSTING_READ(SDEIER);
1976         }
1977
1978         return ret;
1979 }
1980
1981 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1982 {
1983         struct drm_device *dev = arg;
1984         struct drm_i915_private *dev_priv = dev->dev_private;
1985         u32 master_ctl;
1986         irqreturn_t ret = IRQ_NONE;
1987         uint32_t tmp = 0;
1988         enum pipe pipe;
1989
1990         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1991         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1992         if (!master_ctl)
1993                 return IRQ_NONE;
1994
1995         I915_WRITE(GEN8_MASTER_IRQ, 0);
1996         POSTING_READ(GEN8_MASTER_IRQ);
1997
1998         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1999
2000         if (master_ctl & GEN8_DE_MISC_IRQ) {
2001                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2002                 if (tmp & GEN8_DE_MISC_GSE)
2003                         intel_opregion_asle_intr(dev);
2004                 else if (tmp)
2005                         DRM_ERROR("Unexpected DE Misc interrupt\n");
2006                 else
2007                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2008
2009                 if (tmp) {
2010                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2011                         ret = IRQ_HANDLED;
2012                 }
2013         }
2014
2015         if (master_ctl & GEN8_DE_PORT_IRQ) {
2016                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2017                 if (tmp & GEN8_AUX_CHANNEL_A)
2018                         dp_aux_irq_handler(dev);
2019                 else if (tmp)
2020                         DRM_ERROR("Unexpected DE Port interrupt\n");
2021                 else
2022                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2023
2024                 if (tmp) {
2025                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2026                         ret = IRQ_HANDLED;
2027                 }
2028         }
2029
2030         for_each_pipe(pipe) {
2031                 uint32_t pipe_iir;
2032
2033                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2034                         continue;
2035
2036                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2037                 if (pipe_iir & GEN8_PIPE_VBLANK)
2038                         drm_handle_vblank(dev, pipe);
2039
2040                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2041                         intel_prepare_page_flip(dev, pipe);
2042                         intel_finish_page_flip_plane(dev, pipe);
2043                 }
2044
2045                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2046                         hsw_pipe_crc_irq_handler(dev, pipe);
2047
2048                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2049                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2050                                                                   false))
2051                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2052                                           pipe_name(pipe));
2053                 }
2054
2055                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2056                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2057                                   pipe_name(pipe),
2058                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2059                 }
2060
2061                 if (pipe_iir) {
2062                         ret = IRQ_HANDLED;
2063                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2064                 } else
2065                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2066         }
2067
2068         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2069                 /*
2070                  * FIXME(BDW): Assume for now that the new interrupt handling
2071                  * scheme also closed the SDE interrupt handling race we've seen
2072                  * on older pch-split platforms. But this needs testing.
2073                  */
2074                 u32 pch_iir = I915_READ(SDEIIR);
2075
2076                 cpt_irq_handler(dev, pch_iir);
2077
2078                 if (pch_iir) {
2079                         I915_WRITE(SDEIIR, pch_iir);
2080                         ret = IRQ_HANDLED;
2081                 }
2082         }
2083
2084         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2085         POSTING_READ(GEN8_MASTER_IRQ);
2086
2087         return ret;
2088 }
2089
2090 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2091                                bool reset_completed)
2092 {
2093         struct intel_ring_buffer *ring;
2094         int i;
2095
2096         /*
2097          * Notify all waiters for GPU completion events that reset state has
2098          * been changed, and that they need to restart their wait after
2099          * checking for potential errors (and bail out to drop locks if there is
2100          * a gpu reset pending so that i915_error_work_func can acquire them).
2101          */
2102
2103         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2104         for_each_ring(ring, dev_priv, i)
2105                 wake_up_all(&ring->irq_queue);
2106
2107         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2108         wake_up_all(&dev_priv->pending_flip_queue);
2109
2110         /*
2111          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2112          * reset state is cleared.
2113          */
2114         if (reset_completed)
2115                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2116 }
2117
2118 /**
2119  * i915_error_work_func - do process context error handling work
2120  * @work: work struct
2121  *
2122  * Fire an error uevent so userspace can see that a hang or error
2123  * was detected.
2124  */
2125 static void i915_error_work_func(struct work_struct *work)
2126 {
2127         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2128                                                     work);
2129         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2130                                                     gpu_error);
2131         struct drm_device *dev = dev_priv->dev;
2132         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2133         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2134         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2135         int ret;
2136
2137         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2138
2139         /*
2140          * Note that there's only one work item which does gpu resets, so we
2141          * need not worry about concurrent gpu resets potentially incrementing
2142          * error->reset_counter twice. We only need to take care of another
2143          * racing irq/hangcheck declaring the gpu dead for a second time. A
2144          * quick check for that is good enough: schedule_work ensures the
2145          * correct ordering between hang detection and this work item, and since
2146          * the reset in-progress bit is only ever set by code outside of this
2147          * work we don't need to worry about any other races.
2148          */
2149         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2150                 DRM_DEBUG_DRIVER("resetting chip\n");
2151                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2152                                    reset_event);
2153
2154                 /*
2155                  * All state reset _must_ be completed before we update the
2156                  * reset counter, for otherwise waiters might miss the reset
2157                  * pending state and not properly drop locks, resulting in
2158                  * deadlocks with the reset work.
2159                  */
2160                 ret = i915_reset(dev);
2161
2162                 intel_display_handle_reset(dev);
2163
2164                 if (ret == 0) {
2165                         /*
2166                          * After all the gem state is reset, increment the reset
2167                          * counter and wake up everyone waiting for the reset to
2168                          * complete.
2169                          *
2170                          * Since unlock operations are a one-sided barrier only,
2171                          * we need to insert a barrier here to order any seqno
2172                          * updates before
2173                          * the counter increment.
2174                          */
2175                         smp_mb__before_atomic_inc();
2176                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2177
2178                         kobject_uevent_env(&dev->primary->kdev->kobj,
2179                                            KOBJ_CHANGE, reset_done_event);
2180                 } else {
2181                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2182                 }
2183
2184                 /*
2185                  * Note: The wake_up also serves as a memory barrier so that
2186                  * waiters see the update value of the reset counter atomic_t.
2187                  */
2188                 i915_error_wake_up(dev_priv, true);
2189         }
2190 }
2191
2192 static void i915_report_and_clear_eir(struct drm_device *dev)
2193 {
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         uint32_t instdone[I915_NUM_INSTDONE_REG];
2196         u32 eir = I915_READ(EIR);
2197         int pipe, i;
2198
2199         if (!eir)
2200                 return;
2201
2202         pr_err("render error detected, EIR: 0x%08x\n", eir);
2203
2204         i915_get_extra_instdone(dev, instdone);
2205
2206         if (IS_G4X(dev)) {
2207                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2208                         u32 ipeir = I915_READ(IPEIR_I965);
2209
2210                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2211                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2212                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2213                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2214                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2215                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2216                         I915_WRITE(IPEIR_I965, ipeir);
2217                         POSTING_READ(IPEIR_I965);
2218                 }
2219                 if (eir & GM45_ERROR_PAGE_TABLE) {
2220                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2221                         pr_err("page table error\n");
2222                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2223                         I915_WRITE(PGTBL_ER, pgtbl_err);
2224                         POSTING_READ(PGTBL_ER);
2225                 }
2226         }
2227
2228         if (!IS_GEN2(dev)) {
2229                 if (eir & I915_ERROR_PAGE_TABLE) {
2230                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2231                         pr_err("page table error\n");
2232                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2233                         I915_WRITE(PGTBL_ER, pgtbl_err);
2234                         POSTING_READ(PGTBL_ER);
2235                 }
2236         }
2237
2238         if (eir & I915_ERROR_MEMORY_REFRESH) {
2239                 pr_err("memory refresh error:\n");
2240                 for_each_pipe(pipe)
2241                         pr_err("pipe %c stat: 0x%08x\n",
2242                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2243                 /* pipestat has already been acked */
2244         }
2245         if (eir & I915_ERROR_INSTRUCTION) {
2246                 pr_err("instruction error\n");
2247                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2248                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2249                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2250                 if (INTEL_INFO(dev)->gen < 4) {
2251                         u32 ipeir = I915_READ(IPEIR);
2252
2253                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2254                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2255                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2256                         I915_WRITE(IPEIR, ipeir);
2257                         POSTING_READ(IPEIR);
2258                 } else {
2259                         u32 ipeir = I915_READ(IPEIR_I965);
2260
2261                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2262                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2263                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2264                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2265                         I915_WRITE(IPEIR_I965, ipeir);
2266                         POSTING_READ(IPEIR_I965);
2267                 }
2268         }
2269
2270         I915_WRITE(EIR, eir);
2271         POSTING_READ(EIR);
2272         eir = I915_READ(EIR);
2273         if (eir) {
2274                 /*
2275                  * some errors might have become stuck,
2276                  * mask them.
2277                  */
2278                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2279                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2280                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2281         }
2282 }
2283
2284 /**
2285  * i915_handle_error - handle an error interrupt
2286  * @dev: drm device
2287  *
2288  * Do some basic checking of regsiter state at error interrupt time and
2289  * dump it to the syslog.  Also call i915_capture_error_state() to make
2290  * sure we get a record and make it available in debugfs.  Fire a uevent
2291  * so userspace knows something bad happened (should trigger collection
2292  * of a ring dump etc.).
2293  */
2294 void i915_handle_error(struct drm_device *dev, bool wedged,
2295                        const char *fmt, ...)
2296 {
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298         va_list args;
2299         char error_msg[80];
2300
2301         va_start(args, fmt);
2302         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2303         va_end(args);
2304
2305         i915_capture_error_state(dev, wedged, error_msg);
2306         i915_report_and_clear_eir(dev);
2307
2308         if (wedged) {
2309                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2310                                 &dev_priv->gpu_error.reset_counter);
2311
2312                 /*
2313                  * Wakeup waiting processes so that the reset work function
2314                  * i915_error_work_func doesn't deadlock trying to grab various
2315                  * locks. By bumping the reset counter first, the woken
2316                  * processes will see a reset in progress and back off,
2317                  * releasing their locks and then wait for the reset completion.
2318                  * We must do this for _all_ gpu waiters that might hold locks
2319                  * that the reset work needs to acquire.
2320                  *
2321                  * Note: The wake_up serves as the required memory barrier to
2322                  * ensure that the waiters see the updated value of the reset
2323                  * counter atomic_t.
2324                  */
2325                 i915_error_wake_up(dev_priv, false);
2326         }
2327
2328         /*
2329          * Our reset work can grab modeset locks (since it needs to reset the
2330          * state of outstanding pagelips). Hence it must not be run on our own
2331          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2332          * code will deadlock.
2333          */
2334         schedule_work(&dev_priv->gpu_error.work);
2335 }
2336
2337 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2338 {
2339         drm_i915_private_t *dev_priv = dev->dev_private;
2340         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2342         struct drm_i915_gem_object *obj;
2343         struct intel_unpin_work *work;
2344         unsigned long flags;
2345         bool stall_detected;
2346
2347         /* Ignore early vblank irqs */
2348         if (intel_crtc == NULL)
2349                 return;
2350
2351         spin_lock_irqsave(&dev->event_lock, flags);
2352         work = intel_crtc->unpin_work;
2353
2354         if (work == NULL ||
2355             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2356             !work->enable_stall_check) {
2357                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2358                 spin_unlock_irqrestore(&dev->event_lock, flags);
2359                 return;
2360         }
2361
2362         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2363         obj = work->pending_flip_obj;
2364         if (INTEL_INFO(dev)->gen >= 4) {
2365                 int dspsurf = DSPSURF(intel_crtc->plane);
2366                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2367                                         i915_gem_obj_ggtt_offset(obj);
2368         } else {
2369                 int dspaddr = DSPADDR(intel_crtc->plane);
2370                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2371                                                         crtc->y * crtc->fb->pitches[0] +
2372                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2373         }
2374
2375         spin_unlock_irqrestore(&dev->event_lock, flags);
2376
2377         if (stall_detected) {
2378                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2379                 intel_prepare_page_flip(dev, intel_crtc->plane);
2380         }
2381 }
2382
2383 /* Called from drm generic code, passed 'crtc' which
2384  * we use as a pipe index
2385  */
2386 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2387 {
2388         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2389         unsigned long irqflags;
2390
2391         if (!i915_pipe_enabled(dev, pipe))
2392                 return -EINVAL;
2393
2394         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2395         if (INTEL_INFO(dev)->gen >= 4)
2396                 i915_enable_pipestat(dev_priv, pipe,
2397                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2398         else
2399                 i915_enable_pipestat(dev_priv, pipe,
2400                                      PIPE_VBLANK_INTERRUPT_STATUS);
2401
2402         /* maintain vblank delivery even in deep C-states */
2403         if (INTEL_INFO(dev)->gen == 3)
2404                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2405         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2406
2407         return 0;
2408 }
2409
2410 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2411 {
2412         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2413         unsigned long irqflags;
2414         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2415                                                      DE_PIPE_VBLANK(pipe);
2416
2417         if (!i915_pipe_enabled(dev, pipe))
2418                 return -EINVAL;
2419
2420         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2421         ironlake_enable_display_irq(dev_priv, bit);
2422         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2423
2424         return 0;
2425 }
2426
2427 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2428 {
2429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2430         unsigned long irqflags;
2431
2432         if (!i915_pipe_enabled(dev, pipe))
2433                 return -EINVAL;
2434
2435         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2436         i915_enable_pipestat(dev_priv, pipe,
2437                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2438         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2439
2440         return 0;
2441 }
2442
2443 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2444 {
2445         struct drm_i915_private *dev_priv = dev->dev_private;
2446         unsigned long irqflags;
2447
2448         if (!i915_pipe_enabled(dev, pipe))
2449                 return -EINVAL;
2450
2451         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2452         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2453         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2454         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2455         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2456         return 0;
2457 }
2458
2459 /* Called from drm generic code, passed 'crtc' which
2460  * we use as a pipe index
2461  */
2462 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2463 {
2464         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2465         unsigned long irqflags;
2466
2467         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2468         if (INTEL_INFO(dev)->gen == 3)
2469                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2470
2471         i915_disable_pipestat(dev_priv, pipe,
2472                               PIPE_VBLANK_INTERRUPT_STATUS |
2473                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2474         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2475 }
2476
2477 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2478 {
2479         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2480         unsigned long irqflags;
2481         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2482                                                      DE_PIPE_VBLANK(pipe);
2483
2484         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2485         ironlake_disable_display_irq(dev_priv, bit);
2486         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2487 }
2488
2489 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2490 {
2491         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2492         unsigned long irqflags;
2493
2494         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2495         i915_disable_pipestat(dev_priv, pipe,
2496                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2497         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2498 }
2499
2500 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2501 {
2502         struct drm_i915_private *dev_priv = dev->dev_private;
2503         unsigned long irqflags;
2504
2505         if (!i915_pipe_enabled(dev, pipe))
2506                 return;
2507
2508         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2509         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2510         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2511         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2513 }
2514
2515 static u32
2516 ring_last_seqno(struct intel_ring_buffer *ring)
2517 {
2518         return list_entry(ring->request_list.prev,
2519                           struct drm_i915_gem_request, list)->seqno;
2520 }
2521
2522 static bool
2523 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2524 {
2525         return (list_empty(&ring->request_list) ||
2526                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2527 }
2528
2529 static struct intel_ring_buffer *
2530 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2531 {
2532         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2533         u32 cmd, ipehr, acthd, acthd_min;
2534
2535         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2536         if ((ipehr & ~(0x3 << 16)) !=
2537             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2538                 return NULL;
2539
2540         /* ACTHD is likely pointing to the dword after the actual command,
2541          * so scan backwards until we find the MBOX.
2542          */
2543         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2544         acthd_min = max((int)acthd - 3 * 4, 0);
2545         do {
2546                 cmd = ioread32(ring->virtual_start + acthd);
2547                 if (cmd == ipehr)
2548                         break;
2549
2550                 acthd -= 4;
2551                 if (acthd < acthd_min)
2552                         return NULL;
2553         } while (1);
2554
2555         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2556         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2557 }
2558
2559 static int semaphore_passed(struct intel_ring_buffer *ring)
2560 {
2561         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2562         struct intel_ring_buffer *signaller;
2563         u32 seqno, ctl;
2564
2565         ring->hangcheck.deadlock = true;
2566
2567         signaller = semaphore_waits_for(ring, &seqno);
2568         if (signaller == NULL || signaller->hangcheck.deadlock)
2569                 return -1;
2570
2571         /* cursory check for an unkickable deadlock */
2572         ctl = I915_READ_CTL(signaller);
2573         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2574                 return -1;
2575
2576         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2577 }
2578
2579 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2580 {
2581         struct intel_ring_buffer *ring;
2582         int i;
2583
2584         for_each_ring(ring, dev_priv, i)
2585                 ring->hangcheck.deadlock = false;
2586 }
2587
2588 static enum intel_ring_hangcheck_action
2589 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2590 {
2591         struct drm_device *dev = ring->dev;
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593         u32 tmp;
2594
2595         if (ring->hangcheck.acthd != acthd)
2596                 return HANGCHECK_ACTIVE;
2597
2598         if (IS_GEN2(dev))
2599                 return HANGCHECK_HUNG;
2600
2601         /* Is the chip hanging on a WAIT_FOR_EVENT?
2602          * If so we can simply poke the RB_WAIT bit
2603          * and break the hang. This should work on
2604          * all but the second generation chipsets.
2605          */
2606         tmp = I915_READ_CTL(ring);
2607         if (tmp & RING_WAIT) {
2608                 i915_handle_error(dev, false,
2609                                   "Kicking stuck wait on %s",
2610                                   ring->name);
2611                 I915_WRITE_CTL(ring, tmp);
2612                 return HANGCHECK_KICK;
2613         }
2614
2615         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2616                 switch (semaphore_passed(ring)) {
2617                 default:
2618                         return HANGCHECK_HUNG;
2619                 case 1:
2620                         i915_handle_error(dev, false,
2621                                           "Kicking stuck semaphore on %s",
2622                                           ring->name);
2623                         I915_WRITE_CTL(ring, tmp);
2624                         return HANGCHECK_KICK;
2625                 case 0:
2626                         return HANGCHECK_WAIT;
2627                 }
2628         }
2629
2630         return HANGCHECK_HUNG;
2631 }
2632
2633 /**
2634  * This is called when the chip hasn't reported back with completed
2635  * batchbuffers in a long time. We keep track per ring seqno progress and
2636  * if there are no progress, hangcheck score for that ring is increased.
2637  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2638  * we kick the ring. If we see no progress on three subsequent calls
2639  * we assume chip is wedged and try to fix it by resetting the chip.
2640  */
2641 static void i915_hangcheck_elapsed(unsigned long data)
2642 {
2643         struct drm_device *dev = (struct drm_device *)data;
2644         drm_i915_private_t *dev_priv = dev->dev_private;
2645         struct intel_ring_buffer *ring;
2646         int i;
2647         int busy_count = 0, rings_hung = 0;
2648         bool stuck[I915_NUM_RINGS] = { 0 };
2649 #define BUSY 1
2650 #define KICK 5
2651 #define HUNG 20
2652
2653         if (!i915.enable_hangcheck)
2654                 return;
2655
2656         for_each_ring(ring, dev_priv, i) {
2657                 u32 seqno, acthd;
2658                 bool busy = true;
2659
2660                 semaphore_clear_deadlocks(dev_priv);
2661
2662                 seqno = ring->get_seqno(ring, false);
2663                 acthd = intel_ring_get_active_head(ring);
2664
2665                 if (ring->hangcheck.seqno == seqno) {
2666                         if (ring_idle(ring, seqno)) {
2667                                 ring->hangcheck.action = HANGCHECK_IDLE;
2668
2669                                 if (waitqueue_active(&ring->irq_queue)) {
2670                                         /* Issue a wake-up to catch stuck h/w. */
2671                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2672                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2673                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2674                                                                   ring->name);
2675                                                 else
2676                                                         DRM_INFO("Fake missed irq on %s\n",
2677                                                                  ring->name);
2678                                                 wake_up_all(&ring->irq_queue);
2679                                         }
2680                                         /* Safeguard against driver failure */
2681                                         ring->hangcheck.score += BUSY;
2682                                 } else
2683                                         busy = false;
2684                         } else {
2685                                 /* We always increment the hangcheck score
2686                                  * if the ring is busy and still processing
2687                                  * the same request, so that no single request
2688                                  * can run indefinitely (such as a chain of
2689                                  * batches). The only time we do not increment
2690                                  * the hangcheck score on this ring, if this
2691                                  * ring is in a legitimate wait for another
2692                                  * ring. In that case the waiting ring is a
2693                                  * victim and we want to be sure we catch the
2694                                  * right culprit. Then every time we do kick
2695                                  * the ring, add a small increment to the
2696                                  * score so that we can catch a batch that is
2697                                  * being repeatedly kicked and so responsible
2698                                  * for stalling the machine.
2699                                  */
2700                                 ring->hangcheck.action = ring_stuck(ring,
2701                                                                     acthd);
2702
2703                                 switch (ring->hangcheck.action) {
2704                                 case HANGCHECK_IDLE:
2705                                 case HANGCHECK_WAIT:
2706                                         break;
2707                                 case HANGCHECK_ACTIVE:
2708                                         ring->hangcheck.score += BUSY;
2709                                         break;
2710                                 case HANGCHECK_KICK:
2711                                         ring->hangcheck.score += KICK;
2712                                         break;
2713                                 case HANGCHECK_HUNG:
2714                                         ring->hangcheck.score += HUNG;
2715                                         stuck[i] = true;
2716                                         break;
2717                                 }
2718                         }
2719                 } else {
2720                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2721
2722                         /* Gradually reduce the count so that we catch DoS
2723                          * attempts across multiple batches.
2724                          */
2725                         if (ring->hangcheck.score > 0)
2726                                 ring->hangcheck.score--;
2727                 }
2728
2729                 ring->hangcheck.seqno = seqno;
2730                 ring->hangcheck.acthd = acthd;
2731                 busy_count += busy;
2732         }
2733
2734         for_each_ring(ring, dev_priv, i) {
2735                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2736                         DRM_INFO("%s on %s\n",
2737                                  stuck[i] ? "stuck" : "no progress",
2738                                  ring->name);
2739                         rings_hung++;
2740                 }
2741         }
2742
2743         if (rings_hung)
2744                 return i915_handle_error(dev, true, "Ring hung");
2745
2746         if (busy_count)
2747                 /* Reset timer case chip hangs without another request
2748                  * being added */
2749                 i915_queue_hangcheck(dev);
2750 }
2751
2752 void i915_queue_hangcheck(struct drm_device *dev)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         if (!i915.enable_hangcheck)
2756                 return;
2757
2758         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2759                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2760 }
2761
2762 static void ibx_irq_preinstall(struct drm_device *dev)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765
2766         if (HAS_PCH_NOP(dev))
2767                 return;
2768
2769         /* south display irq */
2770         I915_WRITE(SDEIMR, 0xffffffff);
2771         /*
2772          * SDEIER is also touched by the interrupt handler to work around missed
2773          * PCH interrupts. Hence we can't update it after the interrupt handler
2774          * is enabled - instead we unconditionally enable all PCH interrupt
2775          * sources here, but then only unmask them as needed with SDEIMR.
2776          */
2777         I915_WRITE(SDEIER, 0xffffffff);
2778         POSTING_READ(SDEIER);
2779 }
2780
2781 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784
2785         /* and GT */
2786         I915_WRITE(GTIMR, 0xffffffff);
2787         I915_WRITE(GTIER, 0x0);
2788         POSTING_READ(GTIER);
2789
2790         if (INTEL_INFO(dev)->gen >= 6) {
2791                 /* and PM */
2792                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2793                 I915_WRITE(GEN6_PMIER, 0x0);
2794                 POSTING_READ(GEN6_PMIER);
2795         }
2796 }
2797
2798 /* drm_dma.h hooks
2799 */
2800 static void ironlake_irq_preinstall(struct drm_device *dev)
2801 {
2802         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2803
2804         I915_WRITE(HWSTAM, 0xeffe);
2805
2806         I915_WRITE(DEIMR, 0xffffffff);
2807         I915_WRITE(DEIER, 0x0);
2808         POSTING_READ(DEIER);
2809
2810         gen5_gt_irq_preinstall(dev);
2811
2812         ibx_irq_preinstall(dev);
2813 }
2814
2815 static void valleyview_irq_preinstall(struct drm_device *dev)
2816 {
2817         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2818         int pipe;
2819
2820         /* VLV magic */
2821         I915_WRITE(VLV_IMR, 0);
2822         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2823         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2824         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2825
2826         /* and GT */
2827         I915_WRITE(GTIIR, I915_READ(GTIIR));
2828         I915_WRITE(GTIIR, I915_READ(GTIIR));
2829
2830         gen5_gt_irq_preinstall(dev);
2831
2832         I915_WRITE(DPINVGTT, 0xff);
2833
2834         I915_WRITE(PORT_HOTPLUG_EN, 0);
2835         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2836         for_each_pipe(pipe)
2837                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2838         I915_WRITE(VLV_IIR, 0xffffffff);
2839         I915_WRITE(VLV_IMR, 0xffffffff);
2840         I915_WRITE(VLV_IER, 0x0);
2841         POSTING_READ(VLV_IER);
2842 }
2843
2844 static void gen8_irq_preinstall(struct drm_device *dev)
2845 {
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         int pipe;
2848
2849         I915_WRITE(GEN8_MASTER_IRQ, 0);
2850         POSTING_READ(GEN8_MASTER_IRQ);
2851
2852         /* IIR can theoretically queue up two events. Be paranoid */
2853 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2854                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2855                 POSTING_READ(GEN8_##type##_IMR(which)); \
2856                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2857                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2858                 POSTING_READ(GEN8_##type##_IIR(which)); \
2859                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2860         } while (0)
2861
2862 #define GEN8_IRQ_INIT(type) do { \
2863                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2864                 POSTING_READ(GEN8_##type##_IMR); \
2865                 I915_WRITE(GEN8_##type##_IER, 0); \
2866                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2867                 POSTING_READ(GEN8_##type##_IIR); \
2868                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2869         } while (0)
2870
2871         GEN8_IRQ_INIT_NDX(GT, 0);
2872         GEN8_IRQ_INIT_NDX(GT, 1);
2873         GEN8_IRQ_INIT_NDX(GT, 2);
2874         GEN8_IRQ_INIT_NDX(GT, 3);
2875
2876         for_each_pipe(pipe) {
2877                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2878         }
2879
2880         GEN8_IRQ_INIT(DE_PORT);
2881         GEN8_IRQ_INIT(DE_MISC);
2882         GEN8_IRQ_INIT(PCU);
2883 #undef GEN8_IRQ_INIT
2884 #undef GEN8_IRQ_INIT_NDX
2885
2886         POSTING_READ(GEN8_PCU_IIR);
2887
2888         ibx_irq_preinstall(dev);
2889 }
2890
2891 static void ibx_hpd_irq_setup(struct drm_device *dev)
2892 {
2893         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2894         struct drm_mode_config *mode_config = &dev->mode_config;
2895         struct intel_encoder *intel_encoder;
2896         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2897
2898         if (HAS_PCH_IBX(dev)) {
2899                 hotplug_irqs = SDE_HOTPLUG_MASK;
2900                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2901                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2902                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2903         } else {
2904                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2905                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2906                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2907                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2908         }
2909
2910         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2911
2912         /*
2913          * Enable digital hotplug on the PCH, and configure the DP short pulse
2914          * duration to 2ms (which is the minimum in the Display Port spec)
2915          *
2916          * This register is the same on all known PCH chips.
2917          */
2918         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2919         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2920         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2921         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2922         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2923         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2924 }
2925
2926 static void ibx_irq_postinstall(struct drm_device *dev)
2927 {
2928         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2929         u32 mask;
2930
2931         if (HAS_PCH_NOP(dev))
2932                 return;
2933
2934         if (HAS_PCH_IBX(dev)) {
2935                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2936                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2937         } else {
2938                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2939
2940                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2941         }
2942
2943         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2944         I915_WRITE(SDEIMR, ~mask);
2945 }
2946
2947 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2948 {
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950         u32 pm_irqs, gt_irqs;
2951
2952         pm_irqs = gt_irqs = 0;
2953
2954         dev_priv->gt_irq_mask = ~0;
2955         if (HAS_L3_DPF(dev)) {
2956                 /* L3 parity interrupt is always unmasked. */
2957                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2958                 gt_irqs |= GT_PARITY_ERROR(dev);
2959         }
2960
2961         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2962         if (IS_GEN5(dev)) {
2963                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2964                            ILK_BSD_USER_INTERRUPT;
2965         } else {
2966                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2967         }
2968
2969         I915_WRITE(GTIIR, I915_READ(GTIIR));
2970         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2971         I915_WRITE(GTIER, gt_irqs);
2972         POSTING_READ(GTIER);
2973
2974         if (INTEL_INFO(dev)->gen >= 6) {
2975                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2976
2977                 if (HAS_VEBOX(dev))
2978                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2979
2980                 dev_priv->pm_irq_mask = 0xffffffff;
2981                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2982                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2983                 I915_WRITE(GEN6_PMIER, pm_irqs);
2984                 POSTING_READ(GEN6_PMIER);
2985         }
2986 }
2987
2988 static int ironlake_irq_postinstall(struct drm_device *dev)
2989 {
2990         unsigned long irqflags;
2991         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2992         u32 display_mask, extra_mask;
2993
2994         if (INTEL_INFO(dev)->gen >= 7) {
2995                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2996                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2997                                 DE_PLANEB_FLIP_DONE_IVB |
2998                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2999                                 DE_ERR_INT_IVB);
3000                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3001                               DE_PIPEA_VBLANK_IVB);
3002
3003                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3004         } else {
3005                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3006                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3007                                 DE_AUX_CHANNEL_A |
3008                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3009                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3010                                 DE_POISON);
3011                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
3012         }
3013
3014         dev_priv->irq_mask = ~display_mask;
3015
3016         /* should always can generate irq */
3017         I915_WRITE(DEIIR, I915_READ(DEIIR));
3018         I915_WRITE(DEIMR, dev_priv->irq_mask);
3019         I915_WRITE(DEIER, display_mask | extra_mask);
3020         POSTING_READ(DEIER);
3021
3022         gen5_gt_irq_postinstall(dev);
3023
3024         ibx_irq_postinstall(dev);
3025
3026         if (IS_IRONLAKE_M(dev)) {
3027                 /* Enable PCU event interrupts
3028                  *
3029                  * spinlocking not required here for correctness since interrupt
3030                  * setup is guaranteed to run in single-threaded context. But we
3031                  * need it to make the assert_spin_locked happy. */
3032                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3033                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3034                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3035         }
3036
3037         return 0;
3038 }
3039
3040 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3041 {
3042         u32 pipestat_mask;
3043         u32 iir_mask;
3044
3045         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3046                         PIPE_FIFO_UNDERRUN_STATUS;
3047
3048         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3049         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3050         POSTING_READ(PIPESTAT(PIPE_A));
3051
3052         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3053                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3054
3055         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3056                                                PIPE_GMBUS_INTERRUPT_STATUS);
3057         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3058
3059         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3060                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3061                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3062         dev_priv->irq_mask &= ~iir_mask;
3063
3064         I915_WRITE(VLV_IIR, iir_mask);
3065         I915_WRITE(VLV_IIR, iir_mask);
3066         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3067         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3068         POSTING_READ(VLV_IER);
3069 }
3070
3071 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3072 {
3073         u32 pipestat_mask;
3074         u32 iir_mask;
3075
3076         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3077                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3078                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3079
3080         dev_priv->irq_mask |= iir_mask;
3081         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3082         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3083         I915_WRITE(VLV_IIR, iir_mask);
3084         I915_WRITE(VLV_IIR, iir_mask);
3085         POSTING_READ(VLV_IIR);
3086
3087         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3088                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3089
3090         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3091                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3092         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3093
3094         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3095                         PIPE_FIFO_UNDERRUN_STATUS;
3096         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3097         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3098         POSTING_READ(PIPESTAT(PIPE_A));
3099 }
3100
3101 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3102 {
3103         assert_spin_locked(&dev_priv->irq_lock);
3104
3105         if (dev_priv->display_irqs_enabled)
3106                 return;
3107
3108         dev_priv->display_irqs_enabled = true;
3109
3110         if (dev_priv->dev->irq_enabled)
3111                 valleyview_display_irqs_install(dev_priv);
3112 }
3113
3114 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3115 {
3116         assert_spin_locked(&dev_priv->irq_lock);
3117
3118         if (!dev_priv->display_irqs_enabled)
3119                 return;
3120
3121         dev_priv->display_irqs_enabled = false;
3122
3123         if (dev_priv->dev->irq_enabled)
3124                 valleyview_display_irqs_uninstall(dev_priv);
3125 }
3126
3127 static int valleyview_irq_postinstall(struct drm_device *dev)
3128 {
3129         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3130         unsigned long irqflags;
3131
3132         dev_priv->irq_mask = ~0;
3133
3134         I915_WRITE(PORT_HOTPLUG_EN, 0);
3135         POSTING_READ(PORT_HOTPLUG_EN);
3136
3137         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3138         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3139         I915_WRITE(VLV_IIR, 0xffffffff);
3140         POSTING_READ(VLV_IER);
3141
3142         /* Interrupt setup is already guaranteed to be single-threaded, this is
3143          * just to make the assert_spin_locked check happy. */
3144         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3145         if (dev_priv->display_irqs_enabled)
3146                 valleyview_display_irqs_install(dev_priv);
3147         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3148
3149         I915_WRITE(VLV_IIR, 0xffffffff);
3150         I915_WRITE(VLV_IIR, 0xffffffff);
3151
3152         gen5_gt_irq_postinstall(dev);
3153
3154         /* ack & enable invalid PTE error interrupts */
3155 #if 0 /* FIXME: add support to irq handler for checking these bits */
3156         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3157         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3158 #endif
3159
3160         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3161
3162         return 0;
3163 }
3164
3165 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3166 {
3167         int i;
3168
3169         /* These are interrupts we'll toggle with the ring mask register */
3170         uint32_t gt_interrupts[] = {
3171                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3172                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3173                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3174                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3175                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3176                 0,
3177                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3178                 };
3179
3180         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
3181                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
3182                 if (tmp)
3183                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3184                                   i, tmp);
3185                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
3186                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
3187         }
3188         POSTING_READ(GEN8_GT_IER(0));
3189 }
3190
3191 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3192 {
3193         struct drm_device *dev = dev_priv->dev;
3194         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3195                 GEN8_PIPE_CDCLK_CRC_DONE |
3196                 GEN8_PIPE_FIFO_UNDERRUN |
3197                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3198         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
3199         int pipe;
3200         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3201         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3202         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3203
3204         for_each_pipe(pipe) {
3205                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3206                 if (tmp)
3207                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3208                                   pipe, tmp);
3209                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3210                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3211         }
3212         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3213
3214         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3215         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3216         POSTING_READ(GEN8_DE_PORT_IER);
3217 }
3218
3219 static int gen8_irq_postinstall(struct drm_device *dev)
3220 {
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222
3223         gen8_gt_irq_postinstall(dev_priv);
3224         gen8_de_irq_postinstall(dev_priv);
3225
3226         ibx_irq_postinstall(dev);
3227
3228         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3229         POSTING_READ(GEN8_MASTER_IRQ);
3230
3231         return 0;
3232 }
3233
3234 static void gen8_irq_uninstall(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = dev->dev_private;
3237         int pipe;
3238
3239         if (!dev_priv)
3240                 return;
3241
3242         I915_WRITE(GEN8_MASTER_IRQ, 0);
3243
3244 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3245                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3246                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3247                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3248         } while (0)
3249
3250 #define GEN8_IRQ_FINI(type) do { \
3251                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3252                 I915_WRITE(GEN8_##type##_IER, 0); \
3253                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3254         } while (0)
3255
3256         GEN8_IRQ_FINI_NDX(GT, 0);
3257         GEN8_IRQ_FINI_NDX(GT, 1);
3258         GEN8_IRQ_FINI_NDX(GT, 2);
3259         GEN8_IRQ_FINI_NDX(GT, 3);
3260
3261         for_each_pipe(pipe) {
3262                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3263         }
3264
3265         GEN8_IRQ_FINI(DE_PORT);
3266         GEN8_IRQ_FINI(DE_MISC);
3267         GEN8_IRQ_FINI(PCU);
3268 #undef GEN8_IRQ_FINI
3269 #undef GEN8_IRQ_FINI_NDX
3270
3271         POSTING_READ(GEN8_PCU_IIR);
3272 }
3273
3274 static void valleyview_irq_uninstall(struct drm_device *dev)
3275 {
3276         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3277         unsigned long irqflags;
3278         int pipe;
3279
3280         if (!dev_priv)
3281                 return;
3282
3283         intel_hpd_irq_uninstall(dev_priv);
3284
3285         for_each_pipe(pipe)
3286                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3287
3288         I915_WRITE(HWSTAM, 0xffffffff);
3289         I915_WRITE(PORT_HOTPLUG_EN, 0);
3290         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3291
3292         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3293         if (dev_priv->display_irqs_enabled)
3294                 valleyview_display_irqs_uninstall(dev_priv);
3295         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3296
3297         dev_priv->irq_mask = 0;
3298
3299         I915_WRITE(VLV_IIR, 0xffffffff);
3300         I915_WRITE(VLV_IMR, 0xffffffff);
3301         I915_WRITE(VLV_IER, 0x0);
3302         POSTING_READ(VLV_IER);
3303 }
3304
3305 static void ironlake_irq_uninstall(struct drm_device *dev)
3306 {
3307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3308
3309         if (!dev_priv)
3310                 return;
3311
3312         intel_hpd_irq_uninstall(dev_priv);
3313
3314         I915_WRITE(HWSTAM, 0xffffffff);
3315
3316         I915_WRITE(DEIMR, 0xffffffff);
3317         I915_WRITE(DEIER, 0x0);
3318         I915_WRITE(DEIIR, I915_READ(DEIIR));
3319         if (IS_GEN7(dev))
3320                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3321
3322         I915_WRITE(GTIMR, 0xffffffff);
3323         I915_WRITE(GTIER, 0x0);
3324         I915_WRITE(GTIIR, I915_READ(GTIIR));
3325
3326         if (HAS_PCH_NOP(dev))
3327                 return;
3328
3329         I915_WRITE(SDEIMR, 0xffffffff);
3330         I915_WRITE(SDEIER, 0x0);
3331         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3332         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3333                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3334 }
3335
3336 static void i8xx_irq_preinstall(struct drm_device * dev)
3337 {
3338         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3339         int pipe;
3340
3341         for_each_pipe(pipe)
3342                 I915_WRITE(PIPESTAT(pipe), 0);
3343         I915_WRITE16(IMR, 0xffff);
3344         I915_WRITE16(IER, 0x0);
3345         POSTING_READ16(IER);
3346 }
3347
3348 static int i8xx_irq_postinstall(struct drm_device *dev)
3349 {
3350         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3351         unsigned long irqflags;
3352
3353         I915_WRITE16(EMR,
3354                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3355
3356         /* Unmask the interrupts that we always want on. */
3357         dev_priv->irq_mask =
3358                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3359                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3360                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3361                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3362                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3363         I915_WRITE16(IMR, dev_priv->irq_mask);
3364
3365         I915_WRITE16(IER,
3366                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3367                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3368                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3369                      I915_USER_INTERRUPT);
3370         POSTING_READ16(IER);
3371
3372         /* Interrupt setup is already guaranteed to be single-threaded, this is
3373          * just to make the assert_spin_locked check happy. */
3374         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3375         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3376         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3377         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3378
3379         return 0;
3380 }
3381
3382 /*
3383  * Returns true when a page flip has completed.
3384  */
3385 static bool i8xx_handle_vblank(struct drm_device *dev,
3386                                int plane, int pipe, u32 iir)
3387 {
3388         drm_i915_private_t *dev_priv = dev->dev_private;
3389         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3390
3391         if (!drm_handle_vblank(dev, pipe))
3392                 return false;
3393
3394         if ((iir & flip_pending) == 0)
3395                 return false;
3396
3397         intel_prepare_page_flip(dev, plane);
3398
3399         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3400          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3401          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3402          * the flip is completed (no longer pending). Since this doesn't raise
3403          * an interrupt per se, we watch for the change at vblank.
3404          */
3405         if (I915_READ16(ISR) & flip_pending)
3406                 return false;
3407
3408         intel_finish_page_flip(dev, pipe);
3409
3410         return true;
3411 }
3412
3413 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3414 {
3415         struct drm_device *dev = (struct drm_device *) arg;
3416         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3417         u16 iir, new_iir;
3418         u32 pipe_stats[2];
3419         unsigned long irqflags;
3420         int pipe;
3421         u16 flip_mask =
3422                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3423                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3424
3425         iir = I915_READ16(IIR);
3426         if (iir == 0)
3427                 return IRQ_NONE;
3428
3429         while (iir & ~flip_mask) {
3430                 /* Can't rely on pipestat interrupt bit in iir as it might
3431                  * have been cleared after the pipestat interrupt was received.
3432                  * It doesn't set the bit in iir again, but it still produces
3433                  * interrupts (for non-MSI).
3434                  */
3435                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3436                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3437                         i915_handle_error(dev, false,
3438                                           "Command parser error, iir 0x%08x",
3439                                           iir);
3440
3441                 for_each_pipe(pipe) {
3442                         int reg = PIPESTAT(pipe);
3443                         pipe_stats[pipe] = I915_READ(reg);
3444
3445                         /*
3446                          * Clear the PIPE*STAT regs before the IIR
3447                          */
3448                         if (pipe_stats[pipe] & 0x8000ffff)
3449                                 I915_WRITE(reg, pipe_stats[pipe]);
3450                 }
3451                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3452
3453                 I915_WRITE16(IIR, iir & ~flip_mask);
3454                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3455
3456                 i915_update_dri1_breadcrumb(dev);
3457
3458                 if (iir & I915_USER_INTERRUPT)
3459                         notify_ring(dev, &dev_priv->ring[RCS]);
3460
3461                 for_each_pipe(pipe) {
3462                         int plane = pipe;
3463                         if (HAS_FBC(dev))
3464                                 plane = !plane;
3465
3466                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3467                             i8xx_handle_vblank(dev, plane, pipe, iir))
3468                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3469
3470                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3471                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3472
3473                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3474                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3475                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3476                 }
3477
3478                 iir = new_iir;
3479         }
3480
3481         return IRQ_HANDLED;
3482 }
3483
3484 static void i8xx_irq_uninstall(struct drm_device * dev)
3485 {
3486         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3487         int pipe;
3488
3489         for_each_pipe(pipe) {
3490                 /* Clear enable bits; then clear status bits */
3491                 I915_WRITE(PIPESTAT(pipe), 0);
3492                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3493         }
3494         I915_WRITE16(IMR, 0xffff);
3495         I915_WRITE16(IER, 0x0);
3496         I915_WRITE16(IIR, I915_READ16(IIR));
3497 }
3498
3499 static void i915_irq_preinstall(struct drm_device * dev)
3500 {
3501         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3502         int pipe;
3503
3504         if (I915_HAS_HOTPLUG(dev)) {
3505                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3506                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3507         }
3508
3509         I915_WRITE16(HWSTAM, 0xeffe);
3510         for_each_pipe(pipe)
3511                 I915_WRITE(PIPESTAT(pipe), 0);
3512         I915_WRITE(IMR, 0xffffffff);
3513         I915_WRITE(IER, 0x0);
3514         POSTING_READ(IER);
3515 }
3516
3517 static int i915_irq_postinstall(struct drm_device *dev)
3518 {
3519         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3520         u32 enable_mask;
3521         unsigned long irqflags;
3522
3523         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3524
3525         /* Unmask the interrupts that we always want on. */
3526         dev_priv->irq_mask =
3527                 ~(I915_ASLE_INTERRUPT |
3528                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3529                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3530                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3531                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3532                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3533
3534         enable_mask =
3535                 I915_ASLE_INTERRUPT |
3536                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3537                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3538                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3539                 I915_USER_INTERRUPT;
3540
3541         if (I915_HAS_HOTPLUG(dev)) {
3542                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3543                 POSTING_READ(PORT_HOTPLUG_EN);
3544
3545                 /* Enable in IER... */
3546                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3547                 /* and unmask in IMR */
3548                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3549         }
3550
3551         I915_WRITE(IMR, dev_priv->irq_mask);
3552         I915_WRITE(IER, enable_mask);
3553         POSTING_READ(IER);
3554
3555         i915_enable_asle_pipestat(dev);
3556
3557         /* Interrupt setup is already guaranteed to be single-threaded, this is
3558          * just to make the assert_spin_locked check happy. */
3559         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3560         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3561         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3562         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3563
3564         return 0;
3565 }
3566
3567 /*
3568  * Returns true when a page flip has completed.
3569  */
3570 static bool i915_handle_vblank(struct drm_device *dev,
3571                                int plane, int pipe, u32 iir)
3572 {
3573         drm_i915_private_t *dev_priv = dev->dev_private;
3574         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3575
3576         if (!drm_handle_vblank(dev, pipe))
3577                 return false;
3578
3579         if ((iir & flip_pending) == 0)
3580                 return false;
3581
3582         intel_prepare_page_flip(dev, plane);
3583
3584         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3585          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3586          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3587          * the flip is completed (no longer pending). Since this doesn't raise
3588          * an interrupt per se, we watch for the change at vblank.
3589          */
3590         if (I915_READ(ISR) & flip_pending)
3591                 return false;
3592
3593         intel_finish_page_flip(dev, pipe);
3594
3595         return true;
3596 }
3597
3598 static irqreturn_t i915_irq_handler(int irq, void *arg)
3599 {
3600         struct drm_device *dev = (struct drm_device *) arg;
3601         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3602         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3603         unsigned long irqflags;
3604         u32 flip_mask =
3605                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3606                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3607         int pipe, ret = IRQ_NONE;
3608
3609         iir = I915_READ(IIR);
3610         do {
3611                 bool irq_received = (iir & ~flip_mask) != 0;
3612                 bool blc_event = false;
3613
3614                 /* Can't rely on pipestat interrupt bit in iir as it might
3615                  * have been cleared after the pipestat interrupt was received.
3616                  * It doesn't set the bit in iir again, but it still produces
3617                  * interrupts (for non-MSI).
3618                  */
3619                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3620                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3621                         i915_handle_error(dev, false,
3622                                           "Command parser error, iir 0x%08x",
3623                                           iir);
3624
3625                 for_each_pipe(pipe) {
3626                         int reg = PIPESTAT(pipe);
3627                         pipe_stats[pipe] = I915_READ(reg);
3628
3629                         /* Clear the PIPE*STAT regs before the IIR */
3630                         if (pipe_stats[pipe] & 0x8000ffff) {
3631                                 I915_WRITE(reg, pipe_stats[pipe]);
3632                                 irq_received = true;
3633                         }
3634                 }
3635                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3636
3637                 if (!irq_received)
3638                         break;
3639
3640                 /* Consume port.  Then clear IIR or we'll miss events */
3641                 if ((I915_HAS_HOTPLUG(dev)) &&
3642                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3643                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3644                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3645
3646                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3647
3648                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3649                         POSTING_READ(PORT_HOTPLUG_STAT);
3650                 }
3651
3652                 I915_WRITE(IIR, iir & ~flip_mask);
3653                 new_iir = I915_READ(IIR); /* Flush posted writes */
3654
3655                 if (iir & I915_USER_INTERRUPT)
3656                         notify_ring(dev, &dev_priv->ring[RCS]);
3657
3658                 for_each_pipe(pipe) {
3659                         int plane = pipe;
3660                         if (HAS_FBC(dev))
3661                                 plane = !plane;
3662
3663                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3664                             i915_handle_vblank(dev, plane, pipe, iir))
3665                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3666
3667                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3668                                 blc_event = true;
3669
3670                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3671                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3672
3673                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3674                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3675                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3676                 }
3677
3678                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3679                         intel_opregion_asle_intr(dev);
3680
3681                 /* With MSI, interrupts are only generated when iir
3682                  * transitions from zero to nonzero.  If another bit got
3683                  * set while we were handling the existing iir bits, then
3684                  * we would never get another interrupt.
3685                  *
3686                  * This is fine on non-MSI as well, as if we hit this path
3687                  * we avoid exiting the interrupt handler only to generate
3688                  * another one.
3689                  *
3690                  * Note that for MSI this could cause a stray interrupt report
3691                  * if an interrupt landed in the time between writing IIR and
3692                  * the posting read.  This should be rare enough to never
3693                  * trigger the 99% of 100,000 interrupts test for disabling
3694                  * stray interrupts.
3695                  */
3696                 ret = IRQ_HANDLED;
3697                 iir = new_iir;
3698         } while (iir & ~flip_mask);
3699
3700         i915_update_dri1_breadcrumb(dev);
3701
3702         return ret;
3703 }
3704
3705 static void i915_irq_uninstall(struct drm_device * dev)
3706 {
3707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3708         int pipe;
3709
3710         intel_hpd_irq_uninstall(dev_priv);
3711
3712         if (I915_HAS_HOTPLUG(dev)) {
3713                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3714                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3715         }
3716
3717         I915_WRITE16(HWSTAM, 0xffff);
3718         for_each_pipe(pipe) {
3719                 /* Clear enable bits; then clear status bits */
3720                 I915_WRITE(PIPESTAT(pipe), 0);
3721                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3722         }
3723         I915_WRITE(IMR, 0xffffffff);
3724         I915_WRITE(IER, 0x0);
3725
3726         I915_WRITE(IIR, I915_READ(IIR));
3727 }
3728
3729 static void i965_irq_preinstall(struct drm_device * dev)
3730 {
3731         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3732         int pipe;
3733
3734         I915_WRITE(PORT_HOTPLUG_EN, 0);
3735         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3736
3737         I915_WRITE(HWSTAM, 0xeffe);
3738         for_each_pipe(pipe)
3739                 I915_WRITE(PIPESTAT(pipe), 0);
3740         I915_WRITE(IMR, 0xffffffff);
3741         I915_WRITE(IER, 0x0);
3742         POSTING_READ(IER);
3743 }
3744
3745 static int i965_irq_postinstall(struct drm_device *dev)
3746 {
3747         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3748         u32 enable_mask;
3749         u32 error_mask;
3750         unsigned long irqflags;
3751
3752         /* Unmask the interrupts that we always want on. */
3753         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3754                                I915_DISPLAY_PORT_INTERRUPT |
3755                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3756                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3757                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3758                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3759                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3760
3761         enable_mask = ~dev_priv->irq_mask;
3762         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3763                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3764         enable_mask |= I915_USER_INTERRUPT;
3765
3766         if (IS_G4X(dev))
3767                 enable_mask |= I915_BSD_USER_INTERRUPT;
3768
3769         /* Interrupt setup is already guaranteed to be single-threaded, this is
3770          * just to make the assert_spin_locked check happy. */
3771         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3772         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3773         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3774         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3775         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3776
3777         /*
3778          * Enable some error detection, note the instruction error mask
3779          * bit is reserved, so we leave it masked.
3780          */
3781         if (IS_G4X(dev)) {
3782                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3783                                GM45_ERROR_MEM_PRIV |
3784                                GM45_ERROR_CP_PRIV |
3785                                I915_ERROR_MEMORY_REFRESH);
3786         } else {
3787                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3788                                I915_ERROR_MEMORY_REFRESH);
3789         }
3790         I915_WRITE(EMR, error_mask);
3791
3792         I915_WRITE(IMR, dev_priv->irq_mask);
3793         I915_WRITE(IER, enable_mask);
3794         POSTING_READ(IER);
3795
3796         I915_WRITE(PORT_HOTPLUG_EN, 0);
3797         POSTING_READ(PORT_HOTPLUG_EN);
3798
3799         i915_enable_asle_pipestat(dev);
3800
3801         return 0;
3802 }
3803
3804 static void i915_hpd_irq_setup(struct drm_device *dev)
3805 {
3806         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3807         struct drm_mode_config *mode_config = &dev->mode_config;
3808         struct intel_encoder *intel_encoder;
3809         u32 hotplug_en;
3810
3811         assert_spin_locked(&dev_priv->irq_lock);
3812
3813         if (I915_HAS_HOTPLUG(dev)) {
3814                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3815                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3816                 /* Note HDMI and DP share hotplug bits */
3817                 /* enable bits are the same for all generations */
3818                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3819                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3820                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3821                 /* Programming the CRT detection parameters tends
3822                    to generate a spurious hotplug event about three
3823                    seconds later.  So just do it once.
3824                 */
3825                 if (IS_G4X(dev))
3826                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3827                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3828                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3829
3830                 /* Ignore TV since it's buggy */
3831                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3832         }
3833 }
3834
3835 static irqreturn_t i965_irq_handler(int irq, void *arg)
3836 {
3837         struct drm_device *dev = (struct drm_device *) arg;
3838         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3839         u32 iir, new_iir;
3840         u32 pipe_stats[I915_MAX_PIPES];
3841         unsigned long irqflags;
3842         int ret = IRQ_NONE, pipe;
3843         u32 flip_mask =
3844                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3845                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3846
3847         iir = I915_READ(IIR);
3848
3849         for (;;) {
3850                 bool irq_received = (iir & ~flip_mask) != 0;
3851                 bool blc_event = false;
3852
3853                 /* Can't rely on pipestat interrupt bit in iir as it might
3854                  * have been cleared after the pipestat interrupt was received.
3855                  * It doesn't set the bit in iir again, but it still produces
3856                  * interrupts (for non-MSI).
3857                  */
3858                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3859                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3860                         i915_handle_error(dev, false,
3861                                           "Command parser error, iir 0x%08x",
3862                                           iir);
3863
3864                 for_each_pipe(pipe) {
3865                         int reg = PIPESTAT(pipe);
3866                         pipe_stats[pipe] = I915_READ(reg);
3867
3868                         /*
3869                          * Clear the PIPE*STAT regs before the IIR
3870                          */
3871                         if (pipe_stats[pipe] & 0x8000ffff) {
3872                                 I915_WRITE(reg, pipe_stats[pipe]);
3873                                 irq_received = true;
3874                         }
3875                 }
3876                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3877
3878                 if (!irq_received)
3879                         break;
3880
3881                 ret = IRQ_HANDLED;
3882
3883                 /* Consume port.  Then clear IIR or we'll miss events */
3884                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3885                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3886                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3887                                                                   HOTPLUG_INT_STATUS_G4X :
3888                                                                   HOTPLUG_INT_STATUS_I915);
3889
3890                         intel_hpd_irq_handler(dev, hotplug_trigger,
3891                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3892
3893                         if (IS_G4X(dev) &&
3894                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3895                                 dp_aux_irq_handler(dev);
3896
3897                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3898                         I915_READ(PORT_HOTPLUG_STAT);
3899                 }
3900
3901                 I915_WRITE(IIR, iir & ~flip_mask);
3902                 new_iir = I915_READ(IIR); /* Flush posted writes */
3903
3904                 if (iir & I915_USER_INTERRUPT)
3905                         notify_ring(dev, &dev_priv->ring[RCS]);
3906                 if (iir & I915_BSD_USER_INTERRUPT)
3907                         notify_ring(dev, &dev_priv->ring[VCS]);
3908
3909                 for_each_pipe(pipe) {
3910                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3911                             i915_handle_vblank(dev, pipe, pipe, iir))
3912                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3913
3914                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3915                                 blc_event = true;
3916
3917                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3918                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3919
3920                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3921                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3922                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3923                 }
3924
3925                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3926                         intel_opregion_asle_intr(dev);
3927
3928                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3929                         gmbus_irq_handler(dev);
3930
3931                 /* With MSI, interrupts are only generated when iir
3932                  * transitions from zero to nonzero.  If another bit got
3933                  * set while we were handling the existing iir bits, then
3934                  * we would never get another interrupt.
3935                  *
3936                  * This is fine on non-MSI as well, as if we hit this path
3937                  * we avoid exiting the interrupt handler only to generate
3938                  * another one.
3939                  *
3940                  * Note that for MSI this could cause a stray interrupt report
3941                  * if an interrupt landed in the time between writing IIR and
3942                  * the posting read.  This should be rare enough to never
3943                  * trigger the 99% of 100,000 interrupts test for disabling
3944                  * stray interrupts.
3945                  */
3946                 iir = new_iir;
3947         }
3948
3949         i915_update_dri1_breadcrumb(dev);
3950
3951         return ret;
3952 }
3953
3954 static void i965_irq_uninstall(struct drm_device * dev)
3955 {
3956         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3957         int pipe;
3958
3959         if (!dev_priv)
3960                 return;
3961
3962         intel_hpd_irq_uninstall(dev_priv);
3963
3964         I915_WRITE(PORT_HOTPLUG_EN, 0);
3965         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3966
3967         I915_WRITE(HWSTAM, 0xffffffff);
3968         for_each_pipe(pipe)
3969                 I915_WRITE(PIPESTAT(pipe), 0);
3970         I915_WRITE(IMR, 0xffffffff);
3971         I915_WRITE(IER, 0x0);
3972
3973         for_each_pipe(pipe)
3974                 I915_WRITE(PIPESTAT(pipe),
3975                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3976         I915_WRITE(IIR, I915_READ(IIR));
3977 }
3978
3979 static void intel_hpd_irq_reenable(unsigned long data)
3980 {
3981         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3982         struct drm_device *dev = dev_priv->dev;
3983         struct drm_mode_config *mode_config = &dev->mode_config;
3984         unsigned long irqflags;
3985         int i;
3986
3987         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3988         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3989                 struct drm_connector *connector;
3990
3991                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3992                         continue;
3993
3994                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3995
3996                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3997                         struct intel_connector *intel_connector = to_intel_connector(connector);
3998
3999                         if (intel_connector->encoder->hpd_pin == i) {
4000                                 if (connector->polled != intel_connector->polled)
4001                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4002                                                          drm_get_connector_name(connector));
4003                                 connector->polled = intel_connector->polled;
4004                                 if (!connector->polled)
4005                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4006                         }
4007                 }
4008         }
4009         if (dev_priv->display.hpd_irq_setup)
4010                 dev_priv->display.hpd_irq_setup(dev);
4011         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4012 }
4013
4014 void intel_irq_init(struct drm_device *dev)
4015 {
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017
4018         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4019         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4020         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4021         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4022
4023         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4024                     i915_hangcheck_elapsed,
4025                     (unsigned long) dev);
4026         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4027                     (unsigned long) dev_priv);
4028
4029         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4030
4031         if (IS_GEN2(dev)) {
4032                 dev->max_vblank_count = 0;
4033                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4034         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4035                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4036                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4037         } else {
4038                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4039                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4040         }
4041
4042         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4043                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4044                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4045         }
4046
4047         if (IS_VALLEYVIEW(dev)) {
4048                 dev->driver->irq_handler = valleyview_irq_handler;
4049                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4050                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4051                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4052                 dev->driver->enable_vblank = valleyview_enable_vblank;
4053                 dev->driver->disable_vblank = valleyview_disable_vblank;
4054                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4055         } else if (IS_GEN8(dev)) {
4056                 dev->driver->irq_handler = gen8_irq_handler;
4057                 dev->driver->irq_preinstall = gen8_irq_preinstall;
4058                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4059                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4060                 dev->driver->enable_vblank = gen8_enable_vblank;
4061                 dev->driver->disable_vblank = gen8_disable_vblank;
4062                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4063         } else if (HAS_PCH_SPLIT(dev)) {
4064                 dev->driver->irq_handler = ironlake_irq_handler;
4065                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4066                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4067                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4068                 dev->driver->enable_vblank = ironlake_enable_vblank;
4069                 dev->driver->disable_vblank = ironlake_disable_vblank;
4070                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4071         } else {
4072                 if (INTEL_INFO(dev)->gen == 2) {
4073                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4074                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4075                         dev->driver->irq_handler = i8xx_irq_handler;
4076                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4077                 } else if (INTEL_INFO(dev)->gen == 3) {
4078                         dev->driver->irq_preinstall = i915_irq_preinstall;
4079                         dev->driver->irq_postinstall = i915_irq_postinstall;
4080                         dev->driver->irq_uninstall = i915_irq_uninstall;
4081                         dev->driver->irq_handler = i915_irq_handler;
4082                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4083                 } else {
4084                         dev->driver->irq_preinstall = i965_irq_preinstall;
4085                         dev->driver->irq_postinstall = i965_irq_postinstall;
4086                         dev->driver->irq_uninstall = i965_irq_uninstall;
4087                         dev->driver->irq_handler = i965_irq_handler;
4088                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4089                 }
4090                 dev->driver->enable_vblank = i915_enable_vblank;
4091                 dev->driver->disable_vblank = i915_disable_vblank;
4092         }
4093 }
4094
4095 void intel_hpd_init(struct drm_device *dev)
4096 {
4097         struct drm_i915_private *dev_priv = dev->dev_private;
4098         struct drm_mode_config *mode_config = &dev->mode_config;
4099         struct drm_connector *connector;
4100         unsigned long irqflags;
4101         int i;
4102
4103         for (i = 1; i < HPD_NUM_PINS; i++) {
4104                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4105                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4106         }
4107         list_for_each_entry(connector, &mode_config->connector_list, head) {
4108                 struct intel_connector *intel_connector = to_intel_connector(connector);
4109                 connector->polled = intel_connector->polled;
4110                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4111                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4112         }
4113
4114         /* Interrupt setup is already guaranteed to be single-threaded, this is
4115          * just to make the assert_spin_locked checks happy. */
4116         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4117         if (dev_priv->display.hpd_irq_setup)
4118                 dev_priv->display.hpd_irq_setup(dev);
4119         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4120 }
4121
4122 /* Disable interrupts so we can allow runtime PM. */
4123 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
4124 {
4125         struct drm_i915_private *dev_priv = dev->dev_private;
4126         unsigned long irqflags;
4127
4128         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4129
4130         dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
4131         dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
4132         dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
4133         dev_priv->pm.regsave.gtier = I915_READ(GTIER);
4134         dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4135
4136         ironlake_disable_display_irq(dev_priv, 0xffffffff);
4137         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4138         ilk_disable_gt_irq(dev_priv, 0xffffffff);
4139         snb_disable_pm_irq(dev_priv, 0xffffffff);
4140
4141         dev_priv->pm.irqs_disabled = true;
4142
4143         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4144 }
4145
4146 /* Restore interrupts so we can recover from runtime PM. */
4147 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
4148 {
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         unsigned long irqflags;
4151         uint32_t val;
4152
4153         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4154
4155         val = I915_READ(DEIMR);
4156         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4157
4158         val = I915_READ(SDEIMR);
4159         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4160
4161         val = I915_READ(GTIMR);
4162         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4163
4164         val = I915_READ(GEN6_PMIMR);
4165         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4166
4167         dev_priv->pm.irqs_disabled = false;
4168
4169         ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
4170         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
4171         ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
4172         snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
4173         I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
4174
4175         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4176 }