drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 236                                                  enum pipe pipe, bool enable)
 237 {
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 240                                           DE_PIPEB_FIFO_UNDERRUN;
 241
 242         if (enable)
 243                 ironlake_enable_display_irq(dev_priv, bit);
 244         else
 245                 ironlake_disable_display_irq(dev_priv, bit);
 246 }
 247
 248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 249                                                   enum pipe pipe, bool enable)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         if (enable) {
 253                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 254
 255                 if (!ivb_can_enable_err_int(dev))
 256                         return;
 257
 258                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 259         } else {
 260                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 261
 262                 /* Change the state _after_ we've read out the current one. */
 263                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 264
 265                 if (!was_enabled &&
 266                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 267                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 268                                       pipe_name(pipe));
 269                 }
 270         }
 271 }
 272
 273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 274                                                   enum pipe pipe, bool enable)
 275 {
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277
 278         assert_spin_locked(&dev_priv->irq_lock);
 279
 280         if (enable)
 281                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 282         else
 283                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 284         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 285         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 286 }
 287
 288 /**
 289  * ibx_display_interrupt_update - update SDEIMR
 290  * @dev_priv: driver private
 291  * @interrupt_mask: mask of interrupt bits to update
 292  * @enabled_irq_mask: mask of interrupt bits to enable
 293  */
 294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 295                                          uint32_t interrupt_mask,
 296                                          uint32_t enabled_irq_mask)
 297 {
 298         uint32_t sdeimr = I915_READ(SDEIMR);
 299         sdeimr &= ~interrupt_mask;
 300         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 301
 302         assert_spin_locked(&dev_priv->irq_lock);
 303
 304         if (dev_priv->pc8.irqs_disabled &&
 305             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 306                 WARN(1, "IRQs disabled\n");
 307                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 308                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 309                                                  interrupt_mask);
 310                 return;
 311         }
 312
 313         I915_WRITE(SDEIMR, sdeimr);
 314         POSTING_READ(SDEIMR);
 315 }
 316 #define ibx_enable_display_interrupt(dev_priv, bits) \
 317         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 318 #define ibx_disable_display_interrupt(dev_priv, bits) \
 319         ibx_display_interrupt_update((dev_priv), (bits), 0)
 320
 321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 322                                             enum transcoder pch_transcoder,
 323                                             bool enable)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 327                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 328
 329         if (enable)
 330                 ibx_enable_display_interrupt(dev_priv, bit);
 331         else
 332                 ibx_disable_display_interrupt(dev_priv, bit);
 333 }
 334
 335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 336                                             enum transcoder pch_transcoder,
 337                                             bool enable)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (enable) {
 342                 I915_WRITE(SERR_INT,
 343                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 344
 345                 if (!cpt_can_enable_serr_int(dev))
 346                         return;
 347
 348                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 349         } else {
 350                 uint32_t tmp = I915_READ(SERR_INT);
 351                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 352
 353                 /* Change the state _after_ we've read out the current one. */
 354                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 355
 356                 if (!was_enabled &&
 357                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 358                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 359                                       transcoder_name(pch_transcoder));
 360                 }
 361         }
 362 }
 363
 364 /**
 365  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 366  * @dev: drm device
 367  * @pipe: pipe
 368  * @enable: true if we want to report FIFO underrun errors, false otherwise
 369  *
 370  * This function makes us disable or enable CPU fifo underruns for a specific
 371  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 372  * reporting for one pipe may also disable all the other CPU error interruts for
 373  * the other pipes, due to the fact that there's just one interrupt mask/enable
 374  * bit for all the pipes.
 375  *
 376  * Returns the previous state of underrun reporting.
 377  */
 378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 379                                            enum pipe pipe, bool enable)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 384         unsigned long flags;
 385         bool ret;
 386
 387         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 388
 389         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 390
 391         if (enable == ret)
 392                 goto done;
 393
 394         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 395
 396         if (IS_GEN5(dev) || IS_GEN6(dev))
 397                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 398         else if (IS_GEN7(dev))
 399                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 400         else if (IS_GEN8(dev))
 401                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 402
 403 done:
 404         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 405         return ret;
 406 }
 407
 408 /**
 409  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 410  * @dev: drm device
 411  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 412  * @enable: true if we want to report FIFO underrun errors, false otherwise
 413  *
 414  * This function makes us disable or enable PCH fifo underruns for a specific
 415  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 416  * underrun reporting for one transcoder may also disable all the other PCH
 417  * error interruts for the other transcoders, due to the fact that there's just
 418  * one interrupt mask/enable bit for all the transcoders.
 419  *
 420  * Returns the previous state of underrun reporting.
 421  */
 422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 423                                            enum transcoder pch_transcoder,
 424                                            bool enable)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 429         unsigned long flags;
 430         bool ret;
 431
 432         /*
 433          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 434          * has only one pch transcoder A that all pipes can use. To avoid racy
 435          * pch transcoder -> pipe lookups from interrupt code simply store the
 436          * underrun statistics in crtc A. Since we never expose this anywhere
 437          * nor use it outside of the fifo underrun code here using the "wrong"
 438          * crtc on LPT won't cause issues.
 439          */
 440
 441         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 442
 443         ret = !intel_crtc->pch_fifo_underrun_disabled;
 444
 445         if (enable == ret)
 446                 goto done;
 447
 448         intel_crtc->pch_fifo_underrun_disabled = !enable;
 449
 450         if (HAS_PCH_IBX(dev))
 451                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 452         else
 453                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 454
 455 done:
 456         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 457         return ret;
 458 }
 459
 460
 461 void
 462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 463 {
 464         u32 reg = PIPESTAT(pipe);
 465         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 466
 467         assert_spin_locked(&dev_priv->irq_lock);
 468
 469         if ((pipestat & mask) == mask)
 470                 return;
 471
 472         /* Enable the interrupt, clear any pending status */
 473         pipestat |= mask | (mask >> 16);
 474         I915_WRITE(reg, pipestat);
 475         POSTING_READ(reg);
 476 }
 477
 478 void
 479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 480 {
 481         u32 reg = PIPESTAT(pipe);
 482         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 483
 484         assert_spin_locked(&dev_priv->irq_lock);
 485
 486         if ((pipestat & mask) == 0)
 487                 return;
 488
 489         pipestat &= ~mask;
 490         I915_WRITE(reg, pipestat);
 491         POSTING_READ(reg);
 492 }
 493
 494 /**
 495  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 496  */
 497 static void i915_enable_asle_pipestat(struct drm_device *dev)
 498 {
 499         drm_i915_private_t *dev_priv = dev->dev_private;
 500         unsigned long irqflags;
 501
 502         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 503                 return;
 504
 505         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 506
 507         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
 508         if (INTEL_INFO(dev)->gen >= 4)
 509                 i915_enable_pipestat(dev_priv, PIPE_A,
 510                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 511
 512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 513 }
 514
 515 /**
 516  * i915_pipe_enabled - check if a pipe is enabled
 517  * @dev: DRM device
 518  * @pipe: pipe to check
 519  *
 520  * Reading certain registers when the pipe is disabled can hang the chip.
 521  * Use this routine to make sure the PLL is running and the pipe is active
 522  * before reading such registers if unsure.
 523  */
 524 static int
 525 i915_pipe_enabled(struct drm_device *dev, int pipe)
 526 {
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528
 529         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 530                 /* Locking is horribly broken here, but whatever. */
 531                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 533
 534                 return intel_crtc->active;
 535         } else {
 536                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 537         }
 538 }
 539
 540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 541 {
 542         /* Gen2 doesn't have a hardware frame counter */
 543         return 0;
 544 }
 545
 546 /* Called from drm generic code, passed a 'crtc', which
 547  * we use as a pipe index
 548  */
 549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 550 {
 551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 552         unsigned long high_frame;
 553         unsigned long low_frame;
 554         u32 high1, high2, low, pixel, vbl_start;
 555
 556         if (!i915_pipe_enabled(dev, pipe)) {
 557                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 558                                 "pipe %c\n", pipe_name(pipe));
 559                 return 0;
 560         }
 561
 562         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 563                 struct intel_crtc *intel_crtc =
 564                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 565                 const struct drm_display_mode *mode =
 566                         &intel_crtc->config.adjusted_mode;
 567
 568                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 569         } else {
 570                 enum transcoder cpu_transcoder =
 571                         intel_pipe_to_cpu_transcoder(dev_priv, pipe);
 572                 u32 htotal;
 573
 574                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 575                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 576
 577                 vbl_start *= htotal;
 578         }
 579
 580         high_frame = PIPEFRAME(pipe);
 581         low_frame = PIPEFRAMEPIXEL(pipe);
 582
 583         /*
 584          * High & low register fields aren't synchronized, so make sure
 585          * we get a low value that's stable across two reads of the high
 586          * register.
 587          */
 588         do {
 589                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 590                 low   = I915_READ(low_frame);
 591                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 592         } while (high1 != high2);
 593
 594         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 595         pixel = low & PIPE_PIXEL_MASK;
 596         low >>= PIPE_FRAME_LOW_SHIFT;
 597
 598         /*
 599          * The frame counter increments at beginning of active.
 600          * Cook up a vblank counter by also checking the pixel
 601          * counter against vblank start.
 602          */
 603         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 604 }
 605
 606 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 607 {
 608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 609         int reg = PIPE_FRMCOUNT_GM45(pipe);
 610
 611         if (!i915_pipe_enabled(dev, pipe)) {
 612                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 613                                  "pipe %c\n", pipe_name(pipe));
 614                 return 0;
 615         }
 616
 617         return I915_READ(reg);
 618 }
 619
 620 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 621 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 622 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 623
 624 static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         uint32_t status;
 628         int reg;
 629
 630         if (IS_VALLEYVIEW(dev)) {
 631                 status = pipe == PIPE_A ?
 632                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 633                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 634
 635                 reg = VLV_ISR;
 636         } else if (IS_GEN2(dev)) {
 637                 status = pipe == PIPE_A ?
 638                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 639                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 640
 641                 reg = ISR;
 642         } else if (INTEL_INFO(dev)->gen < 5) {
 643                 status = pipe == PIPE_A ?
 644                         I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
 645                         I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 646
 647                 reg = ISR;
 648         } else if (INTEL_INFO(dev)->gen < 7) {
 649                 status = pipe == PIPE_A ?
 650                         DE_PIPEA_VBLANK :
 651                         DE_PIPEB_VBLANK;
 652
 653                 reg = DEISR;
 654         } else {
 655                 switch (pipe) {
 656                 default:
 657                 case PIPE_A:
 658                         status = DE_PIPEA_VBLANK_IVB;
 659                         break;
 660                 case PIPE_B:
 661                         status = DE_PIPEB_VBLANK_IVB;
 662                         break;
 663                 case PIPE_C:
 664                         status = DE_PIPEC_VBLANK_IVB;
 665                         break;
 666                 }
 667
 668                 reg = DEISR;
 669         }
 670
 671         if (IS_GEN2(dev))
 672                 return __raw_i915_read16(dev_priv, reg) & status;
 673         else
 674                 return __raw_i915_read32(dev_priv, reg) & status;
 675 }
 676
 677 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 678                              int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
 679 {
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 683         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 684         int position;
 685         int vbl_start, vbl_end, htotal, vtotal;
 686         bool in_vbl = true;
 687         int ret = 0;
 688         unsigned long irqflags;
 689
 690         if (!intel_crtc->active) {
 691                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 692                                  "pipe %c\n", pipe_name(pipe));
 693                 return 0;
 694         }
 695
 696         htotal = mode->crtc_htotal;
 697         vtotal = mode->crtc_vtotal;
 698         vbl_start = mode->crtc_vblank_start;
 699         vbl_end = mode->crtc_vblank_end;
 700
 701         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 702
 703         /*
 704          * Lock uncore.lock, as we will do multiple timing critical raw
 705          * register reads, potentially with preemption disabled, so the
 706          * following code must not block on uncore.lock.
 707          */
 708         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 709
 710         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 711
 712         /* Get optional system timestamp before query. */
 713         if (stime)
 714                 *stime = ktime_get();
 715
 716         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 717                 /* No obvious pixelcount register. Only query vertical
 718                  * scanout position from Display scan line register.
 719                  */
 720                 if (IS_GEN2(dev))
 721                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 722                 else
 723                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 724
 725                 /*
 726                  * The scanline counter increments at the leading edge
 727                  * of hsync, ie. it completely misses the active portion
 728                  * of the line. Fix up the counter at both edges of vblank
 729                  * to get a more accurate picture whether we're in vblank
 730                  * or not.
 731                  */
 732                 in_vbl = intel_pipe_in_vblank_locked(dev, pipe);
 733                 if ((in_vbl && position == vbl_start - 1) ||
 734                     (!in_vbl && position == vbl_end - 1))
 735                         position = (position + 1) % vtotal;
 736         } else {
 737                 /* Have access to pixelcount since start of frame.
 738                  * We can split this into vertical and horizontal
 739                  * scanout position.
 740                  */
 741                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 742
 743                 /* convert to pixel counts */
 744                 vbl_start *= htotal;
 745                 vbl_end *= htotal;
 746                 vtotal *= htotal;
 747         }
 748
 749         /* Get optional system timestamp after query. */
 750         if (etime)
 751                 *etime = ktime_get();
 752
 753         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 754
 755         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 756
 757         in_vbl = position >= vbl_start && position < vbl_end;
 758
 759         /*
 760          * While in vblank, position will be negative
 761          * counting up towards 0 at vbl_end. And outside
 762          * vblank, position will be positive counting
 763          * up since vbl_end.
 764          */
 765         if (position >= vbl_start)
 766                 position -= vbl_end;
 767         else
 768                 position += vtotal - vbl_end;
 769
 770         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 771                 *vpos = position;
 772                 *hpos = 0;
 773         } else {
 774                 *vpos = position / htotal;
 775                 *hpos = position - (*vpos * htotal);
 776         }
 777
 778         /* In vblank? */
 779         if (in_vbl)
 780                 ret |= DRM_SCANOUTPOS_INVBL;
 781
 782         return ret;
 783 }
 784
 785 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 786                               int *max_error,
 787                               struct timeval *vblank_time,
 788                               unsigned flags)
 789 {
 790         struct drm_crtc *crtc;
 791
 792         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 793                 DRM_ERROR("Invalid crtc %d\n", pipe);
 794                 return -EINVAL;
 795         }
 796
 797         /* Get drm_crtc to timestamp: */
 798         crtc = intel_get_crtc_for_pipe(dev, pipe);
 799         if (crtc == NULL) {
 800                 DRM_ERROR("Invalid crtc %d\n", pipe);
 801                 return -EINVAL;
 802         }
 803
 804         if (!crtc->enabled) {
 805                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 806                 return -EBUSY;
 807         }
 808
 809         /* Helper routine in DRM core does all the work: */
 810         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 811                                                      vblank_time, flags,
 812                                                      crtc,
 813                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 814 }
 815
 816 static bool intel_hpd_irq_event(struct drm_device *dev,
 817                                 struct drm_connector *connector)
 818 {
 819         enum drm_connector_status old_status;
 820
 821         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 822         old_status = connector->status;
 823
 824         connector->status = connector->funcs->detect(connector, false);
 825         if (old_status == connector->status)
 826                 return false;
 827
 828         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 829                       connector->base.id,
 830                       drm_get_connector_name(connector),
 831                       drm_get_connector_status_name(old_status),
 832                       drm_get_connector_status_name(connector->status));
 833
 834         return true;
 835 }
 836
 837 /*
 838  * Handle hotplug events outside the interrupt handler proper.
 839  */
 840 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 841
 842 static void i915_hotplug_work_func(struct work_struct *work)
 843 {
 844         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 845                                                     hotplug_work);
 846         struct drm_device *dev = dev_priv->dev;
 847         struct drm_mode_config *mode_config = &dev->mode_config;
 848         struct intel_connector *intel_connector;
 849         struct intel_encoder *intel_encoder;
 850         struct drm_connector *connector;
 851         unsigned long irqflags;
 852         bool hpd_disabled = false;
 853         bool changed = false;
 854         u32 hpd_event_bits;
 855
 856         /* HPD irq before everything is fully set up. */
 857         if (!dev_priv->enable_hotplug_processing)
 858                 return;
 859
 860         mutex_lock(&mode_config->mutex);
 861         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 862
 863         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 864
 865         hpd_event_bits = dev_priv->hpd_event_bits;
 866         dev_priv->hpd_event_bits = 0;
 867         list_for_each_entry(connector, &mode_config->connector_list, head) {
 868                 intel_connector = to_intel_connector(connector);
 869                 intel_encoder = intel_connector->encoder;
 870                 if (intel_encoder->hpd_pin > HPD_NONE &&
 871                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 872                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 873                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 874                                  "switching from hotplug detection to polling\n",
 875                                 drm_get_connector_name(connector));
 876                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 877                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 878                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 879                         hpd_disabled = true;
 880                 }
 881                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 882                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 883                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 884                 }
 885         }
 886          /* if there were no outputs to poll, poll was disabled,
 887           * therefore make sure it's enabled when disabling HPD on
 888           * some connectors */
 889         if (hpd_disabled) {
 890                 drm_kms_helper_poll_enable(dev);
 891                 mod_timer(&dev_priv->hotplug_reenable_timer,
 892                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 893         }
 894
 895         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 896
 897         list_for_each_entry(connector, &mode_config->connector_list, head) {
 898                 intel_connector = to_intel_connector(connector);
 899                 intel_encoder = intel_connector->encoder;
 900                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 901                         if (intel_encoder->hot_plug)
 902                                 intel_encoder->hot_plug(intel_encoder);
 903                         if (intel_hpd_irq_event(dev, connector))
 904                                 changed = true;
 905                 }
 906         }
 907         mutex_unlock(&mode_config->mutex);
 908
 909         if (changed)
 910                 drm_kms_helper_hotplug_event(dev);
 911 }
 912
 913 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 914 {
 915         drm_i915_private_t *dev_priv = dev->dev_private;
 916         u32 busy_up, busy_down, max_avg, min_avg;
 917         u8 new_delay;
 918
 919         spin_lock(&mchdev_lock);
 920
 921         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 922
 923         new_delay = dev_priv->ips.cur_delay;
 924
 925         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 926         busy_up = I915_READ(RCPREVBSYTUPAVG);
 927         busy_down = I915_READ(RCPREVBSYTDNAVG);
 928         max_avg = I915_READ(RCBMAXAVG);
 929         min_avg = I915_READ(RCBMINAVG);
 930
 931         /* Handle RCS change request from hw */
 932         if (busy_up > max_avg) {
 933                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 934                         new_delay = dev_priv->ips.cur_delay - 1;
 935                 if (new_delay < dev_priv->ips.max_delay)
 936                         new_delay = dev_priv->ips.max_delay;
 937         } else if (busy_down < min_avg) {
 938                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 939                         new_delay = dev_priv->ips.cur_delay + 1;
 940                 if (new_delay > dev_priv->ips.min_delay)
 941                         new_delay = dev_priv->ips.min_delay;
 942         }
 943
 944         if (ironlake_set_drps(dev, new_delay))
 945                 dev_priv->ips.cur_delay = new_delay;
 946
 947         spin_unlock(&mchdev_lock);
 948
 949         return;
 950 }
 951
 952 static void notify_ring(struct drm_device *dev,
 953                         struct intel_ring_buffer *ring)
 954 {
 955         if (ring->obj == NULL)
 956                 return;
 957
 958         trace_i915_gem_request_complete(ring);
 959
 960         wake_up_all(&ring->irq_queue);
 961         i915_queue_hangcheck(dev);
 962 }
 963
 964 static void gen6_pm_rps_work(struct work_struct *work)
 965 {
 966         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 967                                                     rps.work);
 968         u32 pm_iir;
 969         int new_delay, adj;
 970
 971         spin_lock_irq(&dev_priv->irq_lock);
 972         pm_iir = dev_priv->rps.pm_iir;
 973         dev_priv->rps.pm_iir = 0;
 974         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 975         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 976         spin_unlock_irq(&dev_priv->irq_lock);
 977
 978         /* Make sure we didn't queue anything we're not going to process. */
 979         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 980
 981         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 982                 return;
 983
 984         mutex_lock(&dev_priv->rps.hw_lock);
 985
 986         adj = dev_priv->rps.last_adj;
 987         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 988                 if (adj > 0)
 989                         adj *= 2;
 990                 else
 991                         adj = 1;
 992                 new_delay = dev_priv->rps.cur_delay + adj;
 993
 994                 /*
 995                  * For better performance, jump directly
 996                  * to RPe if we're below it.
 997                  */
 998                 if (new_delay < dev_priv->rps.rpe_delay)
 999                         new_delay = dev_priv->rps.rpe_delay;
1000         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1001                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1002                         new_delay = dev_priv->rps.rpe_delay;
1003                 else
1004                         new_delay = dev_priv->rps.min_delay;
1005                 adj = 0;
1006         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1007                 if (adj < 0)
1008                         adj *= 2;
1009                 else
1010                         adj = -1;
1011                 new_delay = dev_priv->rps.cur_delay + adj;
1012         } else { /* unknown event */
1013                 new_delay = dev_priv->rps.cur_delay;
1014         }
1015
1016         /* sysfs frequency interfaces may have snuck in while servicing the
1017          * interrupt
1018          */
1019         new_delay = clamp_t(int, new_delay,
1020                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1021         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1022
1023         if (IS_VALLEYVIEW(dev_priv->dev))
1024                 valleyview_set_rps(dev_priv->dev, new_delay);
1025         else
1026                 gen6_set_rps(dev_priv->dev, new_delay);
1027
1028         mutex_unlock(&dev_priv->rps.hw_lock);
1029 }
1030
1031
1032 /**
1033  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1034  * occurred.
1035  * @work: workqueue struct
1036  *
1037  * Doesn't actually do anything except notify userspace. As a consequence of
1038  * this event, userspace should try to remap the bad rows since statistically
1039  * it is likely the same row is more likely to go bad again.
1040  */
1041 static void ivybridge_parity_work(struct work_struct *work)
1042 {
1043         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1044                                                     l3_parity.error_work);
1045         u32 error_status, row, bank, subbank;
1046         char *parity_event[6];
1047         uint32_t misccpctl;
1048         unsigned long flags;
1049         uint8_t slice = 0;
1050
1051         /* We must turn off DOP level clock gating to access the L3 registers.
1052          * In order to prevent a get/put style interface, acquire struct mutex
1053          * any time we access those registers.
1054          */
1055         mutex_lock(&dev_priv->dev->struct_mutex);
1056
1057         /* If we've screwed up tracking, just let the interrupt fire again */
1058         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1059                 goto out;
1060
1061         misccpctl = I915_READ(GEN7_MISCCPCTL);
1062         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1063         POSTING_READ(GEN7_MISCCPCTL);
1064
1065         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1066                 u32 reg;
1067
1068                 slice--;
1069                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1070                         break;
1071
1072                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1073
1074                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1075
1076                 error_status = I915_READ(reg);
1077                 row = GEN7_PARITY_ERROR_ROW(error_status);
1078                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1079                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1080
1081                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1082                 POSTING_READ(reg);
1083
1084                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1085                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1086                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1087                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1088                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1089                 parity_event[5] = NULL;
1090
1091                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1092                                    KOBJ_CHANGE, parity_event);
1093
1094                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1095                           slice, row, bank, subbank);
1096
1097                 kfree(parity_event[4]);
1098                 kfree(parity_event[3]);
1099                 kfree(parity_event[2]);
1100                 kfree(parity_event[1]);
1101         }
1102
1103         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1104
1105 out:
1106         WARN_ON(dev_priv->l3_parity.which_slice);
1107         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1108         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1109         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1110
1111         mutex_unlock(&dev_priv->dev->struct_mutex);
1112 }
1113
1114 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1115 {
1116         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1117
1118         if (!HAS_L3_DPF(dev))
1119                 return;
1120
1121         spin_lock(&dev_priv->irq_lock);
1122         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1123         spin_unlock(&dev_priv->irq_lock);
1124
1125         iir &= GT_PARITY_ERROR(dev);
1126         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1127                 dev_priv->l3_parity.which_slice |= 1 << 1;
1128
1129         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1130                 dev_priv->l3_parity.which_slice |= 1 << 0;
1131
1132         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1133 }
1134
1135 static void ilk_gt_irq_handler(struct drm_device *dev,
1136                                struct drm_i915_private *dev_priv,
1137                                u32 gt_iir)
1138 {
1139         if (gt_iir &
1140             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1141                 notify_ring(dev, &dev_priv->ring[RCS]);
1142         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1143                 notify_ring(dev, &dev_priv->ring[VCS]);
1144 }
1145
1146 static void snb_gt_irq_handler(struct drm_device *dev,
1147                                struct drm_i915_private *dev_priv,
1148                                u32 gt_iir)
1149 {
1150
1151         if (gt_iir &
1152             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1153                 notify_ring(dev, &dev_priv->ring[RCS]);
1154         if (gt_iir & GT_BSD_USER_INTERRUPT)
1155                 notify_ring(dev, &dev_priv->ring[VCS]);
1156         if (gt_iir & GT_BLT_USER_INTERRUPT)
1157                 notify_ring(dev, &dev_priv->ring[BCS]);
1158
1159         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1160                       GT_BSD_CS_ERROR_INTERRUPT |
1161                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1162                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1163                 i915_handle_error(dev, false);
1164         }
1165
1166         if (gt_iir & GT_PARITY_ERROR(dev))
1167                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1168 }
1169
1170 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1171                                        struct drm_i915_private *dev_priv,
1172                                        u32 master_ctl)
1173 {
1174         u32 rcs, bcs, vcs;
1175         uint32_t tmp = 0;
1176         irqreturn_t ret = IRQ_NONE;
1177
1178         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1179                 tmp = I915_READ(GEN8_GT_IIR(0));
1180                 if (tmp) {
1181                         ret = IRQ_HANDLED;
1182                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1183                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1184                         if (rcs & GT_RENDER_USER_INTERRUPT)
1185                                 notify_ring(dev, &dev_priv->ring[RCS]);
1186                         if (bcs & GT_RENDER_USER_INTERRUPT)
1187                                 notify_ring(dev, &dev_priv->ring[BCS]);
1188                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1189                 } else
1190                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1191         }
1192
1193         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1194                 tmp = I915_READ(GEN8_GT_IIR(1));
1195                 if (tmp) {
1196                         ret = IRQ_HANDLED;
1197                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1198                         if (vcs & GT_RENDER_USER_INTERRUPT)
1199                                 notify_ring(dev, &dev_priv->ring[VCS]);
1200                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1201                 } else
1202                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1203         }
1204
1205         if (master_ctl & GEN8_GT_VECS_IRQ) {
1206                 tmp = I915_READ(GEN8_GT_IIR(3));
1207                 if (tmp) {
1208                         ret = IRQ_HANDLED;
1209                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1210                         if (vcs & GT_RENDER_USER_INTERRUPT)
1211                                 notify_ring(dev, &dev_priv->ring[VECS]);
1212                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1213                 } else
1214                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1215         }
1216
1217         return ret;
1218 }
1219
1220 #define HPD_STORM_DETECT_PERIOD 1000
1221 #define HPD_STORM_THRESHOLD 5
1222
1223 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1224                                          u32 hotplug_trigger,
1225                                          const u32 *hpd)
1226 {
1227         drm_i915_private_t *dev_priv = dev->dev_private;
1228         int i;
1229         bool storm_detected = false;
1230
1231         if (!hotplug_trigger)
1232                 return;
1233
1234         spin_lock(&dev_priv->irq_lock);
1235         for (i = 1; i < HPD_NUM_PINS; i++) {
1236
1237                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1238                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1239                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1240                           hotplug_trigger, i, hpd[i]);
1241
1242                 if (!(hpd[i] & hotplug_trigger) ||
1243                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1244                         continue;
1245
1246                 dev_priv->hpd_event_bits |= (1 << i);
1247                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1248                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1249                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1250                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1251                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1252                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1253                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1254                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1255                         dev_priv->hpd_event_bits &= ~(1 << i);
1256                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1257                         storm_detected = true;
1258                 } else {
1259                         dev_priv->hpd_stats[i].hpd_cnt++;
1260                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1261                                       dev_priv->hpd_stats[i].hpd_cnt);
1262                 }
1263         }
1264
1265         if (storm_detected)
1266                 dev_priv->display.hpd_irq_setup(dev);
1267         spin_unlock(&dev_priv->irq_lock);
1268
1269         /*
1270          * Our hotplug handler can grab modeset locks (by calling down into the
1271          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1272          * queue for otherwise the flush_work in the pageflip code will
1273          * deadlock.
1274          */
1275         schedule_work(&dev_priv->hotplug_work);
1276 }
1277
1278 static void gmbus_irq_handler(struct drm_device *dev)
1279 {
1280         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1281
1282         wake_up_all(&dev_priv->gmbus_wait_queue);
1283 }
1284
1285 static void dp_aux_irq_handler(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1288
1289         wake_up_all(&dev_priv->gmbus_wait_queue);
1290 }
1291
1292 #if defined(CONFIG_DEBUG_FS)
1293 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1294                                          uint32_t crc0, uint32_t crc1,
1295                                          uint32_t crc2, uint32_t crc3,
1296                                          uint32_t crc4)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1300         struct intel_pipe_crc_entry *entry;
1301         int head, tail;
1302
1303         spin_lock(&pipe_crc->lock);
1304
1305         if (!pipe_crc->entries) {
1306                 spin_unlock(&pipe_crc->lock);
1307                 DRM_ERROR("spurious interrupt\n");
1308                 return;
1309         }
1310
1311         head = pipe_crc->head;
1312         tail = pipe_crc->tail;
1313
1314         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1315                 spin_unlock(&pipe_crc->lock);
1316                 DRM_ERROR("CRC buffer overflowing\n");
1317                 return;
1318         }
1319
1320         entry = &pipe_crc->entries[head];
1321
1322         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1323         entry->crc[0] = crc0;
1324         entry->crc[1] = crc1;
1325         entry->crc[2] = crc2;
1326         entry->crc[3] = crc3;
1327         entry->crc[4] = crc4;
1328
1329         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1330         pipe_crc->head = head;
1331
1332         spin_unlock(&pipe_crc->lock);
1333
1334         wake_up_interruptible(&pipe_crc->wq);
1335 }
1336 #else
1337 static inline void
1338 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1339                              uint32_t crc0, uint32_t crc1,
1340                              uint32_t crc2, uint32_t crc3,
1341                              uint32_t crc4) {}
1342 #endif
1343
1344
1345 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1346 {
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348
1349         display_pipe_crc_irq_handler(dev, pipe,
1350                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1351                                      0, 0, 0, 0);
1352 }
1353
1354 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1355 {
1356         struct drm_i915_private *dev_priv = dev->dev_private;
1357
1358         display_pipe_crc_irq_handler(dev, pipe,
1359                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1360                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1361                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1362                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1363                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1364 }
1365
1366 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1367 {
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         uint32_t res1, res2;
1370
1371         if (INTEL_INFO(dev)->gen >= 3)
1372                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1373         else
1374                 res1 = 0;
1375
1376         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1377                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1378         else
1379                 res2 = 0;
1380
1381         display_pipe_crc_irq_handler(dev, pipe,
1382                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1383                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1384                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1385                                      res1, res2);
1386 }
1387
1388 /* The RPS events need forcewake, so we add them to a work queue and mask their
1389  * IMR bits until the work is done. Other interrupts can be processed without
1390  * the work queue. */
1391 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1392 {
1393         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1394                 spin_lock(&dev_priv->irq_lock);
1395                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1396                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1397                 spin_unlock(&dev_priv->irq_lock);
1398
1399                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1400         }
1401
1402         if (HAS_VEBOX(dev_priv->dev)) {
1403                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1404                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1405
1406                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1407                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1408                         i915_handle_error(dev_priv->dev, false);
1409                 }
1410         }
1411 }
1412
1413 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1414 {
1415         struct drm_device *dev = (struct drm_device *) arg;
1416         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1417         u32 iir, gt_iir, pm_iir;
1418         irqreturn_t ret = IRQ_NONE;
1419         unsigned long irqflags;
1420         int pipe;
1421         u32 pipe_stats[I915_MAX_PIPES];
1422
1423         atomic_inc(&dev_priv->irq_received);
1424
1425         while (true) {
1426                 iir = I915_READ(VLV_IIR);
1427                 gt_iir = I915_READ(GTIIR);
1428                 pm_iir = I915_READ(GEN6_PMIIR);
1429
1430                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1431                         goto out;
1432
1433                 ret = IRQ_HANDLED;
1434
1435                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1436
1437                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1438                 for_each_pipe(pipe) {
1439                         int reg = PIPESTAT(pipe);
1440                         pipe_stats[pipe] = I915_READ(reg);
1441
1442                         /*
1443                          * Clear the PIPE*STAT regs before the IIR
1444                          */
1445                         if (pipe_stats[pipe] & 0x8000ffff) {
1446                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1447                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1448                                                          pipe_name(pipe));
1449                                 I915_WRITE(reg, pipe_stats[pipe]);
1450                         }
1451                 }
1452                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1453
1454                 for_each_pipe(pipe) {
1455                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1456                                 drm_handle_vblank(dev, pipe);
1457
1458                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1459                                 intel_prepare_page_flip(dev, pipe);
1460                                 intel_finish_page_flip(dev, pipe);
1461                         }
1462
1463                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1464                                 i9xx_pipe_crc_irq_handler(dev, pipe);
1465                 }
1466
1467                 /* Consume port.  Then clear IIR or we'll miss events */
1468                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1469                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1470                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1471
1472                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1473                                          hotplug_status);
1474
1475                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1476
1477                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1478                                 dp_aux_irq_handler(dev);
1479
1480                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1481                         I915_READ(PORT_HOTPLUG_STAT);
1482                 }
1483
1484                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1485                         gmbus_irq_handler(dev);
1486
1487                 if (pm_iir)
1488                         gen6_rps_irq_handler(dev_priv, pm_iir);
1489
1490                 I915_WRITE(GTIIR, gt_iir);
1491                 I915_WRITE(GEN6_PMIIR, pm_iir);
1492                 I915_WRITE(VLV_IIR, iir);
1493         }
1494
1495 out:
1496         return ret;
1497 }
1498
1499 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1500 {
1501         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1502         int pipe;
1503         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1504
1505         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1506
1507         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1508                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1509                                SDE_AUDIO_POWER_SHIFT);
1510                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1511                                  port_name(port));
1512         }
1513
1514         if (pch_iir & SDE_AUX_MASK)
1515                 dp_aux_irq_handler(dev);
1516
1517         if (pch_iir & SDE_GMBUS)
1518                 gmbus_irq_handler(dev);
1519
1520         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1521                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1522
1523         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1524                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1525
1526         if (pch_iir & SDE_POISON)
1527                 DRM_ERROR("PCH poison interrupt\n");
1528
1529         if (pch_iir & SDE_FDI_MASK)
1530                 for_each_pipe(pipe)
1531                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1532                                          pipe_name(pipe),
1533                                          I915_READ(FDI_RX_IIR(pipe)));
1534
1535         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1536                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1537
1538         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1539                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1540
1541         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1542                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1543                                                           false))
1544                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1545
1546         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1547                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1548                                                           false))
1549                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1550 }
1551
1552 static void ivb_err_int_handler(struct drm_device *dev)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         u32 err_int = I915_READ(GEN7_ERR_INT);
1556         enum pipe pipe;
1557
1558         if (err_int & ERR_INT_POISON)
1559                 DRM_ERROR("Poison interrupt\n");
1560
1561         for_each_pipe(pipe) {
1562                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1563                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1564                                                                   false))
1565                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1566                                                  pipe_name(pipe));
1567                 }
1568
1569                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1570                         if (IS_IVYBRIDGE(dev))
1571                                 ivb_pipe_crc_irq_handler(dev, pipe);
1572                         else
1573                                 hsw_pipe_crc_irq_handler(dev, pipe);
1574                 }
1575         }
1576
1577         I915_WRITE(GEN7_ERR_INT, err_int);
1578 }
1579
1580 static void cpt_serr_int_handler(struct drm_device *dev)
1581 {
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         u32 serr_int = I915_READ(SERR_INT);
1584
1585         if (serr_int & SERR_INT_POISON)
1586                 DRM_ERROR("PCH poison interrupt\n");
1587
1588         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1589                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1590                                                           false))
1591                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1592
1593         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1594                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1595                                                           false))
1596                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1597
1598         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1599                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1600                                                           false))
1601                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1602
1603         I915_WRITE(SERR_INT, serr_int);
1604 }
1605
1606 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1607 {
1608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1609         int pipe;
1610         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1611
1612         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1613
1614         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1615                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1616                                SDE_AUDIO_POWER_SHIFT_CPT);
1617                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1618                                  port_name(port));
1619         }
1620
1621         if (pch_iir & SDE_AUX_MASK_CPT)
1622                 dp_aux_irq_handler(dev);
1623
1624         if (pch_iir & SDE_GMBUS_CPT)
1625                 gmbus_irq_handler(dev);
1626
1627         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1628                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1629
1630         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1631                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1632
1633         if (pch_iir & SDE_FDI_MASK_CPT)
1634                 for_each_pipe(pipe)
1635                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1636                                          pipe_name(pipe),
1637                                          I915_READ(FDI_RX_IIR(pipe)));
1638
1639         if (pch_iir & SDE_ERROR_CPT)
1640                 cpt_serr_int_handler(dev);
1641 }
1642
1643 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         enum pipe pipe;
1647
1648         if (de_iir & DE_AUX_CHANNEL_A)
1649                 dp_aux_irq_handler(dev);
1650
1651         if (de_iir & DE_GSE)
1652                 intel_opregion_asle_intr(dev);
1653
1654         if (de_iir & DE_POISON)
1655                 DRM_ERROR("Poison interrupt\n");
1656
1657         for_each_pipe(pipe) {
1658                 if (de_iir & DE_PIPE_VBLANK(pipe))
1659                         drm_handle_vblank(dev, pipe);
1660
1661                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1662                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1663                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1664                                                  pipe_name(pipe));
1665
1666                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1667                         i9xx_pipe_crc_irq_handler(dev, pipe);
1668
1669                 /* plane/pipes map 1:1 on ilk+ */
1670                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1671                         intel_prepare_page_flip(dev, pipe);
1672                         intel_finish_page_flip_plane(dev, pipe);
1673                 }
1674         }
1675
1676         /* check event from PCH */
1677         if (de_iir & DE_PCH_EVENT) {
1678                 u32 pch_iir = I915_READ(SDEIIR);
1679
1680                 if (HAS_PCH_CPT(dev))
1681                         cpt_irq_handler(dev, pch_iir);
1682                 else
1683                         ibx_irq_handler(dev, pch_iir);
1684
1685                 /* should clear PCH hotplug event before clear CPU irq */
1686                 I915_WRITE(SDEIIR, pch_iir);
1687         }
1688
1689         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1690                 ironlake_rps_change_irq_handler(dev);
1691 }
1692
1693 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1694 {
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         enum pipe i;
1697
1698         if (de_iir & DE_ERR_INT_IVB)
1699                 ivb_err_int_handler(dev);
1700
1701         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1702                 dp_aux_irq_handler(dev);
1703
1704         if (de_iir & DE_GSE_IVB)
1705                 intel_opregion_asle_intr(dev);
1706
1707         for_each_pipe(i) {
1708                 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1709                         drm_handle_vblank(dev, i);
1710
1711                 /* plane/pipes map 1:1 on ilk+ */
1712                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1713                         intel_prepare_page_flip(dev, i);
1714                         intel_finish_page_flip_plane(dev, i);
1715                 }
1716         }
1717
1718         /* check event from PCH */
1719         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1720                 u32 pch_iir = I915_READ(SDEIIR);
1721
1722                 cpt_irq_handler(dev, pch_iir);
1723
1724                 /* clear PCH hotplug event before clear CPU irq */
1725                 I915_WRITE(SDEIIR, pch_iir);
1726         }
1727 }
1728
1729 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1730 {
1731         struct drm_device *dev = (struct drm_device *) arg;
1732         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1733         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1734         irqreturn_t ret = IRQ_NONE;
1735
1736         atomic_inc(&dev_priv->irq_received);
1737
1738         /* We get interrupts on unclaimed registers, so check for this before we
1739          * do any I915_{READ,WRITE}. */
1740         intel_uncore_check_errors(dev);
1741
1742         /* disable master interrupt before clearing iir  */
1743         de_ier = I915_READ(DEIER);
1744         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1745         POSTING_READ(DEIER);
1746
1747         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1748          * interrupts will will be stored on its back queue, and then we'll be
1749          * able to process them after we restore SDEIER (as soon as we restore
1750          * it, we'll get an interrupt if SDEIIR still has something to process
1751          * due to its back queue). */
1752         if (!HAS_PCH_NOP(dev)) {
1753                 sde_ier = I915_READ(SDEIER);
1754                 I915_WRITE(SDEIER, 0);
1755                 POSTING_READ(SDEIER);
1756         }
1757
1758         gt_iir = I915_READ(GTIIR);
1759         if (gt_iir) {
1760                 if (INTEL_INFO(dev)->gen >= 6)
1761                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1762                 else
1763                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1764                 I915_WRITE(GTIIR, gt_iir);
1765                 ret = IRQ_HANDLED;
1766         }
1767
1768         de_iir = I915_READ(DEIIR);
1769         if (de_iir) {
1770                 if (INTEL_INFO(dev)->gen >= 7)
1771                         ivb_display_irq_handler(dev, de_iir);
1772                 else
1773                         ilk_display_irq_handler(dev, de_iir);
1774                 I915_WRITE(DEIIR, de_iir);
1775                 ret = IRQ_HANDLED;
1776         }
1777
1778         if (INTEL_INFO(dev)->gen >= 6) {
1779                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1780                 if (pm_iir) {
1781                         gen6_rps_irq_handler(dev_priv, pm_iir);
1782                         I915_WRITE(GEN6_PMIIR, pm_iir);
1783                         ret = IRQ_HANDLED;
1784                 }
1785         }
1786
1787         I915_WRITE(DEIER, de_ier);
1788         POSTING_READ(DEIER);
1789         if (!HAS_PCH_NOP(dev)) {
1790                 I915_WRITE(SDEIER, sde_ier);
1791                 POSTING_READ(SDEIER);
1792         }
1793
1794         return ret;
1795 }
1796
1797 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1798 {
1799         struct drm_device *dev = arg;
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         u32 master_ctl;
1802         irqreturn_t ret = IRQ_NONE;
1803         uint32_t tmp = 0;
1804         enum pipe pipe;
1805
1806         atomic_inc(&dev_priv->irq_received);
1807
1808         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1809         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1810         if (!master_ctl)
1811                 return IRQ_NONE;
1812
1813         I915_WRITE(GEN8_MASTER_IRQ, 0);
1814         POSTING_READ(GEN8_MASTER_IRQ);
1815
1816         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1817
1818         if (master_ctl & GEN8_DE_MISC_IRQ) {
1819                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1820                 if (tmp & GEN8_DE_MISC_GSE)
1821                         intel_opregion_asle_intr(dev);
1822                 else if (tmp)
1823                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1824                 else
1825                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1826
1827                 if (tmp) {
1828                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1829                         ret = IRQ_HANDLED;
1830                 }
1831         }
1832
1833         if (master_ctl & GEN8_DE_PORT_IRQ) {
1834                 tmp = I915_READ(GEN8_DE_PORT_IIR);
1835                 if (tmp & GEN8_AUX_CHANNEL_A)
1836                         dp_aux_irq_handler(dev);
1837                 else if (tmp)
1838                         DRM_ERROR("Unexpected DE Port interrupt\n");
1839                 else
1840                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1841
1842                 if (tmp) {
1843                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1844                         ret = IRQ_HANDLED;
1845                 }
1846         }
1847
1848         for_each_pipe(pipe) {
1849                 uint32_t pipe_iir;
1850
1851                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1852                         continue;
1853
1854                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1855                 if (pipe_iir & GEN8_PIPE_VBLANK)
1856                         drm_handle_vblank(dev, pipe);
1857
1858                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1859                         intel_prepare_page_flip(dev, pipe);
1860                         intel_finish_page_flip_plane(dev, pipe);
1861                 }
1862
1863                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1864                         hsw_pipe_crc_irq_handler(dev, pipe);
1865
1866                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1867                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1868                                                                   false))
1869                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1870                                                  pipe_name(pipe));
1871                 }
1872
1873                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1874                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1875                                   pipe_name(pipe),
1876                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1877                 }
1878
1879                 if (pipe_iir) {
1880                         ret = IRQ_HANDLED;
1881                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1882                 } else
1883                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1884         }
1885
1886         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1887                 /*
1888                  * FIXME(BDW): Assume for now that the new interrupt handling
1889                  * scheme also closed the SDE interrupt handling race we've seen
1890                  * on older pch-split platforms. But this needs testing.
1891                  */
1892                 u32 pch_iir = I915_READ(SDEIIR);
1893
1894                 cpt_irq_handler(dev, pch_iir);
1895
1896                 if (pch_iir) {
1897                         I915_WRITE(SDEIIR, pch_iir);
1898                         ret = IRQ_HANDLED;
1899                 }
1900         }
1901
1902         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1903         POSTING_READ(GEN8_MASTER_IRQ);
1904
1905         return ret;
1906 }
1907
1908 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1909                                bool reset_completed)
1910 {
1911         struct intel_ring_buffer *ring;
1912         int i;
1913
1914         /*
1915          * Notify all waiters for GPU completion events that reset state has
1916          * been changed, and that they need to restart their wait after
1917          * checking for potential errors (and bail out to drop locks if there is
1918          * a gpu reset pending so that i915_error_work_func can acquire them).
1919          */
1920
1921         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1922         for_each_ring(ring, dev_priv, i)
1923                 wake_up_all(&ring->irq_queue);
1924
1925         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1926         wake_up_all(&dev_priv->pending_flip_queue);
1927
1928         /*
1929          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1930          * reset state is cleared.
1931          */
1932         if (reset_completed)
1933                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1934 }
1935
1936 /**
1937  * i915_error_work_func - do process context error handling work
1938  * @work: work struct
1939  *
1940  * Fire an error uevent so userspace can see that a hang or error
1941  * was detected.
1942  */
1943 static void i915_error_work_func(struct work_struct *work)
1944 {
1945         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1946                                                     work);
1947         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1948                                                     gpu_error);
1949         struct drm_device *dev = dev_priv->dev;
1950         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1951         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1952         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1953         int ret;
1954
1955         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1956
1957         /*
1958          * Note that there's only one work item which does gpu resets, so we
1959          * need not worry about concurrent gpu resets potentially incrementing
1960          * error->reset_counter twice. We only need to take care of another
1961          * racing irq/hangcheck declaring the gpu dead for a second time. A
1962          * quick check for that is good enough: schedule_work ensures the
1963          * correct ordering between hang detection and this work item, and since
1964          * the reset in-progress bit is only ever set by code outside of this
1965          * work we don't need to worry about any other races.
1966          */
1967         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1968                 DRM_DEBUG_DRIVER("resetting chip\n");
1969                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1970                                    reset_event);
1971
1972                 /*
1973                  * All state reset _must_ be completed before we update the
1974                  * reset counter, for otherwise waiters might miss the reset
1975                  * pending state and not properly drop locks, resulting in
1976                  * deadlocks with the reset work.
1977                  */
1978                 ret = i915_reset(dev);
1979
1980                 intel_display_handle_reset(dev);
1981
1982                 if (ret == 0) {
1983                         /*
1984                          * After all the gem state is reset, increment the reset
1985                          * counter and wake up everyone waiting for the reset to
1986                          * complete.
1987                          *
1988                          * Since unlock operations are a one-sided barrier only,
1989                          * we need to insert a barrier here to order any seqno
1990                          * updates before
1991                          * the counter increment.
1992                          */
1993                         smp_mb__before_atomic_inc();
1994                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1995
1996                         kobject_uevent_env(&dev->primary->kdev->kobj,
1997                                            KOBJ_CHANGE, reset_done_event);
1998                 } else {
1999                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2000                 }
2001
2002                 /*
2003                  * Note: The wake_up also serves as a memory barrier so that
2004                  * waiters see the update value of the reset counter atomic_t.
2005                  */
2006                 i915_error_wake_up(dev_priv, true);
2007         }
2008 }
2009
2010 static void i915_report_and_clear_eir(struct drm_device *dev)
2011 {
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         uint32_t instdone[I915_NUM_INSTDONE_REG];
2014         u32 eir = I915_READ(EIR);
2015         int pipe, i;
2016
2017         if (!eir)
2018                 return;
2019
2020         pr_err("render error detected, EIR: 0x%08x\n", eir);
2021
2022         i915_get_extra_instdone(dev, instdone);
2023
2024         if (IS_G4X(dev)) {
2025                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2026                         u32 ipeir = I915_READ(IPEIR_I965);
2027
2028                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2029                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2030                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2031                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2032                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2033                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2034                         I915_WRITE(IPEIR_I965, ipeir);
2035                         POSTING_READ(IPEIR_I965);
2036                 }
2037                 if (eir & GM45_ERROR_PAGE_TABLE) {
2038                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2039                         pr_err("page table error\n");
2040                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2041                         I915_WRITE(PGTBL_ER, pgtbl_err);
2042                         POSTING_READ(PGTBL_ER);
2043                 }
2044         }
2045
2046         if (!IS_GEN2(dev)) {
2047                 if (eir & I915_ERROR_PAGE_TABLE) {
2048                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2049                         pr_err("page table error\n");
2050                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2051                         I915_WRITE(PGTBL_ER, pgtbl_err);
2052                         POSTING_READ(PGTBL_ER);
2053                 }
2054         }
2055
2056         if (eir & I915_ERROR_MEMORY_REFRESH) {
2057                 pr_err("memory refresh error:\n");
2058                 for_each_pipe(pipe)
2059                         pr_err("pipe %c stat: 0x%08x\n",
2060                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2061                 /* pipestat has already been acked */
2062         }
2063         if (eir & I915_ERROR_INSTRUCTION) {
2064                 pr_err("instruction error\n");
2065                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2066                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2067                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2068                 if (INTEL_INFO(dev)->gen < 4) {
2069                         u32 ipeir = I915_READ(IPEIR);
2070
2071                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2072                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2073                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2074                         I915_WRITE(IPEIR, ipeir);
2075                         POSTING_READ(IPEIR);
2076                 } else {
2077                         u32 ipeir = I915_READ(IPEIR_I965);
2078
2079                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2080                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2081                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2082                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2083                         I915_WRITE(IPEIR_I965, ipeir);
2084                         POSTING_READ(IPEIR_I965);
2085                 }
2086         }
2087
2088         I915_WRITE(EIR, eir);
2089         POSTING_READ(EIR);
2090         eir = I915_READ(EIR);
2091         if (eir) {
2092                 /*
2093                  * some errors might have become stuck,
2094                  * mask them.
2095                  */
2096                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2097                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2098                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2099         }
2100 }
2101
2102 /**
2103  * i915_handle_error - handle an error interrupt
2104  * @dev: drm device
2105  *
2106  * Do some basic checking of regsiter state at error interrupt time and
2107  * dump it to the syslog.  Also call i915_capture_error_state() to make
2108  * sure we get a record and make it available in debugfs.  Fire a uevent
2109  * so userspace knows something bad happened (should trigger collection
2110  * of a ring dump etc.).
2111  */
2112 void i915_handle_error(struct drm_device *dev, bool wedged)
2113 {
2114         struct drm_i915_private *dev_priv = dev->dev_private;
2115
2116         i915_capture_error_state(dev);
2117         i915_report_and_clear_eir(dev);
2118
2119         if (wedged) {
2120                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2121                                 &dev_priv->gpu_error.reset_counter);
2122
2123                 /*
2124                  * Wakeup waiting processes so that the reset work function
2125                  * i915_error_work_func doesn't deadlock trying to grab various
2126                  * locks. By bumping the reset counter first, the woken
2127                  * processes will see a reset in progress and back off,
2128                  * releasing their locks and then wait for the reset completion.
2129                  * We must do this for _all_ gpu waiters that might hold locks
2130                  * that the reset work needs to acquire.
2131                  *
2132                  * Note: The wake_up serves as the required memory barrier to
2133                  * ensure that the waiters see the updated value of the reset
2134                  * counter atomic_t.
2135                  */
2136                 i915_error_wake_up(dev_priv, false);
2137         }
2138
2139         /*
2140          * Our reset work can grab modeset locks (since it needs to reset the
2141          * state of outstanding pagelips). Hence it must not be run on our own
2142          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2143          * code will deadlock.
2144          */
2145         schedule_work(&dev_priv->gpu_error.work);
2146 }
2147
2148 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2149 {
2150         drm_i915_private_t *dev_priv = dev->dev_private;
2151         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2153         struct drm_i915_gem_object *obj;
2154         struct intel_unpin_work *work;
2155         unsigned long flags;
2156         bool stall_detected;
2157
2158         /* Ignore early vblank irqs */
2159         if (intel_crtc == NULL)
2160                 return;
2161
2162         spin_lock_irqsave(&dev->event_lock, flags);
2163         work = intel_crtc->unpin_work;
2164
2165         if (work == NULL ||
2166             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2167             !work->enable_stall_check) {
2168                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2169                 spin_unlock_irqrestore(&dev->event_lock, flags);
2170                 return;
2171         }
2172
2173         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2174         obj = work->pending_flip_obj;
2175         if (INTEL_INFO(dev)->gen >= 4) {
2176                 int dspsurf = DSPSURF(intel_crtc->plane);
2177                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2178                                         i915_gem_obj_ggtt_offset(obj);
2179         } else {
2180                 int dspaddr = DSPADDR(intel_crtc->plane);
2181                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2182                                                         crtc->y * crtc->fb->pitches[0] +
2183                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2184         }
2185
2186         spin_unlock_irqrestore(&dev->event_lock, flags);
2187
2188         if (stall_detected) {
2189                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2190                 intel_prepare_page_flip(dev, intel_crtc->plane);
2191         }
2192 }
2193
2194 /* Called from drm generic code, passed 'crtc' which
2195  * we use as a pipe index
2196  */
2197 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2198 {
2199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2200         unsigned long irqflags;
2201
2202         if (!i915_pipe_enabled(dev, pipe))
2203                 return -EINVAL;
2204
2205         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2206         if (INTEL_INFO(dev)->gen >= 4)
2207                 i915_enable_pipestat(dev_priv, pipe,
2208                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2209         else
2210                 i915_enable_pipestat(dev_priv, pipe,
2211                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2212
2213         /* maintain vblank delivery even in deep C-states */
2214         if (dev_priv->info->gen == 3)
2215                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2216         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2217
2218         return 0;
2219 }
2220
2221 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2222 {
2223         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2224         unsigned long irqflags;
2225         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2226                                                      DE_PIPE_VBLANK(pipe);
2227
2228         if (!i915_pipe_enabled(dev, pipe))
2229                 return -EINVAL;
2230
2231         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2232         ironlake_enable_display_irq(dev_priv, bit);
2233         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2234
2235         return 0;
2236 }
2237
2238 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2239 {
2240         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2241         unsigned long irqflags;
2242         u32 imr;
2243
2244         if (!i915_pipe_enabled(dev, pipe))
2245                 return -EINVAL;
2246
2247         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2248         imr = I915_READ(VLV_IMR);
2249         if (pipe == PIPE_A)
2250                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2251         else
2252                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2253         I915_WRITE(VLV_IMR, imr);
2254         i915_enable_pipestat(dev_priv, pipe,
2255                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2256         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2257
2258         return 0;
2259 }
2260
2261 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2262 {
2263         struct drm_i915_private *dev_priv = dev->dev_private;
2264         unsigned long irqflags;
2265
2266         if (!i915_pipe_enabled(dev, pipe))
2267                 return -EINVAL;
2268
2269         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2270         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2271         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2272         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2273         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2274         return 0;
2275 }
2276
2277 /* Called from drm generic code, passed 'crtc' which
2278  * we use as a pipe index
2279  */
2280 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2281 {
2282         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2283         unsigned long irqflags;
2284
2285         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2286         if (dev_priv->info->gen == 3)
2287                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2288
2289         i915_disable_pipestat(dev_priv, pipe,
2290                               PIPE_VBLANK_INTERRUPT_ENABLE |
2291                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2292         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2293 }
2294
2295 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2296 {
2297         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2298         unsigned long irqflags;
2299         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2300                                                      DE_PIPE_VBLANK(pipe);
2301
2302         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2303         ironlake_disable_display_irq(dev_priv, bit);
2304         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2305 }
2306
2307 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2308 {
2309         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2310         unsigned long irqflags;
2311         u32 imr;
2312
2313         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2314         i915_disable_pipestat(dev_priv, pipe,
2315                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2316         imr = I915_READ(VLV_IMR);
2317         if (pipe == PIPE_A)
2318                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2319         else
2320                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2321         I915_WRITE(VLV_IMR, imr);
2322         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2323 }
2324
2325 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2326 {
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         unsigned long irqflags;
2329
2330         if (!i915_pipe_enabled(dev, pipe))
2331                 return;
2332
2333         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2334         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2335         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2336         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2337         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2338 }
2339
2340 static u32
2341 ring_last_seqno(struct intel_ring_buffer *ring)
2342 {
2343         return list_entry(ring->request_list.prev,
2344                           struct drm_i915_gem_request, list)->seqno;
2345 }
2346
2347 static bool
2348 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2349 {
2350         return (list_empty(&ring->request_list) ||
2351                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2352 }
2353
2354 static struct intel_ring_buffer *
2355 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2356 {
2357         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2358         u32 cmd, ipehr, acthd, acthd_min;
2359
2360         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2361         if ((ipehr & ~(0x3 << 16)) !=
2362             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2363                 return NULL;
2364
2365         /* ACTHD is likely pointing to the dword after the actual command,
2366          * so scan backwards until we find the MBOX.
2367          */
2368         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2369         acthd_min = max((int)acthd - 3 * 4, 0);
2370         do {
2371                 cmd = ioread32(ring->virtual_start + acthd);
2372                 if (cmd == ipehr)
2373                         break;
2374
2375                 acthd -= 4;
2376                 if (acthd < acthd_min)
2377                         return NULL;
2378         } while (1);
2379
2380         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2381         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2382 }
2383
2384 static int semaphore_passed(struct intel_ring_buffer *ring)
2385 {
2386         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2387         struct intel_ring_buffer *signaller;
2388         u32 seqno, ctl;
2389
2390         ring->hangcheck.deadlock = true;
2391
2392         signaller = semaphore_waits_for(ring, &seqno);
2393         if (signaller == NULL || signaller->hangcheck.deadlock)
2394                 return -1;
2395
2396         /* cursory check for an unkickable deadlock */
2397         ctl = I915_READ_CTL(signaller);
2398         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2399                 return -1;
2400
2401         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2402 }
2403
2404 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2405 {
2406         struct intel_ring_buffer *ring;
2407         int i;
2408
2409         for_each_ring(ring, dev_priv, i)
2410                 ring->hangcheck.deadlock = false;
2411 }
2412
2413 static enum intel_ring_hangcheck_action
2414 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2415 {
2416         struct drm_device *dev = ring->dev;
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         u32 tmp;
2419
2420         if (ring->hangcheck.acthd != acthd)
2421                 return HANGCHECK_ACTIVE;
2422
2423         if (IS_GEN2(dev))
2424                 return HANGCHECK_HUNG;
2425
2426         /* Is the chip hanging on a WAIT_FOR_EVENT?
2427          * If so we can simply poke the RB_WAIT bit
2428          * and break the hang. This should work on
2429          * all but the second generation chipsets.
2430          */
2431         tmp = I915_READ_CTL(ring);
2432         if (tmp & RING_WAIT) {
2433                 DRM_ERROR("Kicking stuck wait on %s\n",
2434                           ring->name);
2435                 i915_handle_error(dev, false);
2436                 I915_WRITE_CTL(ring, tmp);
2437                 return HANGCHECK_KICK;
2438         }
2439
2440         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2441                 switch (semaphore_passed(ring)) {
2442                 default:
2443                         return HANGCHECK_HUNG;
2444                 case 1:
2445                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2446                                   ring->name);
2447                         i915_handle_error(dev, false);
2448                         I915_WRITE_CTL(ring, tmp);
2449                         return HANGCHECK_KICK;
2450                 case 0:
2451                         return HANGCHECK_WAIT;
2452                 }
2453         }
2454
2455         return HANGCHECK_HUNG;
2456 }
2457
2458 /**
2459  * This is called when the chip hasn't reported back with completed
2460  * batchbuffers in a long time. We keep track per ring seqno progress and
2461  * if there are no progress, hangcheck score for that ring is increased.
2462  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2463  * we kick the ring. If we see no progress on three subsequent calls
2464  * we assume chip is wedged and try to fix it by resetting the chip.
2465  */
2466 static void i915_hangcheck_elapsed(unsigned long data)
2467 {
2468         struct drm_device *dev = (struct drm_device *)data;
2469         drm_i915_private_t *dev_priv = dev->dev_private;
2470         struct intel_ring_buffer *ring;
2471         int i;
2472         int busy_count = 0, rings_hung = 0;
2473         bool stuck[I915_NUM_RINGS] = { 0 };
2474 #define BUSY 1
2475 #define KICK 5
2476 #define HUNG 20
2477 #define FIRE 30
2478
2479         if (!i915_enable_hangcheck)
2480                 return;
2481
2482         for_each_ring(ring, dev_priv, i) {
2483                 u32 seqno, acthd;
2484                 bool busy = true;
2485
2486                 semaphore_clear_deadlocks(dev_priv);
2487
2488                 seqno = ring->get_seqno(ring, false);
2489                 acthd = intel_ring_get_active_head(ring);
2490
2491                 if (ring->hangcheck.seqno == seqno) {
2492                         if (ring_idle(ring, seqno)) {
2493                                 ring->hangcheck.action = HANGCHECK_IDLE;
2494
2495                                 if (waitqueue_active(&ring->irq_queue)) {
2496                                         /* Issue a wake-up to catch stuck h/w. */
2497                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2498                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2499                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2500                                                                   ring->name);
2501                                                 else
2502                                                         DRM_INFO("Fake missed irq on %s\n",
2503                                                                  ring->name);
2504                                                 wake_up_all(&ring->irq_queue);
2505                                         }
2506                                         /* Safeguard against driver failure */
2507                                         ring->hangcheck.score += BUSY;
2508                                 } else
2509                                         busy = false;
2510                         } else {
2511                                 /* We always increment the hangcheck score
2512                                  * if the ring is busy and still processing
2513                                  * the same request, so that no single request
2514                                  * can run indefinitely (such as a chain of
2515                                  * batches). The only time we do not increment
2516                                  * the hangcheck score on this ring, if this
2517                                  * ring is in a legitimate wait for another
2518                                  * ring. In that case the waiting ring is a
2519                                  * victim and we want to be sure we catch the
2520                                  * right culprit. Then every time we do kick
2521                                  * the ring, add a small increment to the
2522                                  * score so that we can catch a batch that is
2523                                  * being repeatedly kicked and so responsible
2524                                  * for stalling the machine.
2525                                  */
2526                                 ring->hangcheck.action = ring_stuck(ring,
2527                                                                     acthd);
2528
2529                                 switch (ring->hangcheck.action) {
2530                                 case HANGCHECK_IDLE:
2531                                 case HANGCHECK_WAIT:
2532                                         break;
2533                                 case HANGCHECK_ACTIVE:
2534                                         ring->hangcheck.score += BUSY;
2535                                         break;
2536                                 case HANGCHECK_KICK:
2537                                         ring->hangcheck.score += KICK;
2538                                         break;
2539                                 case HANGCHECK_HUNG:
2540                                         ring->hangcheck.score += HUNG;
2541                                         stuck[i] = true;
2542                                         break;
2543                                 }
2544                         }
2545                 } else {
2546                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2547
2548                         /* Gradually reduce the count so that we catch DoS
2549                          * attempts across multiple batches.
2550                          */
2551                         if (ring->hangcheck.score > 0)
2552                                 ring->hangcheck.score--;
2553                 }
2554
2555                 ring->hangcheck.seqno = seqno;
2556                 ring->hangcheck.acthd = acthd;
2557                 busy_count += busy;
2558         }
2559
2560         for_each_ring(ring, dev_priv, i) {
2561                 if (ring->hangcheck.score > FIRE) {
2562                         DRM_INFO("%s on %s\n",
2563                                  stuck[i] ? "stuck" : "no progress",
2564                                  ring->name);
2565                         rings_hung++;
2566                 }
2567         }
2568
2569         if (rings_hung)
2570                 return i915_handle_error(dev, true);
2571
2572         if (busy_count)
2573                 /* Reset timer case chip hangs without another request
2574                  * being added */
2575                 i915_queue_hangcheck(dev);
2576 }
2577
2578 void i915_queue_hangcheck(struct drm_device *dev)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         if (!i915_enable_hangcheck)
2582                 return;
2583
2584         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2585                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2586 }
2587
2588 static void ibx_irq_preinstall(struct drm_device *dev)
2589 {
2590         struct drm_i915_private *dev_priv = dev->dev_private;
2591
2592         if (HAS_PCH_NOP(dev))
2593                 return;
2594
2595         /* south display irq */
2596         I915_WRITE(SDEIMR, 0xffffffff);
2597         /*
2598          * SDEIER is also touched by the interrupt handler to work around missed
2599          * PCH interrupts. Hence we can't update it after the interrupt handler
2600          * is enabled - instead we unconditionally enable all PCH interrupt
2601          * sources here, but then only unmask them as needed with SDEIMR.
2602          */
2603         I915_WRITE(SDEIER, 0xffffffff);
2604         POSTING_READ(SDEIER);
2605 }
2606
2607 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2608 {
2609         struct drm_i915_private *dev_priv = dev->dev_private;
2610
2611         /* and GT */
2612         I915_WRITE(GTIMR, 0xffffffff);
2613         I915_WRITE(GTIER, 0x0);
2614         POSTING_READ(GTIER);
2615
2616         if (INTEL_INFO(dev)->gen >= 6) {
2617                 /* and PM */
2618                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2619                 I915_WRITE(GEN6_PMIER, 0x0);
2620                 POSTING_READ(GEN6_PMIER);
2621         }
2622 }
2623
2624 /* drm_dma.h hooks
2625 */
2626 static void ironlake_irq_preinstall(struct drm_device *dev)
2627 {
2628         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2629
2630         atomic_set(&dev_priv->irq_received, 0);
2631
2632         I915_WRITE(HWSTAM, 0xeffe);
2633
2634         I915_WRITE(DEIMR, 0xffffffff);
2635         I915_WRITE(DEIER, 0x0);
2636         POSTING_READ(DEIER);
2637
2638         gen5_gt_irq_preinstall(dev);
2639
2640         ibx_irq_preinstall(dev);
2641 }
2642
2643 static void valleyview_irq_preinstall(struct drm_device *dev)
2644 {
2645         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2646         int pipe;
2647
2648         atomic_set(&dev_priv->irq_received, 0);
2649
2650         /* VLV magic */
2651         I915_WRITE(VLV_IMR, 0);
2652         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2653         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2654         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2655
2656         /* and GT */
2657         I915_WRITE(GTIIR, I915_READ(GTIIR));
2658         I915_WRITE(GTIIR, I915_READ(GTIIR));
2659
2660         gen5_gt_irq_preinstall(dev);
2661
2662         I915_WRITE(DPINVGTT, 0xff);
2663
2664         I915_WRITE(PORT_HOTPLUG_EN, 0);
2665         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2666         for_each_pipe(pipe)
2667                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2668         I915_WRITE(VLV_IIR, 0xffffffff);
2669         I915_WRITE(VLV_IMR, 0xffffffff);
2670         I915_WRITE(VLV_IER, 0x0);
2671         POSTING_READ(VLV_IER);
2672 }
2673
2674 static void gen8_irq_preinstall(struct drm_device *dev)
2675 {
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         int pipe;
2678
2679         atomic_set(&dev_priv->irq_received, 0);
2680
2681         I915_WRITE(GEN8_MASTER_IRQ, 0);
2682         POSTING_READ(GEN8_MASTER_IRQ);
2683
2684         /* IIR can theoretically queue up two events. Be paranoid */
2685 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2686                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2687                 POSTING_READ(GEN8_##type##_IMR(which)); \
2688                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2689                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2690                 POSTING_READ(GEN8_##type##_IIR(which)); \
2691                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2692         } while (0)
2693
2694 #define GEN8_IRQ_INIT(type) do { \
2695                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2696                 POSTING_READ(GEN8_##type##_IMR); \
2697                 I915_WRITE(GEN8_##type##_IER, 0); \
2698                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2699                 POSTING_READ(GEN8_##type##_IIR); \
2700                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2701         } while (0)
2702
2703         GEN8_IRQ_INIT_NDX(GT, 0);
2704         GEN8_IRQ_INIT_NDX(GT, 1);
2705         GEN8_IRQ_INIT_NDX(GT, 2);
2706         GEN8_IRQ_INIT_NDX(GT, 3);
2707
2708         for_each_pipe(pipe) {
2709                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2710         }
2711
2712         GEN8_IRQ_INIT(DE_PORT);
2713         GEN8_IRQ_INIT(DE_MISC);
2714         GEN8_IRQ_INIT(PCU);
2715 #undef GEN8_IRQ_INIT
2716 #undef GEN8_IRQ_INIT_NDX
2717
2718         POSTING_READ(GEN8_PCU_IIR);
2719
2720         ibx_irq_preinstall(dev);
2721 }
2722
2723 static void ibx_hpd_irq_setup(struct drm_device *dev)
2724 {
2725         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2726         struct drm_mode_config *mode_config = &dev->mode_config;
2727         struct intel_encoder *intel_encoder;
2728         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2729
2730         if (HAS_PCH_IBX(dev)) {
2731                 hotplug_irqs = SDE_HOTPLUG_MASK;
2732                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2733                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2734                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2735         } else {
2736                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2737                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2738                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2739                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2740         }
2741
2742         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2743
2744         /*
2745          * Enable digital hotplug on the PCH, and configure the DP short pulse
2746          * duration to 2ms (which is the minimum in the Display Port spec)
2747          *
2748          * This register is the same on all known PCH chips.
2749          */
2750         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2751         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2752         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2753         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2754         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2755         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2756 }
2757
2758 static void ibx_irq_postinstall(struct drm_device *dev)
2759 {
2760         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2761         u32 mask;
2762
2763         if (HAS_PCH_NOP(dev))
2764                 return;
2765
2766         if (HAS_PCH_IBX(dev)) {
2767                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2768                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2769         } else {
2770                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2771
2772                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2773         }
2774
2775         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2776         I915_WRITE(SDEIMR, ~mask);
2777 }
2778
2779 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2780 {
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         u32 pm_irqs, gt_irqs;
2783
2784         pm_irqs = gt_irqs = 0;
2785
2786         dev_priv->gt_irq_mask = ~0;
2787         if (HAS_L3_DPF(dev)) {
2788                 /* L3 parity interrupt is always unmasked. */
2789                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2790                 gt_irqs |= GT_PARITY_ERROR(dev);
2791         }
2792
2793         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2794         if (IS_GEN5(dev)) {
2795                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2796                            ILK_BSD_USER_INTERRUPT;
2797         } else {
2798                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2799         }
2800
2801         I915_WRITE(GTIIR, I915_READ(GTIIR));
2802         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2803         I915_WRITE(GTIER, gt_irqs);
2804         POSTING_READ(GTIER);
2805
2806         if (INTEL_INFO(dev)->gen >= 6) {
2807                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2808
2809                 if (HAS_VEBOX(dev))
2810                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2811
2812                 dev_priv->pm_irq_mask = 0xffffffff;
2813                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2814                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2815                 I915_WRITE(GEN6_PMIER, pm_irqs);
2816                 POSTING_READ(GEN6_PMIER);
2817         }
2818 }
2819
2820 static int ironlake_irq_postinstall(struct drm_device *dev)
2821 {
2822         unsigned long irqflags;
2823         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2824         u32 display_mask, extra_mask;
2825
2826         if (INTEL_INFO(dev)->gen >= 7) {
2827                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2828                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2829                                 DE_PLANEB_FLIP_DONE_IVB |
2830                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2831                                 DE_ERR_INT_IVB);
2832                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2833                               DE_PIPEA_VBLANK_IVB);
2834
2835                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2836         } else {
2837                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2838                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2839                                 DE_AUX_CHANNEL_A |
2840                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2841                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2842                                 DE_POISON);
2843                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2844         }
2845
2846         dev_priv->irq_mask = ~display_mask;
2847
2848         /* should always can generate irq */
2849         I915_WRITE(DEIIR, I915_READ(DEIIR));
2850         I915_WRITE(DEIMR, dev_priv->irq_mask);
2851         I915_WRITE(DEIER, display_mask | extra_mask);
2852         POSTING_READ(DEIER);
2853
2854         gen5_gt_irq_postinstall(dev);
2855
2856         ibx_irq_postinstall(dev);
2857
2858         if (IS_IRONLAKE_M(dev)) {
2859                 /* Enable PCU event interrupts
2860                  *
2861                  * spinlocking not required here for correctness since interrupt
2862                  * setup is guaranteed to run in single-threaded context. But we
2863                  * need it to make the assert_spin_locked happy. */
2864                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2865                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2866                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2867         }
2868
2869         return 0;
2870 }
2871
2872 static int valleyview_irq_postinstall(struct drm_device *dev)
2873 {
2874         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2875         u32 enable_mask;
2876         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2877                 PIPE_CRC_DONE_ENABLE;
2878         unsigned long irqflags;
2879
2880         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2881         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2882                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2883                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2884                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2885
2886         /*
2887          *Leave vblank interrupts masked initially.  enable/disable will
2888          * toggle them based on usage.
2889          */
2890         dev_priv->irq_mask = (~enable_mask) |
2891                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2892                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2893
2894         I915_WRITE(PORT_HOTPLUG_EN, 0);
2895         POSTING_READ(PORT_HOTPLUG_EN);
2896
2897         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2898         I915_WRITE(VLV_IER, enable_mask);
2899         I915_WRITE(VLV_IIR, 0xffffffff);
2900         I915_WRITE(PIPESTAT(0), 0xffff);
2901         I915_WRITE(PIPESTAT(1), 0xffff);
2902         POSTING_READ(VLV_IER);
2903
2904         /* Interrupt setup is already guaranteed to be single-threaded, this is
2905          * just to make the assert_spin_locked check happy. */
2906         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2907         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2908         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2909         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2910         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2911
2912         I915_WRITE(VLV_IIR, 0xffffffff);
2913         I915_WRITE(VLV_IIR, 0xffffffff);
2914
2915         gen5_gt_irq_postinstall(dev);
2916
2917         /* ack & enable invalid PTE error interrupts */
2918 #if 0 /* FIXME: add support to irq handler for checking these bits */
2919         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2920         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2921 #endif
2922
2923         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2924
2925         return 0;
2926 }
2927
2928 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2929 {
2930         int i;
2931
2932         /* These are interrupts we'll toggle with the ring mask register */
2933         uint32_t gt_interrupts[] = {
2934                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2935                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2936                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2937                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2938                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2939                 0,
2940                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2941                 };
2942
2943         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2944                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2945                 if (tmp)
2946                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2947                                   i, tmp);
2948                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2949                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2950         }
2951         POSTING_READ(GEN8_GT_IER(0));
2952 }
2953
2954 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2955 {
2956         struct drm_device *dev = dev_priv->dev;
2957         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2958                 GEN8_PIPE_CDCLK_CRC_DONE |
2959                 GEN8_PIPE_FIFO_UNDERRUN |
2960                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2961         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
2962         int pipe;
2963         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2964         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2965         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2966
2967         for_each_pipe(pipe) {
2968                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2969                 if (tmp)
2970                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2971                                   pipe, tmp);
2972                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2973                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2974         }
2975         POSTING_READ(GEN8_DE_PIPE_ISR(0));
2976
2977         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2978         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2979         POSTING_READ(GEN8_DE_PORT_IER);
2980 }
2981
2982 static int gen8_irq_postinstall(struct drm_device *dev)
2983 {
2984         struct drm_i915_private *dev_priv = dev->dev_private;
2985
2986         gen8_gt_irq_postinstall(dev_priv);
2987         gen8_de_irq_postinstall(dev_priv);
2988
2989         ibx_irq_postinstall(dev);
2990
2991         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2992         POSTING_READ(GEN8_MASTER_IRQ);
2993
2994         return 0;
2995 }
2996
2997 static void gen8_irq_uninstall(struct drm_device *dev)
2998 {
2999         struct drm_i915_private *dev_priv = dev->dev_private;
3000         int pipe;
3001
3002         if (!dev_priv)
3003                 return;
3004
3005         atomic_set(&dev_priv->irq_received, 0);
3006
3007         I915_WRITE(GEN8_MASTER_IRQ, 0);
3008
3009 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3010                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3011                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3012                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3013         } while (0)
3014
3015 #define GEN8_IRQ_FINI(type) do { \
3016                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3017                 I915_WRITE(GEN8_##type##_IER, 0); \
3018                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3019         } while (0)
3020
3021         GEN8_IRQ_FINI_NDX(GT, 0);
3022         GEN8_IRQ_FINI_NDX(GT, 1);
3023         GEN8_IRQ_FINI_NDX(GT, 2);
3024         GEN8_IRQ_FINI_NDX(GT, 3);
3025
3026         for_each_pipe(pipe) {
3027                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3028         }
3029
3030         GEN8_IRQ_FINI(DE_PORT);
3031         GEN8_IRQ_FINI(DE_MISC);
3032         GEN8_IRQ_FINI(PCU);
3033 #undef GEN8_IRQ_FINI
3034 #undef GEN8_IRQ_FINI_NDX
3035
3036         POSTING_READ(GEN8_PCU_IIR);
3037 }
3038
3039 static void valleyview_irq_uninstall(struct drm_device *dev)
3040 {
3041         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3042         int pipe;
3043
3044         if (!dev_priv)
3045                 return;
3046
3047         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3048
3049         for_each_pipe(pipe)
3050                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3051
3052         I915_WRITE(HWSTAM, 0xffffffff);
3053         I915_WRITE(PORT_HOTPLUG_EN, 0);
3054         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3055         for_each_pipe(pipe)
3056                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3057         I915_WRITE(VLV_IIR, 0xffffffff);
3058         I915_WRITE(VLV_IMR, 0xffffffff);
3059         I915_WRITE(VLV_IER, 0x0);
3060         POSTING_READ(VLV_IER);
3061 }
3062
3063 static void ironlake_irq_uninstall(struct drm_device *dev)
3064 {
3065         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3066
3067         if (!dev_priv)
3068                 return;
3069
3070         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3071
3072         I915_WRITE(HWSTAM, 0xffffffff);
3073
3074         I915_WRITE(DEIMR, 0xffffffff);
3075         I915_WRITE(DEIER, 0x0);
3076         I915_WRITE(DEIIR, I915_READ(DEIIR));
3077         if (IS_GEN7(dev))
3078                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3079
3080         I915_WRITE(GTIMR, 0xffffffff);
3081         I915_WRITE(GTIER, 0x0);
3082         I915_WRITE(GTIIR, I915_READ(GTIIR));
3083
3084         if (HAS_PCH_NOP(dev))
3085                 return;
3086
3087         I915_WRITE(SDEIMR, 0xffffffff);
3088         I915_WRITE(SDEIER, 0x0);
3089         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3090         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3091                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3092 }
3093
3094 static void i8xx_irq_preinstall(struct drm_device * dev)
3095 {
3096         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3097         int pipe;
3098
3099         atomic_set(&dev_priv->irq_received, 0);
3100
3101         for_each_pipe(pipe)
3102                 I915_WRITE(PIPESTAT(pipe), 0);
3103         I915_WRITE16(IMR, 0xffff);
3104         I915_WRITE16(IER, 0x0);
3105         POSTING_READ16(IER);
3106 }
3107
3108 static int i8xx_irq_postinstall(struct drm_device *dev)
3109 {
3110         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3111         unsigned long irqflags;
3112
3113         I915_WRITE16(EMR,
3114                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3115
3116         /* Unmask the interrupts that we always want on. */
3117         dev_priv->irq_mask =
3118                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3119                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3120                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3121                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3122                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3123         I915_WRITE16(IMR, dev_priv->irq_mask);
3124
3125         I915_WRITE16(IER,
3126                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3127                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3128                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3129                      I915_USER_INTERRUPT);
3130         POSTING_READ16(IER);
3131
3132         /* Interrupt setup is already guaranteed to be single-threaded, this is
3133          * just to make the assert_spin_locked check happy. */
3134         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3135         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3136         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3137         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3138
3139         return 0;
3140 }
3141
3142 /*
3143  * Returns true when a page flip has completed.
3144  */
3145 static bool i8xx_handle_vblank(struct drm_device *dev,
3146                                int plane, int pipe, u32 iir)
3147 {
3148         drm_i915_private_t *dev_priv = dev->dev_private;
3149         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3150
3151         if (!drm_handle_vblank(dev, pipe))
3152                 return false;
3153
3154         if ((iir & flip_pending) == 0)
3155                 return false;
3156
3157         intel_prepare_page_flip(dev, plane);
3158
3159         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3160          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3161          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3162          * the flip is completed (no longer pending). Since this doesn't raise
3163          * an interrupt per se, we watch for the change at vblank.
3164          */
3165         if (I915_READ16(ISR) & flip_pending)
3166                 return false;
3167
3168         intel_finish_page_flip(dev, pipe);
3169
3170         return true;
3171 }
3172
3173 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3174 {
3175         struct drm_device *dev = (struct drm_device *) arg;
3176         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3177         u16 iir, new_iir;
3178         u32 pipe_stats[2];
3179         unsigned long irqflags;
3180         int pipe;
3181         u16 flip_mask =
3182                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3183                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3184
3185         atomic_inc(&dev_priv->irq_received);
3186
3187         iir = I915_READ16(IIR);
3188         if (iir == 0)
3189                 return IRQ_NONE;
3190
3191         while (iir & ~flip_mask) {
3192                 /* Can't rely on pipestat interrupt bit in iir as it might
3193                  * have been cleared after the pipestat interrupt was received.
3194                  * It doesn't set the bit in iir again, but it still produces
3195                  * interrupts (for non-MSI).
3196                  */
3197                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3198                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3199                         i915_handle_error(dev, false);
3200
3201                 for_each_pipe(pipe) {
3202                         int reg = PIPESTAT(pipe);
3203                         pipe_stats[pipe] = I915_READ(reg);
3204
3205                         /*
3206                          * Clear the PIPE*STAT regs before the IIR
3207                          */
3208                         if (pipe_stats[pipe] & 0x8000ffff) {
3209                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3210                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3211                                                          pipe_name(pipe));
3212                                 I915_WRITE(reg, pipe_stats[pipe]);
3213                         }
3214                 }
3215                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3216
3217                 I915_WRITE16(IIR, iir & ~flip_mask);
3218                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3219
3220                 i915_update_dri1_breadcrumb(dev);
3221
3222                 if (iir & I915_USER_INTERRUPT)
3223                         notify_ring(dev, &dev_priv->ring[RCS]);
3224
3225                 for_each_pipe(pipe) {
3226                         int plane = pipe;
3227                         if (HAS_FBC(dev))
3228                                 plane = !plane;
3229
3230                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3231                             i8xx_handle_vblank(dev, plane, pipe, iir))
3232                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3233
3234                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3235                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3236                 }
3237
3238                 iir = new_iir;
3239         }
3240
3241         return IRQ_HANDLED;
3242 }
3243
3244 static void i8xx_irq_uninstall(struct drm_device * dev)
3245 {
3246         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3247         int pipe;
3248
3249         for_each_pipe(pipe) {
3250                 /* Clear enable bits; then clear status bits */
3251                 I915_WRITE(PIPESTAT(pipe), 0);
3252                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3253         }
3254         I915_WRITE16(IMR, 0xffff);
3255         I915_WRITE16(IER, 0x0);
3256         I915_WRITE16(IIR, I915_READ16(IIR));
3257 }
3258
3259 static void i915_irq_preinstall(struct drm_device * dev)
3260 {
3261         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3262         int pipe;
3263
3264         atomic_set(&dev_priv->irq_received, 0);
3265
3266         if (I915_HAS_HOTPLUG(dev)) {
3267                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3268                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3269         }
3270
3271         I915_WRITE16(HWSTAM, 0xeffe);
3272         for_each_pipe(pipe)
3273                 I915_WRITE(PIPESTAT(pipe), 0);
3274         I915_WRITE(IMR, 0xffffffff);
3275         I915_WRITE(IER, 0x0);
3276         POSTING_READ(IER);
3277 }
3278
3279 static int i915_irq_postinstall(struct drm_device *dev)
3280 {
3281         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3282         u32 enable_mask;
3283         unsigned long irqflags;
3284
3285         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3286
3287         /* Unmask the interrupts that we always want on. */
3288         dev_priv->irq_mask =
3289                 ~(I915_ASLE_INTERRUPT |
3290                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3291                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3292                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3293                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3294                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3295
3296         enable_mask =
3297                 I915_ASLE_INTERRUPT |
3298                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3299                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3300                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3301                 I915_USER_INTERRUPT;
3302
3303         if (I915_HAS_HOTPLUG(dev)) {
3304                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3305                 POSTING_READ(PORT_HOTPLUG_EN);
3306
3307                 /* Enable in IER... */
3308                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3309                 /* and unmask in IMR */
3310                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3311         }
3312
3313         I915_WRITE(IMR, dev_priv->irq_mask);
3314         I915_WRITE(IER, enable_mask);
3315         POSTING_READ(IER);
3316
3317         i915_enable_asle_pipestat(dev);
3318
3319         /* Interrupt setup is already guaranteed to be single-threaded, this is
3320          * just to make the assert_spin_locked check happy. */
3321         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3322         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3323         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3324         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3325
3326         return 0;
3327 }
3328
3329 /*
3330  * Returns true when a page flip has completed.
3331  */
3332 static bool i915_handle_vblank(struct drm_device *dev,
3333                                int plane, int pipe, u32 iir)
3334 {
3335         drm_i915_private_t *dev_priv = dev->dev_private;
3336         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3337
3338         if (!drm_handle_vblank(dev, pipe))
3339                 return false;
3340
3341         if ((iir & flip_pending) == 0)
3342                 return false;
3343
3344         intel_prepare_page_flip(dev, plane);
3345
3346         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3347          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3348          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3349          * the flip is completed (no longer pending). Since this doesn't raise
3350          * an interrupt per se, we watch for the change at vblank.
3351          */
3352         if (I915_READ(ISR) & flip_pending)
3353                 return false;
3354
3355         intel_finish_page_flip(dev, pipe);
3356
3357         return true;
3358 }
3359
3360 static irqreturn_t i915_irq_handler(int irq, void *arg)
3361 {
3362         struct drm_device *dev = (struct drm_device *) arg;
3363         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3364         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3365         unsigned long irqflags;
3366         u32 flip_mask =
3367                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3368                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3369         int pipe, ret = IRQ_NONE;
3370
3371         atomic_inc(&dev_priv->irq_received);
3372
3373         iir = I915_READ(IIR);
3374         do {
3375                 bool irq_received = (iir & ~flip_mask) != 0;
3376                 bool blc_event = false;
3377
3378                 /* Can't rely on pipestat interrupt bit in iir as it might
3379                  * have been cleared after the pipestat interrupt was received.
3380                  * It doesn't set the bit in iir again, but it still produces
3381                  * interrupts (for non-MSI).
3382                  */
3383                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3384                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3385                         i915_handle_error(dev, false);
3386
3387                 for_each_pipe(pipe) {
3388                         int reg = PIPESTAT(pipe);
3389                         pipe_stats[pipe] = I915_READ(reg);
3390
3391                         /* Clear the PIPE*STAT regs before the IIR */
3392                         if (pipe_stats[pipe] & 0x8000ffff) {
3393                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3394                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3395                                                          pipe_name(pipe));
3396                                 I915_WRITE(reg, pipe_stats[pipe]);
3397                                 irq_received = true;
3398                         }
3399                 }
3400                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3401
3402                 if (!irq_received)
3403                         break;
3404
3405                 /* Consume port.  Then clear IIR or we'll miss events */
3406                 if ((I915_HAS_HOTPLUG(dev)) &&
3407                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3408                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3409                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3410
3411                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3412                                   hotplug_status);
3413
3414                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3415
3416                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3417                         POSTING_READ(PORT_HOTPLUG_STAT);
3418                 }
3419
3420                 I915_WRITE(IIR, iir & ~flip_mask);
3421                 new_iir = I915_READ(IIR); /* Flush posted writes */
3422
3423                 if (iir & I915_USER_INTERRUPT)
3424                         notify_ring(dev, &dev_priv->ring[RCS]);
3425
3426                 for_each_pipe(pipe) {
3427                         int plane = pipe;
3428                         if (HAS_FBC(dev))
3429                                 plane = !plane;
3430
3431                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3432                             i915_handle_vblank(dev, plane, pipe, iir))
3433                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3434
3435                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3436                                 blc_event = true;
3437
3438                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3439                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3440                 }
3441
3442                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3443                         intel_opregion_asle_intr(dev);
3444
3445                 /* With MSI, interrupts are only generated when iir
3446                  * transitions from zero to nonzero.  If another bit got
3447                  * set while we were handling the existing iir bits, then
3448                  * we would never get another interrupt.
3449                  *
3450                  * This is fine on non-MSI as well, as if we hit this path
3451                  * we avoid exiting the interrupt handler only to generate
3452                  * another one.
3453                  *
3454                  * Note that for MSI this could cause a stray interrupt report
3455                  * if an interrupt landed in the time between writing IIR and
3456                  * the posting read.  This should be rare enough to never
3457                  * trigger the 99% of 100,000 interrupts test for disabling
3458                  * stray interrupts.
3459                  */
3460                 ret = IRQ_HANDLED;
3461                 iir = new_iir;
3462         } while (iir & ~flip_mask);
3463
3464         i915_update_dri1_breadcrumb(dev);
3465
3466         return ret;
3467 }
3468
3469 static void i915_irq_uninstall(struct drm_device * dev)
3470 {
3471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3472         int pipe;
3473
3474         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3475
3476         if (I915_HAS_HOTPLUG(dev)) {
3477                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3478                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3479         }
3480
3481         I915_WRITE16(HWSTAM, 0xffff);
3482         for_each_pipe(pipe) {
3483                 /* Clear enable bits; then clear status bits */
3484                 I915_WRITE(PIPESTAT(pipe), 0);
3485                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3486         }
3487         I915_WRITE(IMR, 0xffffffff);
3488         I915_WRITE(IER, 0x0);
3489
3490         I915_WRITE(IIR, I915_READ(IIR));
3491 }
3492
3493 static void i965_irq_preinstall(struct drm_device * dev)
3494 {
3495         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3496         int pipe;
3497
3498         atomic_set(&dev_priv->irq_received, 0);
3499
3500         I915_WRITE(PORT_HOTPLUG_EN, 0);
3501         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3502
3503         I915_WRITE(HWSTAM, 0xeffe);
3504         for_each_pipe(pipe)
3505                 I915_WRITE(PIPESTAT(pipe), 0);
3506         I915_WRITE(IMR, 0xffffffff);
3507         I915_WRITE(IER, 0x0);
3508         POSTING_READ(IER);
3509 }
3510
3511 static int i965_irq_postinstall(struct drm_device *dev)
3512 {
3513         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3514         u32 enable_mask;
3515         u32 error_mask;
3516         unsigned long irqflags;
3517
3518         /* Unmask the interrupts that we always want on. */
3519         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3520                                I915_DISPLAY_PORT_INTERRUPT |
3521                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3522                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3523                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3524                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3525                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3526
3527         enable_mask = ~dev_priv->irq_mask;
3528         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3529                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3530         enable_mask |= I915_USER_INTERRUPT;
3531
3532         if (IS_G4X(dev))
3533                 enable_mask |= I915_BSD_USER_INTERRUPT;
3534
3535         /* Interrupt setup is already guaranteed to be single-threaded, this is
3536          * just to make the assert_spin_locked check happy. */
3537         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3538         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3539         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3540         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3541         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3542
3543         /*
3544          * Enable some error detection, note the instruction error mask
3545          * bit is reserved, so we leave it masked.
3546          */
3547         if (IS_G4X(dev)) {
3548                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3549                                GM45_ERROR_MEM_PRIV |
3550                                GM45_ERROR_CP_PRIV |
3551                                I915_ERROR_MEMORY_REFRESH);
3552         } else {
3553                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3554                                I915_ERROR_MEMORY_REFRESH);
3555         }
3556         I915_WRITE(EMR, error_mask);
3557
3558         I915_WRITE(IMR, dev_priv->irq_mask);
3559         I915_WRITE(IER, enable_mask);
3560         POSTING_READ(IER);
3561
3562         I915_WRITE(PORT_HOTPLUG_EN, 0);
3563         POSTING_READ(PORT_HOTPLUG_EN);
3564
3565         i915_enable_asle_pipestat(dev);
3566
3567         return 0;
3568 }
3569
3570 static void i915_hpd_irq_setup(struct drm_device *dev)
3571 {
3572         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3573         struct drm_mode_config *mode_config = &dev->mode_config;
3574         struct intel_encoder *intel_encoder;
3575         u32 hotplug_en;
3576
3577         assert_spin_locked(&dev_priv->irq_lock);
3578
3579         if (I915_HAS_HOTPLUG(dev)) {
3580                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3581                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3582                 /* Note HDMI and DP share hotplug bits */
3583                 /* enable bits are the same for all generations */
3584                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3585                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3586                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3587                 /* Programming the CRT detection parameters tends
3588                    to generate a spurious hotplug event about three
3589                    seconds later.  So just do it once.
3590                 */
3591                 if (IS_G4X(dev))
3592                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3593                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3594                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3595
3596                 /* Ignore TV since it's buggy */
3597                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3598         }
3599 }
3600
3601 static irqreturn_t i965_irq_handler(int irq, void *arg)
3602 {
3603         struct drm_device *dev = (struct drm_device *) arg;
3604         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3605         u32 iir, new_iir;
3606         u32 pipe_stats[I915_MAX_PIPES];
3607         unsigned long irqflags;
3608         int irq_received;
3609         int ret = IRQ_NONE, pipe;
3610         u32 flip_mask =
3611                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3612                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3613
3614         atomic_inc(&dev_priv->irq_received);
3615
3616         iir = I915_READ(IIR);
3617
3618         for (;;) {
3619                 bool blc_event = false;
3620
3621                 irq_received = (iir & ~flip_mask) != 0;
3622
3623                 /* Can't rely on pipestat interrupt bit in iir as it might
3624                  * have been cleared after the pipestat interrupt was received.
3625                  * It doesn't set the bit in iir again, but it still produces
3626                  * interrupts (for non-MSI).
3627                  */
3628                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3629                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3630                         i915_handle_error(dev, false);
3631
3632                 for_each_pipe(pipe) {
3633                         int reg = PIPESTAT(pipe);
3634                         pipe_stats[pipe] = I915_READ(reg);
3635
3636                         /*
3637                          * Clear the PIPE*STAT regs before the IIR
3638                          */
3639                         if (pipe_stats[pipe] & 0x8000ffff) {
3640                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3641                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3642                                                          pipe_name(pipe));
3643                                 I915_WRITE(reg, pipe_stats[pipe]);
3644                                 irq_received = 1;
3645                         }
3646                 }
3647                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3648
3649                 if (!irq_received)
3650                         break;
3651
3652                 ret = IRQ_HANDLED;
3653
3654                 /* Consume port.  Then clear IIR or we'll miss events */
3655                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3656                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3657                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3658                                                                   HOTPLUG_INT_STATUS_G4X :
3659                                                                   HOTPLUG_INT_STATUS_I915);
3660
3661                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3662                                   hotplug_status);
3663
3664                         intel_hpd_irq_handler(dev, hotplug_trigger,
3665                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3666
3667                         if (IS_G4X(dev) &&
3668                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3669                                 dp_aux_irq_handler(dev);
3670
3671                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3672                         I915_READ(PORT_HOTPLUG_STAT);
3673                 }
3674
3675                 I915_WRITE(IIR, iir & ~flip_mask);
3676                 new_iir = I915_READ(IIR); /* Flush posted writes */
3677
3678                 if (iir & I915_USER_INTERRUPT)
3679                         notify_ring(dev, &dev_priv->ring[RCS]);
3680                 if (iir & I915_BSD_USER_INTERRUPT)
3681                         notify_ring(dev, &dev_priv->ring[VCS]);
3682
3683                 for_each_pipe(pipe) {
3684                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3685                             i915_handle_vblank(dev, pipe, pipe, iir))
3686                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3687
3688                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3689                                 blc_event = true;
3690
3691                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3692                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3693                 }
3694
3695
3696                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3697                         intel_opregion_asle_intr(dev);
3698
3699                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3700                         gmbus_irq_handler(dev);
3701
3702                 /* With MSI, interrupts are only generated when iir
3703                  * transitions from zero to nonzero.  If another bit got
3704                  * set while we were handling the existing iir bits, then
3705                  * we would never get another interrupt.
3706                  *
3707                  * This is fine on non-MSI as well, as if we hit this path
3708                  * we avoid exiting the interrupt handler only to generate
3709                  * another one.
3710                  *
3711                  * Note that for MSI this could cause a stray interrupt report
3712                  * if an interrupt landed in the time between writing IIR and
3713                  * the posting read.  This should be rare enough to never
3714                  * trigger the 99% of 100,000 interrupts test for disabling
3715                  * stray interrupts.
3716                  */
3717                 iir = new_iir;
3718         }
3719
3720         i915_update_dri1_breadcrumb(dev);
3721
3722         return ret;
3723 }
3724
3725 static void i965_irq_uninstall(struct drm_device * dev)
3726 {
3727         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3728         int pipe;
3729
3730         if (!dev_priv)
3731                 return;
3732
3733         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3734
3735         I915_WRITE(PORT_HOTPLUG_EN, 0);
3736         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3737
3738         I915_WRITE(HWSTAM, 0xffffffff);
3739         for_each_pipe(pipe)
3740                 I915_WRITE(PIPESTAT(pipe), 0);
3741         I915_WRITE(IMR, 0xffffffff);
3742         I915_WRITE(IER, 0x0);
3743
3744         for_each_pipe(pipe)
3745                 I915_WRITE(PIPESTAT(pipe),
3746                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3747         I915_WRITE(IIR, I915_READ(IIR));
3748 }
3749
3750 static void i915_reenable_hotplug_timer_func(unsigned long data)
3751 {
3752         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3753         struct drm_device *dev = dev_priv->dev;
3754         struct drm_mode_config *mode_config = &dev->mode_config;
3755         unsigned long irqflags;
3756         int i;
3757
3758         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3759         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3760                 struct drm_connector *connector;
3761
3762                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3763                         continue;
3764
3765                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3766
3767                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3768                         struct intel_connector *intel_connector = to_intel_connector(connector);
3769
3770                         if (intel_connector->encoder->hpd_pin == i) {
3771                                 if (connector->polled != intel_connector->polled)
3772                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3773                                                          drm_get_connector_name(connector));
3774                                 connector->polled = intel_connector->polled;
3775                                 if (!connector->polled)
3776                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3777                         }
3778                 }
3779         }
3780         if (dev_priv->display.hpd_irq_setup)
3781                 dev_priv->display.hpd_irq_setup(dev);
3782         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3783 }
3784
3785 void intel_irq_init(struct drm_device *dev)
3786 {
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788
3789         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3790         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3791         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3792         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3793
3794         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3795                     i915_hangcheck_elapsed,
3796                     (unsigned long) dev);
3797         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3798                     (unsigned long) dev_priv);
3799
3800         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3801
3802         if (IS_GEN2(dev)) {
3803                 dev->max_vblank_count = 0;
3804                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3805         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3806                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3807                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3808         } else {
3809                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3810                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3811         }
3812
3813         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3814                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3815                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3816         }
3817
3818         if (IS_VALLEYVIEW(dev)) {
3819                 dev->driver->irq_handler = valleyview_irq_handler;
3820                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3821                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3822                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3823                 dev->driver->enable_vblank = valleyview_enable_vblank;
3824                 dev->driver->disable_vblank = valleyview_disable_vblank;
3825                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3826         } else if (IS_GEN8(dev)) {
3827                 dev->driver->irq_handler = gen8_irq_handler;
3828                 dev->driver->irq_preinstall = gen8_irq_preinstall;
3829                 dev->driver->irq_postinstall = gen8_irq_postinstall;
3830                 dev->driver->irq_uninstall = gen8_irq_uninstall;
3831                 dev->driver->enable_vblank = gen8_enable_vblank;
3832                 dev->driver->disable_vblank = gen8_disable_vblank;
3833                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3834         } else if (HAS_PCH_SPLIT(dev)) {
3835                 dev->driver->irq_handler = ironlake_irq_handler;
3836                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3837                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3838                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3839                 dev->driver->enable_vblank = ironlake_enable_vblank;
3840                 dev->driver->disable_vblank = ironlake_disable_vblank;
3841                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3842         } else {
3843                 if (INTEL_INFO(dev)->gen == 2) {
3844                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3845                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3846                         dev->driver->irq_handler = i8xx_irq_handler;
3847                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3848                 } else if (INTEL_INFO(dev)->gen == 3) {
3849                         dev->driver->irq_preinstall = i915_irq_preinstall;
3850                         dev->driver->irq_postinstall = i915_irq_postinstall;
3851                         dev->driver->irq_uninstall = i915_irq_uninstall;
3852                         dev->driver->irq_handler = i915_irq_handler;
3853                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3854                 } else {
3855                         dev->driver->irq_preinstall = i965_irq_preinstall;
3856                         dev->driver->irq_postinstall = i965_irq_postinstall;
3857                         dev->driver->irq_uninstall = i965_irq_uninstall;
3858                         dev->driver->irq_handler = i965_irq_handler;
3859                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3860                 }
3861                 dev->driver->enable_vblank = i915_enable_vblank;
3862                 dev->driver->disable_vblank = i915_disable_vblank;
3863         }
3864 }
3865
3866 void intel_hpd_init(struct drm_device *dev)
3867 {
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869         struct drm_mode_config *mode_config = &dev->mode_config;
3870         struct drm_connector *connector;
3871         unsigned long irqflags;
3872         int i;
3873
3874         for (i = 1; i < HPD_NUM_PINS; i++) {
3875                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3876                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3877         }
3878         list_for_each_entry(connector, &mode_config->connector_list, head) {
3879                 struct intel_connector *intel_connector = to_intel_connector(connector);
3880                 connector->polled = intel_connector->polled;
3881                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3882                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3883         }
3884
3885         /* Interrupt setup is already guaranteed to be single-threaded, this is
3886          * just to make the assert_spin_locked checks happy. */
3887         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3888         if (dev_priv->display.hpd_irq_setup)
3889                 dev_priv->display.hpd_irq_setup(dev);
3890         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3891 }
3892
3893 /* Disable interrupts so we can allow Package C8+. */
3894 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3895 {
3896         struct drm_i915_private *dev_priv = dev->dev_private;
3897         unsigned long irqflags;
3898
3899         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3900
3901         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3902         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3903         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3904         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3905         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3906
3907         ironlake_disable_display_irq(dev_priv, 0xffffffff);
3908         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3909         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3910         snb_disable_pm_irq(dev_priv, 0xffffffff);
3911
3912         dev_priv->pc8.irqs_disabled = true;
3913
3914         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3915 }
3916
3917 /* Restore interrupts so we can recover from Package C8+. */
3918 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3919 {
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         unsigned long irqflags;
3922         uint32_t val;
3923
3924         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3925
3926         val = I915_READ(DEIMR);
3927         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3928
3929         val = I915_READ(SDEIMR);
3930         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3931
3932         val = I915_READ(GTIMR);
3933         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3934
3935         val = I915_READ(GEN6_PMIMR);
3936         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3937
3938         dev_priv->pc8.irqs_disabled = false;
3939
3940         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3941         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3942         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3943         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3944         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3945
3946         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3947 }